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TARGET_SAKURAIO_EVB_01/core_cm0plus.h@159:7130f322cb7e, 2017-12-21 (annotated)

Committer:
mbed_official
Date:
Thu Dec 21 18:20:02 2017 +0000
Revision:
159:7130f322cb7e
mbed library version 157

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 159:7130f322cb7e 1 /**************************************************************************//**
mbed_official 159:7130f322cb7e 2 * @file core_cm0plus.h
mbed_official 159:7130f322cb7e 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
mbed_official 159:7130f322cb7e 4 * @version V5.0.2
mbed_official 159:7130f322cb7e 5 * @date 13. February 2017
mbed_official 159:7130f322cb7e 6 ******************************************************************************/
mbed_official 159:7130f322cb7e 7 /*
mbed_official 159:7130f322cb7e 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
mbed_official 159:7130f322cb7e 9 *
mbed_official 159:7130f322cb7e 10 * SPDX-License-Identifier: Apache-2.0
mbed_official 159:7130f322cb7e 11 *
mbed_official 159:7130f322cb7e 12 * Licensed under the Apache License, Version 2.0 (the License); you may
mbed_official 159:7130f322cb7e 13 * not use this file except in compliance with the License.
mbed_official 159:7130f322cb7e 14 * You may obtain a copy of the License at
mbed_official 159:7130f322cb7e 15 *
mbed_official 159:7130f322cb7e 16 * www.apache.org/licenses/LICENSE-2.0
mbed_official 159:7130f322cb7e 17 *
mbed_official 159:7130f322cb7e 18 * Unless required by applicable law or agreed to in writing, software
mbed_official 159:7130f322cb7e 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
mbed_official 159:7130f322cb7e 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 159:7130f322cb7e 21 * See the License for the specific language governing permissions and
mbed_official 159:7130f322cb7e 22 * limitations under the License.
mbed_official 159:7130f322cb7e 23 */
mbed_official 159:7130f322cb7e 24
mbed_official 159:7130f322cb7e 25 #if defined ( __ICCARM__ )
mbed_official 159:7130f322cb7e 26 #pragma system_include /* treat file as system include file for MISRA check */
mbed_official 159:7130f322cb7e 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official 159:7130f322cb7e 28 #pragma clang system_header /* treat file as system include file */
mbed_official 159:7130f322cb7e 29 #endif
mbed_official 159:7130f322cb7e 30
mbed_official 159:7130f322cb7e 31 #ifndef __CORE_CM0PLUS_H_GENERIC
mbed_official 159:7130f322cb7e 32 #define __CORE_CM0PLUS_H_GENERIC
mbed_official 159:7130f322cb7e 33
mbed_official 159:7130f322cb7e 34 #include <stdint.h>
mbed_official 159:7130f322cb7e 35
mbed_official 159:7130f322cb7e 36 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 37 extern "C" {
mbed_official 159:7130f322cb7e 38 #endif
mbed_official 159:7130f322cb7e 39
mbed_official 159:7130f322cb7e 40 /**
mbed_official 159:7130f322cb7e 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official 159:7130f322cb7e 42 CMSIS violates the following MISRA-C:2004 rules:
mbed_official 159:7130f322cb7e 43
mbed_official 159:7130f322cb7e 44 \li Required Rule 8.5, object/function definition in header file.<br>
mbed_official 159:7130f322cb7e 45 Function definitions in header files are used to allow 'inlining'.
mbed_official 159:7130f322cb7e 46
mbed_official 159:7130f322cb7e 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official 159:7130f322cb7e 48 Unions are used for effective representation of core registers.
mbed_official 159:7130f322cb7e 49
mbed_official 159:7130f322cb7e 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official 159:7130f322cb7e 51 Function-like macros are used to allow more efficient code.
mbed_official 159:7130f322cb7e 52 */
mbed_official 159:7130f322cb7e 53
mbed_official 159:7130f322cb7e 54
mbed_official 159:7130f322cb7e 55 /*******************************************************************************
mbed_official 159:7130f322cb7e 56 * CMSIS definitions
mbed_official 159:7130f322cb7e 57 ******************************************************************************/
mbed_official 159:7130f322cb7e 58 /**
mbed_official 159:7130f322cb7e 59 \ingroup Cortex-M0+
mbed_official 159:7130f322cb7e 60 @{
mbed_official 159:7130f322cb7e 61 */
mbed_official 159:7130f322cb7e 62
mbed_official 159:7130f322cb7e 63 /* CMSIS CM0+ definitions */
mbed_official 159:7130f322cb7e 64 #define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
mbed_official 159:7130f322cb7e 65 #define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
mbed_official 159:7130f322cb7e 66 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
mbed_official 159:7130f322cb7e 67 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbed_official 159:7130f322cb7e 68
mbed_official 159:7130f322cb7e 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
mbed_official 159:7130f322cb7e 70
mbed_official 159:7130f322cb7e 71 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 159:7130f322cb7e 72 This core does not support an FPU at all
mbed_official 159:7130f322cb7e 73 */
mbed_official 159:7130f322cb7e 74 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 75
mbed_official 159:7130f322cb7e 76 #if defined ( __CC_ARM )
mbed_official 159:7130f322cb7e 77 #if defined __TARGET_FPU_VFP
mbed_official 159:7130f322cb7e 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 79 #endif
mbed_official 159:7130f322cb7e 80
mbed_official 159:7130f322cb7e 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official 159:7130f322cb7e 82 #if defined __ARM_PCS_VFP
mbed_official 159:7130f322cb7e 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 84 #endif
mbed_official 159:7130f322cb7e 85
mbed_official 159:7130f322cb7e 86 #elif defined ( __GNUC__ )
mbed_official 159:7130f322cb7e 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 159:7130f322cb7e 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 89 #endif
mbed_official 159:7130f322cb7e 90
mbed_official 159:7130f322cb7e 91 #elif defined ( __ICCARM__ )
mbed_official 159:7130f322cb7e 92 #if defined __ARMVFP__
mbed_official 159:7130f322cb7e 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 94 #endif
mbed_official 159:7130f322cb7e 95
mbed_official 159:7130f322cb7e 96 #elif defined ( __TI_ARM__ )
mbed_official 159:7130f322cb7e 97 #if defined __TI_VFP_SUPPORT__
mbed_official 159:7130f322cb7e 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 99 #endif
mbed_official 159:7130f322cb7e 100
mbed_official 159:7130f322cb7e 101 #elif defined ( __TASKING__ )
mbed_official 159:7130f322cb7e 102 #if defined __FPU_VFP__
mbed_official 159:7130f322cb7e 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 104 #endif
mbed_official 159:7130f322cb7e 105
mbed_official 159:7130f322cb7e 106 #elif defined ( __CSMC__ )
mbed_official 159:7130f322cb7e 107 #if ( __CSMC__ & 0x400U)
mbed_official 159:7130f322cb7e 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 109 #endif
mbed_official 159:7130f322cb7e 110
mbed_official 159:7130f322cb7e 111 #endif
mbed_official 159:7130f322cb7e 112
mbed_official 159:7130f322cb7e 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
mbed_official 159:7130f322cb7e 114
mbed_official 159:7130f322cb7e 115
mbed_official 159:7130f322cb7e 116 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 117 }
mbed_official 159:7130f322cb7e 118 #endif
mbed_official 159:7130f322cb7e 119
mbed_official 159:7130f322cb7e 120 #endif /* __CORE_CM0PLUS_H_GENERIC */
mbed_official 159:7130f322cb7e 121
mbed_official 159:7130f322cb7e 122 #ifndef __CMSIS_GENERIC
mbed_official 159:7130f322cb7e 123
mbed_official 159:7130f322cb7e 124 #ifndef __CORE_CM0PLUS_H_DEPENDANT
mbed_official 159:7130f322cb7e 125 #define __CORE_CM0PLUS_H_DEPENDANT
mbed_official 159:7130f322cb7e 126
mbed_official 159:7130f322cb7e 127 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 128 extern "C" {
mbed_official 159:7130f322cb7e 129 #endif
mbed_official 159:7130f322cb7e 130
mbed_official 159:7130f322cb7e 131 /* check device defines and use defaults */
mbed_official 159:7130f322cb7e 132 #if defined __CHECK_DEVICE_DEFINES
mbed_official 159:7130f322cb7e 133 #ifndef __CM0PLUS_REV
mbed_official 159:7130f322cb7e 134 #define __CM0PLUS_REV 0x0000U
mbed_official 159:7130f322cb7e 135 #warning "__CM0PLUS_REV not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 136 #endif
mbed_official 159:7130f322cb7e 137
mbed_official 159:7130f322cb7e 138 #ifndef __MPU_PRESENT
mbed_official 159:7130f322cb7e 139 #define __MPU_PRESENT 0U
mbed_official 159:7130f322cb7e 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 141 #endif
mbed_official 159:7130f322cb7e 142
mbed_official 159:7130f322cb7e 143 #ifndef __VTOR_PRESENT
mbed_official 159:7130f322cb7e 144 #define __VTOR_PRESENT 0U
mbed_official 159:7130f322cb7e 145 #warning "__VTOR_PRESENT not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 146 #endif
mbed_official 159:7130f322cb7e 147
mbed_official 159:7130f322cb7e 148 #ifndef __NVIC_PRIO_BITS
mbed_official 159:7130f322cb7e 149 #define __NVIC_PRIO_BITS 2U
mbed_official 159:7130f322cb7e 150 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 151 #endif
mbed_official 159:7130f322cb7e 152
mbed_official 159:7130f322cb7e 153 #ifndef __Vendor_SysTickConfig
mbed_official 159:7130f322cb7e 154 #define __Vendor_SysTickConfig 0U
mbed_official 159:7130f322cb7e 155 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 156 #endif
mbed_official 159:7130f322cb7e 157 #endif
mbed_official 159:7130f322cb7e 158
mbed_official 159:7130f322cb7e 159 /* IO definitions (access restrictions to peripheral registers) */
mbed_official 159:7130f322cb7e 160 /**
mbed_official 159:7130f322cb7e 161 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official 159:7130f322cb7e 162
mbed_official 159:7130f322cb7e 163 <strong>IO Type Qualifiers</strong> are used
mbed_official 159:7130f322cb7e 164 \li to specify the access to peripheral variables.
mbed_official 159:7130f322cb7e 165 \li for automatic generation of peripheral register debug information.
mbed_official 159:7130f322cb7e 166 */
mbed_official 159:7130f322cb7e 167 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 168 #define __I volatile /*!< Defines 'read only' permissions */
mbed_official 159:7130f322cb7e 169 #else
mbed_official 159:7130f322cb7e 170 #define __I volatile const /*!< Defines 'read only' permissions */
mbed_official 159:7130f322cb7e 171 #endif
mbed_official 159:7130f322cb7e 172 #define __O volatile /*!< Defines 'write only' permissions */
mbed_official 159:7130f322cb7e 173 #define __IO volatile /*!< Defines 'read / write' permissions */
mbed_official 159:7130f322cb7e 174
mbed_official 159:7130f322cb7e 175 /* following defines should be used for structure members */
mbed_official 159:7130f322cb7e 176 #define __IM volatile const /*! Defines 'read only' structure member permissions */
mbed_official 159:7130f322cb7e 177 #define __OM volatile /*! Defines 'write only' structure member permissions */
mbed_official 159:7130f322cb7e 178 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
mbed_official 159:7130f322cb7e 179
mbed_official 159:7130f322cb7e 180 /*@} end of group Cortex-M0+ */
mbed_official 159:7130f322cb7e 181
mbed_official 159:7130f322cb7e 182
mbed_official 159:7130f322cb7e 183
mbed_official 159:7130f322cb7e 184 /*******************************************************************************
mbed_official 159:7130f322cb7e 185 * Register Abstraction
mbed_official 159:7130f322cb7e 186 Core Register contain:
mbed_official 159:7130f322cb7e 187 - Core Register
mbed_official 159:7130f322cb7e 188 - Core NVIC Register
mbed_official 159:7130f322cb7e 189 - Core SCB Register
mbed_official 159:7130f322cb7e 190 - Core SysTick Register
mbed_official 159:7130f322cb7e 191 - Core MPU Register
mbed_official 159:7130f322cb7e 192 ******************************************************************************/
mbed_official 159:7130f322cb7e 193 /**
mbed_official 159:7130f322cb7e 194 \defgroup CMSIS_core_register Defines and Type Definitions
mbed_official 159:7130f322cb7e 195 \brief Type definitions and defines for Cortex-M processor based devices.
mbed_official 159:7130f322cb7e 196 */
mbed_official 159:7130f322cb7e 197
mbed_official 159:7130f322cb7e 198 /**
mbed_official 159:7130f322cb7e 199 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 200 \defgroup CMSIS_CORE Status and Control Registers
mbed_official 159:7130f322cb7e 201 \brief Core Register type definitions.
mbed_official 159:7130f322cb7e 202 @{
mbed_official 159:7130f322cb7e 203 */
mbed_official 159:7130f322cb7e 204
mbed_official 159:7130f322cb7e 205 /**
mbed_official 159:7130f322cb7e 206 \brief Union type to access the Application Program Status Register (APSR).
mbed_official 159:7130f322cb7e 207 */
mbed_official 159:7130f322cb7e 208 typedef union
mbed_official 159:7130f322cb7e 209 {
mbed_official 159:7130f322cb7e 210 struct
mbed_official 159:7130f322cb7e 211 {
mbed_official 159:7130f322cb7e 212 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
mbed_official 159:7130f322cb7e 213 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 159:7130f322cb7e 214 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 159:7130f322cb7e 215 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 159:7130f322cb7e 216 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 159:7130f322cb7e 217 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 218 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 219 } APSR_Type;
mbed_official 159:7130f322cb7e 220
mbed_official 159:7130f322cb7e 221 /* APSR Register Definitions */
mbed_official 159:7130f322cb7e 222 #define APSR_N_Pos 31U /*!< APSR: N Position */
mbed_official 159:7130f322cb7e 223 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 159:7130f322cb7e 224
mbed_official 159:7130f322cb7e 225 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
mbed_official 159:7130f322cb7e 226 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 159:7130f322cb7e 227
mbed_official 159:7130f322cb7e 228 #define APSR_C_Pos 29U /*!< APSR: C Position */
mbed_official 159:7130f322cb7e 229 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 159:7130f322cb7e 230
mbed_official 159:7130f322cb7e 231 #define APSR_V_Pos 28U /*!< APSR: V Position */
mbed_official 159:7130f322cb7e 232 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 159:7130f322cb7e 233
mbed_official 159:7130f322cb7e 234
mbed_official 159:7130f322cb7e 235 /**
mbed_official 159:7130f322cb7e 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official 159:7130f322cb7e 237 */
mbed_official 159:7130f322cb7e 238 typedef union
mbed_official 159:7130f322cb7e 239 {
mbed_official 159:7130f322cb7e 240 struct
mbed_official 159:7130f322cb7e 241 {
mbed_official 159:7130f322cb7e 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 159:7130f322cb7e 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbed_official 159:7130f322cb7e 244 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 245 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 246 } IPSR_Type;
mbed_official 159:7130f322cb7e 247
mbed_official 159:7130f322cb7e 248 /* IPSR Register Definitions */
mbed_official 159:7130f322cb7e 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
mbed_official 159:7130f322cb7e 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 159:7130f322cb7e 251
mbed_official 159:7130f322cb7e 252
mbed_official 159:7130f322cb7e 253 /**
mbed_official 159:7130f322cb7e 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official 159:7130f322cb7e 255 */
mbed_official 159:7130f322cb7e 256 typedef union
mbed_official 159:7130f322cb7e 257 {
mbed_official 159:7130f322cb7e 258 struct
mbed_official 159:7130f322cb7e 259 {
mbed_official 159:7130f322cb7e 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 159:7130f322cb7e 261 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mbed_official 159:7130f322cb7e 262 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbed_official 159:7130f322cb7e 263 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
mbed_official 159:7130f322cb7e 264 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 159:7130f322cb7e 265 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 159:7130f322cb7e 266 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 159:7130f322cb7e 267 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 159:7130f322cb7e 268 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 269 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 270 } xPSR_Type;
mbed_official 159:7130f322cb7e 271
mbed_official 159:7130f322cb7e 272 /* xPSR Register Definitions */
mbed_official 159:7130f322cb7e 273 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
mbed_official 159:7130f322cb7e 274 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 159:7130f322cb7e 275
mbed_official 159:7130f322cb7e 276 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
mbed_official 159:7130f322cb7e 277 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 159:7130f322cb7e 278
mbed_official 159:7130f322cb7e 279 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
mbed_official 159:7130f322cb7e 280 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 159:7130f322cb7e 281
mbed_official 159:7130f322cb7e 282 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
mbed_official 159:7130f322cb7e 283 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 159:7130f322cb7e 284
mbed_official 159:7130f322cb7e 285 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
mbed_official 159:7130f322cb7e 286 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 159:7130f322cb7e 287
mbed_official 159:7130f322cb7e 288 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
mbed_official 159:7130f322cb7e 289 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 159:7130f322cb7e 290
mbed_official 159:7130f322cb7e 291
mbed_official 159:7130f322cb7e 292 /**
mbed_official 159:7130f322cb7e 293 \brief Union type to access the Control Registers (CONTROL).
mbed_official 159:7130f322cb7e 294 */
mbed_official 159:7130f322cb7e 295 typedef union
mbed_official 159:7130f322cb7e 296 {
mbed_official 159:7130f322cb7e 297 struct
mbed_official 159:7130f322cb7e 298 {
mbed_official 159:7130f322cb7e 299 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mbed_official 159:7130f322cb7e 300 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbed_official 159:7130f322cb7e 301 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
mbed_official 159:7130f322cb7e 302 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 303 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 304 } CONTROL_Type;
mbed_official 159:7130f322cb7e 305
mbed_official 159:7130f322cb7e 306 /* CONTROL Register Definitions */
mbed_official 159:7130f322cb7e 307 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
mbed_official 159:7130f322cb7e 308 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 159:7130f322cb7e 309
mbed_official 159:7130f322cb7e 310 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
mbed_official 159:7130f322cb7e 311 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
mbed_official 159:7130f322cb7e 312
mbed_official 159:7130f322cb7e 313 /*@} end of group CMSIS_CORE */
mbed_official 159:7130f322cb7e 314
mbed_official 159:7130f322cb7e 315
mbed_official 159:7130f322cb7e 316 /**
mbed_official 159:7130f322cb7e 317 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 318 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official 159:7130f322cb7e 319 \brief Type definitions for the NVIC Registers
mbed_official 159:7130f322cb7e 320 @{
mbed_official 159:7130f322cb7e 321 */
mbed_official 159:7130f322cb7e 322
mbed_official 159:7130f322cb7e 323 /**
mbed_official 159:7130f322cb7e 324 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official 159:7130f322cb7e 325 */
mbed_official 159:7130f322cb7e 326 typedef struct
mbed_official 159:7130f322cb7e 327 {
mbed_official 159:7130f322cb7e 328 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbed_official 159:7130f322cb7e 329 uint32_t RESERVED0[31U];
mbed_official 159:7130f322cb7e 330 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbed_official 159:7130f322cb7e 331 uint32_t RSERVED1[31U];
mbed_official 159:7130f322cb7e 332 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbed_official 159:7130f322cb7e 333 uint32_t RESERVED2[31U];
mbed_official 159:7130f322cb7e 334 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbed_official 159:7130f322cb7e 335 uint32_t RESERVED3[31U];
mbed_official 159:7130f322cb7e 336 uint32_t RESERVED4[64U];
mbed_official 159:7130f322cb7e 337 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mbed_official 159:7130f322cb7e 338 } NVIC_Type;
mbed_official 159:7130f322cb7e 339
mbed_official 159:7130f322cb7e 340 /*@} end of group CMSIS_NVIC */
mbed_official 159:7130f322cb7e 341
mbed_official 159:7130f322cb7e 342
mbed_official 159:7130f322cb7e 343 /**
mbed_official 159:7130f322cb7e 344 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 345 \defgroup CMSIS_SCB System Control Block (SCB)
mbed_official 159:7130f322cb7e 346 \brief Type definitions for the System Control Block Registers
mbed_official 159:7130f322cb7e 347 @{
mbed_official 159:7130f322cb7e 348 */
mbed_official 159:7130f322cb7e 349
mbed_official 159:7130f322cb7e 350 /**
mbed_official 159:7130f322cb7e 351 \brief Structure type to access the System Control Block (SCB).
mbed_official 159:7130f322cb7e 352 */
mbed_official 159:7130f322cb7e 353 typedef struct
mbed_official 159:7130f322cb7e 354 {
mbed_official 159:7130f322cb7e 355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbed_official 159:7130f322cb7e 356 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbed_official 159:7130f322cb7e 357 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official 159:7130f322cb7e 358 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mbed_official 159:7130f322cb7e 359 #else
mbed_official 159:7130f322cb7e 360 uint32_t RESERVED0;
mbed_official 159:7130f322cb7e 361 #endif
mbed_official 159:7130f322cb7e 362 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbed_official 159:7130f322cb7e 363 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbed_official 159:7130f322cb7e 364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbed_official 159:7130f322cb7e 365 uint32_t RESERVED1;
mbed_official 159:7130f322cb7e 366 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mbed_official 159:7130f322cb7e 367 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbed_official 159:7130f322cb7e 368 } SCB_Type;
mbed_official 159:7130f322cb7e 369
mbed_official 159:7130f322cb7e 370 /* SCB CPUID Register Definitions */
mbed_official 159:7130f322cb7e 371 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
mbed_official 159:7130f322cb7e 372 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbed_official 159:7130f322cb7e 373
mbed_official 159:7130f322cb7e 374 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
mbed_official 159:7130f322cb7e 375 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbed_official 159:7130f322cb7e 376
mbed_official 159:7130f322cb7e 377 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
mbed_official 159:7130f322cb7e 378 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbed_official 159:7130f322cb7e 379
mbed_official 159:7130f322cb7e 380 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
mbed_official 159:7130f322cb7e 381 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbed_official 159:7130f322cb7e 382
mbed_official 159:7130f322cb7e 383 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
mbed_official 159:7130f322cb7e 384 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mbed_official 159:7130f322cb7e 385
mbed_official 159:7130f322cb7e 386 /* SCB Interrupt Control State Register Definitions */
mbed_official 159:7130f322cb7e 387 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
mbed_official 159:7130f322cb7e 388 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbed_official 159:7130f322cb7e 389
mbed_official 159:7130f322cb7e 390 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
mbed_official 159:7130f322cb7e 391 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbed_official 159:7130f322cb7e 392
mbed_official 159:7130f322cb7e 393 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
mbed_official 159:7130f322cb7e 394 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbed_official 159:7130f322cb7e 395
mbed_official 159:7130f322cb7e 396 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
mbed_official 159:7130f322cb7e 397 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbed_official 159:7130f322cb7e 398
mbed_official 159:7130f322cb7e 399 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
mbed_official 159:7130f322cb7e 400 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbed_official 159:7130f322cb7e 401
mbed_official 159:7130f322cb7e 402 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
mbed_official 159:7130f322cb7e 403 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbed_official 159:7130f322cb7e 404
mbed_official 159:7130f322cb7e 405 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
mbed_official 159:7130f322cb7e 406 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbed_official 159:7130f322cb7e 407
mbed_official 159:7130f322cb7e 408 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
mbed_official 159:7130f322cb7e 409 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbed_official 159:7130f322cb7e 410
mbed_official 159:7130f322cb7e 411 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 159:7130f322cb7e 412 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mbed_official 159:7130f322cb7e 413
mbed_official 159:7130f322cb7e 414 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official 159:7130f322cb7e 415 /* SCB Interrupt Control State Register Definitions */
mbed_official 159:7130f322cb7e 416 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
mbed_official 159:7130f322cb7e 417 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mbed_official 159:7130f322cb7e 418 #endif
mbed_official 159:7130f322cb7e 419
mbed_official 159:7130f322cb7e 420 /* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official 159:7130f322cb7e 421 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
mbed_official 159:7130f322cb7e 422 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbed_official 159:7130f322cb7e 423
mbed_official 159:7130f322cb7e 424 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
mbed_official 159:7130f322cb7e 425 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbed_official 159:7130f322cb7e 426
mbed_official 159:7130f322cb7e 427 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
mbed_official 159:7130f322cb7e 428 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbed_official 159:7130f322cb7e 429
mbed_official 159:7130f322cb7e 430 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
mbed_official 159:7130f322cb7e 431 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbed_official 159:7130f322cb7e 432
mbed_official 159:7130f322cb7e 433 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbed_official 159:7130f322cb7e 434 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbed_official 159:7130f322cb7e 435
mbed_official 159:7130f322cb7e 436 /* SCB System Control Register Definitions */
mbed_official 159:7130f322cb7e 437 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
mbed_official 159:7130f322cb7e 438 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbed_official 159:7130f322cb7e 439
mbed_official 159:7130f322cb7e 440 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
mbed_official 159:7130f322cb7e 441 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbed_official 159:7130f322cb7e 442
mbed_official 159:7130f322cb7e 443 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
mbed_official 159:7130f322cb7e 444 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbed_official 159:7130f322cb7e 445
mbed_official 159:7130f322cb7e 446 /* SCB Configuration Control Register Definitions */
mbed_official 159:7130f322cb7e 447 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
mbed_official 159:7130f322cb7e 448 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbed_official 159:7130f322cb7e 449
mbed_official 159:7130f322cb7e 450 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
mbed_official 159:7130f322cb7e 451 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbed_official 159:7130f322cb7e 452
mbed_official 159:7130f322cb7e 453 /* SCB System Handler Control and State Register Definitions */
mbed_official 159:7130f322cb7e 454 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
mbed_official 159:7130f322cb7e 455 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbed_official 159:7130f322cb7e 456
mbed_official 159:7130f322cb7e 457 /*@} end of group CMSIS_SCB */
mbed_official 159:7130f322cb7e 458
mbed_official 159:7130f322cb7e 459
mbed_official 159:7130f322cb7e 460 /**
mbed_official 159:7130f322cb7e 461 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 462 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official 159:7130f322cb7e 463 \brief Type definitions for the System Timer Registers.
mbed_official 159:7130f322cb7e 464 @{
mbed_official 159:7130f322cb7e 465 */
mbed_official 159:7130f322cb7e 466
mbed_official 159:7130f322cb7e 467 /**
mbed_official 159:7130f322cb7e 468 \brief Structure type to access the System Timer (SysTick).
mbed_official 159:7130f322cb7e 469 */
mbed_official 159:7130f322cb7e 470 typedef struct
mbed_official 159:7130f322cb7e 471 {
mbed_official 159:7130f322cb7e 472 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbed_official 159:7130f322cb7e 473 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbed_official 159:7130f322cb7e 474 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbed_official 159:7130f322cb7e 475 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbed_official 159:7130f322cb7e 476 } SysTick_Type;
mbed_official 159:7130f322cb7e 477
mbed_official 159:7130f322cb7e 478 /* SysTick Control / Status Register Definitions */
mbed_official 159:7130f322cb7e 479 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
mbed_official 159:7130f322cb7e 480 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbed_official 159:7130f322cb7e 481
mbed_official 159:7130f322cb7e 482 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
mbed_official 159:7130f322cb7e 483 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbed_official 159:7130f322cb7e 484
mbed_official 159:7130f322cb7e 485 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
mbed_official 159:7130f322cb7e 486 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbed_official 159:7130f322cb7e 487
mbed_official 159:7130f322cb7e 488 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
mbed_official 159:7130f322cb7e 489 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mbed_official 159:7130f322cb7e 490
mbed_official 159:7130f322cb7e 491 /* SysTick Reload Register Definitions */
mbed_official 159:7130f322cb7e 492 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
mbed_official 159:7130f322cb7e 493 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mbed_official 159:7130f322cb7e 494
mbed_official 159:7130f322cb7e 495 /* SysTick Current Register Definitions */
mbed_official 159:7130f322cb7e 496 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
mbed_official 159:7130f322cb7e 497 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mbed_official 159:7130f322cb7e 498
mbed_official 159:7130f322cb7e 499 /* SysTick Calibration Register Definitions */
mbed_official 159:7130f322cb7e 500 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
mbed_official 159:7130f322cb7e 501 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbed_official 159:7130f322cb7e 502
mbed_official 159:7130f322cb7e 503 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
mbed_official 159:7130f322cb7e 504 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbed_official 159:7130f322cb7e 505
mbed_official 159:7130f322cb7e 506 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
mbed_official 159:7130f322cb7e 507 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mbed_official 159:7130f322cb7e 508
mbed_official 159:7130f322cb7e 509 /*@} end of group CMSIS_SysTick */
mbed_official 159:7130f322cb7e 510
mbed_official 159:7130f322cb7e 511 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 512 /**
mbed_official 159:7130f322cb7e 513 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 514 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbed_official 159:7130f322cb7e 515 \brief Type definitions for the Memory Protection Unit (MPU)
mbed_official 159:7130f322cb7e 516 @{
mbed_official 159:7130f322cb7e 517 */
mbed_official 159:7130f322cb7e 518
mbed_official 159:7130f322cb7e 519 /**
mbed_official 159:7130f322cb7e 520 \brief Structure type to access the Memory Protection Unit (MPU).
mbed_official 159:7130f322cb7e 521 */
mbed_official 159:7130f322cb7e 522 typedef struct
mbed_official 159:7130f322cb7e 523 {
mbed_official 159:7130f322cb7e 524 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mbed_official 159:7130f322cb7e 525 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mbed_official 159:7130f322cb7e 526 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mbed_official 159:7130f322cb7e 527 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mbed_official 159:7130f322cb7e 528 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mbed_official 159:7130f322cb7e 529 } MPU_Type;
mbed_official 159:7130f322cb7e 530
mbed_official 159:7130f322cb7e 531 /* MPU Type Register Definitions */
mbed_official 159:7130f322cb7e 532 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
mbed_official 159:7130f322cb7e 533 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mbed_official 159:7130f322cb7e 534
mbed_official 159:7130f322cb7e 535 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
mbed_official 159:7130f322cb7e 536 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mbed_official 159:7130f322cb7e 537
mbed_official 159:7130f322cb7e 538 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
mbed_official 159:7130f322cb7e 539 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mbed_official 159:7130f322cb7e 540
mbed_official 159:7130f322cb7e 541 /* MPU Control Register Definitions */
mbed_official 159:7130f322cb7e 542 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
mbed_official 159:7130f322cb7e 543 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mbed_official 159:7130f322cb7e 544
mbed_official 159:7130f322cb7e 545 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
mbed_official 159:7130f322cb7e 546 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mbed_official 159:7130f322cb7e 547
mbed_official 159:7130f322cb7e 548 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
mbed_official 159:7130f322cb7e 549 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mbed_official 159:7130f322cb7e 550
mbed_official 159:7130f322cb7e 551 /* MPU Region Number Register Definitions */
mbed_official 159:7130f322cb7e 552 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
mbed_official 159:7130f322cb7e 553 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mbed_official 159:7130f322cb7e 554
mbed_official 159:7130f322cb7e 555 /* MPU Region Base Address Register Definitions */
mbed_official 159:7130f322cb7e 556 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
mbed_official 159:7130f322cb7e 557 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mbed_official 159:7130f322cb7e 558
mbed_official 159:7130f322cb7e 559 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
mbed_official 159:7130f322cb7e 560 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mbed_official 159:7130f322cb7e 561
mbed_official 159:7130f322cb7e 562 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
mbed_official 159:7130f322cb7e 563 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mbed_official 159:7130f322cb7e 564
mbed_official 159:7130f322cb7e 565 /* MPU Region Attribute and Size Register Definitions */
mbed_official 159:7130f322cb7e 566 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
mbed_official 159:7130f322cb7e 567 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mbed_official 159:7130f322cb7e 568
mbed_official 159:7130f322cb7e 569 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
mbed_official 159:7130f322cb7e 570 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mbed_official 159:7130f322cb7e 571
mbed_official 159:7130f322cb7e 572 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
mbed_official 159:7130f322cb7e 573 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mbed_official 159:7130f322cb7e 574
mbed_official 159:7130f322cb7e 575 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
mbed_official 159:7130f322cb7e 576 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mbed_official 159:7130f322cb7e 577
mbed_official 159:7130f322cb7e 578 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
mbed_official 159:7130f322cb7e 579 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mbed_official 159:7130f322cb7e 580
mbed_official 159:7130f322cb7e 581 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
mbed_official 159:7130f322cb7e 582 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mbed_official 159:7130f322cb7e 583
mbed_official 159:7130f322cb7e 584 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
mbed_official 159:7130f322cb7e 585 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mbed_official 159:7130f322cb7e 586
mbed_official 159:7130f322cb7e 587 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
mbed_official 159:7130f322cb7e 588 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mbed_official 159:7130f322cb7e 589
mbed_official 159:7130f322cb7e 590 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
mbed_official 159:7130f322cb7e 591 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mbed_official 159:7130f322cb7e 592
mbed_official 159:7130f322cb7e 593 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
mbed_official 159:7130f322cb7e 594 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mbed_official 159:7130f322cb7e 595
mbed_official 159:7130f322cb7e 596 /*@} end of group CMSIS_MPU */
mbed_official 159:7130f322cb7e 597 #endif
mbed_official 159:7130f322cb7e 598
mbed_official 159:7130f322cb7e 599
mbed_official 159:7130f322cb7e 600 /**
mbed_official 159:7130f322cb7e 601 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 602 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official 159:7130f322cb7e 603 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
mbed_official 159:7130f322cb7e 604 Therefore they are not covered by the Cortex-M0+ header file.
mbed_official 159:7130f322cb7e 605 @{
mbed_official 159:7130f322cb7e 606 */
mbed_official 159:7130f322cb7e 607 /*@} end of group CMSIS_CoreDebug */
mbed_official 159:7130f322cb7e 608
mbed_official 159:7130f322cb7e 609
mbed_official 159:7130f322cb7e 610 /**
mbed_official 159:7130f322cb7e 611 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 612 \defgroup CMSIS_core_bitfield Core register bit field macros
mbed_official 159:7130f322cb7e 613 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mbed_official 159:7130f322cb7e 614 @{
mbed_official 159:7130f322cb7e 615 */
mbed_official 159:7130f322cb7e 616
mbed_official 159:7130f322cb7e 617 /**
mbed_official 159:7130f322cb7e 618 \brief Mask and shift a bit field value for use in a register bit range.
mbed_official 159:7130f322cb7e 619 \param[in] field Name of the register bit field.
mbed_official 159:7130f322cb7e 620 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
mbed_official 159:7130f322cb7e 621 \return Masked and shifted value.
mbed_official 159:7130f322cb7e 622 */
mbed_official 159:7130f322cb7e 623 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
mbed_official 159:7130f322cb7e 624
mbed_official 159:7130f322cb7e 625 /**
mbed_official 159:7130f322cb7e 626 \brief Mask and shift a register value to extract a bit filed value.
mbed_official 159:7130f322cb7e 627 \param[in] field Name of the register bit field.
mbed_official 159:7130f322cb7e 628 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
mbed_official 159:7130f322cb7e 629 \return Masked and shifted bit field value.
mbed_official 159:7130f322cb7e 630 */
mbed_official 159:7130f322cb7e 631 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
mbed_official 159:7130f322cb7e 632
mbed_official 159:7130f322cb7e 633 /*@} end of group CMSIS_core_bitfield */
mbed_official 159:7130f322cb7e 634
mbed_official 159:7130f322cb7e 635
mbed_official 159:7130f322cb7e 636 /**
mbed_official 159:7130f322cb7e 637 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 638 \defgroup CMSIS_core_base Core Definitions
mbed_official 159:7130f322cb7e 639 \brief Definitions for base addresses, unions, and structures.
mbed_official 159:7130f322cb7e 640 @{
mbed_official 159:7130f322cb7e 641 */
mbed_official 159:7130f322cb7e 642
mbed_official 159:7130f322cb7e 643 /* Memory mapping of Core Hardware */
mbed_official 159:7130f322cb7e 644 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbed_official 159:7130f322cb7e 645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbed_official 159:7130f322cb7e 646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbed_official 159:7130f322cb7e 647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbed_official 159:7130f322cb7e 648
mbed_official 159:7130f322cb7e 649 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbed_official 159:7130f322cb7e 650 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbed_official 159:7130f322cb7e 651 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbed_official 159:7130f322cb7e 652
mbed_official 159:7130f322cb7e 653 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mbed_official 159:7130f322cb7e 654 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mbed_official 159:7130f322cb7e 655 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mbed_official 159:7130f322cb7e 656 #endif
mbed_official 159:7130f322cb7e 657
mbed_official 159:7130f322cb7e 658 /*@} */
mbed_official 159:7130f322cb7e 659
mbed_official 159:7130f322cb7e 660
mbed_official 159:7130f322cb7e 661
mbed_official 159:7130f322cb7e 662 /*******************************************************************************
mbed_official 159:7130f322cb7e 663 * Hardware Abstraction Layer
mbed_official 159:7130f322cb7e 664 Core Function Interface contains:
mbed_official 159:7130f322cb7e 665 - Core NVIC Functions
mbed_official 159:7130f322cb7e 666 - Core SysTick Functions
mbed_official 159:7130f322cb7e 667 - Core Register Access Functions
mbed_official 159:7130f322cb7e 668 ******************************************************************************/
mbed_official 159:7130f322cb7e 669 /**
mbed_official 159:7130f322cb7e 670 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official 159:7130f322cb7e 671 */
mbed_official 159:7130f322cb7e 672
mbed_official 159:7130f322cb7e 673
mbed_official 159:7130f322cb7e 674
mbed_official 159:7130f322cb7e 675 /* ########################## NVIC functions #################################### */
mbed_official 159:7130f322cb7e 676 /**
mbed_official 159:7130f322cb7e 677 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 678 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official 159:7130f322cb7e 679 \brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official 159:7130f322cb7e 680 @{
mbed_official 159:7130f322cb7e 681 */
mbed_official 159:7130f322cb7e 682
mbed_official 159:7130f322cb7e 683 #ifdef CMSIS_NVIC_VIRTUAL
mbed_official 159:7130f322cb7e 684 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 685 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mbed_official 159:7130f322cb7e 686 #endif
mbed_official 159:7130f322cb7e 687 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 688 #else
mbed_official 159:7130f322cb7e 689 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
mbed_official 159:7130f322cb7e 690 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
mbed_official 159:7130f322cb7e 691 #define NVIC_EnableIRQ __NVIC_EnableIRQ
mbed_official 159:7130f322cb7e 692 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
mbed_official 159:7130f322cb7e 693 #define NVIC_DisableIRQ __NVIC_DisableIRQ
mbed_official 159:7130f322cb7e 694 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mbed_official 159:7130f322cb7e 695 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mbed_official 159:7130f322cb7e 696 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mbed_official 159:7130f322cb7e 697 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
mbed_official 159:7130f322cb7e 698 #define NVIC_SetPriority __NVIC_SetPriority
mbed_official 159:7130f322cb7e 699 #define NVIC_GetPriority __NVIC_GetPriority
mbed_official 159:7130f322cb7e 700 #define NVIC_SystemReset __NVIC_SystemReset
mbed_official 159:7130f322cb7e 701 #endif /* CMSIS_NVIC_VIRTUAL */
mbed_official 159:7130f322cb7e 702
mbed_official 159:7130f322cb7e 703 #ifdef CMSIS_VECTAB_VIRTUAL
mbed_official 159:7130f322cb7e 704 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 705 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mbed_official 159:7130f322cb7e 706 #endif
mbed_official 159:7130f322cb7e 707 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 708 #else
mbed_official 159:7130f322cb7e 709 #define NVIC_SetVector __NVIC_SetVector
mbed_official 159:7130f322cb7e 710 #define NVIC_GetVector __NVIC_GetVector
mbed_official 159:7130f322cb7e 711 #endif /* (CMSIS_VECTAB_VIRTUAL) */
mbed_official 159:7130f322cb7e 712
mbed_official 159:7130f322cb7e 713 #define NVIC_USER_IRQ_OFFSET 16
mbed_official 159:7130f322cb7e 714
mbed_official 159:7130f322cb7e 715
mbed_official 159:7130f322cb7e 716 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mbed_official 159:7130f322cb7e 717 /* The following MACROS handle generation of the register offset and byte masks */
mbed_official 159:7130f322cb7e 718 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mbed_official 159:7130f322cb7e 719 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mbed_official 159:7130f322cb7e 720 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mbed_official 159:7130f322cb7e 721
mbed_official 159:7130f322cb7e 722
mbed_official 159:7130f322cb7e 723 /**
mbed_official 159:7130f322cb7e 724 \brief Enable Interrupt
mbed_official 159:7130f322cb7e 725 \details Enables a device specific interrupt in the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 726 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 727 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 728 */
mbed_official 159:7130f322cb7e 729 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 730 {
mbed_official 159:7130f322cb7e 731 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 732 {
mbed_official 159:7130f322cb7e 733 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 734 }
mbed_official 159:7130f322cb7e 735 }
mbed_official 159:7130f322cb7e 736
mbed_official 159:7130f322cb7e 737
mbed_official 159:7130f322cb7e 738 /**
mbed_official 159:7130f322cb7e 739 \brief Get Interrupt Enable status
mbed_official 159:7130f322cb7e 740 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 741 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 742 \return 0 Interrupt is not enabled.
mbed_official 159:7130f322cb7e 743 \return 1 Interrupt is enabled.
mbed_official 159:7130f322cb7e 744 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 745 */
mbed_official 159:7130f322cb7e 746 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 747 {
mbed_official 159:7130f322cb7e 748 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 749 {
mbed_official 159:7130f322cb7e 750 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 751 }
mbed_official 159:7130f322cb7e 752 else
mbed_official 159:7130f322cb7e 753 {
mbed_official 159:7130f322cb7e 754 return(0U);
mbed_official 159:7130f322cb7e 755 }
mbed_official 159:7130f322cb7e 756 }
mbed_official 159:7130f322cb7e 757
mbed_official 159:7130f322cb7e 758
mbed_official 159:7130f322cb7e 759 /**
mbed_official 159:7130f322cb7e 760 \brief Disable Interrupt
mbed_official 159:7130f322cb7e 761 \details Disables a device specific interrupt in the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 762 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 763 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 764 */
mbed_official 159:7130f322cb7e 765 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 766 {
mbed_official 159:7130f322cb7e 767 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 768 {
mbed_official 159:7130f322cb7e 769 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 770 __DSB();
mbed_official 159:7130f322cb7e 771 __ISB();
mbed_official 159:7130f322cb7e 772 }
mbed_official 159:7130f322cb7e 773 }
mbed_official 159:7130f322cb7e 774
mbed_official 159:7130f322cb7e 775
mbed_official 159:7130f322cb7e 776 /**
mbed_official 159:7130f322cb7e 777 \brief Get Pending Interrupt
mbed_official 159:7130f322cb7e 778 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
mbed_official 159:7130f322cb7e 779 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 780 \return 0 Interrupt status is not pending.
mbed_official 159:7130f322cb7e 781 \return 1 Interrupt status is pending.
mbed_official 159:7130f322cb7e 782 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 783 */
mbed_official 159:7130f322cb7e 784 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 785 {
mbed_official 159:7130f322cb7e 786 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 787 {
mbed_official 159:7130f322cb7e 788 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 789 }
mbed_official 159:7130f322cb7e 790 else
mbed_official 159:7130f322cb7e 791 {
mbed_official 159:7130f322cb7e 792 return(0U);
mbed_official 159:7130f322cb7e 793 }
mbed_official 159:7130f322cb7e 794 }
mbed_official 159:7130f322cb7e 795
mbed_official 159:7130f322cb7e 796
mbed_official 159:7130f322cb7e 797 /**
mbed_official 159:7130f322cb7e 798 \brief Set Pending Interrupt
mbed_official 159:7130f322cb7e 799 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official 159:7130f322cb7e 800 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 801 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 802 */
mbed_official 159:7130f322cb7e 803 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 804 {
mbed_official 159:7130f322cb7e 805 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 806 {
mbed_official 159:7130f322cb7e 807 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 808 }
mbed_official 159:7130f322cb7e 809 }
mbed_official 159:7130f322cb7e 810
mbed_official 159:7130f322cb7e 811
mbed_official 159:7130f322cb7e 812 /**
mbed_official 159:7130f322cb7e 813 \brief Clear Pending Interrupt
mbed_official 159:7130f322cb7e 814 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official 159:7130f322cb7e 815 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 816 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 817 */
mbed_official 159:7130f322cb7e 818 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 819 {
mbed_official 159:7130f322cb7e 820 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 821 {
mbed_official 159:7130f322cb7e 822 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 823 }
mbed_official 159:7130f322cb7e 824 }
mbed_official 159:7130f322cb7e 825
mbed_official 159:7130f322cb7e 826
mbed_official 159:7130f322cb7e 827 /**
mbed_official 159:7130f322cb7e 828 \brief Set Interrupt Priority
mbed_official 159:7130f322cb7e 829 \details Sets the priority of a device specific interrupt or a processor exception.
mbed_official 159:7130f322cb7e 830 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 831 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 832 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 833 \param [in] priority Priority to set.
mbed_official 159:7130f322cb7e 834 \note The priority cannot be set for every processor exception.
mbed_official 159:7130f322cb7e 835 */
mbed_official 159:7130f322cb7e 836 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 159:7130f322cb7e 837 {
mbed_official 159:7130f322cb7e 838 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 839 {
mbed_official 159:7130f322cb7e 840 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 159:7130f322cb7e 841 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 159:7130f322cb7e 842 }
mbed_official 159:7130f322cb7e 843 else
mbed_official 159:7130f322cb7e 844 {
mbed_official 159:7130f322cb7e 845 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 159:7130f322cb7e 846 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 159:7130f322cb7e 847 }
mbed_official 159:7130f322cb7e 848 }
mbed_official 159:7130f322cb7e 849
mbed_official 159:7130f322cb7e 850
mbed_official 159:7130f322cb7e 851 /**
mbed_official 159:7130f322cb7e 852 \brief Get Interrupt Priority
mbed_official 159:7130f322cb7e 853 \details Reads the priority of a device specific interrupt or a processor exception.
mbed_official 159:7130f322cb7e 854 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 855 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 856 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 857 \return Interrupt Priority.
mbed_official 159:7130f322cb7e 858 Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official 159:7130f322cb7e 859 */
mbed_official 159:7130f322cb7e 860 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 861 {
mbed_official 159:7130f322cb7e 862
mbed_official 159:7130f322cb7e 863 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 864 {
mbed_official 159:7130f322cb7e 865 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 866 }
mbed_official 159:7130f322cb7e 867 else
mbed_official 159:7130f322cb7e 868 {
mbed_official 159:7130f322cb7e 869 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 870 }
mbed_official 159:7130f322cb7e 871 }
mbed_official 159:7130f322cb7e 872
mbed_official 159:7130f322cb7e 873
mbed_official 159:7130f322cb7e 874 /**
mbed_official 159:7130f322cb7e 875 \brief Set Interrupt Vector
mbed_official 159:7130f322cb7e 876 \details Sets an interrupt vector in SRAM based interrupt vector table.
mbed_official 159:7130f322cb7e 877 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 878 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 879 VTOR must been relocated to SRAM before.
mbed_official 159:7130f322cb7e 880 If VTOR is not present address 0 must be mapped to SRAM.
mbed_official 159:7130f322cb7e 881 \param [in] IRQn Interrupt number
mbed_official 159:7130f322cb7e 882 \param [in] vector Address of interrupt handler function
mbed_official 159:7130f322cb7e 883 */
mbed_official 159:7130f322cb7e 884 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
mbed_official 159:7130f322cb7e 885 {
mbed_official 159:7130f322cb7e 886 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official 159:7130f322cb7e 887 uint32_t *vectors = (uint32_t *)SCB->VTOR;
mbed_official 159:7130f322cb7e 888 #else
mbed_official 159:7130f322cb7e 889 uint32_t *vectors = (uint32_t *)0x0U;
mbed_official 159:7130f322cb7e 890 #endif
mbed_official 159:7130f322cb7e 891 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
mbed_official 159:7130f322cb7e 892 }
mbed_official 159:7130f322cb7e 893
mbed_official 159:7130f322cb7e 894
mbed_official 159:7130f322cb7e 895 /**
mbed_official 159:7130f322cb7e 896 \brief Get Interrupt Vector
mbed_official 159:7130f322cb7e 897 \details Reads an interrupt vector from interrupt vector table.
mbed_official 159:7130f322cb7e 898 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 899 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 900 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 901 \return Address of interrupt handler function
mbed_official 159:7130f322cb7e 902 */
mbed_official 159:7130f322cb7e 903 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 904 {
mbed_official 159:7130f322cb7e 905 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
mbed_official 159:7130f322cb7e 906 uint32_t *vectors = (uint32_t *)SCB->VTOR;
mbed_official 159:7130f322cb7e 907 #else
mbed_official 159:7130f322cb7e 908 uint32_t *vectors = (uint32_t *)0x0U;
mbed_official 159:7130f322cb7e 909 #endif
mbed_official 159:7130f322cb7e 910 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
mbed_official 159:7130f322cb7e 911
mbed_official 159:7130f322cb7e 912 }
mbed_official 159:7130f322cb7e 913
mbed_official 159:7130f322cb7e 914
mbed_official 159:7130f322cb7e 915 /**
mbed_official 159:7130f322cb7e 916 \brief System Reset
mbed_official 159:7130f322cb7e 917 \details Initiates a system reset request to reset the MCU.
mbed_official 159:7130f322cb7e 918 */
mbed_official 159:7130f322cb7e 919 __STATIC_INLINE void __NVIC_SystemReset(void)
mbed_official 159:7130f322cb7e 920 {
mbed_official 159:7130f322cb7e 921 __DSB(); /* Ensure all outstanding memory accesses included
mbed_official 159:7130f322cb7e 922 buffered write are completed before reset */
mbed_official 159:7130f322cb7e 923 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 159:7130f322cb7e 924 SCB_AIRCR_SYSRESETREQ_Msk);
mbed_official 159:7130f322cb7e 925 __DSB(); /* Ensure completion of memory access */
mbed_official 159:7130f322cb7e 926
mbed_official 159:7130f322cb7e 927 for(;;) /* wait until reset */
mbed_official 159:7130f322cb7e 928 {
mbed_official 159:7130f322cb7e 929 __NOP();
mbed_official 159:7130f322cb7e 930 }
mbed_official 159:7130f322cb7e 931 }
mbed_official 159:7130f322cb7e 932
mbed_official 159:7130f322cb7e 933 /*@} end of CMSIS_Core_NVICFunctions */
mbed_official 159:7130f322cb7e 934
mbed_official 159:7130f322cb7e 935
mbed_official 159:7130f322cb7e 936 /* ########################## FPU functions #################################### */
mbed_official 159:7130f322cb7e 937 /**
mbed_official 159:7130f322cb7e 938 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 939 \defgroup CMSIS_Core_FpuFunctions FPU Functions
mbed_official 159:7130f322cb7e 940 \brief Function that provides FPU type.
mbed_official 159:7130f322cb7e 941 @{
mbed_official 159:7130f322cb7e 942 */
mbed_official 159:7130f322cb7e 943
mbed_official 159:7130f322cb7e 944 /**
mbed_official 159:7130f322cb7e 945 \brief get FPU type
mbed_official 159:7130f322cb7e 946 \details returns the FPU type
mbed_official 159:7130f322cb7e 947 \returns
mbed_official 159:7130f322cb7e 948 - \b 0: No FPU
mbed_official 159:7130f322cb7e 949 - \b 1: Single precision FPU
mbed_official 159:7130f322cb7e 950 - \b 2: Double + Single precision FPU
mbed_official 159:7130f322cb7e 951 */
mbed_official 159:7130f322cb7e 952 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
mbed_official 159:7130f322cb7e 953 {
mbed_official 159:7130f322cb7e 954 return 0U; /* No FPU */
mbed_official 159:7130f322cb7e 955 }
mbed_official 159:7130f322cb7e 956
mbed_official 159:7130f322cb7e 957
mbed_official 159:7130f322cb7e 958 /*@} end of CMSIS_Core_FpuFunctions */
mbed_official 159:7130f322cb7e 959
mbed_official 159:7130f322cb7e 960
mbed_official 159:7130f322cb7e 961
mbed_official 159:7130f322cb7e 962 /* ################################## SysTick function ############################################ */
mbed_official 159:7130f322cb7e 963 /**
mbed_official 159:7130f322cb7e 964 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 965 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official 159:7130f322cb7e 966 \brief Functions that configure the System.
mbed_official 159:7130f322cb7e 967 @{
mbed_official 159:7130f322cb7e 968 */
mbed_official 159:7130f322cb7e 969
mbed_official 159:7130f322cb7e 970 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mbed_official 159:7130f322cb7e 971
mbed_official 159:7130f322cb7e 972 /**
mbed_official 159:7130f322cb7e 973 \brief System Tick Configuration
mbed_official 159:7130f322cb7e 974 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official 159:7130f322cb7e 975 Counter is in free running mode to generate periodic interrupts.
mbed_official 159:7130f322cb7e 976 \param [in] ticks Number of ticks between two interrupts.
mbed_official 159:7130f322cb7e 977 \return 0 Function succeeded.
mbed_official 159:7130f322cb7e 978 \return 1 Function failed.
mbed_official 159:7130f322cb7e 979 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official 159:7130f322cb7e 980 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official 159:7130f322cb7e 981 must contain a vendor-specific implementation of this function.
mbed_official 159:7130f322cb7e 982 */
mbed_official 159:7130f322cb7e 983 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official 159:7130f322cb7e 984 {
mbed_official 159:7130f322cb7e 985 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mbed_official 159:7130f322cb7e 986 {
mbed_official 159:7130f322cb7e 987 return (1UL); /* Reload value impossible */
mbed_official 159:7130f322cb7e 988 }
mbed_official 159:7130f322cb7e 989
mbed_official 159:7130f322cb7e 990 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 159:7130f322cb7e 991 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 159:7130f322cb7e 992 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 159:7130f322cb7e 993 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 159:7130f322cb7e 994 SysTick_CTRL_TICKINT_Msk |
mbed_official 159:7130f322cb7e 995 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 159:7130f322cb7e 996 return (0UL); /* Function successful */
mbed_official 159:7130f322cb7e 997 }
mbed_official 159:7130f322cb7e 998
mbed_official 159:7130f322cb7e 999 #endif
mbed_official 159:7130f322cb7e 1000
mbed_official 159:7130f322cb7e 1001 /*@} end of CMSIS_Core_SysTickFunctions */
mbed_official 159:7130f322cb7e 1002
mbed_official 159:7130f322cb7e 1003
mbed_official 159:7130f322cb7e 1004
mbed_official 159:7130f322cb7e 1005
mbed_official 159:7130f322cb7e 1006 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 1007 }
mbed_official 159:7130f322cb7e 1008 #endif
mbed_official 159:7130f322cb7e 1009
mbed_official 159:7130f322cb7e 1010 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
mbed_official 159:7130f322cb7e 1011
mbed_official 159:7130f322cb7e 1012 #endif /* __CMSIS_GENERIC */