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TARGET_SAKURAIO_EVB_01/core_cm0.h@159:7130f322cb7e, 2017-12-21 (annotated)

Committer:
mbed_official
Date:
Thu Dec 21 18:20:02 2017 +0000
Revision:
159:7130f322cb7e
mbed library version 157

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 159:7130f322cb7e 1 /**************************************************************************//**
mbed_official 159:7130f322cb7e 2 * @file core_cm0.h
mbed_official 159:7130f322cb7e 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
mbed_official 159:7130f322cb7e 4 * @version V5.0.2
mbed_official 159:7130f322cb7e 5 * @date 13. February 2017
mbed_official 159:7130f322cb7e 6 ******************************************************************************/
mbed_official 159:7130f322cb7e 7 /*
mbed_official 159:7130f322cb7e 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
mbed_official 159:7130f322cb7e 9 *
mbed_official 159:7130f322cb7e 10 * SPDX-License-Identifier: Apache-2.0
mbed_official 159:7130f322cb7e 11 *
mbed_official 159:7130f322cb7e 12 * Licensed under the Apache License, Version 2.0 (the License); you may
mbed_official 159:7130f322cb7e 13 * not use this file except in compliance with the License.
mbed_official 159:7130f322cb7e 14 * You may obtain a copy of the License at
mbed_official 159:7130f322cb7e 15 *
mbed_official 159:7130f322cb7e 16 * www.apache.org/licenses/LICENSE-2.0
mbed_official 159:7130f322cb7e 17 *
mbed_official 159:7130f322cb7e 18 * Unless required by applicable law or agreed to in writing, software
mbed_official 159:7130f322cb7e 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
mbed_official 159:7130f322cb7e 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 159:7130f322cb7e 21 * See the License for the specific language governing permissions and
mbed_official 159:7130f322cb7e 22 * limitations under the License.
mbed_official 159:7130f322cb7e 23 */
mbed_official 159:7130f322cb7e 24
mbed_official 159:7130f322cb7e 25 #if defined ( __ICCARM__ )
mbed_official 159:7130f322cb7e 26 #pragma system_include /* treat file as system include file for MISRA check */
mbed_official 159:7130f322cb7e 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official 159:7130f322cb7e 28 #pragma clang system_header /* treat file as system include file */
mbed_official 159:7130f322cb7e 29 #endif
mbed_official 159:7130f322cb7e 30
mbed_official 159:7130f322cb7e 31 #ifndef __CORE_CM0_H_GENERIC
mbed_official 159:7130f322cb7e 32 #define __CORE_CM0_H_GENERIC
mbed_official 159:7130f322cb7e 33
mbed_official 159:7130f322cb7e 34 #include <stdint.h>
mbed_official 159:7130f322cb7e 35
mbed_official 159:7130f322cb7e 36 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 37 extern "C" {
mbed_official 159:7130f322cb7e 38 #endif
mbed_official 159:7130f322cb7e 39
mbed_official 159:7130f322cb7e 40 /**
mbed_official 159:7130f322cb7e 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official 159:7130f322cb7e 42 CMSIS violates the following MISRA-C:2004 rules:
mbed_official 159:7130f322cb7e 43
mbed_official 159:7130f322cb7e 44 \li Required Rule 8.5, object/function definition in header file.<br>
mbed_official 159:7130f322cb7e 45 Function definitions in header files are used to allow 'inlining'.
mbed_official 159:7130f322cb7e 46
mbed_official 159:7130f322cb7e 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official 159:7130f322cb7e 48 Unions are used for effective representation of core registers.
mbed_official 159:7130f322cb7e 49
mbed_official 159:7130f322cb7e 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official 159:7130f322cb7e 51 Function-like macros are used to allow more efficient code.
mbed_official 159:7130f322cb7e 52 */
mbed_official 159:7130f322cb7e 53
mbed_official 159:7130f322cb7e 54
mbed_official 159:7130f322cb7e 55 /*******************************************************************************
mbed_official 159:7130f322cb7e 56 * CMSIS definitions
mbed_official 159:7130f322cb7e 57 ******************************************************************************/
mbed_official 159:7130f322cb7e 58 /**
mbed_official 159:7130f322cb7e 59 \ingroup Cortex_M0
mbed_official 159:7130f322cb7e 60 @{
mbed_official 159:7130f322cb7e 61 */
mbed_official 159:7130f322cb7e 62
mbed_official 159:7130f322cb7e 63 /* CMSIS CM0 definitions */
mbed_official 159:7130f322cb7e 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
mbed_official 159:7130f322cb7e 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
mbed_official 159:7130f322cb7e 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
mbed_official 159:7130f322cb7e 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbed_official 159:7130f322cb7e 68
mbed_official 159:7130f322cb7e 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
mbed_official 159:7130f322cb7e 70
mbed_official 159:7130f322cb7e 71 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 159:7130f322cb7e 72 This core does not support an FPU at all
mbed_official 159:7130f322cb7e 73 */
mbed_official 159:7130f322cb7e 74 #define __FPU_USED 0U
mbed_official 159:7130f322cb7e 75
mbed_official 159:7130f322cb7e 76 #if defined ( __CC_ARM )
mbed_official 159:7130f322cb7e 77 #if defined __TARGET_FPU_VFP
mbed_official 159:7130f322cb7e 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 79 #endif
mbed_official 159:7130f322cb7e 80
mbed_official 159:7130f322cb7e 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mbed_official 159:7130f322cb7e 82 #if defined __ARM_PCS_VFP
mbed_official 159:7130f322cb7e 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 84 #endif
mbed_official 159:7130f322cb7e 85
mbed_official 159:7130f322cb7e 86 #elif defined ( __GNUC__ )
mbed_official 159:7130f322cb7e 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 159:7130f322cb7e 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 89 #endif
mbed_official 159:7130f322cb7e 90
mbed_official 159:7130f322cb7e 91 #elif defined ( __ICCARM__ )
mbed_official 159:7130f322cb7e 92 #if defined __ARMVFP__
mbed_official 159:7130f322cb7e 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 94 #endif
mbed_official 159:7130f322cb7e 95
mbed_official 159:7130f322cb7e 96 #elif defined ( __TI_ARM__ )
mbed_official 159:7130f322cb7e 97 #if defined __TI_VFP_SUPPORT__
mbed_official 159:7130f322cb7e 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 99 #endif
mbed_official 159:7130f322cb7e 100
mbed_official 159:7130f322cb7e 101 #elif defined ( __TASKING__ )
mbed_official 159:7130f322cb7e 102 #if defined __FPU_VFP__
mbed_official 159:7130f322cb7e 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 104 #endif
mbed_official 159:7130f322cb7e 105
mbed_official 159:7130f322cb7e 106 #elif defined ( __CSMC__ )
mbed_official 159:7130f322cb7e 107 #if ( __CSMC__ & 0x400U)
mbed_official 159:7130f322cb7e 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 159:7130f322cb7e 109 #endif
mbed_official 159:7130f322cb7e 110
mbed_official 159:7130f322cb7e 111 #endif
mbed_official 159:7130f322cb7e 112
mbed_official 159:7130f322cb7e 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
mbed_official 159:7130f322cb7e 114
mbed_official 159:7130f322cb7e 115
mbed_official 159:7130f322cb7e 116 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 117 }
mbed_official 159:7130f322cb7e 118 #endif
mbed_official 159:7130f322cb7e 119
mbed_official 159:7130f322cb7e 120 #endif /* __CORE_CM0_H_GENERIC */
mbed_official 159:7130f322cb7e 121
mbed_official 159:7130f322cb7e 122 #ifndef __CMSIS_GENERIC
mbed_official 159:7130f322cb7e 123
mbed_official 159:7130f322cb7e 124 #ifndef __CORE_CM0_H_DEPENDANT
mbed_official 159:7130f322cb7e 125 #define __CORE_CM0_H_DEPENDANT
mbed_official 159:7130f322cb7e 126
mbed_official 159:7130f322cb7e 127 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 128 extern "C" {
mbed_official 159:7130f322cb7e 129 #endif
mbed_official 159:7130f322cb7e 130
mbed_official 159:7130f322cb7e 131 /* check device defines and use defaults */
mbed_official 159:7130f322cb7e 132 #if defined __CHECK_DEVICE_DEFINES
mbed_official 159:7130f322cb7e 133 #ifndef __CM0_REV
mbed_official 159:7130f322cb7e 134 #define __CM0_REV 0x0000U
mbed_official 159:7130f322cb7e 135 #warning "__CM0_REV not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 136 #endif
mbed_official 159:7130f322cb7e 137
mbed_official 159:7130f322cb7e 138 #ifndef __NVIC_PRIO_BITS
mbed_official 159:7130f322cb7e 139 #define __NVIC_PRIO_BITS 2U
mbed_official 159:7130f322cb7e 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 141 #endif
mbed_official 159:7130f322cb7e 142
mbed_official 159:7130f322cb7e 143 #ifndef __Vendor_SysTickConfig
mbed_official 159:7130f322cb7e 144 #define __Vendor_SysTickConfig 0U
mbed_official 159:7130f322cb7e 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official 159:7130f322cb7e 146 #endif
mbed_official 159:7130f322cb7e 147 #endif
mbed_official 159:7130f322cb7e 148
mbed_official 159:7130f322cb7e 149 /* IO definitions (access restrictions to peripheral registers) */
mbed_official 159:7130f322cb7e 150 /**
mbed_official 159:7130f322cb7e 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official 159:7130f322cb7e 152
mbed_official 159:7130f322cb7e 153 <strong>IO Type Qualifiers</strong> are used
mbed_official 159:7130f322cb7e 154 \li to specify the access to peripheral variables.
mbed_official 159:7130f322cb7e 155 \li for automatic generation of peripheral register debug information.
mbed_official 159:7130f322cb7e 156 */
mbed_official 159:7130f322cb7e 157 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 158 #define __I volatile /*!< Defines 'read only' permissions */
mbed_official 159:7130f322cb7e 159 #else
mbed_official 159:7130f322cb7e 160 #define __I volatile const /*!< Defines 'read only' permissions */
mbed_official 159:7130f322cb7e 161 #endif
mbed_official 159:7130f322cb7e 162 #define __O volatile /*!< Defines 'write only' permissions */
mbed_official 159:7130f322cb7e 163 #define __IO volatile /*!< Defines 'read / write' permissions */
mbed_official 159:7130f322cb7e 164
mbed_official 159:7130f322cb7e 165 /* following defines should be used for structure members */
mbed_official 159:7130f322cb7e 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
mbed_official 159:7130f322cb7e 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
mbed_official 159:7130f322cb7e 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
mbed_official 159:7130f322cb7e 169
mbed_official 159:7130f322cb7e 170 /*@} end of group Cortex_M0 */
mbed_official 159:7130f322cb7e 171
mbed_official 159:7130f322cb7e 172
mbed_official 159:7130f322cb7e 173
mbed_official 159:7130f322cb7e 174 /*******************************************************************************
mbed_official 159:7130f322cb7e 175 * Register Abstraction
mbed_official 159:7130f322cb7e 176 Core Register contain:
mbed_official 159:7130f322cb7e 177 - Core Register
mbed_official 159:7130f322cb7e 178 - Core NVIC Register
mbed_official 159:7130f322cb7e 179 - Core SCB Register
mbed_official 159:7130f322cb7e 180 - Core SysTick Register
mbed_official 159:7130f322cb7e 181 ******************************************************************************/
mbed_official 159:7130f322cb7e 182 /**
mbed_official 159:7130f322cb7e 183 \defgroup CMSIS_core_register Defines and Type Definitions
mbed_official 159:7130f322cb7e 184 \brief Type definitions and defines for Cortex-M processor based devices.
mbed_official 159:7130f322cb7e 185 */
mbed_official 159:7130f322cb7e 186
mbed_official 159:7130f322cb7e 187 /**
mbed_official 159:7130f322cb7e 188 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 189 \defgroup CMSIS_CORE Status and Control Registers
mbed_official 159:7130f322cb7e 190 \brief Core Register type definitions.
mbed_official 159:7130f322cb7e 191 @{
mbed_official 159:7130f322cb7e 192 */
mbed_official 159:7130f322cb7e 193
mbed_official 159:7130f322cb7e 194 /**
mbed_official 159:7130f322cb7e 195 \brief Union type to access the Application Program Status Register (APSR).
mbed_official 159:7130f322cb7e 196 */
mbed_official 159:7130f322cb7e 197 typedef union
mbed_official 159:7130f322cb7e 198 {
mbed_official 159:7130f322cb7e 199 struct
mbed_official 159:7130f322cb7e 200 {
mbed_official 159:7130f322cb7e 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
mbed_official 159:7130f322cb7e 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 159:7130f322cb7e 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 159:7130f322cb7e 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 159:7130f322cb7e 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 159:7130f322cb7e 206 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 207 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 208 } APSR_Type;
mbed_official 159:7130f322cb7e 209
mbed_official 159:7130f322cb7e 210 /* APSR Register Definitions */
mbed_official 159:7130f322cb7e 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
mbed_official 159:7130f322cb7e 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 159:7130f322cb7e 213
mbed_official 159:7130f322cb7e 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
mbed_official 159:7130f322cb7e 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 159:7130f322cb7e 216
mbed_official 159:7130f322cb7e 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
mbed_official 159:7130f322cb7e 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 159:7130f322cb7e 219
mbed_official 159:7130f322cb7e 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
mbed_official 159:7130f322cb7e 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 159:7130f322cb7e 222
mbed_official 159:7130f322cb7e 223
mbed_official 159:7130f322cb7e 224 /**
mbed_official 159:7130f322cb7e 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official 159:7130f322cb7e 226 */
mbed_official 159:7130f322cb7e 227 typedef union
mbed_official 159:7130f322cb7e 228 {
mbed_official 159:7130f322cb7e 229 struct
mbed_official 159:7130f322cb7e 230 {
mbed_official 159:7130f322cb7e 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 159:7130f322cb7e 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbed_official 159:7130f322cb7e 233 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 234 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 235 } IPSR_Type;
mbed_official 159:7130f322cb7e 236
mbed_official 159:7130f322cb7e 237 /* IPSR Register Definitions */
mbed_official 159:7130f322cb7e 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
mbed_official 159:7130f322cb7e 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 159:7130f322cb7e 240
mbed_official 159:7130f322cb7e 241
mbed_official 159:7130f322cb7e 242 /**
mbed_official 159:7130f322cb7e 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official 159:7130f322cb7e 244 */
mbed_official 159:7130f322cb7e 245 typedef union
mbed_official 159:7130f322cb7e 246 {
mbed_official 159:7130f322cb7e 247 struct
mbed_official 159:7130f322cb7e 248 {
mbed_official 159:7130f322cb7e 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 159:7130f322cb7e 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mbed_official 159:7130f322cb7e 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbed_official 159:7130f322cb7e 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
mbed_official 159:7130f322cb7e 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 159:7130f322cb7e 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 159:7130f322cb7e 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 159:7130f322cb7e 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 159:7130f322cb7e 257 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 258 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 259 } xPSR_Type;
mbed_official 159:7130f322cb7e 260
mbed_official 159:7130f322cb7e 261 /* xPSR Register Definitions */
mbed_official 159:7130f322cb7e 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
mbed_official 159:7130f322cb7e 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 159:7130f322cb7e 264
mbed_official 159:7130f322cb7e 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
mbed_official 159:7130f322cb7e 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 159:7130f322cb7e 267
mbed_official 159:7130f322cb7e 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
mbed_official 159:7130f322cb7e 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 159:7130f322cb7e 270
mbed_official 159:7130f322cb7e 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
mbed_official 159:7130f322cb7e 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 159:7130f322cb7e 273
mbed_official 159:7130f322cb7e 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
mbed_official 159:7130f322cb7e 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 159:7130f322cb7e 276
mbed_official 159:7130f322cb7e 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
mbed_official 159:7130f322cb7e 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 159:7130f322cb7e 279
mbed_official 159:7130f322cb7e 280
mbed_official 159:7130f322cb7e 281 /**
mbed_official 159:7130f322cb7e 282 \brief Union type to access the Control Registers (CONTROL).
mbed_official 159:7130f322cb7e 283 */
mbed_official 159:7130f322cb7e 284 typedef union
mbed_official 159:7130f322cb7e 285 {
mbed_official 159:7130f322cb7e 286 struct
mbed_official 159:7130f322cb7e 287 {
mbed_official 159:7130f322cb7e 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
mbed_official 159:7130f322cb7e 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbed_official 159:7130f322cb7e 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
mbed_official 159:7130f322cb7e 291 } b; /*!< Structure used for bit access */
mbed_official 159:7130f322cb7e 292 uint32_t w; /*!< Type used for word access */
mbed_official 159:7130f322cb7e 293 } CONTROL_Type;
mbed_official 159:7130f322cb7e 294
mbed_official 159:7130f322cb7e 295 /* CONTROL Register Definitions */
mbed_official 159:7130f322cb7e 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
mbed_official 159:7130f322cb7e 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 159:7130f322cb7e 298
mbed_official 159:7130f322cb7e 299 /*@} end of group CMSIS_CORE */
mbed_official 159:7130f322cb7e 300
mbed_official 159:7130f322cb7e 301
mbed_official 159:7130f322cb7e 302 /**
mbed_official 159:7130f322cb7e 303 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official 159:7130f322cb7e 305 \brief Type definitions for the NVIC Registers
mbed_official 159:7130f322cb7e 306 @{
mbed_official 159:7130f322cb7e 307 */
mbed_official 159:7130f322cb7e 308
mbed_official 159:7130f322cb7e 309 /**
mbed_official 159:7130f322cb7e 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official 159:7130f322cb7e 311 */
mbed_official 159:7130f322cb7e 312 typedef struct
mbed_official 159:7130f322cb7e 313 {
mbed_official 159:7130f322cb7e 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbed_official 159:7130f322cb7e 315 uint32_t RESERVED0[31U];
mbed_official 159:7130f322cb7e 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbed_official 159:7130f322cb7e 317 uint32_t RSERVED1[31U];
mbed_official 159:7130f322cb7e 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbed_official 159:7130f322cb7e 319 uint32_t RESERVED2[31U];
mbed_official 159:7130f322cb7e 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbed_official 159:7130f322cb7e 321 uint32_t RESERVED3[31U];
mbed_official 159:7130f322cb7e 322 uint32_t RESERVED4[64U];
mbed_official 159:7130f322cb7e 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mbed_official 159:7130f322cb7e 324 } NVIC_Type;
mbed_official 159:7130f322cb7e 325
mbed_official 159:7130f322cb7e 326 /*@} end of group CMSIS_NVIC */
mbed_official 159:7130f322cb7e 327
mbed_official 159:7130f322cb7e 328
mbed_official 159:7130f322cb7e 329 /**
mbed_official 159:7130f322cb7e 330 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 331 \defgroup CMSIS_SCB System Control Block (SCB)
mbed_official 159:7130f322cb7e 332 \brief Type definitions for the System Control Block Registers
mbed_official 159:7130f322cb7e 333 @{
mbed_official 159:7130f322cb7e 334 */
mbed_official 159:7130f322cb7e 335
mbed_official 159:7130f322cb7e 336 /**
mbed_official 159:7130f322cb7e 337 \brief Structure type to access the System Control Block (SCB).
mbed_official 159:7130f322cb7e 338 */
mbed_official 159:7130f322cb7e 339 typedef struct
mbed_official 159:7130f322cb7e 340 {
mbed_official 159:7130f322cb7e 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbed_official 159:7130f322cb7e 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbed_official 159:7130f322cb7e 343 uint32_t RESERVED0;
mbed_official 159:7130f322cb7e 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbed_official 159:7130f322cb7e 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbed_official 159:7130f322cb7e 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbed_official 159:7130f322cb7e 347 uint32_t RESERVED1;
mbed_official 159:7130f322cb7e 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mbed_official 159:7130f322cb7e 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbed_official 159:7130f322cb7e 350 } SCB_Type;
mbed_official 159:7130f322cb7e 351
mbed_official 159:7130f322cb7e 352 /* SCB CPUID Register Definitions */
mbed_official 159:7130f322cb7e 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
mbed_official 159:7130f322cb7e 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbed_official 159:7130f322cb7e 355
mbed_official 159:7130f322cb7e 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
mbed_official 159:7130f322cb7e 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbed_official 159:7130f322cb7e 358
mbed_official 159:7130f322cb7e 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
mbed_official 159:7130f322cb7e 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbed_official 159:7130f322cb7e 361
mbed_official 159:7130f322cb7e 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
mbed_official 159:7130f322cb7e 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbed_official 159:7130f322cb7e 364
mbed_official 159:7130f322cb7e 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
mbed_official 159:7130f322cb7e 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mbed_official 159:7130f322cb7e 367
mbed_official 159:7130f322cb7e 368 /* SCB Interrupt Control State Register Definitions */
mbed_official 159:7130f322cb7e 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
mbed_official 159:7130f322cb7e 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbed_official 159:7130f322cb7e 371
mbed_official 159:7130f322cb7e 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
mbed_official 159:7130f322cb7e 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbed_official 159:7130f322cb7e 374
mbed_official 159:7130f322cb7e 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
mbed_official 159:7130f322cb7e 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbed_official 159:7130f322cb7e 377
mbed_official 159:7130f322cb7e 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
mbed_official 159:7130f322cb7e 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbed_official 159:7130f322cb7e 380
mbed_official 159:7130f322cb7e 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
mbed_official 159:7130f322cb7e 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbed_official 159:7130f322cb7e 383
mbed_official 159:7130f322cb7e 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
mbed_official 159:7130f322cb7e 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbed_official 159:7130f322cb7e 386
mbed_official 159:7130f322cb7e 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
mbed_official 159:7130f322cb7e 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbed_official 159:7130f322cb7e 389
mbed_official 159:7130f322cb7e 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
mbed_official 159:7130f322cb7e 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbed_official 159:7130f322cb7e 392
mbed_official 159:7130f322cb7e 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 159:7130f322cb7e 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mbed_official 159:7130f322cb7e 395
mbed_official 159:7130f322cb7e 396 /* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official 159:7130f322cb7e 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
mbed_official 159:7130f322cb7e 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbed_official 159:7130f322cb7e 399
mbed_official 159:7130f322cb7e 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
mbed_official 159:7130f322cb7e 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbed_official 159:7130f322cb7e 402
mbed_official 159:7130f322cb7e 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
mbed_official 159:7130f322cb7e 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbed_official 159:7130f322cb7e 405
mbed_official 159:7130f322cb7e 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
mbed_official 159:7130f322cb7e 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbed_official 159:7130f322cb7e 408
mbed_official 159:7130f322cb7e 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbed_official 159:7130f322cb7e 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbed_official 159:7130f322cb7e 411
mbed_official 159:7130f322cb7e 412 /* SCB System Control Register Definitions */
mbed_official 159:7130f322cb7e 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
mbed_official 159:7130f322cb7e 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbed_official 159:7130f322cb7e 415
mbed_official 159:7130f322cb7e 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
mbed_official 159:7130f322cb7e 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbed_official 159:7130f322cb7e 418
mbed_official 159:7130f322cb7e 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
mbed_official 159:7130f322cb7e 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbed_official 159:7130f322cb7e 421
mbed_official 159:7130f322cb7e 422 /* SCB Configuration Control Register Definitions */
mbed_official 159:7130f322cb7e 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
mbed_official 159:7130f322cb7e 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbed_official 159:7130f322cb7e 425
mbed_official 159:7130f322cb7e 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
mbed_official 159:7130f322cb7e 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbed_official 159:7130f322cb7e 428
mbed_official 159:7130f322cb7e 429 /* SCB System Handler Control and State Register Definitions */
mbed_official 159:7130f322cb7e 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
mbed_official 159:7130f322cb7e 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbed_official 159:7130f322cb7e 432
mbed_official 159:7130f322cb7e 433 /*@} end of group CMSIS_SCB */
mbed_official 159:7130f322cb7e 434
mbed_official 159:7130f322cb7e 435
mbed_official 159:7130f322cb7e 436 /**
mbed_official 159:7130f322cb7e 437 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official 159:7130f322cb7e 439 \brief Type definitions for the System Timer Registers.
mbed_official 159:7130f322cb7e 440 @{
mbed_official 159:7130f322cb7e 441 */
mbed_official 159:7130f322cb7e 442
mbed_official 159:7130f322cb7e 443 /**
mbed_official 159:7130f322cb7e 444 \brief Structure type to access the System Timer (SysTick).
mbed_official 159:7130f322cb7e 445 */
mbed_official 159:7130f322cb7e 446 typedef struct
mbed_official 159:7130f322cb7e 447 {
mbed_official 159:7130f322cb7e 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbed_official 159:7130f322cb7e 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbed_official 159:7130f322cb7e 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbed_official 159:7130f322cb7e 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbed_official 159:7130f322cb7e 452 } SysTick_Type;
mbed_official 159:7130f322cb7e 453
mbed_official 159:7130f322cb7e 454 /* SysTick Control / Status Register Definitions */
mbed_official 159:7130f322cb7e 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
mbed_official 159:7130f322cb7e 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbed_official 159:7130f322cb7e 457
mbed_official 159:7130f322cb7e 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
mbed_official 159:7130f322cb7e 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbed_official 159:7130f322cb7e 460
mbed_official 159:7130f322cb7e 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
mbed_official 159:7130f322cb7e 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbed_official 159:7130f322cb7e 463
mbed_official 159:7130f322cb7e 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
mbed_official 159:7130f322cb7e 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mbed_official 159:7130f322cb7e 466
mbed_official 159:7130f322cb7e 467 /* SysTick Reload Register Definitions */
mbed_official 159:7130f322cb7e 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
mbed_official 159:7130f322cb7e 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mbed_official 159:7130f322cb7e 470
mbed_official 159:7130f322cb7e 471 /* SysTick Current Register Definitions */
mbed_official 159:7130f322cb7e 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
mbed_official 159:7130f322cb7e 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mbed_official 159:7130f322cb7e 474
mbed_official 159:7130f322cb7e 475 /* SysTick Calibration Register Definitions */
mbed_official 159:7130f322cb7e 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
mbed_official 159:7130f322cb7e 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbed_official 159:7130f322cb7e 478
mbed_official 159:7130f322cb7e 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
mbed_official 159:7130f322cb7e 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbed_official 159:7130f322cb7e 481
mbed_official 159:7130f322cb7e 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
mbed_official 159:7130f322cb7e 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mbed_official 159:7130f322cb7e 484
mbed_official 159:7130f322cb7e 485 /*@} end of group CMSIS_SysTick */
mbed_official 159:7130f322cb7e 486
mbed_official 159:7130f322cb7e 487
mbed_official 159:7130f322cb7e 488 /**
mbed_official 159:7130f322cb7e 489 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official 159:7130f322cb7e 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
mbed_official 159:7130f322cb7e 492 Therefore they are not covered by the Cortex-M0 header file.
mbed_official 159:7130f322cb7e 493 @{
mbed_official 159:7130f322cb7e 494 */
mbed_official 159:7130f322cb7e 495 /*@} end of group CMSIS_CoreDebug */
mbed_official 159:7130f322cb7e 496
mbed_official 159:7130f322cb7e 497
mbed_official 159:7130f322cb7e 498 /**
mbed_official 159:7130f322cb7e 499 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 500 \defgroup CMSIS_core_bitfield Core register bit field macros
mbed_official 159:7130f322cb7e 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mbed_official 159:7130f322cb7e 502 @{
mbed_official 159:7130f322cb7e 503 */
mbed_official 159:7130f322cb7e 504
mbed_official 159:7130f322cb7e 505 /**
mbed_official 159:7130f322cb7e 506 \brief Mask and shift a bit field value for use in a register bit range.
mbed_official 159:7130f322cb7e 507 \param[in] field Name of the register bit field.
mbed_official 159:7130f322cb7e 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
mbed_official 159:7130f322cb7e 509 \return Masked and shifted value.
mbed_official 159:7130f322cb7e 510 */
mbed_official 159:7130f322cb7e 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
mbed_official 159:7130f322cb7e 512
mbed_official 159:7130f322cb7e 513 /**
mbed_official 159:7130f322cb7e 514 \brief Mask and shift a register value to extract a bit filed value.
mbed_official 159:7130f322cb7e 515 \param[in] field Name of the register bit field.
mbed_official 159:7130f322cb7e 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
mbed_official 159:7130f322cb7e 517 \return Masked and shifted bit field value.
mbed_official 159:7130f322cb7e 518 */
mbed_official 159:7130f322cb7e 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
mbed_official 159:7130f322cb7e 520
mbed_official 159:7130f322cb7e 521 /*@} end of group CMSIS_core_bitfield */
mbed_official 159:7130f322cb7e 522
mbed_official 159:7130f322cb7e 523
mbed_official 159:7130f322cb7e 524 /**
mbed_official 159:7130f322cb7e 525 \ingroup CMSIS_core_register
mbed_official 159:7130f322cb7e 526 \defgroup CMSIS_core_base Core Definitions
mbed_official 159:7130f322cb7e 527 \brief Definitions for base addresses, unions, and structures.
mbed_official 159:7130f322cb7e 528 @{
mbed_official 159:7130f322cb7e 529 */
mbed_official 159:7130f322cb7e 530
mbed_official 159:7130f322cb7e 531 /* Memory mapping of Core Hardware */
mbed_official 159:7130f322cb7e 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbed_official 159:7130f322cb7e 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbed_official 159:7130f322cb7e 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbed_official 159:7130f322cb7e 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbed_official 159:7130f322cb7e 536
mbed_official 159:7130f322cb7e 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbed_official 159:7130f322cb7e 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbed_official 159:7130f322cb7e 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbed_official 159:7130f322cb7e 540
mbed_official 159:7130f322cb7e 541
mbed_official 159:7130f322cb7e 542 /*@} */
mbed_official 159:7130f322cb7e 543
mbed_official 159:7130f322cb7e 544
mbed_official 159:7130f322cb7e 545
mbed_official 159:7130f322cb7e 546 /*******************************************************************************
mbed_official 159:7130f322cb7e 547 * Hardware Abstraction Layer
mbed_official 159:7130f322cb7e 548 Core Function Interface contains:
mbed_official 159:7130f322cb7e 549 - Core NVIC Functions
mbed_official 159:7130f322cb7e 550 - Core SysTick Functions
mbed_official 159:7130f322cb7e 551 - Core Register Access Functions
mbed_official 159:7130f322cb7e 552 ******************************************************************************/
mbed_official 159:7130f322cb7e 553 /**
mbed_official 159:7130f322cb7e 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official 159:7130f322cb7e 555 */
mbed_official 159:7130f322cb7e 556
mbed_official 159:7130f322cb7e 557
mbed_official 159:7130f322cb7e 558
mbed_official 159:7130f322cb7e 559 /* ########################## NVIC functions #################################### */
mbed_official 159:7130f322cb7e 560 /**
mbed_official 159:7130f322cb7e 561 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official 159:7130f322cb7e 563 \brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official 159:7130f322cb7e 564 @{
mbed_official 159:7130f322cb7e 565 */
mbed_official 159:7130f322cb7e 566
mbed_official 159:7130f322cb7e 567 #ifdef CMSIS_NVIC_VIRTUAL
mbed_official 159:7130f322cb7e 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mbed_official 159:7130f322cb7e 570 #endif
mbed_official 159:7130f322cb7e 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 572 #else
mbed_official 159:7130f322cb7e 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
mbed_official 159:7130f322cb7e 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
mbed_official 159:7130f322cb7e 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
mbed_official 159:7130f322cb7e 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
mbed_official 159:7130f322cb7e 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
mbed_official 159:7130f322cb7e 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mbed_official 159:7130f322cb7e 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mbed_official 159:7130f322cb7e 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mbed_official 159:7130f322cb7e 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
mbed_official 159:7130f322cb7e 582 #define NVIC_SetPriority __NVIC_SetPriority
mbed_official 159:7130f322cb7e 583 #define NVIC_GetPriority __NVIC_GetPriority
mbed_official 159:7130f322cb7e 584 #define NVIC_SystemReset __NVIC_SystemReset
mbed_official 159:7130f322cb7e 585 #endif /* CMSIS_NVIC_VIRTUAL */
mbed_official 159:7130f322cb7e 586
mbed_official 159:7130f322cb7e 587 #ifdef CMSIS_VECTAB_VIRTUAL
mbed_official 159:7130f322cb7e 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mbed_official 159:7130f322cb7e 590 #endif
mbed_official 159:7130f322cb7e 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mbed_official 159:7130f322cb7e 592 #else
mbed_official 159:7130f322cb7e 593 #define NVIC_SetVector __NVIC_SetVector
mbed_official 159:7130f322cb7e 594 #define NVIC_GetVector __NVIC_GetVector
mbed_official 159:7130f322cb7e 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
mbed_official 159:7130f322cb7e 596
mbed_official 159:7130f322cb7e 597 #define NVIC_USER_IRQ_OFFSET 16
mbed_official 159:7130f322cb7e 598
mbed_official 159:7130f322cb7e 599
mbed_official 159:7130f322cb7e 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mbed_official 159:7130f322cb7e 601 /* The following MACROS handle generation of the register offset and byte masks */
mbed_official 159:7130f322cb7e 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mbed_official 159:7130f322cb7e 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mbed_official 159:7130f322cb7e 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mbed_official 159:7130f322cb7e 605
mbed_official 159:7130f322cb7e 606
mbed_official 159:7130f322cb7e 607 /**
mbed_official 159:7130f322cb7e 608 \brief Enable Interrupt
mbed_official 159:7130f322cb7e 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 610 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 611 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 612 */
mbed_official 159:7130f322cb7e 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 614 {
mbed_official 159:7130f322cb7e 615 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 616 {
mbed_official 159:7130f322cb7e 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 618 }
mbed_official 159:7130f322cb7e 619 }
mbed_official 159:7130f322cb7e 620
mbed_official 159:7130f322cb7e 621
mbed_official 159:7130f322cb7e 622 /**
mbed_official 159:7130f322cb7e 623 \brief Get Interrupt Enable status
mbed_official 159:7130f322cb7e 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 625 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 626 \return 0 Interrupt is not enabled.
mbed_official 159:7130f322cb7e 627 \return 1 Interrupt is enabled.
mbed_official 159:7130f322cb7e 628 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 629 */
mbed_official 159:7130f322cb7e 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 631 {
mbed_official 159:7130f322cb7e 632 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 633 {
mbed_official 159:7130f322cb7e 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 635 }
mbed_official 159:7130f322cb7e 636 else
mbed_official 159:7130f322cb7e 637 {
mbed_official 159:7130f322cb7e 638 return(0U);
mbed_official 159:7130f322cb7e 639 }
mbed_official 159:7130f322cb7e 640 }
mbed_official 159:7130f322cb7e 641
mbed_official 159:7130f322cb7e 642
mbed_official 159:7130f322cb7e 643 /**
mbed_official 159:7130f322cb7e 644 \brief Disable Interrupt
mbed_official 159:7130f322cb7e 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
mbed_official 159:7130f322cb7e 646 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 647 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 648 */
mbed_official 159:7130f322cb7e 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 650 {
mbed_official 159:7130f322cb7e 651 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 652 {
mbed_official 159:7130f322cb7e 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 654 __DSB();
mbed_official 159:7130f322cb7e 655 __ISB();
mbed_official 159:7130f322cb7e 656 }
mbed_official 159:7130f322cb7e 657 }
mbed_official 159:7130f322cb7e 658
mbed_official 159:7130f322cb7e 659
mbed_official 159:7130f322cb7e 660 /**
mbed_official 159:7130f322cb7e 661 \brief Get Pending Interrupt
mbed_official 159:7130f322cb7e 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
mbed_official 159:7130f322cb7e 663 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 664 \return 0 Interrupt status is not pending.
mbed_official 159:7130f322cb7e 665 \return 1 Interrupt status is pending.
mbed_official 159:7130f322cb7e 666 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 667 */
mbed_official 159:7130f322cb7e 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 669 {
mbed_official 159:7130f322cb7e 670 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 671 {
mbed_official 159:7130f322cb7e 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 159:7130f322cb7e 673 }
mbed_official 159:7130f322cb7e 674 else
mbed_official 159:7130f322cb7e 675 {
mbed_official 159:7130f322cb7e 676 return(0U);
mbed_official 159:7130f322cb7e 677 }
mbed_official 159:7130f322cb7e 678 }
mbed_official 159:7130f322cb7e 679
mbed_official 159:7130f322cb7e 680
mbed_official 159:7130f322cb7e 681 /**
mbed_official 159:7130f322cb7e 682 \brief Set Pending Interrupt
mbed_official 159:7130f322cb7e 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official 159:7130f322cb7e 684 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 685 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 686 */
mbed_official 159:7130f322cb7e 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 688 {
mbed_official 159:7130f322cb7e 689 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 690 {
mbed_official 159:7130f322cb7e 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 692 }
mbed_official 159:7130f322cb7e 693 }
mbed_official 159:7130f322cb7e 694
mbed_official 159:7130f322cb7e 695
mbed_official 159:7130f322cb7e 696 /**
mbed_official 159:7130f322cb7e 697 \brief Clear Pending Interrupt
mbed_official 159:7130f322cb7e 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
mbed_official 159:7130f322cb7e 699 \param [in] IRQn Device specific interrupt number.
mbed_official 159:7130f322cb7e 700 \note IRQn must not be negative.
mbed_official 159:7130f322cb7e 701 */
mbed_official 159:7130f322cb7e 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 703 {
mbed_official 159:7130f322cb7e 704 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 705 {
mbed_official 159:7130f322cb7e 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 159:7130f322cb7e 707 }
mbed_official 159:7130f322cb7e 708 }
mbed_official 159:7130f322cb7e 709
mbed_official 159:7130f322cb7e 710
mbed_official 159:7130f322cb7e 711 /**
mbed_official 159:7130f322cb7e 712 \brief Set Interrupt Priority
mbed_official 159:7130f322cb7e 713 \details Sets the priority of a device specific interrupt or a processor exception.
mbed_official 159:7130f322cb7e 714 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 715 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 716 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 717 \param [in] priority Priority to set.
mbed_official 159:7130f322cb7e 718 \note The priority cannot be set for every processor exception.
mbed_official 159:7130f322cb7e 719 */
mbed_official 159:7130f322cb7e 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 159:7130f322cb7e 721 {
mbed_official 159:7130f322cb7e 722 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 723 {
mbed_official 159:7130f322cb7e 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 159:7130f322cb7e 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 159:7130f322cb7e 726 }
mbed_official 159:7130f322cb7e 727 else
mbed_official 159:7130f322cb7e 728 {
mbed_official 159:7130f322cb7e 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 159:7130f322cb7e 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 159:7130f322cb7e 731 }
mbed_official 159:7130f322cb7e 732 }
mbed_official 159:7130f322cb7e 733
mbed_official 159:7130f322cb7e 734
mbed_official 159:7130f322cb7e 735 /**
mbed_official 159:7130f322cb7e 736 \brief Get Interrupt Priority
mbed_official 159:7130f322cb7e 737 \details Reads the priority of a device specific interrupt or a processor exception.
mbed_official 159:7130f322cb7e 738 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 739 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 740 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 741 \return Interrupt Priority.
mbed_official 159:7130f322cb7e 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
mbed_official 159:7130f322cb7e 743 */
mbed_official 159:7130f322cb7e 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 745 {
mbed_official 159:7130f322cb7e 746
mbed_official 159:7130f322cb7e 747 if ((int32_t)(IRQn) >= 0)
mbed_official 159:7130f322cb7e 748 {
mbed_official 159:7130f322cb7e 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 750 }
mbed_official 159:7130f322cb7e 751 else
mbed_official 159:7130f322cb7e 752 {
mbed_official 159:7130f322cb7e 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mbed_official 159:7130f322cb7e 754 }
mbed_official 159:7130f322cb7e 755 }
mbed_official 159:7130f322cb7e 756
mbed_official 159:7130f322cb7e 757
mbed_official 159:7130f322cb7e 758 /**
mbed_official 159:7130f322cb7e 759 \brief Set Interrupt Vector
mbed_official 159:7130f322cb7e 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
mbed_official 159:7130f322cb7e 761 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 762 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 763 Address 0 must be mapped to SRAM.
mbed_official 159:7130f322cb7e 764 \param [in] IRQn Interrupt number
mbed_official 159:7130f322cb7e 765 \param [in] vector Address of interrupt handler function
mbed_official 159:7130f322cb7e 766 */
mbed_official 159:7130f322cb7e 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
mbed_official 159:7130f322cb7e 768 {
mbed_official 159:7130f322cb7e 769 uint32_t *vectors = (uint32_t *)0x0U;
mbed_official 159:7130f322cb7e 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
mbed_official 159:7130f322cb7e 771 }
mbed_official 159:7130f322cb7e 772
mbed_official 159:7130f322cb7e 773
mbed_official 159:7130f322cb7e 774 /**
mbed_official 159:7130f322cb7e 775 \brief Get Interrupt Vector
mbed_official 159:7130f322cb7e 776 \details Reads an interrupt vector from interrupt vector table.
mbed_official 159:7130f322cb7e 777 The interrupt number can be positive to specify a device specific interrupt,
mbed_official 159:7130f322cb7e 778 or negative to specify a processor exception.
mbed_official 159:7130f322cb7e 779 \param [in] IRQn Interrupt number.
mbed_official 159:7130f322cb7e 780 \return Address of interrupt handler function
mbed_official 159:7130f322cb7e 781 */
mbed_official 159:7130f322cb7e 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
mbed_official 159:7130f322cb7e 783 {
mbed_official 159:7130f322cb7e 784 uint32_t *vectors = (uint32_t *)0x0U;
mbed_official 159:7130f322cb7e 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
mbed_official 159:7130f322cb7e 786 }
mbed_official 159:7130f322cb7e 787
mbed_official 159:7130f322cb7e 788
mbed_official 159:7130f322cb7e 789 /**
mbed_official 159:7130f322cb7e 790 \brief System Reset
mbed_official 159:7130f322cb7e 791 \details Initiates a system reset request to reset the MCU.
mbed_official 159:7130f322cb7e 792 */
mbed_official 159:7130f322cb7e 793 __STATIC_INLINE void __NVIC_SystemReset(void)
mbed_official 159:7130f322cb7e 794 {
mbed_official 159:7130f322cb7e 795 __DSB(); /* Ensure all outstanding memory accesses included
mbed_official 159:7130f322cb7e 796 buffered write are completed before reset */
mbed_official 159:7130f322cb7e 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 159:7130f322cb7e 798 SCB_AIRCR_SYSRESETREQ_Msk);
mbed_official 159:7130f322cb7e 799 __DSB(); /* Ensure completion of memory access */
mbed_official 159:7130f322cb7e 800
mbed_official 159:7130f322cb7e 801 for(;;) /* wait until reset */
mbed_official 159:7130f322cb7e 802 {
mbed_official 159:7130f322cb7e 803 __NOP();
mbed_official 159:7130f322cb7e 804 }
mbed_official 159:7130f322cb7e 805 }
mbed_official 159:7130f322cb7e 806
mbed_official 159:7130f322cb7e 807 /*@} end of CMSIS_Core_NVICFunctions */
mbed_official 159:7130f322cb7e 808
mbed_official 159:7130f322cb7e 809
mbed_official 159:7130f322cb7e 810 /* ########################## FPU functions #################################### */
mbed_official 159:7130f322cb7e 811 /**
mbed_official 159:7130f322cb7e 812 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
mbed_official 159:7130f322cb7e 814 \brief Function that provides FPU type.
mbed_official 159:7130f322cb7e 815 @{
mbed_official 159:7130f322cb7e 816 */
mbed_official 159:7130f322cb7e 817
mbed_official 159:7130f322cb7e 818 /**
mbed_official 159:7130f322cb7e 819 \brief get FPU type
mbed_official 159:7130f322cb7e 820 \details returns the FPU type
mbed_official 159:7130f322cb7e 821 \returns
mbed_official 159:7130f322cb7e 822 - \b 0: No FPU
mbed_official 159:7130f322cb7e 823 - \b 1: Single precision FPU
mbed_official 159:7130f322cb7e 824 - \b 2: Double + Single precision FPU
mbed_official 159:7130f322cb7e 825 */
mbed_official 159:7130f322cb7e 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
mbed_official 159:7130f322cb7e 827 {
mbed_official 159:7130f322cb7e 828 return 0U; /* No FPU */
mbed_official 159:7130f322cb7e 829 }
mbed_official 159:7130f322cb7e 830
mbed_official 159:7130f322cb7e 831
mbed_official 159:7130f322cb7e 832 /*@} end of CMSIS_Core_FpuFunctions */
mbed_official 159:7130f322cb7e 833
mbed_official 159:7130f322cb7e 834
mbed_official 159:7130f322cb7e 835
mbed_official 159:7130f322cb7e 836 /* ################################## SysTick function ############################################ */
mbed_official 159:7130f322cb7e 837 /**
mbed_official 159:7130f322cb7e 838 \ingroup CMSIS_Core_FunctionInterface
mbed_official 159:7130f322cb7e 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official 159:7130f322cb7e 840 \brief Functions that configure the System.
mbed_official 159:7130f322cb7e 841 @{
mbed_official 159:7130f322cb7e 842 */
mbed_official 159:7130f322cb7e 843
mbed_official 159:7130f322cb7e 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mbed_official 159:7130f322cb7e 845
mbed_official 159:7130f322cb7e 846 /**
mbed_official 159:7130f322cb7e 847 \brief System Tick Configuration
mbed_official 159:7130f322cb7e 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official 159:7130f322cb7e 849 Counter is in free running mode to generate periodic interrupts.
mbed_official 159:7130f322cb7e 850 \param [in] ticks Number of ticks between two interrupts.
mbed_official 159:7130f322cb7e 851 \return 0 Function succeeded.
mbed_official 159:7130f322cb7e 852 \return 1 Function failed.
mbed_official 159:7130f322cb7e 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official 159:7130f322cb7e 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official 159:7130f322cb7e 855 must contain a vendor-specific implementation of this function.
mbed_official 159:7130f322cb7e 856 */
mbed_official 159:7130f322cb7e 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official 159:7130f322cb7e 858 {
mbed_official 159:7130f322cb7e 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mbed_official 159:7130f322cb7e 860 {
mbed_official 159:7130f322cb7e 861 return (1UL); /* Reload value impossible */
mbed_official 159:7130f322cb7e 862 }
mbed_official 159:7130f322cb7e 863
mbed_official 159:7130f322cb7e 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 159:7130f322cb7e 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 159:7130f322cb7e 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 159:7130f322cb7e 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 159:7130f322cb7e 868 SysTick_CTRL_TICKINT_Msk |
mbed_official 159:7130f322cb7e 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 159:7130f322cb7e 870 return (0UL); /* Function successful */
mbed_official 159:7130f322cb7e 871 }
mbed_official 159:7130f322cb7e 872
mbed_official 159:7130f322cb7e 873 #endif
mbed_official 159:7130f322cb7e 874
mbed_official 159:7130f322cb7e 875 /*@} end of CMSIS_Core_SysTickFunctions */
mbed_official 159:7130f322cb7e 876
mbed_official 159:7130f322cb7e 877
mbed_official 159:7130f322cb7e 878
mbed_official 159:7130f322cb7e 879
mbed_official 159:7130f322cb7e 880 #ifdef __cplusplus
mbed_official 159:7130f322cb7e 881 }
mbed_official 159:7130f322cb7e 882 #endif
mbed_official 159:7130f322cb7e 883
mbed_official 159:7130f322cb7e 884 #endif /* __CORE_CM0_H_DEPENDANT */
mbed_official 159:7130f322cb7e 885
mbed_official 159:7130f322cb7e 886 #endif /* __CMSIS_GENERIC */