mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

hal/spi_api.h@151:675da3299148, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:46:57 2017 +0100
Revision:
151:675da3299148
Parent:
148:fd96258d940d 
Release 151 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1
<> 128:9bcdf88f62b0 2 /** \addtogroup hal */
<> 128:9bcdf88f62b0 3 /** @{*/
<> 128:9bcdf88f62b0 4 /* mbed Microcontroller Library
<> 128:9bcdf88f62b0 5 * Copyright (c) 2006-2013 ARM Limited
<> 128:9bcdf88f62b0 6 *
<> 128:9bcdf88f62b0 7 * Licensed under the Apache License, Version 2.0 (the "License");
<> 128:9bcdf88f62b0 8 * you may not use this file except in compliance with the License.
<> 128:9bcdf88f62b0 9 * You may obtain a copy of the License at
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * http://www.apache.org/licenses/LICENSE-2.0
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Unless required by applicable law or agreed to in writing, software
<> 128:9bcdf88f62b0 14 * distributed under the License is distributed on an "AS IS" BASIS,
<> 128:9bcdf88f62b0 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 128:9bcdf88f62b0 16 * See the License for the specific language governing permissions and
<> 128:9bcdf88f62b0 17 * limitations under the License.
<> 128:9bcdf88f62b0 18 */
<> 128:9bcdf88f62b0 19 #ifndef MBED_SPI_API_H
<> 128:9bcdf88f62b0 20 #define MBED_SPI_API_H
<> 128:9bcdf88f62b0 21
<> 128:9bcdf88f62b0 22 #include "device.h"
<> 128:9bcdf88f62b0 23 #include "hal/dma_api.h"
<> 128:9bcdf88f62b0 24 #include "hal/buffer.h"
<> 128:9bcdf88f62b0 25
<> 128:9bcdf88f62b0 26 #if DEVICE_SPI
<> 128:9bcdf88f62b0 27
<> 128:9bcdf88f62b0 28 #define SPI_EVENT_ERROR (1 << 1)
<> 128:9bcdf88f62b0 29 #define SPI_EVENT_COMPLETE (1 << 2)
<> 128:9bcdf88f62b0 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
<> 128:9bcdf88f62b0 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
<> 128:9bcdf88f62b0 32
<> 128:9bcdf88f62b0 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
<> 128:9bcdf88f62b0 34
<> 128:9bcdf88f62b0 35 #define SPI_FILL_WORD (0xFFFF)
Kojto 148:fd96258d940d 36 #define SPI_FILL_CHAR (0xFF)
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 #if DEVICE_SPI_ASYNCH
<> 128:9bcdf88f62b0 39 /** Asynch SPI HAL structure
<> 128:9bcdf88f62b0 40 */
<> 128:9bcdf88f62b0 41 typedef struct {
<> 128:9bcdf88f62b0 42 struct spi_s spi; /**< Target specific SPI structure */
<> 128:9bcdf88f62b0 43 struct buffer_s tx_buff; /**< Tx buffer */
<> 128:9bcdf88f62b0 44 struct buffer_s rx_buff; /**< Rx buffer */
<> 128:9bcdf88f62b0 45 } spi_t;
<> 128:9bcdf88f62b0 46
<> 128:9bcdf88f62b0 47 #else
<> 128:9bcdf88f62b0 48 /** Non-asynch SPI HAL structure
<> 128:9bcdf88f62b0 49 */
<> 128:9bcdf88f62b0 50 typedef struct spi_s spi_t;
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 #endif
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 #ifdef __cplusplus
<> 128:9bcdf88f62b0 55 extern "C" {
<> 128:9bcdf88f62b0 56 #endif
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 /**
<> 128:9bcdf88f62b0 59 * \defgroup hal_GeneralSPI SPI Configuration Functions
<> 128:9bcdf88f62b0 60 * @{
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 /** Initialize the SPI peripheral
<> 128:9bcdf88f62b0 64 *
<> 128:9bcdf88f62b0 65 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
<> 128:9bcdf88f62b0 66 * @param[out] obj The SPI object to initialize
<> 128:9bcdf88f62b0 67 * @param[in] mosi The pin to use for MOSI
<> 128:9bcdf88f62b0 68 * @param[in] miso The pin to use for MISO
<> 128:9bcdf88f62b0 69 * @param[in] sclk The pin to use for SCLK
<> 128:9bcdf88f62b0 70 * @param[in] ssel The pin to use for SSEL
<> 128:9bcdf88f62b0 71 */
<> 128:9bcdf88f62b0 72 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 /** Release a SPI object
<> 128:9bcdf88f62b0 75 *
<> 128:9bcdf88f62b0 76 * TODO: spi_free is currently unimplemented
<> 128:9bcdf88f62b0 77 * This will require reference counting at the C++ level to be safe
<> 128:9bcdf88f62b0 78 *
<> 128:9bcdf88f62b0 79 * Return the pins owned by the SPI object to their reset state
<> 128:9bcdf88f62b0 80 * Disable the SPI peripheral
<> 128:9bcdf88f62b0 81 * Disable the SPI clock
<> 128:9bcdf88f62b0 82 * @param[in] obj The SPI object to deinitialize
<> 128:9bcdf88f62b0 83 */
<> 128:9bcdf88f62b0 84 void spi_free(spi_t *obj);
<> 128:9bcdf88f62b0 85
<> 128:9bcdf88f62b0 86 /** Configure the SPI format
<> 128:9bcdf88f62b0 87 *
<> 128:9bcdf88f62b0 88 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
<> 128:9bcdf88f62b0 89 * The default bit order is MSB.
<> 128:9bcdf88f62b0 90 * @param[in,out] obj The SPI object to configure
<> 128:9bcdf88f62b0 91 * @param[in] bits The number of bits per frame
<> 128:9bcdf88f62b0 92 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
<> 128:9bcdf88f62b0 93 * @param[in] slave Zero for master mode or non-zero for slave mode
<> 128:9bcdf88f62b0 94 */
<> 128:9bcdf88f62b0 95 void spi_format(spi_t *obj, int bits, int mode, int slave);
<> 128:9bcdf88f62b0 96
<> 128:9bcdf88f62b0 97 /** Set the SPI baud rate
<> 128:9bcdf88f62b0 98 *
<> 128:9bcdf88f62b0 99 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
<> 128:9bcdf88f62b0 100 * Configures the SPI peripheral's baud rate
<> 128:9bcdf88f62b0 101 * @param[in,out] obj The SPI object to configure
<> 128:9bcdf88f62b0 102 * @param[in] hz The baud rate in Hz
<> 128:9bcdf88f62b0 103 */
<> 128:9bcdf88f62b0 104 void spi_frequency(spi_t *obj, int hz);
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 /**@}*/
<> 128:9bcdf88f62b0 107 /**
<> 128:9bcdf88f62b0 108 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
<> 128:9bcdf88f62b0 109 * @{
<> 128:9bcdf88f62b0 110 */
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112 /** Write a byte out in master mode and receive a value
<> 128:9bcdf88f62b0 113 *
<> 128:9bcdf88f62b0 114 * @param[in] obj The SPI peripheral to use for sending
<> 128:9bcdf88f62b0 115 * @param[in] value The value to send
<> 128:9bcdf88f62b0 116 * @return Returns the value received during send
<> 128:9bcdf88f62b0 117 */
<> 128:9bcdf88f62b0 118 int spi_master_write(spi_t *obj, int value);
<> 128:9bcdf88f62b0 119
AnnaBridge 145:64910690c574 120 /** Write a block out in master mode and receive a value
AnnaBridge 145:64910690c574 121 *
AnnaBridge 145:64910690c574 122 * The total number of bytes sent and recieved will be the maximum of
AnnaBridge 145:64910690c574 123 * tx_length and rx_length. The bytes written will be padded with the
AnnaBridge 145:64910690c574 124 * value 0xff.
AnnaBridge 145:64910690c574 125 *
Kojto 148:fd96258d940d 126 * @param[in] obj The SPI peripheral to use for sending
Kojto 148:fd96258d940d 127 * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
Kojto 148:fd96258d940d 128 * @param[in] tx_length Number of bytes to write, may be zero
Kojto 148:fd96258d940d 129 * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
Kojto 148:fd96258d940d 130 * @param[in] rx_length Number of bytes to read, may be zero
Kojto 148:fd96258d940d 131 * @param[in] write_fill Default data transmitted while performing a read
AnnaBridge 145:64910690c574 132 * @returns
AnnaBridge 145:64910690c574 133 * The number of bytes written and read from the device. This is
AnnaBridge 145:64910690c574 134 * maximum of tx_length and rx_length.
AnnaBridge 145:64910690c574 135 */
Kojto 148:fd96258d940d 136 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
AnnaBridge 145:64910690c574 137
<> 128:9bcdf88f62b0 138 /** Check if a value is available to read
<> 128:9bcdf88f62b0 139 *
<> 128:9bcdf88f62b0 140 * @param[in] obj The SPI peripheral to check
<> 128:9bcdf88f62b0 141 * @return non-zero if a value is available
<> 128:9bcdf88f62b0 142 */
<> 128:9bcdf88f62b0 143 int spi_slave_receive(spi_t *obj);
<> 128:9bcdf88f62b0 144
<> 128:9bcdf88f62b0 145 /** Get a received value out of the SPI receive buffer in slave mode
<> 128:9bcdf88f62b0 146 *
<> 128:9bcdf88f62b0 147 * Blocks until a value is available
<> 128:9bcdf88f62b0 148 * @param[in] obj The SPI peripheral to read
<> 128:9bcdf88f62b0 149 * @return The value received
<> 128:9bcdf88f62b0 150 */
<> 128:9bcdf88f62b0 151 int spi_slave_read(spi_t *obj);
<> 128:9bcdf88f62b0 152
<> 128:9bcdf88f62b0 153 /** Write a value to the SPI peripheral in slave mode
<> 128:9bcdf88f62b0 154 *
<> 128:9bcdf88f62b0 155 * Blocks until the SPI peripheral can be written to
<> 128:9bcdf88f62b0 156 * @param[in] obj The SPI peripheral to write
<> 128:9bcdf88f62b0 157 * @param[in] value The value to write
<> 128:9bcdf88f62b0 158 */
<> 128:9bcdf88f62b0 159 void spi_slave_write(spi_t *obj, int value);
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161 /** Checks if the specified SPI peripheral is in use
<> 128:9bcdf88f62b0 162 *
<> 128:9bcdf88f62b0 163 * @param[in] obj The SPI peripheral to check
<> 128:9bcdf88f62b0 164 * @return non-zero if the peripheral is currently transmitting
<> 128:9bcdf88f62b0 165 */
<> 128:9bcdf88f62b0 166 int spi_busy(spi_t *obj);
<> 128:9bcdf88f62b0 167
<> 128:9bcdf88f62b0 168 /** Get the module number
<> 128:9bcdf88f62b0 169 *
<> 128:9bcdf88f62b0 170 * @param[in] obj The SPI peripheral to check
<> 128:9bcdf88f62b0 171 * @return The module number
<> 128:9bcdf88f62b0 172 */
<> 128:9bcdf88f62b0 173 uint8_t spi_get_module(spi_t *obj);
<> 128:9bcdf88f62b0 174
<> 128:9bcdf88f62b0 175 /**@}*/
<> 128:9bcdf88f62b0 176
<> 128:9bcdf88f62b0 177 #if DEVICE_SPI_ASYNCH
<> 128:9bcdf88f62b0 178 /**
<> 128:9bcdf88f62b0 179 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
<> 128:9bcdf88f62b0 180 * @{
<> 128:9bcdf88f62b0 181 */
<> 128:9bcdf88f62b0 182
<> 128:9bcdf88f62b0 183 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
<> 128:9bcdf88f62b0 184 *
<> 128:9bcdf88f62b0 185 * @param[in] obj The SPI object that holds the transfer information
<> 128:9bcdf88f62b0 186 * @param[in] tx The transmit buffer
<> 128:9bcdf88f62b0 187 * @param[in] tx_length The number of bytes to transmit
<> 128:9bcdf88f62b0 188 * @param[in] rx The receive buffer
<> 128:9bcdf88f62b0 189 * @param[in] rx_length The number of bytes to receive
<> 128:9bcdf88f62b0 190 * @param[in] bit_width The bit width of buffer words
<> 128:9bcdf88f62b0 191 * @param[in] event The logical OR of events to be registered
<> 128:9bcdf88f62b0 192 * @param[in] handler SPI interrupt handler
<> 128:9bcdf88f62b0 193 * @param[in] hint A suggestion for how to use DMA with this transfer
<> 128:9bcdf88f62b0 194 */
<> 128:9bcdf88f62b0 195 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
<> 128:9bcdf88f62b0 196
<> 128:9bcdf88f62b0 197 /** The asynchronous IRQ handler
<> 128:9bcdf88f62b0 198 *
<> 128:9bcdf88f62b0 199 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
<> 128:9bcdf88f62b0 200 * conditions, such as buffer overflows or transfer complete.
<> 128:9bcdf88f62b0 201 * @param[in] obj The SPI object that holds the transfer information
<> 128:9bcdf88f62b0 202 * @return Event flags if a transfer termination condition was met; otherwise 0.
<> 128:9bcdf88f62b0 203 */
<> 128:9bcdf88f62b0 204 uint32_t spi_irq_handler_asynch(spi_t *obj);
<> 128:9bcdf88f62b0 205
<> 128:9bcdf88f62b0 206 /** Attempts to determine if the SPI peripheral is already in use
<> 128:9bcdf88f62b0 207 *
<> 128:9bcdf88f62b0 208 * If a temporary DMA channel has been allocated, peripheral is in use.
<> 128:9bcdf88f62b0 209 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
<> 128:9bcdf88f62b0 210 * channel were allocated.
<> 128:9bcdf88f62b0 211 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
<> 128:9bcdf88f62b0 212 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
<> 128:9bcdf88f62b0 213 * there are any bytes in the FIFOs.
<> 128:9bcdf88f62b0 214 * @param[in] obj The SPI object to check for activity
<> 128:9bcdf88f62b0 215 * @return Non-zero if the SPI port is active or zero if it is not.
<> 128:9bcdf88f62b0 216 */
<> 128:9bcdf88f62b0 217 uint8_t spi_active(spi_t *obj);
<> 128:9bcdf88f62b0 218
<> 128:9bcdf88f62b0 219 /** Abort an SPI transfer
<> 128:9bcdf88f62b0 220 *
<> 128:9bcdf88f62b0 221 * @param obj The SPI peripheral to stop
<> 128:9bcdf88f62b0 222 */
<> 128:9bcdf88f62b0 223 void spi_abort_asynch(spi_t *obj);
<> 128:9bcdf88f62b0 224
<> 128:9bcdf88f62b0 225
<> 128:9bcdf88f62b0 226 #endif
<> 128:9bcdf88f62b0 227
<> 128:9bcdf88f62b0 228 /**@}*/
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 #ifdef __cplusplus
<> 128:9bcdf88f62b0 231 }
<> 128:9bcdf88f62b0 232 #endif // __cplusplus
<> 128:9bcdf88f62b0 233
<> 128:9bcdf88f62b0 234 #endif // SPI_DEVICE
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 #endif // MBED_SPI_API_H
<> 128:9bcdf88f62b0 237
<> 128:9bcdf88f62b0 238 /** @}*/