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TARGET_VBLUNO52/core_sc000.h@151:675da3299148, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:46:57 2017 +0100
Revision:
151:675da3299148
Parent:
148:fd96258d940d
Child:
160:5571c4ff569f
Release 151 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 148:fd96258d940d 1 /**************************************************************************//**
Kojto 148:fd96258d940d 2 * @file core_sc000.h
Kojto 148:fd96258d940d 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
Kojto 148:fd96258d940d 4 * @version V5.0.2
Kojto 148:fd96258d940d 5 * @date 13. February 2017
Kojto 148:fd96258d940d 6 ******************************************************************************/
Kojto 148:fd96258d940d 7 /*
Kojto 148:fd96258d940d 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
Kojto 148:fd96258d940d 9 *
Kojto 148:fd96258d940d 10 * SPDX-License-Identifier: Apache-2.0
Kojto 148:fd96258d940d 11 *
Kojto 148:fd96258d940d 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Kojto 148:fd96258d940d 13 * not use this file except in compliance with the License.
Kojto 148:fd96258d940d 14 * You may obtain a copy of the License at
Kojto 148:fd96258d940d 15 *
Kojto 148:fd96258d940d 16 * www.apache.org/licenses/LICENSE-2.0
Kojto 148:fd96258d940d 17 *
Kojto 148:fd96258d940d 18 * Unless required by applicable law or agreed to in writing, software
Kojto 148:fd96258d940d 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Kojto 148:fd96258d940d 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 148:fd96258d940d 21 * See the License for the specific language governing permissions and
Kojto 148:fd96258d940d 22 * limitations under the License.
Kojto 148:fd96258d940d 23 */
Kojto 148:fd96258d940d 24
Kojto 148:fd96258d940d 25 #if defined ( __ICCARM__ )
Kojto 148:fd96258d940d 26 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 148:fd96258d940d 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto 148:fd96258d940d 28 #pragma clang system_header /* treat file as system include file */
Kojto 148:fd96258d940d 29 #endif
Kojto 148:fd96258d940d 30
Kojto 148:fd96258d940d 31 #ifndef __CORE_SC000_H_GENERIC
Kojto 148:fd96258d940d 32 #define __CORE_SC000_H_GENERIC
Kojto 148:fd96258d940d 33
Kojto 148:fd96258d940d 34 #include <stdint.h>
Kojto 148:fd96258d940d 35
Kojto 148:fd96258d940d 36 #ifdef __cplusplus
Kojto 148:fd96258d940d 37 extern "C" {
Kojto 148:fd96258d940d 38 #endif
Kojto 148:fd96258d940d 39
Kojto 148:fd96258d940d 40 /**
Kojto 148:fd96258d940d 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 148:fd96258d940d 42 CMSIS violates the following MISRA-C:2004 rules:
Kojto 148:fd96258d940d 43
Kojto 148:fd96258d940d 44 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 148:fd96258d940d 45 Function definitions in header files are used to allow 'inlining'.
Kojto 148:fd96258d940d 46
Kojto 148:fd96258d940d 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 148:fd96258d940d 48 Unions are used for effective representation of core registers.
Kojto 148:fd96258d940d 49
Kojto 148:fd96258d940d 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 148:fd96258d940d 51 Function-like macros are used to allow more efficient code.
Kojto 148:fd96258d940d 52 */
Kojto 148:fd96258d940d 53
Kojto 148:fd96258d940d 54
Kojto 148:fd96258d940d 55 /*******************************************************************************
Kojto 148:fd96258d940d 56 * CMSIS definitions
Kojto 148:fd96258d940d 57 ******************************************************************************/
Kojto 148:fd96258d940d 58 /**
Kojto 148:fd96258d940d 59 \ingroup SC000
Kojto 148:fd96258d940d 60 @{
Kojto 148:fd96258d940d 61 */
Kojto 148:fd96258d940d 62
Kojto 148:fd96258d940d 63 /* CMSIS SC000 definitions */
Kojto 148:fd96258d940d 64 #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
Kojto 148:fd96258d940d 65 #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
Kojto 148:fd96258d940d 66 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
Kojto 148:fd96258d940d 67 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 148:fd96258d940d 68
Kojto 148:fd96258d940d 69 #define __CORTEX_SC (000U) /*!< Cortex secure core */
Kojto 148:fd96258d940d 70
Kojto 148:fd96258d940d 71 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 148:fd96258d940d 72 This core does not support an FPU at all
Kojto 148:fd96258d940d 73 */
Kojto 148:fd96258d940d 74 #define __FPU_USED 0U
Kojto 148:fd96258d940d 75
Kojto 148:fd96258d940d 76 #if defined ( __CC_ARM )
Kojto 148:fd96258d940d 77 #if defined __TARGET_FPU_VFP
Kojto 148:fd96258d940d 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 79 #endif
Kojto 148:fd96258d940d 80
Kojto 148:fd96258d940d 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
Kojto 148:fd96258d940d 82 #if defined __ARM_PCS_VFP
Kojto 148:fd96258d940d 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 84 #endif
Kojto 148:fd96258d940d 85
Kojto 148:fd96258d940d 86 #elif defined ( __GNUC__ )
Kojto 148:fd96258d940d 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 148:fd96258d940d 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 89 #endif
Kojto 148:fd96258d940d 90
Kojto 148:fd96258d940d 91 #elif defined ( __ICCARM__ )
Kojto 148:fd96258d940d 92 #if defined __ARMVFP__
Kojto 148:fd96258d940d 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 94 #endif
Kojto 148:fd96258d940d 95
Kojto 148:fd96258d940d 96 #elif defined ( __TI_ARM__ )
Kojto 148:fd96258d940d 97 #if defined __TI_VFP_SUPPORT__
Kojto 148:fd96258d940d 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 99 #endif
Kojto 148:fd96258d940d 100
Kojto 148:fd96258d940d 101 #elif defined ( __TASKING__ )
Kojto 148:fd96258d940d 102 #if defined __FPU_VFP__
Kojto 148:fd96258d940d 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 104 #endif
Kojto 148:fd96258d940d 105
Kojto 148:fd96258d940d 106 #elif defined ( __CSMC__ )
Kojto 148:fd96258d940d 107 #if ( __CSMC__ & 0x400U)
Kojto 148:fd96258d940d 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 148:fd96258d940d 109 #endif
Kojto 148:fd96258d940d 110
Kojto 148:fd96258d940d 111 #endif
Kojto 148:fd96258d940d 112
Kojto 148:fd96258d940d 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Kojto 148:fd96258d940d 114
Kojto 148:fd96258d940d 115
Kojto 148:fd96258d940d 116 #ifdef __cplusplus
Kojto 148:fd96258d940d 117 }
Kojto 148:fd96258d940d 118 #endif
Kojto 148:fd96258d940d 119
Kojto 148:fd96258d940d 120 #endif /* __CORE_SC000_H_GENERIC */
Kojto 148:fd96258d940d 121
Kojto 148:fd96258d940d 122 #ifndef __CMSIS_GENERIC
Kojto 148:fd96258d940d 123
Kojto 148:fd96258d940d 124 #ifndef __CORE_SC000_H_DEPENDANT
Kojto 148:fd96258d940d 125 #define __CORE_SC000_H_DEPENDANT
Kojto 148:fd96258d940d 126
Kojto 148:fd96258d940d 127 #ifdef __cplusplus
Kojto 148:fd96258d940d 128 extern "C" {
Kojto 148:fd96258d940d 129 #endif
Kojto 148:fd96258d940d 130
Kojto 148:fd96258d940d 131 /* check device defines and use defaults */
Kojto 148:fd96258d940d 132 #if defined __CHECK_DEVICE_DEFINES
Kojto 148:fd96258d940d 133 #ifndef __SC000_REV
Kojto 148:fd96258d940d 134 #define __SC000_REV 0x0000U
Kojto 148:fd96258d940d 135 #warning "__SC000_REV not defined in device header file; using default!"
Kojto 148:fd96258d940d 136 #endif
Kojto 148:fd96258d940d 137
Kojto 148:fd96258d940d 138 #ifndef __MPU_PRESENT
Kojto 148:fd96258d940d 139 #define __MPU_PRESENT 0U
Kojto 148:fd96258d940d 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 148:fd96258d940d 141 #endif
Kojto 148:fd96258d940d 142
Kojto 148:fd96258d940d 143 #ifndef __NVIC_PRIO_BITS
Kojto 148:fd96258d940d 144 #define __NVIC_PRIO_BITS 2U
Kojto 148:fd96258d940d 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 148:fd96258d940d 146 #endif
Kojto 148:fd96258d940d 147
Kojto 148:fd96258d940d 148 #ifndef __Vendor_SysTickConfig
Kojto 148:fd96258d940d 149 #define __Vendor_SysTickConfig 0U
Kojto 148:fd96258d940d 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 148:fd96258d940d 151 #endif
Kojto 148:fd96258d940d 152 #endif
Kojto 148:fd96258d940d 153
Kojto 148:fd96258d940d 154 /* IO definitions (access restrictions to peripheral registers) */
Kojto 148:fd96258d940d 155 /**
Kojto 148:fd96258d940d 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 148:fd96258d940d 157
Kojto 148:fd96258d940d 158 <strong>IO Type Qualifiers</strong> are used
Kojto 148:fd96258d940d 159 \li to specify the access to peripheral variables.
Kojto 148:fd96258d940d 160 \li for automatic generation of peripheral register debug information.
Kojto 148:fd96258d940d 161 */
Kojto 148:fd96258d940d 162 #ifdef __cplusplus
Kojto 148:fd96258d940d 163 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 148:fd96258d940d 164 #else
Kojto 148:fd96258d940d 165 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 148:fd96258d940d 166 #endif
Kojto 148:fd96258d940d 167 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 148:fd96258d940d 168 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 148:fd96258d940d 169
Kojto 148:fd96258d940d 170 /* following defines should be used for structure members */
Kojto 148:fd96258d940d 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Kojto 148:fd96258d940d 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
Kojto 148:fd96258d940d 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Kojto 148:fd96258d940d 174
Kojto 148:fd96258d940d 175 /*@} end of group SC000 */
Kojto 148:fd96258d940d 176
Kojto 148:fd96258d940d 177
Kojto 148:fd96258d940d 178
Kojto 148:fd96258d940d 179 /*******************************************************************************
Kojto 148:fd96258d940d 180 * Register Abstraction
Kojto 148:fd96258d940d 181 Core Register contain:
Kojto 148:fd96258d940d 182 - Core Register
Kojto 148:fd96258d940d 183 - Core NVIC Register
Kojto 148:fd96258d940d 184 - Core SCB Register
Kojto 148:fd96258d940d 185 - Core SysTick Register
Kojto 148:fd96258d940d 186 - Core MPU Register
Kojto 148:fd96258d940d 187 ******************************************************************************/
Kojto 148:fd96258d940d 188 /**
Kojto 148:fd96258d940d 189 \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 148:fd96258d940d 190 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 148:fd96258d940d 191 */
Kojto 148:fd96258d940d 192
Kojto 148:fd96258d940d 193 /**
Kojto 148:fd96258d940d 194 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 195 \defgroup CMSIS_CORE Status and Control Registers
Kojto 148:fd96258d940d 196 \brief Core Register type definitions.
Kojto 148:fd96258d940d 197 @{
Kojto 148:fd96258d940d 198 */
Kojto 148:fd96258d940d 199
Kojto 148:fd96258d940d 200 /**
Kojto 148:fd96258d940d 201 \brief Union type to access the Application Program Status Register (APSR).
Kojto 148:fd96258d940d 202 */
Kojto 148:fd96258d940d 203 typedef union
Kojto 148:fd96258d940d 204 {
Kojto 148:fd96258d940d 205 struct
Kojto 148:fd96258d940d 206 {
Kojto 148:fd96258d940d 207 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 148:fd96258d940d 208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 148:fd96258d940d 209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 148:fd96258d940d 210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 148:fd96258d940d 211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 148:fd96258d940d 212 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 213 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 214 } APSR_Type;
Kojto 148:fd96258d940d 215
Kojto 148:fd96258d940d 216 /* APSR Register Definitions */
Kojto 148:fd96258d940d 217 #define APSR_N_Pos 31U /*!< APSR: N Position */
Kojto 148:fd96258d940d 218 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 148:fd96258d940d 219
Kojto 148:fd96258d940d 220 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Kojto 148:fd96258d940d 221 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 148:fd96258d940d 222
Kojto 148:fd96258d940d 223 #define APSR_C_Pos 29U /*!< APSR: C Position */
Kojto 148:fd96258d940d 224 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 148:fd96258d940d 225
Kojto 148:fd96258d940d 226 #define APSR_V_Pos 28U /*!< APSR: V Position */
Kojto 148:fd96258d940d 227 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 148:fd96258d940d 228
Kojto 148:fd96258d940d 229
Kojto 148:fd96258d940d 230 /**
Kojto 148:fd96258d940d 231 \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 148:fd96258d940d 232 */
Kojto 148:fd96258d940d 233 typedef union
Kojto 148:fd96258d940d 234 {
Kojto 148:fd96258d940d 235 struct
Kojto 148:fd96258d940d 236 {
Kojto 148:fd96258d940d 237 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 148:fd96258d940d 238 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 148:fd96258d940d 239 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 240 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 241 } IPSR_Type;
Kojto 148:fd96258d940d 242
Kojto 148:fd96258d940d 243 /* IPSR Register Definitions */
Kojto 148:fd96258d940d 244 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Kojto 148:fd96258d940d 245 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 148:fd96258d940d 246
Kojto 148:fd96258d940d 247
Kojto 148:fd96258d940d 248 /**
Kojto 148:fd96258d940d 249 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 148:fd96258d940d 250 */
Kojto 148:fd96258d940d 251 typedef union
Kojto 148:fd96258d940d 252 {
Kojto 148:fd96258d940d 253 struct
Kojto 148:fd96258d940d 254 {
Kojto 148:fd96258d940d 255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 148:fd96258d940d 256 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 148:fd96258d940d 257 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 148:fd96258d940d 258 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 148:fd96258d940d 259 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 148:fd96258d940d 260 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 148:fd96258d940d 261 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 148:fd96258d940d 262 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 148:fd96258d940d 263 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 264 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 265 } xPSR_Type;
Kojto 148:fd96258d940d 266
Kojto 148:fd96258d940d 267 /* xPSR Register Definitions */
Kojto 148:fd96258d940d 268 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Kojto 148:fd96258d940d 269 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 148:fd96258d940d 270
Kojto 148:fd96258d940d 271 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Kojto 148:fd96258d940d 272 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 148:fd96258d940d 273
Kojto 148:fd96258d940d 274 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Kojto 148:fd96258d940d 275 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 148:fd96258d940d 276
Kojto 148:fd96258d940d 277 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Kojto 148:fd96258d940d 278 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 148:fd96258d940d 279
Kojto 148:fd96258d940d 280 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Kojto 148:fd96258d940d 281 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 148:fd96258d940d 282
Kojto 148:fd96258d940d 283 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Kojto 148:fd96258d940d 284 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 148:fd96258d940d 285
Kojto 148:fd96258d940d 286
Kojto 148:fd96258d940d 287 /**
Kojto 148:fd96258d940d 288 \brief Union type to access the Control Registers (CONTROL).
Kojto 148:fd96258d940d 289 */
Kojto 148:fd96258d940d 290 typedef union
Kojto 148:fd96258d940d 291 {
Kojto 148:fd96258d940d 292 struct
Kojto 148:fd96258d940d 293 {
Kojto 148:fd96258d940d 294 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
Kojto 148:fd96258d940d 295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 148:fd96258d940d 296 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 148:fd96258d940d 297 } b; /*!< Structure used for bit access */
Kojto 148:fd96258d940d 298 uint32_t w; /*!< Type used for word access */
Kojto 148:fd96258d940d 299 } CONTROL_Type;
Kojto 148:fd96258d940d 300
Kojto 148:fd96258d940d 301 /* CONTROL Register Definitions */
Kojto 148:fd96258d940d 302 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Kojto 148:fd96258d940d 303 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 148:fd96258d940d 304
Kojto 148:fd96258d940d 305 /*@} end of group CMSIS_CORE */
Kojto 148:fd96258d940d 306
Kojto 148:fd96258d940d 307
Kojto 148:fd96258d940d 308 /**
Kojto 148:fd96258d940d 309 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 310 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 148:fd96258d940d 311 \brief Type definitions for the NVIC Registers
Kojto 148:fd96258d940d 312 @{
Kojto 148:fd96258d940d 313 */
Kojto 148:fd96258d940d 314
Kojto 148:fd96258d940d 315 /**
Kojto 148:fd96258d940d 316 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 148:fd96258d940d 317 */
Kojto 148:fd96258d940d 318 typedef struct
Kojto 148:fd96258d940d 319 {
Kojto 148:fd96258d940d 320 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 148:fd96258d940d 321 uint32_t RESERVED0[31U];
Kojto 148:fd96258d940d 322 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 148:fd96258d940d 323 uint32_t RSERVED1[31U];
Kojto 148:fd96258d940d 324 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 148:fd96258d940d 325 uint32_t RESERVED2[31U];
Kojto 148:fd96258d940d 326 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 148:fd96258d940d 327 uint32_t RESERVED3[31U];
Kojto 148:fd96258d940d 328 uint32_t RESERVED4[64U];
Kojto 148:fd96258d940d 329 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 148:fd96258d940d 330 } NVIC_Type;
Kojto 148:fd96258d940d 331
Kojto 148:fd96258d940d 332 /*@} end of group CMSIS_NVIC */
Kojto 148:fd96258d940d 333
Kojto 148:fd96258d940d 334
Kojto 148:fd96258d940d 335 /**
Kojto 148:fd96258d940d 336 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 337 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 148:fd96258d940d 338 \brief Type definitions for the System Control Block Registers
Kojto 148:fd96258d940d 339 @{
Kojto 148:fd96258d940d 340 */
Kojto 148:fd96258d940d 341
Kojto 148:fd96258d940d 342 /**
Kojto 148:fd96258d940d 343 \brief Structure type to access the System Control Block (SCB).
Kojto 148:fd96258d940d 344 */
Kojto 148:fd96258d940d 345 typedef struct
Kojto 148:fd96258d940d 346 {
Kojto 148:fd96258d940d 347 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 148:fd96258d940d 348 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 148:fd96258d940d 349 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 148:fd96258d940d 350 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 148:fd96258d940d 351 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 148:fd96258d940d 352 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 148:fd96258d940d 353 uint32_t RESERVED0[1U];
Kojto 148:fd96258d940d 354 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 148:fd96258d940d 355 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 148:fd96258d940d 356 uint32_t RESERVED1[154U];
Kojto 148:fd96258d940d 357 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Kojto 148:fd96258d940d 358 } SCB_Type;
Kojto 148:fd96258d940d 359
Kojto 148:fd96258d940d 360 /* SCB CPUID Register Definitions */
Kojto 148:fd96258d940d 361 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 148:fd96258d940d 362 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 148:fd96258d940d 363
Kojto 148:fd96258d940d 364 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Kojto 148:fd96258d940d 365 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 148:fd96258d940d 366
Kojto 148:fd96258d940d 367 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 148:fd96258d940d 368 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 148:fd96258d940d 369
Kojto 148:fd96258d940d 370 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Kojto 148:fd96258d940d 371 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 148:fd96258d940d 372
Kojto 148:fd96258d940d 373 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Kojto 148:fd96258d940d 374 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 148:fd96258d940d 375
Kojto 148:fd96258d940d 376 /* SCB Interrupt Control State Register Definitions */
Kojto 148:fd96258d940d 377 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Kojto 148:fd96258d940d 378 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 148:fd96258d940d 379
Kojto 148:fd96258d940d 380 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Kojto 148:fd96258d940d 381 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 148:fd96258d940d 382
Kojto 148:fd96258d940d 383 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Kojto 148:fd96258d940d 384 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 148:fd96258d940d 385
Kojto 148:fd96258d940d 386 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Kojto 148:fd96258d940d 387 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 148:fd96258d940d 388
Kojto 148:fd96258d940d 389 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Kojto 148:fd96258d940d 390 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 148:fd96258d940d 391
Kojto 148:fd96258d940d 392 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 148:fd96258d940d 393 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 148:fd96258d940d 394
Kojto 148:fd96258d940d 395 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Kojto 148:fd96258d940d 396 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 148:fd96258d940d 397
Kojto 148:fd96258d940d 398 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Kojto 148:fd96258d940d 399 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 148:fd96258d940d 400
Kojto 148:fd96258d940d 401 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Kojto 148:fd96258d940d 402 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 148:fd96258d940d 403
Kojto 148:fd96258d940d 404 /* SCB Interrupt Control State Register Definitions */
Kojto 148:fd96258d940d 405 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Kojto 148:fd96258d940d 406 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 148:fd96258d940d 407
Kojto 148:fd96258d940d 408 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 148:fd96258d940d 409 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Kojto 148:fd96258d940d 410 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 148:fd96258d940d 411
Kojto 148:fd96258d940d 412 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 148:fd96258d940d 413 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 148:fd96258d940d 414
Kojto 148:fd96258d940d 415 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Kojto 148:fd96258d940d 416 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 148:fd96258d940d 417
Kojto 148:fd96258d940d 418 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 148:fd96258d940d 419 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 148:fd96258d940d 420
Kojto 148:fd96258d940d 421 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 148:fd96258d940d 422 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 148:fd96258d940d 423
Kojto 148:fd96258d940d 424 /* SCB System Control Register Definitions */
Kojto 148:fd96258d940d 425 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Kojto 148:fd96258d940d 426 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 148:fd96258d940d 427
Kojto 148:fd96258d940d 428 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Kojto 148:fd96258d940d 429 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 148:fd96258d940d 430
Kojto 148:fd96258d940d 431 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 148:fd96258d940d 432 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 148:fd96258d940d 433
Kojto 148:fd96258d940d 434 /* SCB Configuration Control Register Definitions */
Kojto 148:fd96258d940d 435 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Kojto 148:fd96258d940d 436 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 148:fd96258d940d 437
Kojto 148:fd96258d940d 438 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 148:fd96258d940d 439 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 148:fd96258d940d 440
Kojto 148:fd96258d940d 441 /* SCB System Handler Control and State Register Definitions */
Kojto 148:fd96258d940d 442 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 148:fd96258d940d 443 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 148:fd96258d940d 444
Kojto 148:fd96258d940d 445 /*@} end of group CMSIS_SCB */
Kojto 148:fd96258d940d 446
Kojto 148:fd96258d940d 447
Kojto 148:fd96258d940d 448 /**
Kojto 148:fd96258d940d 449 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 450 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 148:fd96258d940d 451 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 148:fd96258d940d 452 @{
Kojto 148:fd96258d940d 453 */
Kojto 148:fd96258d940d 454
Kojto 148:fd96258d940d 455 /**
Kojto 148:fd96258d940d 456 \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 148:fd96258d940d 457 */
Kojto 148:fd96258d940d 458 typedef struct
Kojto 148:fd96258d940d 459 {
Kojto 148:fd96258d940d 460 uint32_t RESERVED0[2U];
Kojto 148:fd96258d940d 461 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 148:fd96258d940d 462 } SCnSCB_Type;
Kojto 148:fd96258d940d 463
Kojto 148:fd96258d940d 464 /* Auxiliary Control Register Definitions */
Kojto 148:fd96258d940d 465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
Kojto 148:fd96258d940d 466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 148:fd96258d940d 467
Kojto 148:fd96258d940d 468 /*@} end of group CMSIS_SCnotSCB */
Kojto 148:fd96258d940d 469
Kojto 148:fd96258d940d 470
Kojto 148:fd96258d940d 471 /**
Kojto 148:fd96258d940d 472 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 473 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 148:fd96258d940d 474 \brief Type definitions for the System Timer Registers.
Kojto 148:fd96258d940d 475 @{
Kojto 148:fd96258d940d 476 */
Kojto 148:fd96258d940d 477
Kojto 148:fd96258d940d 478 /**
Kojto 148:fd96258d940d 479 \brief Structure type to access the System Timer (SysTick).
Kojto 148:fd96258d940d 480 */
Kojto 148:fd96258d940d 481 typedef struct
Kojto 148:fd96258d940d 482 {
Kojto 148:fd96258d940d 483 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 148:fd96258d940d 484 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 148:fd96258d940d 485 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 148:fd96258d940d 486 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 148:fd96258d940d 487 } SysTick_Type;
Kojto 148:fd96258d940d 488
Kojto 148:fd96258d940d 489 /* SysTick Control / Status Register Definitions */
Kojto 148:fd96258d940d 490 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 148:fd96258d940d 491 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 148:fd96258d940d 492
Kojto 148:fd96258d940d 493 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 148:fd96258d940d 494 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 148:fd96258d940d 495
Kojto 148:fd96258d940d 496 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Kojto 148:fd96258d940d 497 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 148:fd96258d940d 498
Kojto 148:fd96258d940d 499 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Kojto 148:fd96258d940d 500 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 148:fd96258d940d 501
Kojto 148:fd96258d940d 502 /* SysTick Reload Register Definitions */
Kojto 148:fd96258d940d 503 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Kojto 148:fd96258d940d 504 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 148:fd96258d940d 505
Kojto 148:fd96258d940d 506 /* SysTick Current Register Definitions */
Kojto 148:fd96258d940d 507 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Kojto 148:fd96258d940d 508 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 148:fd96258d940d 509
Kojto 148:fd96258d940d 510 /* SysTick Calibration Register Definitions */
Kojto 148:fd96258d940d 511 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Kojto 148:fd96258d940d 512 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 148:fd96258d940d 513
Kojto 148:fd96258d940d 514 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Kojto 148:fd96258d940d 515 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 148:fd96258d940d 516
Kojto 148:fd96258d940d 517 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Kojto 148:fd96258d940d 518 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 148:fd96258d940d 519
Kojto 148:fd96258d940d 520 /*@} end of group CMSIS_SysTick */
Kojto 148:fd96258d940d 521
Kojto 148:fd96258d940d 522 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto 148:fd96258d940d 523 /**
Kojto 148:fd96258d940d 524 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 525 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 148:fd96258d940d 526 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 148:fd96258d940d 527 @{
Kojto 148:fd96258d940d 528 */
Kojto 148:fd96258d940d 529
Kojto 148:fd96258d940d 530 /**
Kojto 148:fd96258d940d 531 \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 148:fd96258d940d 532 */
Kojto 148:fd96258d940d 533 typedef struct
Kojto 148:fd96258d940d 534 {
Kojto 148:fd96258d940d 535 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 148:fd96258d940d 536 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 148:fd96258d940d 537 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 148:fd96258d940d 538 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 148:fd96258d940d 539 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 148:fd96258d940d 540 } MPU_Type;
Kojto 148:fd96258d940d 541
Kojto 148:fd96258d940d 542 /* MPU Type Register Definitions */
Kojto 148:fd96258d940d 543 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Kojto 148:fd96258d940d 544 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 148:fd96258d940d 545
Kojto 148:fd96258d940d 546 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Kojto 148:fd96258d940d 547 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 148:fd96258d940d 548
Kojto 148:fd96258d940d 549 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Kojto 148:fd96258d940d 550 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 148:fd96258d940d 551
Kojto 148:fd96258d940d 552 /* MPU Control Register Definitions */
Kojto 148:fd96258d940d 553 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 148:fd96258d940d 554 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 148:fd96258d940d 555
Kojto 148:fd96258d940d 556 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Kojto 148:fd96258d940d 557 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 148:fd96258d940d 558
Kojto 148:fd96258d940d 559 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Kojto 148:fd96258d940d 560 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 148:fd96258d940d 561
Kojto 148:fd96258d940d 562 /* MPU Region Number Register Definitions */
Kojto 148:fd96258d940d 563 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Kojto 148:fd96258d940d 564 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 148:fd96258d940d 565
Kojto 148:fd96258d940d 566 /* MPU Region Base Address Register Definitions */
Kojto 148:fd96258d940d 567 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
Kojto 148:fd96258d940d 568 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 148:fd96258d940d 569
Kojto 148:fd96258d940d 570 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Kojto 148:fd96258d940d 571 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 148:fd96258d940d 572
Kojto 148:fd96258d940d 573 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Kojto 148:fd96258d940d 574 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 148:fd96258d940d 575
Kojto 148:fd96258d940d 576 /* MPU Region Attribute and Size Register Definitions */
Kojto 148:fd96258d940d 577 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 148:fd96258d940d 578 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 148:fd96258d940d 579
Kojto 148:fd96258d940d 580 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Kojto 148:fd96258d940d 581 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 148:fd96258d940d 582
Kojto 148:fd96258d940d 583 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Kojto 148:fd96258d940d 584 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 148:fd96258d940d 585
Kojto 148:fd96258d940d 586 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Kojto 148:fd96258d940d 587 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 148:fd96258d940d 588
Kojto 148:fd96258d940d 589 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Kojto 148:fd96258d940d 590 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 148:fd96258d940d 591
Kojto 148:fd96258d940d 592 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Kojto 148:fd96258d940d 593 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 148:fd96258d940d 594
Kojto 148:fd96258d940d 595 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Kojto 148:fd96258d940d 596 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 148:fd96258d940d 597
Kojto 148:fd96258d940d 598 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Kojto 148:fd96258d940d 599 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 148:fd96258d940d 600
Kojto 148:fd96258d940d 601 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Kojto 148:fd96258d940d 602 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 148:fd96258d940d 603
Kojto 148:fd96258d940d 604 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Kojto 148:fd96258d940d 605 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 148:fd96258d940d 606
Kojto 148:fd96258d940d 607 /*@} end of group CMSIS_MPU */
Kojto 148:fd96258d940d 608 #endif
Kojto 148:fd96258d940d 609
Kojto 148:fd96258d940d 610
Kojto 148:fd96258d940d 611 /**
Kojto 148:fd96258d940d 612 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 613 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 148:fd96258d940d 614 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Kojto 148:fd96258d940d 615 Therefore they are not covered by the SC000 header file.
Kojto 148:fd96258d940d 616 @{
Kojto 148:fd96258d940d 617 */
Kojto 148:fd96258d940d 618 /*@} end of group CMSIS_CoreDebug */
Kojto 148:fd96258d940d 619
Kojto 148:fd96258d940d 620
Kojto 148:fd96258d940d 621 /**
Kojto 148:fd96258d940d 622 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 623 \defgroup CMSIS_core_bitfield Core register bit field macros
Kojto 148:fd96258d940d 624 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Kojto 148:fd96258d940d 625 @{
Kojto 148:fd96258d940d 626 */
Kojto 148:fd96258d940d 627
Kojto 148:fd96258d940d 628 /**
Kojto 148:fd96258d940d 629 \brief Mask and shift a bit field value for use in a register bit range.
Kojto 148:fd96258d940d 630 \param[in] field Name of the register bit field.
Kojto 148:fd96258d940d 631 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Kojto 148:fd96258d940d 632 \return Masked and shifted value.
Kojto 148:fd96258d940d 633 */
Kojto 148:fd96258d940d 634 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Kojto 148:fd96258d940d 635
Kojto 148:fd96258d940d 636 /**
Kojto 148:fd96258d940d 637 \brief Mask and shift a register value to extract a bit filed value.
Kojto 148:fd96258d940d 638 \param[in] field Name of the register bit field.
Kojto 148:fd96258d940d 639 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Kojto 148:fd96258d940d 640 \return Masked and shifted bit field value.
Kojto 148:fd96258d940d 641 */
Kojto 148:fd96258d940d 642 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Kojto 148:fd96258d940d 643
Kojto 148:fd96258d940d 644 /*@} end of group CMSIS_core_bitfield */
Kojto 148:fd96258d940d 645
Kojto 148:fd96258d940d 646
Kojto 148:fd96258d940d 647 /**
Kojto 148:fd96258d940d 648 \ingroup CMSIS_core_register
Kojto 148:fd96258d940d 649 \defgroup CMSIS_core_base Core Definitions
Kojto 148:fd96258d940d 650 \brief Definitions for base addresses, unions, and structures.
Kojto 148:fd96258d940d 651 @{
Kojto 148:fd96258d940d 652 */
Kojto 148:fd96258d940d 653
Kojto 148:fd96258d940d 654 /* Memory mapping of Core Hardware */
Kojto 148:fd96258d940d 655 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 148:fd96258d940d 656 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 148:fd96258d940d 657 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 148:fd96258d940d 658 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 148:fd96258d940d 659
Kojto 148:fd96258d940d 660 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 148:fd96258d940d 661 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 148:fd96258d940d 662 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 148:fd96258d940d 663 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 148:fd96258d940d 664
Kojto 148:fd96258d940d 665 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Kojto 148:fd96258d940d 666 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 148:fd96258d940d 667 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 148:fd96258d940d 668 #endif
Kojto 148:fd96258d940d 669
Kojto 148:fd96258d940d 670 /*@} */
Kojto 148:fd96258d940d 671
Kojto 148:fd96258d940d 672
Kojto 148:fd96258d940d 673
Kojto 148:fd96258d940d 674 /*******************************************************************************
Kojto 148:fd96258d940d 675 * Hardware Abstraction Layer
Kojto 148:fd96258d940d 676 Core Function Interface contains:
Kojto 148:fd96258d940d 677 - Core NVIC Functions
Kojto 148:fd96258d940d 678 - Core SysTick Functions
Kojto 148:fd96258d940d 679 - Core Register Access Functions
Kojto 148:fd96258d940d 680 ******************************************************************************/
Kojto 148:fd96258d940d 681 /**
Kojto 148:fd96258d940d 682 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 148:fd96258d940d 683 */
Kojto 148:fd96258d940d 684
Kojto 148:fd96258d940d 685
Kojto 148:fd96258d940d 686
Kojto 148:fd96258d940d 687 /* ########################## NVIC functions #################################### */
Kojto 148:fd96258d940d 688 /**
Kojto 148:fd96258d940d 689 \ingroup CMSIS_Core_FunctionInterface
Kojto 148:fd96258d940d 690 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 148:fd96258d940d 691 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 148:fd96258d940d 692 @{
Kojto 148:fd96258d940d 693 */
Kojto 148:fd96258d940d 694
Kojto 148:fd96258d940d 695 #ifdef CMSIS_NVIC_VIRTUAL
Kojto 148:fd96258d940d 696 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 697 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Kojto 148:fd96258d940d 698 #endif
Kojto 148:fd96258d940d 699 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 700 #else
Kojto 148:fd96258d940d 701 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
Kojto 148:fd96258d940d 702 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
Kojto 148:fd96258d940d 703 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Kojto 148:fd96258d940d 704 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Kojto 148:fd96258d940d 705 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Kojto 148:fd96258d940d 706 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Kojto 148:fd96258d940d 707 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Kojto 148:fd96258d940d 708 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Kojto 148:fd96258d940d 709 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
Kojto 148:fd96258d940d 710 #define NVIC_SetPriority __NVIC_SetPriority
Kojto 148:fd96258d940d 711 #define NVIC_GetPriority __NVIC_GetPriority
Kojto 148:fd96258d940d 712 #define NVIC_SystemReset __NVIC_SystemReset
Kojto 148:fd96258d940d 713 #endif /* CMSIS_NVIC_VIRTUAL */
Kojto 148:fd96258d940d 714
Kojto 148:fd96258d940d 715 #ifdef CMSIS_VECTAB_VIRTUAL
Kojto 148:fd96258d940d 716 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 717 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Kojto 148:fd96258d940d 718 #endif
Kojto 148:fd96258d940d 719 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto 148:fd96258d940d 720 #else
Kojto 148:fd96258d940d 721 #define NVIC_SetVector __NVIC_SetVector
Kojto 148:fd96258d940d 722 #define NVIC_GetVector __NVIC_GetVector
Kojto 148:fd96258d940d 723 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Kojto 148:fd96258d940d 724
Kojto 148:fd96258d940d 725 #define NVIC_USER_IRQ_OFFSET 16
Kojto 148:fd96258d940d 726
Kojto 148:fd96258d940d 727
Kojto 148:fd96258d940d 728 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 148:fd96258d940d 729 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 148:fd96258d940d 730 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 148:fd96258d940d 731 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 148:fd96258d940d 732 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 148:fd96258d940d 733
Kojto 148:fd96258d940d 734
Kojto 148:fd96258d940d 735 /**
Kojto 148:fd96258d940d 736 \brief Enable Interrupt
Kojto 148:fd96258d940d 737 \details Enables a device specific interrupt in the NVIC interrupt controller.
Kojto 148:fd96258d940d 738 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 739 \note IRQn must not be negative.
Kojto 148:fd96258d940d 740 */
Kojto 148:fd96258d940d 741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 742 {
Kojto 148:fd96258d940d 743 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 744 {
Kojto 148:fd96258d940d 745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 746 }
Kojto 148:fd96258d940d 747 }
Kojto 148:fd96258d940d 748
Kojto 148:fd96258d940d 749
Kojto 148:fd96258d940d 750 /**
Kojto 148:fd96258d940d 751 \brief Get Interrupt Enable status
Kojto 148:fd96258d940d 752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Kojto 148:fd96258d940d 753 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 754 \return 0 Interrupt is not enabled.
Kojto 148:fd96258d940d 755 \return 1 Interrupt is enabled.
Kojto 148:fd96258d940d 756 \note IRQn must not be negative.
Kojto 148:fd96258d940d 757 */
Kojto 148:fd96258d940d 758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 759 {
Kojto 148:fd96258d940d 760 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 761 {
Kojto 148:fd96258d940d 762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 148:fd96258d940d 763 }
Kojto 148:fd96258d940d 764 else
Kojto 148:fd96258d940d 765 {
Kojto 148:fd96258d940d 766 return(0U);
Kojto 148:fd96258d940d 767 }
Kojto 148:fd96258d940d 768 }
Kojto 148:fd96258d940d 769
Kojto 148:fd96258d940d 770
Kojto 148:fd96258d940d 771 /**
Kojto 148:fd96258d940d 772 \brief Disable Interrupt
Kojto 148:fd96258d940d 773 \details Disables a device specific interrupt in the NVIC interrupt controller.
Kojto 148:fd96258d940d 774 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 775 \note IRQn must not be negative.
Kojto 148:fd96258d940d 776 */
Kojto 148:fd96258d940d 777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 778 {
Kojto 148:fd96258d940d 779 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 780 {
Kojto 148:fd96258d940d 781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 782 __DSB();
Kojto 148:fd96258d940d 783 __ISB();
Kojto 148:fd96258d940d 784 }
Kojto 148:fd96258d940d 785 }
Kojto 148:fd96258d940d 786
Kojto 148:fd96258d940d 787
Kojto 148:fd96258d940d 788 /**
Kojto 148:fd96258d940d 789 \brief Get Pending Interrupt
Kojto 148:fd96258d940d 790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Kojto 148:fd96258d940d 791 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 792 \return 0 Interrupt status is not pending.
Kojto 148:fd96258d940d 793 \return 1 Interrupt status is pending.
Kojto 148:fd96258d940d 794 \note IRQn must not be negative.
Kojto 148:fd96258d940d 795 */
Kojto 148:fd96258d940d 796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 797 {
Kojto 148:fd96258d940d 798 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 799 {
Kojto 148:fd96258d940d 800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 148:fd96258d940d 801 }
Kojto 148:fd96258d940d 802 else
Kojto 148:fd96258d940d 803 {
Kojto 148:fd96258d940d 804 return(0U);
Kojto 148:fd96258d940d 805 }
Kojto 148:fd96258d940d 806 }
Kojto 148:fd96258d940d 807
Kojto 148:fd96258d940d 808
Kojto 148:fd96258d940d 809 /**
Kojto 148:fd96258d940d 810 \brief Set Pending Interrupt
Kojto 148:fd96258d940d 811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Kojto 148:fd96258d940d 812 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 813 \note IRQn must not be negative.
Kojto 148:fd96258d940d 814 */
Kojto 148:fd96258d940d 815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 816 {
Kojto 148:fd96258d940d 817 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 818 {
Kojto 148:fd96258d940d 819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 820 }
Kojto 148:fd96258d940d 821 }
Kojto 148:fd96258d940d 822
Kojto 148:fd96258d940d 823
Kojto 148:fd96258d940d 824 /**
Kojto 148:fd96258d940d 825 \brief Clear Pending Interrupt
Kojto 148:fd96258d940d 826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Kojto 148:fd96258d940d 827 \param [in] IRQn Device specific interrupt number.
Kojto 148:fd96258d940d 828 \note IRQn must not be negative.
Kojto 148:fd96258d940d 829 */
Kojto 148:fd96258d940d 830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 148:fd96258d940d 831 {
Kojto 148:fd96258d940d 832 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 833 {
Kojto 148:fd96258d940d 834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 148:fd96258d940d 835 }
Kojto 148:fd96258d940d 836 }
Kojto 148:fd96258d940d 837
Kojto 148:fd96258d940d 838
Kojto 148:fd96258d940d 839 /**
Kojto 148:fd96258d940d 840 \brief Set Interrupt Priority
Kojto 148:fd96258d940d 841 \details Sets the priority of a device specific interrupt or a processor exception.
Kojto 148:fd96258d940d 842 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 843 or negative to specify a processor exception.
Kojto 148:fd96258d940d 844 \param [in] IRQn Interrupt number.
Kojto 148:fd96258d940d 845 \param [in] priority Priority to set.
Kojto 148:fd96258d940d 846 \note The priority cannot be set for every processor exception.
Kojto 148:fd96258d940d 847 */
Kojto 148:fd96258d940d 848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 148:fd96258d940d 849 {
Kojto 148:fd96258d940d 850 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 851 {
Kojto 148:fd96258d940d 852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 148:fd96258d940d 853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 148:fd96258d940d 854 }
Kojto 148:fd96258d940d 855 else
Kojto 148:fd96258d940d 856 {
Kojto 148:fd96258d940d 857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 148:fd96258d940d 858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 148:fd96258d940d 859 }
Kojto 148:fd96258d940d 860 }
Kojto 148:fd96258d940d 861
Kojto 148:fd96258d940d 862
Kojto 148:fd96258d940d 863 /**
Kojto 148:fd96258d940d 864 \brief Get Interrupt Priority
Kojto 148:fd96258d940d 865 \details Reads the priority of a device specific interrupt or a processor exception.
Kojto 148:fd96258d940d 866 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 867 or negative to specify a processor exception.
Kojto 148:fd96258d940d 868 \param [in] IRQn Interrupt number.
Kojto 148:fd96258d940d 869 \return Interrupt Priority.
Kojto 148:fd96258d940d 870 Value is aligned automatically to the implemented priority bits of the microcontroller.
Kojto 148:fd96258d940d 871 */
Kojto 148:fd96258d940d 872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Kojto 148:fd96258d940d 873 {
Kojto 148:fd96258d940d 874
Kojto 148:fd96258d940d 875 if ((int32_t)(IRQn) >= 0)
Kojto 148:fd96258d940d 876 {
Kojto 148:fd96258d940d 877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Kojto 148:fd96258d940d 878 }
Kojto 148:fd96258d940d 879 else
Kojto 148:fd96258d940d 880 {
Kojto 148:fd96258d940d 881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Kojto 148:fd96258d940d 882 }
Kojto 148:fd96258d940d 883 }
Kojto 148:fd96258d940d 884
Kojto 148:fd96258d940d 885
Kojto 148:fd96258d940d 886 /**
Kojto 148:fd96258d940d 887 \brief Set Interrupt Vector
Kojto 148:fd96258d940d 888 \details Sets an interrupt vector in SRAM based interrupt vector table.
Kojto 148:fd96258d940d 889 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 890 or negative to specify a processor exception.
Kojto 148:fd96258d940d 891 VTOR must been relocated to SRAM before.
Kojto 148:fd96258d940d 892 \param [in] IRQn Interrupt number
Kojto 148:fd96258d940d 893 \param [in] vector Address of interrupt handler function
Kojto 148:fd96258d940d 894 */
Kojto 148:fd96258d940d 895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Kojto 148:fd96258d940d 896 {
Kojto 148:fd96258d940d 897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Kojto 148:fd96258d940d 898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Kojto 148:fd96258d940d 899 }
Kojto 148:fd96258d940d 900
Kojto 148:fd96258d940d 901
Kojto 148:fd96258d940d 902 /**
Kojto 148:fd96258d940d 903 \brief Get Interrupt Vector
Kojto 148:fd96258d940d 904 \details Reads an interrupt vector from interrupt vector table.
Kojto 148:fd96258d940d 905 The interrupt number can be positive to specify a device specific interrupt,
Kojto 148:fd96258d940d 906 or negative to specify a processor exception.
Kojto 148:fd96258d940d 907 \param [in] IRQn Interrupt number.
Kojto 148:fd96258d940d 908 \return Address of interrupt handler function
Kojto 148:fd96258d940d 909 */
Kojto 148:fd96258d940d 910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Kojto 148:fd96258d940d 911 {
Kojto 148:fd96258d940d 912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Kojto 148:fd96258d940d 913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Kojto 148:fd96258d940d 914 }
Kojto 148:fd96258d940d 915
Kojto 148:fd96258d940d 916
Kojto 148:fd96258d940d 917 /**
Kojto 148:fd96258d940d 918 \brief System Reset
Kojto 148:fd96258d940d 919 \details Initiates a system reset request to reset the MCU.
Kojto 148:fd96258d940d 920 */
Kojto 148:fd96258d940d 921 __STATIC_INLINE void __NVIC_SystemReset(void)
Kojto 148:fd96258d940d 922 {
Kojto 148:fd96258d940d 923 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 148:fd96258d940d 924 buffered write are completed before reset */
Kojto 148:fd96258d940d 925 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 148:fd96258d940d 926 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 148:fd96258d940d 927 __DSB(); /* Ensure completion of memory access */
Kojto 148:fd96258d940d 928
Kojto 148:fd96258d940d 929 for(;;) /* wait until reset */
Kojto 148:fd96258d940d 930 {
Kojto 148:fd96258d940d 931 __NOP();
Kojto 148:fd96258d940d 932 }
Kojto 148:fd96258d940d 933 }
Kojto 148:fd96258d940d 934
Kojto 148:fd96258d940d 935 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 148:fd96258d940d 936
Kojto 148:fd96258d940d 937
Kojto 148:fd96258d940d 938 /* ########################## FPU functions #################################### */
Kojto 148:fd96258d940d 939 /**
Kojto 148:fd96258d940d 940 \ingroup CMSIS_Core_FunctionInterface
Kojto 148:fd96258d940d 941 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto 148:fd96258d940d 942 \brief Function that provides FPU type.
Kojto 148:fd96258d940d 943 @{
Kojto 148:fd96258d940d 944 */
Kojto 148:fd96258d940d 945
Kojto 148:fd96258d940d 946 /**
Kojto 148:fd96258d940d 947 \brief get FPU type
Kojto 148:fd96258d940d 948 \details returns the FPU type
Kojto 148:fd96258d940d 949 \returns
Kojto 148:fd96258d940d 950 - \b 0: No FPU
Kojto 148:fd96258d940d 951 - \b 1: Single precision FPU
Kojto 148:fd96258d940d 952 - \b 2: Double + Single precision FPU
Kojto 148:fd96258d940d 953 */
Kojto 148:fd96258d940d 954 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto 148:fd96258d940d 955 {
Kojto 148:fd96258d940d 956 return 0U; /* No FPU */
Kojto 148:fd96258d940d 957 }
Kojto 148:fd96258d940d 958
Kojto 148:fd96258d940d 959
Kojto 148:fd96258d940d 960 /*@} end of CMSIS_Core_FpuFunctions */
Kojto 148:fd96258d940d 961
Kojto 148:fd96258d940d 962
Kojto 148:fd96258d940d 963
Kojto 148:fd96258d940d 964 /* ################################## SysTick function ############################################ */
Kojto 148:fd96258d940d 965 /**
Kojto 148:fd96258d940d 966 \ingroup CMSIS_Core_FunctionInterface
Kojto 148:fd96258d940d 967 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 148:fd96258d940d 968 \brief Functions that configure the System.
Kojto 148:fd96258d940d 969 @{
Kojto 148:fd96258d940d 970 */
Kojto 148:fd96258d940d 971
Kojto 148:fd96258d940d 972 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Kojto 148:fd96258d940d 973
Kojto 148:fd96258d940d 974 /**
Kojto 148:fd96258d940d 975 \brief System Tick Configuration
Kojto 148:fd96258d940d 976 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 148:fd96258d940d 977 Counter is in free running mode to generate periodic interrupts.
Kojto 148:fd96258d940d 978 \param [in] ticks Number of ticks between two interrupts.
Kojto 148:fd96258d940d 979 \return 0 Function succeeded.
Kojto 148:fd96258d940d 980 \return 1 Function failed.
Kojto 148:fd96258d940d 981 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 148:fd96258d940d 982 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 148:fd96258d940d 983 must contain a vendor-specific implementation of this function.
Kojto 148:fd96258d940d 984 */
Kojto 148:fd96258d940d 985 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 148:fd96258d940d 986 {
Kojto 148:fd96258d940d 987 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Kojto 148:fd96258d940d 988 {
Kojto 148:fd96258d940d 989 return (1UL); /* Reload value impossible */
Kojto 148:fd96258d940d 990 }
Kojto 148:fd96258d940d 991
Kojto 148:fd96258d940d 992 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 148:fd96258d940d 993 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 148:fd96258d940d 994 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 148:fd96258d940d 995 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 148:fd96258d940d 996 SysTick_CTRL_TICKINT_Msk |
Kojto 148:fd96258d940d 997 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 148:fd96258d940d 998 return (0UL); /* Function successful */
Kojto 148:fd96258d940d 999 }
Kojto 148:fd96258d940d 1000
Kojto 148:fd96258d940d 1001 #endif
Kojto 148:fd96258d940d 1002
Kojto 148:fd96258d940d 1003 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 148:fd96258d940d 1004
Kojto 148:fd96258d940d 1005
Kojto 148:fd96258d940d 1006
Kojto 148:fd96258d940d 1007
Kojto 148:fd96258d940d 1008 #ifdef __cplusplus
Kojto 148:fd96258d940d 1009 }
Kojto 148:fd96258d940d 1010 #endif
Kojto 148:fd96258d940d 1011
Kojto 148:fd96258d940d 1012 #endif /* __CORE_SC000_H_DEPENDANT */
Kojto 148:fd96258d940d 1013
Kojto 148:fd96258d940d 1014 #endif /* __CMSIS_GENERIC */