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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_VBLUNO51/core_cm0.h@151:675da3299148, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:46:57 2017 +0100
Revision:
151:675da3299148
Parent:
146:22da6e220af6
Child:
160:5571c4ff569f
Release 151 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 146:22da6e220af6 1 /**************************************************************************//**
AnnaBridge 146:22da6e220af6 2 * @file core_cm0.h
AnnaBridge 146:22da6e220af6 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
AnnaBridge 146:22da6e220af6 4 * @version V5.0.2
AnnaBridge 146:22da6e220af6 5 * @date 13. February 2017
AnnaBridge 146:22da6e220af6 6 ******************************************************************************/
AnnaBridge 146:22da6e220af6 7 /*
AnnaBridge 146:22da6e220af6 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 146:22da6e220af6 9 *
AnnaBridge 146:22da6e220af6 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 146:22da6e220af6 11 *
AnnaBridge 146:22da6e220af6 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 146:22da6e220af6 13 * not use this file except in compliance with the License.
AnnaBridge 146:22da6e220af6 14 * You may obtain a copy of the License at
AnnaBridge 146:22da6e220af6 15 *
AnnaBridge 146:22da6e220af6 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 146:22da6e220af6 17 *
AnnaBridge 146:22da6e220af6 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 146:22da6e220af6 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 146:22da6e220af6 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 146:22da6e220af6 21 * See the License for the specific language governing permissions and
AnnaBridge 146:22da6e220af6 22 * limitations under the License.
AnnaBridge 146:22da6e220af6 23 */
AnnaBridge 146:22da6e220af6 24
AnnaBridge 146:22da6e220af6 25 #if defined ( __ICCARM__ )
AnnaBridge 146:22da6e220af6 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 146:22da6e220af6 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 146:22da6e220af6 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 146:22da6e220af6 29 #endif
AnnaBridge 146:22da6e220af6 30
AnnaBridge 146:22da6e220af6 31 #ifndef __CORE_CM0_H_GENERIC
AnnaBridge 146:22da6e220af6 32 #define __CORE_CM0_H_GENERIC
AnnaBridge 146:22da6e220af6 33
AnnaBridge 146:22da6e220af6 34 #include <stdint.h>
AnnaBridge 146:22da6e220af6 35
AnnaBridge 146:22da6e220af6 36 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 37 extern "C" {
AnnaBridge 146:22da6e220af6 38 #endif
AnnaBridge 146:22da6e220af6 39
AnnaBridge 146:22da6e220af6 40 /**
AnnaBridge 146:22da6e220af6 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 146:22da6e220af6 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 146:22da6e220af6 43
AnnaBridge 146:22da6e220af6 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 146:22da6e220af6 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 146:22da6e220af6 46
AnnaBridge 146:22da6e220af6 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 146:22da6e220af6 48 Unions are used for effective representation of core registers.
AnnaBridge 146:22da6e220af6 49
AnnaBridge 146:22da6e220af6 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 146:22da6e220af6 51 Function-like macros are used to allow more efficient code.
AnnaBridge 146:22da6e220af6 52 */
AnnaBridge 146:22da6e220af6 53
AnnaBridge 146:22da6e220af6 54
AnnaBridge 146:22da6e220af6 55 /*******************************************************************************
AnnaBridge 146:22da6e220af6 56 * CMSIS definitions
AnnaBridge 146:22da6e220af6 57 ******************************************************************************/
AnnaBridge 146:22da6e220af6 58 /**
AnnaBridge 146:22da6e220af6 59 \ingroup Cortex_M0
AnnaBridge 146:22da6e220af6 60 @{
AnnaBridge 146:22da6e220af6 61 */
AnnaBridge 146:22da6e220af6 62
AnnaBridge 146:22da6e220af6 63 /* CMSIS CM0 definitions */
AnnaBridge 146:22da6e220af6 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 146:22da6e220af6 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 146:22da6e220af6 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 146:22da6e220af6 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 146:22da6e220af6 68
AnnaBridge 146:22da6e220af6 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 146:22da6e220af6 70
AnnaBridge 146:22da6e220af6 71 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 146:22da6e220af6 72 This core does not support an FPU at all
AnnaBridge 146:22da6e220af6 73 */
AnnaBridge 146:22da6e220af6 74 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 75
AnnaBridge 146:22da6e220af6 76 #if defined ( __CC_ARM )
AnnaBridge 146:22da6e220af6 77 #if defined __TARGET_FPU_VFP
AnnaBridge 146:22da6e220af6 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 79 #endif
AnnaBridge 146:22da6e220af6 80
AnnaBridge 146:22da6e220af6 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 146:22da6e220af6 82 #if defined __ARM_PCS_VFP
AnnaBridge 146:22da6e220af6 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 84 #endif
AnnaBridge 146:22da6e220af6 85
AnnaBridge 146:22da6e220af6 86 #elif defined ( __GNUC__ )
AnnaBridge 146:22da6e220af6 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 146:22da6e220af6 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 89 #endif
AnnaBridge 146:22da6e220af6 90
AnnaBridge 146:22da6e220af6 91 #elif defined ( __ICCARM__ )
AnnaBridge 146:22da6e220af6 92 #if defined __ARMVFP__
AnnaBridge 146:22da6e220af6 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 94 #endif
AnnaBridge 146:22da6e220af6 95
AnnaBridge 146:22da6e220af6 96 #elif defined ( __TI_ARM__ )
AnnaBridge 146:22da6e220af6 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 146:22da6e220af6 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 99 #endif
AnnaBridge 146:22da6e220af6 100
AnnaBridge 146:22da6e220af6 101 #elif defined ( __TASKING__ )
AnnaBridge 146:22da6e220af6 102 #if defined __FPU_VFP__
AnnaBridge 146:22da6e220af6 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 104 #endif
AnnaBridge 146:22da6e220af6 105
AnnaBridge 146:22da6e220af6 106 #elif defined ( __CSMC__ )
AnnaBridge 146:22da6e220af6 107 #if ( __CSMC__ & 0x400U)
AnnaBridge 146:22da6e220af6 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 109 #endif
AnnaBridge 146:22da6e220af6 110
AnnaBridge 146:22da6e220af6 111 #endif
AnnaBridge 146:22da6e220af6 112
AnnaBridge 146:22da6e220af6 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 146:22da6e220af6 114
AnnaBridge 146:22da6e220af6 115
AnnaBridge 146:22da6e220af6 116 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 117 }
AnnaBridge 146:22da6e220af6 118 #endif
AnnaBridge 146:22da6e220af6 119
AnnaBridge 146:22da6e220af6 120 #endif /* __CORE_CM0_H_GENERIC */
AnnaBridge 146:22da6e220af6 121
AnnaBridge 146:22da6e220af6 122 #ifndef __CMSIS_GENERIC
AnnaBridge 146:22da6e220af6 123
AnnaBridge 146:22da6e220af6 124 #ifndef __CORE_CM0_H_DEPENDANT
AnnaBridge 146:22da6e220af6 125 #define __CORE_CM0_H_DEPENDANT
AnnaBridge 146:22da6e220af6 126
AnnaBridge 146:22da6e220af6 127 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 128 extern "C" {
AnnaBridge 146:22da6e220af6 129 #endif
AnnaBridge 146:22da6e220af6 130
AnnaBridge 146:22da6e220af6 131 /* check device defines and use defaults */
AnnaBridge 146:22da6e220af6 132 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 146:22da6e220af6 133 #ifndef __CM0_REV
AnnaBridge 146:22da6e220af6 134 #define __CM0_REV 0x0000U
AnnaBridge 146:22da6e220af6 135 #warning "__CM0_REV not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 136 #endif
AnnaBridge 146:22da6e220af6 137
AnnaBridge 146:22da6e220af6 138 #ifndef __NVIC_PRIO_BITS
AnnaBridge 146:22da6e220af6 139 #define __NVIC_PRIO_BITS 2U
AnnaBridge 146:22da6e220af6 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 141 #endif
AnnaBridge 146:22da6e220af6 142
AnnaBridge 146:22da6e220af6 143 #ifndef __Vendor_SysTickConfig
AnnaBridge 146:22da6e220af6 144 #define __Vendor_SysTickConfig 0U
AnnaBridge 146:22da6e220af6 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 146 #endif
AnnaBridge 146:22da6e220af6 147 #endif
AnnaBridge 146:22da6e220af6 148
AnnaBridge 146:22da6e220af6 149 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 146:22da6e220af6 150 /**
AnnaBridge 146:22da6e220af6 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 146:22da6e220af6 152
AnnaBridge 146:22da6e220af6 153 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 146:22da6e220af6 154 \li to specify the access to peripheral variables.
AnnaBridge 146:22da6e220af6 155 \li for automatic generation of peripheral register debug information.
AnnaBridge 146:22da6e220af6 156 */
AnnaBridge 146:22da6e220af6 157 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 158 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 146:22da6e220af6 159 #else
AnnaBridge 146:22da6e220af6 160 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 146:22da6e220af6 161 #endif
AnnaBridge 146:22da6e220af6 162 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 146:22da6e220af6 163 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 146:22da6e220af6 164
AnnaBridge 146:22da6e220af6 165 /* following defines should be used for structure members */
AnnaBridge 146:22da6e220af6 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 146:22da6e220af6 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 146:22da6e220af6 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 146:22da6e220af6 169
AnnaBridge 146:22da6e220af6 170 /*@} end of group Cortex_M0 */
AnnaBridge 146:22da6e220af6 171
AnnaBridge 146:22da6e220af6 172
AnnaBridge 146:22da6e220af6 173
AnnaBridge 146:22da6e220af6 174 /*******************************************************************************
AnnaBridge 146:22da6e220af6 175 * Register Abstraction
AnnaBridge 146:22da6e220af6 176 Core Register contain:
AnnaBridge 146:22da6e220af6 177 - Core Register
AnnaBridge 146:22da6e220af6 178 - Core NVIC Register
AnnaBridge 146:22da6e220af6 179 - Core SCB Register
AnnaBridge 146:22da6e220af6 180 - Core SysTick Register
AnnaBridge 146:22da6e220af6 181 ******************************************************************************/
AnnaBridge 146:22da6e220af6 182 /**
AnnaBridge 146:22da6e220af6 183 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 146:22da6e220af6 184 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 146:22da6e220af6 185 */
AnnaBridge 146:22da6e220af6 186
AnnaBridge 146:22da6e220af6 187 /**
AnnaBridge 146:22da6e220af6 188 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 189 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 146:22da6e220af6 190 \brief Core Register type definitions.
AnnaBridge 146:22da6e220af6 191 @{
AnnaBridge 146:22da6e220af6 192 */
AnnaBridge 146:22da6e220af6 193
AnnaBridge 146:22da6e220af6 194 /**
AnnaBridge 146:22da6e220af6 195 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 146:22da6e220af6 196 */
AnnaBridge 146:22da6e220af6 197 typedef union
AnnaBridge 146:22da6e220af6 198 {
AnnaBridge 146:22da6e220af6 199 struct
AnnaBridge 146:22da6e220af6 200 {
AnnaBridge 146:22da6e220af6 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 146:22da6e220af6 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 146:22da6e220af6 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 146:22da6e220af6 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 146:22da6e220af6 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 146:22da6e220af6 206 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 207 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 208 } APSR_Type;
AnnaBridge 146:22da6e220af6 209
AnnaBridge 146:22da6e220af6 210 /* APSR Register Definitions */
AnnaBridge 146:22da6e220af6 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 146:22da6e220af6 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 146:22da6e220af6 213
AnnaBridge 146:22da6e220af6 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 146:22da6e220af6 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 146:22da6e220af6 216
AnnaBridge 146:22da6e220af6 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 146:22da6e220af6 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 146:22da6e220af6 219
AnnaBridge 146:22da6e220af6 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 146:22da6e220af6 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 146:22da6e220af6 222
AnnaBridge 146:22da6e220af6 223
AnnaBridge 146:22da6e220af6 224 /**
AnnaBridge 146:22da6e220af6 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 146:22da6e220af6 226 */
AnnaBridge 146:22da6e220af6 227 typedef union
AnnaBridge 146:22da6e220af6 228 {
AnnaBridge 146:22da6e220af6 229 struct
AnnaBridge 146:22da6e220af6 230 {
AnnaBridge 146:22da6e220af6 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 146:22da6e220af6 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 146:22da6e220af6 233 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 234 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 235 } IPSR_Type;
AnnaBridge 146:22da6e220af6 236
AnnaBridge 146:22da6e220af6 237 /* IPSR Register Definitions */
AnnaBridge 146:22da6e220af6 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 146:22da6e220af6 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 146:22da6e220af6 240
AnnaBridge 146:22da6e220af6 241
AnnaBridge 146:22da6e220af6 242 /**
AnnaBridge 146:22da6e220af6 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 146:22da6e220af6 244 */
AnnaBridge 146:22da6e220af6 245 typedef union
AnnaBridge 146:22da6e220af6 246 {
AnnaBridge 146:22da6e220af6 247 struct
AnnaBridge 146:22da6e220af6 248 {
AnnaBridge 146:22da6e220af6 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 146:22da6e220af6 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 146:22da6e220af6 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 146:22da6e220af6 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 146:22da6e220af6 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 146:22da6e220af6 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 146:22da6e220af6 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 146:22da6e220af6 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 146:22da6e220af6 257 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 258 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 259 } xPSR_Type;
AnnaBridge 146:22da6e220af6 260
AnnaBridge 146:22da6e220af6 261 /* xPSR Register Definitions */
AnnaBridge 146:22da6e220af6 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 146:22da6e220af6 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 146:22da6e220af6 264
AnnaBridge 146:22da6e220af6 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 146:22da6e220af6 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 146:22da6e220af6 267
AnnaBridge 146:22da6e220af6 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 146:22da6e220af6 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 146:22da6e220af6 270
AnnaBridge 146:22da6e220af6 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 146:22da6e220af6 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 146:22da6e220af6 273
AnnaBridge 146:22da6e220af6 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 146:22da6e220af6 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 146:22da6e220af6 276
AnnaBridge 146:22da6e220af6 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 146:22da6e220af6 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 146:22da6e220af6 279
AnnaBridge 146:22da6e220af6 280
AnnaBridge 146:22da6e220af6 281 /**
AnnaBridge 146:22da6e220af6 282 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 146:22da6e220af6 283 */
AnnaBridge 146:22da6e220af6 284 typedef union
AnnaBridge 146:22da6e220af6 285 {
AnnaBridge 146:22da6e220af6 286 struct
AnnaBridge 146:22da6e220af6 287 {
AnnaBridge 146:22da6e220af6 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 146:22da6e220af6 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 146:22da6e220af6 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 146:22da6e220af6 291 } b; /*!< Structure used for bit access */
AnnaBridge 146:22da6e220af6 292 uint32_t w; /*!< Type used for word access */
AnnaBridge 146:22da6e220af6 293 } CONTROL_Type;
AnnaBridge 146:22da6e220af6 294
AnnaBridge 146:22da6e220af6 295 /* CONTROL Register Definitions */
AnnaBridge 146:22da6e220af6 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 146:22da6e220af6 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 146:22da6e220af6 298
AnnaBridge 146:22da6e220af6 299 /*@} end of group CMSIS_CORE */
AnnaBridge 146:22da6e220af6 300
AnnaBridge 146:22da6e220af6 301
AnnaBridge 146:22da6e220af6 302 /**
AnnaBridge 146:22da6e220af6 303 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 146:22da6e220af6 305 \brief Type definitions for the NVIC Registers
AnnaBridge 146:22da6e220af6 306 @{
AnnaBridge 146:22da6e220af6 307 */
AnnaBridge 146:22da6e220af6 308
AnnaBridge 146:22da6e220af6 309 /**
AnnaBridge 146:22da6e220af6 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 146:22da6e220af6 311 */
AnnaBridge 146:22da6e220af6 312 typedef struct
AnnaBridge 146:22da6e220af6 313 {
AnnaBridge 146:22da6e220af6 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 146:22da6e220af6 315 uint32_t RESERVED0[31U];
AnnaBridge 146:22da6e220af6 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 146:22da6e220af6 317 uint32_t RSERVED1[31U];
AnnaBridge 146:22da6e220af6 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 146:22da6e220af6 319 uint32_t RESERVED2[31U];
AnnaBridge 146:22da6e220af6 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 146:22da6e220af6 321 uint32_t RESERVED3[31U];
AnnaBridge 146:22da6e220af6 322 uint32_t RESERVED4[64U];
AnnaBridge 146:22da6e220af6 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 146:22da6e220af6 324 } NVIC_Type;
AnnaBridge 146:22da6e220af6 325
AnnaBridge 146:22da6e220af6 326 /*@} end of group CMSIS_NVIC */
AnnaBridge 146:22da6e220af6 327
AnnaBridge 146:22da6e220af6 328
AnnaBridge 146:22da6e220af6 329 /**
AnnaBridge 146:22da6e220af6 330 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 331 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 146:22da6e220af6 332 \brief Type definitions for the System Control Block Registers
AnnaBridge 146:22da6e220af6 333 @{
AnnaBridge 146:22da6e220af6 334 */
AnnaBridge 146:22da6e220af6 335
AnnaBridge 146:22da6e220af6 336 /**
AnnaBridge 146:22da6e220af6 337 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 146:22da6e220af6 338 */
AnnaBridge 146:22da6e220af6 339 typedef struct
AnnaBridge 146:22da6e220af6 340 {
AnnaBridge 146:22da6e220af6 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 146:22da6e220af6 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 146:22da6e220af6 343 uint32_t RESERVED0;
AnnaBridge 146:22da6e220af6 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 146:22da6e220af6 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 146:22da6e220af6 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 146:22da6e220af6 347 uint32_t RESERVED1;
AnnaBridge 146:22da6e220af6 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 146:22da6e220af6 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 146:22da6e220af6 350 } SCB_Type;
AnnaBridge 146:22da6e220af6 351
AnnaBridge 146:22da6e220af6 352 /* SCB CPUID Register Definitions */
AnnaBridge 146:22da6e220af6 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 146:22da6e220af6 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 146:22da6e220af6 355
AnnaBridge 146:22da6e220af6 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 146:22da6e220af6 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 146:22da6e220af6 358
AnnaBridge 146:22da6e220af6 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 146:22da6e220af6 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 146:22da6e220af6 361
AnnaBridge 146:22da6e220af6 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 146:22da6e220af6 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 146:22da6e220af6 364
AnnaBridge 146:22da6e220af6 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 146:22da6e220af6 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 146:22da6e220af6 367
AnnaBridge 146:22da6e220af6 368 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 146:22da6e220af6 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 146:22da6e220af6 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 146:22da6e220af6 371
AnnaBridge 146:22da6e220af6 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 146:22da6e220af6 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 146:22da6e220af6 374
AnnaBridge 146:22da6e220af6 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 146:22da6e220af6 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 146:22da6e220af6 377
AnnaBridge 146:22da6e220af6 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 146:22da6e220af6 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 146:22da6e220af6 380
AnnaBridge 146:22da6e220af6 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 146:22da6e220af6 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 146:22da6e220af6 383
AnnaBridge 146:22da6e220af6 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 146:22da6e220af6 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 146:22da6e220af6 386
AnnaBridge 146:22da6e220af6 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 146:22da6e220af6 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 146:22da6e220af6 389
AnnaBridge 146:22da6e220af6 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 146:22da6e220af6 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 146:22da6e220af6 392
AnnaBridge 146:22da6e220af6 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 146:22da6e220af6 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 146:22da6e220af6 395
AnnaBridge 146:22da6e220af6 396 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 146:22da6e220af6 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 146:22da6e220af6 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 146:22da6e220af6 399
AnnaBridge 146:22da6e220af6 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 146:22da6e220af6 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 146:22da6e220af6 402
AnnaBridge 146:22da6e220af6 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 146:22da6e220af6 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 146:22da6e220af6 405
AnnaBridge 146:22da6e220af6 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 146:22da6e220af6 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 146:22da6e220af6 408
AnnaBridge 146:22da6e220af6 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 146:22da6e220af6 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 146:22da6e220af6 411
AnnaBridge 146:22da6e220af6 412 /* SCB System Control Register Definitions */
AnnaBridge 146:22da6e220af6 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 146:22da6e220af6 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 146:22da6e220af6 415
AnnaBridge 146:22da6e220af6 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 146:22da6e220af6 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 146:22da6e220af6 418
AnnaBridge 146:22da6e220af6 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 146:22da6e220af6 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 146:22da6e220af6 421
AnnaBridge 146:22da6e220af6 422 /* SCB Configuration Control Register Definitions */
AnnaBridge 146:22da6e220af6 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 146:22da6e220af6 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 146:22da6e220af6 425
AnnaBridge 146:22da6e220af6 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 146:22da6e220af6 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 146:22da6e220af6 428
AnnaBridge 146:22da6e220af6 429 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 146:22da6e220af6 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 146:22da6e220af6 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 146:22da6e220af6 432
AnnaBridge 146:22da6e220af6 433 /*@} end of group CMSIS_SCB */
AnnaBridge 146:22da6e220af6 434
AnnaBridge 146:22da6e220af6 435
AnnaBridge 146:22da6e220af6 436 /**
AnnaBridge 146:22da6e220af6 437 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 146:22da6e220af6 439 \brief Type definitions for the System Timer Registers.
AnnaBridge 146:22da6e220af6 440 @{
AnnaBridge 146:22da6e220af6 441 */
AnnaBridge 146:22da6e220af6 442
AnnaBridge 146:22da6e220af6 443 /**
AnnaBridge 146:22da6e220af6 444 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 146:22da6e220af6 445 */
AnnaBridge 146:22da6e220af6 446 typedef struct
AnnaBridge 146:22da6e220af6 447 {
AnnaBridge 146:22da6e220af6 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 146:22da6e220af6 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 146:22da6e220af6 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 146:22da6e220af6 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 146:22da6e220af6 452 } SysTick_Type;
AnnaBridge 146:22da6e220af6 453
AnnaBridge 146:22da6e220af6 454 /* SysTick Control / Status Register Definitions */
AnnaBridge 146:22da6e220af6 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 146:22da6e220af6 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 146:22da6e220af6 457
AnnaBridge 146:22da6e220af6 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 146:22da6e220af6 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 146:22da6e220af6 460
AnnaBridge 146:22da6e220af6 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 146:22da6e220af6 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 146:22da6e220af6 463
AnnaBridge 146:22da6e220af6 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 146:22da6e220af6 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 146:22da6e220af6 466
AnnaBridge 146:22da6e220af6 467 /* SysTick Reload Register Definitions */
AnnaBridge 146:22da6e220af6 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 146:22da6e220af6 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 146:22da6e220af6 470
AnnaBridge 146:22da6e220af6 471 /* SysTick Current Register Definitions */
AnnaBridge 146:22da6e220af6 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 146:22da6e220af6 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 146:22da6e220af6 474
AnnaBridge 146:22da6e220af6 475 /* SysTick Calibration Register Definitions */
AnnaBridge 146:22da6e220af6 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 146:22da6e220af6 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 146:22da6e220af6 478
AnnaBridge 146:22da6e220af6 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 146:22da6e220af6 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 146:22da6e220af6 481
AnnaBridge 146:22da6e220af6 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 146:22da6e220af6 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 146:22da6e220af6 484
AnnaBridge 146:22da6e220af6 485 /*@} end of group CMSIS_SysTick */
AnnaBridge 146:22da6e220af6 486
AnnaBridge 146:22da6e220af6 487
AnnaBridge 146:22da6e220af6 488 /**
AnnaBridge 146:22da6e220af6 489 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 146:22da6e220af6 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 146:22da6e220af6 492 Therefore they are not covered by the Cortex-M0 header file.
AnnaBridge 146:22da6e220af6 493 @{
AnnaBridge 146:22da6e220af6 494 */
AnnaBridge 146:22da6e220af6 495 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 146:22da6e220af6 496
AnnaBridge 146:22da6e220af6 497
AnnaBridge 146:22da6e220af6 498 /**
AnnaBridge 146:22da6e220af6 499 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 500 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 146:22da6e220af6 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 146:22da6e220af6 502 @{
AnnaBridge 146:22da6e220af6 503 */
AnnaBridge 146:22da6e220af6 504
AnnaBridge 146:22da6e220af6 505 /**
AnnaBridge 146:22da6e220af6 506 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 146:22da6e220af6 507 \param[in] field Name of the register bit field.
AnnaBridge 146:22da6e220af6 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 146:22da6e220af6 509 \return Masked and shifted value.
AnnaBridge 146:22da6e220af6 510 */
AnnaBridge 146:22da6e220af6 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 146:22da6e220af6 512
AnnaBridge 146:22da6e220af6 513 /**
AnnaBridge 146:22da6e220af6 514 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 146:22da6e220af6 515 \param[in] field Name of the register bit field.
AnnaBridge 146:22da6e220af6 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 146:22da6e220af6 517 \return Masked and shifted bit field value.
AnnaBridge 146:22da6e220af6 518 */
AnnaBridge 146:22da6e220af6 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 146:22da6e220af6 520
AnnaBridge 146:22da6e220af6 521 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 146:22da6e220af6 522
AnnaBridge 146:22da6e220af6 523
AnnaBridge 146:22da6e220af6 524 /**
AnnaBridge 146:22da6e220af6 525 \ingroup CMSIS_core_register
AnnaBridge 146:22da6e220af6 526 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 146:22da6e220af6 527 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 146:22da6e220af6 528 @{
AnnaBridge 146:22da6e220af6 529 */
AnnaBridge 146:22da6e220af6 530
AnnaBridge 146:22da6e220af6 531 /* Memory mapping of Core Hardware */
AnnaBridge 146:22da6e220af6 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 146:22da6e220af6 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 146:22da6e220af6 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 146:22da6e220af6 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 146:22da6e220af6 536
AnnaBridge 146:22da6e220af6 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 146:22da6e220af6 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 146:22da6e220af6 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 146:22da6e220af6 540
AnnaBridge 146:22da6e220af6 541
AnnaBridge 146:22da6e220af6 542 /*@} */
AnnaBridge 146:22da6e220af6 543
AnnaBridge 146:22da6e220af6 544
AnnaBridge 146:22da6e220af6 545
AnnaBridge 146:22da6e220af6 546 /*******************************************************************************
AnnaBridge 146:22da6e220af6 547 * Hardware Abstraction Layer
AnnaBridge 146:22da6e220af6 548 Core Function Interface contains:
AnnaBridge 146:22da6e220af6 549 - Core NVIC Functions
AnnaBridge 146:22da6e220af6 550 - Core SysTick Functions
AnnaBridge 146:22da6e220af6 551 - Core Register Access Functions
AnnaBridge 146:22da6e220af6 552 ******************************************************************************/
AnnaBridge 146:22da6e220af6 553 /**
AnnaBridge 146:22da6e220af6 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 146:22da6e220af6 555 */
AnnaBridge 146:22da6e220af6 556
AnnaBridge 146:22da6e220af6 557
AnnaBridge 146:22da6e220af6 558
AnnaBridge 146:22da6e220af6 559 /* ########################## NVIC functions #################################### */
AnnaBridge 146:22da6e220af6 560 /**
AnnaBridge 146:22da6e220af6 561 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 146:22da6e220af6 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 146:22da6e220af6 563 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 146:22da6e220af6 564 @{
AnnaBridge 146:22da6e220af6 565 */
AnnaBridge 146:22da6e220af6 566
AnnaBridge 146:22da6e220af6 567 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 146:22da6e220af6 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 146:22da6e220af6 570 #endif
AnnaBridge 146:22da6e220af6 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 572 #else
AnnaBridge 146:22da6e220af6 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 146:22da6e220af6 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 146:22da6e220af6 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 146:22da6e220af6 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 146:22da6e220af6 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 146:22da6e220af6 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 146:22da6e220af6 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 146:22da6e220af6 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 146:22da6e220af6 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
AnnaBridge 146:22da6e220af6 582 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 146:22da6e220af6 583 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 146:22da6e220af6 584 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 146:22da6e220af6 585 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 146:22da6e220af6 586
AnnaBridge 146:22da6e220af6 587 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 146:22da6e220af6 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 146:22da6e220af6 590 #endif
AnnaBridge 146:22da6e220af6 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 146:22da6e220af6 592 #else
AnnaBridge 146:22da6e220af6 593 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 146:22da6e220af6 594 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 146:22da6e220af6 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 146:22da6e220af6 596
AnnaBridge 146:22da6e220af6 597 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 146:22da6e220af6 598
AnnaBridge 146:22da6e220af6 599
AnnaBridge 146:22da6e220af6 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 146:22da6e220af6 601 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 146:22da6e220af6 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 146:22da6e220af6 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 146:22da6e220af6 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 146:22da6e220af6 605
AnnaBridge 146:22da6e220af6 606
AnnaBridge 146:22da6e220af6 607 /**
AnnaBridge 146:22da6e220af6 608 \brief Enable Interrupt
AnnaBridge 146:22da6e220af6 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 146:22da6e220af6 610 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 611 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 612 */
AnnaBridge 146:22da6e220af6 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 614 {
AnnaBridge 146:22da6e220af6 615 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 616 {
AnnaBridge 146:22da6e220af6 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 618 }
AnnaBridge 146:22da6e220af6 619 }
AnnaBridge 146:22da6e220af6 620
AnnaBridge 146:22da6e220af6 621
AnnaBridge 146:22da6e220af6 622 /**
AnnaBridge 146:22da6e220af6 623 \brief Get Interrupt Enable status
AnnaBridge 146:22da6e220af6 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 146:22da6e220af6 625 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 626 \return 0 Interrupt is not enabled.
AnnaBridge 146:22da6e220af6 627 \return 1 Interrupt is enabled.
AnnaBridge 146:22da6e220af6 628 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 629 */
AnnaBridge 146:22da6e220af6 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 631 {
AnnaBridge 146:22da6e220af6 632 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 633 {
AnnaBridge 146:22da6e220af6 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 146:22da6e220af6 635 }
AnnaBridge 146:22da6e220af6 636 else
AnnaBridge 146:22da6e220af6 637 {
AnnaBridge 146:22da6e220af6 638 return(0U);
AnnaBridge 146:22da6e220af6 639 }
AnnaBridge 146:22da6e220af6 640 }
AnnaBridge 146:22da6e220af6 641
AnnaBridge 146:22da6e220af6 642
AnnaBridge 146:22da6e220af6 643 /**
AnnaBridge 146:22da6e220af6 644 \brief Disable Interrupt
AnnaBridge 146:22da6e220af6 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 146:22da6e220af6 646 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 647 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 648 */
AnnaBridge 146:22da6e220af6 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 650 {
AnnaBridge 146:22da6e220af6 651 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 652 {
AnnaBridge 146:22da6e220af6 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 654 __DSB();
AnnaBridge 146:22da6e220af6 655 __ISB();
AnnaBridge 146:22da6e220af6 656 }
AnnaBridge 146:22da6e220af6 657 }
AnnaBridge 146:22da6e220af6 658
AnnaBridge 146:22da6e220af6 659
AnnaBridge 146:22da6e220af6 660 /**
AnnaBridge 146:22da6e220af6 661 \brief Get Pending Interrupt
AnnaBridge 146:22da6e220af6 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 146:22da6e220af6 663 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 664 \return 0 Interrupt status is not pending.
AnnaBridge 146:22da6e220af6 665 \return 1 Interrupt status is pending.
AnnaBridge 146:22da6e220af6 666 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 667 */
AnnaBridge 146:22da6e220af6 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 669 {
AnnaBridge 146:22da6e220af6 670 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 671 {
AnnaBridge 146:22da6e220af6 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 146:22da6e220af6 673 }
AnnaBridge 146:22da6e220af6 674 else
AnnaBridge 146:22da6e220af6 675 {
AnnaBridge 146:22da6e220af6 676 return(0U);
AnnaBridge 146:22da6e220af6 677 }
AnnaBridge 146:22da6e220af6 678 }
AnnaBridge 146:22da6e220af6 679
AnnaBridge 146:22da6e220af6 680
AnnaBridge 146:22da6e220af6 681 /**
AnnaBridge 146:22da6e220af6 682 \brief Set Pending Interrupt
AnnaBridge 146:22da6e220af6 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 146:22da6e220af6 684 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 685 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 686 */
AnnaBridge 146:22da6e220af6 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 688 {
AnnaBridge 146:22da6e220af6 689 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 690 {
AnnaBridge 146:22da6e220af6 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 692 }
AnnaBridge 146:22da6e220af6 693 }
AnnaBridge 146:22da6e220af6 694
AnnaBridge 146:22da6e220af6 695
AnnaBridge 146:22da6e220af6 696 /**
AnnaBridge 146:22da6e220af6 697 \brief Clear Pending Interrupt
AnnaBridge 146:22da6e220af6 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 146:22da6e220af6 699 \param [in] IRQn Device specific interrupt number.
AnnaBridge 146:22da6e220af6 700 \note IRQn must not be negative.
AnnaBridge 146:22da6e220af6 701 */
AnnaBridge 146:22da6e220af6 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 703 {
AnnaBridge 146:22da6e220af6 704 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 705 {
AnnaBridge 146:22da6e220af6 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 146:22da6e220af6 707 }
AnnaBridge 146:22da6e220af6 708 }
AnnaBridge 146:22da6e220af6 709
AnnaBridge 146:22da6e220af6 710
AnnaBridge 146:22da6e220af6 711 /**
AnnaBridge 146:22da6e220af6 712 \brief Set Interrupt Priority
AnnaBridge 146:22da6e220af6 713 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 146:22da6e220af6 714 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 715 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 716 \param [in] IRQn Interrupt number.
AnnaBridge 146:22da6e220af6 717 \param [in] priority Priority to set.
AnnaBridge 146:22da6e220af6 718 \note The priority cannot be set for every processor exception.
AnnaBridge 146:22da6e220af6 719 */
AnnaBridge 146:22da6e220af6 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 146:22da6e220af6 721 {
AnnaBridge 146:22da6e220af6 722 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 723 {
AnnaBridge 146:22da6e220af6 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 146:22da6e220af6 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 146:22da6e220af6 726 }
AnnaBridge 146:22da6e220af6 727 else
AnnaBridge 146:22da6e220af6 728 {
AnnaBridge 146:22da6e220af6 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 146:22da6e220af6 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 146:22da6e220af6 731 }
AnnaBridge 146:22da6e220af6 732 }
AnnaBridge 146:22da6e220af6 733
AnnaBridge 146:22da6e220af6 734
AnnaBridge 146:22da6e220af6 735 /**
AnnaBridge 146:22da6e220af6 736 \brief Get Interrupt Priority
AnnaBridge 146:22da6e220af6 737 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 146:22da6e220af6 738 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 739 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 740 \param [in] IRQn Interrupt number.
AnnaBridge 146:22da6e220af6 741 \return Interrupt Priority.
AnnaBridge 146:22da6e220af6 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 146:22da6e220af6 743 */
AnnaBridge 146:22da6e220af6 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 745 {
AnnaBridge 146:22da6e220af6 746
AnnaBridge 146:22da6e220af6 747 if ((int32_t)(IRQn) >= 0)
AnnaBridge 146:22da6e220af6 748 {
AnnaBridge 146:22da6e220af6 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 146:22da6e220af6 750 }
AnnaBridge 146:22da6e220af6 751 else
AnnaBridge 146:22da6e220af6 752 {
AnnaBridge 146:22da6e220af6 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 146:22da6e220af6 754 }
AnnaBridge 146:22da6e220af6 755 }
AnnaBridge 146:22da6e220af6 756
AnnaBridge 146:22da6e220af6 757
AnnaBridge 146:22da6e220af6 758 /**
AnnaBridge 146:22da6e220af6 759 \brief Set Interrupt Vector
AnnaBridge 146:22da6e220af6 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 146:22da6e220af6 761 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 762 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 763 Address 0 must be mapped to SRAM.
AnnaBridge 146:22da6e220af6 764 \param [in] IRQn Interrupt number
AnnaBridge 146:22da6e220af6 765 \param [in] vector Address of interrupt handler function
AnnaBridge 146:22da6e220af6 766 */
AnnaBridge 146:22da6e220af6 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 146:22da6e220af6 768 {
AnnaBridge 146:22da6e220af6 769 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 146:22da6e220af6 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 146:22da6e220af6 771 }
AnnaBridge 146:22da6e220af6 772
AnnaBridge 146:22da6e220af6 773
AnnaBridge 146:22da6e220af6 774 /**
AnnaBridge 146:22da6e220af6 775 \brief Get Interrupt Vector
AnnaBridge 146:22da6e220af6 776 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 146:22da6e220af6 777 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 146:22da6e220af6 778 or negative to specify a processor exception.
AnnaBridge 146:22da6e220af6 779 \param [in] IRQn Interrupt number.
AnnaBridge 146:22da6e220af6 780 \return Address of interrupt handler function
AnnaBridge 146:22da6e220af6 781 */
AnnaBridge 146:22da6e220af6 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 783 {
AnnaBridge 146:22da6e220af6 784 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 146:22da6e220af6 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 146:22da6e220af6 786 }
AnnaBridge 146:22da6e220af6 787
AnnaBridge 146:22da6e220af6 788
AnnaBridge 146:22da6e220af6 789 /**
AnnaBridge 146:22da6e220af6 790 \brief System Reset
AnnaBridge 146:22da6e220af6 791 \details Initiates a system reset request to reset the MCU.
AnnaBridge 146:22da6e220af6 792 */
AnnaBridge 146:22da6e220af6 793 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 146:22da6e220af6 794 {
AnnaBridge 146:22da6e220af6 795 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 146:22da6e220af6 796 buffered write are completed before reset */
AnnaBridge 146:22da6e220af6 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 146:22da6e220af6 798 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 146:22da6e220af6 799 __DSB(); /* Ensure completion of memory access */
AnnaBridge 146:22da6e220af6 800
AnnaBridge 146:22da6e220af6 801 for(;;) /* wait until reset */
AnnaBridge 146:22da6e220af6 802 {
AnnaBridge 146:22da6e220af6 803 __NOP();
AnnaBridge 146:22da6e220af6 804 }
AnnaBridge 146:22da6e220af6 805 }
AnnaBridge 146:22da6e220af6 806
AnnaBridge 146:22da6e220af6 807 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 146:22da6e220af6 808
AnnaBridge 146:22da6e220af6 809
AnnaBridge 146:22da6e220af6 810 /* ########################## FPU functions #################################### */
AnnaBridge 146:22da6e220af6 811 /**
AnnaBridge 146:22da6e220af6 812 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 146:22da6e220af6 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 146:22da6e220af6 814 \brief Function that provides FPU type.
AnnaBridge 146:22da6e220af6 815 @{
AnnaBridge 146:22da6e220af6 816 */
AnnaBridge 146:22da6e220af6 817
AnnaBridge 146:22da6e220af6 818 /**
AnnaBridge 146:22da6e220af6 819 \brief get FPU type
AnnaBridge 146:22da6e220af6 820 \details returns the FPU type
AnnaBridge 146:22da6e220af6 821 \returns
AnnaBridge 146:22da6e220af6 822 - \b 0: No FPU
AnnaBridge 146:22da6e220af6 823 - \b 1: Single precision FPU
AnnaBridge 146:22da6e220af6 824 - \b 2: Double + Single precision FPU
AnnaBridge 146:22da6e220af6 825 */
AnnaBridge 146:22da6e220af6 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 146:22da6e220af6 827 {
AnnaBridge 146:22da6e220af6 828 return 0U; /* No FPU */
AnnaBridge 146:22da6e220af6 829 }
AnnaBridge 146:22da6e220af6 830
AnnaBridge 146:22da6e220af6 831
AnnaBridge 146:22da6e220af6 832 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 146:22da6e220af6 833
AnnaBridge 146:22da6e220af6 834
AnnaBridge 146:22da6e220af6 835
AnnaBridge 146:22da6e220af6 836 /* ################################## SysTick function ############################################ */
AnnaBridge 146:22da6e220af6 837 /**
AnnaBridge 146:22da6e220af6 838 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 146:22da6e220af6 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 146:22da6e220af6 840 \brief Functions that configure the System.
AnnaBridge 146:22da6e220af6 841 @{
AnnaBridge 146:22da6e220af6 842 */
AnnaBridge 146:22da6e220af6 843
AnnaBridge 146:22da6e220af6 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 146:22da6e220af6 845
AnnaBridge 146:22da6e220af6 846 /**
AnnaBridge 146:22da6e220af6 847 \brief System Tick Configuration
AnnaBridge 146:22da6e220af6 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 146:22da6e220af6 849 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 146:22da6e220af6 850 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 146:22da6e220af6 851 \return 0 Function succeeded.
AnnaBridge 146:22da6e220af6 852 \return 1 Function failed.
AnnaBridge 146:22da6e220af6 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 146:22da6e220af6 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 146:22da6e220af6 855 must contain a vendor-specific implementation of this function.
AnnaBridge 146:22da6e220af6 856 */
AnnaBridge 146:22da6e220af6 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 146:22da6e220af6 858 {
AnnaBridge 146:22da6e220af6 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 146:22da6e220af6 860 {
AnnaBridge 146:22da6e220af6 861 return (1UL); /* Reload value impossible */
AnnaBridge 146:22da6e220af6 862 }
AnnaBridge 146:22da6e220af6 863
AnnaBridge 146:22da6e220af6 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 146:22da6e220af6 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 146:22da6e220af6 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 146:22da6e220af6 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 146:22da6e220af6 868 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 146:22da6e220af6 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 146:22da6e220af6 870 return (0UL); /* Function successful */
AnnaBridge 146:22da6e220af6 871 }
AnnaBridge 146:22da6e220af6 872
AnnaBridge 146:22da6e220af6 873 #endif
AnnaBridge 146:22da6e220af6 874
AnnaBridge 146:22da6e220af6 875 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 146:22da6e220af6 876
AnnaBridge 146:22da6e220af6 877
AnnaBridge 146:22da6e220af6 878
AnnaBridge 146:22da6e220af6 879
AnnaBridge 146:22da6e220af6 880 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 881 }
AnnaBridge 146:22da6e220af6 882 #endif
AnnaBridge 146:22da6e220af6 883
AnnaBridge 146:22da6e220af6 884 #endif /* __CORE_CM0_H_DEPENDANT */
AnnaBridge 146:22da6e220af6 885
AnnaBridge 146:22da6e220af6 886 #endif /* __CMSIS_GENERIC */