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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_VBLUNO51/core_ca.h@151:675da3299148, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:46:57 2017 +0100
Revision:
151:675da3299148
Parent:
146:22da6e220af6 
Release 151 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 146:22da6e220af6 1 /**************************************************************************//**
AnnaBridge 146:22da6e220af6 2 * @file core_ca.h
AnnaBridge 146:22da6e220af6 3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
AnnaBridge 146:22da6e220af6 4 * @version V1.00
AnnaBridge 146:22da6e220af6 5 * @date 22. Feb 2017
AnnaBridge 146:22da6e220af6 6 ******************************************************************************/
AnnaBridge 146:22da6e220af6 7 /*
AnnaBridge 146:22da6e220af6 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 146:22da6e220af6 9 *
AnnaBridge 146:22da6e220af6 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 146:22da6e220af6 11 *
AnnaBridge 146:22da6e220af6 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 146:22da6e220af6 13 * not use this file except in compliance with the License.
AnnaBridge 146:22da6e220af6 14 * You may obtain a copy of the License at
AnnaBridge 146:22da6e220af6 15 *
AnnaBridge 146:22da6e220af6 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 146:22da6e220af6 17 *
AnnaBridge 146:22da6e220af6 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 146:22da6e220af6 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 146:22da6e220af6 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 146:22da6e220af6 21 * See the License for the specific language governing permissions and
AnnaBridge 146:22da6e220af6 22 * limitations under the License.
AnnaBridge 146:22da6e220af6 23 */
AnnaBridge 146:22da6e220af6 24
AnnaBridge 146:22da6e220af6 25 #if defined ( __ICCARM__ )
AnnaBridge 146:22da6e220af6 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 146:22da6e220af6 27 #endif
AnnaBridge 146:22da6e220af6 28
AnnaBridge 146:22da6e220af6 29 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 30 extern "C" {
AnnaBridge 146:22da6e220af6 31 #endif
AnnaBridge 146:22da6e220af6 32
AnnaBridge 146:22da6e220af6 33 #ifndef __CORE_CA_H_GENERIC
AnnaBridge 146:22da6e220af6 34 #define __CORE_CA_H_GENERIC
AnnaBridge 146:22da6e220af6 35
AnnaBridge 146:22da6e220af6 36
AnnaBridge 146:22da6e220af6 37 /*******************************************************************************
AnnaBridge 146:22da6e220af6 38 * CMSIS definitions
AnnaBridge 146:22da6e220af6 39 ******************************************************************************/
AnnaBridge 146:22da6e220af6 40
AnnaBridge 146:22da6e220af6 41 /* CMSIS CA definitions */
AnnaBridge 146:22da6e220af6 42 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS HAL main version */
AnnaBridge 146:22da6e220af6 43 #define __CA_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS HAL sub version */
AnnaBridge 146:22da6e220af6 44 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 146:22da6e220af6 45 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS HAL version number */
AnnaBridge 146:22da6e220af6 46
AnnaBridge 146:22da6e220af6 47 #if defined ( __CC_ARM )
AnnaBridge 146:22da6e220af6 48 #if defined __TARGET_FPU_VFP
AnnaBridge 146:22da6e220af6 49 #if (__FPU_PRESENT == 1)
AnnaBridge 146:22da6e220af6 50 #define __FPU_USED 1U
AnnaBridge 146:22da6e220af6 51 #else
AnnaBridge 146:22da6e220af6 52 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 53 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 54 #endif
AnnaBridge 146:22da6e220af6 55 #else
AnnaBridge 146:22da6e220af6 56 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 57 #endif
AnnaBridge 146:22da6e220af6 58
AnnaBridge 146:22da6e220af6 59 #elif defined ( __ICCARM__ )
AnnaBridge 146:22da6e220af6 60 #if defined __ARMVFP__
AnnaBridge 146:22da6e220af6 61 #if (__FPU_PRESENT == 1)
AnnaBridge 146:22da6e220af6 62 #define __FPU_USED 1U
AnnaBridge 146:22da6e220af6 63 #else
AnnaBridge 146:22da6e220af6 64 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 65 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 66 #endif
AnnaBridge 146:22da6e220af6 67 #else
AnnaBridge 146:22da6e220af6 68 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 69 #endif
AnnaBridge 146:22da6e220af6 70
AnnaBridge 146:22da6e220af6 71 #elif defined ( __TMS470__ )
AnnaBridge 146:22da6e220af6 72 #if defined __TI_VFP_SUPPORT__
AnnaBridge 146:22da6e220af6 73 #if (__FPU_PRESENT == 1)
AnnaBridge 146:22da6e220af6 74 #define __FPU_USED 1U
AnnaBridge 146:22da6e220af6 75 #else
AnnaBridge 146:22da6e220af6 76 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 77 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 78 #endif
AnnaBridge 146:22da6e220af6 79 #else
AnnaBridge 146:22da6e220af6 80 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 81 #endif
AnnaBridge 146:22da6e220af6 82
AnnaBridge 146:22da6e220af6 83 #elif defined ( __GNUC__ )
AnnaBridge 146:22da6e220af6 84 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 146:22da6e220af6 85 #if (__FPU_PRESENT == 1)
AnnaBridge 146:22da6e220af6 86 #define __FPU_USED 1U
AnnaBridge 146:22da6e220af6 87 #else
AnnaBridge 146:22da6e220af6 88 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 89 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 90 #endif
AnnaBridge 146:22da6e220af6 91 #else
AnnaBridge 146:22da6e220af6 92 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 93 #endif
AnnaBridge 146:22da6e220af6 94
AnnaBridge 146:22da6e220af6 95 #elif defined ( __TASKING__ )
AnnaBridge 146:22da6e220af6 96 #if defined __FPU_VFP__
AnnaBridge 146:22da6e220af6 97 #if (__FPU_PRESENT == 1)
AnnaBridge 146:22da6e220af6 98 #define __FPU_USED 1U
AnnaBridge 146:22da6e220af6 99 #else
AnnaBridge 146:22da6e220af6 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 146:22da6e220af6 101 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 102 #endif
AnnaBridge 146:22da6e220af6 103 #else
AnnaBridge 146:22da6e220af6 104 #define __FPU_USED 0U
AnnaBridge 146:22da6e220af6 105 #endif
AnnaBridge 146:22da6e220af6 106 #endif
AnnaBridge 146:22da6e220af6 107
AnnaBridge 146:22da6e220af6 108 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 146:22da6e220af6 109
AnnaBridge 146:22da6e220af6 110 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 111 }
AnnaBridge 146:22da6e220af6 112 #endif
AnnaBridge 146:22da6e220af6 113
AnnaBridge 146:22da6e220af6 114 #endif /* __CORE_CA_H_GENERIC */
AnnaBridge 146:22da6e220af6 115
AnnaBridge 146:22da6e220af6 116 #ifndef __CMSIS_GENERIC
AnnaBridge 146:22da6e220af6 117
AnnaBridge 146:22da6e220af6 118 #ifndef __CORE_CA_H_DEPENDANT
AnnaBridge 146:22da6e220af6 119 #define __CORE_CA_H_DEPENDANT
AnnaBridge 146:22da6e220af6 120
AnnaBridge 146:22da6e220af6 121 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 122 extern "C" {
AnnaBridge 146:22da6e220af6 123 #endif
AnnaBridge 146:22da6e220af6 124
AnnaBridge 146:22da6e220af6 125 /* check device defines and use defaults */
AnnaBridge 146:22da6e220af6 126 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 146:22da6e220af6 127 #ifndef __CA_REV
AnnaBridge 146:22da6e220af6 128 #define __CA_REV 0x0000U
AnnaBridge 146:22da6e220af6 129 #warning "__CA_REV not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 130 #endif
AnnaBridge 146:22da6e220af6 131
AnnaBridge 146:22da6e220af6 132 #ifndef __FPU_PRESENT
AnnaBridge 146:22da6e220af6 133 #define __FPU_PRESENT 0U
AnnaBridge 146:22da6e220af6 134 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 135 #endif
AnnaBridge 146:22da6e220af6 136
AnnaBridge 146:22da6e220af6 137 #ifndef __MPU_PRESENT
AnnaBridge 146:22da6e220af6 138 #define __MPU_PRESENT 0U
AnnaBridge 146:22da6e220af6 139 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 140 #endif
AnnaBridge 146:22da6e220af6 141
AnnaBridge 146:22da6e220af6 142 #ifndef __GIC_PRESENT
AnnaBridge 146:22da6e220af6 143 #define __GIC_PRESENT 1U
AnnaBridge 146:22da6e220af6 144 #warning "__GIC_PRESENT not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 145 #endif
AnnaBridge 146:22da6e220af6 146
AnnaBridge 146:22da6e220af6 147 #ifndef __TIM_PRESENT
AnnaBridge 146:22da6e220af6 148 #define __TIM_PRESENT 1U
AnnaBridge 146:22da6e220af6 149 #warning "__TIM_PRESENT not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 150 #endif
AnnaBridge 146:22da6e220af6 151
AnnaBridge 146:22da6e220af6 152 #ifndef __L2C_PRESENT
AnnaBridge 146:22da6e220af6 153 #define __L2C_PRESENT 0U
AnnaBridge 146:22da6e220af6 154 #warning "__L2C_PRESENT not defined in device header file; using default!"
AnnaBridge 146:22da6e220af6 155 #endif
AnnaBridge 146:22da6e220af6 156 #endif
AnnaBridge 146:22da6e220af6 157
AnnaBridge 146:22da6e220af6 158 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 146:22da6e220af6 159 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 160 #define __I volatile /*!< \brief Defines 'read only' permissions */
AnnaBridge 146:22da6e220af6 161 #else
AnnaBridge 146:22da6e220af6 162 #define __I volatile const /*!< \brief Defines 'read only' permissions */
AnnaBridge 146:22da6e220af6 163 #endif
AnnaBridge 146:22da6e220af6 164 #define __O volatile /*!< \brief Defines 'write only' permissions */
AnnaBridge 146:22da6e220af6 165 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
AnnaBridge 146:22da6e220af6 166
AnnaBridge 146:22da6e220af6 167 /* following defines should be used for structure members */
AnnaBridge 146:22da6e220af6 168 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
AnnaBridge 146:22da6e220af6 169 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
AnnaBridge 146:22da6e220af6 170 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
AnnaBridge 146:22da6e220af6 171
AnnaBridge 146:22da6e220af6 172
AnnaBridge 146:22da6e220af6 173 /*******************************************************************************
AnnaBridge 146:22da6e220af6 174 * Register Abstraction
AnnaBridge 146:22da6e220af6 175 Core Register contain:
AnnaBridge 146:22da6e220af6 176 - CPSR
AnnaBridge 146:22da6e220af6 177 - CP15 Registers
AnnaBridge 146:22da6e220af6 178 - L2C-310 Cache Controller
AnnaBridge 146:22da6e220af6 179 - Generic Interrupt Controller Distributor
AnnaBridge 146:22da6e220af6 180 - Generic Interrupt Controller Interface
AnnaBridge 146:22da6e220af6 181 ******************************************************************************/
AnnaBridge 146:22da6e220af6 182
AnnaBridge 146:22da6e220af6 183 /* Core Register CPSR */
AnnaBridge 146:22da6e220af6 184 typedef union
AnnaBridge 146:22da6e220af6 185 {
AnnaBridge 146:22da6e220af6 186 struct
AnnaBridge 146:22da6e220af6 187 {
AnnaBridge 146:22da6e220af6 188 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
AnnaBridge 146:22da6e220af6 189 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
AnnaBridge 146:22da6e220af6 190 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
AnnaBridge 146:22da6e220af6 191 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
AnnaBridge 146:22da6e220af6 192 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
AnnaBridge 146:22da6e220af6 193 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
AnnaBridge 146:22da6e220af6 194 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
AnnaBridge 146:22da6e220af6 195 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
AnnaBridge 146:22da6e220af6 196 uint32_t _reserved0:4; /*!< \brief bit: 20..23 Reserved */
AnnaBridge 146:22da6e220af6 197 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
AnnaBridge 146:22da6e220af6 198 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
AnnaBridge 146:22da6e220af6 199 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
AnnaBridge 146:22da6e220af6 200 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
AnnaBridge 146:22da6e220af6 201 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
AnnaBridge 146:22da6e220af6 202 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
AnnaBridge 146:22da6e220af6 203 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
AnnaBridge 146:22da6e220af6 204 } b; /*!< \brief Structure used for bit access */
AnnaBridge 146:22da6e220af6 205 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 146:22da6e220af6 206 } CPSR_Type;
AnnaBridge 146:22da6e220af6 207
AnnaBridge 146:22da6e220af6 208 /* CPSR Register Definitions */
AnnaBridge 146:22da6e220af6 209 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
AnnaBridge 146:22da6e220af6 210 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
AnnaBridge 146:22da6e220af6 211
AnnaBridge 146:22da6e220af6 212 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
AnnaBridge 146:22da6e220af6 213 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
AnnaBridge 146:22da6e220af6 214
AnnaBridge 146:22da6e220af6 215 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
AnnaBridge 146:22da6e220af6 216 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
AnnaBridge 146:22da6e220af6 217
AnnaBridge 146:22da6e220af6 218 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
AnnaBridge 146:22da6e220af6 219 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
AnnaBridge 146:22da6e220af6 220
AnnaBridge 146:22da6e220af6 221 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
AnnaBridge 146:22da6e220af6 222 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
AnnaBridge 146:22da6e220af6 223
AnnaBridge 146:22da6e220af6 224 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
AnnaBridge 146:22da6e220af6 225 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
AnnaBridge 146:22da6e220af6 226
AnnaBridge 146:22da6e220af6 227 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
AnnaBridge 146:22da6e220af6 228 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
AnnaBridge 146:22da6e220af6 229
AnnaBridge 146:22da6e220af6 230 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
AnnaBridge 146:22da6e220af6 231 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
AnnaBridge 146:22da6e220af6 232
AnnaBridge 146:22da6e220af6 233 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
AnnaBridge 146:22da6e220af6 234 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
AnnaBridge 146:22da6e220af6 235
AnnaBridge 146:22da6e220af6 236 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
AnnaBridge 146:22da6e220af6 237 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
AnnaBridge 146:22da6e220af6 238
AnnaBridge 146:22da6e220af6 239 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
AnnaBridge 146:22da6e220af6 240 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
AnnaBridge 146:22da6e220af6 241
AnnaBridge 146:22da6e220af6 242 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
AnnaBridge 146:22da6e220af6 243 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
AnnaBridge 146:22da6e220af6 244
AnnaBridge 146:22da6e220af6 245 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
AnnaBridge 146:22da6e220af6 246 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
AnnaBridge 146:22da6e220af6 247
AnnaBridge 146:22da6e220af6 248 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
AnnaBridge 146:22da6e220af6 249 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
AnnaBridge 146:22da6e220af6 250
AnnaBridge 146:22da6e220af6 251 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
AnnaBridge 146:22da6e220af6 252 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
AnnaBridge 146:22da6e220af6 253
AnnaBridge 146:22da6e220af6 254 /* CP15 Register SCTLR */
AnnaBridge 146:22da6e220af6 255 typedef union
AnnaBridge 146:22da6e220af6 256 {
AnnaBridge 146:22da6e220af6 257 struct
AnnaBridge 146:22da6e220af6 258 {
AnnaBridge 146:22da6e220af6 259 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
AnnaBridge 146:22da6e220af6 260 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
AnnaBridge 146:22da6e220af6 261 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
AnnaBridge 146:22da6e220af6 262 uint32_t _reserved0:2; /*!< \brief bit: 3.. 4 Reserved */
AnnaBridge 146:22da6e220af6 263 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
AnnaBridge 146:22da6e220af6 264 uint32_t _reserved1:1; /*!< \brief bit: 6 Reserved */
AnnaBridge 146:22da6e220af6 265 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
AnnaBridge 146:22da6e220af6 266 uint32_t _reserved2:2; /*!< \brief bit: 8.. 9 Reserved */
AnnaBridge 146:22da6e220af6 267 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
AnnaBridge 146:22da6e220af6 268 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
AnnaBridge 146:22da6e220af6 269 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
AnnaBridge 146:22da6e220af6 270 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
AnnaBridge 146:22da6e220af6 271 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
AnnaBridge 146:22da6e220af6 272 uint32_t _reserved3:2; /*!< \brief bit:15..16 Reserved */
AnnaBridge 146:22da6e220af6 273 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
AnnaBridge 146:22da6e220af6 274 uint32_t _reserved4:1; /*!< \brief bit: 18 Reserved */
AnnaBridge 146:22da6e220af6 275 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
AnnaBridge 146:22da6e220af6 276 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
AnnaBridge 146:22da6e220af6 277 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
AnnaBridge 146:22da6e220af6 278 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
AnnaBridge 146:22da6e220af6 279 uint32_t _reserved5:1; /*!< \brief bit: 23 Reserved */
AnnaBridge 146:22da6e220af6 280 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
AnnaBridge 146:22da6e220af6 281 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
AnnaBridge 146:22da6e220af6 282 uint32_t _reserved6:1; /*!< \brief bit: 26 Reserved */
AnnaBridge 146:22da6e220af6 283 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
AnnaBridge 146:22da6e220af6 284 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
AnnaBridge 146:22da6e220af6 285 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
AnnaBridge 146:22da6e220af6 286 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
AnnaBridge 146:22da6e220af6 287 uint32_t _reserved7:1; /*!< \brief bit: 31 Reserved */
AnnaBridge 146:22da6e220af6 288 } b; /*!< \brief Structure used for bit access */
AnnaBridge 146:22da6e220af6 289 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 146:22da6e220af6 290 } SCTLR_Type;
AnnaBridge 146:22da6e220af6 291
AnnaBridge 146:22da6e220af6 292 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
AnnaBridge 146:22da6e220af6 293 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
AnnaBridge 146:22da6e220af6 294
AnnaBridge 146:22da6e220af6 295 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
AnnaBridge 146:22da6e220af6 296 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
AnnaBridge 146:22da6e220af6 297
AnnaBridge 146:22da6e220af6 298 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
AnnaBridge 146:22da6e220af6 299 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
AnnaBridge 146:22da6e220af6 300
AnnaBridge 146:22da6e220af6 301 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
AnnaBridge 146:22da6e220af6 302 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
AnnaBridge 146:22da6e220af6 303
AnnaBridge 146:22da6e220af6 304 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
AnnaBridge 146:22da6e220af6 305 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
AnnaBridge 146:22da6e220af6 306
AnnaBridge 146:22da6e220af6 307 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
AnnaBridge 146:22da6e220af6 308 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
AnnaBridge 146:22da6e220af6 309
AnnaBridge 146:22da6e220af6 310 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
AnnaBridge 146:22da6e220af6 311 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
AnnaBridge 146:22da6e220af6 312
AnnaBridge 146:22da6e220af6 313 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
AnnaBridge 146:22da6e220af6 314 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
AnnaBridge 146:22da6e220af6 315
AnnaBridge 146:22da6e220af6 316 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
AnnaBridge 146:22da6e220af6 317 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
AnnaBridge 146:22da6e220af6 318
AnnaBridge 146:22da6e220af6 319 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
AnnaBridge 146:22da6e220af6 320 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
AnnaBridge 146:22da6e220af6 321
AnnaBridge 146:22da6e220af6 322 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
AnnaBridge 146:22da6e220af6 323 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
AnnaBridge 146:22da6e220af6 324
AnnaBridge 146:22da6e220af6 325 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
AnnaBridge 146:22da6e220af6 326 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
AnnaBridge 146:22da6e220af6 327
AnnaBridge 146:22da6e220af6 328 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
AnnaBridge 146:22da6e220af6 329 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
AnnaBridge 146:22da6e220af6 330
AnnaBridge 146:22da6e220af6 331 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
AnnaBridge 146:22da6e220af6 332 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
AnnaBridge 146:22da6e220af6 333
AnnaBridge 146:22da6e220af6 334 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
AnnaBridge 146:22da6e220af6 335 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
AnnaBridge 146:22da6e220af6 336
AnnaBridge 146:22da6e220af6 337 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
AnnaBridge 146:22da6e220af6 338 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
AnnaBridge 146:22da6e220af6 339
AnnaBridge 146:22da6e220af6 340 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
AnnaBridge 146:22da6e220af6 341 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
AnnaBridge 146:22da6e220af6 342
AnnaBridge 146:22da6e220af6 343 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
AnnaBridge 146:22da6e220af6 344 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
AnnaBridge 146:22da6e220af6 345
AnnaBridge 146:22da6e220af6 346 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
AnnaBridge 146:22da6e220af6 347 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
AnnaBridge 146:22da6e220af6 348
AnnaBridge 146:22da6e220af6 349 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
AnnaBridge 146:22da6e220af6 350 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
AnnaBridge 146:22da6e220af6 351
AnnaBridge 146:22da6e220af6 352 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
AnnaBridge 146:22da6e220af6 353 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
AnnaBridge 146:22da6e220af6 354
AnnaBridge 146:22da6e220af6 355 /* CP15 Register CPACR */
AnnaBridge 146:22da6e220af6 356 typedef union
AnnaBridge 146:22da6e220af6 357 {
AnnaBridge 146:22da6e220af6 358 struct
AnnaBridge 146:22da6e220af6 359 {
AnnaBridge 146:22da6e220af6 360 uint32_t _reserved0:20; /*!< \brief bit: 0..19 Reserved */
AnnaBridge 146:22da6e220af6 361 uint32_t cp10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
AnnaBridge 146:22da6e220af6 362 uint32_t cp11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
AnnaBridge 146:22da6e220af6 363 uint32_t _reserved1:6; /*!< \brief bit:24..29 Reserved */
AnnaBridge 146:22da6e220af6 364 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
AnnaBridge 146:22da6e220af6 365 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
AnnaBridge 146:22da6e220af6 366 } b; /*!< \brief Structure used for bit access */
AnnaBridge 146:22da6e220af6 367 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 146:22da6e220af6 368 } CPACR_Type;
AnnaBridge 146:22da6e220af6 369
AnnaBridge 146:22da6e220af6 370 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
AnnaBridge 146:22da6e220af6 371 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
AnnaBridge 146:22da6e220af6 372
AnnaBridge 146:22da6e220af6 373 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
AnnaBridge 146:22da6e220af6 374 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
AnnaBridge 146:22da6e220af6 375
AnnaBridge 146:22da6e220af6 376 #define CPACR_cp11_Pos 22U /*!< \brief CPACR: cp11 Position */
AnnaBridge 146:22da6e220af6 377 #define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< \brief CPACR: cp11 Mask */
AnnaBridge 146:22da6e220af6 378
AnnaBridge 146:22da6e220af6 379 #define CPACR_cp10_Pos 20U /*!< \brief CPACR: cp10 Position */
AnnaBridge 146:22da6e220af6 380 #define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< \brief CPACR: cp10 Mask */
AnnaBridge 146:22da6e220af6 381
AnnaBridge 146:22da6e220af6 382 /* CP15 Register DFSR */
AnnaBridge 146:22da6e220af6 383 typedef union
AnnaBridge 146:22da6e220af6 384 {
AnnaBridge 146:22da6e220af6 385 struct
AnnaBridge 146:22da6e220af6 386 {
AnnaBridge 146:22da6e220af6 387 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
AnnaBridge 146:22da6e220af6 388 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
AnnaBridge 146:22da6e220af6 389 uint32_t _reserved0:2; /*!< \brief bit: 8.. 9 Reserved */
AnnaBridge 146:22da6e220af6 390 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
AnnaBridge 146:22da6e220af6 391 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
AnnaBridge 146:22da6e220af6 392 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 146:22da6e220af6 393 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
AnnaBridge 146:22da6e220af6 394 uint32_t _reserved1:18; /*!< \brief bit:14..31 Reserved */
AnnaBridge 146:22da6e220af6 395 } b; /*!< \brief Structure used for bit access */
AnnaBridge 146:22da6e220af6 396 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 146:22da6e220af6 397 } DFSR_Type;
AnnaBridge 146:22da6e220af6 398
AnnaBridge 146:22da6e220af6 399 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
AnnaBridge 146:22da6e220af6 400 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
AnnaBridge 146:22da6e220af6 401
AnnaBridge 146:22da6e220af6 402 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
AnnaBridge 146:22da6e220af6 403 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
AnnaBridge 146:22da6e220af6 404
AnnaBridge 146:22da6e220af6 405 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
AnnaBridge 146:22da6e220af6 406 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
AnnaBridge 146:22da6e220af6 407
AnnaBridge 146:22da6e220af6 408 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
AnnaBridge 146:22da6e220af6 409 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
AnnaBridge 146:22da6e220af6 410
AnnaBridge 146:22da6e220af6 411 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
AnnaBridge 146:22da6e220af6 412 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
AnnaBridge 146:22da6e220af6 413
AnnaBridge 146:22da6e220af6 414 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
AnnaBridge 146:22da6e220af6 415 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
AnnaBridge 146:22da6e220af6 416
AnnaBridge 146:22da6e220af6 417 /* CP15 Register IFSR */
AnnaBridge 146:22da6e220af6 418 typedef union
AnnaBridge 146:22da6e220af6 419 {
AnnaBridge 146:22da6e220af6 420 struct
AnnaBridge 146:22da6e220af6 421 {
AnnaBridge 146:22da6e220af6 422 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
AnnaBridge 146:22da6e220af6 423 uint32_t _reserved0:6; /*!< \brief bit: 4.. 9 Reserved */
AnnaBridge 146:22da6e220af6 424 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
AnnaBridge 146:22da6e220af6 425 uint32_t _reserved1:1; /*!< \brief bit: 11 Reserved */
AnnaBridge 146:22da6e220af6 426 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
AnnaBridge 146:22da6e220af6 427 uint32_t _reserved2:19; /*!< \brief bit:13..31 Reserved */
AnnaBridge 146:22da6e220af6 428 } b; /*!< \brief Structure used for bit access */
AnnaBridge 146:22da6e220af6 429 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 146:22da6e220af6 430 } IFSR_Type;
AnnaBridge 146:22da6e220af6 431
AnnaBridge 146:22da6e220af6 432 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
AnnaBridge 146:22da6e220af6 433 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
AnnaBridge 146:22da6e220af6 434
AnnaBridge 146:22da6e220af6 435 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
AnnaBridge 146:22da6e220af6 436 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
AnnaBridge 146:22da6e220af6 437
AnnaBridge 146:22da6e220af6 438 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
AnnaBridge 146:22da6e220af6 439 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
AnnaBridge 146:22da6e220af6 440
AnnaBridge 146:22da6e220af6 441 /* CP15 Register ISR */
AnnaBridge 146:22da6e220af6 442 typedef union
AnnaBridge 146:22da6e220af6 443 {
AnnaBridge 146:22da6e220af6 444 struct
AnnaBridge 146:22da6e220af6 445 {
AnnaBridge 146:22da6e220af6 446 uint32_t _reserved0:6; /*!< \brief bit: 0.. 5 Reserved */
AnnaBridge 146:22da6e220af6 447 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
AnnaBridge 146:22da6e220af6 448 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
AnnaBridge 146:22da6e220af6 449 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
AnnaBridge 146:22da6e220af6 450 uint32_t _reserved1:23; /*!< \brief bit:14..31 Reserved */
AnnaBridge 146:22da6e220af6 451 } b; /*!< \brief Structure used for bit access */
AnnaBridge 146:22da6e220af6 452 uint32_t w; /*!< \brief Type used for word access */
AnnaBridge 146:22da6e220af6 453 } ISR_Type;
AnnaBridge 146:22da6e220af6 454
AnnaBridge 146:22da6e220af6 455 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
AnnaBridge 146:22da6e220af6 456 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
AnnaBridge 146:22da6e220af6 457
AnnaBridge 146:22da6e220af6 458 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
AnnaBridge 146:22da6e220af6 459 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
AnnaBridge 146:22da6e220af6 460
AnnaBridge 146:22da6e220af6 461 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
AnnaBridge 146:22da6e220af6 462 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
AnnaBridge 146:22da6e220af6 463
AnnaBridge 146:22da6e220af6 464
AnnaBridge 146:22da6e220af6 465 /**
AnnaBridge 146:22da6e220af6 466 \brief Union type to access the L2C_310 Cache Controller.
AnnaBridge 146:22da6e220af6 467 */
AnnaBridge 146:22da6e220af6 468 #if (__L2C_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 469 typedef struct
AnnaBridge 146:22da6e220af6 470 {
AnnaBridge 146:22da6e220af6 471 __I uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 Cache ID Register */
AnnaBridge 146:22da6e220af6 472 __I uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 Cache Type Register */
AnnaBridge 146:22da6e220af6 473 uint32_t RESERVED0[0x3e];
AnnaBridge 146:22da6e220af6 474 __IO uint32_t CONTROL; /*!< \brief Offset: 0x0100 Control Register */
AnnaBridge 146:22da6e220af6 475 __IO uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 Auxiliary Control */
AnnaBridge 146:22da6e220af6 476 uint32_t RESERVED1[0x3e];
AnnaBridge 146:22da6e220af6 477 __IO uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 Event Counter Control */
AnnaBridge 146:22da6e220af6 478 __IO uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 Event Counter 1 Configuration */
AnnaBridge 146:22da6e220af6 479 __IO uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 Event Counter 1 Configuration */
AnnaBridge 146:22da6e220af6 480 uint32_t RESERVED2[0x2];
AnnaBridge 146:22da6e220af6 481 __IO uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 Interrupt Mask */
AnnaBridge 146:22da6e220af6 482 __I uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 Masked Interrupt Status */
AnnaBridge 146:22da6e220af6 483 __I uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c Raw Interrupt Status */
AnnaBridge 146:22da6e220af6 484 __O uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 Interrupt Clear */
AnnaBridge 146:22da6e220af6 485 uint32_t RESERVED3[0x143];
AnnaBridge 146:22da6e220af6 486 __IO uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 Cache Sync */
AnnaBridge 146:22da6e220af6 487 uint32_t RESERVED4[0xf];
AnnaBridge 146:22da6e220af6 488 __IO uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 Invalidate Line By PA */
AnnaBridge 146:22da6e220af6 489 uint32_t RESERVED6[2];
AnnaBridge 146:22da6e220af6 490 __IO uint32_t INV_WAY; /*!< \brief Offset: 0x077c Invalidate by Way */
AnnaBridge 146:22da6e220af6 491 uint32_t RESERVED5[0xc];
AnnaBridge 146:22da6e220af6 492 __IO uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 Clean Line by PA */
AnnaBridge 146:22da6e220af6 493 uint32_t RESERVED7[1];
AnnaBridge 146:22da6e220af6 494 __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 Clean Line by Index/Way */
AnnaBridge 146:22da6e220af6 495 __IO uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc Clean by Way */
AnnaBridge 146:22da6e220af6 496 uint32_t RESERVED8[0xc];
AnnaBridge 146:22da6e220af6 497 __IO uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA */
AnnaBridge 146:22da6e220af6 498 uint32_t RESERVED9[1];
AnnaBridge 146:22da6e220af6 499 __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
AnnaBridge 146:22da6e220af6 500 __IO uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc Clean and Invalidate by Way */
AnnaBridge 146:22da6e220af6 501 uint32_t RESERVED10[0x40];
AnnaBridge 146:22da6e220af6 502 __IO uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 Data Lockdown 0 by Way */
AnnaBridge 146:22da6e220af6 503 __IO uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way */
AnnaBridge 146:22da6e220af6 504 __IO uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 Data Lockdown 1 by Way */
AnnaBridge 146:22da6e220af6 505 __IO uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c Instruction Lockdown 1 by Way */
AnnaBridge 146:22da6e220af6 506 __IO uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 Data Lockdown 2 by Way */
AnnaBridge 146:22da6e220af6 507 __IO uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way */
AnnaBridge 146:22da6e220af6 508 __IO uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 Data Lockdown 3 by Way */
AnnaBridge 146:22da6e220af6 509 __IO uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c Instruction Lockdown 3 by Way */
AnnaBridge 146:22da6e220af6 510 __IO uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 Data Lockdown 4 by Way */
AnnaBridge 146:22da6e220af6 511 __IO uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way */
AnnaBridge 146:22da6e220af6 512 __IO uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 Data Lockdown 5 by Way */
AnnaBridge 146:22da6e220af6 513 __IO uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c Instruction Lockdown 5 by Way */
AnnaBridge 146:22da6e220af6 514 __IO uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 Data Lockdown 5 by Way */
AnnaBridge 146:22da6e220af6 515 __IO uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way */
AnnaBridge 146:22da6e220af6 516 __IO uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 Data Lockdown 6 by Way */
AnnaBridge 146:22da6e220af6 517 __IO uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c Instruction Lockdown 6 by Way */
AnnaBridge 146:22da6e220af6 518 uint32_t RESERVED11[0x4];
AnnaBridge 146:22da6e220af6 519 __IO uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 Lockdown by Line Enable */
AnnaBridge 146:22da6e220af6 520 __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 Unlock All Lines by Way */
AnnaBridge 146:22da6e220af6 521 uint32_t RESERVED12[0xaa];
AnnaBridge 146:22da6e220af6 522 __IO uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 Address Filtering Start */
AnnaBridge 146:22da6e220af6 523 __IO uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 Address Filtering End */
AnnaBridge 146:22da6e220af6 524 uint32_t RESERVED13[0xce];
AnnaBridge 146:22da6e220af6 525 __IO uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 Debug Control Register */
AnnaBridge 146:22da6e220af6 526 } L2C_310_TypeDef;
AnnaBridge 146:22da6e220af6 527
AnnaBridge 146:22da6e220af6 528 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 Declaration */
AnnaBridge 146:22da6e220af6 529 #endif
AnnaBridge 146:22da6e220af6 530
AnnaBridge 146:22da6e220af6 531 #if (__GIC_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 532 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
AnnaBridge 146:22da6e220af6 533 */
AnnaBridge 146:22da6e220af6 534 typedef struct
AnnaBridge 146:22da6e220af6 535 {
AnnaBridge 146:22da6e220af6 536 __IO uint32_t ICDDCR;
AnnaBridge 146:22da6e220af6 537 __I uint32_t ICDICTR;
AnnaBridge 146:22da6e220af6 538 __I uint32_t ICDIIDR;
AnnaBridge 146:22da6e220af6 539 uint32_t RESERVED0[29];
AnnaBridge 146:22da6e220af6 540 __IO uint32_t ICDISR[32];
AnnaBridge 146:22da6e220af6 541 __IO uint32_t ICDISER[32];
AnnaBridge 146:22da6e220af6 542 __IO uint32_t ICDICER[32];
AnnaBridge 146:22da6e220af6 543 __IO uint32_t ICDISPR[32];
AnnaBridge 146:22da6e220af6 544 __IO uint32_t ICDICPR[32];
AnnaBridge 146:22da6e220af6 545 __I uint32_t ICDABR[32];
AnnaBridge 146:22da6e220af6 546 uint32_t RESERVED1[32];
AnnaBridge 146:22da6e220af6 547 __IO uint32_t ICDIPR[256];
AnnaBridge 146:22da6e220af6 548 __IO uint32_t ICDIPTR[256];
AnnaBridge 146:22da6e220af6 549 __IO uint32_t ICDICFR[64];
AnnaBridge 146:22da6e220af6 550 uint32_t RESERVED2[128];
AnnaBridge 146:22da6e220af6 551 __IO uint32_t ICDSGIR;
AnnaBridge 146:22da6e220af6 552 } GICDistributor_Type;
AnnaBridge 146:22da6e220af6 553
AnnaBridge 146:22da6e220af6 554 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
AnnaBridge 146:22da6e220af6 555
AnnaBridge 146:22da6e220af6 556 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
AnnaBridge 146:22da6e220af6 557 */
AnnaBridge 146:22da6e220af6 558 typedef struct
AnnaBridge 146:22da6e220af6 559 {
AnnaBridge 146:22da6e220af6 560 __IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register
AnnaBridge 146:22da6e220af6 561 __IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register
AnnaBridge 146:22da6e220af6 562 __IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register
AnnaBridge 146:22da6e220af6 563 __I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register
AnnaBridge 146:22da6e220af6 564 __IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register
AnnaBridge 146:22da6e220af6 565 __I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register
AnnaBridge 146:22da6e220af6 566 __I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register
AnnaBridge 146:22da6e220af6 567 __IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register
AnnaBridge 146:22da6e220af6 568 uint32_t RESERVED[55];
AnnaBridge 146:22da6e220af6 569 __I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register
AnnaBridge 146:22da6e220af6 570 } GICInterface_Type;
AnnaBridge 146:22da6e220af6 571
AnnaBridge 146:22da6e220af6 572 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
AnnaBridge 146:22da6e220af6 573 #endif
AnnaBridge 146:22da6e220af6 574
AnnaBridge 146:22da6e220af6 575 #if (__TIM_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 576 #if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
AnnaBridge 146:22da6e220af6 577 /** \brief Structure type to access the Private Timer
AnnaBridge 146:22da6e220af6 578 */
AnnaBridge 146:22da6e220af6 579 typedef struct
AnnaBridge 146:22da6e220af6 580 {
AnnaBridge 146:22da6e220af6 581 __IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register
AnnaBridge 146:22da6e220af6 582 __IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register
AnnaBridge 146:22da6e220af6 583 __IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register
AnnaBridge 146:22da6e220af6 584 __IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register
AnnaBridge 146:22da6e220af6 585 uint32_t RESERVED[8];
AnnaBridge 146:22da6e220af6 586 __IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register
AnnaBridge 146:22da6e220af6 587 __IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register
AnnaBridge 146:22da6e220af6 588 __IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register
AnnaBridge 146:22da6e220af6 589 __IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register
AnnaBridge 146:22da6e220af6 590 __IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register
AnnaBridge 146:22da6e220af6 591 __I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register
AnnaBridge 146:22da6e220af6 592 } Timer_Type;
AnnaBridge 146:22da6e220af6 593 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer configuration struct */
AnnaBridge 146:22da6e220af6 594 #endif
AnnaBridge 146:22da6e220af6 595 #endif
AnnaBridge 146:22da6e220af6 596
AnnaBridge 146:22da6e220af6 597 /*******************************************************************************
AnnaBridge 146:22da6e220af6 598 * Hardware Abstraction Layer
AnnaBridge 146:22da6e220af6 599 Core Function Interface contains:
AnnaBridge 146:22da6e220af6 600 - L1 Cache Functions
AnnaBridge 146:22da6e220af6 601 - L2C-310 Cache Controller Functions
AnnaBridge 146:22da6e220af6 602 - PL1 Timer Functions
AnnaBridge 146:22da6e220af6 603 - GIC Functions
AnnaBridge 146:22da6e220af6 604 - MMU Functions
AnnaBridge 146:22da6e220af6 605 ******************************************************************************/
AnnaBridge 146:22da6e220af6 606
AnnaBridge 146:22da6e220af6 607 /* ########################## L1 Cache functions ################################# */
AnnaBridge 146:22da6e220af6 608
AnnaBridge 146:22da6e220af6 609 /** \brief Enable Caches
AnnaBridge 146:22da6e220af6 610
AnnaBridge 146:22da6e220af6 611 Enable Caches
AnnaBridge 146:22da6e220af6 612 */
AnnaBridge 146:22da6e220af6 613 __STATIC_INLINE void L1C_EnableCaches(void) {
AnnaBridge 146:22da6e220af6 614 // Set I bit 12 to enable I Cache
AnnaBridge 146:22da6e220af6 615 // Set C bit 2 to enable D Cache
AnnaBridge 146:22da6e220af6 616 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 146:22da6e220af6 617 }
AnnaBridge 146:22da6e220af6 618
AnnaBridge 146:22da6e220af6 619 /** \brief Disable Caches
AnnaBridge 146:22da6e220af6 620
AnnaBridge 146:22da6e220af6 621 Disable Caches
AnnaBridge 146:22da6e220af6 622 */
AnnaBridge 146:22da6e220af6 623 __STATIC_INLINE void L1C_DisableCaches(void) {
AnnaBridge 146:22da6e220af6 624 // Clear I bit 12 to disable I Cache
AnnaBridge 146:22da6e220af6 625 // Clear C bit 2 to disable D Cache
AnnaBridge 146:22da6e220af6 626 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 146:22da6e220af6 627 __ISB();
AnnaBridge 146:22da6e220af6 628 }
AnnaBridge 146:22da6e220af6 629
AnnaBridge 146:22da6e220af6 630 /** \brief Enable BTAC
AnnaBridge 146:22da6e220af6 631
AnnaBridge 146:22da6e220af6 632 Enable BTAC
AnnaBridge 146:22da6e220af6 633 */
AnnaBridge 146:22da6e220af6 634 __STATIC_INLINE void L1C_EnableBTAC(void) {
AnnaBridge 146:22da6e220af6 635 // Set Z bit 11 to enable branch prediction
AnnaBridge 146:22da6e220af6 636 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 146:22da6e220af6 637 __ISB();
AnnaBridge 146:22da6e220af6 638 }
AnnaBridge 146:22da6e220af6 639
AnnaBridge 146:22da6e220af6 640 /** \brief Disable BTAC
AnnaBridge 146:22da6e220af6 641
AnnaBridge 146:22da6e220af6 642 Disable BTAC
AnnaBridge 146:22da6e220af6 643 */
AnnaBridge 146:22da6e220af6 644 __STATIC_INLINE void L1C_DisableBTAC(void) {
AnnaBridge 146:22da6e220af6 645 // Clear Z bit 11 to disable branch prediction
AnnaBridge 146:22da6e220af6 646 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 146:22da6e220af6 647 }
AnnaBridge 146:22da6e220af6 648
AnnaBridge 146:22da6e220af6 649 /** \brief Invalidate entire branch predictor array
AnnaBridge 146:22da6e220af6 650
AnnaBridge 146:22da6e220af6 651 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 146:22da6e220af6 652 */
AnnaBridge 146:22da6e220af6 653
AnnaBridge 146:22da6e220af6 654 __STATIC_INLINE void L1C_InvalidateBTAC(void) {
AnnaBridge 146:22da6e220af6 655 __set_BPIALL(0);
AnnaBridge 146:22da6e220af6 656 __DSB(); //ensure completion of the invalidation
AnnaBridge 146:22da6e220af6 657 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 146:22da6e220af6 658 }
AnnaBridge 146:22da6e220af6 659
AnnaBridge 146:22da6e220af6 660 /** \brief Invalidate the whole I$
AnnaBridge 146:22da6e220af6 661
AnnaBridge 146:22da6e220af6 662 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 146:22da6e220af6 663 */
AnnaBridge 146:22da6e220af6 664 __STATIC_INLINE void L1C_InvalidateICacheAll(void) {
AnnaBridge 146:22da6e220af6 665 __set_ICIALLU(0);
AnnaBridge 146:22da6e220af6 666 __DSB(); //ensure completion of the invalidation
AnnaBridge 146:22da6e220af6 667 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 146:22da6e220af6 668 }
AnnaBridge 146:22da6e220af6 669
AnnaBridge 146:22da6e220af6 670 /** \brief Clean D$ by MVA
AnnaBridge 146:22da6e220af6 671
AnnaBridge 146:22da6e220af6 672 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 146:22da6e220af6 673 */
AnnaBridge 146:22da6e220af6 674 __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
AnnaBridge 146:22da6e220af6 675 __set_DCCMVAC((uint32_t)va);
AnnaBridge 146:22da6e220af6 676 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 146:22da6e220af6 677 }
AnnaBridge 146:22da6e220af6 678
AnnaBridge 146:22da6e220af6 679 /** \brief Invalidate D$ by MVA
AnnaBridge 146:22da6e220af6 680
AnnaBridge 146:22da6e220af6 681 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 146:22da6e220af6 682 */
AnnaBridge 146:22da6e220af6 683 __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
AnnaBridge 146:22da6e220af6 684 __set_DCIMVAC((uint32_t)va);
AnnaBridge 146:22da6e220af6 685 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 146:22da6e220af6 686 }
AnnaBridge 146:22da6e220af6 687
AnnaBridge 146:22da6e220af6 688 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 146:22da6e220af6 689
AnnaBridge 146:22da6e220af6 690 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 146:22da6e220af6 691 */
AnnaBridge 146:22da6e220af6 692 __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
AnnaBridge 146:22da6e220af6 693 __set_DCCIMVAC((uint32_t)va);
AnnaBridge 146:22da6e220af6 694 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 146:22da6e220af6 695 }
AnnaBridge 146:22da6e220af6 696
AnnaBridge 146:22da6e220af6 697 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 146:22da6e220af6 698
AnnaBridge 146:22da6e220af6 699 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 146:22da6e220af6 700 */
AnnaBridge 146:22da6e220af6 701 __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge 146:22da6e220af6 702 __L1C_CleanInvalidateCache(op); // compiler specific call
AnnaBridge 146:22da6e220af6 703 }
AnnaBridge 146:22da6e220af6 704
AnnaBridge 146:22da6e220af6 705
AnnaBridge 146:22da6e220af6 706 /** \brief Invalidate the whole D$
AnnaBridge 146:22da6e220af6 707
AnnaBridge 146:22da6e220af6 708 DCISW. Invalidate by Set/Way
AnnaBridge 146:22da6e220af6 709 */
AnnaBridge 146:22da6e220af6 710
AnnaBridge 146:22da6e220af6 711 __STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
AnnaBridge 146:22da6e220af6 712 L1C_CleanInvalidateCache(0);
AnnaBridge 146:22da6e220af6 713 }
AnnaBridge 146:22da6e220af6 714
AnnaBridge 146:22da6e220af6 715 /** \brief Clean the whole D$
AnnaBridge 146:22da6e220af6 716
AnnaBridge 146:22da6e220af6 717 DCCSW. Clean by Set/Way
AnnaBridge 146:22da6e220af6 718 */
AnnaBridge 146:22da6e220af6 719
AnnaBridge 146:22da6e220af6 720 __STATIC_INLINE void L1C_CleanDCacheAll(void) {
AnnaBridge 146:22da6e220af6 721 L1C_CleanInvalidateCache(1);
AnnaBridge 146:22da6e220af6 722 }
AnnaBridge 146:22da6e220af6 723
AnnaBridge 146:22da6e220af6 724 /** \brief Clean and invalidate the whole D$
AnnaBridge 146:22da6e220af6 725
AnnaBridge 146:22da6e220af6 726 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 146:22da6e220af6 727 */
AnnaBridge 146:22da6e220af6 728
AnnaBridge 146:22da6e220af6 729 __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
AnnaBridge 146:22da6e220af6 730 L1C_CleanInvalidateCache(2);
AnnaBridge 146:22da6e220af6 731 }
AnnaBridge 146:22da6e220af6 732
AnnaBridge 146:22da6e220af6 733
AnnaBridge 146:22da6e220af6 734 /* ########################## L2 Cache functions ################################# */
AnnaBridge 146:22da6e220af6 735 #if (__L2C_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 736 //Cache Sync operation
AnnaBridge 146:22da6e220af6 737 __STATIC_INLINE void L2C_Sync(void)
AnnaBridge 146:22da6e220af6 738 {
AnnaBridge 146:22da6e220af6 739 L2C_310->CACHE_SYNC = 0x0;
AnnaBridge 146:22da6e220af6 740 }
AnnaBridge 146:22da6e220af6 741
AnnaBridge 146:22da6e220af6 742 //return Cache controller cache ID
AnnaBridge 146:22da6e220af6 743 __STATIC_INLINE int L2C_GetID (void)
AnnaBridge 146:22da6e220af6 744 {
AnnaBridge 146:22da6e220af6 745 return L2C_310->CACHE_ID;
AnnaBridge 146:22da6e220af6 746 }
AnnaBridge 146:22da6e220af6 747
AnnaBridge 146:22da6e220af6 748 //return Cache controller cache Type
AnnaBridge 146:22da6e220af6 749 __STATIC_INLINE int L2C_GetType (void)
AnnaBridge 146:22da6e220af6 750 {
AnnaBridge 146:22da6e220af6 751 return L2C_310->CACHE_TYPE;
AnnaBridge 146:22da6e220af6 752 }
AnnaBridge 146:22da6e220af6 753
AnnaBridge 146:22da6e220af6 754 //Invalidate all cache by way
AnnaBridge 146:22da6e220af6 755 __STATIC_INLINE void L2C_InvAllByWay (void)
AnnaBridge 146:22da6e220af6 756 {
AnnaBridge 146:22da6e220af6 757 unsigned int assoc;
AnnaBridge 146:22da6e220af6 758
AnnaBridge 146:22da6e220af6 759 if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge 146:22da6e220af6 760 assoc = 16;
AnnaBridge 146:22da6e220af6 761 else
AnnaBridge 146:22da6e220af6 762 assoc = 8;
AnnaBridge 146:22da6e220af6 763
AnnaBridge 146:22da6e220af6 764 L2C_310->INV_WAY = (1 << assoc) - 1;
AnnaBridge 146:22da6e220af6 765 while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge 146:22da6e220af6 766
AnnaBridge 146:22da6e220af6 767 L2C_Sync();
AnnaBridge 146:22da6e220af6 768 }
AnnaBridge 146:22da6e220af6 769
AnnaBridge 146:22da6e220af6 770 //Clean and Invalidate all cache by way
AnnaBridge 146:22da6e220af6 771 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
AnnaBridge 146:22da6e220af6 772 {
AnnaBridge 146:22da6e220af6 773 unsigned int assoc;
AnnaBridge 146:22da6e220af6 774
AnnaBridge 146:22da6e220af6 775 if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge 146:22da6e220af6 776 assoc = 16;
AnnaBridge 146:22da6e220af6 777 else
AnnaBridge 146:22da6e220af6 778 assoc = 8;
AnnaBridge 146:22da6e220af6 779
AnnaBridge 146:22da6e220af6 780 L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
AnnaBridge 146:22da6e220af6 781 while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge 146:22da6e220af6 782
AnnaBridge 146:22da6e220af6 783 L2C_Sync();
AnnaBridge 146:22da6e220af6 784 }
AnnaBridge 146:22da6e220af6 785
AnnaBridge 146:22da6e220af6 786 //Enable Cache
AnnaBridge 146:22da6e220af6 787 __STATIC_INLINE void L2C_Enable(void)
AnnaBridge 146:22da6e220af6 788 {
AnnaBridge 146:22da6e220af6 789 L2C_310->CONTROL = 0;
AnnaBridge 146:22da6e220af6 790 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
AnnaBridge 146:22da6e220af6 791 L2C_310->DEBUG_CONTROL = 0;
AnnaBridge 146:22da6e220af6 792 L2C_310->DATA_LOCK_0_WAY = 0;
AnnaBridge 146:22da6e220af6 793 L2C_310->CACHE_SYNC = 0;
AnnaBridge 146:22da6e220af6 794 L2C_310->CONTROL = 0x01;
AnnaBridge 146:22da6e220af6 795 L2C_Sync();
AnnaBridge 146:22da6e220af6 796 }
AnnaBridge 146:22da6e220af6 797 //Disable Cache
AnnaBridge 146:22da6e220af6 798 __STATIC_INLINE void L2C_Disable(void)
AnnaBridge 146:22da6e220af6 799 {
AnnaBridge 146:22da6e220af6 800 L2C_310->CONTROL = 0x00;
AnnaBridge 146:22da6e220af6 801 L2C_Sync();
AnnaBridge 146:22da6e220af6 802 }
AnnaBridge 146:22da6e220af6 803
AnnaBridge 146:22da6e220af6 804 //Invalidate cache by physical address
AnnaBridge 146:22da6e220af6 805 __STATIC_INLINE void L2C_InvPa (void *pa)
AnnaBridge 146:22da6e220af6 806 {
AnnaBridge 146:22da6e220af6 807 L2C_310->INV_LINE_PA = (unsigned int)pa;
AnnaBridge 146:22da6e220af6 808 L2C_Sync();
AnnaBridge 146:22da6e220af6 809 }
AnnaBridge 146:22da6e220af6 810
AnnaBridge 146:22da6e220af6 811 //Clean cache by physical address
AnnaBridge 146:22da6e220af6 812 __STATIC_INLINE void L2C_CleanPa (void *pa)
AnnaBridge 146:22da6e220af6 813 {
AnnaBridge 146:22da6e220af6 814 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
AnnaBridge 146:22da6e220af6 815 L2C_Sync();
AnnaBridge 146:22da6e220af6 816 }
AnnaBridge 146:22da6e220af6 817
AnnaBridge 146:22da6e220af6 818 //Clean and invalidate cache by physical address
AnnaBridge 146:22da6e220af6 819 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
AnnaBridge 146:22da6e220af6 820 {
AnnaBridge 146:22da6e220af6 821 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
AnnaBridge 146:22da6e220af6 822 L2C_Sync();
AnnaBridge 146:22da6e220af6 823 }
AnnaBridge 146:22da6e220af6 824 #endif
AnnaBridge 146:22da6e220af6 825
AnnaBridge 146:22da6e220af6 826 /* ########################## GIC functions ###################################### */
AnnaBridge 146:22da6e220af6 827 #if (__GIC_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 828
AnnaBridge 146:22da6e220af6 829 __STATIC_INLINE void GIC_EnableDistributor(void)
AnnaBridge 146:22da6e220af6 830 {
AnnaBridge 146:22da6e220af6 831 GICDistributor->ICDDCR |= 1; //enable distributor
AnnaBridge 146:22da6e220af6 832 }
AnnaBridge 146:22da6e220af6 833
AnnaBridge 146:22da6e220af6 834 __STATIC_INLINE void GIC_DisableDistributor(void)
AnnaBridge 146:22da6e220af6 835 {
AnnaBridge 146:22da6e220af6 836 GICDistributor->ICDDCR &=~1; //disable distributor
AnnaBridge 146:22da6e220af6 837 }
AnnaBridge 146:22da6e220af6 838
AnnaBridge 146:22da6e220af6 839 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
AnnaBridge 146:22da6e220af6 840 {
AnnaBridge 146:22da6e220af6 841 return (uint32_t)(GICDistributor->ICDICTR);
AnnaBridge 146:22da6e220af6 842 }
AnnaBridge 146:22da6e220af6 843
AnnaBridge 146:22da6e220af6 844 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
AnnaBridge 146:22da6e220af6 845 {
AnnaBridge 146:22da6e220af6 846 return (uint32_t)(GICDistributor->ICDIIDR);
AnnaBridge 146:22da6e220af6 847 }
AnnaBridge 146:22da6e220af6 848
AnnaBridge 146:22da6e220af6 849 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
AnnaBridge 146:22da6e220af6 850 {
AnnaBridge 146:22da6e220af6 851 char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge 146:22da6e220af6 852 field += IRQn % 4;
AnnaBridge 146:22da6e220af6 853 *field = (char)cpu_target & 0xf;
AnnaBridge 146:22da6e220af6 854 }
AnnaBridge 146:22da6e220af6 855
AnnaBridge 146:22da6e220af6 856 __STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
AnnaBridge 146:22da6e220af6 857 {
AnnaBridge 146:22da6e220af6 858 uint32_t i, num_irq;
AnnaBridge 146:22da6e220af6 859
AnnaBridge 146:22da6e220af6 860 //Get the maximum number of interrupts that the GIC supports
AnnaBridge 146:22da6e220af6 861 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge 146:22da6e220af6 862
AnnaBridge 146:22da6e220af6 863 for (i = 0; i < (num_irq/16); i++)
AnnaBridge 146:22da6e220af6 864 {
AnnaBridge 146:22da6e220af6 865 GICDistributor->ICDISPR[i] = *ICDICFRn++;
AnnaBridge 146:22da6e220af6 866 }
AnnaBridge 146:22da6e220af6 867 }
AnnaBridge 146:22da6e220af6 868
AnnaBridge 146:22da6e220af6 869 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 870 {
AnnaBridge 146:22da6e220af6 871 char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge 146:22da6e220af6 872 field += IRQn % 4;
AnnaBridge 146:22da6e220af6 873 return ((uint32_t)*field & 0xf);
AnnaBridge 146:22da6e220af6 874 }
AnnaBridge 146:22da6e220af6 875
AnnaBridge 146:22da6e220af6 876 __STATIC_INLINE void GIC_EnableInterface(void)
AnnaBridge 146:22da6e220af6 877 {
AnnaBridge 146:22da6e220af6 878 GICInterface->ICCICR |= 1; //enable interface
AnnaBridge 146:22da6e220af6 879 }
AnnaBridge 146:22da6e220af6 880
AnnaBridge 146:22da6e220af6 881 __STATIC_INLINE void GIC_DisableInterface(void)
AnnaBridge 146:22da6e220af6 882 {
AnnaBridge 146:22da6e220af6 883 GICInterface->ICCICR &=~1; //disable distributor
AnnaBridge 146:22da6e220af6 884 }
AnnaBridge 146:22da6e220af6 885
AnnaBridge 146:22da6e220af6 886 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
AnnaBridge 146:22da6e220af6 887 {
AnnaBridge 146:22da6e220af6 888 return (IRQn_Type)(GICInterface->ICCIAR);
AnnaBridge 146:22da6e220af6 889 }
AnnaBridge 146:22da6e220af6 890
AnnaBridge 146:22da6e220af6 891 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 892 {
AnnaBridge 146:22da6e220af6 893 GICInterface->ICCEOIR = IRQn;
AnnaBridge 146:22da6e220af6 894 }
AnnaBridge 146:22da6e220af6 895
AnnaBridge 146:22da6e220af6 896 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 897 {
AnnaBridge 146:22da6e220af6 898 GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 146:22da6e220af6 899 }
AnnaBridge 146:22da6e220af6 900
AnnaBridge 146:22da6e220af6 901 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 902 {
AnnaBridge 146:22da6e220af6 903 GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 146:22da6e220af6 904 }
AnnaBridge 146:22da6e220af6 905
AnnaBridge 146:22da6e220af6 906 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 907 {
AnnaBridge 146:22da6e220af6 908 GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 146:22da6e220af6 909 }
AnnaBridge 146:22da6e220af6 910
AnnaBridge 146:22da6e220af6 911 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 912 {
AnnaBridge 146:22da6e220af6 913 GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge 146:22da6e220af6 914 }
AnnaBridge 146:22da6e220af6 915
AnnaBridge 146:22da6e220af6 916 __STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
AnnaBridge 146:22da6e220af6 917 {
AnnaBridge 146:22da6e220af6 918 // Word-size read/writes must be used to access this register
AnnaBridge 146:22da6e220af6 919 volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
AnnaBridge 146:22da6e220af6 920 unsigned bit_shift = (IRQn % 16)<<1;
AnnaBridge 146:22da6e220af6 921 unsigned int save_word;
AnnaBridge 146:22da6e220af6 922
AnnaBridge 146:22da6e220af6 923 save_word = *field;
AnnaBridge 146:22da6e220af6 924 save_word &= (~(3 << bit_shift));
AnnaBridge 146:22da6e220af6 925
AnnaBridge 146:22da6e220af6 926 *field = (save_word | (((edge_level<<1) | model) << bit_shift));
AnnaBridge 146:22da6e220af6 927 }
AnnaBridge 146:22da6e220af6 928
AnnaBridge 146:22da6e220af6 929 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 146:22da6e220af6 930 {
AnnaBridge 146:22da6e220af6 931 char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge 146:22da6e220af6 932 field += IRQn % 4;
AnnaBridge 146:22da6e220af6 933 *field = (char)priority;
AnnaBridge 146:22da6e220af6 934 }
AnnaBridge 146:22da6e220af6 935
AnnaBridge 146:22da6e220af6 936 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 937 {
AnnaBridge 146:22da6e220af6 938 char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge 146:22da6e220af6 939 field += IRQn % 4;
AnnaBridge 146:22da6e220af6 940 return (uint32_t)*field;
AnnaBridge 146:22da6e220af6 941 }
AnnaBridge 146:22da6e220af6 942
AnnaBridge 146:22da6e220af6 943 __STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
AnnaBridge 146:22da6e220af6 944 {
AnnaBridge 146:22da6e220af6 945 GICInterface->ICCPMR = priority & 0xff; //set priority mask
AnnaBridge 146:22da6e220af6 946 }
AnnaBridge 146:22da6e220af6 947
AnnaBridge 146:22da6e220af6 948 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
AnnaBridge 146:22da6e220af6 949 {
AnnaBridge 146:22da6e220af6 950 GICInterface->ICCBPR = binary_point & 0x07; //set binary point
AnnaBridge 146:22da6e220af6 951 }
AnnaBridge 146:22da6e220af6 952
AnnaBridge 146:22da6e220af6 953 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
AnnaBridge 146:22da6e220af6 954 {
AnnaBridge 146:22da6e220af6 955 return (uint32_t)GICInterface->ICCBPR;
AnnaBridge 146:22da6e220af6 956 }
AnnaBridge 146:22da6e220af6 957
AnnaBridge 146:22da6e220af6 958 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
AnnaBridge 146:22da6e220af6 959 {
AnnaBridge 146:22da6e220af6 960 uint32_t pending, active;
AnnaBridge 146:22da6e220af6 961
AnnaBridge 146:22da6e220af6 962 active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge 146:22da6e220af6 963 pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge 146:22da6e220af6 964
AnnaBridge 146:22da6e220af6 965 return ((active<<1) | pending);
AnnaBridge 146:22da6e220af6 966 }
AnnaBridge 146:22da6e220af6 967
AnnaBridge 146:22da6e220af6 968 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
AnnaBridge 146:22da6e220af6 969 {
AnnaBridge 146:22da6e220af6 970 GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
AnnaBridge 146:22da6e220af6 971 }
AnnaBridge 146:22da6e220af6 972
AnnaBridge 146:22da6e220af6 973 __STATIC_INLINE void GIC_DistInit(void)
AnnaBridge 146:22da6e220af6 974 {
AnnaBridge 146:22da6e220af6 975 IRQn_Type i;
AnnaBridge 146:22da6e220af6 976 uint32_t num_irq = 0;
AnnaBridge 146:22da6e220af6 977 uint32_t priority_field;
AnnaBridge 146:22da6e220af6 978
AnnaBridge 146:22da6e220af6 979 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge 146:22da6e220af6 980 //configuring all of the interrupts as Secure.
AnnaBridge 146:22da6e220af6 981
AnnaBridge 146:22da6e220af6 982 //Disable interrupt forwarding
AnnaBridge 146:22da6e220af6 983 GIC_DisableDistributor();
AnnaBridge 146:22da6e220af6 984 //Get the maximum number of interrupts that the GIC supports
AnnaBridge 146:22da6e220af6 985 num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge 146:22da6e220af6 986
AnnaBridge 146:22da6e220af6 987 /* Priority level is implementation defined.
AnnaBridge 146:22da6e220af6 988 To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge 146:22da6e220af6 989 priority field and read back the value stored.*/
AnnaBridge 146:22da6e220af6 990 GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge 146:22da6e220af6 991 priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge 146:22da6e220af6 992
AnnaBridge 146:22da6e220af6 993 for (i = (IRQn_Type)32; i < num_irq; i++)
AnnaBridge 146:22da6e220af6 994 {
AnnaBridge 146:22da6e220af6 995 //Disable the SPI interrupt
AnnaBridge 146:22da6e220af6 996 GIC_DisableIRQ(i);
AnnaBridge 146:22da6e220af6 997 //Set level-sensitive and 1-N model
AnnaBridge 146:22da6e220af6 998 GIC_SetLevelModel(i, 0, 1);
AnnaBridge 146:22da6e220af6 999 //Set priority
AnnaBridge 146:22da6e220af6 1000 GIC_SetPriority(i, priority_field/2);
AnnaBridge 146:22da6e220af6 1001 //Set target list to CPU0
AnnaBridge 146:22da6e220af6 1002 GIC_SetTarget(i, 1);
AnnaBridge 146:22da6e220af6 1003 }
AnnaBridge 146:22da6e220af6 1004 //Enable distributor
AnnaBridge 146:22da6e220af6 1005 GIC_EnableDistributor();
AnnaBridge 146:22da6e220af6 1006 }
AnnaBridge 146:22da6e220af6 1007
AnnaBridge 146:22da6e220af6 1008 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
AnnaBridge 146:22da6e220af6 1009 {
AnnaBridge 146:22da6e220af6 1010 IRQn_Type i;
AnnaBridge 146:22da6e220af6 1011 uint32_t priority_field;
AnnaBridge 146:22da6e220af6 1012
AnnaBridge 146:22da6e220af6 1013 //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge 146:22da6e220af6 1014 //configuring all of the interrupts as Secure.
AnnaBridge 146:22da6e220af6 1015
AnnaBridge 146:22da6e220af6 1016 //Disable interrupt forwarding
AnnaBridge 146:22da6e220af6 1017 GIC_DisableInterface();
AnnaBridge 146:22da6e220af6 1018
AnnaBridge 146:22da6e220af6 1019 /* Priority level is implementation defined.
AnnaBridge 146:22da6e220af6 1020 To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge 146:22da6e220af6 1021 priority field and read back the value stored.*/
AnnaBridge 146:22da6e220af6 1022 GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge 146:22da6e220af6 1023 priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge 146:22da6e220af6 1024
AnnaBridge 146:22da6e220af6 1025 //SGI and PPI
AnnaBridge 146:22da6e220af6 1026 for (i = (IRQn_Type)0; i < 32; i++)
AnnaBridge 146:22da6e220af6 1027 {
AnnaBridge 146:22da6e220af6 1028 //Set level-sensitive and 1-N model for PPI
AnnaBridge 146:22da6e220af6 1029 if(i > 15)
AnnaBridge 146:22da6e220af6 1030 GIC_SetLevelModel(i, 0, 1);
AnnaBridge 146:22da6e220af6 1031 //Disable SGI and PPI interrupts
AnnaBridge 146:22da6e220af6 1032 GIC_DisableIRQ(i);
AnnaBridge 146:22da6e220af6 1033 //Set priority
AnnaBridge 146:22da6e220af6 1034 GIC_SetPriority(i, priority_field/2);
AnnaBridge 146:22da6e220af6 1035 }
AnnaBridge 146:22da6e220af6 1036 //Enable interface
AnnaBridge 146:22da6e220af6 1037 GIC_EnableInterface();
AnnaBridge 146:22da6e220af6 1038 //Set binary point to 0
AnnaBridge 146:22da6e220af6 1039 GIC_SetBinaryPoint(0);
AnnaBridge 146:22da6e220af6 1040 //Set priority mask
AnnaBridge 146:22da6e220af6 1041 GIC_InterfacePriorityMask(0xff);
AnnaBridge 146:22da6e220af6 1042 }
AnnaBridge 146:22da6e220af6 1043
AnnaBridge 146:22da6e220af6 1044 __STATIC_INLINE void GIC_Enable(void)
AnnaBridge 146:22da6e220af6 1045 {
AnnaBridge 146:22da6e220af6 1046 GIC_DistInit();
AnnaBridge 146:22da6e220af6 1047 GIC_CPUInterfaceInit(); //per CPU
AnnaBridge 146:22da6e220af6 1048 }
AnnaBridge 146:22da6e220af6 1049 #endif
AnnaBridge 146:22da6e220af6 1050
AnnaBridge 146:22da6e220af6 1051 /* ########################## Generic Timer functions ############################ */
AnnaBridge 146:22da6e220af6 1052 #if (__TIM_PRESENT == 1U)
AnnaBridge 146:22da6e220af6 1053
AnnaBridge 146:22da6e220af6 1054 /* PL1 Physical Timer */
AnnaBridge 146:22da6e220af6 1055 #if (__CORTEX_A == 7U)
AnnaBridge 146:22da6e220af6 1056 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
AnnaBridge 146:22da6e220af6 1057 __set_CNTP_TVAL(value);
AnnaBridge 146:22da6e220af6 1058 __ISB();
AnnaBridge 146:22da6e220af6 1059 }
AnnaBridge 146:22da6e220af6 1060
AnnaBridge 146:22da6e220af6 1061 __STATIC_INLINE uint32_t PL1_GetCurrentValue() {
AnnaBridge 146:22da6e220af6 1062 return(__get_CNTP_TVAL());
AnnaBridge 146:22da6e220af6 1063 }
AnnaBridge 146:22da6e220af6 1064
AnnaBridge 146:22da6e220af6 1065 __STATIC_INLINE void PL1_SetControl(uint32_t value) {
AnnaBridge 146:22da6e220af6 1066 __set_CNTP_CTL(value);
AnnaBridge 146:22da6e220af6 1067 __ISB();
AnnaBridge 146:22da6e220af6 1068 }
AnnaBridge 146:22da6e220af6 1069
AnnaBridge 146:22da6e220af6 1070 /* Private Timer */
AnnaBridge 146:22da6e220af6 1071 #elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
AnnaBridge 146:22da6e220af6 1072 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
AnnaBridge 146:22da6e220af6 1073 PTIM->LOAD = value;
AnnaBridge 146:22da6e220af6 1074 }
AnnaBridge 146:22da6e220af6 1075
AnnaBridge 146:22da6e220af6 1076 __STATIC_INLINE uint32_t PTIM_GetLoadValue() {
AnnaBridge 146:22da6e220af6 1077 return(PTIM->LOAD);
AnnaBridge 146:22da6e220af6 1078 }
AnnaBridge 146:22da6e220af6 1079
AnnaBridge 146:22da6e220af6 1080 __STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
AnnaBridge 146:22da6e220af6 1081 return(PTIM->COUNTER);
AnnaBridge 146:22da6e220af6 1082 }
AnnaBridge 146:22da6e220af6 1083
AnnaBridge 146:22da6e220af6 1084 __STATIC_INLINE void PTIM_SetControl(uint32_t value) {
AnnaBridge 146:22da6e220af6 1085 PTIM->CONTROL = value;
AnnaBridge 146:22da6e220af6 1086 }
AnnaBridge 146:22da6e220af6 1087
AnnaBridge 146:22da6e220af6 1088 __STATIC_INLINE uint32_t PTIM_GetControl(void) {
AnnaBridge 146:22da6e220af6 1089 return(PTIM->CONTROL);
AnnaBridge 146:22da6e220af6 1090 }
AnnaBridge 146:22da6e220af6 1091
AnnaBridge 146:22da6e220af6 1092 __STATIC_INLINE void PTIM_ClearEventFlag(void) {
AnnaBridge 146:22da6e220af6 1093 PTIM->ISR = 1;
AnnaBridge 146:22da6e220af6 1094 }
AnnaBridge 146:22da6e220af6 1095 #endif
AnnaBridge 146:22da6e220af6 1096 #endif
AnnaBridge 146:22da6e220af6 1097
AnnaBridge 146:22da6e220af6 1098 /* ########################## MMU functions ###################################### */
AnnaBridge 146:22da6e220af6 1099
AnnaBridge 146:22da6e220af6 1100 #define SECTION_DESCRIPTOR (0x2)
AnnaBridge 146:22da6e220af6 1101 #define SECTION_MASK (0xFFFFFFFC)
AnnaBridge 146:22da6e220af6 1102
AnnaBridge 146:22da6e220af6 1103 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 146:22da6e220af6 1104 #define SECTION_B_SHIFT (2)
AnnaBridge 146:22da6e220af6 1105 #define SECTION_C_SHIFT (3)
AnnaBridge 146:22da6e220af6 1106 #define SECTION_TEX0_SHIFT (12)
AnnaBridge 146:22da6e220af6 1107 #define SECTION_TEX1_SHIFT (13)
AnnaBridge 146:22da6e220af6 1108 #define SECTION_TEX2_SHIFT (14)
AnnaBridge 146:22da6e220af6 1109
AnnaBridge 146:22da6e220af6 1110 #define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge 146:22da6e220af6 1111 #define SECTION_XN_SHIFT (4)
AnnaBridge 146:22da6e220af6 1112
AnnaBridge 146:22da6e220af6 1113 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 146:22da6e220af6 1114 #define SECTION_DOMAIN_SHIFT (5)
AnnaBridge 146:22da6e220af6 1115
AnnaBridge 146:22da6e220af6 1116 #define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge 146:22da6e220af6 1117 #define SECTION_P_SHIFT (9)
AnnaBridge 146:22da6e220af6 1118
AnnaBridge 146:22da6e220af6 1119 #define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge 146:22da6e220af6 1120 #define SECTION_AP_SHIFT (10)
AnnaBridge 146:22da6e220af6 1121 #define SECTION_AP2_SHIFT (15)
AnnaBridge 146:22da6e220af6 1122
AnnaBridge 146:22da6e220af6 1123 #define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge 146:22da6e220af6 1124 #define SECTION_S_SHIFT (16)
AnnaBridge 146:22da6e220af6 1125
AnnaBridge 146:22da6e220af6 1126 #define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge 146:22da6e220af6 1127 #define SECTION_NG_SHIFT (17)
AnnaBridge 146:22da6e220af6 1128
AnnaBridge 146:22da6e220af6 1129 #define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge 146:22da6e220af6 1130 #define SECTION_NS_SHIFT (19)
AnnaBridge 146:22da6e220af6 1131
AnnaBridge 146:22da6e220af6 1132 #define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge 146:22da6e220af6 1133 #define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge 146:22da6e220af6 1134
AnnaBridge 146:22da6e220af6 1135 #define PAGE_L2_4K_DESC (0x2)
AnnaBridge 146:22da6e220af6 1136 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge 146:22da6e220af6 1137
AnnaBridge 146:22da6e220af6 1138 #define PAGE_L2_64K_DESC (0x1)
AnnaBridge 146:22da6e220af6 1139 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge 146:22da6e220af6 1140
AnnaBridge 146:22da6e220af6 1141 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge 146:22da6e220af6 1142 #define PAGE_4K_B_SHIFT (2)
AnnaBridge 146:22da6e220af6 1143 #define PAGE_4K_C_SHIFT (3)
AnnaBridge 146:22da6e220af6 1144 #define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge 146:22da6e220af6 1145 #define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge 146:22da6e220af6 1146 #define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge 146:22da6e220af6 1147
AnnaBridge 146:22da6e220af6 1148 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 146:22da6e220af6 1149 #define PAGE_64K_B_SHIFT (2)
AnnaBridge 146:22da6e220af6 1150 #define PAGE_64K_C_SHIFT (3)
AnnaBridge 146:22da6e220af6 1151 #define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge 146:22da6e220af6 1152 #define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge 146:22da6e220af6 1153 #define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge 146:22da6e220af6 1154
AnnaBridge 146:22da6e220af6 1155 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 146:22da6e220af6 1156 #define PAGE_B_SHIFT (2)
AnnaBridge 146:22da6e220af6 1157 #define PAGE_C_SHIFT (3)
AnnaBridge 146:22da6e220af6 1158 #define PAGE_TEX_SHIFT (12)
AnnaBridge 146:22da6e220af6 1159
AnnaBridge 146:22da6e220af6 1160 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge 146:22da6e220af6 1161 #define PAGE_XN_4K_SHIFT (0)
AnnaBridge 146:22da6e220af6 1162 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge 146:22da6e220af6 1163 #define PAGE_XN_64K_SHIFT (15)
AnnaBridge 146:22da6e220af6 1164
AnnaBridge 146:22da6e220af6 1165 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 146:22da6e220af6 1166 #define PAGE_DOMAIN_SHIFT (5)
AnnaBridge 146:22da6e220af6 1167
AnnaBridge 146:22da6e220af6 1168 #define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge 146:22da6e220af6 1169 #define PAGE_P_SHIFT (9)
AnnaBridge 146:22da6e220af6 1170
AnnaBridge 146:22da6e220af6 1171 #define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge 146:22da6e220af6 1172 #define PAGE_AP_SHIFT (4)
AnnaBridge 146:22da6e220af6 1173 #define PAGE_AP2_SHIFT (9)
AnnaBridge 146:22da6e220af6 1174
AnnaBridge 146:22da6e220af6 1175 #define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge 146:22da6e220af6 1176 #define PAGE_S_SHIFT (10)
AnnaBridge 146:22da6e220af6 1177
AnnaBridge 146:22da6e220af6 1178 #define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge 146:22da6e220af6 1179 #define PAGE_NG_SHIFT (11)
AnnaBridge 146:22da6e220af6 1180
AnnaBridge 146:22da6e220af6 1181 #define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge 146:22da6e220af6 1182 #define PAGE_NS_SHIFT (3)
AnnaBridge 146:22da6e220af6 1183
AnnaBridge 146:22da6e220af6 1184 #define OFFSET_1M (0x00100000)
AnnaBridge 146:22da6e220af6 1185 #define OFFSET_64K (0x00010000)
AnnaBridge 146:22da6e220af6 1186 #define OFFSET_4K (0x00001000)
AnnaBridge 146:22da6e220af6 1187
AnnaBridge 146:22da6e220af6 1188 #define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge 146:22da6e220af6 1189
AnnaBridge 146:22da6e220af6 1190 /* Attributes enumerations */
AnnaBridge 146:22da6e220af6 1191
AnnaBridge 146:22da6e220af6 1192 /* Region size attributes */
AnnaBridge 146:22da6e220af6 1193 typedef enum
AnnaBridge 146:22da6e220af6 1194 {
AnnaBridge 146:22da6e220af6 1195 SECTION,
AnnaBridge 146:22da6e220af6 1196 PAGE_4k,
AnnaBridge 146:22da6e220af6 1197 PAGE_64k,
AnnaBridge 146:22da6e220af6 1198 } mmu_region_size_Type;
AnnaBridge 146:22da6e220af6 1199
AnnaBridge 146:22da6e220af6 1200 /* Region type attributes */
AnnaBridge 146:22da6e220af6 1201 typedef enum
AnnaBridge 146:22da6e220af6 1202 {
AnnaBridge 146:22da6e220af6 1203 NORMAL,
AnnaBridge 146:22da6e220af6 1204 DEVICE,
AnnaBridge 146:22da6e220af6 1205 SHARED_DEVICE,
AnnaBridge 146:22da6e220af6 1206 NON_SHARED_DEVICE,
AnnaBridge 146:22da6e220af6 1207 STRONGLY_ORDERED
AnnaBridge 146:22da6e220af6 1208 } mmu_memory_Type;
AnnaBridge 146:22da6e220af6 1209
AnnaBridge 146:22da6e220af6 1210 /* Region cacheability attributes */
AnnaBridge 146:22da6e220af6 1211 typedef enum
AnnaBridge 146:22da6e220af6 1212 {
AnnaBridge 146:22da6e220af6 1213 NON_CACHEABLE,
AnnaBridge 146:22da6e220af6 1214 WB_WA,
AnnaBridge 146:22da6e220af6 1215 WT,
AnnaBridge 146:22da6e220af6 1216 WB_NO_WA,
AnnaBridge 146:22da6e220af6 1217 } mmu_cacheability_Type;
AnnaBridge 146:22da6e220af6 1218
AnnaBridge 146:22da6e220af6 1219 /* Region parity check attributes */
AnnaBridge 146:22da6e220af6 1220 typedef enum
AnnaBridge 146:22da6e220af6 1221 {
AnnaBridge 146:22da6e220af6 1222 ECC_DISABLED,
AnnaBridge 146:22da6e220af6 1223 ECC_ENABLED,
AnnaBridge 146:22da6e220af6 1224 } mmu_ecc_check_Type;
AnnaBridge 146:22da6e220af6 1225
AnnaBridge 146:22da6e220af6 1226 /* Region execution attributes */
AnnaBridge 146:22da6e220af6 1227 typedef enum
AnnaBridge 146:22da6e220af6 1228 {
AnnaBridge 146:22da6e220af6 1229 EXECUTE,
AnnaBridge 146:22da6e220af6 1230 NON_EXECUTE,
AnnaBridge 146:22da6e220af6 1231 } mmu_execute_Type;
AnnaBridge 146:22da6e220af6 1232
AnnaBridge 146:22da6e220af6 1233 /* Region global attributes */
AnnaBridge 146:22da6e220af6 1234 typedef enum
AnnaBridge 146:22da6e220af6 1235 {
AnnaBridge 146:22da6e220af6 1236 GLOBAL,
AnnaBridge 146:22da6e220af6 1237 NON_GLOBAL,
AnnaBridge 146:22da6e220af6 1238 } mmu_global_Type;
AnnaBridge 146:22da6e220af6 1239
AnnaBridge 146:22da6e220af6 1240 /* Region shareability attributes */
AnnaBridge 146:22da6e220af6 1241 typedef enum
AnnaBridge 146:22da6e220af6 1242 {
AnnaBridge 146:22da6e220af6 1243 NON_SHARED,
AnnaBridge 146:22da6e220af6 1244 SHARED,
AnnaBridge 146:22da6e220af6 1245 } mmu_shared_Type;
AnnaBridge 146:22da6e220af6 1246
AnnaBridge 146:22da6e220af6 1247 /* Region security attributes */
AnnaBridge 146:22da6e220af6 1248 typedef enum
AnnaBridge 146:22da6e220af6 1249 {
AnnaBridge 146:22da6e220af6 1250 SECURE,
AnnaBridge 146:22da6e220af6 1251 NON_SECURE,
AnnaBridge 146:22da6e220af6 1252 } mmu_secure_Type;
AnnaBridge 146:22da6e220af6 1253
AnnaBridge 146:22da6e220af6 1254 /* Region access attributes */
AnnaBridge 146:22da6e220af6 1255 typedef enum
AnnaBridge 146:22da6e220af6 1256 {
AnnaBridge 146:22da6e220af6 1257 NO_ACCESS,
AnnaBridge 146:22da6e220af6 1258 RW,
AnnaBridge 146:22da6e220af6 1259 READ,
AnnaBridge 146:22da6e220af6 1260 } mmu_access_Type;
AnnaBridge 146:22da6e220af6 1261
AnnaBridge 146:22da6e220af6 1262 /* Memory Region definition */
AnnaBridge 146:22da6e220af6 1263 typedef struct RegionStruct {
AnnaBridge 146:22da6e220af6 1264 mmu_region_size_Type rg_t;
AnnaBridge 146:22da6e220af6 1265 mmu_memory_Type mem_t;
AnnaBridge 146:22da6e220af6 1266 uint8_t domain;
AnnaBridge 146:22da6e220af6 1267 mmu_cacheability_Type inner_norm_t;
AnnaBridge 146:22da6e220af6 1268 mmu_cacheability_Type outer_norm_t;
AnnaBridge 146:22da6e220af6 1269 mmu_ecc_check_Type e_t;
AnnaBridge 146:22da6e220af6 1270 mmu_execute_Type xn_t;
AnnaBridge 146:22da6e220af6 1271 mmu_global_Type g_t;
AnnaBridge 146:22da6e220af6 1272 mmu_secure_Type sec_t;
AnnaBridge 146:22da6e220af6 1273 mmu_access_Type priv_t;
AnnaBridge 146:22da6e220af6 1274 mmu_access_Type user_t;
AnnaBridge 146:22da6e220af6 1275 mmu_shared_Type sh_t;
AnnaBridge 146:22da6e220af6 1276
AnnaBridge 146:22da6e220af6 1277 } mmu_region_attributes_Type;
AnnaBridge 146:22da6e220af6 1278
AnnaBridge 146:22da6e220af6 1279 //Following macros define the descriptors and attributes
AnnaBridge 146:22da6e220af6 1280 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
AnnaBridge 146:22da6e220af6 1281 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 146:22da6e220af6 1282 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1283 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1284 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1285 region.inner_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1286 region.outer_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1287 region.mem_t = NORMAL; \
AnnaBridge 146:22da6e220af6 1288 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1289 region.xn_t = EXECUTE; \
AnnaBridge 146:22da6e220af6 1290 region.priv_t = RW; \
AnnaBridge 146:22da6e220af6 1291 region.user_t = RW; \
AnnaBridge 146:22da6e220af6 1292 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1293 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 146:22da6e220af6 1294
AnnaBridge 146:22da6e220af6 1295 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
AnnaBridge 146:22da6e220af6 1296 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 146:22da6e220af6 1297 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1298 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1299 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1300 region.inner_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1301 region.outer_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1302 region.mem_t = NORMAL; \
AnnaBridge 146:22da6e220af6 1303 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1304 region.xn_t = EXECUTE; \
AnnaBridge 146:22da6e220af6 1305 region.priv_t = READ; \
AnnaBridge 146:22da6e220af6 1306 region.user_t = READ; \
AnnaBridge 146:22da6e220af6 1307 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1308 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 146:22da6e220af6 1309
AnnaBridge 146:22da6e220af6 1310 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
AnnaBridge 146:22da6e220af6 1311 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 146:22da6e220af6 1312 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1313 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1314 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1315 region.inner_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1316 region.outer_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1317 region.mem_t = NORMAL; \
AnnaBridge 146:22da6e220af6 1318 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1319 region.xn_t = NON_EXECUTE; \
AnnaBridge 146:22da6e220af6 1320 region.priv_t = READ; \
AnnaBridge 146:22da6e220af6 1321 region.user_t = READ; \
AnnaBridge 146:22da6e220af6 1322 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1323 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 146:22da6e220af6 1324
AnnaBridge 146:22da6e220af6 1325 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
AnnaBridge 146:22da6e220af6 1326 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 146:22da6e220af6 1327 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1328 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1329 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1330 region.inner_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1331 region.outer_norm_t = WB_WA; \
AnnaBridge 146:22da6e220af6 1332 region.mem_t = NORMAL; \
AnnaBridge 146:22da6e220af6 1333 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1334 region.xn_t = NON_EXECUTE; \
AnnaBridge 146:22da6e220af6 1335 region.priv_t = RW; \
AnnaBridge 146:22da6e220af6 1336 region.user_t = RW; \
AnnaBridge 146:22da6e220af6 1337 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1338 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 146:22da6e220af6 1339 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
AnnaBridge 146:22da6e220af6 1340 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 146:22da6e220af6 1341 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1342 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1343 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1344 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1345 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1346 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 146:22da6e220af6 1347 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1348 region.xn_t = NON_EXECUTE; \
AnnaBridge 146:22da6e220af6 1349 region.priv_t = RW; \
AnnaBridge 146:22da6e220af6 1350 region.user_t = RW; \
AnnaBridge 146:22da6e220af6 1351 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1352 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 146:22da6e220af6 1353
AnnaBridge 146:22da6e220af6 1354 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
AnnaBridge 146:22da6e220af6 1355 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 146:22da6e220af6 1356 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1357 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1358 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1359 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1360 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1361 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 146:22da6e220af6 1362 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1363 region.xn_t = NON_EXECUTE; \
AnnaBridge 146:22da6e220af6 1364 region.priv_t = READ; \
AnnaBridge 146:22da6e220af6 1365 region.user_t = READ; \
AnnaBridge 146:22da6e220af6 1366 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1367 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 146:22da6e220af6 1368
AnnaBridge 146:22da6e220af6 1369 //Sect_Device_RW. Sect_Device_RO, but writeable
AnnaBridge 146:22da6e220af6 1370 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge 146:22da6e220af6 1371 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1372 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1373 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1374 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1375 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1376 region.mem_t = STRONGLY_ORDERED; \
AnnaBridge 146:22da6e220af6 1377 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1378 region.xn_t = NON_EXECUTE; \
AnnaBridge 146:22da6e220af6 1379 region.priv_t = RW; \
AnnaBridge 146:22da6e220af6 1380 region.user_t = RW; \
AnnaBridge 146:22da6e220af6 1381 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1382 MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge 146:22da6e220af6 1383 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge 146:22da6e220af6 1384 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
AnnaBridge 146:22da6e220af6 1385 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1386 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1387 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1388 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1389 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1390 region.mem_t = SHARED_DEVICE; \
AnnaBridge 146:22da6e220af6 1391 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1392 region.xn_t = NON_EXECUTE; \
AnnaBridge 146:22da6e220af6 1393 region.priv_t = RW; \
AnnaBridge 146:22da6e220af6 1394 region.user_t = RW; \
AnnaBridge 146:22da6e220af6 1395 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1396 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge 146:22da6e220af6 1397
AnnaBridge 146:22da6e220af6 1398 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge 146:22da6e220af6 1399 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
AnnaBridge 146:22da6e220af6 1400 region.domain = 0x0; \
AnnaBridge 146:22da6e220af6 1401 region.e_t = ECC_DISABLED; \
AnnaBridge 146:22da6e220af6 1402 region.g_t = GLOBAL; \
AnnaBridge 146:22da6e220af6 1403 region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1404 region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge 146:22da6e220af6 1405 region.mem_t = SHARED_DEVICE; \
AnnaBridge 146:22da6e220af6 1406 region.sec_t = SECURE; \
AnnaBridge 146:22da6e220af6 1407 region.xn_t = NON_EXECUTE; \
AnnaBridge 146:22da6e220af6 1408 region.priv_t = RW; \
AnnaBridge 146:22da6e220af6 1409 region.user_t = RW; \
AnnaBridge 146:22da6e220af6 1410 region.sh_t = NON_SHARED; \
AnnaBridge 146:22da6e220af6 1411 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge 146:22da6e220af6 1412
AnnaBridge 146:22da6e220af6 1413 /** \brief Set section execution-never attribute
AnnaBridge 146:22da6e220af6 1414
AnnaBridge 146:22da6e220af6 1415 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1416 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 146:22da6e220af6 1417
AnnaBridge 146:22da6e220af6 1418 \return 0
AnnaBridge 146:22da6e220af6 1419 */
AnnaBridge 146:22da6e220af6 1420 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge 146:22da6e220af6 1421 {
AnnaBridge 146:22da6e220af6 1422 *descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge 146:22da6e220af6 1423 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge 146:22da6e220af6 1424 return 0;
AnnaBridge 146:22da6e220af6 1425 }
AnnaBridge 146:22da6e220af6 1426
AnnaBridge 146:22da6e220af6 1427 /** \brief Set section domain
AnnaBridge 146:22da6e220af6 1428
AnnaBridge 146:22da6e220af6 1429 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1430 \param [in] domain Section domain
AnnaBridge 146:22da6e220af6 1431
AnnaBridge 146:22da6e220af6 1432 \return 0
AnnaBridge 146:22da6e220af6 1433 */
AnnaBridge 146:22da6e220af6 1434 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 146:22da6e220af6 1435 {
AnnaBridge 146:22da6e220af6 1436 *descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge 146:22da6e220af6 1437 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge 146:22da6e220af6 1438 return 0;
AnnaBridge 146:22da6e220af6 1439 }
AnnaBridge 146:22da6e220af6 1440
AnnaBridge 146:22da6e220af6 1441 /** \brief Set section parity check
AnnaBridge 146:22da6e220af6 1442
AnnaBridge 146:22da6e220af6 1443 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1444 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 146:22da6e220af6 1445
AnnaBridge 146:22da6e220af6 1446 \return 0
AnnaBridge 146:22da6e220af6 1447 */
AnnaBridge 146:22da6e220af6 1448 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 146:22da6e220af6 1449 {
AnnaBridge 146:22da6e220af6 1450 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 146:22da6e220af6 1451 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 146:22da6e220af6 1452 return 0;
AnnaBridge 146:22da6e220af6 1453 }
AnnaBridge 146:22da6e220af6 1454
AnnaBridge 146:22da6e220af6 1455 /** \brief Set section access privileges
AnnaBridge 146:22da6e220af6 1456
AnnaBridge 146:22da6e220af6 1457 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1458 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 146:22da6e220af6 1459 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 146:22da6e220af6 1460 \param [in] afe Access flag enable
AnnaBridge 146:22da6e220af6 1461
AnnaBridge 146:22da6e220af6 1462 \return 0
AnnaBridge 146:22da6e220af6 1463 */
AnnaBridge 146:22da6e220af6 1464 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 146:22da6e220af6 1465 {
AnnaBridge 146:22da6e220af6 1466 uint32_t ap = 0;
AnnaBridge 146:22da6e220af6 1467
AnnaBridge 146:22da6e220af6 1468 if (afe == 0) { //full access
AnnaBridge 146:22da6e220af6 1469 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 146:22da6e220af6 1470 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 146:22da6e220af6 1471 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 146:22da6e220af6 1472 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 146:22da6e220af6 1473 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 146:22da6e220af6 1474 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 146:22da6e220af6 1475 }
AnnaBridge 146:22da6e220af6 1476
AnnaBridge 146:22da6e220af6 1477 else { //Simplified access
AnnaBridge 146:22da6e220af6 1478 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 146:22da6e220af6 1479 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 146:22da6e220af6 1480 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 146:22da6e220af6 1481 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 146:22da6e220af6 1482 }
AnnaBridge 146:22da6e220af6 1483
AnnaBridge 146:22da6e220af6 1484 *descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge 146:22da6e220af6 1485 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge 146:22da6e220af6 1486 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge 146:22da6e220af6 1487
AnnaBridge 146:22da6e220af6 1488 return 0;
AnnaBridge 146:22da6e220af6 1489 }
AnnaBridge 146:22da6e220af6 1490
AnnaBridge 146:22da6e220af6 1491 /** \brief Set section shareability
AnnaBridge 146:22da6e220af6 1492
AnnaBridge 146:22da6e220af6 1493 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1494 \param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge 146:22da6e220af6 1495
AnnaBridge 146:22da6e220af6 1496 \return 0
AnnaBridge 146:22da6e220af6 1497 */
AnnaBridge 146:22da6e220af6 1498 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge 146:22da6e220af6 1499 {
AnnaBridge 146:22da6e220af6 1500 *descriptor_l1 &= SECTION_S_MASK;
AnnaBridge 146:22da6e220af6 1501 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge 146:22da6e220af6 1502 return 0;
AnnaBridge 146:22da6e220af6 1503 }
AnnaBridge 146:22da6e220af6 1504
AnnaBridge 146:22da6e220af6 1505 /** \brief Set section Global attribute
AnnaBridge 146:22da6e220af6 1506
AnnaBridge 146:22da6e220af6 1507 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1508 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge 146:22da6e220af6 1509
AnnaBridge 146:22da6e220af6 1510 \return 0
AnnaBridge 146:22da6e220af6 1511 */
AnnaBridge 146:22da6e220af6 1512 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge 146:22da6e220af6 1513 {
AnnaBridge 146:22da6e220af6 1514 *descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge 146:22da6e220af6 1515 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge 146:22da6e220af6 1516 return 0;
AnnaBridge 146:22da6e220af6 1517 }
AnnaBridge 146:22da6e220af6 1518
AnnaBridge 146:22da6e220af6 1519 /** \brief Set section Security attribute
AnnaBridge 146:22da6e220af6 1520
AnnaBridge 146:22da6e220af6 1521 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1522 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge 146:22da6e220af6 1523
AnnaBridge 146:22da6e220af6 1524 \return 0
AnnaBridge 146:22da6e220af6 1525 */
AnnaBridge 146:22da6e220af6 1526 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 146:22da6e220af6 1527 {
AnnaBridge 146:22da6e220af6 1528 *descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge 146:22da6e220af6 1529 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge 146:22da6e220af6 1530 return 0;
AnnaBridge 146:22da6e220af6 1531 }
AnnaBridge 146:22da6e220af6 1532
AnnaBridge 146:22da6e220af6 1533 /* Page 4k or 64k */
AnnaBridge 146:22da6e220af6 1534 /** \brief Set 4k/64k page execution-never attribute
AnnaBridge 146:22da6e220af6 1535
AnnaBridge 146:22da6e220af6 1536 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 146:22da6e220af6 1537 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 146:22da6e220af6 1538 \param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge 146:22da6e220af6 1539
AnnaBridge 146:22da6e220af6 1540 \return 0
AnnaBridge 146:22da6e220af6 1541 */
AnnaBridge 146:22da6e220af6 1542 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge 146:22da6e220af6 1543 {
AnnaBridge 146:22da6e220af6 1544 if (page == PAGE_4k)
AnnaBridge 146:22da6e220af6 1545 {
AnnaBridge 146:22da6e220af6 1546 *descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge 146:22da6e220af6 1547 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge 146:22da6e220af6 1548 }
AnnaBridge 146:22da6e220af6 1549 else
AnnaBridge 146:22da6e220af6 1550 {
AnnaBridge 146:22da6e220af6 1551 *descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge 146:22da6e220af6 1552 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge 146:22da6e220af6 1553 }
AnnaBridge 146:22da6e220af6 1554 return 0;
AnnaBridge 146:22da6e220af6 1555 }
AnnaBridge 146:22da6e220af6 1556
AnnaBridge 146:22da6e220af6 1557 /** \brief Set 4k/64k page domain
AnnaBridge 146:22da6e220af6 1558
AnnaBridge 146:22da6e220af6 1559 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1560 \param [in] domain Page domain
AnnaBridge 146:22da6e220af6 1561
AnnaBridge 146:22da6e220af6 1562 \return 0
AnnaBridge 146:22da6e220af6 1563 */
AnnaBridge 146:22da6e220af6 1564 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 146:22da6e220af6 1565 {
AnnaBridge 146:22da6e220af6 1566 *descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge 146:22da6e220af6 1567 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge 146:22da6e220af6 1568 return 0;
AnnaBridge 146:22da6e220af6 1569 }
AnnaBridge 146:22da6e220af6 1570
AnnaBridge 146:22da6e220af6 1571 /** \brief Set 4k/64k page parity check
AnnaBridge 146:22da6e220af6 1572
AnnaBridge 146:22da6e220af6 1573 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1574 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 146:22da6e220af6 1575
AnnaBridge 146:22da6e220af6 1576 \return 0
AnnaBridge 146:22da6e220af6 1577 */
AnnaBridge 146:22da6e220af6 1578 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 146:22da6e220af6 1579 {
AnnaBridge 146:22da6e220af6 1580 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 146:22da6e220af6 1581 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 146:22da6e220af6 1582 return 0;
AnnaBridge 146:22da6e220af6 1583 }
AnnaBridge 146:22da6e220af6 1584
AnnaBridge 146:22da6e220af6 1585 /** \brief Set 4k/64k page access privileges
AnnaBridge 146:22da6e220af6 1586
AnnaBridge 146:22da6e220af6 1587 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 146:22da6e220af6 1588 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 146:22da6e220af6 1589 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 146:22da6e220af6 1590 \param [in] afe Access flag enable
AnnaBridge 146:22da6e220af6 1591
AnnaBridge 146:22da6e220af6 1592 \return 0
AnnaBridge 146:22da6e220af6 1593 */
AnnaBridge 146:22da6e220af6 1594 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 146:22da6e220af6 1595 {
AnnaBridge 146:22da6e220af6 1596 uint32_t ap = 0;
AnnaBridge 146:22da6e220af6 1597
AnnaBridge 146:22da6e220af6 1598 if (afe == 0) { //full access
AnnaBridge 146:22da6e220af6 1599 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 146:22da6e220af6 1600 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 146:22da6e220af6 1601 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 146:22da6e220af6 1602 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 146:22da6e220af6 1603 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 146:22da6e220af6 1604 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge 146:22da6e220af6 1605 }
AnnaBridge 146:22da6e220af6 1606
AnnaBridge 146:22da6e220af6 1607 else { //Simplified access
AnnaBridge 146:22da6e220af6 1608 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 146:22da6e220af6 1609 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 146:22da6e220af6 1610 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 146:22da6e220af6 1611 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 146:22da6e220af6 1612 }
AnnaBridge 146:22da6e220af6 1613
AnnaBridge 146:22da6e220af6 1614 *descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge 146:22da6e220af6 1615 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge 146:22da6e220af6 1616 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge 146:22da6e220af6 1617
AnnaBridge 146:22da6e220af6 1618 return 0;
AnnaBridge 146:22da6e220af6 1619 }
AnnaBridge 146:22da6e220af6 1620
AnnaBridge 146:22da6e220af6 1621 /** \brief Set 4k/64k page shareability
AnnaBridge 146:22da6e220af6 1622
AnnaBridge 146:22da6e220af6 1623 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 146:22da6e220af6 1624 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge 146:22da6e220af6 1625
AnnaBridge 146:22da6e220af6 1626 \return 0
AnnaBridge 146:22da6e220af6 1627 */
AnnaBridge 146:22da6e220af6 1628 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge 146:22da6e220af6 1629 {
AnnaBridge 146:22da6e220af6 1630 *descriptor_l2 &= PAGE_S_MASK;
AnnaBridge 146:22da6e220af6 1631 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge 146:22da6e220af6 1632 return 0;
AnnaBridge 146:22da6e220af6 1633 }
AnnaBridge 146:22da6e220af6 1634
AnnaBridge 146:22da6e220af6 1635 /** \brief Set 4k/64k page Global attribute
AnnaBridge 146:22da6e220af6 1636
AnnaBridge 146:22da6e220af6 1637 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 146:22da6e220af6 1638 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge 146:22da6e220af6 1639
AnnaBridge 146:22da6e220af6 1640 \return 0
AnnaBridge 146:22da6e220af6 1641 */
AnnaBridge 146:22da6e220af6 1642 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge 146:22da6e220af6 1643 {
AnnaBridge 146:22da6e220af6 1644 *descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge 146:22da6e220af6 1645 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge 146:22da6e220af6 1646 return 0;
AnnaBridge 146:22da6e220af6 1647 }
AnnaBridge 146:22da6e220af6 1648
AnnaBridge 146:22da6e220af6 1649 /** \brief Set 4k/64k page Security attribute
AnnaBridge 146:22da6e220af6 1650
AnnaBridge 146:22da6e220af6 1651 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1652 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge 146:22da6e220af6 1653
AnnaBridge 146:22da6e220af6 1654 \return 0
AnnaBridge 146:22da6e220af6 1655 */
AnnaBridge 146:22da6e220af6 1656 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 146:22da6e220af6 1657 {
AnnaBridge 146:22da6e220af6 1658 *descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge 146:22da6e220af6 1659 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge 146:22da6e220af6 1660 return 0;
AnnaBridge 146:22da6e220af6 1661 }
AnnaBridge 146:22da6e220af6 1662
AnnaBridge 146:22da6e220af6 1663 /** \brief Set Section memory attributes
AnnaBridge 146:22da6e220af6 1664
AnnaBridge 146:22da6e220af6 1665 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 146:22da6e220af6 1666 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 146:22da6e220af6 1667 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 146:22da6e220af6 1668 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 146:22da6e220af6 1669
AnnaBridge 146:22da6e220af6 1670 \return 0
AnnaBridge 146:22da6e220af6 1671 */
AnnaBridge 146:22da6e220af6 1672 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge 146:22da6e220af6 1673 {
AnnaBridge 146:22da6e220af6 1674 *descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge 146:22da6e220af6 1675
AnnaBridge 146:22da6e220af6 1676 if (STRONGLY_ORDERED == mem)
AnnaBridge 146:22da6e220af6 1677 {
AnnaBridge 146:22da6e220af6 1678 return 0;
AnnaBridge 146:22da6e220af6 1679 }
AnnaBridge 146:22da6e220af6 1680 else if (SHARED_DEVICE == mem)
AnnaBridge 146:22da6e220af6 1681 {
AnnaBridge 146:22da6e220af6 1682 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 146:22da6e220af6 1683 }
AnnaBridge 146:22da6e220af6 1684 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 146:22da6e220af6 1685 {
AnnaBridge 146:22da6e220af6 1686 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
AnnaBridge 146:22da6e220af6 1687 }
AnnaBridge 146:22da6e220af6 1688 else if (NORMAL == mem)
AnnaBridge 146:22da6e220af6 1689 {
AnnaBridge 146:22da6e220af6 1690 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
AnnaBridge 146:22da6e220af6 1691 switch(inner)
AnnaBridge 146:22da6e220af6 1692 {
AnnaBridge 146:22da6e220af6 1693 case NON_CACHEABLE:
AnnaBridge 146:22da6e220af6 1694 break;
AnnaBridge 146:22da6e220af6 1695 case WB_WA:
AnnaBridge 146:22da6e220af6 1696 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 146:22da6e220af6 1697 break;
AnnaBridge 146:22da6e220af6 1698 case WT:
AnnaBridge 146:22da6e220af6 1699 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
AnnaBridge 146:22da6e220af6 1700 break;
AnnaBridge 146:22da6e220af6 1701 case WB_NO_WA:
AnnaBridge 146:22da6e220af6 1702 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
AnnaBridge 146:22da6e220af6 1703 break;
AnnaBridge 146:22da6e220af6 1704 }
AnnaBridge 146:22da6e220af6 1705 switch(outer)
AnnaBridge 146:22da6e220af6 1706 {
AnnaBridge 146:22da6e220af6 1707 case NON_CACHEABLE:
AnnaBridge 146:22da6e220af6 1708 break;
AnnaBridge 146:22da6e220af6 1709 case WB_WA:
AnnaBridge 146:22da6e220af6 1710 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
AnnaBridge 146:22da6e220af6 1711 break;
AnnaBridge 146:22da6e220af6 1712 case WT:
AnnaBridge 146:22da6e220af6 1713 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
AnnaBridge 146:22da6e220af6 1714 break;
AnnaBridge 146:22da6e220af6 1715 case WB_NO_WA:
AnnaBridge 146:22da6e220af6 1716 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
AnnaBridge 146:22da6e220af6 1717 break;
AnnaBridge 146:22da6e220af6 1718 }
AnnaBridge 146:22da6e220af6 1719 }
AnnaBridge 146:22da6e220af6 1720 return 0;
AnnaBridge 146:22da6e220af6 1721 }
AnnaBridge 146:22da6e220af6 1722
AnnaBridge 146:22da6e220af6 1723 /** \brief Set 4k/64k page memory attributes
AnnaBridge 146:22da6e220af6 1724
AnnaBridge 146:22da6e220af6 1725 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 146:22da6e220af6 1726 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 146:22da6e220af6 1727 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 146:22da6e220af6 1728 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 146:22da6e220af6 1729 \param [in] page Page size
AnnaBridge 146:22da6e220af6 1730
AnnaBridge 146:22da6e220af6 1731 \return 0
AnnaBridge 146:22da6e220af6 1732 */
AnnaBridge 146:22da6e220af6 1733 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge 146:22da6e220af6 1734 {
AnnaBridge 146:22da6e220af6 1735 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge 146:22da6e220af6 1736
AnnaBridge 146:22da6e220af6 1737 if (page == PAGE_64k)
AnnaBridge 146:22da6e220af6 1738 {
AnnaBridge 146:22da6e220af6 1739 //same as section
AnnaBridge 146:22da6e220af6 1740 MMU_MemorySection(descriptor_l2, mem, outer, inner);
AnnaBridge 146:22da6e220af6 1741 }
AnnaBridge 146:22da6e220af6 1742 else
AnnaBridge 146:22da6e220af6 1743 {
AnnaBridge 146:22da6e220af6 1744 if (STRONGLY_ORDERED == mem)
AnnaBridge 146:22da6e220af6 1745 {
AnnaBridge 146:22da6e220af6 1746 return 0;
AnnaBridge 146:22da6e220af6 1747 }
AnnaBridge 146:22da6e220af6 1748 else if (SHARED_DEVICE == mem)
AnnaBridge 146:22da6e220af6 1749 {
AnnaBridge 146:22da6e220af6 1750 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 146:22da6e220af6 1751 }
AnnaBridge 146:22da6e220af6 1752 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 146:22da6e220af6 1753 {
AnnaBridge 146:22da6e220af6 1754 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge 146:22da6e220af6 1755 }
AnnaBridge 146:22da6e220af6 1756 else if (NORMAL == mem)
AnnaBridge 146:22da6e220af6 1757 {
AnnaBridge 146:22da6e220af6 1758 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge 146:22da6e220af6 1759 switch(inner)
AnnaBridge 146:22da6e220af6 1760 {
AnnaBridge 146:22da6e220af6 1761 case NON_CACHEABLE:
AnnaBridge 146:22da6e220af6 1762 break;
AnnaBridge 146:22da6e220af6 1763 case WB_WA:
AnnaBridge 146:22da6e220af6 1764 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 146:22da6e220af6 1765 break;
AnnaBridge 146:22da6e220af6 1766 case WT:
AnnaBridge 146:22da6e220af6 1767 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
AnnaBridge 146:22da6e220af6 1768 break;
AnnaBridge 146:22da6e220af6 1769 case WB_NO_WA:
AnnaBridge 146:22da6e220af6 1770 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
AnnaBridge 146:22da6e220af6 1771 break;
AnnaBridge 146:22da6e220af6 1772 }
AnnaBridge 146:22da6e220af6 1773 switch(outer)
AnnaBridge 146:22da6e220af6 1774 {
AnnaBridge 146:22da6e220af6 1775 case NON_CACHEABLE:
AnnaBridge 146:22da6e220af6 1776 break;
AnnaBridge 146:22da6e220af6 1777 case WB_WA:
AnnaBridge 146:22da6e220af6 1778 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 146:22da6e220af6 1779 break;
AnnaBridge 146:22da6e220af6 1780 case WT:
AnnaBridge 146:22da6e220af6 1781 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge 146:22da6e220af6 1782 break;
AnnaBridge 146:22da6e220af6 1783 case WB_NO_WA:
AnnaBridge 146:22da6e220af6 1784 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 146:22da6e220af6 1785 break;
AnnaBridge 146:22da6e220af6 1786 }
AnnaBridge 146:22da6e220af6 1787 }
AnnaBridge 146:22da6e220af6 1788 }
AnnaBridge 146:22da6e220af6 1789
AnnaBridge 146:22da6e220af6 1790 return 0;
AnnaBridge 146:22da6e220af6 1791 }
AnnaBridge 146:22da6e220af6 1792
AnnaBridge 146:22da6e220af6 1793 /** \brief Create a L1 section descriptor
AnnaBridge 146:22da6e220af6 1794
AnnaBridge 146:22da6e220af6 1795 \param [out] descriptor L1 descriptor
AnnaBridge 146:22da6e220af6 1796 \param [in] reg Section attributes
AnnaBridge 146:22da6e220af6 1797
AnnaBridge 146:22da6e220af6 1798 \return 0
AnnaBridge 146:22da6e220af6 1799 */
AnnaBridge 146:22da6e220af6 1800 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge 146:22da6e220af6 1801 {
AnnaBridge 146:22da6e220af6 1802 *descriptor = 0;
AnnaBridge 146:22da6e220af6 1803
AnnaBridge 146:22da6e220af6 1804 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge 146:22da6e220af6 1805 MMU_XNSection(descriptor,reg.xn_t);
AnnaBridge 146:22da6e220af6 1806 MMU_DomainSection(descriptor, reg.domain);
AnnaBridge 146:22da6e220af6 1807 MMU_PSection(descriptor, reg.e_t);
AnnaBridge 146:22da6e220af6 1808 MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge 146:22da6e220af6 1809 MMU_SharedSection(descriptor,reg.sh_t);
AnnaBridge 146:22da6e220af6 1810 MMU_GlobalSection(descriptor,reg.g_t);
AnnaBridge 146:22da6e220af6 1811 MMU_SecureSection(descriptor,reg.sec_t);
AnnaBridge 146:22da6e220af6 1812 *descriptor &= SECTION_MASK;
AnnaBridge 146:22da6e220af6 1813 *descriptor |= SECTION_DESCRIPTOR;
AnnaBridge 146:22da6e220af6 1814
AnnaBridge 146:22da6e220af6 1815 return 0;
AnnaBridge 146:22da6e220af6 1816 }
AnnaBridge 146:22da6e220af6 1817
AnnaBridge 146:22da6e220af6 1818
AnnaBridge 146:22da6e220af6 1819 /** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge 146:22da6e220af6 1820
AnnaBridge 146:22da6e220af6 1821 \param [out] descriptor L1 descriptor
AnnaBridge 146:22da6e220af6 1822 \param [out] descriptor2 L2 descriptor
AnnaBridge 146:22da6e220af6 1823 \param [in] reg 4k/64k page attributes
AnnaBridge 146:22da6e220af6 1824
AnnaBridge 146:22da6e220af6 1825 \return 0
AnnaBridge 146:22da6e220af6 1826 */
AnnaBridge 146:22da6e220af6 1827 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
AnnaBridge 146:22da6e220af6 1828 {
AnnaBridge 146:22da6e220af6 1829 *descriptor = 0;
AnnaBridge 146:22da6e220af6 1830 *descriptor2 = 0;
AnnaBridge 146:22da6e220af6 1831
AnnaBridge 146:22da6e220af6 1832 switch (reg.rg_t)
AnnaBridge 146:22da6e220af6 1833 {
AnnaBridge 146:22da6e220af6 1834 case PAGE_4k:
AnnaBridge 146:22da6e220af6 1835 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge 146:22da6e220af6 1836 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge 146:22da6e220af6 1837 MMU_DomainPage(descriptor, reg.domain);
AnnaBridge 146:22da6e220af6 1838 MMU_PPage(descriptor, reg.e_t);
AnnaBridge 146:22da6e220af6 1839 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 146:22da6e220af6 1840 MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge 146:22da6e220af6 1841 MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge 146:22da6e220af6 1842 MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge 146:22da6e220af6 1843 *descriptor &= PAGE_L1_MASK;
AnnaBridge 146:22da6e220af6 1844 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 146:22da6e220af6 1845 *descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge 146:22da6e220af6 1846 *descriptor2 |= PAGE_L2_4K_DESC;
AnnaBridge 146:22da6e220af6 1847 break;
AnnaBridge 146:22da6e220af6 1848
AnnaBridge 146:22da6e220af6 1849 case PAGE_64k:
AnnaBridge 146:22da6e220af6 1850 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge 146:22da6e220af6 1851 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge 146:22da6e220af6 1852 MMU_DomainPage(descriptor, reg.domain);
AnnaBridge 146:22da6e220af6 1853 MMU_PPage(descriptor, reg.e_t);
AnnaBridge 146:22da6e220af6 1854 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 146:22da6e220af6 1855 MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge 146:22da6e220af6 1856 MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge 146:22da6e220af6 1857 MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge 146:22da6e220af6 1858 *descriptor &= PAGE_L1_MASK;
AnnaBridge 146:22da6e220af6 1859 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 146:22da6e220af6 1860 *descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge 146:22da6e220af6 1861 *descriptor2 |= PAGE_L2_64K_DESC;
AnnaBridge 146:22da6e220af6 1862 break;
AnnaBridge 146:22da6e220af6 1863
AnnaBridge 146:22da6e220af6 1864 case SECTION:
AnnaBridge 146:22da6e220af6 1865 //error
AnnaBridge 146:22da6e220af6 1866 break;
AnnaBridge 146:22da6e220af6 1867 }
AnnaBridge 146:22da6e220af6 1868
AnnaBridge 146:22da6e220af6 1869 return 0;
AnnaBridge 146:22da6e220af6 1870 }
AnnaBridge 146:22da6e220af6 1871
AnnaBridge 146:22da6e220af6 1872 /** \brief Create a 1MB Section
AnnaBridge 146:22da6e220af6 1873
AnnaBridge 146:22da6e220af6 1874 \param [in] ttb Translation table base address
AnnaBridge 146:22da6e220af6 1875 \param [in] base_address Section base address
AnnaBridge 146:22da6e220af6 1876 \param [in] count Number of sections to create
AnnaBridge 146:22da6e220af6 1877 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 146:22da6e220af6 1878
AnnaBridge 146:22da6e220af6 1879 */
AnnaBridge 146:22da6e220af6 1880 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge 146:22da6e220af6 1881 {
AnnaBridge 146:22da6e220af6 1882 uint32_t offset;
AnnaBridge 146:22da6e220af6 1883 uint32_t entry;
AnnaBridge 146:22da6e220af6 1884 uint32_t i;
AnnaBridge 146:22da6e220af6 1885
AnnaBridge 146:22da6e220af6 1886 offset = base_address >> 20;
AnnaBridge 146:22da6e220af6 1887 entry = (base_address & 0xFFF00000) | descriptor_l1;
AnnaBridge 146:22da6e220af6 1888
AnnaBridge 146:22da6e220af6 1889 //4 bytes aligned
AnnaBridge 146:22da6e220af6 1890 ttb = ttb + offset;
AnnaBridge 146:22da6e220af6 1891
AnnaBridge 146:22da6e220af6 1892 for (i = 0; i < count; i++ )
AnnaBridge 146:22da6e220af6 1893 {
AnnaBridge 146:22da6e220af6 1894 //4 bytes aligned
AnnaBridge 146:22da6e220af6 1895 *ttb++ = entry;
AnnaBridge 146:22da6e220af6 1896 entry += OFFSET_1M;
AnnaBridge 146:22da6e220af6 1897 }
AnnaBridge 146:22da6e220af6 1898 }
AnnaBridge 146:22da6e220af6 1899
AnnaBridge 146:22da6e220af6 1900 /** \brief Create a 4k page entry
AnnaBridge 146:22da6e220af6 1901
AnnaBridge 146:22da6e220af6 1902 \param [in] ttb L1 table base address
AnnaBridge 146:22da6e220af6 1903 \param [in] base_address 4k base address
AnnaBridge 146:22da6e220af6 1904 \param [in] count Number of 4k pages to create
AnnaBridge 146:22da6e220af6 1905 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 146:22da6e220af6 1906 \param [in] ttb_l2 L2 table base address
AnnaBridge 146:22da6e220af6 1907 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 146:22da6e220af6 1908
AnnaBridge 146:22da6e220af6 1909 */
AnnaBridge 146:22da6e220af6 1910 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 146:22da6e220af6 1911 {
AnnaBridge 146:22da6e220af6 1912
AnnaBridge 146:22da6e220af6 1913 uint32_t offset, offset2;
AnnaBridge 146:22da6e220af6 1914 uint32_t entry, entry2;
AnnaBridge 146:22da6e220af6 1915 uint32_t i;
AnnaBridge 146:22da6e220af6 1916
AnnaBridge 146:22da6e220af6 1917 offset = base_address >> 20;
AnnaBridge 146:22da6e220af6 1918 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 146:22da6e220af6 1919
AnnaBridge 146:22da6e220af6 1920 //4 bytes aligned
AnnaBridge 146:22da6e220af6 1921 ttb += offset;
AnnaBridge 146:22da6e220af6 1922 //create l1_entry
AnnaBridge 146:22da6e220af6 1923 *ttb = entry;
AnnaBridge 146:22da6e220af6 1924
AnnaBridge 146:22da6e220af6 1925 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 146:22da6e220af6 1926 ttb_l2 += offset2;
AnnaBridge 146:22da6e220af6 1927 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
AnnaBridge 146:22da6e220af6 1928 for (i = 0; i < count; i++ )
AnnaBridge 146:22da6e220af6 1929 {
AnnaBridge 146:22da6e220af6 1930 //4 bytes aligned
AnnaBridge 146:22da6e220af6 1931 *ttb_l2++ = entry2;
AnnaBridge 146:22da6e220af6 1932 entry2 += OFFSET_4K;
AnnaBridge 146:22da6e220af6 1933 }
AnnaBridge 146:22da6e220af6 1934 }
AnnaBridge 146:22da6e220af6 1935
AnnaBridge 146:22da6e220af6 1936 /** \brief Create a 64k page entry
AnnaBridge 146:22da6e220af6 1937
AnnaBridge 146:22da6e220af6 1938 \param [in] ttb L1 table base address
AnnaBridge 146:22da6e220af6 1939 \param [in] base_address 64k base address
AnnaBridge 146:22da6e220af6 1940 \param [in] count Number of 64k pages to create
AnnaBridge 146:22da6e220af6 1941 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 146:22da6e220af6 1942 \param [in] ttb_l2 L2 table base address
AnnaBridge 146:22da6e220af6 1943 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 146:22da6e220af6 1944
AnnaBridge 146:22da6e220af6 1945 */
AnnaBridge 146:22da6e220af6 1946 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 146:22da6e220af6 1947 {
AnnaBridge 146:22da6e220af6 1948 uint32_t offset, offset2;
AnnaBridge 146:22da6e220af6 1949 uint32_t entry, entry2;
AnnaBridge 146:22da6e220af6 1950 uint32_t i,j;
AnnaBridge 146:22da6e220af6 1951
AnnaBridge 146:22da6e220af6 1952
AnnaBridge 146:22da6e220af6 1953 offset = base_address >> 20;
AnnaBridge 146:22da6e220af6 1954 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 146:22da6e220af6 1955
AnnaBridge 146:22da6e220af6 1956 //4 bytes aligned
AnnaBridge 146:22da6e220af6 1957 ttb += offset;
AnnaBridge 146:22da6e220af6 1958 //create l1_entry
AnnaBridge 146:22da6e220af6 1959 *ttb = entry;
AnnaBridge 146:22da6e220af6 1960
AnnaBridge 146:22da6e220af6 1961 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 146:22da6e220af6 1962 ttb_l2 += offset2;
AnnaBridge 146:22da6e220af6 1963 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
AnnaBridge 146:22da6e220af6 1964 for (i = 0; i < count; i++ )
AnnaBridge 146:22da6e220af6 1965 {
AnnaBridge 146:22da6e220af6 1966 //create 16 entries
AnnaBridge 146:22da6e220af6 1967 for (j = 0; j < 16; j++)
AnnaBridge 146:22da6e220af6 1968 {
AnnaBridge 146:22da6e220af6 1969 //4 bytes aligned
AnnaBridge 146:22da6e220af6 1970 *ttb_l2++ = entry2;
AnnaBridge 146:22da6e220af6 1971 }
AnnaBridge 146:22da6e220af6 1972 entry2 += OFFSET_64K;
AnnaBridge 146:22da6e220af6 1973 }
AnnaBridge 146:22da6e220af6 1974 }
AnnaBridge 146:22da6e220af6 1975
AnnaBridge 146:22da6e220af6 1976 /** \brief Enable MMU
AnnaBridge 146:22da6e220af6 1977
AnnaBridge 146:22da6e220af6 1978 Enable MMU
AnnaBridge 146:22da6e220af6 1979 */
AnnaBridge 146:22da6e220af6 1980 __STATIC_INLINE void MMU_Enable(void) {
AnnaBridge 146:22da6e220af6 1981 // Set M bit 0 to enable the MMU
AnnaBridge 146:22da6e220af6 1982 // Set AFE bit to enable simplified access permissions model
AnnaBridge 146:22da6e220af6 1983 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 146:22da6e220af6 1984 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 146:22da6e220af6 1985 __ISB();
AnnaBridge 146:22da6e220af6 1986 }
AnnaBridge 146:22da6e220af6 1987
AnnaBridge 146:22da6e220af6 1988 /** \brief Disable MMU
AnnaBridge 146:22da6e220af6 1989
AnnaBridge 146:22da6e220af6 1990 Disable MMU
AnnaBridge 146:22da6e220af6 1991 */
AnnaBridge 146:22da6e220af6 1992 __STATIC_INLINE void MMU_Disable(void) {
AnnaBridge 146:22da6e220af6 1993 // Clear M bit 0 to disable the MMU
AnnaBridge 146:22da6e220af6 1994 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 146:22da6e220af6 1995 __ISB();
AnnaBridge 146:22da6e220af6 1996 }
AnnaBridge 146:22da6e220af6 1997
AnnaBridge 146:22da6e220af6 1998 /** \brief Invalidate entire unified TLB
AnnaBridge 146:22da6e220af6 1999
AnnaBridge 146:22da6e220af6 2000 TLBIALL. Invalidate entire unified TLB
AnnaBridge 146:22da6e220af6 2001 */
AnnaBridge 146:22da6e220af6 2002
AnnaBridge 146:22da6e220af6 2003 __STATIC_INLINE void MMU_InvalidateTLB(void) {
AnnaBridge 146:22da6e220af6 2004 __set_TLBIALL(0);
AnnaBridge 146:22da6e220af6 2005 __DSB(); //ensure completion of the invalidation
AnnaBridge 146:22da6e220af6 2006 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 146:22da6e220af6 2007 }
AnnaBridge 146:22da6e220af6 2008
AnnaBridge 146:22da6e220af6 2009
AnnaBridge 146:22da6e220af6 2010 #ifdef __cplusplus
AnnaBridge 146:22da6e220af6 2011 }
AnnaBridge 146:22da6e220af6 2012 #endif
AnnaBridge 146:22da6e220af6 2013
AnnaBridge 146:22da6e220af6 2014 #endif /* __CORE_CA_H_DEPENDANT */
AnnaBridge 146:22da6e220af6 2015
AnnaBridge 146:22da6e220af6 2016 #endif /* __CMSIS_GENERIC */