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TARGET_UBLOX_EVA_NINA/core_cm0.h@151:675da3299148, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:46:57 2017 +0100
Revision:
151:675da3299148
Parent:
145:64910690c574 
Release 151 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 132:9baf128c2fab 1 /**************************************************************************//**
<> 132:9baf128c2fab 2 * @file core_cm0.h
<> 132:9baf128c2fab 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
AnnaBridge 145:64910690c574 4 * @version V5.0.2
AnnaBridge 145:64910690c574 5 * @date 13. February 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
<> 132:9baf128c2fab 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
<> 132:9baf128c2fab 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
<> 132:9baf128c2fab 24
AnnaBridge 145:64910690c574 25 #if defined ( __ICCARM__ )
AnnaBridge 145:64910690c574 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 145:64910690c574 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 28 #pragma clang system_header /* treat file as system include file */
<> 132:9baf128c2fab 29 #endif
<> 132:9baf128c2fab 30
<> 132:9baf128c2fab 31 #ifndef __CORE_CM0_H_GENERIC
<> 132:9baf128c2fab 32 #define __CORE_CM0_H_GENERIC
<> 132:9baf128c2fab 33
AnnaBridge 145:64910690c574 34 #include <stdint.h>
AnnaBridge 145:64910690c574 35
<> 132:9baf128c2fab 36 #ifdef __cplusplus
<> 132:9baf128c2fab 37 extern "C" {
<> 132:9baf128c2fab 38 #endif
<> 132:9baf128c2fab 39
AnnaBridge 145:64910690c574 40 /**
AnnaBridge 145:64910690c574 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 132:9baf128c2fab 42 CMSIS violates the following MISRA-C:2004 rules:
<> 132:9baf128c2fab 43
<> 132:9baf128c2fab 44 \li Required Rule 8.5, object/function definition in header file.<br>
<> 132:9baf128c2fab 45 Function definitions in header files are used to allow 'inlining'.
<> 132:9baf128c2fab 46
<> 132:9baf128c2fab 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 132:9baf128c2fab 48 Unions are used for effective representation of core registers.
<> 132:9baf128c2fab 49
<> 132:9baf128c2fab 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 132:9baf128c2fab 51 Function-like macros are used to allow more efficient code.
<> 132:9baf128c2fab 52 */
<> 132:9baf128c2fab 53
<> 132:9baf128c2fab 54
<> 132:9baf128c2fab 55 /*******************************************************************************
<> 132:9baf128c2fab 56 * CMSIS definitions
<> 132:9baf128c2fab 57 ******************************************************************************/
AnnaBridge 145:64910690c574 58 /**
AnnaBridge 145:64910690c574 59 \ingroup Cortex_M0
<> 132:9baf128c2fab 60 @{
<> 132:9baf128c2fab 61 */
<> 132:9baf128c2fab 62
<> 132:9baf128c2fab 63 /* CMSIS CM0 definitions */
AnnaBridge 145:64910690c574 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 145:64910690c574 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 145:64910690c574 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 145:64910690c574 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 132:9baf128c2fab 68
AnnaBridge 145:64910690c574 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
<> 132:9baf128c2fab 70
<> 132:9baf128c2fab 71 /** __FPU_USED indicates whether an FPU is used or not.
<> 132:9baf128c2fab 72 This core does not support an FPU at all
<> 132:9baf128c2fab 73 */
AnnaBridge 145:64910690c574 74 #define __FPU_USED 0U
<> 132:9baf128c2fab 75
<> 132:9baf128c2fab 76 #if defined ( __CC_ARM )
<> 132:9baf128c2fab 77 #if defined __TARGET_FPU_VFP
AnnaBridge 145:64910690c574 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 79 #endif
AnnaBridge 145:64910690c574 80
AnnaBridge 145:64910690c574 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 82 #if defined __ARM_PCS_VFP
AnnaBridge 145:64910690c574 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 84 #endif
<> 132:9baf128c2fab 85
<> 132:9baf128c2fab 86 #elif defined ( __GNUC__ )
<> 132:9baf128c2fab 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 145:64910690c574 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 89 #endif
<> 132:9baf128c2fab 90
<> 132:9baf128c2fab 91 #elif defined ( __ICCARM__ )
<> 132:9baf128c2fab 92 #if defined __ARMVFP__
AnnaBridge 145:64910690c574 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 94 #endif
<> 132:9baf128c2fab 95
AnnaBridge 145:64910690c574 96 #elif defined ( __TI_ARM__ )
AnnaBridge 145:64910690c574 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 145:64910690c574 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 99 #endif
<> 132:9baf128c2fab 100
<> 132:9baf128c2fab 101 #elif defined ( __TASKING__ )
<> 132:9baf128c2fab 102 #if defined __FPU_VFP__
<> 132:9baf128c2fab 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 104 #endif
<> 132:9baf128c2fab 105
AnnaBridge 145:64910690c574 106 #elif defined ( __CSMC__ )
AnnaBridge 145:64910690c574 107 #if ( __CSMC__ & 0x400U)
<> 132:9baf128c2fab 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 132:9baf128c2fab 109 #endif
AnnaBridge 145:64910690c574 110
<> 132:9baf128c2fab 111 #endif
<> 132:9baf128c2fab 112
AnnaBridge 145:64910690c574 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 114
<> 132:9baf128c2fab 115
<> 132:9baf128c2fab 116 #ifdef __cplusplus
<> 132:9baf128c2fab 117 }
<> 132:9baf128c2fab 118 #endif
<> 132:9baf128c2fab 119
<> 132:9baf128c2fab 120 #endif /* __CORE_CM0_H_GENERIC */
<> 132:9baf128c2fab 121
<> 132:9baf128c2fab 122 #ifndef __CMSIS_GENERIC
<> 132:9baf128c2fab 123
<> 132:9baf128c2fab 124 #ifndef __CORE_CM0_H_DEPENDANT
<> 132:9baf128c2fab 125 #define __CORE_CM0_H_DEPENDANT
<> 132:9baf128c2fab 126
<> 132:9baf128c2fab 127 #ifdef __cplusplus
<> 132:9baf128c2fab 128 extern "C" {
<> 132:9baf128c2fab 129 #endif
<> 132:9baf128c2fab 130
<> 132:9baf128c2fab 131 /* check device defines and use defaults */
<> 132:9baf128c2fab 132 #if defined __CHECK_DEVICE_DEFINES
<> 132:9baf128c2fab 133 #ifndef __CM0_REV
AnnaBridge 145:64910690c574 134 #define __CM0_REV 0x0000U
<> 132:9baf128c2fab 135 #warning "__CM0_REV not defined in device header file; using default!"
<> 132:9baf128c2fab 136 #endif
<> 132:9baf128c2fab 137
<> 132:9baf128c2fab 138 #ifndef __NVIC_PRIO_BITS
AnnaBridge 145:64910690c574 139 #define __NVIC_PRIO_BITS 2U
<> 132:9baf128c2fab 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 132:9baf128c2fab 141 #endif
<> 132:9baf128c2fab 142
<> 132:9baf128c2fab 143 #ifndef __Vendor_SysTickConfig
AnnaBridge 145:64910690c574 144 #define __Vendor_SysTickConfig 0U
<> 132:9baf128c2fab 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 132:9baf128c2fab 146 #endif
<> 132:9baf128c2fab 147 #endif
<> 132:9baf128c2fab 148
<> 132:9baf128c2fab 149 /* IO definitions (access restrictions to peripheral registers) */
<> 132:9baf128c2fab 150 /**
<> 132:9baf128c2fab 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 132:9baf128c2fab 152
<> 132:9baf128c2fab 153 <strong>IO Type Qualifiers</strong> are used
<> 132:9baf128c2fab 154 \li to specify the access to peripheral variables.
<> 132:9baf128c2fab 155 \li for automatic generation of peripheral register debug information.
<> 132:9baf128c2fab 156 */
<> 132:9baf128c2fab 157 #ifdef __cplusplus
AnnaBridge 145:64910690c574 158 #define __I volatile /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 159 #else
AnnaBridge 145:64910690c574 160 #define __I volatile const /*!< Defines 'read only' permissions */
<> 132:9baf128c2fab 161 #endif
AnnaBridge 145:64910690c574 162 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 145:64910690c574 163 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 132:9baf128c2fab 164
AnnaBridge 145:64910690c574 165 /* following defines should be used for structure members */
AnnaBridge 145:64910690c574 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 145:64910690c574 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 145:64910690c574 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
<> 132:9baf128c2fab 169
<> 132:9baf128c2fab 170 /*@} end of group Cortex_M0 */
<> 132:9baf128c2fab 171
<> 132:9baf128c2fab 172
<> 132:9baf128c2fab 173
<> 132:9baf128c2fab 174 /*******************************************************************************
<> 132:9baf128c2fab 175 * Register Abstraction
<> 132:9baf128c2fab 176 Core Register contain:
<> 132:9baf128c2fab 177 - Core Register
<> 132:9baf128c2fab 178 - Core NVIC Register
<> 132:9baf128c2fab 179 - Core SCB Register
<> 132:9baf128c2fab 180 - Core SysTick Register
<> 132:9baf128c2fab 181 ******************************************************************************/
AnnaBridge 145:64910690c574 182 /**
AnnaBridge 145:64910690c574 183 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 145:64910690c574 184 \brief Type definitions and defines for Cortex-M processor based devices.
<> 132:9baf128c2fab 185 */
<> 132:9baf128c2fab 186
AnnaBridge 145:64910690c574 187 /**
AnnaBridge 145:64910690c574 188 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 189 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 145:64910690c574 190 \brief Core Register type definitions.
<> 132:9baf128c2fab 191 @{
<> 132:9baf128c2fab 192 */
<> 132:9baf128c2fab 193
AnnaBridge 145:64910690c574 194 /**
AnnaBridge 145:64910690c574 195 \brief Union type to access the Application Program Status Register (APSR).
<> 132:9baf128c2fab 196 */
<> 132:9baf128c2fab 197 typedef union
<> 132:9baf128c2fab 198 {
<> 132:9baf128c2fab 199 struct
<> 132:9baf128c2fab 200 {
AnnaBridge 145:64910690c574 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 145:64910690c574 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 206 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 207 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 208 } APSR_Type;
<> 132:9baf128c2fab 209
<> 132:9baf128c2fab 210 /* APSR Register Definitions */
AnnaBridge 145:64910690c574 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
<> 132:9baf128c2fab 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 132:9baf128c2fab 213
AnnaBridge 145:64910690c574 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
<> 132:9baf128c2fab 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 132:9baf128c2fab 216
AnnaBridge 145:64910690c574 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
<> 132:9baf128c2fab 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 132:9baf128c2fab 219
AnnaBridge 145:64910690c574 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
<> 132:9baf128c2fab 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 132:9baf128c2fab 222
<> 132:9baf128c2fab 223
AnnaBridge 145:64910690c574 224 /**
AnnaBridge 145:64910690c574 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 132:9baf128c2fab 226 */
<> 132:9baf128c2fab 227 typedef union
<> 132:9baf128c2fab 228 {
<> 132:9baf128c2fab 229 struct
<> 132:9baf128c2fab 230 {
AnnaBridge 145:64910690c574 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 145:64910690c574 233 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 234 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 235 } IPSR_Type;
<> 132:9baf128c2fab 236
<> 132:9baf128c2fab 237 /* IPSR Register Definitions */
AnnaBridge 145:64910690c574 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
<> 132:9baf128c2fab 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 132:9baf128c2fab 240
<> 132:9baf128c2fab 241
AnnaBridge 145:64910690c574 242 /**
AnnaBridge 145:64910690c574 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 132:9baf128c2fab 244 */
<> 132:9baf128c2fab 245 typedef union
<> 132:9baf128c2fab 246 {
<> 132:9baf128c2fab 247 struct
<> 132:9baf128c2fab 248 {
AnnaBridge 145:64910690c574 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 145:64910690c574 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 145:64910690c574 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 145:64910690c574 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 257 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 258 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 259 } xPSR_Type;
<> 132:9baf128c2fab 260
<> 132:9baf128c2fab 261 /* xPSR Register Definitions */
AnnaBridge 145:64910690c574 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
<> 132:9baf128c2fab 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 132:9baf128c2fab 264
AnnaBridge 145:64910690c574 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
<> 132:9baf128c2fab 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 132:9baf128c2fab 267
AnnaBridge 145:64910690c574 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
<> 132:9baf128c2fab 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 132:9baf128c2fab 270
AnnaBridge 145:64910690c574 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
<> 132:9baf128c2fab 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 132:9baf128c2fab 273
AnnaBridge 145:64910690c574 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
<> 132:9baf128c2fab 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 132:9baf128c2fab 276
AnnaBridge 145:64910690c574 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
<> 132:9baf128c2fab 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 132:9baf128c2fab 279
<> 132:9baf128c2fab 280
AnnaBridge 145:64910690c574 281 /**
AnnaBridge 145:64910690c574 282 \brief Union type to access the Control Registers (CONTROL).
<> 132:9baf128c2fab 283 */
<> 132:9baf128c2fab 284 typedef union
<> 132:9baf128c2fab 285 {
<> 132:9baf128c2fab 286 struct
<> 132:9baf128c2fab 287 {
AnnaBridge 145:64910690c574 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 145:64910690c574 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 145:64910690c574 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 145:64910690c574 291 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 292 uint32_t w; /*!< Type used for word access */
<> 132:9baf128c2fab 293 } CONTROL_Type;
<> 132:9baf128c2fab 294
<> 132:9baf128c2fab 295 /* CONTROL Register Definitions */
AnnaBridge 145:64910690c574 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
<> 132:9baf128c2fab 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 132:9baf128c2fab 298
<> 132:9baf128c2fab 299 /*@} end of group CMSIS_CORE */
<> 132:9baf128c2fab 300
<> 132:9baf128c2fab 301
AnnaBridge 145:64910690c574 302 /**
AnnaBridge 145:64910690c574 303 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 145:64910690c574 305 \brief Type definitions for the NVIC Registers
<> 132:9baf128c2fab 306 @{
<> 132:9baf128c2fab 307 */
<> 132:9baf128c2fab 308
AnnaBridge 145:64910690c574 309 /**
AnnaBridge 145:64910690c574 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 132:9baf128c2fab 311 */
<> 132:9baf128c2fab 312 typedef struct
<> 132:9baf128c2fab 313 {
AnnaBridge 145:64910690c574 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 145:64910690c574 315 uint32_t RESERVED0[31U];
AnnaBridge 145:64910690c574 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 145:64910690c574 317 uint32_t RSERVED1[31U];
AnnaBridge 145:64910690c574 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 145:64910690c574 319 uint32_t RESERVED2[31U];
AnnaBridge 145:64910690c574 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 145:64910690c574 321 uint32_t RESERVED3[31U];
AnnaBridge 145:64910690c574 322 uint32_t RESERVED4[64U];
AnnaBridge 145:64910690c574 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 132:9baf128c2fab 324 } NVIC_Type;
<> 132:9baf128c2fab 325
<> 132:9baf128c2fab 326 /*@} end of group CMSIS_NVIC */
<> 132:9baf128c2fab 327
<> 132:9baf128c2fab 328
AnnaBridge 145:64910690c574 329 /**
AnnaBridge 145:64910690c574 330 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 331 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 145:64910690c574 332 \brief Type definitions for the System Control Block Registers
<> 132:9baf128c2fab 333 @{
<> 132:9baf128c2fab 334 */
<> 132:9baf128c2fab 335
AnnaBridge 145:64910690c574 336 /**
AnnaBridge 145:64910690c574 337 \brief Structure type to access the System Control Block (SCB).
<> 132:9baf128c2fab 338 */
<> 132:9baf128c2fab 339 typedef struct
<> 132:9baf128c2fab 340 {
AnnaBridge 145:64910690c574 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 145:64910690c574 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 145:64910690c574 343 uint32_t RESERVED0;
AnnaBridge 145:64910690c574 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 145:64910690c574 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 145:64910690c574 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 145:64910690c574 347 uint32_t RESERVED1;
AnnaBridge 145:64910690c574 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 145:64910690c574 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 132:9baf128c2fab 350 } SCB_Type;
<> 132:9baf128c2fab 351
<> 132:9baf128c2fab 352 /* SCB CPUID Register Definitions */
AnnaBridge 145:64910690c574 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
<> 132:9baf128c2fab 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 132:9baf128c2fab 355
AnnaBridge 145:64910690c574 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
<> 132:9baf128c2fab 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 132:9baf128c2fab 358
AnnaBridge 145:64910690c574 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
<> 132:9baf128c2fab 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 132:9baf128c2fab 361
AnnaBridge 145:64910690c574 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
<> 132:9baf128c2fab 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 132:9baf128c2fab 364
AnnaBridge 145:64910690c574 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
<> 132:9baf128c2fab 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 132:9baf128c2fab 367
<> 132:9baf128c2fab 368 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
<> 132:9baf128c2fab 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 132:9baf128c2fab 371
AnnaBridge 145:64910690c574 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
<> 132:9baf128c2fab 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 132:9baf128c2fab 374
AnnaBridge 145:64910690c574 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
<> 132:9baf128c2fab 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 132:9baf128c2fab 377
AnnaBridge 145:64910690c574 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
<> 132:9baf128c2fab 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 132:9baf128c2fab 380
AnnaBridge 145:64910690c574 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
<> 132:9baf128c2fab 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 132:9baf128c2fab 383
AnnaBridge 145:64910690c574 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
<> 132:9baf128c2fab 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 132:9baf128c2fab 386
AnnaBridge 145:64910690c574 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
<> 132:9baf128c2fab 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 132:9baf128c2fab 389
AnnaBridge 145:64910690c574 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
<> 132:9baf128c2fab 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 132:9baf128c2fab 392
AnnaBridge 145:64910690c574 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
<> 132:9baf128c2fab 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 132:9baf128c2fab 395
<> 132:9baf128c2fab 396 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 145:64910690c574 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
<> 132:9baf128c2fab 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 132:9baf128c2fab 399
AnnaBridge 145:64910690c574 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 132:9baf128c2fab 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 132:9baf128c2fab 402
AnnaBridge 145:64910690c574 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
<> 132:9baf128c2fab 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 132:9baf128c2fab 405
AnnaBridge 145:64910690c574 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
<> 132:9baf128c2fab 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 132:9baf128c2fab 408
AnnaBridge 145:64910690c574 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 132:9baf128c2fab 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 132:9baf128c2fab 411
<> 132:9baf128c2fab 412 /* SCB System Control Register Definitions */
AnnaBridge 145:64910690c574 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
<> 132:9baf128c2fab 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 132:9baf128c2fab 415
AnnaBridge 145:64910690c574 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
<> 132:9baf128c2fab 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 132:9baf128c2fab 418
AnnaBridge 145:64910690c574 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
<> 132:9baf128c2fab 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 132:9baf128c2fab 421
<> 132:9baf128c2fab 422 /* SCB Configuration Control Register Definitions */
AnnaBridge 145:64910690c574 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
<> 132:9baf128c2fab 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 132:9baf128c2fab 425
AnnaBridge 145:64910690c574 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
<> 132:9baf128c2fab 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 132:9baf128c2fab 428
<> 132:9baf128c2fab 429 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 145:64910690c574 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
<> 132:9baf128c2fab 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 132:9baf128c2fab 432
<> 132:9baf128c2fab 433 /*@} end of group CMSIS_SCB */
<> 132:9baf128c2fab 434
<> 132:9baf128c2fab 435
AnnaBridge 145:64910690c574 436 /**
AnnaBridge 145:64910690c574 437 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 145:64910690c574 439 \brief Type definitions for the System Timer Registers.
<> 132:9baf128c2fab 440 @{
<> 132:9baf128c2fab 441 */
<> 132:9baf128c2fab 442
AnnaBridge 145:64910690c574 443 /**
AnnaBridge 145:64910690c574 444 \brief Structure type to access the System Timer (SysTick).
<> 132:9baf128c2fab 445 */
<> 132:9baf128c2fab 446 typedef struct
<> 132:9baf128c2fab 447 {
AnnaBridge 145:64910690c574 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 145:64910690c574 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 145:64910690c574 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 145:64910690c574 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 132:9baf128c2fab 452 } SysTick_Type;
<> 132:9baf128c2fab 453
<> 132:9baf128c2fab 454 /* SysTick Control / Status Register Definitions */
AnnaBridge 145:64910690c574 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
<> 132:9baf128c2fab 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 132:9baf128c2fab 457
AnnaBridge 145:64910690c574 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
<> 132:9baf128c2fab 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 132:9baf128c2fab 460
AnnaBridge 145:64910690c574 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
<> 132:9baf128c2fab 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 132:9baf128c2fab 463
AnnaBridge 145:64910690c574 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
<> 132:9baf128c2fab 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 132:9baf128c2fab 466
<> 132:9baf128c2fab 467 /* SysTick Reload Register Definitions */
AnnaBridge 145:64910690c574 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
<> 132:9baf128c2fab 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 132:9baf128c2fab 470
<> 132:9baf128c2fab 471 /* SysTick Current Register Definitions */
AnnaBridge 145:64910690c574 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
<> 132:9baf128c2fab 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 132:9baf128c2fab 474
<> 132:9baf128c2fab 475 /* SysTick Calibration Register Definitions */
AnnaBridge 145:64910690c574 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
<> 132:9baf128c2fab 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 132:9baf128c2fab 478
AnnaBridge 145:64910690c574 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
<> 132:9baf128c2fab 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 132:9baf128c2fab 481
AnnaBridge 145:64910690c574 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
<> 132:9baf128c2fab 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 132:9baf128c2fab 484
<> 132:9baf128c2fab 485 /*@} end of group CMSIS_SysTick */
<> 132:9baf128c2fab 486
<> 132:9baf128c2fab 487
AnnaBridge 145:64910690c574 488 /**
AnnaBridge 145:64910690c574 489 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 145:64910690c574 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 145:64910690c574 492 Therefore they are not covered by the Cortex-M0 header file.
<> 132:9baf128c2fab 493 @{
<> 132:9baf128c2fab 494 */
<> 132:9baf128c2fab 495 /*@} end of group CMSIS_CoreDebug */
<> 132:9baf128c2fab 496
<> 132:9baf128c2fab 497
AnnaBridge 145:64910690c574 498 /**
AnnaBridge 145:64910690c574 499 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 500 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 145:64910690c574 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
<> 132:9baf128c2fab 502 @{
<> 132:9baf128c2fab 503 */
<> 132:9baf128c2fab 504
AnnaBridge 145:64910690c574 505 /**
AnnaBridge 145:64910690c574 506 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 145:64910690c574 507 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 509 \return Masked and shifted value.
AnnaBridge 145:64910690c574 510 */
AnnaBridge 145:64910690c574 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 145:64910690c574 512
AnnaBridge 145:64910690c574 513 /**
AnnaBridge 145:64910690c574 514 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 145:64910690c574 515 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 517 \return Masked and shifted bit field value.
AnnaBridge 145:64910690c574 518 */
AnnaBridge 145:64910690c574 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 145:64910690c574 520
AnnaBridge 145:64910690c574 521 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 145:64910690c574 522
AnnaBridge 145:64910690c574 523
AnnaBridge 145:64910690c574 524 /**
AnnaBridge 145:64910690c574 525 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 526 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 145:64910690c574 527 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 145:64910690c574 528 @{
AnnaBridge 145:64910690c574 529 */
AnnaBridge 145:64910690c574 530
AnnaBridge 145:64910690c574 531 /* Memory mapping of Core Hardware */
<> 132:9baf128c2fab 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 145:64910690c574 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 145:64910690c574 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 132:9baf128c2fab 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 132:9baf128c2fab 536
AnnaBridge 145:64910690c574 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 145:64910690c574 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 145:64910690c574 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 132:9baf128c2fab 540
<> 132:9baf128c2fab 541
<> 132:9baf128c2fab 542 /*@} */
<> 132:9baf128c2fab 543
<> 132:9baf128c2fab 544
<> 132:9baf128c2fab 545
<> 132:9baf128c2fab 546 /*******************************************************************************
<> 132:9baf128c2fab 547 * Hardware Abstraction Layer
<> 132:9baf128c2fab 548 Core Function Interface contains:
<> 132:9baf128c2fab 549 - Core NVIC Functions
<> 132:9baf128c2fab 550 - Core SysTick Functions
<> 132:9baf128c2fab 551 - Core Register Access Functions
<> 132:9baf128c2fab 552 ******************************************************************************/
AnnaBridge 145:64910690c574 553 /**
AnnaBridge 145:64910690c574 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 132:9baf128c2fab 555 */
<> 132:9baf128c2fab 556
<> 132:9baf128c2fab 557
<> 132:9baf128c2fab 558
<> 132:9baf128c2fab 559 /* ########################## NVIC functions #################################### */
AnnaBridge 145:64910690c574 560 /**
AnnaBridge 145:64910690c574 561 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 145:64910690c574 563 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 145:64910690c574 564 @{
<> 132:9baf128c2fab 565 */
<> 132:9baf128c2fab 566
AnnaBridge 145:64910690c574 567 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 145:64910690c574 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 145:64910690c574 570 #endif
AnnaBridge 145:64910690c574 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 572 #else
AnnaBridge 145:64910690c574 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 145:64910690c574 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
AnnaBridge 145:64910690c574 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 145:64910690c574 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 145:64910690c574 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 145:64910690c574 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 145:64910690c574 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 145:64910690c574 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 145:64910690c574 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
AnnaBridge 145:64910690c574 582 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 145:64910690c574 583 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 145:64910690c574 584 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 145:64910690c574 585 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 145:64910690c574 586
AnnaBridge 145:64910690c574 587 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 145:64910690c574 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 145:64910690c574 590 #endif
AnnaBridge 145:64910690c574 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 592 #else
AnnaBridge 145:64910690c574 593 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 145:64910690c574 594 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 145:64910690c574 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 145:64910690c574 596
AnnaBridge 145:64910690c574 597 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 145:64910690c574 598
AnnaBridge 145:64910690c574 599
<> 132:9baf128c2fab 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 132:9baf128c2fab 601 /* The following MACROS handle generation of the register offset and byte masks */
<> 132:9baf128c2fab 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 132:9baf128c2fab 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 132:9baf128c2fab 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 132:9baf128c2fab 605
<> 132:9baf128c2fab 606
AnnaBridge 145:64910690c574 607 /**
AnnaBridge 145:64910690c574 608 \brief Enable Interrupt
AnnaBridge 145:64910690c574 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 610 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 611 \note IRQn must not be negative.
<> 132:9baf128c2fab 612 */
AnnaBridge 145:64910690c574 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 614 {
AnnaBridge 145:64910690c574 615 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 616 {
AnnaBridge 145:64910690c574 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 618 }
<> 132:9baf128c2fab 619 }
<> 132:9baf128c2fab 620
<> 132:9baf128c2fab 621
AnnaBridge 145:64910690c574 622 /**
AnnaBridge 145:64910690c574 623 \brief Get Interrupt Enable status
AnnaBridge 145:64910690c574 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 145:64910690c574 625 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 626 \return 0 Interrupt is not enabled.
AnnaBridge 145:64910690c574 627 \return 1 Interrupt is enabled.
AnnaBridge 145:64910690c574 628 \note IRQn must not be negative.
<> 132:9baf128c2fab 629 */
AnnaBridge 145:64910690c574 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 631 {
AnnaBridge 145:64910690c574 632 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 633 {
AnnaBridge 145:64910690c574 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 635 }
AnnaBridge 145:64910690c574 636 else
AnnaBridge 145:64910690c574 637 {
AnnaBridge 145:64910690c574 638 return(0U);
AnnaBridge 145:64910690c574 639 }
<> 132:9baf128c2fab 640 }
<> 132:9baf128c2fab 641
<> 132:9baf128c2fab 642
AnnaBridge 145:64910690c574 643 /**
AnnaBridge 145:64910690c574 644 \brief Disable Interrupt
AnnaBridge 145:64910690c574 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 646 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 647 \note IRQn must not be negative.
<> 132:9baf128c2fab 648 */
AnnaBridge 145:64910690c574 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 650 {
AnnaBridge 145:64910690c574 651 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 652 {
AnnaBridge 145:64910690c574 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 654 __DSB();
AnnaBridge 145:64910690c574 655 __ISB();
AnnaBridge 145:64910690c574 656 }
<> 132:9baf128c2fab 657 }
<> 132:9baf128c2fab 658
<> 132:9baf128c2fab 659
AnnaBridge 145:64910690c574 660 /**
AnnaBridge 145:64910690c574 661 \brief Get Pending Interrupt
AnnaBridge 145:64910690c574 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 145:64910690c574 663 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 664 \return 0 Interrupt status is not pending.
AnnaBridge 145:64910690c574 665 \return 1 Interrupt status is pending.
AnnaBridge 145:64910690c574 666 \note IRQn must not be negative.
<> 132:9baf128c2fab 667 */
AnnaBridge 145:64910690c574 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 669 {
AnnaBridge 145:64910690c574 670 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 671 {
AnnaBridge 145:64910690c574 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 673 }
AnnaBridge 145:64910690c574 674 else
AnnaBridge 145:64910690c574 675 {
AnnaBridge 145:64910690c574 676 return(0U);
AnnaBridge 145:64910690c574 677 }
<> 132:9baf128c2fab 678 }
<> 132:9baf128c2fab 679
<> 132:9baf128c2fab 680
AnnaBridge 145:64910690c574 681 /**
AnnaBridge 145:64910690c574 682 \brief Set Pending Interrupt
AnnaBridge 145:64910690c574 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 684 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 685 \note IRQn must not be negative.
<> 132:9baf128c2fab 686 */
AnnaBridge 145:64910690c574 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 132:9baf128c2fab 688 {
AnnaBridge 145:64910690c574 689 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 690 {
AnnaBridge 145:64910690c574 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 132:9baf128c2fab 692 }
<> 132:9baf128c2fab 693 }
<> 132:9baf128c2fab 694
<> 132:9baf128c2fab 695
AnnaBridge 145:64910690c574 696 /**
AnnaBridge 145:64910690c574 697 \brief Clear Pending Interrupt
AnnaBridge 145:64910690c574 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 699 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 700 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 701 */
AnnaBridge 145:64910690c574 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 703 {
AnnaBridge 145:64910690c574 704 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 705 {
AnnaBridge 145:64910690c574 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 707 }
AnnaBridge 145:64910690c574 708 }
<> 132:9baf128c2fab 709
<> 132:9baf128c2fab 710
AnnaBridge 145:64910690c574 711 /**
AnnaBridge 145:64910690c574 712 \brief Set Interrupt Priority
AnnaBridge 145:64910690c574 713 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 714 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 715 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 716 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 717 \param [in] priority Priority to set.
AnnaBridge 145:64910690c574 718 \note The priority cannot be set for every processor exception.
<> 132:9baf128c2fab 719 */
AnnaBridge 145:64910690c574 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 132:9baf128c2fab 721 {
AnnaBridge 145:64910690c574 722 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 723 {
AnnaBridge 145:64910690c574 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 132:9baf128c2fab 726 }
AnnaBridge 145:64910690c574 727 else
AnnaBridge 145:64910690c574 728 {
AnnaBridge 145:64910690c574 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 132:9baf128c2fab 731 }
<> 132:9baf128c2fab 732 }
<> 132:9baf128c2fab 733
<> 132:9baf128c2fab 734
AnnaBridge 145:64910690c574 735 /**
AnnaBridge 145:64910690c574 736 \brief Get Interrupt Priority
AnnaBridge 145:64910690c574 737 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 738 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 739 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 740 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 741 \return Interrupt Priority.
AnnaBridge 145:64910690c574 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
<> 132:9baf128c2fab 743 */
AnnaBridge 145:64910690c574 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 745 {
AnnaBridge 145:64910690c574 746
AnnaBridge 145:64910690c574 747 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 748 {
AnnaBridge 145:64910690c574 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 750 }
AnnaBridge 145:64910690c574 751 else
AnnaBridge 145:64910690c574 752 {
AnnaBridge 145:64910690c574 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 754 }
AnnaBridge 145:64910690c574 755 }
AnnaBridge 145:64910690c574 756
AnnaBridge 145:64910690c574 757
AnnaBridge 145:64910690c574 758 /**
AnnaBridge 145:64910690c574 759 \brief Set Interrupt Vector
AnnaBridge 145:64910690c574 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 145:64910690c574 761 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 762 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 763 Address 0 must be mapped to SRAM.
AnnaBridge 145:64910690c574 764 \param [in] IRQn Interrupt number
AnnaBridge 145:64910690c574 765 \param [in] vector Address of interrupt handler function
AnnaBridge 145:64910690c574 766 */
AnnaBridge 145:64910690c574 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
<> 132:9baf128c2fab 768 {
AnnaBridge 145:64910690c574 769 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 145:64910690c574 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 145:64910690c574 771 }
AnnaBridge 145:64910690c574 772
AnnaBridge 145:64910690c574 773
AnnaBridge 145:64910690c574 774 /**
AnnaBridge 145:64910690c574 775 \brief Get Interrupt Vector
AnnaBridge 145:64910690c574 776 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 145:64910690c574 777 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 778 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 779 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 780 \return Address of interrupt handler function
AnnaBridge 145:64910690c574 781 */
AnnaBridge 145:64910690c574 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 783 {
AnnaBridge 145:64910690c574 784 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 145:64910690c574 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 145:64910690c574 786 }
AnnaBridge 145:64910690c574 787
AnnaBridge 145:64910690c574 788
AnnaBridge 145:64910690c574 789 /**
AnnaBridge 145:64910690c574 790 \brief System Reset
AnnaBridge 145:64910690c574 791 \details Initiates a system reset request to reset the MCU.
AnnaBridge 145:64910690c574 792 */
AnnaBridge 145:64910690c574 793 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 145:64910690c574 794 {
AnnaBridge 145:64910690c574 795 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 145:64910690c574 796 buffered write are completed before reset */
<> 132:9baf128c2fab 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 132:9baf128c2fab 798 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 145:64910690c574 799 __DSB(); /* Ensure completion of memory access */
AnnaBridge 145:64910690c574 800
AnnaBridge 145:64910690c574 801 for(;;) /* wait until reset */
AnnaBridge 145:64910690c574 802 {
AnnaBridge 145:64910690c574 803 __NOP();
AnnaBridge 145:64910690c574 804 }
<> 132:9baf128c2fab 805 }
<> 132:9baf128c2fab 806
<> 132:9baf128c2fab 807 /*@} end of CMSIS_Core_NVICFunctions */
<> 132:9baf128c2fab 808
<> 132:9baf128c2fab 809
AnnaBridge 145:64910690c574 810 /* ########################## FPU functions #################################### */
AnnaBridge 145:64910690c574 811 /**
AnnaBridge 145:64910690c574 812 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 145:64910690c574 814 \brief Function that provides FPU type.
<> 132:9baf128c2fab 815 @{
<> 132:9baf128c2fab 816 */
<> 132:9baf128c2fab 817
AnnaBridge 145:64910690c574 818 /**
AnnaBridge 145:64910690c574 819 \brief get FPU type
AnnaBridge 145:64910690c574 820 \details returns the FPU type
AnnaBridge 145:64910690c574 821 \returns
AnnaBridge 145:64910690c574 822 - \b 0: No FPU
AnnaBridge 145:64910690c574 823 - \b 1: Single precision FPU
AnnaBridge 145:64910690c574 824 - \b 2: Double + Single precision FPU
AnnaBridge 145:64910690c574 825 */
AnnaBridge 145:64910690c574 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 145:64910690c574 827 {
AnnaBridge 145:64910690c574 828 return 0U; /* No FPU */
AnnaBridge 145:64910690c574 829 }
<> 132:9baf128c2fab 830
<> 132:9baf128c2fab 831
AnnaBridge 145:64910690c574 832 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 145:64910690c574 833
AnnaBridge 145:64910690c574 834
<> 132:9baf128c2fab 835
AnnaBridge 145:64910690c574 836 /* ################################## SysTick function ############################################ */
AnnaBridge 145:64910690c574 837 /**
AnnaBridge 145:64910690c574 838 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 145:64910690c574 840 \brief Functions that configure the System.
AnnaBridge 145:64910690c574 841 @{
AnnaBridge 145:64910690c574 842 */
<> 132:9baf128c2fab 843
AnnaBridge 145:64910690c574 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
<> 132:9baf128c2fab 845
AnnaBridge 145:64910690c574 846 /**
AnnaBridge 145:64910690c574 847 \brief System Tick Configuration
AnnaBridge 145:64910690c574 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 145:64910690c574 849 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 145:64910690c574 850 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 145:64910690c574 851 \return 0 Function succeeded.
AnnaBridge 145:64910690c574 852 \return 1 Function failed.
AnnaBridge 145:64910690c574 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 145:64910690c574 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 145:64910690c574 855 must contain a vendor-specific implementation of this function.
<> 132:9baf128c2fab 856 */
<> 132:9baf128c2fab 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 132:9baf128c2fab 858 {
AnnaBridge 145:64910690c574 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 145:64910690c574 860 {
AnnaBridge 145:64910690c574 861 return (1UL); /* Reload value impossible */
AnnaBridge 145:64910690c574 862 }
<> 132:9baf128c2fab 863
<> 132:9baf128c2fab 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 132:9baf128c2fab 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 132:9baf128c2fab 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 132:9baf128c2fab 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 132:9baf128c2fab 868 SysTick_CTRL_TICKINT_Msk |
<> 132:9baf128c2fab 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 132:9baf128c2fab 870 return (0UL); /* Function successful */
<> 132:9baf128c2fab 871 }
<> 132:9baf128c2fab 872
<> 132:9baf128c2fab 873 #endif
<> 132:9baf128c2fab 874
<> 132:9baf128c2fab 875 /*@} end of CMSIS_Core_SysTickFunctions */
<> 132:9baf128c2fab 876
<> 132:9baf128c2fab 877
<> 132:9baf128c2fab 878
<> 132:9baf128c2fab 879
<> 132:9baf128c2fab 880 #ifdef __cplusplus
<> 132:9baf128c2fab 881 }
<> 132:9baf128c2fab 882 #endif
<> 132:9baf128c2fab 883
<> 132:9baf128c2fab 884 #endif /* __CORE_CM0_H_DEPENDANT */
<> 132:9baf128c2fab 885
<> 132:9baf128c2fab 886 #endif /* __CMSIS_GENERIC */