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TARGET_LPC1768/core_cm23.h@151:675da3299148, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:46:57 2017 +0100
Revision:
151:675da3299148
Parent:
145:64910690c574
Child:
160:5571c4ff569f
Release 151 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**************************************************************************//**
AnnaBridge 145:64910690c574 2 * @file core_cm23.h
AnnaBridge 145:64910690c574 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
AnnaBridge 145:64910690c574 4 * @version V5.0.2
AnnaBridge 145:64910690c574 5 * @date 13. February 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 145:64910690c574 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 145:64910690c574 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
AnnaBridge 145:64910690c574 24
AnnaBridge 145:64910690c574 25 #if defined ( __ICCARM__ )
AnnaBridge 145:64910690c574 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 145:64910690c574 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 145:64910690c574 29 #endif
AnnaBridge 145:64910690c574 30
AnnaBridge 145:64910690c574 31 #ifndef __CORE_CM23_H_GENERIC
AnnaBridge 145:64910690c574 32 #define __CORE_CM23_H_GENERIC
AnnaBridge 145:64910690c574 33
AnnaBridge 145:64910690c574 34 #include <stdint.h>
AnnaBridge 145:64910690c574 35
AnnaBridge 145:64910690c574 36 #ifdef __cplusplus
AnnaBridge 145:64910690c574 37 extern "C" {
AnnaBridge 145:64910690c574 38 #endif
AnnaBridge 145:64910690c574 39
AnnaBridge 145:64910690c574 40 /**
AnnaBridge 145:64910690c574 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 145:64910690c574 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 145:64910690c574 43
AnnaBridge 145:64910690c574 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 145:64910690c574 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 145:64910690c574 46
AnnaBridge 145:64910690c574 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 145:64910690c574 48 Unions are used for effective representation of core registers.
AnnaBridge 145:64910690c574 49
AnnaBridge 145:64910690c574 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 145:64910690c574 51 Function-like macros are used to allow more efficient code.
AnnaBridge 145:64910690c574 52 */
AnnaBridge 145:64910690c574 53
AnnaBridge 145:64910690c574 54
AnnaBridge 145:64910690c574 55 /*******************************************************************************
AnnaBridge 145:64910690c574 56 * CMSIS definitions
AnnaBridge 145:64910690c574 57 ******************************************************************************/
AnnaBridge 145:64910690c574 58 /**
AnnaBridge 145:64910690c574 59 \ingroup Cortex_M23
AnnaBridge 145:64910690c574 60 @{
AnnaBridge 145:64910690c574 61 */
AnnaBridge 145:64910690c574 62
AnnaBridge 145:64910690c574 63 /* CMSIS cmGrebe definitions */
AnnaBridge 145:64910690c574 64 #define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 145:64910690c574 65 #define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 145:64910690c574 66 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 145:64910690c574 67 __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 145:64910690c574 68
AnnaBridge 145:64910690c574 69 #define __CORTEX_M (23U) /*!< Cortex-M Core */
AnnaBridge 145:64910690c574 70
AnnaBridge 145:64910690c574 71 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 145:64910690c574 72 This core does not support an FPU at all
AnnaBridge 145:64910690c574 73 */
AnnaBridge 145:64910690c574 74 #define __FPU_USED 0U
AnnaBridge 145:64910690c574 75
AnnaBridge 145:64910690c574 76 #if defined ( __CC_ARM )
AnnaBridge 145:64910690c574 77 #if defined __TARGET_FPU_VFP
AnnaBridge 145:64910690c574 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 79 #endif
AnnaBridge 145:64910690c574 80
AnnaBridge 145:64910690c574 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 82 #if defined __ARM_PCS_VFP
AnnaBridge 145:64910690c574 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 84 #endif
AnnaBridge 145:64910690c574 85
AnnaBridge 145:64910690c574 86 #elif defined ( __GNUC__ )
AnnaBridge 145:64910690c574 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 145:64910690c574 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 89 #endif
AnnaBridge 145:64910690c574 90
AnnaBridge 145:64910690c574 91 #elif defined ( __ICCARM__ )
AnnaBridge 145:64910690c574 92 #if defined __ARMVFP__
AnnaBridge 145:64910690c574 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 94 #endif
AnnaBridge 145:64910690c574 95
AnnaBridge 145:64910690c574 96 #elif defined ( __TI_ARM__ )
AnnaBridge 145:64910690c574 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 145:64910690c574 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 99 #endif
AnnaBridge 145:64910690c574 100
AnnaBridge 145:64910690c574 101 #elif defined ( __TASKING__ )
AnnaBridge 145:64910690c574 102 #if defined __FPU_VFP__
AnnaBridge 145:64910690c574 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 104 #endif
AnnaBridge 145:64910690c574 105
AnnaBridge 145:64910690c574 106 #elif defined ( __CSMC__ )
AnnaBridge 145:64910690c574 107 #if ( __CSMC__ & 0x400U)
AnnaBridge 145:64910690c574 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 109 #endif
AnnaBridge 145:64910690c574 110
AnnaBridge 145:64910690c574 111 #endif
AnnaBridge 145:64910690c574 112
AnnaBridge 145:64910690c574 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 114
AnnaBridge 145:64910690c574 115
AnnaBridge 145:64910690c574 116 #ifdef __cplusplus
AnnaBridge 145:64910690c574 117 }
AnnaBridge 145:64910690c574 118 #endif
AnnaBridge 145:64910690c574 119
AnnaBridge 145:64910690c574 120 #endif /* __CORE_CM23_H_GENERIC */
AnnaBridge 145:64910690c574 121
AnnaBridge 145:64910690c574 122 #ifndef __CMSIS_GENERIC
AnnaBridge 145:64910690c574 123
AnnaBridge 145:64910690c574 124 #ifndef __CORE_CM23_H_DEPENDANT
AnnaBridge 145:64910690c574 125 #define __CORE_CM23_H_DEPENDANT
AnnaBridge 145:64910690c574 126
AnnaBridge 145:64910690c574 127 #ifdef __cplusplus
AnnaBridge 145:64910690c574 128 extern "C" {
AnnaBridge 145:64910690c574 129 #endif
AnnaBridge 145:64910690c574 130
AnnaBridge 145:64910690c574 131 /* check device defines and use defaults */
AnnaBridge 145:64910690c574 132 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 145:64910690c574 133 #ifndef __CM23_REV
AnnaBridge 145:64910690c574 134 #define __CM23_REV 0x0000U
AnnaBridge 145:64910690c574 135 #warning "__CM23_REV not defined in device header file; using default!"
AnnaBridge 145:64910690c574 136 #endif
AnnaBridge 145:64910690c574 137
AnnaBridge 145:64910690c574 138 #ifndef __FPU_PRESENT
AnnaBridge 145:64910690c574 139 #define __FPU_PRESENT 0U
AnnaBridge 145:64910690c574 140 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 145:64910690c574 141 #endif
AnnaBridge 145:64910690c574 142
AnnaBridge 145:64910690c574 143 #ifndef __MPU_PRESENT
AnnaBridge 145:64910690c574 144 #define __MPU_PRESENT 0U
AnnaBridge 145:64910690c574 145 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 145:64910690c574 146 #endif
AnnaBridge 145:64910690c574 147
AnnaBridge 145:64910690c574 148 #ifndef __SAUREGION_PRESENT
AnnaBridge 145:64910690c574 149 #define __SAUREGION_PRESENT 0U
AnnaBridge 145:64910690c574 150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge 145:64910690c574 151 #endif
AnnaBridge 145:64910690c574 152
AnnaBridge 145:64910690c574 153 #ifndef __VTOR_PRESENT
AnnaBridge 145:64910690c574 154 #define __VTOR_PRESENT 0U
AnnaBridge 145:64910690c574 155 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 145:64910690c574 156 #endif
AnnaBridge 145:64910690c574 157
AnnaBridge 145:64910690c574 158 #ifndef __NVIC_PRIO_BITS
AnnaBridge 145:64910690c574 159 #define __NVIC_PRIO_BITS 2U
AnnaBridge 145:64910690c574 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 145:64910690c574 161 #endif
AnnaBridge 145:64910690c574 162
AnnaBridge 145:64910690c574 163 #ifndef __Vendor_SysTickConfig
AnnaBridge 145:64910690c574 164 #define __Vendor_SysTickConfig 0U
AnnaBridge 145:64910690c574 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 145:64910690c574 166 #endif
AnnaBridge 145:64910690c574 167
AnnaBridge 145:64910690c574 168 #ifndef __ETM_PRESENT
AnnaBridge 145:64910690c574 169 #define __ETM_PRESENT 0U
AnnaBridge 145:64910690c574 170 #warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge 145:64910690c574 171 #endif
AnnaBridge 145:64910690c574 172
AnnaBridge 145:64910690c574 173 #ifndef __MTB_PRESENT
AnnaBridge 145:64910690c574 174 #define __MTB_PRESENT 0U
AnnaBridge 145:64910690c574 175 #warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge 145:64910690c574 176 #endif
AnnaBridge 145:64910690c574 177
AnnaBridge 145:64910690c574 178 #endif
AnnaBridge 145:64910690c574 179
AnnaBridge 145:64910690c574 180 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 145:64910690c574 181 /**
AnnaBridge 145:64910690c574 182 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 145:64910690c574 183
AnnaBridge 145:64910690c574 184 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 145:64910690c574 185 \li to specify the access to peripheral variables.
AnnaBridge 145:64910690c574 186 \li for automatic generation of peripheral register debug information.
AnnaBridge 145:64910690c574 187 */
AnnaBridge 145:64910690c574 188 #ifdef __cplusplus
AnnaBridge 145:64910690c574 189 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 145:64910690c574 190 #else
AnnaBridge 145:64910690c574 191 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 145:64910690c574 192 #endif
AnnaBridge 145:64910690c574 193 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 145:64910690c574 194 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 145:64910690c574 195
AnnaBridge 145:64910690c574 196 /* following defines should be used for structure members */
AnnaBridge 145:64910690c574 197 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 145:64910690c574 198 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 145:64910690c574 199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 145:64910690c574 200
AnnaBridge 145:64910690c574 201 /*@} end of group Cortex_M23 */
AnnaBridge 145:64910690c574 202
AnnaBridge 145:64910690c574 203
AnnaBridge 145:64910690c574 204
AnnaBridge 145:64910690c574 205 /*******************************************************************************
AnnaBridge 145:64910690c574 206 * Register Abstraction
AnnaBridge 145:64910690c574 207 Core Register contain:
AnnaBridge 145:64910690c574 208 - Core Register
AnnaBridge 145:64910690c574 209 - Core NVIC Register
AnnaBridge 145:64910690c574 210 - Core SCB Register
AnnaBridge 145:64910690c574 211 - Core SysTick Register
AnnaBridge 145:64910690c574 212 - Core Debug Register
AnnaBridge 145:64910690c574 213 - Core MPU Register
AnnaBridge 145:64910690c574 214 - Core SAU Register
AnnaBridge 145:64910690c574 215 ******************************************************************************/
AnnaBridge 145:64910690c574 216 /**
AnnaBridge 145:64910690c574 217 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 145:64910690c574 218 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 145:64910690c574 219 */
AnnaBridge 145:64910690c574 220
AnnaBridge 145:64910690c574 221 /**
AnnaBridge 145:64910690c574 222 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 223 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 145:64910690c574 224 \brief Core Register type definitions.
AnnaBridge 145:64910690c574 225 @{
AnnaBridge 145:64910690c574 226 */
AnnaBridge 145:64910690c574 227
AnnaBridge 145:64910690c574 228 /**
AnnaBridge 145:64910690c574 229 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 145:64910690c574 230 */
AnnaBridge 145:64910690c574 231 typedef union
AnnaBridge 145:64910690c574 232 {
AnnaBridge 145:64910690c574 233 struct
AnnaBridge 145:64910690c574 234 {
AnnaBridge 145:64910690c574 235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 145:64910690c574 236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 240 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 241 uint32_t w; /*!< Type used for word access */
AnnaBridge 145:64910690c574 242 } APSR_Type;
AnnaBridge 145:64910690c574 243
AnnaBridge 145:64910690c574 244 /* APSR Register Definitions */
AnnaBridge 145:64910690c574 245 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 145:64910690c574 246 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 145:64910690c574 247
AnnaBridge 145:64910690c574 248 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 145:64910690c574 249 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 145:64910690c574 250
AnnaBridge 145:64910690c574 251 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 145:64910690c574 252 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 145:64910690c574 253
AnnaBridge 145:64910690c574 254 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 145:64910690c574 255 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 145:64910690c574 256
AnnaBridge 145:64910690c574 257
AnnaBridge 145:64910690c574 258 /**
AnnaBridge 145:64910690c574 259 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 145:64910690c574 260 */
AnnaBridge 145:64910690c574 261 typedef union
AnnaBridge 145:64910690c574 262 {
AnnaBridge 145:64910690c574 263 struct
AnnaBridge 145:64910690c574 264 {
AnnaBridge 145:64910690c574 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 145:64910690c574 267 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 268 uint32_t w; /*!< Type used for word access */
AnnaBridge 145:64910690c574 269 } IPSR_Type;
AnnaBridge 145:64910690c574 270
AnnaBridge 145:64910690c574 271 /* IPSR Register Definitions */
AnnaBridge 145:64910690c574 272 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 145:64910690c574 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 145:64910690c574 274
AnnaBridge 145:64910690c574 275
AnnaBridge 145:64910690c574 276 /**
AnnaBridge 145:64910690c574 277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 145:64910690c574 278 */
AnnaBridge 145:64910690c574 279 typedef union
AnnaBridge 145:64910690c574 280 {
AnnaBridge 145:64910690c574 281 struct
AnnaBridge 145:64910690c574 282 {
AnnaBridge 145:64910690c574 283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 145:64910690c574 285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 145:64910690c574 286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 145:64910690c574 287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 291 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 292 uint32_t w; /*!< Type used for word access */
AnnaBridge 145:64910690c574 293 } xPSR_Type;
AnnaBridge 145:64910690c574 294
AnnaBridge 145:64910690c574 295 /* xPSR Register Definitions */
AnnaBridge 145:64910690c574 296 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 145:64910690c574 297 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 145:64910690c574 298
AnnaBridge 145:64910690c574 299 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 145:64910690c574 300 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 145:64910690c574 301
AnnaBridge 145:64910690c574 302 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 145:64910690c574 303 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 145:64910690c574 304
AnnaBridge 145:64910690c574 305 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 145:64910690c574 306 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 145:64910690c574 307
AnnaBridge 145:64910690c574 308 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 145:64910690c574 309 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 145:64910690c574 310
AnnaBridge 145:64910690c574 311 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 145:64910690c574 312 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 145:64910690c574 313
AnnaBridge 145:64910690c574 314
AnnaBridge 145:64910690c574 315 /**
AnnaBridge 145:64910690c574 316 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 145:64910690c574 317 */
AnnaBridge 145:64910690c574 318 typedef union
AnnaBridge 145:64910690c574 319 {
AnnaBridge 145:64910690c574 320 struct
AnnaBridge 145:64910690c574 321 {
AnnaBridge 145:64910690c574 322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 145:64910690c574 323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
AnnaBridge 145:64910690c574 324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 145:64910690c574 325 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 326 uint32_t w; /*!< Type used for word access */
AnnaBridge 145:64910690c574 327 } CONTROL_Type;
AnnaBridge 145:64910690c574 328
AnnaBridge 145:64910690c574 329 /* CONTROL Register Definitions */
AnnaBridge 145:64910690c574 330 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 145:64910690c574 331 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 145:64910690c574 332
AnnaBridge 145:64910690c574 333 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 145:64910690c574 334 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 145:64910690c574 335
AnnaBridge 145:64910690c574 336 /*@} end of group CMSIS_CORE */
AnnaBridge 145:64910690c574 337
AnnaBridge 145:64910690c574 338
AnnaBridge 145:64910690c574 339 /**
AnnaBridge 145:64910690c574 340 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 145:64910690c574 342 \brief Type definitions for the NVIC Registers
AnnaBridge 145:64910690c574 343 @{
AnnaBridge 145:64910690c574 344 */
AnnaBridge 145:64910690c574 345
AnnaBridge 145:64910690c574 346 /**
AnnaBridge 145:64910690c574 347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 145:64910690c574 348 */
AnnaBridge 145:64910690c574 349 typedef struct
AnnaBridge 145:64910690c574 350 {
AnnaBridge 145:64910690c574 351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 145:64910690c574 352 uint32_t RESERVED0[16U];
AnnaBridge 145:64910690c574 353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 145:64910690c574 354 uint32_t RSERVED1[16U];
AnnaBridge 145:64910690c574 355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 145:64910690c574 356 uint32_t RESERVED2[16U];
AnnaBridge 145:64910690c574 357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 145:64910690c574 358 uint32_t RESERVED3[16U];
AnnaBridge 145:64910690c574 359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 145:64910690c574 360 uint32_t RESERVED4[16U];
AnnaBridge 145:64910690c574 361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
AnnaBridge 145:64910690c574 362 uint32_t RESERVED5[16U];
AnnaBridge 145:64910690c574 363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 145:64910690c574 364 } NVIC_Type;
AnnaBridge 145:64910690c574 365
AnnaBridge 145:64910690c574 366 /*@} end of group CMSIS_NVIC */
AnnaBridge 145:64910690c574 367
AnnaBridge 145:64910690c574 368
AnnaBridge 145:64910690c574 369 /**
AnnaBridge 145:64910690c574 370 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 371 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 145:64910690c574 372 \brief Type definitions for the System Control Block Registers
AnnaBridge 145:64910690c574 373 @{
AnnaBridge 145:64910690c574 374 */
AnnaBridge 145:64910690c574 375
AnnaBridge 145:64910690c574 376 /**
AnnaBridge 145:64910690c574 377 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 145:64910690c574 378 */
AnnaBridge 145:64910690c574 379 typedef struct
AnnaBridge 145:64910690c574 380 {
AnnaBridge 145:64910690c574 381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 145:64910690c574 382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 145:64910690c574 383 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 145:64910690c574 384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 145:64910690c574 385 #else
AnnaBridge 145:64910690c574 386 uint32_t RESERVED0;
AnnaBridge 145:64910690c574 387 #endif
AnnaBridge 145:64910690c574 388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 145:64910690c574 389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 145:64910690c574 390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 145:64910690c574 391 uint32_t RESERVED1;
AnnaBridge 145:64910690c574 392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 145:64910690c574 393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 145:64910690c574 394 } SCB_Type;
AnnaBridge 145:64910690c574 395
AnnaBridge 145:64910690c574 396 /* SCB CPUID Register Definitions */
AnnaBridge 145:64910690c574 397 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 145:64910690c574 398 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 145:64910690c574 399
AnnaBridge 145:64910690c574 400 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 145:64910690c574 401 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 145:64910690c574 402
AnnaBridge 145:64910690c574 403 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 145:64910690c574 404 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 145:64910690c574 405
AnnaBridge 145:64910690c574 406 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 145:64910690c574 407 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 145:64910690c574 408
AnnaBridge 145:64910690c574 409 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 145:64910690c574 410 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 145:64910690c574 411
AnnaBridge 145:64910690c574 412 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 413 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
AnnaBridge 145:64910690c574 414 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
AnnaBridge 145:64910690c574 415
AnnaBridge 145:64910690c574 416 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
AnnaBridge 145:64910690c574 417 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
AnnaBridge 145:64910690c574 418
AnnaBridge 145:64910690c574 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 145:64910690c574 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 145:64910690c574 421
AnnaBridge 145:64910690c574 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 145:64910690c574 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 145:64910690c574 424
AnnaBridge 145:64910690c574 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 145:64910690c574 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 145:64910690c574 427
AnnaBridge 145:64910690c574 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 145:64910690c574 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 145:64910690c574 430
AnnaBridge 145:64910690c574 431 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
AnnaBridge 145:64910690c574 432 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
AnnaBridge 145:64910690c574 433
AnnaBridge 145:64910690c574 434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 145:64910690c574 435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 145:64910690c574 436
AnnaBridge 145:64910690c574 437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 145:64910690c574 438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 145:64910690c574 439
AnnaBridge 145:64910690c574 440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 145:64910690c574 441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 145:64910690c574 442
AnnaBridge 145:64910690c574 443 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 145:64910690c574 444 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 145:64910690c574 445
AnnaBridge 145:64910690c574 446 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 145:64910690c574 447 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 145:64910690c574 448
AnnaBridge 145:64910690c574 449 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 145:64910690c574 450 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 145:64910690c574 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 145:64910690c574 452 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 145:64910690c574 453 #endif
AnnaBridge 145:64910690c574 454
AnnaBridge 145:64910690c574 455 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 145:64910690c574 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 145:64910690c574 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 145:64910690c574 458
AnnaBridge 145:64910690c574 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 145:64910690c574 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 145:64910690c574 461
AnnaBridge 145:64910690c574 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 145:64910690c574 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 145:64910690c574 464
AnnaBridge 145:64910690c574 465 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
AnnaBridge 145:64910690c574 466 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
AnnaBridge 145:64910690c574 467
AnnaBridge 145:64910690c574 468 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
AnnaBridge 145:64910690c574 469 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
AnnaBridge 145:64910690c574 470
AnnaBridge 145:64910690c574 471 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
AnnaBridge 145:64910690c574 472 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
AnnaBridge 145:64910690c574 473
AnnaBridge 145:64910690c574 474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 145:64910690c574 475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 145:64910690c574 476
AnnaBridge 145:64910690c574 477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 145:64910690c574 478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 145:64910690c574 479
AnnaBridge 145:64910690c574 480 /* SCB System Control Register Definitions */
AnnaBridge 145:64910690c574 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 145:64910690c574 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 145:64910690c574 483
AnnaBridge 145:64910690c574 484 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
AnnaBridge 145:64910690c574 485 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
AnnaBridge 145:64910690c574 486
AnnaBridge 145:64910690c574 487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 145:64910690c574 488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 145:64910690c574 489
AnnaBridge 145:64910690c574 490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 145:64910690c574 491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 145:64910690c574 492
AnnaBridge 145:64910690c574 493 /* SCB Configuration Control Register Definitions */
AnnaBridge 145:64910690c574 494 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
AnnaBridge 145:64910690c574 495 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
AnnaBridge 145:64910690c574 496
AnnaBridge 145:64910690c574 497 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
AnnaBridge 145:64910690c574 498 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
AnnaBridge 145:64910690c574 499
AnnaBridge 145:64910690c574 500 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
AnnaBridge 145:64910690c574 501 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
AnnaBridge 145:64910690c574 502
AnnaBridge 145:64910690c574 503 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
AnnaBridge 145:64910690c574 504 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
AnnaBridge 145:64910690c574 505
AnnaBridge 145:64910690c574 506 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 145:64910690c574 507 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 145:64910690c574 508
AnnaBridge 145:64910690c574 509 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 145:64910690c574 510 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 145:64910690c574 511
AnnaBridge 145:64910690c574 512 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 145:64910690c574 513 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 145:64910690c574 514
AnnaBridge 145:64910690c574 515 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 145:64910690c574 516 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 145:64910690c574 517
AnnaBridge 145:64910690c574 518 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 145:64910690c574 519 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
AnnaBridge 145:64910690c574 520 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
AnnaBridge 145:64910690c574 521
AnnaBridge 145:64910690c574 522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 145:64910690c574 523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 145:64910690c574 524
AnnaBridge 145:64910690c574 525 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 145:64910690c574 526 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 145:64910690c574 527
AnnaBridge 145:64910690c574 528 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 145:64910690c574 529 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 145:64910690c574 530
AnnaBridge 145:64910690c574 531 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 145:64910690c574 532 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 145:64910690c574 533
AnnaBridge 145:64910690c574 534 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
AnnaBridge 145:64910690c574 535 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
AnnaBridge 145:64910690c574 536
AnnaBridge 145:64910690c574 537 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
AnnaBridge 145:64910690c574 538 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
AnnaBridge 145:64910690c574 539
AnnaBridge 145:64910690c574 540 /*@} end of group CMSIS_SCB */
AnnaBridge 145:64910690c574 541
AnnaBridge 145:64910690c574 542
AnnaBridge 145:64910690c574 543 /**
AnnaBridge 145:64910690c574 544 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 545 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 145:64910690c574 546 \brief Type definitions for the System Timer Registers.
AnnaBridge 145:64910690c574 547 @{
AnnaBridge 145:64910690c574 548 */
AnnaBridge 145:64910690c574 549
AnnaBridge 145:64910690c574 550 /**
AnnaBridge 145:64910690c574 551 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 145:64910690c574 552 */
AnnaBridge 145:64910690c574 553 typedef struct
AnnaBridge 145:64910690c574 554 {
AnnaBridge 145:64910690c574 555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 145:64910690c574 556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 145:64910690c574 557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 145:64910690c574 558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 145:64910690c574 559 } SysTick_Type;
AnnaBridge 145:64910690c574 560
AnnaBridge 145:64910690c574 561 /* SysTick Control / Status Register Definitions */
AnnaBridge 145:64910690c574 562 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 145:64910690c574 563 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 145:64910690c574 564
AnnaBridge 145:64910690c574 565 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 145:64910690c574 566 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 145:64910690c574 567
AnnaBridge 145:64910690c574 568 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 145:64910690c574 569 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 145:64910690c574 570
AnnaBridge 145:64910690c574 571 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 145:64910690c574 572 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 145:64910690c574 573
AnnaBridge 145:64910690c574 574 /* SysTick Reload Register Definitions */
AnnaBridge 145:64910690c574 575 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 145:64910690c574 576 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 145:64910690c574 577
AnnaBridge 145:64910690c574 578 /* SysTick Current Register Definitions */
AnnaBridge 145:64910690c574 579 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 145:64910690c574 580 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 145:64910690c574 581
AnnaBridge 145:64910690c574 582 /* SysTick Calibration Register Definitions */
AnnaBridge 145:64910690c574 583 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 145:64910690c574 584 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 145:64910690c574 585
AnnaBridge 145:64910690c574 586 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 145:64910690c574 587 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 145:64910690c574 588
AnnaBridge 145:64910690c574 589 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 145:64910690c574 590 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 145:64910690c574 591
AnnaBridge 145:64910690c574 592 /*@} end of group CMSIS_SysTick */
AnnaBridge 145:64910690c574 593
AnnaBridge 145:64910690c574 594
AnnaBridge 145:64910690c574 595 /**
AnnaBridge 145:64910690c574 596 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 145:64910690c574 598 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 145:64910690c574 599 @{
AnnaBridge 145:64910690c574 600 */
AnnaBridge 145:64910690c574 601
AnnaBridge 145:64910690c574 602 /**
AnnaBridge 145:64910690c574 603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 145:64910690c574 604 */
AnnaBridge 145:64910690c574 605 typedef struct
AnnaBridge 145:64910690c574 606 {
AnnaBridge 145:64910690c574 607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 145:64910690c574 608 uint32_t RESERVED0[6U];
AnnaBridge 145:64910690c574 609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 145:64910690c574 610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 145:64910690c574 611 uint32_t RESERVED1[1U];
AnnaBridge 145:64910690c574 612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 145:64910690c574 613 uint32_t RESERVED2[1U];
AnnaBridge 145:64910690c574 614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 145:64910690c574 615 uint32_t RESERVED3[1U];
AnnaBridge 145:64910690c574 616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 145:64910690c574 617 uint32_t RESERVED4[1U];
AnnaBridge 145:64910690c574 618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 145:64910690c574 619 uint32_t RESERVED5[1U];
AnnaBridge 145:64910690c574 620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 145:64910690c574 621 uint32_t RESERVED6[1U];
AnnaBridge 145:64910690c574 622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 145:64910690c574 623 uint32_t RESERVED7[1U];
AnnaBridge 145:64910690c574 624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 145:64910690c574 625 uint32_t RESERVED8[1U];
AnnaBridge 145:64910690c574 626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
AnnaBridge 145:64910690c574 627 uint32_t RESERVED9[1U];
AnnaBridge 145:64910690c574 628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
AnnaBridge 145:64910690c574 629 uint32_t RESERVED10[1U];
AnnaBridge 145:64910690c574 630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
AnnaBridge 145:64910690c574 631 uint32_t RESERVED11[1U];
AnnaBridge 145:64910690c574 632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
AnnaBridge 145:64910690c574 633 uint32_t RESERVED12[1U];
AnnaBridge 145:64910690c574 634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
AnnaBridge 145:64910690c574 635 uint32_t RESERVED13[1U];
AnnaBridge 145:64910690c574 636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
AnnaBridge 145:64910690c574 637 uint32_t RESERVED14[1U];
AnnaBridge 145:64910690c574 638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
AnnaBridge 145:64910690c574 639 uint32_t RESERVED15[1U];
AnnaBridge 145:64910690c574 640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
AnnaBridge 145:64910690c574 641 uint32_t RESERVED16[1U];
AnnaBridge 145:64910690c574 642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
AnnaBridge 145:64910690c574 643 uint32_t RESERVED17[1U];
AnnaBridge 145:64910690c574 644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
AnnaBridge 145:64910690c574 645 uint32_t RESERVED18[1U];
AnnaBridge 145:64910690c574 646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
AnnaBridge 145:64910690c574 647 uint32_t RESERVED19[1U];
AnnaBridge 145:64910690c574 648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
AnnaBridge 145:64910690c574 649 uint32_t RESERVED20[1U];
AnnaBridge 145:64910690c574 650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
AnnaBridge 145:64910690c574 651 uint32_t RESERVED21[1U];
AnnaBridge 145:64910690c574 652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
AnnaBridge 145:64910690c574 653 uint32_t RESERVED22[1U];
AnnaBridge 145:64910690c574 654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
AnnaBridge 145:64910690c574 655 uint32_t RESERVED23[1U];
AnnaBridge 145:64910690c574 656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
AnnaBridge 145:64910690c574 657 uint32_t RESERVED24[1U];
AnnaBridge 145:64910690c574 658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
AnnaBridge 145:64910690c574 659 uint32_t RESERVED25[1U];
AnnaBridge 145:64910690c574 660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
AnnaBridge 145:64910690c574 661 uint32_t RESERVED26[1U];
AnnaBridge 145:64910690c574 662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
AnnaBridge 145:64910690c574 663 uint32_t RESERVED27[1U];
AnnaBridge 145:64910690c574 664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
AnnaBridge 145:64910690c574 665 uint32_t RESERVED28[1U];
AnnaBridge 145:64910690c574 666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
AnnaBridge 145:64910690c574 667 uint32_t RESERVED29[1U];
AnnaBridge 145:64910690c574 668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
AnnaBridge 145:64910690c574 669 uint32_t RESERVED30[1U];
AnnaBridge 145:64910690c574 670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
AnnaBridge 145:64910690c574 671 uint32_t RESERVED31[1U];
AnnaBridge 145:64910690c574 672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
AnnaBridge 145:64910690c574 673 } DWT_Type;
AnnaBridge 145:64910690c574 674
AnnaBridge 145:64910690c574 675 /* DWT Control Register Definitions */
AnnaBridge 145:64910690c574 676 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 145:64910690c574 677 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 145:64910690c574 678
AnnaBridge 145:64910690c574 679 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 145:64910690c574 680 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 145:64910690c574 681
AnnaBridge 145:64910690c574 682 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 145:64910690c574 683 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 145:64910690c574 684
AnnaBridge 145:64910690c574 685 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 145:64910690c574 686 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 145:64910690c574 687
AnnaBridge 145:64910690c574 688 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 145:64910690c574 689 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 145:64910690c574 690
AnnaBridge 145:64910690c574 691 /* DWT Comparator Function Register Definitions */
AnnaBridge 145:64910690c574 692 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
AnnaBridge 145:64910690c574 693 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
AnnaBridge 145:64910690c574 694
AnnaBridge 145:64910690c574 695 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 145:64910690c574 696 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 145:64910690c574 697
AnnaBridge 145:64910690c574 698 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 145:64910690c574 699 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 145:64910690c574 700
AnnaBridge 145:64910690c574 701 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
AnnaBridge 145:64910690c574 702 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
AnnaBridge 145:64910690c574 703
AnnaBridge 145:64910690c574 704 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
AnnaBridge 145:64910690c574 705 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
AnnaBridge 145:64910690c574 706
AnnaBridge 145:64910690c574 707 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 145:64910690c574 708
AnnaBridge 145:64910690c574 709
AnnaBridge 145:64910690c574 710 /**
AnnaBridge 145:64910690c574 711 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 712 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 145:64910690c574 713 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 145:64910690c574 714 @{
AnnaBridge 145:64910690c574 715 */
AnnaBridge 145:64910690c574 716
AnnaBridge 145:64910690c574 717 /**
AnnaBridge 145:64910690c574 718 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 145:64910690c574 719 */
AnnaBridge 145:64910690c574 720 typedef struct
AnnaBridge 145:64910690c574 721 {
AnnaBridge 145:64910690c574 722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 145:64910690c574 723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 145:64910690c574 724 uint32_t RESERVED0[2U];
AnnaBridge 145:64910690c574 725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 145:64910690c574 726 uint32_t RESERVED1[55U];
AnnaBridge 145:64910690c574 727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 145:64910690c574 728 uint32_t RESERVED2[131U];
AnnaBridge 145:64910690c574 729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 145:64910690c574 730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 145:64910690c574 731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 145:64910690c574 732 uint32_t RESERVED3[759U];
AnnaBridge 145:64910690c574 733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 145:64910690c574 734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 145:64910690c574 735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 145:64910690c574 736 uint32_t RESERVED4[1U];
AnnaBridge 145:64910690c574 737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 145:64910690c574 738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 145:64910690c574 739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 145:64910690c574 740 uint32_t RESERVED5[39U];
AnnaBridge 145:64910690c574 741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 145:64910690c574 742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 145:64910690c574 743 uint32_t RESERVED7[8U];
AnnaBridge 145:64910690c574 744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 145:64910690c574 745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 145:64910690c574 746 } TPI_Type;
AnnaBridge 145:64910690c574 747
AnnaBridge 145:64910690c574 748 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 145:64910690c574 749 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 145:64910690c574 750 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 145:64910690c574 751
AnnaBridge 145:64910690c574 752 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 145:64910690c574 753 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 145:64910690c574 754 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 145:64910690c574 755
AnnaBridge 145:64910690c574 756 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 145:64910690c574 757 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 145:64910690c574 758 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 145:64910690c574 759
AnnaBridge 145:64910690c574 760 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 145:64910690c574 761 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 145:64910690c574 762
AnnaBridge 145:64910690c574 763 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 145:64910690c574 764 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 145:64910690c574 765
AnnaBridge 145:64910690c574 766 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 145:64910690c574 767 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 145:64910690c574 768
AnnaBridge 145:64910690c574 769 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 145:64910690c574 770 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 145:64910690c574 771 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 145:64910690c574 772
AnnaBridge 145:64910690c574 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 145:64910690c574 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 145:64910690c574 775
AnnaBridge 145:64910690c574 776 /* TPI TRIGGER Register Definitions */
AnnaBridge 145:64910690c574 777 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 145:64910690c574 778 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 145:64910690c574 779
AnnaBridge 145:64910690c574 780 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 145:64910690c574 781 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 145:64910690c574 782 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 145:64910690c574 783
AnnaBridge 145:64910690c574 784 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 145:64910690c574 785 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 145:64910690c574 786
AnnaBridge 145:64910690c574 787 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 145:64910690c574 788 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 145:64910690c574 789
AnnaBridge 145:64910690c574 790 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 145:64910690c574 791 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 145:64910690c574 792
AnnaBridge 145:64910690c574 793 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 145:64910690c574 794 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 145:64910690c574 795
AnnaBridge 145:64910690c574 796 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 145:64910690c574 797 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 145:64910690c574 798
AnnaBridge 145:64910690c574 799 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 145:64910690c574 800 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 145:64910690c574 801
AnnaBridge 145:64910690c574 802 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 145:64910690c574 803 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 145:64910690c574 804 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 145:64910690c574 805
AnnaBridge 145:64910690c574 806 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 145:64910690c574 807 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 145:64910690c574 808 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 145:64910690c574 809
AnnaBridge 145:64910690c574 810 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 145:64910690c574 811 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 145:64910690c574 812
AnnaBridge 145:64910690c574 813 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 145:64910690c574 814 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 145:64910690c574 815
AnnaBridge 145:64910690c574 816 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 145:64910690c574 817 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 145:64910690c574 818
AnnaBridge 145:64910690c574 819 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 145:64910690c574 820 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 145:64910690c574 821
AnnaBridge 145:64910690c574 822 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 145:64910690c574 823 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 145:64910690c574 824
AnnaBridge 145:64910690c574 825 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 145:64910690c574 826 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 145:64910690c574 827
AnnaBridge 145:64910690c574 828 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 145:64910690c574 829 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 145:64910690c574 830 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 145:64910690c574 831
AnnaBridge 145:64910690c574 832 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 145:64910690c574 833 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 145:64910690c574 834 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 145:64910690c574 835
AnnaBridge 145:64910690c574 836 /* TPI DEVID Register Definitions */
AnnaBridge 145:64910690c574 837 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 145:64910690c574 838 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 145:64910690c574 839
AnnaBridge 145:64910690c574 840 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 145:64910690c574 841 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 145:64910690c574 842
AnnaBridge 145:64910690c574 843 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 145:64910690c574 844 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 145:64910690c574 845
AnnaBridge 145:64910690c574 846 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 145:64910690c574 847 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 145:64910690c574 848
AnnaBridge 145:64910690c574 849 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 145:64910690c574 850 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 145:64910690c574 851
AnnaBridge 145:64910690c574 852 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 145:64910690c574 853 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 145:64910690c574 854
AnnaBridge 145:64910690c574 855 /* TPI DEVTYPE Register Definitions */
AnnaBridge 145:64910690c574 856 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 145:64910690c574 857 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 145:64910690c574 858
AnnaBridge 145:64910690c574 859 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 145:64910690c574 860 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 145:64910690c574 861
AnnaBridge 145:64910690c574 862 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 145:64910690c574 863
AnnaBridge 145:64910690c574 864
AnnaBridge 145:64910690c574 865 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 866 /**
AnnaBridge 145:64910690c574 867 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 868 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 145:64910690c574 869 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 145:64910690c574 870 @{
AnnaBridge 145:64910690c574 871 */
AnnaBridge 145:64910690c574 872
AnnaBridge 145:64910690c574 873 /**
AnnaBridge 145:64910690c574 874 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 145:64910690c574 875 */
AnnaBridge 145:64910690c574 876 typedef struct
AnnaBridge 145:64910690c574 877 {
AnnaBridge 145:64910690c574 878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 145:64910690c574 879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 145:64910690c574 880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
AnnaBridge 145:64910690c574 881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 145:64910690c574 882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
AnnaBridge 145:64910690c574 883 uint32_t RESERVED0[7U];
AnnaBridge 145:64910690c574 884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
AnnaBridge 145:64910690c574 885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
AnnaBridge 145:64910690c574 886 } MPU_Type;
AnnaBridge 145:64910690c574 887
AnnaBridge 145:64910690c574 888 /* MPU Type Register Definitions */
AnnaBridge 145:64910690c574 889 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 145:64910690c574 890 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 145:64910690c574 891
AnnaBridge 145:64910690c574 892 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 145:64910690c574 893 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 145:64910690c574 894
AnnaBridge 145:64910690c574 895 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 145:64910690c574 896 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 145:64910690c574 897
AnnaBridge 145:64910690c574 898 /* MPU Control Register Definitions */
AnnaBridge 145:64910690c574 899 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 145:64910690c574 900 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 145:64910690c574 901
AnnaBridge 145:64910690c574 902 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 145:64910690c574 903 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 145:64910690c574 904
AnnaBridge 145:64910690c574 905 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 145:64910690c574 906 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 145:64910690c574 907
AnnaBridge 145:64910690c574 908 /* MPU Region Number Register Definitions */
AnnaBridge 145:64910690c574 909 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 145:64910690c574 910 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 145:64910690c574 911
AnnaBridge 145:64910690c574 912 /* MPU Region Base Address Register Definitions */
AnnaBridge 145:64910690c574 913 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
AnnaBridge 145:64910690c574 914 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
AnnaBridge 145:64910690c574 915
AnnaBridge 145:64910690c574 916 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
AnnaBridge 145:64910690c574 917 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
AnnaBridge 145:64910690c574 918
AnnaBridge 145:64910690c574 919 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
AnnaBridge 145:64910690c574 920 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
AnnaBridge 145:64910690c574 921
AnnaBridge 145:64910690c574 922 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
AnnaBridge 145:64910690c574 923 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
AnnaBridge 145:64910690c574 924
AnnaBridge 145:64910690c574 925 /* MPU Region Limit Address Register Definitions */
AnnaBridge 145:64910690c574 926 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
AnnaBridge 145:64910690c574 927 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
AnnaBridge 145:64910690c574 928
AnnaBridge 145:64910690c574 929 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
AnnaBridge 145:64910690c574 930 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
AnnaBridge 145:64910690c574 931
AnnaBridge 145:64910690c574 932 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
AnnaBridge 145:64910690c574 933 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
AnnaBridge 145:64910690c574 934
AnnaBridge 145:64910690c574 935 /* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge 145:64910690c574 936 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
AnnaBridge 145:64910690c574 937 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
AnnaBridge 145:64910690c574 938
AnnaBridge 145:64910690c574 939 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
AnnaBridge 145:64910690c574 940 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
AnnaBridge 145:64910690c574 941
AnnaBridge 145:64910690c574 942 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
AnnaBridge 145:64910690c574 943 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
AnnaBridge 145:64910690c574 944
AnnaBridge 145:64910690c574 945 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
AnnaBridge 145:64910690c574 946 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
AnnaBridge 145:64910690c574 947
AnnaBridge 145:64910690c574 948 /* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge 145:64910690c574 949 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
AnnaBridge 145:64910690c574 950 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
AnnaBridge 145:64910690c574 951
AnnaBridge 145:64910690c574 952 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
AnnaBridge 145:64910690c574 953 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
AnnaBridge 145:64910690c574 954
AnnaBridge 145:64910690c574 955 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
AnnaBridge 145:64910690c574 956 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
AnnaBridge 145:64910690c574 957
AnnaBridge 145:64910690c574 958 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
AnnaBridge 145:64910690c574 959 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
AnnaBridge 145:64910690c574 960
AnnaBridge 145:64910690c574 961 /*@} end of group CMSIS_MPU */
AnnaBridge 145:64910690c574 962 #endif
AnnaBridge 145:64910690c574 963
AnnaBridge 145:64910690c574 964
AnnaBridge 145:64910690c574 965 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 145:64910690c574 966 /**
AnnaBridge 145:64910690c574 967 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 968 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge 145:64910690c574 969 \brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge 145:64910690c574 970 @{
AnnaBridge 145:64910690c574 971 */
AnnaBridge 145:64910690c574 972
AnnaBridge 145:64910690c574 973 /**
AnnaBridge 145:64910690c574 974 \brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge 145:64910690c574 975 */
AnnaBridge 145:64910690c574 976 typedef struct
AnnaBridge 145:64910690c574 977 {
AnnaBridge 145:64910690c574 978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
AnnaBridge 145:64910690c574 979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
AnnaBridge 145:64910690c574 980 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 145:64910690c574 981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
AnnaBridge 145:64910690c574 982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
AnnaBridge 145:64910690c574 983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
AnnaBridge 145:64910690c574 984 #endif
AnnaBridge 145:64910690c574 985 } SAU_Type;
AnnaBridge 145:64910690c574 986
AnnaBridge 145:64910690c574 987 /* SAU Control Register Definitions */
AnnaBridge 145:64910690c574 988 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
AnnaBridge 145:64910690c574 989 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
AnnaBridge 145:64910690c574 990
AnnaBridge 145:64910690c574 991 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
AnnaBridge 145:64910690c574 992 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
AnnaBridge 145:64910690c574 993
AnnaBridge 145:64910690c574 994 /* SAU Type Register Definitions */
AnnaBridge 145:64910690c574 995 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
AnnaBridge 145:64910690c574 996 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
AnnaBridge 145:64910690c574 997
AnnaBridge 145:64910690c574 998 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 145:64910690c574 999 /* SAU Region Number Register Definitions */
AnnaBridge 145:64910690c574 1000 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
AnnaBridge 145:64910690c574 1001 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
AnnaBridge 145:64910690c574 1002
AnnaBridge 145:64910690c574 1003 /* SAU Region Base Address Register Definitions */
AnnaBridge 145:64910690c574 1004 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
AnnaBridge 145:64910690c574 1005 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
AnnaBridge 145:64910690c574 1006
AnnaBridge 145:64910690c574 1007 /* SAU Region Limit Address Register Definitions */
AnnaBridge 145:64910690c574 1008 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
AnnaBridge 145:64910690c574 1009 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
AnnaBridge 145:64910690c574 1010
AnnaBridge 145:64910690c574 1011 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
AnnaBridge 145:64910690c574 1012 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
AnnaBridge 145:64910690c574 1013
AnnaBridge 145:64910690c574 1014 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
AnnaBridge 145:64910690c574 1015 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
AnnaBridge 145:64910690c574 1016
AnnaBridge 145:64910690c574 1017 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge 145:64910690c574 1018
AnnaBridge 145:64910690c574 1019 /*@} end of group CMSIS_SAU */
AnnaBridge 145:64910690c574 1020 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 145:64910690c574 1021
AnnaBridge 145:64910690c574 1022
AnnaBridge 145:64910690c574 1023 /**
AnnaBridge 145:64910690c574 1024 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 1025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 145:64910690c574 1026 \brief Type definitions for the Core Debug Registers
AnnaBridge 145:64910690c574 1027 @{
AnnaBridge 145:64910690c574 1028 */
AnnaBridge 145:64910690c574 1029
AnnaBridge 145:64910690c574 1030 /**
AnnaBridge 145:64910690c574 1031 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 145:64910690c574 1032 */
AnnaBridge 145:64910690c574 1033 typedef struct
AnnaBridge 145:64910690c574 1034 {
AnnaBridge 145:64910690c574 1035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 145:64910690c574 1036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 145:64910690c574 1037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 145:64910690c574 1038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 145:64910690c574 1039 uint32_t RESERVED4[1U];
AnnaBridge 145:64910690c574 1040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
AnnaBridge 145:64910690c574 1041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
AnnaBridge 145:64910690c574 1042 } CoreDebug_Type;
AnnaBridge 145:64910690c574 1043
AnnaBridge 145:64910690c574 1044 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 145:64910690c574 1045 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 145:64910690c574 1046 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 145:64910690c574 1047
AnnaBridge 145:64910690c574 1048 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
AnnaBridge 145:64910690c574 1049 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
AnnaBridge 145:64910690c574 1050
AnnaBridge 145:64910690c574 1051 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 145:64910690c574 1052 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 145:64910690c574 1053
AnnaBridge 145:64910690c574 1054 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 145:64910690c574 1055 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 145:64910690c574 1056
AnnaBridge 145:64910690c574 1057 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 145:64910690c574 1058 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 145:64910690c574 1059
AnnaBridge 145:64910690c574 1060 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 145:64910690c574 1061 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 145:64910690c574 1062
AnnaBridge 145:64910690c574 1063 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 145:64910690c574 1064 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 145:64910690c574 1065
AnnaBridge 145:64910690c574 1066 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 145:64910690c574 1067 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 145:64910690c574 1068
AnnaBridge 145:64910690c574 1069 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 145:64910690c574 1070 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 145:64910690c574 1071
AnnaBridge 145:64910690c574 1072 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 145:64910690c574 1073 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 145:64910690c574 1074
AnnaBridge 145:64910690c574 1075 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 145:64910690c574 1076 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 145:64910690c574 1077
AnnaBridge 145:64910690c574 1078 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 145:64910690c574 1079 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 145:64910690c574 1080
AnnaBridge 145:64910690c574 1081 /* Debug Core Register Selector Register Definitions */
AnnaBridge 145:64910690c574 1082 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 145:64910690c574 1083 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 145:64910690c574 1084
AnnaBridge 145:64910690c574 1085 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 145:64910690c574 1086 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 145:64910690c574 1087
AnnaBridge 145:64910690c574 1088 /* Debug Exception and Monitor Control Register */
AnnaBridge 145:64910690c574 1089 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
AnnaBridge 145:64910690c574 1090 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
AnnaBridge 145:64910690c574 1091
AnnaBridge 145:64910690c574 1092 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 145:64910690c574 1093 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 145:64910690c574 1094
AnnaBridge 145:64910690c574 1095 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 145:64910690c574 1096 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 145:64910690c574 1097
AnnaBridge 145:64910690c574 1098 /* Debug Authentication Control Register Definitions */
AnnaBridge 145:64910690c574 1099 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
AnnaBridge 145:64910690c574 1100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
AnnaBridge 145:64910690c574 1101
AnnaBridge 145:64910690c574 1102 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
AnnaBridge 145:64910690c574 1103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
AnnaBridge 145:64910690c574 1104
AnnaBridge 145:64910690c574 1105 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
AnnaBridge 145:64910690c574 1106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
AnnaBridge 145:64910690c574 1107
AnnaBridge 145:64910690c574 1108 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
AnnaBridge 145:64910690c574 1109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
AnnaBridge 145:64910690c574 1110
AnnaBridge 145:64910690c574 1111 /* Debug Security Control and Status Register Definitions */
AnnaBridge 145:64910690c574 1112 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
AnnaBridge 145:64910690c574 1113 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
AnnaBridge 145:64910690c574 1114
AnnaBridge 145:64910690c574 1115 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
AnnaBridge 145:64910690c574 1116 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
AnnaBridge 145:64910690c574 1117
AnnaBridge 145:64910690c574 1118 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
AnnaBridge 145:64910690c574 1119 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
AnnaBridge 145:64910690c574 1120
AnnaBridge 145:64910690c574 1121 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 145:64910690c574 1122
AnnaBridge 145:64910690c574 1123
AnnaBridge 145:64910690c574 1124 /**
AnnaBridge 145:64910690c574 1125 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 1126 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 145:64910690c574 1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 145:64910690c574 1128 @{
AnnaBridge 145:64910690c574 1129 */
AnnaBridge 145:64910690c574 1130
AnnaBridge 145:64910690c574 1131 /**
AnnaBridge 145:64910690c574 1132 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 145:64910690c574 1133 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 1135 \return Masked and shifted value.
AnnaBridge 145:64910690c574 1136 */
AnnaBridge 145:64910690c574 1137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 145:64910690c574 1138
AnnaBridge 145:64910690c574 1139 /**
AnnaBridge 145:64910690c574 1140 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 145:64910690c574 1141 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 1143 \return Masked and shifted bit field value.
AnnaBridge 145:64910690c574 1144 */
AnnaBridge 145:64910690c574 1145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 145:64910690c574 1146
AnnaBridge 145:64910690c574 1147 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 145:64910690c574 1148
AnnaBridge 145:64910690c574 1149
AnnaBridge 145:64910690c574 1150 /**
AnnaBridge 145:64910690c574 1151 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 1152 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 145:64910690c574 1153 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 145:64910690c574 1154 @{
AnnaBridge 145:64910690c574 1155 */
AnnaBridge 145:64910690c574 1156
AnnaBridge 145:64910690c574 1157 /* Memory mapping of Core Hardware */
AnnaBridge 145:64910690c574 1158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 145:64910690c574 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 145:64910690c574 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 145:64910690c574 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 145:64910690c574 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 145:64910690c574 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 145:64910690c574 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 145:64910690c574 1165
AnnaBridge 145:64910690c574 1166
AnnaBridge 145:64910690c574 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 145:64910690c574 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 145:64910690c574 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 145:64910690c574 1170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 145:64910690c574 1171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 145:64910690c574 1172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
AnnaBridge 145:64910690c574 1173
AnnaBridge 145:64910690c574 1174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 1175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 145:64910690c574 1176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 145:64910690c574 1177 #endif
AnnaBridge 145:64910690c574 1178
AnnaBridge 145:64910690c574 1179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 145:64910690c574 1180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
AnnaBridge 145:64910690c574 1181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
AnnaBridge 145:64910690c574 1182 #endif
AnnaBridge 145:64910690c574 1183
AnnaBridge 145:64910690c574 1184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 145:64910690c574 1185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
AnnaBridge 145:64910690c574 1186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
AnnaBridge 145:64910690c574 1187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
AnnaBridge 145:64910690c574 1188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
AnnaBridge 145:64910690c574 1189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
AnnaBridge 145:64910690c574 1190
AnnaBridge 145:64910690c574 1191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
AnnaBridge 145:64910690c574 1192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
AnnaBridge 145:64910690c574 1193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
AnnaBridge 145:64910690c574 1194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
AnnaBridge 145:64910690c574 1195
AnnaBridge 145:64910690c574 1196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 1197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 145:64910690c574 1198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 145:64910690c574 1199 #endif
AnnaBridge 145:64910690c574 1200
AnnaBridge 145:64910690c574 1201 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 145:64910690c574 1202 /*@} */
AnnaBridge 145:64910690c574 1203
AnnaBridge 145:64910690c574 1204
AnnaBridge 145:64910690c574 1205
AnnaBridge 145:64910690c574 1206 /*******************************************************************************
AnnaBridge 145:64910690c574 1207 * Hardware Abstraction Layer
AnnaBridge 145:64910690c574 1208 Core Function Interface contains:
AnnaBridge 145:64910690c574 1209 - Core NVIC Functions
AnnaBridge 145:64910690c574 1210 - Core SysTick Functions
AnnaBridge 145:64910690c574 1211 - Core Register Access Functions
AnnaBridge 145:64910690c574 1212 ******************************************************************************/
AnnaBridge 145:64910690c574 1213 /**
AnnaBridge 145:64910690c574 1214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 145:64910690c574 1215 */
AnnaBridge 145:64910690c574 1216
AnnaBridge 145:64910690c574 1217
AnnaBridge 145:64910690c574 1218
AnnaBridge 145:64910690c574 1219 /* ########################## NVIC functions #################################### */
AnnaBridge 145:64910690c574 1220 /**
AnnaBridge 145:64910690c574 1221 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 145:64910690c574 1223 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 145:64910690c574 1224 @{
AnnaBridge 145:64910690c574 1225 */
AnnaBridge 145:64910690c574 1226
AnnaBridge 145:64910690c574 1227 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 145:64910690c574 1228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 1229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 145:64910690c574 1230 #endif
AnnaBridge 145:64910690c574 1231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 1232 #else
AnnaBridge 145:64910690c574 1233 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
AnnaBridge 145:64910690c574 1234 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
AnnaBridge 145:64910690c574 1235 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 145:64910690c574 1236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 145:64910690c574 1237 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 145:64910690c574 1238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 145:64910690c574 1239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 145:64910690c574 1240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 145:64910690c574 1241 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 145:64910690c574 1242 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 145:64910690c574 1243 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 145:64910690c574 1244 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 145:64910690c574 1245 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 145:64910690c574 1246
AnnaBridge 145:64910690c574 1247 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 145:64910690c574 1248 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 1249 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 145:64910690c574 1250 #endif
AnnaBridge 145:64910690c574 1251 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 1252 #else
AnnaBridge 145:64910690c574 1253 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 145:64910690c574 1254 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 145:64910690c574 1255 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 145:64910690c574 1256
AnnaBridge 145:64910690c574 1257 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 145:64910690c574 1258
AnnaBridge 145:64910690c574 1259
AnnaBridge 145:64910690c574 1260 /* Interrupt Priorities are WORD accessible only under ARMv6M */
AnnaBridge 145:64910690c574 1261 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 145:64910690c574 1262 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 145:64910690c574 1263 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 145:64910690c574 1264 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 145:64910690c574 1265
AnnaBridge 145:64910690c574 1266
AnnaBridge 145:64910690c574 1267 /**
AnnaBridge 145:64910690c574 1268 \brief Enable Interrupt
AnnaBridge 145:64910690c574 1269 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 1270 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1271 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1272 */
AnnaBridge 145:64910690c574 1273 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1274 {
AnnaBridge 145:64910690c574 1275 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1276 {
AnnaBridge 145:64910690c574 1277 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1278 }
AnnaBridge 145:64910690c574 1279 }
AnnaBridge 145:64910690c574 1280
AnnaBridge 145:64910690c574 1281
AnnaBridge 145:64910690c574 1282 /**
AnnaBridge 145:64910690c574 1283 \brief Get Interrupt Enable status
AnnaBridge 145:64910690c574 1284 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 145:64910690c574 1285 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1286 \return 0 Interrupt is not enabled.
AnnaBridge 145:64910690c574 1287 \return 1 Interrupt is enabled.
AnnaBridge 145:64910690c574 1288 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1289 */
AnnaBridge 145:64910690c574 1290 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1291 {
AnnaBridge 145:64910690c574 1292 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1293 {
AnnaBridge 145:64910690c574 1294 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1295 }
AnnaBridge 145:64910690c574 1296 else
AnnaBridge 145:64910690c574 1297 {
AnnaBridge 145:64910690c574 1298 return(0U);
AnnaBridge 145:64910690c574 1299 }
AnnaBridge 145:64910690c574 1300 }
AnnaBridge 145:64910690c574 1301
AnnaBridge 145:64910690c574 1302
AnnaBridge 145:64910690c574 1303 /**
AnnaBridge 145:64910690c574 1304 \brief Disable Interrupt
AnnaBridge 145:64910690c574 1305 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 1306 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1307 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1308 */
AnnaBridge 145:64910690c574 1309 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1310 {
AnnaBridge 145:64910690c574 1311 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1312 {
AnnaBridge 145:64910690c574 1313 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1314 __DSB();
AnnaBridge 145:64910690c574 1315 __ISB();
AnnaBridge 145:64910690c574 1316 }
AnnaBridge 145:64910690c574 1317 }
AnnaBridge 145:64910690c574 1318
AnnaBridge 145:64910690c574 1319
AnnaBridge 145:64910690c574 1320 /**
AnnaBridge 145:64910690c574 1321 \brief Get Pending Interrupt
AnnaBridge 145:64910690c574 1322 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 145:64910690c574 1323 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1324 \return 0 Interrupt status is not pending.
AnnaBridge 145:64910690c574 1325 \return 1 Interrupt status is pending.
AnnaBridge 145:64910690c574 1326 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1327 */
AnnaBridge 145:64910690c574 1328 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1329 {
AnnaBridge 145:64910690c574 1330 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1331 {
AnnaBridge 145:64910690c574 1332 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1333 }
AnnaBridge 145:64910690c574 1334 else
AnnaBridge 145:64910690c574 1335 {
AnnaBridge 145:64910690c574 1336 return(0U);
AnnaBridge 145:64910690c574 1337 }
AnnaBridge 145:64910690c574 1338 }
AnnaBridge 145:64910690c574 1339
AnnaBridge 145:64910690c574 1340
AnnaBridge 145:64910690c574 1341 /**
AnnaBridge 145:64910690c574 1342 \brief Set Pending Interrupt
AnnaBridge 145:64910690c574 1343 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 1344 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1345 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1346 */
AnnaBridge 145:64910690c574 1347 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1348 {
AnnaBridge 145:64910690c574 1349 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1350 {
AnnaBridge 145:64910690c574 1351 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1352 }
AnnaBridge 145:64910690c574 1353 }
AnnaBridge 145:64910690c574 1354
AnnaBridge 145:64910690c574 1355
AnnaBridge 145:64910690c574 1356 /**
AnnaBridge 145:64910690c574 1357 \brief Clear Pending Interrupt
AnnaBridge 145:64910690c574 1358 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 1359 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1360 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1361 */
AnnaBridge 145:64910690c574 1362 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1363 {
AnnaBridge 145:64910690c574 1364 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1365 {
AnnaBridge 145:64910690c574 1366 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1367 }
AnnaBridge 145:64910690c574 1368 }
AnnaBridge 145:64910690c574 1369
AnnaBridge 145:64910690c574 1370
AnnaBridge 145:64910690c574 1371 /**
AnnaBridge 145:64910690c574 1372 \brief Get Active Interrupt
AnnaBridge 145:64910690c574 1373 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 145:64910690c574 1374 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1375 \return 0 Interrupt status is not active.
AnnaBridge 145:64910690c574 1376 \return 1 Interrupt status is active.
AnnaBridge 145:64910690c574 1377 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1378 */
AnnaBridge 145:64910690c574 1379 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1380 {
AnnaBridge 145:64910690c574 1381 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1382 {
AnnaBridge 145:64910690c574 1383 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1384 }
AnnaBridge 145:64910690c574 1385 else
AnnaBridge 145:64910690c574 1386 {
AnnaBridge 145:64910690c574 1387 return(0U);
AnnaBridge 145:64910690c574 1388 }
AnnaBridge 145:64910690c574 1389 }
AnnaBridge 145:64910690c574 1390
AnnaBridge 145:64910690c574 1391
AnnaBridge 145:64910690c574 1392 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 145:64910690c574 1393 /**
AnnaBridge 145:64910690c574 1394 \brief Get Interrupt Target State
AnnaBridge 145:64910690c574 1395 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 145:64910690c574 1396 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1397 \return 0 if interrupt is assigned to Secure
AnnaBridge 145:64910690c574 1398 \return 1 if interrupt is assigned to Non Secure
AnnaBridge 145:64910690c574 1399 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1400 */
AnnaBridge 145:64910690c574 1401 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1402 {
AnnaBridge 145:64910690c574 1403 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1404 {
AnnaBridge 145:64910690c574 1405 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1406 }
AnnaBridge 145:64910690c574 1407 else
AnnaBridge 145:64910690c574 1408 {
AnnaBridge 145:64910690c574 1409 return(0U);
AnnaBridge 145:64910690c574 1410 }
AnnaBridge 145:64910690c574 1411 }
AnnaBridge 145:64910690c574 1412
AnnaBridge 145:64910690c574 1413
AnnaBridge 145:64910690c574 1414 /**
AnnaBridge 145:64910690c574 1415 \brief Set Interrupt Target State
AnnaBridge 145:64910690c574 1416 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 145:64910690c574 1417 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1418 \return 0 if interrupt is assigned to Secure
AnnaBridge 145:64910690c574 1419 1 if interrupt is assigned to Non Secure
AnnaBridge 145:64910690c574 1420 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1421 */
AnnaBridge 145:64910690c574 1422 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1423 {
AnnaBridge 145:64910690c574 1424 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1425 {
AnnaBridge 145:64910690c574 1426 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge 145:64910690c574 1427 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1428 }
AnnaBridge 145:64910690c574 1429 else
AnnaBridge 145:64910690c574 1430 {
AnnaBridge 145:64910690c574 1431 return(0U);
AnnaBridge 145:64910690c574 1432 }
AnnaBridge 145:64910690c574 1433 }
AnnaBridge 145:64910690c574 1434
AnnaBridge 145:64910690c574 1435
AnnaBridge 145:64910690c574 1436 /**
AnnaBridge 145:64910690c574 1437 \brief Clear Interrupt Target State
AnnaBridge 145:64910690c574 1438 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 145:64910690c574 1439 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1440 \return 0 if interrupt is assigned to Secure
AnnaBridge 145:64910690c574 1441 1 if interrupt is assigned to Non Secure
AnnaBridge 145:64910690c574 1442 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1443 */
AnnaBridge 145:64910690c574 1444 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1445 {
AnnaBridge 145:64910690c574 1446 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1447 {
AnnaBridge 145:64910690c574 1448 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
AnnaBridge 145:64910690c574 1449 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1450 }
AnnaBridge 145:64910690c574 1451 else
AnnaBridge 145:64910690c574 1452 {
AnnaBridge 145:64910690c574 1453 return(0U);
AnnaBridge 145:64910690c574 1454 }
AnnaBridge 145:64910690c574 1455 }
AnnaBridge 145:64910690c574 1456 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 145:64910690c574 1457
AnnaBridge 145:64910690c574 1458
AnnaBridge 145:64910690c574 1459 /**
AnnaBridge 145:64910690c574 1460 \brief Set Interrupt Priority
AnnaBridge 145:64910690c574 1461 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 1462 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1463 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1464 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1465 \param [in] priority Priority to set.
AnnaBridge 145:64910690c574 1466 \note The priority cannot be set for every processor exception.
AnnaBridge 145:64910690c574 1467 */
AnnaBridge 145:64910690c574 1468 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 145:64910690c574 1469 {
AnnaBridge 145:64910690c574 1470 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1471 {
AnnaBridge 145:64910690c574 1472 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 1473 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 145:64910690c574 1474 }
AnnaBridge 145:64910690c574 1475 else
AnnaBridge 145:64910690c574 1476 {
AnnaBridge 145:64910690c574 1477 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 1478 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 145:64910690c574 1479 }
AnnaBridge 145:64910690c574 1480 }
AnnaBridge 145:64910690c574 1481
AnnaBridge 145:64910690c574 1482
AnnaBridge 145:64910690c574 1483 /**
AnnaBridge 145:64910690c574 1484 \brief Get Interrupt Priority
AnnaBridge 145:64910690c574 1485 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 1486 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1487 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1488 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1489 \return Interrupt Priority.
AnnaBridge 145:64910690c574 1490 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 145:64910690c574 1491 */
AnnaBridge 145:64910690c574 1492 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1493 {
AnnaBridge 145:64910690c574 1494
AnnaBridge 145:64910690c574 1495 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1496 {
AnnaBridge 145:64910690c574 1497 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 1498 }
AnnaBridge 145:64910690c574 1499 else
AnnaBridge 145:64910690c574 1500 {
AnnaBridge 145:64910690c574 1501 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 1502 }
AnnaBridge 145:64910690c574 1503 }
AnnaBridge 145:64910690c574 1504
AnnaBridge 145:64910690c574 1505
AnnaBridge 145:64910690c574 1506 /**
AnnaBridge 145:64910690c574 1507 \brief Set Interrupt Vector
AnnaBridge 145:64910690c574 1508 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 145:64910690c574 1509 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1510 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1511 VTOR must been relocated to SRAM before.
AnnaBridge 145:64910690c574 1512 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 145:64910690c574 1513 \param [in] IRQn Interrupt number
AnnaBridge 145:64910690c574 1514 \param [in] vector Address of interrupt handler function
AnnaBridge 145:64910690c574 1515 */
AnnaBridge 145:64910690c574 1516 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 145:64910690c574 1517 {
AnnaBridge 145:64910690c574 1518 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 145:64910690c574 1519 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 1520 #else
AnnaBridge 145:64910690c574 1521 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 145:64910690c574 1522 #endif
AnnaBridge 145:64910690c574 1523 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 145:64910690c574 1524 }
AnnaBridge 145:64910690c574 1525
AnnaBridge 145:64910690c574 1526
AnnaBridge 145:64910690c574 1527 /**
AnnaBridge 145:64910690c574 1528 \brief Get Interrupt Vector
AnnaBridge 145:64910690c574 1529 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 145:64910690c574 1530 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1531 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1532 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1533 \return Address of interrupt handler function
AnnaBridge 145:64910690c574 1534 */
AnnaBridge 145:64910690c574 1535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1536 {
AnnaBridge 145:64910690c574 1537 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 145:64910690c574 1538 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 1539 #else
AnnaBridge 145:64910690c574 1540 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 145:64910690c574 1541 #endif
AnnaBridge 145:64910690c574 1542 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 145:64910690c574 1543 }
AnnaBridge 145:64910690c574 1544
AnnaBridge 145:64910690c574 1545
AnnaBridge 145:64910690c574 1546 /**
AnnaBridge 145:64910690c574 1547 \brief System Reset
AnnaBridge 145:64910690c574 1548 \details Initiates a system reset request to reset the MCU.
AnnaBridge 145:64910690c574 1549 */
AnnaBridge 145:64910690c574 1550 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 145:64910690c574 1551 {
AnnaBridge 145:64910690c574 1552 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 145:64910690c574 1553 buffered write are completed before reset */
AnnaBridge 145:64910690c574 1554 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 145:64910690c574 1555 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 145:64910690c574 1556 __DSB(); /* Ensure completion of memory access */
AnnaBridge 145:64910690c574 1557
AnnaBridge 145:64910690c574 1558 for(;;) /* wait until reset */
AnnaBridge 145:64910690c574 1559 {
AnnaBridge 145:64910690c574 1560 __NOP();
AnnaBridge 145:64910690c574 1561 }
AnnaBridge 145:64910690c574 1562 }
AnnaBridge 145:64910690c574 1563
AnnaBridge 145:64910690c574 1564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 145:64910690c574 1565 /**
AnnaBridge 145:64910690c574 1566 \brief Enable Interrupt (non-secure)
AnnaBridge 145:64910690c574 1567 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 145:64910690c574 1568 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1569 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1570 */
AnnaBridge 145:64910690c574 1571 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1572 {
AnnaBridge 145:64910690c574 1573 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1574 {
AnnaBridge 145:64910690c574 1575 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1576 }
AnnaBridge 145:64910690c574 1577 }
AnnaBridge 145:64910690c574 1578
AnnaBridge 145:64910690c574 1579
AnnaBridge 145:64910690c574 1580 /**
AnnaBridge 145:64910690c574 1581 \brief Get Interrupt Enable status (non-secure)
AnnaBridge 145:64910690c574 1582 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 145:64910690c574 1583 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1584 \return 0 Interrupt is not enabled.
AnnaBridge 145:64910690c574 1585 \return 1 Interrupt is enabled.
AnnaBridge 145:64910690c574 1586 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1587 */
AnnaBridge 145:64910690c574 1588 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1589 {
AnnaBridge 145:64910690c574 1590 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1591 {
AnnaBridge 145:64910690c574 1592 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1593 }
AnnaBridge 145:64910690c574 1594 else
AnnaBridge 145:64910690c574 1595 {
AnnaBridge 145:64910690c574 1596 return(0U);
AnnaBridge 145:64910690c574 1597 }
AnnaBridge 145:64910690c574 1598 }
AnnaBridge 145:64910690c574 1599
AnnaBridge 145:64910690c574 1600
AnnaBridge 145:64910690c574 1601 /**
AnnaBridge 145:64910690c574 1602 \brief Disable Interrupt (non-secure)
AnnaBridge 145:64910690c574 1603 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 145:64910690c574 1604 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1605 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1606 */
AnnaBridge 145:64910690c574 1607 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1608 {
AnnaBridge 145:64910690c574 1609 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1610 {
AnnaBridge 145:64910690c574 1611 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1612 }
AnnaBridge 145:64910690c574 1613 }
AnnaBridge 145:64910690c574 1614
AnnaBridge 145:64910690c574 1615
AnnaBridge 145:64910690c574 1616 /**
AnnaBridge 145:64910690c574 1617 \brief Get Pending Interrupt (non-secure)
AnnaBridge 145:64910690c574 1618 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge 145:64910690c574 1619 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1620 \return 0 Interrupt status is not pending.
AnnaBridge 145:64910690c574 1621 \return 1 Interrupt status is pending.
AnnaBridge 145:64910690c574 1622 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1623 */
AnnaBridge 145:64910690c574 1624 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1625 {
AnnaBridge 145:64910690c574 1626 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1627 {
AnnaBridge 145:64910690c574 1628 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1629 }
AnnaBridge 145:64910690c574 1630 }
AnnaBridge 145:64910690c574 1631
AnnaBridge 145:64910690c574 1632
AnnaBridge 145:64910690c574 1633 /**
AnnaBridge 145:64910690c574 1634 \brief Set Pending Interrupt (non-secure)
AnnaBridge 145:64910690c574 1635 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 145:64910690c574 1636 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1637 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1638 */
AnnaBridge 145:64910690c574 1639 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1640 {
AnnaBridge 145:64910690c574 1641 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1642 {
AnnaBridge 145:64910690c574 1643 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1644 }
AnnaBridge 145:64910690c574 1645 }
AnnaBridge 145:64910690c574 1646
AnnaBridge 145:64910690c574 1647
AnnaBridge 145:64910690c574 1648 /**
AnnaBridge 145:64910690c574 1649 \brief Clear Pending Interrupt (non-secure)
AnnaBridge 145:64910690c574 1650 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 145:64910690c574 1651 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1652 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1653 */
AnnaBridge 145:64910690c574 1654 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1655 {
AnnaBridge 145:64910690c574 1656 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1657 {
AnnaBridge 145:64910690c574 1658 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 1659 }
AnnaBridge 145:64910690c574 1660 }
AnnaBridge 145:64910690c574 1661
AnnaBridge 145:64910690c574 1662
AnnaBridge 145:64910690c574 1663 /**
AnnaBridge 145:64910690c574 1664 \brief Get Active Interrupt (non-secure)
AnnaBridge 145:64910690c574 1665 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge 145:64910690c574 1666 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 1667 \return 0 Interrupt status is not active.
AnnaBridge 145:64910690c574 1668 \return 1 Interrupt status is active.
AnnaBridge 145:64910690c574 1669 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 1670 */
AnnaBridge 145:64910690c574 1671 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1672 {
AnnaBridge 145:64910690c574 1673 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1674 {
AnnaBridge 145:64910690c574 1675 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 1676 }
AnnaBridge 145:64910690c574 1677 else
AnnaBridge 145:64910690c574 1678 {
AnnaBridge 145:64910690c574 1679 return(0U);
AnnaBridge 145:64910690c574 1680 }
AnnaBridge 145:64910690c574 1681 }
AnnaBridge 145:64910690c574 1682
AnnaBridge 145:64910690c574 1683
AnnaBridge 145:64910690c574 1684 /**
AnnaBridge 145:64910690c574 1685 \brief Set Interrupt Priority (non-secure)
AnnaBridge 145:64910690c574 1686 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 145:64910690c574 1687 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1688 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1689 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1690 \param [in] priority Priority to set.
AnnaBridge 145:64910690c574 1691 \note The priority cannot be set for every non-secure processor exception.
AnnaBridge 145:64910690c574 1692 */
AnnaBridge 145:64910690c574 1693 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 145:64910690c574 1694 {
AnnaBridge 145:64910690c574 1695 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1696 {
AnnaBridge 145:64910690c574 1697 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 1698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 145:64910690c574 1699 }
AnnaBridge 145:64910690c574 1700 else
AnnaBridge 145:64910690c574 1701 {
AnnaBridge 145:64910690c574 1702 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 1703 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 145:64910690c574 1704 }
AnnaBridge 145:64910690c574 1705 }
AnnaBridge 145:64910690c574 1706
AnnaBridge 145:64910690c574 1707
AnnaBridge 145:64910690c574 1708 /**
AnnaBridge 145:64910690c574 1709 \brief Get Interrupt Priority (non-secure)
AnnaBridge 145:64910690c574 1710 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 145:64910690c574 1711 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 1712 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 1713 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 1714 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 145:64910690c574 1715 */
AnnaBridge 145:64910690c574 1716 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 1717 {
AnnaBridge 145:64910690c574 1718
AnnaBridge 145:64910690c574 1719 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 1720 {
AnnaBridge 145:64910690c574 1721 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 1722 }
AnnaBridge 145:64910690c574 1723 else
AnnaBridge 145:64910690c574 1724 {
AnnaBridge 145:64910690c574 1725 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 1726 }
AnnaBridge 145:64910690c574 1727 }
AnnaBridge 145:64910690c574 1728 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 145:64910690c574 1729
AnnaBridge 145:64910690c574 1730 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 145:64910690c574 1731
AnnaBridge 145:64910690c574 1732
AnnaBridge 145:64910690c574 1733 /* ########################## FPU functions #################################### */
AnnaBridge 145:64910690c574 1734 /**
AnnaBridge 145:64910690c574 1735 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1736 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 145:64910690c574 1737 \brief Function that provides FPU type.
AnnaBridge 145:64910690c574 1738 @{
AnnaBridge 145:64910690c574 1739 */
AnnaBridge 145:64910690c574 1740
AnnaBridge 145:64910690c574 1741 /**
AnnaBridge 145:64910690c574 1742 \brief get FPU type
AnnaBridge 145:64910690c574 1743 \details returns the FPU type
AnnaBridge 145:64910690c574 1744 \returns
AnnaBridge 145:64910690c574 1745 - \b 0: No FPU
AnnaBridge 145:64910690c574 1746 - \b 1: Single precision FPU
AnnaBridge 145:64910690c574 1747 - \b 2: Double + Single precision FPU
AnnaBridge 145:64910690c574 1748 */
AnnaBridge 145:64910690c574 1749 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 145:64910690c574 1750 {
AnnaBridge 145:64910690c574 1751 return 0U; /* No FPU */
AnnaBridge 145:64910690c574 1752 }
AnnaBridge 145:64910690c574 1753
AnnaBridge 145:64910690c574 1754
AnnaBridge 145:64910690c574 1755 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 145:64910690c574 1756
AnnaBridge 145:64910690c574 1757
AnnaBridge 145:64910690c574 1758
AnnaBridge 145:64910690c574 1759 /* ########################## SAU functions #################################### */
AnnaBridge 145:64910690c574 1760 /**
AnnaBridge 145:64910690c574 1761 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1762 \defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge 145:64910690c574 1763 \brief Functions that configure the SAU.
AnnaBridge 145:64910690c574 1764 @{
AnnaBridge 145:64910690c574 1765 */
AnnaBridge 145:64910690c574 1766
AnnaBridge 145:64910690c574 1767 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 145:64910690c574 1768
AnnaBridge 145:64910690c574 1769 /**
AnnaBridge 145:64910690c574 1770 \brief Enable SAU
AnnaBridge 145:64910690c574 1771 \details Enables the Security Attribution Unit (SAU).
AnnaBridge 145:64910690c574 1772 */
AnnaBridge 145:64910690c574 1773 __STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge 145:64910690c574 1774 {
AnnaBridge 145:64910690c574 1775 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
AnnaBridge 145:64910690c574 1776 }
AnnaBridge 145:64910690c574 1777
AnnaBridge 145:64910690c574 1778
AnnaBridge 145:64910690c574 1779
AnnaBridge 145:64910690c574 1780 /**
AnnaBridge 145:64910690c574 1781 \brief Disable SAU
AnnaBridge 145:64910690c574 1782 \details Disables the Security Attribution Unit (SAU).
AnnaBridge 145:64910690c574 1783 */
AnnaBridge 145:64910690c574 1784 __STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge 145:64910690c574 1785 {
AnnaBridge 145:64910690c574 1786 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge 145:64910690c574 1787 }
AnnaBridge 145:64910690c574 1788
AnnaBridge 145:64910690c574 1789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 145:64910690c574 1790
AnnaBridge 145:64910690c574 1791 /*@} end of CMSIS_Core_SAUFunctions */
AnnaBridge 145:64910690c574 1792
AnnaBridge 145:64910690c574 1793
AnnaBridge 145:64910690c574 1794
AnnaBridge 145:64910690c574 1795
AnnaBridge 145:64910690c574 1796 /* ################################## SysTick function ############################################ */
AnnaBridge 145:64910690c574 1797 /**
AnnaBridge 145:64910690c574 1798 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 1799 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 145:64910690c574 1800 \brief Functions that configure the System.
AnnaBridge 145:64910690c574 1801 @{
AnnaBridge 145:64910690c574 1802 */
AnnaBridge 145:64910690c574 1803
AnnaBridge 145:64910690c574 1804 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 145:64910690c574 1805
AnnaBridge 145:64910690c574 1806 /**
AnnaBridge 145:64910690c574 1807 \brief System Tick Configuration
AnnaBridge 145:64910690c574 1808 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 145:64910690c574 1809 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 145:64910690c574 1810 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 145:64910690c574 1811 \return 0 Function succeeded.
AnnaBridge 145:64910690c574 1812 \return 1 Function failed.
AnnaBridge 145:64910690c574 1813 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 145:64910690c574 1814 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 145:64910690c574 1815 must contain a vendor-specific implementation of this function.
AnnaBridge 145:64910690c574 1816 */
AnnaBridge 145:64910690c574 1817 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 145:64910690c574 1818 {
AnnaBridge 145:64910690c574 1819 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 145:64910690c574 1820 {
AnnaBridge 145:64910690c574 1821 return (1UL); /* Reload value impossible */
AnnaBridge 145:64910690c574 1822 }
AnnaBridge 145:64910690c574 1823
AnnaBridge 145:64910690c574 1824 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 145:64910690c574 1825 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 145:64910690c574 1826 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 145:64910690c574 1827 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 145:64910690c574 1828 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 145:64910690c574 1829 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 145:64910690c574 1830 return (0UL); /* Function successful */
AnnaBridge 145:64910690c574 1831 }
AnnaBridge 145:64910690c574 1832
AnnaBridge 145:64910690c574 1833 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 145:64910690c574 1834 /**
AnnaBridge 145:64910690c574 1835 \brief System Tick Configuration (non-secure)
AnnaBridge 145:64910690c574 1836 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge 145:64910690c574 1837 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 145:64910690c574 1838 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 145:64910690c574 1839 \return 0 Function succeeded.
AnnaBridge 145:64910690c574 1840 \return 1 Function failed.
AnnaBridge 145:64910690c574 1841 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 145:64910690c574 1842 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 145:64910690c574 1843 must contain a vendor-specific implementation of this function.
AnnaBridge 145:64910690c574 1844
AnnaBridge 145:64910690c574 1845 */
AnnaBridge 145:64910690c574 1846 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge 145:64910690c574 1847 {
AnnaBridge 145:64910690c574 1848 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 145:64910690c574 1849 {
AnnaBridge 145:64910690c574 1850 return (1UL); /* Reload value impossible */
AnnaBridge 145:64910690c574 1851 }
AnnaBridge 145:64910690c574 1852
AnnaBridge 145:64910690c574 1853 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 145:64910690c574 1854 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 145:64910690c574 1855 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 145:64910690c574 1856 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 145:64910690c574 1857 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 145:64910690c574 1858 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 145:64910690c574 1859 return (0UL); /* Function successful */
AnnaBridge 145:64910690c574 1860 }
AnnaBridge 145:64910690c574 1861 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 145:64910690c574 1862
AnnaBridge 145:64910690c574 1863 #endif
AnnaBridge 145:64910690c574 1864
AnnaBridge 145:64910690c574 1865 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 145:64910690c574 1866
AnnaBridge 145:64910690c574 1867
AnnaBridge 145:64910690c574 1868
AnnaBridge 145:64910690c574 1869
AnnaBridge 145:64910690c574 1870 #ifdef __cplusplus
AnnaBridge 145:64910690c574 1871 }
AnnaBridge 145:64910690c574 1872 #endif
AnnaBridge 145:64910690c574 1873
AnnaBridge 145:64910690c574 1874 #endif /* __CORE_CM23_H_DEPENDANT */
AnnaBridge 145:64910690c574 1875
AnnaBridge 145:64910690c574 1876 #endif /* __CMSIS_GENERIC */