mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_WIO_BG96/TOOLCHAIN_ARM_MICRO/stm32f439xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32f439xx.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
AnnaBridge 172:65be27845400 6 *
AnnaBridge 172:65be27845400 7 * This file contains:
AnnaBridge 172:65be27845400 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 172:65be27845400 9 * - peripherals registers declarations and bits definition
AnnaBridge 172:65be27845400 10 * - Macros to access peripheral's registers hardware
AnnaBridge 172:65be27845400 11 *
AnnaBridge 172:65be27845400 12 ******************************************************************************
AnnaBridge 172:65be27845400 13 * @attention
AnnaBridge 172:65be27845400 14 *
AnnaBridge 172:65be27845400 15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 16 *
AnnaBridge 172:65be27845400 17 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 18 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 19 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 20 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 22 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 23 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 25 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 26 * without specific prior written permission.
AnnaBridge 172:65be27845400 27 *
AnnaBridge 172:65be27845400 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 38 *
AnnaBridge 172:65be27845400 39 ******************************************************************************
AnnaBridge 172:65be27845400 40 */
AnnaBridge 172:65be27845400 41
AnnaBridge 172:65be27845400 42 /** @addtogroup CMSIS_Device
AnnaBridge 172:65be27845400 43 * @{
AnnaBridge 172:65be27845400 44 */
AnnaBridge 172:65be27845400 45
AnnaBridge 172:65be27845400 46 /** @addtogroup stm32f439xx
AnnaBridge 172:65be27845400 47 * @{
AnnaBridge 172:65be27845400 48 */
AnnaBridge 172:65be27845400 49
AnnaBridge 172:65be27845400 50 #ifndef __STM32F439xx_H
AnnaBridge 172:65be27845400 51 #define __STM32F439xx_H
AnnaBridge 172:65be27845400 52
AnnaBridge 172:65be27845400 53 #ifdef __cplusplus
AnnaBridge 172:65be27845400 54 extern "C" {
AnnaBridge 172:65be27845400 55 #endif /* __cplusplus */
AnnaBridge 172:65be27845400 56
AnnaBridge 172:65be27845400 57 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 172:65be27845400 58 * @{
AnnaBridge 172:65be27845400 59 */
AnnaBridge 172:65be27845400 60
AnnaBridge 172:65be27845400 61 /**
AnnaBridge 172:65be27845400 62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
AnnaBridge 172:65be27845400 63 */
AnnaBridge 172:65be27845400 64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
AnnaBridge 172:65be27845400 65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
AnnaBridge 172:65be27845400 66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
AnnaBridge 172:65be27845400 67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 172:65be27845400 68 /* MBED */
AnnaBridge 172:65be27845400 69 #ifndef __FPU_PRESENT
AnnaBridge 172:65be27845400 70 #define __FPU_PRESENT 1U /*!< FPU present */
AnnaBridge 172:65be27845400 71 #endif /* __FPU_PRESENT */
AnnaBridge 172:65be27845400 72 /* MBED */
AnnaBridge 172:65be27845400 73
AnnaBridge 172:65be27845400 74 /**
AnnaBridge 172:65be27845400 75 * @}
AnnaBridge 172:65be27845400 76 */
AnnaBridge 172:65be27845400 77
AnnaBridge 172:65be27845400 78 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 172:65be27845400 79 * @{
AnnaBridge 172:65be27845400 80 */
AnnaBridge 172:65be27845400 81
AnnaBridge 172:65be27845400 82 /**
AnnaBridge 172:65be27845400 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
AnnaBridge 172:65be27845400 84 * in @ref Library_configuration_section
AnnaBridge 172:65be27845400 85 */
AnnaBridge 172:65be27845400 86 typedef enum
AnnaBridge 172:65be27845400 87 {
AnnaBridge 172:65be27845400 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
AnnaBridge 172:65be27845400 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 172:65be27845400 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
AnnaBridge 172:65be27845400 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 172:65be27845400 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 172:65be27845400 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
AnnaBridge 172:65be27845400 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 172:65be27845400 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
AnnaBridge 172:65be27845400 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
AnnaBridge 172:65be27845400 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 172:65be27845400 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 172:65be27845400 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 172:65be27845400 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 172:65be27845400 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 172:65be27845400 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 172:65be27845400 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 172:65be27845400 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 172:65be27845400 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 172:65be27845400 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 172:65be27845400 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 172:65be27845400 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 172:65be27845400 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 172:65be27845400 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 172:65be27845400 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 172:65be27845400 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 172:65be27845400 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 172:65be27845400 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 172:65be27845400 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 172:65be27845400 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
AnnaBridge 172:65be27845400 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
AnnaBridge 172:65be27845400 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
AnnaBridge 172:65be27845400 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
AnnaBridge 172:65be27845400 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
AnnaBridge 172:65be27845400 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 172:65be27845400 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
AnnaBridge 172:65be27845400 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
AnnaBridge 172:65be27845400 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
AnnaBridge 172:65be27845400 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 172:65be27845400 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 172:65be27845400 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 172:65be27845400 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 172:65be27845400 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 172:65be27845400 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 172:65be27845400 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 172:65be27845400 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 172:65be27845400 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 172:65be27845400 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 172:65be27845400 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 172:65be27845400 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 172:65be27845400 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
AnnaBridge 172:65be27845400 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 172:65be27845400 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 172:65be27845400 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
AnnaBridge 172:65be27845400 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
AnnaBridge 172:65be27845400 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
AnnaBridge 172:65be27845400 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
AnnaBridge 172:65be27845400 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
AnnaBridge 172:65be27845400 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 172:65be27845400 146 FMC_IRQn = 48, /*!< FMC global Interrupt */
AnnaBridge 172:65be27845400 147 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
AnnaBridge 172:65be27845400 148 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 172:65be27845400 149 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 172:65be27845400 150 UART4_IRQn = 52, /*!< UART4 global Interrupt */
AnnaBridge 172:65be27845400 151 UART5_IRQn = 53, /*!< UART5 global Interrupt */
AnnaBridge 172:65be27845400 152 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
AnnaBridge 172:65be27845400 153 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
AnnaBridge 172:65be27845400 154 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 172:65be27845400 155 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 172:65be27845400 156 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 172:65be27845400 157 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 172:65be27845400 158 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 172:65be27845400 159 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
AnnaBridge 172:65be27845400 160 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
AnnaBridge 172:65be27845400 161 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
AnnaBridge 172:65be27845400 162 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
AnnaBridge 172:65be27845400 163 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
AnnaBridge 172:65be27845400 164 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
AnnaBridge 172:65be27845400 165 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
AnnaBridge 172:65be27845400 166 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 172:65be27845400 167 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 172:65be27845400 168 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 172:65be27845400 169 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 172:65be27845400 170 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 172:65be27845400 171 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 172:65be27845400 172 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
AnnaBridge 172:65be27845400 173 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
AnnaBridge 172:65be27845400 174 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
AnnaBridge 172:65be27845400 175 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
AnnaBridge 172:65be27845400 176 DCMI_IRQn = 78, /*!< DCMI global interrupt */
AnnaBridge 172:65be27845400 177 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
AnnaBridge 172:65be27845400 178 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
AnnaBridge 172:65be27845400 179 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 172:65be27845400 180 UART7_IRQn = 82, /*!< UART7 global interrupt */
AnnaBridge 172:65be27845400 181 UART8_IRQn = 83, /*!< UART8 global interrupt */
AnnaBridge 172:65be27845400 182 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
AnnaBridge 172:65be27845400 183 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
AnnaBridge 172:65be27845400 184 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
AnnaBridge 172:65be27845400 185 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
AnnaBridge 172:65be27845400 186 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
AnnaBridge 172:65be27845400 187 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
AnnaBridge 172:65be27845400 188 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
AnnaBridge 172:65be27845400 189 } IRQn_Type;
AnnaBridge 172:65be27845400 190
AnnaBridge 172:65be27845400 191 /**
AnnaBridge 172:65be27845400 192 * @}
AnnaBridge 172:65be27845400 193 */
AnnaBridge 172:65be27845400 194
AnnaBridge 172:65be27845400 195 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 172:65be27845400 196 #include "system_stm32f4xx.h"
AnnaBridge 172:65be27845400 197 #include <stdint.h>
AnnaBridge 172:65be27845400 198
AnnaBridge 172:65be27845400 199 /** @addtogroup Peripheral_registers_structures
AnnaBridge 172:65be27845400 200 * @{
AnnaBridge 172:65be27845400 201 */
AnnaBridge 172:65be27845400 202
AnnaBridge 172:65be27845400 203 /**
AnnaBridge 172:65be27845400 204 * @brief Analog to Digital Converter
AnnaBridge 172:65be27845400 205 */
AnnaBridge 172:65be27845400 206
AnnaBridge 172:65be27845400 207 typedef struct
AnnaBridge 172:65be27845400 208 {
AnnaBridge 172:65be27845400 209 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 210 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 172:65be27845400 211 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 172:65be27845400 212 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 172:65be27845400 213 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 172:65be27845400 214 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
AnnaBridge 172:65be27845400 215 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
AnnaBridge 172:65be27845400 216 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
AnnaBridge 172:65be27845400 217 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
AnnaBridge 172:65be27845400 218 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 219 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 220 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
AnnaBridge 172:65be27845400 221 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
AnnaBridge 172:65be27845400 222 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
AnnaBridge 172:65be27845400 223 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
AnnaBridge 172:65be27845400 224 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
AnnaBridge 172:65be27845400 225 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
AnnaBridge 172:65be27845400 226 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
AnnaBridge 172:65be27845400 227 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
AnnaBridge 172:65be27845400 228 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 229 } ADC_TypeDef;
AnnaBridge 172:65be27845400 230
AnnaBridge 172:65be27845400 231 typedef struct
AnnaBridge 172:65be27845400 232 {
AnnaBridge 172:65be27845400 233 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 172:65be27845400 234 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 172:65be27845400 235 __IO uint32_t CDR; /*!< ADC common regular data register for dual
AnnaBridge 172:65be27845400 236 AND triple modes, Address offset: ADC1 base address + 0x308 */
AnnaBridge 172:65be27845400 237 } ADC_Common_TypeDef;
AnnaBridge 172:65be27845400 238
AnnaBridge 172:65be27845400 239
AnnaBridge 172:65be27845400 240 /**
AnnaBridge 172:65be27845400 241 * @brief Controller Area Network TxMailBox
AnnaBridge 172:65be27845400 242 */
AnnaBridge 172:65be27845400 243
AnnaBridge 172:65be27845400 244 typedef struct
AnnaBridge 172:65be27845400 245 {
AnnaBridge 172:65be27845400 246 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
AnnaBridge 172:65be27845400 247 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
AnnaBridge 172:65be27845400 248 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
AnnaBridge 172:65be27845400 249 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
AnnaBridge 172:65be27845400 250 } CAN_TxMailBox_TypeDef;
AnnaBridge 172:65be27845400 251
AnnaBridge 172:65be27845400 252 /**
AnnaBridge 172:65be27845400 253 * @brief Controller Area Network FIFOMailBox
AnnaBridge 172:65be27845400 254 */
AnnaBridge 172:65be27845400 255
AnnaBridge 172:65be27845400 256 typedef struct
AnnaBridge 172:65be27845400 257 {
AnnaBridge 172:65be27845400 258 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
AnnaBridge 172:65be27845400 259 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
AnnaBridge 172:65be27845400 260 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
AnnaBridge 172:65be27845400 261 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
AnnaBridge 172:65be27845400 262 } CAN_FIFOMailBox_TypeDef;
AnnaBridge 172:65be27845400 263
AnnaBridge 172:65be27845400 264 /**
AnnaBridge 172:65be27845400 265 * @brief Controller Area Network FilterRegister
AnnaBridge 172:65be27845400 266 */
AnnaBridge 172:65be27845400 267
AnnaBridge 172:65be27845400 268 typedef struct
AnnaBridge 172:65be27845400 269 {
AnnaBridge 172:65be27845400 270 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
AnnaBridge 172:65be27845400 271 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
AnnaBridge 172:65be27845400 272 } CAN_FilterRegister_TypeDef;
AnnaBridge 172:65be27845400 273
AnnaBridge 172:65be27845400 274 /**
AnnaBridge 172:65be27845400 275 * @brief Controller Area Network
AnnaBridge 172:65be27845400 276 */
AnnaBridge 172:65be27845400 277
AnnaBridge 172:65be27845400 278 typedef struct
AnnaBridge 172:65be27845400 279 {
AnnaBridge 172:65be27845400 280 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 281 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 282 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 283 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 284 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 285 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 286 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 287 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 288 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
AnnaBridge 172:65be27845400 289 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
AnnaBridge 172:65be27845400 290 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
AnnaBridge 172:65be27845400 291 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
AnnaBridge 172:65be27845400 292 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
AnnaBridge 172:65be27845400 293 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
AnnaBridge 172:65be27845400 294 uint32_t RESERVED2; /*!< Reserved, 0x208 */
AnnaBridge 172:65be27845400 295 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
AnnaBridge 172:65be27845400 296 uint32_t RESERVED3; /*!< Reserved, 0x210 */
AnnaBridge 172:65be27845400 297 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
AnnaBridge 172:65be27845400 298 uint32_t RESERVED4; /*!< Reserved, 0x218 */
AnnaBridge 172:65be27845400 299 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
AnnaBridge 172:65be27845400 300 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
AnnaBridge 172:65be27845400 301 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
AnnaBridge 172:65be27845400 302 } CAN_TypeDef;
AnnaBridge 172:65be27845400 303
AnnaBridge 172:65be27845400 304 /**
AnnaBridge 172:65be27845400 305 * @brief CRC calculation unit
AnnaBridge 172:65be27845400 306 */
AnnaBridge 172:65be27845400 307
AnnaBridge 172:65be27845400 308 typedef struct
AnnaBridge 172:65be27845400 309 {
AnnaBridge 172:65be27845400 310 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 311 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 312 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 172:65be27845400 313 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 172:65be27845400 314 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 315 } CRC_TypeDef;
AnnaBridge 172:65be27845400 316
AnnaBridge 172:65be27845400 317 /**
AnnaBridge 172:65be27845400 318 * @brief Digital to Analog Converter
AnnaBridge 172:65be27845400 319 */
AnnaBridge 172:65be27845400 320
AnnaBridge 172:65be27845400 321 typedef struct
AnnaBridge 172:65be27845400 322 {
AnnaBridge 172:65be27845400 323 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 324 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 325 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 326 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 327 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 328 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 329 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 330 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 331 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 332 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 333 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 334 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 335 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 336 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 337 } DAC_TypeDef;
AnnaBridge 172:65be27845400 338
AnnaBridge 172:65be27845400 339 /**
AnnaBridge 172:65be27845400 340 * @brief Debug MCU
AnnaBridge 172:65be27845400 341 */
AnnaBridge 172:65be27845400 342
AnnaBridge 172:65be27845400 343 typedef struct
AnnaBridge 172:65be27845400 344 {
AnnaBridge 172:65be27845400 345 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 172:65be27845400 346 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 347 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 348 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 349 }DBGMCU_TypeDef;
AnnaBridge 172:65be27845400 350
AnnaBridge 172:65be27845400 351 /**
AnnaBridge 172:65be27845400 352 * @brief DCMI
AnnaBridge 172:65be27845400 353 */
AnnaBridge 172:65be27845400 354
AnnaBridge 172:65be27845400 355 typedef struct
AnnaBridge 172:65be27845400 356 {
AnnaBridge 172:65be27845400 357 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 358 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 359 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 360 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 361 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 362 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 363 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 364 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 365 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
AnnaBridge 172:65be27845400 366 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
AnnaBridge 172:65be27845400 367 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 368 } DCMI_TypeDef;
AnnaBridge 172:65be27845400 369
AnnaBridge 172:65be27845400 370 /**
AnnaBridge 172:65be27845400 371 * @brief DMA Controller
AnnaBridge 172:65be27845400 372 */
AnnaBridge 172:65be27845400 373
AnnaBridge 172:65be27845400 374 typedef struct
AnnaBridge 172:65be27845400 375 {
AnnaBridge 172:65be27845400 376 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 172:65be27845400 377 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 172:65be27845400 378 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 172:65be27845400 379 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 172:65be27845400 380 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 172:65be27845400 381 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 172:65be27845400 382 } DMA_Stream_TypeDef;
AnnaBridge 172:65be27845400 383
AnnaBridge 172:65be27845400 384 typedef struct
AnnaBridge 172:65be27845400 385 {
AnnaBridge 172:65be27845400 386 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 387 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 388 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 389 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 390 } DMA_TypeDef;
AnnaBridge 172:65be27845400 391
AnnaBridge 172:65be27845400 392 /**
AnnaBridge 172:65be27845400 393 * @brief DMA2D Controller
AnnaBridge 172:65be27845400 394 */
AnnaBridge 172:65be27845400 395
AnnaBridge 172:65be27845400 396 typedef struct
AnnaBridge 172:65be27845400 397 {
AnnaBridge 172:65be27845400 398 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 399 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 400 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 401 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 402 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 403 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 404 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 405 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 406 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 407 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 408 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 409 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 410 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 411 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 412 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 413 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 414 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 415 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 416 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 417 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 418 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
AnnaBridge 172:65be27845400 419 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
AnnaBridge 172:65be27845400 420 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
AnnaBridge 172:65be27845400 421 } DMA2D_TypeDef;
AnnaBridge 172:65be27845400 422
AnnaBridge 172:65be27845400 423 /**
AnnaBridge 172:65be27845400 424 * @brief Ethernet MAC
AnnaBridge 172:65be27845400 425 */
AnnaBridge 172:65be27845400 426
AnnaBridge 172:65be27845400 427 typedef struct
AnnaBridge 172:65be27845400 428 {
AnnaBridge 172:65be27845400 429 __IO uint32_t MACCR;
AnnaBridge 172:65be27845400 430 __IO uint32_t MACFFR;
AnnaBridge 172:65be27845400 431 __IO uint32_t MACHTHR;
AnnaBridge 172:65be27845400 432 __IO uint32_t MACHTLR;
AnnaBridge 172:65be27845400 433 __IO uint32_t MACMIIAR;
AnnaBridge 172:65be27845400 434 __IO uint32_t MACMIIDR;
AnnaBridge 172:65be27845400 435 __IO uint32_t MACFCR;
AnnaBridge 172:65be27845400 436 __IO uint32_t MACVLANTR; /* 8 */
AnnaBridge 172:65be27845400 437 uint32_t RESERVED0[2];
AnnaBridge 172:65be27845400 438 __IO uint32_t MACRWUFFR; /* 11 */
AnnaBridge 172:65be27845400 439 __IO uint32_t MACPMTCSR;
AnnaBridge 172:65be27845400 440 uint32_t RESERVED1;
AnnaBridge 172:65be27845400 441 __IO uint32_t MACDBGR;
AnnaBridge 172:65be27845400 442 __IO uint32_t MACSR; /* 15 */
AnnaBridge 172:65be27845400 443 __IO uint32_t MACIMR;
AnnaBridge 172:65be27845400 444 __IO uint32_t MACA0HR;
AnnaBridge 172:65be27845400 445 __IO uint32_t MACA0LR;
AnnaBridge 172:65be27845400 446 __IO uint32_t MACA1HR;
AnnaBridge 172:65be27845400 447 __IO uint32_t MACA1LR;
AnnaBridge 172:65be27845400 448 __IO uint32_t MACA2HR;
AnnaBridge 172:65be27845400 449 __IO uint32_t MACA2LR;
AnnaBridge 172:65be27845400 450 __IO uint32_t MACA3HR;
AnnaBridge 172:65be27845400 451 __IO uint32_t MACA3LR; /* 24 */
AnnaBridge 172:65be27845400 452 uint32_t RESERVED2[40];
AnnaBridge 172:65be27845400 453 __IO uint32_t MMCCR; /* 65 */
AnnaBridge 172:65be27845400 454 __IO uint32_t MMCRIR;
AnnaBridge 172:65be27845400 455 __IO uint32_t MMCTIR;
AnnaBridge 172:65be27845400 456 __IO uint32_t MMCRIMR;
AnnaBridge 172:65be27845400 457 __IO uint32_t MMCTIMR; /* 69 */
AnnaBridge 172:65be27845400 458 uint32_t RESERVED3[14];
AnnaBridge 172:65be27845400 459 __IO uint32_t MMCTGFSCCR; /* 84 */
AnnaBridge 172:65be27845400 460 __IO uint32_t MMCTGFMSCCR;
AnnaBridge 172:65be27845400 461 uint32_t RESERVED4[5];
AnnaBridge 172:65be27845400 462 __IO uint32_t MMCTGFCR;
AnnaBridge 172:65be27845400 463 uint32_t RESERVED5[10];
AnnaBridge 172:65be27845400 464 __IO uint32_t MMCRFCECR;
AnnaBridge 172:65be27845400 465 __IO uint32_t MMCRFAECR;
AnnaBridge 172:65be27845400 466 uint32_t RESERVED6[10];
AnnaBridge 172:65be27845400 467 __IO uint32_t MMCRGUFCR;
AnnaBridge 172:65be27845400 468 uint32_t RESERVED7[334];
AnnaBridge 172:65be27845400 469 __IO uint32_t PTPTSCR;
AnnaBridge 172:65be27845400 470 __IO uint32_t PTPSSIR;
AnnaBridge 172:65be27845400 471 __IO uint32_t PTPTSHR;
AnnaBridge 172:65be27845400 472 __IO uint32_t PTPTSLR;
AnnaBridge 172:65be27845400 473 __IO uint32_t PTPTSHUR;
AnnaBridge 172:65be27845400 474 __IO uint32_t PTPTSLUR;
AnnaBridge 172:65be27845400 475 __IO uint32_t PTPTSAR;
AnnaBridge 172:65be27845400 476 __IO uint32_t PTPTTHR;
AnnaBridge 172:65be27845400 477 __IO uint32_t PTPTTLR;
AnnaBridge 172:65be27845400 478 __IO uint32_t RESERVED8;
AnnaBridge 172:65be27845400 479 __IO uint32_t PTPTSSR;
AnnaBridge 172:65be27845400 480 uint32_t RESERVED9[565];
AnnaBridge 172:65be27845400 481 __IO uint32_t DMABMR;
AnnaBridge 172:65be27845400 482 __IO uint32_t DMATPDR;
AnnaBridge 172:65be27845400 483 __IO uint32_t DMARPDR;
AnnaBridge 172:65be27845400 484 __IO uint32_t DMARDLAR;
AnnaBridge 172:65be27845400 485 __IO uint32_t DMATDLAR;
AnnaBridge 172:65be27845400 486 __IO uint32_t DMASR;
AnnaBridge 172:65be27845400 487 __IO uint32_t DMAOMR;
AnnaBridge 172:65be27845400 488 __IO uint32_t DMAIER;
AnnaBridge 172:65be27845400 489 __IO uint32_t DMAMFBOCR;
AnnaBridge 172:65be27845400 490 __IO uint32_t DMARSWTR;
AnnaBridge 172:65be27845400 491 uint32_t RESERVED10[8];
AnnaBridge 172:65be27845400 492 __IO uint32_t DMACHTDR;
AnnaBridge 172:65be27845400 493 __IO uint32_t DMACHRDR;
AnnaBridge 172:65be27845400 494 __IO uint32_t DMACHTBAR;
AnnaBridge 172:65be27845400 495 __IO uint32_t DMACHRBAR;
AnnaBridge 172:65be27845400 496 } ETH_TypeDef;
AnnaBridge 172:65be27845400 497
AnnaBridge 172:65be27845400 498 /**
AnnaBridge 172:65be27845400 499 * @brief External Interrupt/Event Controller
AnnaBridge 172:65be27845400 500 */
AnnaBridge 172:65be27845400 501
AnnaBridge 172:65be27845400 502 typedef struct
AnnaBridge 172:65be27845400 503 {
AnnaBridge 172:65be27845400 504 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 505 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 506 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 507 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 508 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 509 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 510 } EXTI_TypeDef;
AnnaBridge 172:65be27845400 511
AnnaBridge 172:65be27845400 512 /**
AnnaBridge 172:65be27845400 513 * @brief FLASH Registers
AnnaBridge 172:65be27845400 514 */
AnnaBridge 172:65be27845400 515
AnnaBridge 172:65be27845400 516 typedef struct
AnnaBridge 172:65be27845400 517 {
AnnaBridge 172:65be27845400 518 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 519 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 520 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 521 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 522 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 523 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
AnnaBridge 172:65be27845400 524 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
AnnaBridge 172:65be27845400 525 } FLASH_TypeDef;
AnnaBridge 172:65be27845400 526
AnnaBridge 172:65be27845400 527 /**
AnnaBridge 172:65be27845400 528 * @brief Flexible Memory Controller
AnnaBridge 172:65be27845400 529 */
AnnaBridge 172:65be27845400 530
AnnaBridge 172:65be27845400 531 typedef struct
AnnaBridge 172:65be27845400 532 {
AnnaBridge 172:65be27845400 533 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
AnnaBridge 172:65be27845400 534 } FMC_Bank1_TypeDef;
AnnaBridge 172:65be27845400 535
AnnaBridge 172:65be27845400 536 /**
AnnaBridge 172:65be27845400 537 * @brief Flexible Memory Controller Bank1E
AnnaBridge 172:65be27845400 538 */
AnnaBridge 172:65be27845400 539
AnnaBridge 172:65be27845400 540 typedef struct
AnnaBridge 172:65be27845400 541 {
AnnaBridge 172:65be27845400 542 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
AnnaBridge 172:65be27845400 543 } FMC_Bank1E_TypeDef;
AnnaBridge 172:65be27845400 544 /**
AnnaBridge 172:65be27845400 545 * @brief Flexible Memory Controller Bank2
AnnaBridge 172:65be27845400 546 */
AnnaBridge 172:65be27845400 547
AnnaBridge 172:65be27845400 548 typedef struct
AnnaBridge 172:65be27845400 549 {
AnnaBridge 172:65be27845400 550 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
AnnaBridge 172:65be27845400 551 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
AnnaBridge 172:65be27845400 552 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
AnnaBridge 172:65be27845400 553 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
AnnaBridge 172:65be27845400 554 uint32_t RESERVED0; /*!< Reserved, 0x70 */
AnnaBridge 172:65be27845400 555 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
AnnaBridge 172:65be27845400 556 uint32_t RESERVED1; /*!< Reserved, 0x78 */
AnnaBridge 172:65be27845400 557 uint32_t RESERVED2; /*!< Reserved, 0x7C */
AnnaBridge 172:65be27845400 558 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
AnnaBridge 172:65be27845400 559 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
AnnaBridge 172:65be27845400 560 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
AnnaBridge 172:65be27845400 561 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
AnnaBridge 172:65be27845400 562 uint32_t RESERVED3; /*!< Reserved, 0x90 */
AnnaBridge 172:65be27845400 563 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
AnnaBridge 172:65be27845400 564 } FMC_Bank2_3_TypeDef;
AnnaBridge 172:65be27845400 565
AnnaBridge 172:65be27845400 566 /**
AnnaBridge 172:65be27845400 567 * @brief Flexible Memory Controller Bank4
AnnaBridge 172:65be27845400 568 */
AnnaBridge 172:65be27845400 569
AnnaBridge 172:65be27845400 570 typedef struct
AnnaBridge 172:65be27845400 571 {
AnnaBridge 172:65be27845400 572 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
AnnaBridge 172:65be27845400 573 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
AnnaBridge 172:65be27845400 574 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
AnnaBridge 172:65be27845400 575 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
AnnaBridge 172:65be27845400 576 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
AnnaBridge 172:65be27845400 577 } FMC_Bank4_TypeDef;
AnnaBridge 172:65be27845400 578
AnnaBridge 172:65be27845400 579 /**
AnnaBridge 172:65be27845400 580 * @brief Flexible Memory Controller Bank5_6
AnnaBridge 172:65be27845400 581 */
AnnaBridge 172:65be27845400 582
AnnaBridge 172:65be27845400 583 typedef struct
AnnaBridge 172:65be27845400 584 {
AnnaBridge 172:65be27845400 585 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
AnnaBridge 172:65be27845400 586 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
AnnaBridge 172:65be27845400 587 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
AnnaBridge 172:65be27845400 588 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
AnnaBridge 172:65be27845400 589 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
AnnaBridge 172:65be27845400 590 } FMC_Bank5_6_TypeDef;
AnnaBridge 172:65be27845400 591
AnnaBridge 172:65be27845400 592 /**
AnnaBridge 172:65be27845400 593 * @brief General Purpose I/O
AnnaBridge 172:65be27845400 594 */
AnnaBridge 172:65be27845400 595
AnnaBridge 172:65be27845400 596 typedef struct
AnnaBridge 172:65be27845400 597 {
AnnaBridge 172:65be27845400 598 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 599 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 600 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 601 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 602 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 603 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 604 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 605 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 606 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 172:65be27845400 607 } GPIO_TypeDef;
AnnaBridge 172:65be27845400 608
AnnaBridge 172:65be27845400 609 /**
AnnaBridge 172:65be27845400 610 * @brief System configuration controller
AnnaBridge 172:65be27845400 611 */
AnnaBridge 172:65be27845400 612
AnnaBridge 172:65be27845400 613 typedef struct
AnnaBridge 172:65be27845400 614 {
AnnaBridge 172:65be27845400 615 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 616 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 617 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 172:65be27845400 618 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
AnnaBridge 172:65be27845400 619 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 620 } SYSCFG_TypeDef;
AnnaBridge 172:65be27845400 621
AnnaBridge 172:65be27845400 622 /**
AnnaBridge 172:65be27845400 623 * @brief Inter-integrated Circuit Interface
AnnaBridge 172:65be27845400 624 */
AnnaBridge 172:65be27845400 625
AnnaBridge 172:65be27845400 626 typedef struct
AnnaBridge 172:65be27845400 627 {
AnnaBridge 172:65be27845400 628 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 629 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 630 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
AnnaBridge 172:65be27845400 631 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
AnnaBridge 172:65be27845400 632 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 633 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
AnnaBridge 172:65be27845400 634 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
AnnaBridge 172:65be27845400 635 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 636 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 637 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 638 } I2C_TypeDef;
AnnaBridge 172:65be27845400 639
AnnaBridge 172:65be27845400 640 /**
AnnaBridge 172:65be27845400 641 * @brief Independent WATCHDOG
AnnaBridge 172:65be27845400 642 */
AnnaBridge 172:65be27845400 643
AnnaBridge 172:65be27845400 644 typedef struct
AnnaBridge 172:65be27845400 645 {
AnnaBridge 172:65be27845400 646 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 647 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 648 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 649 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 650 } IWDG_TypeDef;
AnnaBridge 172:65be27845400 651
AnnaBridge 172:65be27845400 652 /**
AnnaBridge 172:65be27845400 653 * @brief LCD-TFT Display Controller
AnnaBridge 172:65be27845400 654 */
AnnaBridge 172:65be27845400 655
AnnaBridge 172:65be27845400 656 typedef struct
AnnaBridge 172:65be27845400 657 {
AnnaBridge 172:65be27845400 658 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
AnnaBridge 172:65be27845400 659 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 660 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 661 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 662 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 663 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 664 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
AnnaBridge 172:65be27845400 665 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 666 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
AnnaBridge 172:65be27845400 667 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 668 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
AnnaBridge 172:65be27845400 669 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 670 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 671 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 672 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 673 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 674 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 675 } LTDC_TypeDef;
AnnaBridge 172:65be27845400 676
AnnaBridge 172:65be27845400 677 /**
AnnaBridge 172:65be27845400 678 * @brief LCD-TFT Display layer x Controller
AnnaBridge 172:65be27845400 679 */
AnnaBridge 172:65be27845400 680
AnnaBridge 172:65be27845400 681 typedef struct
AnnaBridge 172:65be27845400 682 {
AnnaBridge 172:65be27845400 683 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
AnnaBridge 172:65be27845400 684 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
AnnaBridge 172:65be27845400 685 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
AnnaBridge 172:65be27845400 686 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
AnnaBridge 172:65be27845400 687 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
AnnaBridge 172:65be27845400 688 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
AnnaBridge 172:65be27845400 689 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
AnnaBridge 172:65be27845400 690 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
AnnaBridge 172:65be27845400 691 uint32_t RESERVED0[2]; /*!< Reserved */
AnnaBridge 172:65be27845400 692 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
AnnaBridge 172:65be27845400 693 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
AnnaBridge 172:65be27845400 694 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
AnnaBridge 172:65be27845400 695 uint32_t RESERVED1[3]; /*!< Reserved */
AnnaBridge 172:65be27845400 696 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
AnnaBridge 172:65be27845400 697 } LTDC_Layer_TypeDef;
AnnaBridge 172:65be27845400 698
AnnaBridge 172:65be27845400 699 /**
AnnaBridge 172:65be27845400 700 * @brief Power Control
AnnaBridge 172:65be27845400 701 */
AnnaBridge 172:65be27845400 702
AnnaBridge 172:65be27845400 703 typedef struct
AnnaBridge 172:65be27845400 704 {
AnnaBridge 172:65be27845400 705 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 706 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 707 } PWR_TypeDef;
AnnaBridge 172:65be27845400 708
AnnaBridge 172:65be27845400 709 /**
AnnaBridge 172:65be27845400 710 * @brief Reset and Clock Control
AnnaBridge 172:65be27845400 711 */
AnnaBridge 172:65be27845400 712
AnnaBridge 172:65be27845400 713 typedef struct
AnnaBridge 172:65be27845400 714 {
AnnaBridge 172:65be27845400 715 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 716 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 717 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 718 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 719 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 720 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 721 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 722 uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 172:65be27845400 723 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 724 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 725 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
AnnaBridge 172:65be27845400 726 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 727 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 728 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 729 uint32_t RESERVED2; /*!< Reserved, 0x3C */
AnnaBridge 172:65be27845400 730 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 731 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 732 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
AnnaBridge 172:65be27845400 733 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
AnnaBridge 172:65be27845400 734 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
AnnaBridge 172:65be27845400 735 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
AnnaBridge 172:65be27845400 736 uint32_t RESERVED4; /*!< Reserved, 0x5C */
AnnaBridge 172:65be27845400 737 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
AnnaBridge 172:65be27845400 738 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
AnnaBridge 172:65be27845400 739 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
AnnaBridge 172:65be27845400 740 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
AnnaBridge 172:65be27845400 741 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 172:65be27845400 742 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
AnnaBridge 172:65be27845400 743 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
AnnaBridge 172:65be27845400 744 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
AnnaBridge 172:65be27845400 745 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
AnnaBridge 172:65be27845400 746 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
AnnaBridge 172:65be27845400 747 } RCC_TypeDef;
AnnaBridge 172:65be27845400 748
AnnaBridge 172:65be27845400 749 /**
AnnaBridge 172:65be27845400 750 * @brief Real-Time Clock
AnnaBridge 172:65be27845400 751 */
AnnaBridge 172:65be27845400 752
AnnaBridge 172:65be27845400 753 typedef struct
AnnaBridge 172:65be27845400 754 {
AnnaBridge 172:65be27845400 755 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 756 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 757 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 758 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 759 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 760 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 761 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 762 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 763 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 764 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 765 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 766 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 767 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 768 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 769 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 770 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 771 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 772 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 773 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 774 uint32_t RESERVED7; /*!< Reserved, 0x4C */
AnnaBridge 172:65be27845400 775 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
AnnaBridge 172:65be27845400 776 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 172:65be27845400 777 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 172:65be27845400 778 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 172:65be27845400 779 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 172:65be27845400 780 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 172:65be27845400 781 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 172:65be27845400 782 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 172:65be27845400 783 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 172:65be27845400 784 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 172:65be27845400 785 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 172:65be27845400 786 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 172:65be27845400 787 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 172:65be27845400 788 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 172:65be27845400 789 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 172:65be27845400 790 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 172:65be27845400 791 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 172:65be27845400 792 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 172:65be27845400 793 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 172:65be27845400 794 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 172:65be27845400 795 } RTC_TypeDef;
AnnaBridge 172:65be27845400 796
AnnaBridge 172:65be27845400 797 /**
AnnaBridge 172:65be27845400 798 * @brief Serial Audio Interface
AnnaBridge 172:65be27845400 799 */
AnnaBridge 172:65be27845400 800
AnnaBridge 172:65be27845400 801 typedef struct
AnnaBridge 172:65be27845400 802 {
AnnaBridge 172:65be27845400 803 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 804 } SAI_TypeDef;
AnnaBridge 172:65be27845400 805
AnnaBridge 172:65be27845400 806 typedef struct
AnnaBridge 172:65be27845400 807 {
AnnaBridge 172:65be27845400 808 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
AnnaBridge 172:65be27845400 809 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
AnnaBridge 172:65be27845400 810 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 811 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 812 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 813 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 814 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 815 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 816 } SAI_Block_TypeDef;
AnnaBridge 172:65be27845400 817
AnnaBridge 172:65be27845400 818 /**
AnnaBridge 172:65be27845400 819 * @brief SD host Interface
AnnaBridge 172:65be27845400 820 */
AnnaBridge 172:65be27845400 821
AnnaBridge 172:65be27845400 822 typedef struct
AnnaBridge 172:65be27845400 823 {
AnnaBridge 172:65be27845400 824 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 825 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 826 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 827 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 828 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 829 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 830 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 831 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 832 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 833 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 834 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 835 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 836 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 837 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 838 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 839 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 840 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 172:65be27845400 841 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 842 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 172:65be27845400 843 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
AnnaBridge 172:65be27845400 844 } SDIO_TypeDef;
AnnaBridge 172:65be27845400 845
AnnaBridge 172:65be27845400 846 /**
AnnaBridge 172:65be27845400 847 * @brief Serial Peripheral Interface
AnnaBridge 172:65be27845400 848 */
AnnaBridge 172:65be27845400 849
AnnaBridge 172:65be27845400 850 typedef struct
AnnaBridge 172:65be27845400 851 {
AnnaBridge 172:65be27845400 852 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 172:65be27845400 853 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 854 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 855 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 856 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 172:65be27845400 857 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 172:65be27845400 858 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 172:65be27845400 859 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 860 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 861 } SPI_TypeDef;
AnnaBridge 172:65be27845400 862
AnnaBridge 172:65be27845400 863
AnnaBridge 172:65be27845400 864 /**
AnnaBridge 172:65be27845400 865 * @brief TIM
AnnaBridge 172:65be27845400 866 */
AnnaBridge 172:65be27845400 867
AnnaBridge 172:65be27845400 868 typedef struct
AnnaBridge 172:65be27845400 869 {
AnnaBridge 172:65be27845400 870 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 871 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 872 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 873 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 874 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 875 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 876 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 172:65be27845400 877 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 172:65be27845400 878 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 879 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 880 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 172:65be27845400 881 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 882 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 883 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 172:65be27845400 884 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 172:65be27845400 885 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 172:65be27845400 886 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 172:65be27845400 887 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 888 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 889 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 172:65be27845400 890 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 172:65be27845400 891 } TIM_TypeDef;
AnnaBridge 172:65be27845400 892
AnnaBridge 172:65be27845400 893 /**
AnnaBridge 172:65be27845400 894 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 172:65be27845400 895 */
AnnaBridge 172:65be27845400 896
AnnaBridge 172:65be27845400 897 typedef struct
AnnaBridge 172:65be27845400 898 {
AnnaBridge 172:65be27845400 899 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 900 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 901 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 902 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
AnnaBridge 172:65be27845400 903 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
AnnaBridge 172:65be27845400 904 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
AnnaBridge 172:65be27845400 905 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 906 } USART_TypeDef;
AnnaBridge 172:65be27845400 907
AnnaBridge 172:65be27845400 908 /**
AnnaBridge 172:65be27845400 909 * @brief Window WATCHDOG
AnnaBridge 172:65be27845400 910 */
AnnaBridge 172:65be27845400 911
AnnaBridge 172:65be27845400 912 typedef struct
AnnaBridge 172:65be27845400 913 {
AnnaBridge 172:65be27845400 914 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 915 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 916 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 917 } WWDG_TypeDef;
AnnaBridge 172:65be27845400 918
AnnaBridge 172:65be27845400 919 /**
AnnaBridge 172:65be27845400 920 * @brief Crypto Processor
AnnaBridge 172:65be27845400 921 */
AnnaBridge 172:65be27845400 922
AnnaBridge 172:65be27845400 923 typedef struct
AnnaBridge 172:65be27845400 924 {
AnnaBridge 172:65be27845400 925 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 926 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 927 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 928 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 929 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 930 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 931 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 932 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 933 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
AnnaBridge 172:65be27845400 934 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
AnnaBridge 172:65be27845400 935 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
AnnaBridge 172:65be27845400 936 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
AnnaBridge 172:65be27845400 937 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
AnnaBridge 172:65be27845400 938 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
AnnaBridge 172:65be27845400 939 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
AnnaBridge 172:65be27845400 940 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
AnnaBridge 172:65be27845400 941 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
AnnaBridge 172:65be27845400 942 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
AnnaBridge 172:65be27845400 943 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
AnnaBridge 172:65be27845400 944 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
AnnaBridge 172:65be27845400 945 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
AnnaBridge 172:65be27845400 946 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
AnnaBridge 172:65be27845400 947 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
AnnaBridge 172:65be27845400 948 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
AnnaBridge 172:65be27845400 949 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
AnnaBridge 172:65be27845400 950 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
AnnaBridge 172:65be27845400 951 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
AnnaBridge 172:65be27845400 952 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
AnnaBridge 172:65be27845400 953 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
AnnaBridge 172:65be27845400 954 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
AnnaBridge 172:65be27845400 955 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
AnnaBridge 172:65be27845400 956 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
AnnaBridge 172:65be27845400 957 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
AnnaBridge 172:65be27845400 958 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
AnnaBridge 172:65be27845400 959 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
AnnaBridge 172:65be27845400 960 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
AnnaBridge 172:65be27845400 961 } CRYP_TypeDef;
AnnaBridge 172:65be27845400 962
AnnaBridge 172:65be27845400 963 /**
AnnaBridge 172:65be27845400 964 * @brief HASH
AnnaBridge 172:65be27845400 965 */
AnnaBridge 172:65be27845400 966
AnnaBridge 172:65be27845400 967 typedef struct
AnnaBridge 172:65be27845400 968 {
AnnaBridge 172:65be27845400 969 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 970 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 971 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 972 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
AnnaBridge 172:65be27845400 973 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 974 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 975 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
AnnaBridge 172:65be27845400 976 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
AnnaBridge 172:65be27845400 977 } HASH_TypeDef;
AnnaBridge 172:65be27845400 978
AnnaBridge 172:65be27845400 979 /**
AnnaBridge 172:65be27845400 980 * @brief HASH_DIGEST
AnnaBridge 172:65be27845400 981 */
AnnaBridge 172:65be27845400 982
AnnaBridge 172:65be27845400 983 typedef struct
AnnaBridge 172:65be27845400 984 {
AnnaBridge 172:65be27845400 985 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
AnnaBridge 172:65be27845400 986 } HASH_DIGEST_TypeDef;
AnnaBridge 172:65be27845400 987
AnnaBridge 172:65be27845400 988 /**
AnnaBridge 172:65be27845400 989 * @brief RNG
AnnaBridge 172:65be27845400 990 */
AnnaBridge 172:65be27845400 991
AnnaBridge 172:65be27845400 992 typedef struct
AnnaBridge 172:65be27845400 993 {
AnnaBridge 172:65be27845400 994 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 995 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 996 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 997 } RNG_TypeDef;
AnnaBridge 172:65be27845400 998
AnnaBridge 172:65be27845400 999 /**
AnnaBridge 172:65be27845400 1000 * @brief USB_OTG_Core_Registers
AnnaBridge 172:65be27845400 1001 */
AnnaBridge 172:65be27845400 1002 typedef struct
AnnaBridge 172:65be27845400 1003 {
AnnaBridge 172:65be27845400 1004 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 172:65be27845400 1005 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 172:65be27845400 1006 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 172:65be27845400 1007 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 172:65be27845400 1008 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 172:65be27845400 1009 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 172:65be27845400 1010 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 172:65be27845400 1011 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 172:65be27845400 1012 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 172:65be27845400 1013 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 172:65be27845400 1014 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 172:65be27845400 1015 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 172:65be27845400 1016 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 172:65be27845400 1017 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 172:65be27845400 1018 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 172:65be27845400 1019 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
AnnaBridge 172:65be27845400 1020 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 172:65be27845400 1021 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 172:65be27845400 1022 } USB_OTG_GlobalTypeDef;
AnnaBridge 172:65be27845400 1023
AnnaBridge 172:65be27845400 1024 /**
AnnaBridge 172:65be27845400 1025 * @brief USB_OTG_device_Registers
AnnaBridge 172:65be27845400 1026 */
AnnaBridge 172:65be27845400 1027 typedef struct
AnnaBridge 172:65be27845400 1028 {
AnnaBridge 172:65be27845400 1029 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 172:65be27845400 1030 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 172:65be27845400 1031 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 172:65be27845400 1032 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 172:65be27845400 1033 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 172:65be27845400 1034 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 172:65be27845400 1035 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 172:65be27845400 1036 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 172:65be27845400 1037 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 172:65be27845400 1038 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 172:65be27845400 1039 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 172:65be27845400 1040 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 172:65be27845400 1041 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 172:65be27845400 1042 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 172:65be27845400 1043 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 172:65be27845400 1044 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 172:65be27845400 1045 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 172:65be27845400 1046 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 172:65be27845400 1047 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 172:65be27845400 1048 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 172:65be27845400 1049 } USB_OTG_DeviceTypeDef;
AnnaBridge 172:65be27845400 1050
AnnaBridge 172:65be27845400 1051 /**
AnnaBridge 172:65be27845400 1052 * @brief USB_OTG_IN_Endpoint-Specific_Register
AnnaBridge 172:65be27845400 1053 */
AnnaBridge 172:65be27845400 1054 typedef struct
AnnaBridge 172:65be27845400 1055 {
AnnaBridge 172:65be27845400 1056 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 172:65be27845400 1057 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 172:65be27845400 1058 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 172:65be27845400 1059 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 172:65be27845400 1060 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 172:65be27845400 1061 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 172:65be27845400 1062 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 172:65be27845400 1063 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 172:65be27845400 1064 } USB_OTG_INEndpointTypeDef;
AnnaBridge 172:65be27845400 1065
AnnaBridge 172:65be27845400 1066 /**
AnnaBridge 172:65be27845400 1067 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
AnnaBridge 172:65be27845400 1068 */
AnnaBridge 172:65be27845400 1069 typedef struct
AnnaBridge 172:65be27845400 1070 {
AnnaBridge 172:65be27845400 1071 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 172:65be27845400 1072 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 172:65be27845400 1073 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 172:65be27845400 1074 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 172:65be27845400 1075 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 172:65be27845400 1076 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 172:65be27845400 1077 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 172:65be27845400 1078 } USB_OTG_OUTEndpointTypeDef;
AnnaBridge 172:65be27845400 1079
AnnaBridge 172:65be27845400 1080 /**
AnnaBridge 172:65be27845400 1081 * @brief USB_OTG_Host_Mode_Register_Structures
AnnaBridge 172:65be27845400 1082 */
AnnaBridge 172:65be27845400 1083 typedef struct
AnnaBridge 172:65be27845400 1084 {
AnnaBridge 172:65be27845400 1085 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 172:65be27845400 1086 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 172:65be27845400 1087 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 172:65be27845400 1088 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 172:65be27845400 1089 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 172:65be27845400 1090 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 172:65be27845400 1091 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 172:65be27845400 1092 } USB_OTG_HostTypeDef;
AnnaBridge 172:65be27845400 1093
AnnaBridge 172:65be27845400 1094 /**
AnnaBridge 172:65be27845400 1095 * @brief USB_OTG_Host_Channel_Specific_Registers
AnnaBridge 172:65be27845400 1096 */
AnnaBridge 172:65be27845400 1097 typedef struct
AnnaBridge 172:65be27845400 1098 {
AnnaBridge 172:65be27845400 1099 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 172:65be27845400 1100 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 172:65be27845400 1101 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 172:65be27845400 1102 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 172:65be27845400 1103 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 172:65be27845400 1104 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 172:65be27845400 1105 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 172:65be27845400 1106 } USB_OTG_HostChannelTypeDef;
AnnaBridge 172:65be27845400 1107
AnnaBridge 172:65be27845400 1108 /**
AnnaBridge 172:65be27845400 1109 * @}
AnnaBridge 172:65be27845400 1110 */
AnnaBridge 172:65be27845400 1111
AnnaBridge 172:65be27845400 1112 /** @addtogroup Peripheral_memory_map
AnnaBridge 172:65be27845400 1113 * @{
AnnaBridge 172:65be27845400 1114 */
AnnaBridge 172:65be27845400 1115 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
AnnaBridge 172:65be27845400 1116 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
AnnaBridge 172:65be27845400 1117 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
AnnaBridge 172:65be27845400 1118 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
AnnaBridge 172:65be27845400 1119 #define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
AnnaBridge 172:65be27845400 1120 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
AnnaBridge 172:65be27845400 1121 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
AnnaBridge 172:65be27845400 1122 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
AnnaBridge 172:65be27845400 1123 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
AnnaBridge 172:65be27845400 1124 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
AnnaBridge 172:65be27845400 1125 #define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
AnnaBridge 172:65be27845400 1126 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
AnnaBridge 172:65be27845400 1127 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
AnnaBridge 172:65be27845400 1128 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
AnnaBridge 172:65be27845400 1129 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 172:65be27845400 1130 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 172:65be27845400 1131 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
AnnaBridge 172:65be27845400 1132
AnnaBridge 172:65be27845400 1133 /* Legacy defines */
AnnaBridge 172:65be27845400 1134 #define SRAM_BASE SRAM1_BASE
AnnaBridge 172:65be27845400 1135 #define SRAM_BB_BASE SRAM1_BB_BASE
AnnaBridge 172:65be27845400 1136
AnnaBridge 172:65be27845400 1137 /*!< Peripheral memory map */
AnnaBridge 172:65be27845400 1138 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 172:65be27845400 1139 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 172:65be27845400 1140 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 172:65be27845400 1141 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
AnnaBridge 172:65be27845400 1142
AnnaBridge 172:65be27845400 1143 /*!< APB1 peripherals */
AnnaBridge 172:65be27845400 1144 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
AnnaBridge 172:65be27845400 1145 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
AnnaBridge 172:65be27845400 1146 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
AnnaBridge 172:65be27845400 1147 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
AnnaBridge 172:65be27845400 1148 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
AnnaBridge 172:65be27845400 1149 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
AnnaBridge 172:65be27845400 1150 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
AnnaBridge 172:65be27845400 1151 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
AnnaBridge 172:65be27845400 1152 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
AnnaBridge 172:65be27845400 1153 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
AnnaBridge 172:65be27845400 1154 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
AnnaBridge 172:65be27845400 1155 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
AnnaBridge 172:65be27845400 1156 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
AnnaBridge 172:65be27845400 1157 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
AnnaBridge 172:65be27845400 1158 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
AnnaBridge 172:65be27845400 1159 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
AnnaBridge 172:65be27845400 1160 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
AnnaBridge 172:65be27845400 1161 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
AnnaBridge 172:65be27845400 1162 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
AnnaBridge 172:65be27845400 1163 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
AnnaBridge 172:65be27845400 1164 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
AnnaBridge 172:65be27845400 1165 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
AnnaBridge 172:65be27845400 1166 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
AnnaBridge 172:65be27845400 1167 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
AnnaBridge 172:65be27845400 1168 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
AnnaBridge 172:65be27845400 1169 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
AnnaBridge 172:65be27845400 1170 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
AnnaBridge 172:65be27845400 1171 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
AnnaBridge 172:65be27845400 1172 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
AnnaBridge 172:65be27845400 1173
AnnaBridge 172:65be27845400 1174 /*!< APB2 peripherals */
AnnaBridge 172:65be27845400 1175 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
AnnaBridge 172:65be27845400 1176 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
AnnaBridge 172:65be27845400 1177 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
AnnaBridge 172:65be27845400 1178 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
AnnaBridge 172:65be27845400 1179 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
AnnaBridge 172:65be27845400 1180 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
AnnaBridge 172:65be27845400 1181 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
AnnaBridge 172:65be27845400 1182 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 172:65be27845400 1183 /* Legacy define */
AnnaBridge 172:65be27845400 1184 #define ADC_BASE ADC123_COMMON_BASE
AnnaBridge 172:65be27845400 1185 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
AnnaBridge 172:65be27845400 1186 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
AnnaBridge 172:65be27845400 1187 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
AnnaBridge 172:65be27845400 1188 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
AnnaBridge 172:65be27845400 1189 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
AnnaBridge 172:65be27845400 1190 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
AnnaBridge 172:65be27845400 1191 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
AnnaBridge 172:65be27845400 1192 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
AnnaBridge 172:65be27845400 1193 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
AnnaBridge 172:65be27845400 1194 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
AnnaBridge 172:65be27845400 1195 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
AnnaBridge 172:65be27845400 1196 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
AnnaBridge 172:65be27845400 1197 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
AnnaBridge 172:65be27845400 1198 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
AnnaBridge 172:65be27845400 1199 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
AnnaBridge 172:65be27845400 1200 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
AnnaBridge 172:65be27845400 1201
AnnaBridge 172:65be27845400 1202 /*!< AHB1 peripherals */
AnnaBridge 172:65be27845400 1203 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
AnnaBridge 172:65be27845400 1204 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
AnnaBridge 172:65be27845400 1205 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
AnnaBridge 172:65be27845400 1206 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
AnnaBridge 172:65be27845400 1207 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
AnnaBridge 172:65be27845400 1208 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
AnnaBridge 172:65be27845400 1209 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
AnnaBridge 172:65be27845400 1210 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
AnnaBridge 172:65be27845400 1211 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
AnnaBridge 172:65be27845400 1212 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
AnnaBridge 172:65be27845400 1213 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
AnnaBridge 172:65be27845400 1214 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
AnnaBridge 172:65be27845400 1215 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
AnnaBridge 172:65be27845400 1216 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
AnnaBridge 172:65be27845400 1217 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
AnnaBridge 172:65be27845400 1218 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
AnnaBridge 172:65be27845400 1219 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
AnnaBridge 172:65be27845400 1220 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
AnnaBridge 172:65be27845400 1221 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
AnnaBridge 172:65be27845400 1222 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
AnnaBridge 172:65be27845400 1223 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
AnnaBridge 172:65be27845400 1224 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
AnnaBridge 172:65be27845400 1225 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
AnnaBridge 172:65be27845400 1226 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
AnnaBridge 172:65be27845400 1227 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
AnnaBridge 172:65be27845400 1228 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
AnnaBridge 172:65be27845400 1229 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
AnnaBridge 172:65be27845400 1230 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
AnnaBridge 172:65be27845400 1231 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
AnnaBridge 172:65be27845400 1232 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
AnnaBridge 172:65be27845400 1233 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
AnnaBridge 172:65be27845400 1234 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
AnnaBridge 172:65be27845400 1235 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
AnnaBridge 172:65be27845400 1236 #define ETH_MAC_BASE (ETH_BASE)
AnnaBridge 172:65be27845400 1237 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
AnnaBridge 172:65be27845400 1238 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
AnnaBridge 172:65be27845400 1239 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
AnnaBridge 172:65be27845400 1240 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
AnnaBridge 172:65be27845400 1241
AnnaBridge 172:65be27845400 1242 /*!< AHB2 peripherals */
AnnaBridge 172:65be27845400 1243 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
AnnaBridge 172:65be27845400 1244 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
AnnaBridge 172:65be27845400 1245 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
AnnaBridge 172:65be27845400 1246 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
AnnaBridge 172:65be27845400 1247 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
AnnaBridge 172:65be27845400 1248
AnnaBridge 172:65be27845400 1249 /*!< FMC Bankx registers base address */
AnnaBridge 172:65be27845400 1250 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
AnnaBridge 172:65be27845400 1251 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
AnnaBridge 172:65be27845400 1252 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
AnnaBridge 172:65be27845400 1253 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
AnnaBridge 172:65be27845400 1254 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
AnnaBridge 172:65be27845400 1255
AnnaBridge 172:65be27845400 1256
AnnaBridge 172:65be27845400 1257 /*!< Debug MCU registers base address */
AnnaBridge 172:65be27845400 1258 #define DBGMCU_BASE 0xE0042000U
AnnaBridge 172:65be27845400 1259 /*!< USB registers base address */
AnnaBridge 172:65be27845400 1260 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
AnnaBridge 172:65be27845400 1261 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
AnnaBridge 172:65be27845400 1262
AnnaBridge 172:65be27845400 1263 #define USB_OTG_GLOBAL_BASE 0x000U
AnnaBridge 172:65be27845400 1264 #define USB_OTG_DEVICE_BASE 0x800U
AnnaBridge 172:65be27845400 1265 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
AnnaBridge 172:65be27845400 1266 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
AnnaBridge 172:65be27845400 1267 #define USB_OTG_EP_REG_SIZE 0x20U
AnnaBridge 172:65be27845400 1268 #define USB_OTG_HOST_BASE 0x400U
AnnaBridge 172:65be27845400 1269 #define USB_OTG_HOST_PORT_BASE 0x440U
AnnaBridge 172:65be27845400 1270 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
AnnaBridge 172:65be27845400 1271 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
AnnaBridge 172:65be27845400 1272 #define USB_OTG_PCGCCTL_BASE 0xE00U
AnnaBridge 172:65be27845400 1273 #define USB_OTG_FIFO_BASE 0x1000U
AnnaBridge 172:65be27845400 1274 #define USB_OTG_FIFO_SIZE 0x1000U
AnnaBridge 172:65be27845400 1275
AnnaBridge 172:65be27845400 1276 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
AnnaBridge 172:65be27845400 1277 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
AnnaBridge 172:65be27845400 1278 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
AnnaBridge 172:65be27845400 1279 /**
AnnaBridge 172:65be27845400 1280 * @}
AnnaBridge 172:65be27845400 1281 */
AnnaBridge 172:65be27845400 1282
AnnaBridge 172:65be27845400 1283 /** @addtogroup Peripheral_declaration
AnnaBridge 172:65be27845400 1284 * @{
AnnaBridge 172:65be27845400 1285 */
AnnaBridge 172:65be27845400 1286 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 172:65be27845400 1287 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 172:65be27845400 1288 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 172:65be27845400 1289 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 172:65be27845400 1290 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 172:65be27845400 1291 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 172:65be27845400 1292 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
AnnaBridge 172:65be27845400 1293 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
AnnaBridge 172:65be27845400 1294 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
AnnaBridge 172:65be27845400 1295 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 172:65be27845400 1296 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 172:65be27845400 1297 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 172:65be27845400 1298 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
AnnaBridge 172:65be27845400 1299 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 172:65be27845400 1300 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 172:65be27845400 1301 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
AnnaBridge 172:65be27845400 1302 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 172:65be27845400 1303 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 172:65be27845400 1304 #define UART4 ((USART_TypeDef *) UART4_BASE)
AnnaBridge 172:65be27845400 1305 #define UART5 ((USART_TypeDef *) UART5_BASE)
AnnaBridge 172:65be27845400 1306 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 172:65be27845400 1307 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 172:65be27845400 1308 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 172:65be27845400 1309 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
AnnaBridge 172:65be27845400 1310 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
AnnaBridge 172:65be27845400 1311 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 172:65be27845400 1312 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 172:65be27845400 1313 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
AnnaBridge 172:65be27845400 1314 #define UART7 ((USART_TypeDef *) UART7_BASE)
AnnaBridge 172:65be27845400 1315 #define UART8 ((USART_TypeDef *) UART8_BASE)
AnnaBridge 172:65be27845400 1316 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 172:65be27845400 1317 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
AnnaBridge 172:65be27845400 1318 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 172:65be27845400 1319 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 172:65be27845400 1320 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 172:65be27845400 1321 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
AnnaBridge 172:65be27845400 1322 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
AnnaBridge 172:65be27845400 1323 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
AnnaBridge 172:65be27845400 1324 /* Legacy define */
AnnaBridge 172:65be27845400 1325 #define ADC ADC123_COMMON
AnnaBridge 172:65be27845400 1326 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
AnnaBridge 172:65be27845400 1327 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 172:65be27845400 1328 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
AnnaBridge 172:65be27845400 1329 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 172:65be27845400 1330 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 172:65be27845400 1331 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 172:65be27845400 1332 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
AnnaBridge 172:65be27845400 1333 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 172:65be27845400 1334 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
AnnaBridge 172:65be27845400 1335 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
AnnaBridge 172:65be27845400 1336 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
AnnaBridge 172:65be27845400 1337 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
AnnaBridge 172:65be27845400 1338 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
AnnaBridge 172:65be27845400 1339 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
AnnaBridge 172:65be27845400 1340 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
AnnaBridge 172:65be27845400 1341 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
AnnaBridge 172:65be27845400 1342 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 172:65be27845400 1343 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 172:65be27845400 1344 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 172:65be27845400 1345 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 172:65be27845400 1346 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 172:65be27845400 1347 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 172:65be27845400 1348 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
AnnaBridge 172:65be27845400 1349 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 172:65be27845400 1350 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
AnnaBridge 172:65be27845400 1351 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
AnnaBridge 172:65be27845400 1352 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
AnnaBridge 172:65be27845400 1353 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 172:65be27845400 1354 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 172:65be27845400 1355 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 172:65be27845400 1356 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 172:65be27845400 1357 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 172:65be27845400 1358 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 172:65be27845400 1359 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 172:65be27845400 1360 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 172:65be27845400 1361 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 172:65be27845400 1362 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 172:65be27845400 1363 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 172:65be27845400 1364 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 172:65be27845400 1365 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 172:65be27845400 1366 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 172:65be27845400 1367 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 172:65be27845400 1368 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 172:65be27845400 1369 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 172:65be27845400 1370 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 172:65be27845400 1371 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 172:65be27845400 1372 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 172:65be27845400 1373 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 172:65be27845400 1374 #define ETH ((ETH_TypeDef *) ETH_BASE)
AnnaBridge 172:65be27845400 1375 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
AnnaBridge 172:65be27845400 1376 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
AnnaBridge 172:65be27845400 1377 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
AnnaBridge 172:65be27845400 1378 #define HASH ((HASH_TypeDef *) HASH_BASE)
AnnaBridge 172:65be27845400 1379 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
AnnaBridge 172:65be27845400 1380 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 172:65be27845400 1381 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
AnnaBridge 172:65be27845400 1382 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
AnnaBridge 172:65be27845400 1383 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
AnnaBridge 172:65be27845400 1384 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
AnnaBridge 172:65be27845400 1385 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
AnnaBridge 172:65be27845400 1386 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 172:65be27845400 1387 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
AnnaBridge 172:65be27845400 1388 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
AnnaBridge 172:65be27845400 1389
AnnaBridge 172:65be27845400 1390 /**
AnnaBridge 172:65be27845400 1391 * @}
AnnaBridge 172:65be27845400 1392 */
AnnaBridge 172:65be27845400 1393
AnnaBridge 172:65be27845400 1394 /** @addtogroup Exported_constants
AnnaBridge 172:65be27845400 1395 * @{
AnnaBridge 172:65be27845400 1396 */
AnnaBridge 172:65be27845400 1397
AnnaBridge 172:65be27845400 1398 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 172:65be27845400 1399 * @{
AnnaBridge 172:65be27845400 1400 */
AnnaBridge 172:65be27845400 1401
AnnaBridge 172:65be27845400 1402 /******************************************************************************/
AnnaBridge 172:65be27845400 1403 /* Peripheral Registers_Bits_Definition */
AnnaBridge 172:65be27845400 1404 /******************************************************************************/
AnnaBridge 172:65be27845400 1405
AnnaBridge 172:65be27845400 1406 /******************************************************************************/
AnnaBridge 172:65be27845400 1407 /* */
AnnaBridge 172:65be27845400 1408 /* Analog to Digital Converter */
AnnaBridge 172:65be27845400 1409 /* */
AnnaBridge 172:65be27845400 1410 /******************************************************************************/
AnnaBridge 172:65be27845400 1411 /*
AnnaBridge 172:65be27845400 1412 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 172:65be27845400 1413 */
AnnaBridge 172:65be27845400 1414 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
AnnaBridge 172:65be27845400 1415
AnnaBridge 172:65be27845400 1416 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 172:65be27845400 1417 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 172:65be27845400 1418 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1419 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 172:65be27845400 1420 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 172:65be27845400 1421 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1422 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 172:65be27845400 1423 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 172:65be27845400 1424 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1425 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 172:65be27845400 1426 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 172:65be27845400 1427 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1428 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 172:65be27845400 1429 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 172:65be27845400 1430 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1431 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 172:65be27845400 1432 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 172:65be27845400 1433 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1434 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 172:65be27845400 1435
AnnaBridge 172:65be27845400 1436 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 172:65be27845400 1437 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 172:65be27845400 1438 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 1439 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 172:65be27845400 1440 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1441 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1442 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1443 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1444 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1445 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 172:65be27845400 1446 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1447 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 172:65be27845400 1448 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 172:65be27845400 1449 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 1450 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 172:65be27845400 1451 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 172:65be27845400 1452 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 1453 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 172:65be27845400 1454 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 172:65be27845400 1455 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1456 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 172:65be27845400 1457 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 172:65be27845400 1458 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1459 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 172:65be27845400 1460 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 172:65be27845400 1461 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1462 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 172:65be27845400 1463 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 172:65be27845400 1464 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1465 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 172:65be27845400 1466 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 172:65be27845400 1467 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1468 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 172:65be27845400 1469 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 172:65be27845400 1470 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 1471 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 172:65be27845400 1472 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1473 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1474 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1475 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 172:65be27845400 1476 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1477 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 172:65be27845400 1478 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 172:65be27845400 1479 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 1480 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 172:65be27845400 1481 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 172:65be27845400 1482 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 1483 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 172:65be27845400 1484 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 1485 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 1486 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 172:65be27845400 1487 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 1488 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
AnnaBridge 172:65be27845400 1489
AnnaBridge 172:65be27845400 1490 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 172:65be27845400 1491 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 172:65be27845400 1492 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1493 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 172:65be27845400 1494 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 172:65be27845400 1495 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1496 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 172:65be27845400 1497 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 172:65be27845400 1498 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1499 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 172:65be27845400 1500 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 172:65be27845400 1501 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1502 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 172:65be27845400 1503 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 172:65be27845400 1504 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1505 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 172:65be27845400 1506 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 172:65be27845400 1507 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1508 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 172:65be27845400 1509 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 172:65be27845400 1510 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 1511 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 172:65be27845400 1512 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1513 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1514 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1515 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1516 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 172:65be27845400 1517 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 1518 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 172:65be27845400 1519 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1520 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1521 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 172:65be27845400 1522 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1523 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 172:65be27845400 1524 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 172:65be27845400 1525 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 1526 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 172:65be27845400 1527 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 1528 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 1529 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 1530 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 1531 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 172:65be27845400 1532 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 1533 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 172:65be27845400 1534 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 1535 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 1536 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 172:65be27845400 1537 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 1538 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
AnnaBridge 172:65be27845400 1539
AnnaBridge 172:65be27845400 1540 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 172:65be27845400 1541 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 172:65be27845400 1542 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 1543 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 172:65be27845400 1544 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1545 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1546 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1547 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 172:65be27845400 1548 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 1549 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 172:65be27845400 1550 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1551 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1552 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1553 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 172:65be27845400 1554 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 172:65be27845400 1555 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 172:65be27845400 1556 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 1557 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 1558 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1559 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 172:65be27845400 1560 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 172:65be27845400 1561 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 172:65be27845400 1562 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1563 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1564 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1565 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 172:65be27845400 1566 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 1567 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 172:65be27845400 1568 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1569 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1570 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1571 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 172:65be27845400 1572 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 172:65be27845400 1573 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 172:65be27845400 1574 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1575 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1576 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1577 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 172:65be27845400 1578 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 172:65be27845400 1579 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 172:65be27845400 1580 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1581 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1582 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1583 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 172:65be27845400 1584 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 172:65be27845400 1585 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 172:65be27845400 1586 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1587 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1588 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 1589 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 172:65be27845400 1590 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 1591 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 172:65be27845400 1592 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 1593 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 1594 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 1595
AnnaBridge 172:65be27845400 1596 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 172:65be27845400 1597 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 172:65be27845400 1598 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 1599 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 172:65be27845400 1600 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1601 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1602 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1603 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 172:65be27845400 1604 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 1605 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 172:65be27845400 1606 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1607 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1608 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1609 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 172:65be27845400 1610 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 172:65be27845400 1611 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 172:65be27845400 1612 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 1613 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 1614 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1615 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 172:65be27845400 1616 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 172:65be27845400 1617 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 172:65be27845400 1618 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1619 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1620 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1621 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 172:65be27845400 1622 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 1623 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 172:65be27845400 1624 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1625 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1626 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1627 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 172:65be27845400 1628 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 172:65be27845400 1629 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 172:65be27845400 1630 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1631 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1632 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1633 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 172:65be27845400 1634 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 172:65be27845400 1635 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 172:65be27845400 1636 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1637 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1638 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1639 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 172:65be27845400 1640 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 172:65be27845400 1641 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 172:65be27845400 1642 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1643 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1644 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 1645 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 172:65be27845400 1646 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 1647 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 172:65be27845400 1648 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 1649 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 1650 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 1651 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 172:65be27845400 1652 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 172:65be27845400 1653 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 172:65be27845400 1654 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 1655 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 1656 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 1657
AnnaBridge 172:65be27845400 1658 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 172:65be27845400 1659 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 172:65be27845400 1660 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 1661 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
AnnaBridge 172:65be27845400 1662
AnnaBridge 172:65be27845400 1663 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 172:65be27845400 1664 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 172:65be27845400 1665 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 1666 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
AnnaBridge 172:65be27845400 1667
AnnaBridge 172:65be27845400 1668 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 172:65be27845400 1669 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 172:65be27845400 1670 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 1671 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
AnnaBridge 172:65be27845400 1672
AnnaBridge 172:65be27845400 1673 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 172:65be27845400 1674 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 172:65be27845400 1675 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 1676 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
AnnaBridge 172:65be27845400 1677
AnnaBridge 172:65be27845400 1678 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 172:65be27845400 1679 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 172:65be27845400 1680 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 1681 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
AnnaBridge 172:65be27845400 1682
AnnaBridge 172:65be27845400 1683 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 172:65be27845400 1684 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 172:65be27845400 1685 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 1686 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
AnnaBridge 172:65be27845400 1687
AnnaBridge 172:65be27845400 1688 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 172:65be27845400 1689 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 172:65be27845400 1690 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 1691 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1692 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1693 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1694 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1695 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1696 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1697 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 172:65be27845400 1698 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 172:65be27845400 1699 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1700 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1701 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 1702 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 1703 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1704 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1705 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 172:65be27845400 1706 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 172:65be27845400 1707 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1708 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1709 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1710 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1711 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1712 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1713 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 172:65be27845400 1714 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 172:65be27845400 1715 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1716 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1717 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1718 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1719 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1720 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1721 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 172:65be27845400 1722 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 1723 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 172:65be27845400 1724 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1725 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1726 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1727 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 1728
AnnaBridge 172:65be27845400 1729 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 172:65be27845400 1730 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 172:65be27845400 1731 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 1732 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1733 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1734 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1735 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1736 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1737 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1738 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 172:65be27845400 1739 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 172:65be27845400 1740 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1741 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1742 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 1743 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 1744 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1745 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1746 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 172:65be27845400 1747 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 172:65be27845400 1748 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1749 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1750 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1751 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1752 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1753 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1754 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 172:65be27845400 1755 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 172:65be27845400 1756 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1757 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1758 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1759 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1760 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1761 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1762 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 172:65be27845400 1763 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 172:65be27845400 1764 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1765 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1766 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1767 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1768 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 1769 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 1770 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 172:65be27845400 1771 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 172:65be27845400 1772 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1773 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 1774 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 1775 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 1776 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 1777 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 1778
AnnaBridge 172:65be27845400 1779 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 172:65be27845400 1780 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 172:65be27845400 1781 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 1782 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 172:65be27845400 1783 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1784 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1785 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1786 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1787 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1788 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 172:65be27845400 1789 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 172:65be27845400 1790 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 172:65be27845400 1791 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1792 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 1793 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 1794 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1795 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1796 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 172:65be27845400 1797 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 172:65be27845400 1798 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 172:65be27845400 1799 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1800 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1801 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1802 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1803 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1804 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 172:65be27845400 1805 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 172:65be27845400 1806 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1807 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1808 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1809 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1810 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1811 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1812 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 172:65be27845400 1813 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 172:65be27845400 1814 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1815 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1816 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1817 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1818 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 1819 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 1820 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 172:65be27845400 1821 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 172:65be27845400 1822 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 172:65be27845400 1823 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 1824 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 1825 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 1826 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 1827 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 1828
AnnaBridge 172:65be27845400 1829 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 172:65be27845400 1830 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 172:65be27845400 1831 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 1832 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 172:65be27845400 1833 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1834 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1835 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1836 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1837 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1838 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 172:65be27845400 1839 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 172:65be27845400 1840 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 172:65be27845400 1841 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1842 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 1843 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 1844 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1845 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1846 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 172:65be27845400 1847 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 172:65be27845400 1848 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 172:65be27845400 1849 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1850 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1851 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1852 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1853 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1854 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 172:65be27845400 1855 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 172:65be27845400 1856 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 172:65be27845400 1857 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1858 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1859 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1860 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1861 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1862 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 172:65be27845400 1863 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 1864 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 172:65be27845400 1865 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1866 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1867
AnnaBridge 172:65be27845400 1868 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 172:65be27845400 1869 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 1870 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 1871 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
AnnaBridge 172:65be27845400 1872
AnnaBridge 172:65be27845400 1873 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 172:65be27845400 1874 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 1875 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 1876 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
AnnaBridge 172:65be27845400 1877
AnnaBridge 172:65be27845400 1878 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 172:65be27845400 1879 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 1880 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 1881 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
AnnaBridge 172:65be27845400 1882
AnnaBridge 172:65be27845400 1883 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 172:65be27845400 1884 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 1885 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 1886 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
AnnaBridge 172:65be27845400 1887
AnnaBridge 172:65be27845400 1888 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 172:65be27845400 1889 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 172:65be27845400 1890 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 1891 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 172:65be27845400 1892 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 172:65be27845400 1893 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 1894 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
AnnaBridge 172:65be27845400 1895
AnnaBridge 172:65be27845400 1896 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 172:65be27845400 1897 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 172:65be27845400 1898 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1899 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 172:65be27845400 1900 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 172:65be27845400 1901 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1902 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 172:65be27845400 1903 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 172:65be27845400 1904 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1905 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 172:65be27845400 1906 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 172:65be27845400 1907 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1908 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 172:65be27845400 1909 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 172:65be27845400 1910 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1911 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 172:65be27845400 1912 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 172:65be27845400 1913 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 1914 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
AnnaBridge 172:65be27845400 1915 #define ADC_CSR_AWD2_Pos (8U)
AnnaBridge 172:65be27845400 1916 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1917 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
AnnaBridge 172:65be27845400 1918 #define ADC_CSR_EOC2_Pos (9U)
AnnaBridge 172:65be27845400 1919 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1920 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
AnnaBridge 172:65be27845400 1921 #define ADC_CSR_JEOC2_Pos (10U)
AnnaBridge 172:65be27845400 1922 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1923 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
AnnaBridge 172:65be27845400 1924 #define ADC_CSR_JSTRT2_Pos (11U)
AnnaBridge 172:65be27845400 1925 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1926 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
AnnaBridge 172:65be27845400 1927 #define ADC_CSR_STRT2_Pos (12U)
AnnaBridge 172:65be27845400 1928 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 1929 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
AnnaBridge 172:65be27845400 1930 #define ADC_CSR_OVR2_Pos (13U)
AnnaBridge 172:65be27845400 1931 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1932 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
AnnaBridge 172:65be27845400 1933 #define ADC_CSR_AWD3_Pos (16U)
AnnaBridge 172:65be27845400 1934 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1935 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
AnnaBridge 172:65be27845400 1936 #define ADC_CSR_EOC3_Pos (17U)
AnnaBridge 172:65be27845400 1937 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1938 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
AnnaBridge 172:65be27845400 1939 #define ADC_CSR_JEOC3_Pos (18U)
AnnaBridge 172:65be27845400 1940 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 1941 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
AnnaBridge 172:65be27845400 1942 #define ADC_CSR_JSTRT3_Pos (19U)
AnnaBridge 172:65be27845400 1943 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 1944 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
AnnaBridge 172:65be27845400 1945 #define ADC_CSR_STRT3_Pos (20U)
AnnaBridge 172:65be27845400 1946 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 1947 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
AnnaBridge 172:65be27845400 1948 #define ADC_CSR_OVR3_Pos (21U)
AnnaBridge 172:65be27845400 1949 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 1950 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
AnnaBridge 172:65be27845400 1951
AnnaBridge 172:65be27845400 1952 /* Legacy defines */
AnnaBridge 172:65be27845400 1953 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
AnnaBridge 172:65be27845400 1954 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
AnnaBridge 172:65be27845400 1955 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
AnnaBridge 172:65be27845400 1956
AnnaBridge 172:65be27845400 1957 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 172:65be27845400 1958 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 172:65be27845400 1959 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 1960 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 172:65be27845400 1961 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 1962 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 1963 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 1964 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 1965 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 1966 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 172:65be27845400 1967 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 1968 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 172:65be27845400 1969 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 1970 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 1971 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 1972 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 1973 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 172:65be27845400 1974 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 1975 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 172:65be27845400 1976 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 172:65be27845400 1977 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 1978 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 172:65be27845400 1979 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 1980 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 1981 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 172:65be27845400 1982 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 1983 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 172:65be27845400 1984 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 1985 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 1986 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 172:65be27845400 1987 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 1988 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 172:65be27845400 1989 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 172:65be27845400 1990 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 1991 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
AnnaBridge 172:65be27845400 1992
AnnaBridge 172:65be27845400 1993 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 172:65be27845400 1994 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 172:65be27845400 1995 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 1996 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 172:65be27845400 1997 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 172:65be27845400 1998 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 1999 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 172:65be27845400 2000
AnnaBridge 172:65be27845400 2001 /* Legacy defines */
AnnaBridge 172:65be27845400 2002 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 172:65be27845400 2003 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
AnnaBridge 172:65be27845400 2004
AnnaBridge 172:65be27845400 2005 /******************************************************************************/
AnnaBridge 172:65be27845400 2006 /* */
AnnaBridge 172:65be27845400 2007 /* Controller Area Network */
AnnaBridge 172:65be27845400 2008 /* */
AnnaBridge 172:65be27845400 2009 /******************************************************************************/
AnnaBridge 172:65be27845400 2010 /*!<CAN control and status registers */
AnnaBridge 172:65be27845400 2011 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 172:65be27845400 2012 #define CAN_MCR_INRQ_Pos (0U)
AnnaBridge 172:65be27845400 2013 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2014 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
AnnaBridge 172:65be27845400 2015 #define CAN_MCR_SLEEP_Pos (1U)
AnnaBridge 172:65be27845400 2016 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2017 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
AnnaBridge 172:65be27845400 2018 #define CAN_MCR_TXFP_Pos (2U)
AnnaBridge 172:65be27845400 2019 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2020 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
AnnaBridge 172:65be27845400 2021 #define CAN_MCR_RFLM_Pos (3U)
AnnaBridge 172:65be27845400 2022 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2023 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
AnnaBridge 172:65be27845400 2024 #define CAN_MCR_NART_Pos (4U)
AnnaBridge 172:65be27845400 2025 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2026 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
AnnaBridge 172:65be27845400 2027 #define CAN_MCR_AWUM_Pos (5U)
AnnaBridge 172:65be27845400 2028 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2029 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
AnnaBridge 172:65be27845400 2030 #define CAN_MCR_ABOM_Pos (6U)
AnnaBridge 172:65be27845400 2031 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2032 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
AnnaBridge 172:65be27845400 2033 #define CAN_MCR_TTCM_Pos (7U)
AnnaBridge 172:65be27845400 2034 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2035 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
AnnaBridge 172:65be27845400 2036 #define CAN_MCR_RESET_Pos (15U)
AnnaBridge 172:65be27845400 2037 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2038 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
AnnaBridge 172:65be27845400 2039 #define CAN_MCR_DBF_Pos (16U)
AnnaBridge 172:65be27845400 2040 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2041 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
AnnaBridge 172:65be27845400 2042 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 172:65be27845400 2043 #define CAN_MSR_INAK_Pos (0U)
AnnaBridge 172:65be27845400 2044 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2045 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
AnnaBridge 172:65be27845400 2046 #define CAN_MSR_SLAK_Pos (1U)
AnnaBridge 172:65be27845400 2047 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2048 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
AnnaBridge 172:65be27845400 2049 #define CAN_MSR_ERRI_Pos (2U)
AnnaBridge 172:65be27845400 2050 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2051 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
AnnaBridge 172:65be27845400 2052 #define CAN_MSR_WKUI_Pos (3U)
AnnaBridge 172:65be27845400 2053 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2054 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
AnnaBridge 172:65be27845400 2055 #define CAN_MSR_SLAKI_Pos (4U)
AnnaBridge 172:65be27845400 2056 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2057 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
AnnaBridge 172:65be27845400 2058 #define CAN_MSR_TXM_Pos (8U)
AnnaBridge 172:65be27845400 2059 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2060 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
AnnaBridge 172:65be27845400 2061 #define CAN_MSR_RXM_Pos (9U)
AnnaBridge 172:65be27845400 2062 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2063 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
AnnaBridge 172:65be27845400 2064 #define CAN_MSR_SAMP_Pos (10U)
AnnaBridge 172:65be27845400 2065 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2066 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
AnnaBridge 172:65be27845400 2067 #define CAN_MSR_RX_Pos (11U)
AnnaBridge 172:65be27845400 2068 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2069 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
AnnaBridge 172:65be27845400 2070
AnnaBridge 172:65be27845400 2071 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 172:65be27845400 2072 #define CAN_TSR_RQCP0_Pos (0U)
AnnaBridge 172:65be27845400 2073 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2074 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
AnnaBridge 172:65be27845400 2075 #define CAN_TSR_TXOK0_Pos (1U)
AnnaBridge 172:65be27845400 2076 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2077 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
AnnaBridge 172:65be27845400 2078 #define CAN_TSR_ALST0_Pos (2U)
AnnaBridge 172:65be27845400 2079 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2080 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 172:65be27845400 2081 #define CAN_TSR_TERR0_Pos (3U)
AnnaBridge 172:65be27845400 2082 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2083 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
AnnaBridge 172:65be27845400 2084 #define CAN_TSR_ABRQ0_Pos (7U)
AnnaBridge 172:65be27845400 2085 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2086 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
AnnaBridge 172:65be27845400 2087 #define CAN_TSR_RQCP1_Pos (8U)
AnnaBridge 172:65be27845400 2088 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2089 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
AnnaBridge 172:65be27845400 2090 #define CAN_TSR_TXOK1_Pos (9U)
AnnaBridge 172:65be27845400 2091 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2092 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
AnnaBridge 172:65be27845400 2093 #define CAN_TSR_ALST1_Pos (10U)
AnnaBridge 172:65be27845400 2094 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2095 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 172:65be27845400 2096 #define CAN_TSR_TERR1_Pos (11U)
AnnaBridge 172:65be27845400 2097 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2098 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
AnnaBridge 172:65be27845400 2099 #define CAN_TSR_ABRQ1_Pos (15U)
AnnaBridge 172:65be27845400 2100 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2101 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
AnnaBridge 172:65be27845400 2102 #define CAN_TSR_RQCP2_Pos (16U)
AnnaBridge 172:65be27845400 2103 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2104 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
AnnaBridge 172:65be27845400 2105 #define CAN_TSR_TXOK2_Pos (17U)
AnnaBridge 172:65be27845400 2106 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2107 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
AnnaBridge 172:65be27845400 2108 #define CAN_TSR_ALST2_Pos (18U)
AnnaBridge 172:65be27845400 2109 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2110 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 172:65be27845400 2111 #define CAN_TSR_TERR2_Pos (19U)
AnnaBridge 172:65be27845400 2112 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2113 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
AnnaBridge 172:65be27845400 2114 #define CAN_TSR_ABRQ2_Pos (23U)
AnnaBridge 172:65be27845400 2115 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2116 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
AnnaBridge 172:65be27845400 2117 #define CAN_TSR_CODE_Pos (24U)
AnnaBridge 172:65be27845400 2118 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 2119 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
AnnaBridge 172:65be27845400 2120
AnnaBridge 172:65be27845400 2121 #define CAN_TSR_TME_Pos (26U)
AnnaBridge 172:65be27845400 2122 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
AnnaBridge 172:65be27845400 2123 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
AnnaBridge 172:65be27845400 2124 #define CAN_TSR_TME0_Pos (26U)
AnnaBridge 172:65be27845400 2125 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2126 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
AnnaBridge 172:65be27845400 2127 #define CAN_TSR_TME1_Pos (27U)
AnnaBridge 172:65be27845400 2128 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2129 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
AnnaBridge 172:65be27845400 2130 #define CAN_TSR_TME2_Pos (28U)
AnnaBridge 172:65be27845400 2131 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 2132 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
AnnaBridge 172:65be27845400 2133
AnnaBridge 172:65be27845400 2134 #define CAN_TSR_LOW_Pos (29U)
AnnaBridge 172:65be27845400 2135 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
AnnaBridge 172:65be27845400 2136 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
AnnaBridge 172:65be27845400 2137 #define CAN_TSR_LOW0_Pos (29U)
AnnaBridge 172:65be27845400 2138 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 2139 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 172:65be27845400 2140 #define CAN_TSR_LOW1_Pos (30U)
AnnaBridge 172:65be27845400 2141 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 2142 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 172:65be27845400 2143 #define CAN_TSR_LOW2_Pos (31U)
AnnaBridge 172:65be27845400 2144 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 2145 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
AnnaBridge 172:65be27845400 2146
AnnaBridge 172:65be27845400 2147 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 172:65be27845400 2148 #define CAN_RF0R_FMP0_Pos (0U)
AnnaBridge 172:65be27845400 2149 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 2150 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
AnnaBridge 172:65be27845400 2151 #define CAN_RF0R_FULL0_Pos (3U)
AnnaBridge 172:65be27845400 2152 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2153 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
AnnaBridge 172:65be27845400 2154 #define CAN_RF0R_FOVR0_Pos (4U)
AnnaBridge 172:65be27845400 2155 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2156 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
AnnaBridge 172:65be27845400 2157 #define CAN_RF0R_RFOM0_Pos (5U)
AnnaBridge 172:65be27845400 2158 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2159 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
AnnaBridge 172:65be27845400 2160
AnnaBridge 172:65be27845400 2161 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 172:65be27845400 2162 #define CAN_RF1R_FMP1_Pos (0U)
AnnaBridge 172:65be27845400 2163 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 2164 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
AnnaBridge 172:65be27845400 2165 #define CAN_RF1R_FULL1_Pos (3U)
AnnaBridge 172:65be27845400 2166 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2167 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
AnnaBridge 172:65be27845400 2168 #define CAN_RF1R_FOVR1_Pos (4U)
AnnaBridge 172:65be27845400 2169 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2170 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
AnnaBridge 172:65be27845400 2171 #define CAN_RF1R_RFOM1_Pos (5U)
AnnaBridge 172:65be27845400 2172 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2173 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
AnnaBridge 172:65be27845400 2174
AnnaBridge 172:65be27845400 2175 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 172:65be27845400 2176 #define CAN_IER_TMEIE_Pos (0U)
AnnaBridge 172:65be27845400 2177 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2178 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 172:65be27845400 2179 #define CAN_IER_FMPIE0_Pos (1U)
AnnaBridge 172:65be27845400 2180 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2181 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 172:65be27845400 2182 #define CAN_IER_FFIE0_Pos (2U)
AnnaBridge 172:65be27845400 2183 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2184 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 172:65be27845400 2185 #define CAN_IER_FOVIE0_Pos (3U)
AnnaBridge 172:65be27845400 2186 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2187 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 172:65be27845400 2188 #define CAN_IER_FMPIE1_Pos (4U)
AnnaBridge 172:65be27845400 2189 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2190 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 172:65be27845400 2191 #define CAN_IER_FFIE1_Pos (5U)
AnnaBridge 172:65be27845400 2192 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2193 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 172:65be27845400 2194 #define CAN_IER_FOVIE1_Pos (6U)
AnnaBridge 172:65be27845400 2195 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2196 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 172:65be27845400 2197 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 172:65be27845400 2198 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2199 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
AnnaBridge 172:65be27845400 2200 #define CAN_IER_EPVIE_Pos (9U)
AnnaBridge 172:65be27845400 2201 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2202 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
AnnaBridge 172:65be27845400 2203 #define CAN_IER_BOFIE_Pos (10U)
AnnaBridge 172:65be27845400 2204 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2205 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
AnnaBridge 172:65be27845400 2206 #define CAN_IER_LECIE_Pos (11U)
AnnaBridge 172:65be27845400 2207 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2208 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
AnnaBridge 172:65be27845400 2209 #define CAN_IER_ERRIE_Pos (15U)
AnnaBridge 172:65be27845400 2210 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2211 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 172:65be27845400 2212 #define CAN_IER_WKUIE_Pos (16U)
AnnaBridge 172:65be27845400 2213 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2214 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
AnnaBridge 172:65be27845400 2215 #define CAN_IER_SLKIE_Pos (17U)
AnnaBridge 172:65be27845400 2216 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2217 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
AnnaBridge 172:65be27845400 2218 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 172:65be27845400 2219
AnnaBridge 172:65be27845400 2220 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 172:65be27845400 2221 #define CAN_ESR_EWGF_Pos (0U)
AnnaBridge 172:65be27845400 2222 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2223 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
AnnaBridge 172:65be27845400 2224 #define CAN_ESR_EPVF_Pos (1U)
AnnaBridge 172:65be27845400 2225 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2226 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
AnnaBridge 172:65be27845400 2227 #define CAN_ESR_BOFF_Pos (2U)
AnnaBridge 172:65be27845400 2228 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2229 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
AnnaBridge 172:65be27845400 2230
AnnaBridge 172:65be27845400 2231 #define CAN_ESR_LEC_Pos (4U)
AnnaBridge 172:65be27845400 2232 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 2233 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 172:65be27845400 2234 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2235 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2236 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2237
AnnaBridge 172:65be27845400 2238 #define CAN_ESR_TEC_Pos (16U)
AnnaBridge 172:65be27845400 2239 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2240 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 172:65be27845400 2241 #define CAN_ESR_REC_Pos (24U)
AnnaBridge 172:65be27845400 2242 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2243 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
AnnaBridge 172:65be27845400 2244
AnnaBridge 172:65be27845400 2245 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 172:65be27845400 2246 #define CAN_BTR_BRP_Pos (0U)
AnnaBridge 172:65be27845400 2247 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 2248 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
AnnaBridge 172:65be27845400 2249 #define CAN_BTR_TS1_Pos (16U)
AnnaBridge 172:65be27845400 2250 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 2251 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
AnnaBridge 172:65be27845400 2252 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2253 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2254 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2255 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2256 #define CAN_BTR_TS2_Pos (20U)
AnnaBridge 172:65be27845400 2257 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
AnnaBridge 172:65be27845400 2258 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
AnnaBridge 172:65be27845400 2259 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2260 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2261 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2262 #define CAN_BTR_SJW_Pos (24U)
AnnaBridge 172:65be27845400 2263 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 2264 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
AnnaBridge 172:65be27845400 2265 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2266 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2267 #define CAN_BTR_LBKM_Pos (30U)
AnnaBridge 172:65be27845400 2268 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 2269 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
AnnaBridge 172:65be27845400 2270 #define CAN_BTR_SILM_Pos (31U)
AnnaBridge 172:65be27845400 2271 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 2272 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
AnnaBridge 172:65be27845400 2273
AnnaBridge 172:65be27845400 2274
AnnaBridge 172:65be27845400 2275 /*!<Mailbox registers */
AnnaBridge 172:65be27845400 2276 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 172:65be27845400 2277 #define CAN_TI0R_TXRQ_Pos (0U)
AnnaBridge 172:65be27845400 2278 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2279 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 172:65be27845400 2280 #define CAN_TI0R_RTR_Pos (1U)
AnnaBridge 172:65be27845400 2281 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2282 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 172:65be27845400 2283 #define CAN_TI0R_IDE_Pos (2U)
AnnaBridge 172:65be27845400 2284 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2285 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 172:65be27845400 2286 #define CAN_TI0R_EXID_Pos (3U)
AnnaBridge 172:65be27845400 2287 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 172:65be27845400 2288 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 172:65be27845400 2289 #define CAN_TI0R_STID_Pos (21U)
AnnaBridge 172:65be27845400 2290 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 172:65be27845400 2291 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 172:65be27845400 2292
AnnaBridge 172:65be27845400 2293 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 172:65be27845400 2294 #define CAN_TDT0R_DLC_Pos (0U)
AnnaBridge 172:65be27845400 2295 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 2296 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 172:65be27845400 2297 #define CAN_TDT0R_TGT_Pos (8U)
AnnaBridge 172:65be27845400 2298 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2299 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 172:65be27845400 2300 #define CAN_TDT0R_TIME_Pos (16U)
AnnaBridge 172:65be27845400 2301 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 2302 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 172:65be27845400 2303
AnnaBridge 172:65be27845400 2304 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 172:65be27845400 2305 #define CAN_TDL0R_DATA0_Pos (0U)
AnnaBridge 172:65be27845400 2306 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2307 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 172:65be27845400 2308 #define CAN_TDL0R_DATA1_Pos (8U)
AnnaBridge 172:65be27845400 2309 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2310 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 172:65be27845400 2311 #define CAN_TDL0R_DATA2_Pos (16U)
AnnaBridge 172:65be27845400 2312 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2313 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 172:65be27845400 2314 #define CAN_TDL0R_DATA3_Pos (24U)
AnnaBridge 172:65be27845400 2315 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2316 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 172:65be27845400 2317
AnnaBridge 172:65be27845400 2318 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 172:65be27845400 2319 #define CAN_TDH0R_DATA4_Pos (0U)
AnnaBridge 172:65be27845400 2320 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2321 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 172:65be27845400 2322 #define CAN_TDH0R_DATA5_Pos (8U)
AnnaBridge 172:65be27845400 2323 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2324 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 172:65be27845400 2325 #define CAN_TDH0R_DATA6_Pos (16U)
AnnaBridge 172:65be27845400 2326 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2327 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 172:65be27845400 2328 #define CAN_TDH0R_DATA7_Pos (24U)
AnnaBridge 172:65be27845400 2329 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2330 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 172:65be27845400 2331
AnnaBridge 172:65be27845400 2332 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 172:65be27845400 2333 #define CAN_TI1R_TXRQ_Pos (0U)
AnnaBridge 172:65be27845400 2334 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2335 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 172:65be27845400 2336 #define CAN_TI1R_RTR_Pos (1U)
AnnaBridge 172:65be27845400 2337 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2338 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 172:65be27845400 2339 #define CAN_TI1R_IDE_Pos (2U)
AnnaBridge 172:65be27845400 2340 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2341 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 172:65be27845400 2342 #define CAN_TI1R_EXID_Pos (3U)
AnnaBridge 172:65be27845400 2343 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 172:65be27845400 2344 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 172:65be27845400 2345 #define CAN_TI1R_STID_Pos (21U)
AnnaBridge 172:65be27845400 2346 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 172:65be27845400 2347 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 172:65be27845400 2348
AnnaBridge 172:65be27845400 2349 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 172:65be27845400 2350 #define CAN_TDT1R_DLC_Pos (0U)
AnnaBridge 172:65be27845400 2351 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 2352 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 172:65be27845400 2353 #define CAN_TDT1R_TGT_Pos (8U)
AnnaBridge 172:65be27845400 2354 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2355 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 172:65be27845400 2356 #define CAN_TDT1R_TIME_Pos (16U)
AnnaBridge 172:65be27845400 2357 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 2358 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 172:65be27845400 2359
AnnaBridge 172:65be27845400 2360 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 172:65be27845400 2361 #define CAN_TDL1R_DATA0_Pos (0U)
AnnaBridge 172:65be27845400 2362 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2363 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 172:65be27845400 2364 #define CAN_TDL1R_DATA1_Pos (8U)
AnnaBridge 172:65be27845400 2365 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2366 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 172:65be27845400 2367 #define CAN_TDL1R_DATA2_Pos (16U)
AnnaBridge 172:65be27845400 2368 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2369 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 172:65be27845400 2370 #define CAN_TDL1R_DATA3_Pos (24U)
AnnaBridge 172:65be27845400 2371 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2372 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 172:65be27845400 2373
AnnaBridge 172:65be27845400 2374 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 172:65be27845400 2375 #define CAN_TDH1R_DATA4_Pos (0U)
AnnaBridge 172:65be27845400 2376 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2377 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 172:65be27845400 2378 #define CAN_TDH1R_DATA5_Pos (8U)
AnnaBridge 172:65be27845400 2379 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2380 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 172:65be27845400 2381 #define CAN_TDH1R_DATA6_Pos (16U)
AnnaBridge 172:65be27845400 2382 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2383 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 172:65be27845400 2384 #define CAN_TDH1R_DATA7_Pos (24U)
AnnaBridge 172:65be27845400 2385 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2386 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 172:65be27845400 2387
AnnaBridge 172:65be27845400 2388 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 172:65be27845400 2389 #define CAN_TI2R_TXRQ_Pos (0U)
AnnaBridge 172:65be27845400 2390 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2391 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 172:65be27845400 2392 #define CAN_TI2R_RTR_Pos (1U)
AnnaBridge 172:65be27845400 2393 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2394 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 172:65be27845400 2395 #define CAN_TI2R_IDE_Pos (2U)
AnnaBridge 172:65be27845400 2396 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2397 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 172:65be27845400 2398 #define CAN_TI2R_EXID_Pos (3U)
AnnaBridge 172:65be27845400 2399 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 172:65be27845400 2400 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
AnnaBridge 172:65be27845400 2401 #define CAN_TI2R_STID_Pos (21U)
AnnaBridge 172:65be27845400 2402 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 172:65be27845400 2403 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 172:65be27845400 2404
AnnaBridge 172:65be27845400 2405 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 172:65be27845400 2406 #define CAN_TDT2R_DLC_Pos (0U)
AnnaBridge 172:65be27845400 2407 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 2408 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
AnnaBridge 172:65be27845400 2409 #define CAN_TDT2R_TGT_Pos (8U)
AnnaBridge 172:65be27845400 2410 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2411 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 172:65be27845400 2412 #define CAN_TDT2R_TIME_Pos (16U)
AnnaBridge 172:65be27845400 2413 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 2414 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 172:65be27845400 2415
AnnaBridge 172:65be27845400 2416 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 172:65be27845400 2417 #define CAN_TDL2R_DATA0_Pos (0U)
AnnaBridge 172:65be27845400 2418 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2419 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 172:65be27845400 2420 #define CAN_TDL2R_DATA1_Pos (8U)
AnnaBridge 172:65be27845400 2421 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2422 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 172:65be27845400 2423 #define CAN_TDL2R_DATA2_Pos (16U)
AnnaBridge 172:65be27845400 2424 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2425 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 172:65be27845400 2426 #define CAN_TDL2R_DATA3_Pos (24U)
AnnaBridge 172:65be27845400 2427 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2428 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 172:65be27845400 2429
AnnaBridge 172:65be27845400 2430 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 172:65be27845400 2431 #define CAN_TDH2R_DATA4_Pos (0U)
AnnaBridge 172:65be27845400 2432 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2433 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 172:65be27845400 2434 #define CAN_TDH2R_DATA5_Pos (8U)
AnnaBridge 172:65be27845400 2435 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2436 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 172:65be27845400 2437 #define CAN_TDH2R_DATA6_Pos (16U)
AnnaBridge 172:65be27845400 2438 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2439 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 172:65be27845400 2440 #define CAN_TDH2R_DATA7_Pos (24U)
AnnaBridge 172:65be27845400 2441 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2442 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 172:65be27845400 2443
AnnaBridge 172:65be27845400 2444 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 172:65be27845400 2445 #define CAN_RI0R_RTR_Pos (1U)
AnnaBridge 172:65be27845400 2446 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2447 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 172:65be27845400 2448 #define CAN_RI0R_IDE_Pos (2U)
AnnaBridge 172:65be27845400 2449 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2450 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 172:65be27845400 2451 #define CAN_RI0R_EXID_Pos (3U)
AnnaBridge 172:65be27845400 2452 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 172:65be27845400 2453 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 172:65be27845400 2454 #define CAN_RI0R_STID_Pos (21U)
AnnaBridge 172:65be27845400 2455 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 172:65be27845400 2456 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 172:65be27845400 2457
AnnaBridge 172:65be27845400 2458 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 172:65be27845400 2459 #define CAN_RDT0R_DLC_Pos (0U)
AnnaBridge 172:65be27845400 2460 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 2461 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 172:65be27845400 2462 #define CAN_RDT0R_FMI_Pos (8U)
AnnaBridge 172:65be27845400 2463 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2464 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 172:65be27845400 2465 #define CAN_RDT0R_TIME_Pos (16U)
AnnaBridge 172:65be27845400 2466 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 2467 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 172:65be27845400 2468
AnnaBridge 172:65be27845400 2469 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 172:65be27845400 2470 #define CAN_RDL0R_DATA0_Pos (0U)
AnnaBridge 172:65be27845400 2471 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2472 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 172:65be27845400 2473 #define CAN_RDL0R_DATA1_Pos (8U)
AnnaBridge 172:65be27845400 2474 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2475 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 172:65be27845400 2476 #define CAN_RDL0R_DATA2_Pos (16U)
AnnaBridge 172:65be27845400 2477 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2478 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 172:65be27845400 2479 #define CAN_RDL0R_DATA3_Pos (24U)
AnnaBridge 172:65be27845400 2480 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2481 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 172:65be27845400 2482
AnnaBridge 172:65be27845400 2483 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 172:65be27845400 2484 #define CAN_RDH0R_DATA4_Pos (0U)
AnnaBridge 172:65be27845400 2485 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2486 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 172:65be27845400 2487 #define CAN_RDH0R_DATA5_Pos (8U)
AnnaBridge 172:65be27845400 2488 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2489 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 172:65be27845400 2490 #define CAN_RDH0R_DATA6_Pos (16U)
AnnaBridge 172:65be27845400 2491 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2492 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 172:65be27845400 2493 #define CAN_RDH0R_DATA7_Pos (24U)
AnnaBridge 172:65be27845400 2494 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2495 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 172:65be27845400 2496
AnnaBridge 172:65be27845400 2497 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 172:65be27845400 2498 #define CAN_RI1R_RTR_Pos (1U)
AnnaBridge 172:65be27845400 2499 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2500 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 172:65be27845400 2501 #define CAN_RI1R_IDE_Pos (2U)
AnnaBridge 172:65be27845400 2502 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2503 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 172:65be27845400 2504 #define CAN_RI1R_EXID_Pos (3U)
AnnaBridge 172:65be27845400 2505 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 172:65be27845400 2506 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
AnnaBridge 172:65be27845400 2507 #define CAN_RI1R_STID_Pos (21U)
AnnaBridge 172:65be27845400 2508 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 172:65be27845400 2509 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
AnnaBridge 172:65be27845400 2510
AnnaBridge 172:65be27845400 2511 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 172:65be27845400 2512 #define CAN_RDT1R_DLC_Pos (0U)
AnnaBridge 172:65be27845400 2513 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 2514 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 172:65be27845400 2515 #define CAN_RDT1R_FMI_Pos (8U)
AnnaBridge 172:65be27845400 2516 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2517 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 172:65be27845400 2518 #define CAN_RDT1R_TIME_Pos (16U)
AnnaBridge 172:65be27845400 2519 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 2520 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
AnnaBridge 172:65be27845400 2521
AnnaBridge 172:65be27845400 2522 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 172:65be27845400 2523 #define CAN_RDL1R_DATA0_Pos (0U)
AnnaBridge 172:65be27845400 2524 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2525 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 172:65be27845400 2526 #define CAN_RDL1R_DATA1_Pos (8U)
AnnaBridge 172:65be27845400 2527 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2528 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 172:65be27845400 2529 #define CAN_RDL1R_DATA2_Pos (16U)
AnnaBridge 172:65be27845400 2530 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2531 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 172:65be27845400 2532 #define CAN_RDL1R_DATA3_Pos (24U)
AnnaBridge 172:65be27845400 2533 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2534 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
AnnaBridge 172:65be27845400 2535
AnnaBridge 172:65be27845400 2536 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 172:65be27845400 2537 #define CAN_RDH1R_DATA4_Pos (0U)
AnnaBridge 172:65be27845400 2538 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 2539 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 172:65be27845400 2540 #define CAN_RDH1R_DATA5_Pos (8U)
AnnaBridge 172:65be27845400 2541 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 2542 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 172:65be27845400 2543 #define CAN_RDH1R_DATA6_Pos (16U)
AnnaBridge 172:65be27845400 2544 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 2545 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 172:65be27845400 2546 #define CAN_RDH1R_DATA7_Pos (24U)
AnnaBridge 172:65be27845400 2547 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 2548 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
AnnaBridge 172:65be27845400 2549
AnnaBridge 172:65be27845400 2550 /*!<CAN filter registers */
AnnaBridge 172:65be27845400 2551 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 172:65be27845400 2552 #define CAN_FMR_FINIT_Pos (0U)
AnnaBridge 172:65be27845400 2553 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2554 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
AnnaBridge 172:65be27845400 2555 #define CAN_FMR_CAN2SB_Pos (8U)
AnnaBridge 172:65be27845400 2556 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
AnnaBridge 172:65be27845400 2557 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
AnnaBridge 172:65be27845400 2558
AnnaBridge 172:65be27845400 2559 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 172:65be27845400 2560 #define CAN_FM1R_FBM_Pos (0U)
AnnaBridge 172:65be27845400 2561 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 172:65be27845400 2562 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
AnnaBridge 172:65be27845400 2563 #define CAN_FM1R_FBM0_Pos (0U)
AnnaBridge 172:65be27845400 2564 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2565 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
AnnaBridge 172:65be27845400 2566 #define CAN_FM1R_FBM1_Pos (1U)
AnnaBridge 172:65be27845400 2567 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2568 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
AnnaBridge 172:65be27845400 2569 #define CAN_FM1R_FBM2_Pos (2U)
AnnaBridge 172:65be27845400 2570 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2571 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
AnnaBridge 172:65be27845400 2572 #define CAN_FM1R_FBM3_Pos (3U)
AnnaBridge 172:65be27845400 2573 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2574 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
AnnaBridge 172:65be27845400 2575 #define CAN_FM1R_FBM4_Pos (4U)
AnnaBridge 172:65be27845400 2576 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2577 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
AnnaBridge 172:65be27845400 2578 #define CAN_FM1R_FBM5_Pos (5U)
AnnaBridge 172:65be27845400 2579 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2580 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
AnnaBridge 172:65be27845400 2581 #define CAN_FM1R_FBM6_Pos (6U)
AnnaBridge 172:65be27845400 2582 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2583 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
AnnaBridge 172:65be27845400 2584 #define CAN_FM1R_FBM7_Pos (7U)
AnnaBridge 172:65be27845400 2585 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2586 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
AnnaBridge 172:65be27845400 2587 #define CAN_FM1R_FBM8_Pos (8U)
AnnaBridge 172:65be27845400 2588 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2589 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
AnnaBridge 172:65be27845400 2590 #define CAN_FM1R_FBM9_Pos (9U)
AnnaBridge 172:65be27845400 2591 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2592 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
AnnaBridge 172:65be27845400 2593 #define CAN_FM1R_FBM10_Pos (10U)
AnnaBridge 172:65be27845400 2594 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2595 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
AnnaBridge 172:65be27845400 2596 #define CAN_FM1R_FBM11_Pos (11U)
AnnaBridge 172:65be27845400 2597 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2598 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
AnnaBridge 172:65be27845400 2599 #define CAN_FM1R_FBM12_Pos (12U)
AnnaBridge 172:65be27845400 2600 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2601 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
AnnaBridge 172:65be27845400 2602 #define CAN_FM1R_FBM13_Pos (13U)
AnnaBridge 172:65be27845400 2603 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2604 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
AnnaBridge 172:65be27845400 2605 #define CAN_FM1R_FBM14_Pos (14U)
AnnaBridge 172:65be27845400 2606 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2607 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
AnnaBridge 172:65be27845400 2608 #define CAN_FM1R_FBM15_Pos (15U)
AnnaBridge 172:65be27845400 2609 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2610 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
AnnaBridge 172:65be27845400 2611 #define CAN_FM1R_FBM16_Pos (16U)
AnnaBridge 172:65be27845400 2612 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2613 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
AnnaBridge 172:65be27845400 2614 #define CAN_FM1R_FBM17_Pos (17U)
AnnaBridge 172:65be27845400 2615 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2616 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
AnnaBridge 172:65be27845400 2617 #define CAN_FM1R_FBM18_Pos (18U)
AnnaBridge 172:65be27845400 2618 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2619 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
AnnaBridge 172:65be27845400 2620 #define CAN_FM1R_FBM19_Pos (19U)
AnnaBridge 172:65be27845400 2621 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2622 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
AnnaBridge 172:65be27845400 2623 #define CAN_FM1R_FBM20_Pos (20U)
AnnaBridge 172:65be27845400 2624 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2625 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
AnnaBridge 172:65be27845400 2626 #define CAN_FM1R_FBM21_Pos (21U)
AnnaBridge 172:65be27845400 2627 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2628 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
AnnaBridge 172:65be27845400 2629 #define CAN_FM1R_FBM22_Pos (22U)
AnnaBridge 172:65be27845400 2630 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2631 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
AnnaBridge 172:65be27845400 2632 #define CAN_FM1R_FBM23_Pos (23U)
AnnaBridge 172:65be27845400 2633 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2634 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
AnnaBridge 172:65be27845400 2635 #define CAN_FM1R_FBM24_Pos (24U)
AnnaBridge 172:65be27845400 2636 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2637 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
AnnaBridge 172:65be27845400 2638 #define CAN_FM1R_FBM25_Pos (25U)
AnnaBridge 172:65be27845400 2639 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2640 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
AnnaBridge 172:65be27845400 2641 #define CAN_FM1R_FBM26_Pos (26U)
AnnaBridge 172:65be27845400 2642 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2643 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
AnnaBridge 172:65be27845400 2644 #define CAN_FM1R_FBM27_Pos (27U)
AnnaBridge 172:65be27845400 2645 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2646 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
AnnaBridge 172:65be27845400 2647
AnnaBridge 172:65be27845400 2648 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 172:65be27845400 2649 #define CAN_FS1R_FSC_Pos (0U)
AnnaBridge 172:65be27845400 2650 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 172:65be27845400 2651 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
AnnaBridge 172:65be27845400 2652 #define CAN_FS1R_FSC0_Pos (0U)
AnnaBridge 172:65be27845400 2653 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2654 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
AnnaBridge 172:65be27845400 2655 #define CAN_FS1R_FSC1_Pos (1U)
AnnaBridge 172:65be27845400 2656 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2657 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
AnnaBridge 172:65be27845400 2658 #define CAN_FS1R_FSC2_Pos (2U)
AnnaBridge 172:65be27845400 2659 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2660 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
AnnaBridge 172:65be27845400 2661 #define CAN_FS1R_FSC3_Pos (3U)
AnnaBridge 172:65be27845400 2662 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2663 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
AnnaBridge 172:65be27845400 2664 #define CAN_FS1R_FSC4_Pos (4U)
AnnaBridge 172:65be27845400 2665 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2666 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
AnnaBridge 172:65be27845400 2667 #define CAN_FS1R_FSC5_Pos (5U)
AnnaBridge 172:65be27845400 2668 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2669 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
AnnaBridge 172:65be27845400 2670 #define CAN_FS1R_FSC6_Pos (6U)
AnnaBridge 172:65be27845400 2671 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2672 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
AnnaBridge 172:65be27845400 2673 #define CAN_FS1R_FSC7_Pos (7U)
AnnaBridge 172:65be27845400 2674 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2675 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
AnnaBridge 172:65be27845400 2676 #define CAN_FS1R_FSC8_Pos (8U)
AnnaBridge 172:65be27845400 2677 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2678 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
AnnaBridge 172:65be27845400 2679 #define CAN_FS1R_FSC9_Pos (9U)
AnnaBridge 172:65be27845400 2680 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2681 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
AnnaBridge 172:65be27845400 2682 #define CAN_FS1R_FSC10_Pos (10U)
AnnaBridge 172:65be27845400 2683 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2684 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
AnnaBridge 172:65be27845400 2685 #define CAN_FS1R_FSC11_Pos (11U)
AnnaBridge 172:65be27845400 2686 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2687 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
AnnaBridge 172:65be27845400 2688 #define CAN_FS1R_FSC12_Pos (12U)
AnnaBridge 172:65be27845400 2689 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2690 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
AnnaBridge 172:65be27845400 2691 #define CAN_FS1R_FSC13_Pos (13U)
AnnaBridge 172:65be27845400 2692 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2693 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
AnnaBridge 172:65be27845400 2694 #define CAN_FS1R_FSC14_Pos (14U)
AnnaBridge 172:65be27845400 2695 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2696 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
AnnaBridge 172:65be27845400 2697 #define CAN_FS1R_FSC15_Pos (15U)
AnnaBridge 172:65be27845400 2698 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2699 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
AnnaBridge 172:65be27845400 2700 #define CAN_FS1R_FSC16_Pos (16U)
AnnaBridge 172:65be27845400 2701 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2702 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
AnnaBridge 172:65be27845400 2703 #define CAN_FS1R_FSC17_Pos (17U)
AnnaBridge 172:65be27845400 2704 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2705 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
AnnaBridge 172:65be27845400 2706 #define CAN_FS1R_FSC18_Pos (18U)
AnnaBridge 172:65be27845400 2707 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2708 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
AnnaBridge 172:65be27845400 2709 #define CAN_FS1R_FSC19_Pos (19U)
AnnaBridge 172:65be27845400 2710 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2711 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
AnnaBridge 172:65be27845400 2712 #define CAN_FS1R_FSC20_Pos (20U)
AnnaBridge 172:65be27845400 2713 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2714 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
AnnaBridge 172:65be27845400 2715 #define CAN_FS1R_FSC21_Pos (21U)
AnnaBridge 172:65be27845400 2716 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2717 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
AnnaBridge 172:65be27845400 2718 #define CAN_FS1R_FSC22_Pos (22U)
AnnaBridge 172:65be27845400 2719 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2720 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
AnnaBridge 172:65be27845400 2721 #define CAN_FS1R_FSC23_Pos (23U)
AnnaBridge 172:65be27845400 2722 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2723 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
AnnaBridge 172:65be27845400 2724 #define CAN_FS1R_FSC24_Pos (24U)
AnnaBridge 172:65be27845400 2725 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2726 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
AnnaBridge 172:65be27845400 2727 #define CAN_FS1R_FSC25_Pos (25U)
AnnaBridge 172:65be27845400 2728 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2729 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
AnnaBridge 172:65be27845400 2730 #define CAN_FS1R_FSC26_Pos (26U)
AnnaBridge 172:65be27845400 2731 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2732 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
AnnaBridge 172:65be27845400 2733 #define CAN_FS1R_FSC27_Pos (27U)
AnnaBridge 172:65be27845400 2734 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2735 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
AnnaBridge 172:65be27845400 2736
AnnaBridge 172:65be27845400 2737 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 172:65be27845400 2738 #define CAN_FFA1R_FFA_Pos (0U)
AnnaBridge 172:65be27845400 2739 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 172:65be27845400 2740 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
AnnaBridge 172:65be27845400 2741 #define CAN_FFA1R_FFA0_Pos (0U)
AnnaBridge 172:65be27845400 2742 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2743 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
AnnaBridge 172:65be27845400 2744 #define CAN_FFA1R_FFA1_Pos (1U)
AnnaBridge 172:65be27845400 2745 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2746 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
AnnaBridge 172:65be27845400 2747 #define CAN_FFA1R_FFA2_Pos (2U)
AnnaBridge 172:65be27845400 2748 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2749 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
AnnaBridge 172:65be27845400 2750 #define CAN_FFA1R_FFA3_Pos (3U)
AnnaBridge 172:65be27845400 2751 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2752 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
AnnaBridge 172:65be27845400 2753 #define CAN_FFA1R_FFA4_Pos (4U)
AnnaBridge 172:65be27845400 2754 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2755 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
AnnaBridge 172:65be27845400 2756 #define CAN_FFA1R_FFA5_Pos (5U)
AnnaBridge 172:65be27845400 2757 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2758 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
AnnaBridge 172:65be27845400 2759 #define CAN_FFA1R_FFA6_Pos (6U)
AnnaBridge 172:65be27845400 2760 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2761 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
AnnaBridge 172:65be27845400 2762 #define CAN_FFA1R_FFA7_Pos (7U)
AnnaBridge 172:65be27845400 2763 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2764 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
AnnaBridge 172:65be27845400 2765 #define CAN_FFA1R_FFA8_Pos (8U)
AnnaBridge 172:65be27845400 2766 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2767 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
AnnaBridge 172:65be27845400 2768 #define CAN_FFA1R_FFA9_Pos (9U)
AnnaBridge 172:65be27845400 2769 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2770 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
AnnaBridge 172:65be27845400 2771 #define CAN_FFA1R_FFA10_Pos (10U)
AnnaBridge 172:65be27845400 2772 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2773 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
AnnaBridge 172:65be27845400 2774 #define CAN_FFA1R_FFA11_Pos (11U)
AnnaBridge 172:65be27845400 2775 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2776 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
AnnaBridge 172:65be27845400 2777 #define CAN_FFA1R_FFA12_Pos (12U)
AnnaBridge 172:65be27845400 2778 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2779 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
AnnaBridge 172:65be27845400 2780 #define CAN_FFA1R_FFA13_Pos (13U)
AnnaBridge 172:65be27845400 2781 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2782 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
AnnaBridge 172:65be27845400 2783 #define CAN_FFA1R_FFA14_Pos (14U)
AnnaBridge 172:65be27845400 2784 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2785 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
AnnaBridge 172:65be27845400 2786 #define CAN_FFA1R_FFA15_Pos (15U)
AnnaBridge 172:65be27845400 2787 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2788 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
AnnaBridge 172:65be27845400 2789 #define CAN_FFA1R_FFA16_Pos (16U)
AnnaBridge 172:65be27845400 2790 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2791 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
AnnaBridge 172:65be27845400 2792 #define CAN_FFA1R_FFA17_Pos (17U)
AnnaBridge 172:65be27845400 2793 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2794 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
AnnaBridge 172:65be27845400 2795 #define CAN_FFA1R_FFA18_Pos (18U)
AnnaBridge 172:65be27845400 2796 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2797 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
AnnaBridge 172:65be27845400 2798 #define CAN_FFA1R_FFA19_Pos (19U)
AnnaBridge 172:65be27845400 2799 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2800 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
AnnaBridge 172:65be27845400 2801 #define CAN_FFA1R_FFA20_Pos (20U)
AnnaBridge 172:65be27845400 2802 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2803 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
AnnaBridge 172:65be27845400 2804 #define CAN_FFA1R_FFA21_Pos (21U)
AnnaBridge 172:65be27845400 2805 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2806 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
AnnaBridge 172:65be27845400 2807 #define CAN_FFA1R_FFA22_Pos (22U)
AnnaBridge 172:65be27845400 2808 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2809 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
AnnaBridge 172:65be27845400 2810 #define CAN_FFA1R_FFA23_Pos (23U)
AnnaBridge 172:65be27845400 2811 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2812 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
AnnaBridge 172:65be27845400 2813 #define CAN_FFA1R_FFA24_Pos (24U)
AnnaBridge 172:65be27845400 2814 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2815 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
AnnaBridge 172:65be27845400 2816 #define CAN_FFA1R_FFA25_Pos (25U)
AnnaBridge 172:65be27845400 2817 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2818 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
AnnaBridge 172:65be27845400 2819 #define CAN_FFA1R_FFA26_Pos (26U)
AnnaBridge 172:65be27845400 2820 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2821 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
AnnaBridge 172:65be27845400 2822 #define CAN_FFA1R_FFA27_Pos (27U)
AnnaBridge 172:65be27845400 2823 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2824 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
AnnaBridge 172:65be27845400 2825
AnnaBridge 172:65be27845400 2826 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 172:65be27845400 2827 #define CAN_FA1R_FACT_Pos (0U)
AnnaBridge 172:65be27845400 2828 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 172:65be27845400 2829 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
AnnaBridge 172:65be27845400 2830 #define CAN_FA1R_FACT0_Pos (0U)
AnnaBridge 172:65be27845400 2831 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2832 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
AnnaBridge 172:65be27845400 2833 #define CAN_FA1R_FACT1_Pos (1U)
AnnaBridge 172:65be27845400 2834 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2835 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
AnnaBridge 172:65be27845400 2836 #define CAN_FA1R_FACT2_Pos (2U)
AnnaBridge 172:65be27845400 2837 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2838 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
AnnaBridge 172:65be27845400 2839 #define CAN_FA1R_FACT3_Pos (3U)
AnnaBridge 172:65be27845400 2840 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2841 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
AnnaBridge 172:65be27845400 2842 #define CAN_FA1R_FACT4_Pos (4U)
AnnaBridge 172:65be27845400 2843 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2844 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
AnnaBridge 172:65be27845400 2845 #define CAN_FA1R_FACT5_Pos (5U)
AnnaBridge 172:65be27845400 2846 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2847 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
AnnaBridge 172:65be27845400 2848 #define CAN_FA1R_FACT6_Pos (6U)
AnnaBridge 172:65be27845400 2849 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2850 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
AnnaBridge 172:65be27845400 2851 #define CAN_FA1R_FACT7_Pos (7U)
AnnaBridge 172:65be27845400 2852 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2853 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
AnnaBridge 172:65be27845400 2854 #define CAN_FA1R_FACT8_Pos (8U)
AnnaBridge 172:65be27845400 2855 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2856 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
AnnaBridge 172:65be27845400 2857 #define CAN_FA1R_FACT9_Pos (9U)
AnnaBridge 172:65be27845400 2858 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2859 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
AnnaBridge 172:65be27845400 2860 #define CAN_FA1R_FACT10_Pos (10U)
AnnaBridge 172:65be27845400 2861 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2862 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
AnnaBridge 172:65be27845400 2863 #define CAN_FA1R_FACT11_Pos (11U)
AnnaBridge 172:65be27845400 2864 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2865 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
AnnaBridge 172:65be27845400 2866 #define CAN_FA1R_FACT12_Pos (12U)
AnnaBridge 172:65be27845400 2867 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2868 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
AnnaBridge 172:65be27845400 2869 #define CAN_FA1R_FACT13_Pos (13U)
AnnaBridge 172:65be27845400 2870 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2871 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
AnnaBridge 172:65be27845400 2872 #define CAN_FA1R_FACT14_Pos (14U)
AnnaBridge 172:65be27845400 2873 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2874 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
AnnaBridge 172:65be27845400 2875 #define CAN_FA1R_FACT15_Pos (15U)
AnnaBridge 172:65be27845400 2876 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2877 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
AnnaBridge 172:65be27845400 2878 #define CAN_FA1R_FACT16_Pos (16U)
AnnaBridge 172:65be27845400 2879 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2880 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
AnnaBridge 172:65be27845400 2881 #define CAN_FA1R_FACT17_Pos (17U)
AnnaBridge 172:65be27845400 2882 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2883 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
AnnaBridge 172:65be27845400 2884 #define CAN_FA1R_FACT18_Pos (18U)
AnnaBridge 172:65be27845400 2885 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2886 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
AnnaBridge 172:65be27845400 2887 #define CAN_FA1R_FACT19_Pos (19U)
AnnaBridge 172:65be27845400 2888 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2889 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
AnnaBridge 172:65be27845400 2890 #define CAN_FA1R_FACT20_Pos (20U)
AnnaBridge 172:65be27845400 2891 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2892 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
AnnaBridge 172:65be27845400 2893 #define CAN_FA1R_FACT21_Pos (21U)
AnnaBridge 172:65be27845400 2894 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2895 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
AnnaBridge 172:65be27845400 2896 #define CAN_FA1R_FACT22_Pos (22U)
AnnaBridge 172:65be27845400 2897 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2898 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
AnnaBridge 172:65be27845400 2899 #define CAN_FA1R_FACT23_Pos (23U)
AnnaBridge 172:65be27845400 2900 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2901 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
AnnaBridge 172:65be27845400 2902 #define CAN_FA1R_FACT24_Pos (24U)
AnnaBridge 172:65be27845400 2903 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2904 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
AnnaBridge 172:65be27845400 2905 #define CAN_FA1R_FACT25_Pos (25U)
AnnaBridge 172:65be27845400 2906 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2907 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
AnnaBridge 172:65be27845400 2908 #define CAN_FA1R_FACT26_Pos (26U)
AnnaBridge 172:65be27845400 2909 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2910 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
AnnaBridge 172:65be27845400 2911 #define CAN_FA1R_FACT27_Pos (27U)
AnnaBridge 172:65be27845400 2912 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2913 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
AnnaBridge 172:65be27845400 2914
AnnaBridge 172:65be27845400 2915
AnnaBridge 172:65be27845400 2916 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 172:65be27845400 2917 #define CAN_F0R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 2918 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2919 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 2920 #define CAN_F0R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 2921 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2922 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 2923 #define CAN_F0R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 2924 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2925 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 2926 #define CAN_F0R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 2927 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2928 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 2929 #define CAN_F0R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 2930 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2931 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 2932 #define CAN_F0R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 2933 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2934 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 2935 #define CAN_F0R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 2936 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2937 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 2938 #define CAN_F0R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 2939 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2940 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 2941 #define CAN_F0R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 2942 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2943 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 2944 #define CAN_F0R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 2945 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2946 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 2947 #define CAN_F0R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 2948 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2949 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 2950 #define CAN_F0R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 2951 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2952 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 2953 #define CAN_F0R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 2954 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2955 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 2956 #define CAN_F0R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 2957 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2958 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 2959 #define CAN_F0R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 2960 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2961 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 2962 #define CAN_F0R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 2963 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2964 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 2965 #define CAN_F0R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 2966 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2967 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 2968 #define CAN_F0R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 2969 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2970 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 2971 #define CAN_F0R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 2972 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2973 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 2974 #define CAN_F0R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 2975 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2976 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 2977 #define CAN_F0R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 2978 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2979 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 2980 #define CAN_F0R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 2981 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2982 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 2983 #define CAN_F0R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 2984 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2985 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 2986 #define CAN_F0R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 2987 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2988 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 2989 #define CAN_F0R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 2990 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2991 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 2992 #define CAN_F0R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 2993 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2994 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 2995 #define CAN_F0R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 2996 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2997 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 2998 #define CAN_F0R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 2999 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3000 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3001 #define CAN_F0R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3002 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3003 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3004 #define CAN_F0R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3005 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3006 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3007 #define CAN_F0R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3008 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3009 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3010 #define CAN_F0R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3011 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3012 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3013
AnnaBridge 172:65be27845400 3014 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 172:65be27845400 3015 #define CAN_F1R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3016 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3017 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3018 #define CAN_F1R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3019 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3020 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3021 #define CAN_F1R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3022 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3023 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3024 #define CAN_F1R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3025 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3026 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3027 #define CAN_F1R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3028 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3029 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3030 #define CAN_F1R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3031 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3032 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3033 #define CAN_F1R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3034 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3035 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3036 #define CAN_F1R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3037 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3038 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3039 #define CAN_F1R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3040 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3041 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3042 #define CAN_F1R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3043 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3044 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3045 #define CAN_F1R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3046 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3047 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3048 #define CAN_F1R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3049 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3050 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3051 #define CAN_F1R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3052 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3053 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3054 #define CAN_F1R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3055 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3056 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3057 #define CAN_F1R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3058 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3059 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3060 #define CAN_F1R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3061 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3062 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3063 #define CAN_F1R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3064 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3065 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3066 #define CAN_F1R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3067 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3068 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3069 #define CAN_F1R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3070 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3071 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3072 #define CAN_F1R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3073 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3074 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3075 #define CAN_F1R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3076 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3077 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3078 #define CAN_F1R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3079 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3080 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3081 #define CAN_F1R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3082 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3083 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3084 #define CAN_F1R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3085 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3086 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3087 #define CAN_F1R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3088 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3089 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3090 #define CAN_F1R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3091 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3092 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3093 #define CAN_F1R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3094 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3095 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3096 #define CAN_F1R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3097 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3098 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3099 #define CAN_F1R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3100 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3101 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3102 #define CAN_F1R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3103 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3104 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3105 #define CAN_F1R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3106 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3107 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3108 #define CAN_F1R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3109 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3110 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3111
AnnaBridge 172:65be27845400 3112 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 172:65be27845400 3113 #define CAN_F2R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3114 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3115 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3116 #define CAN_F2R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3117 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3118 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3119 #define CAN_F2R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3120 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3121 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3122 #define CAN_F2R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3123 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3124 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3125 #define CAN_F2R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3126 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3127 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3128 #define CAN_F2R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3129 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3130 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3131 #define CAN_F2R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3132 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3133 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3134 #define CAN_F2R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3135 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3136 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3137 #define CAN_F2R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3138 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3139 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3140 #define CAN_F2R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3141 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3142 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3143 #define CAN_F2R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3144 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3145 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3146 #define CAN_F2R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3147 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3148 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3149 #define CAN_F2R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3150 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3151 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3152 #define CAN_F2R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3153 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3154 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3155 #define CAN_F2R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3156 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3157 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3158 #define CAN_F2R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3159 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3160 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3161 #define CAN_F2R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3162 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3163 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3164 #define CAN_F2R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3165 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3166 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3167 #define CAN_F2R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3168 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3169 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3170 #define CAN_F2R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3171 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3172 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3173 #define CAN_F2R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3174 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3175 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3176 #define CAN_F2R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3177 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3178 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3179 #define CAN_F2R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3180 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3181 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3182 #define CAN_F2R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3183 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3184 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3185 #define CAN_F2R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3186 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3187 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3188 #define CAN_F2R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3189 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3190 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3191 #define CAN_F2R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3192 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3193 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3194 #define CAN_F2R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3195 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3196 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3197 #define CAN_F2R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3198 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3199 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3200 #define CAN_F2R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3201 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3202 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3203 #define CAN_F2R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3204 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3205 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3206 #define CAN_F2R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3207 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3208 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3209
AnnaBridge 172:65be27845400 3210 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 172:65be27845400 3211 #define CAN_F3R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3212 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3213 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3214 #define CAN_F3R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3215 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3216 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3217 #define CAN_F3R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3218 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3219 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3220 #define CAN_F3R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3221 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3222 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3223 #define CAN_F3R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3224 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3225 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3226 #define CAN_F3R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3227 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3228 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3229 #define CAN_F3R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3230 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3231 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3232 #define CAN_F3R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3233 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3234 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3235 #define CAN_F3R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3236 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3237 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3238 #define CAN_F3R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3239 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3240 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3241 #define CAN_F3R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3242 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3243 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3244 #define CAN_F3R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3245 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3246 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3247 #define CAN_F3R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3248 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3249 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3250 #define CAN_F3R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3251 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3252 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3253 #define CAN_F3R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3254 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3255 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3256 #define CAN_F3R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3257 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3258 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3259 #define CAN_F3R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3260 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3261 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3262 #define CAN_F3R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3263 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3264 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3265 #define CAN_F3R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3266 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3267 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3268 #define CAN_F3R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3269 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3270 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3271 #define CAN_F3R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3272 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3273 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3274 #define CAN_F3R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3275 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3276 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3277 #define CAN_F3R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3278 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3279 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3280 #define CAN_F3R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3281 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3282 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3283 #define CAN_F3R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3284 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3285 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3286 #define CAN_F3R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3287 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3288 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3289 #define CAN_F3R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3290 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3291 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3292 #define CAN_F3R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3293 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3294 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3295 #define CAN_F3R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3296 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3297 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3298 #define CAN_F3R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3299 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3300 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3301 #define CAN_F3R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3302 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3303 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3304 #define CAN_F3R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3305 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3306 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3307
AnnaBridge 172:65be27845400 3308 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 172:65be27845400 3309 #define CAN_F4R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3310 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3311 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3312 #define CAN_F4R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3313 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3314 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3315 #define CAN_F4R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3316 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3317 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3318 #define CAN_F4R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3319 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3320 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3321 #define CAN_F4R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3322 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3323 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3324 #define CAN_F4R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3325 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3326 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3327 #define CAN_F4R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3328 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3329 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3330 #define CAN_F4R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3331 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3332 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3333 #define CAN_F4R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3334 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3335 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3336 #define CAN_F4R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3337 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3338 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3339 #define CAN_F4R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3340 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3341 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3342 #define CAN_F4R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3343 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3344 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3345 #define CAN_F4R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3346 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3347 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3348 #define CAN_F4R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3349 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3350 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3351 #define CAN_F4R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3352 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3353 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3354 #define CAN_F4R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3355 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3356 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3357 #define CAN_F4R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3358 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3359 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3360 #define CAN_F4R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3361 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3362 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3363 #define CAN_F4R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3364 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3365 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3366 #define CAN_F4R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3367 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3368 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3369 #define CAN_F4R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3370 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3371 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3372 #define CAN_F4R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3373 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3374 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3375 #define CAN_F4R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3376 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3377 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3378 #define CAN_F4R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3379 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3380 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3381 #define CAN_F4R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3382 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3383 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3384 #define CAN_F4R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3385 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3386 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3387 #define CAN_F4R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3388 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3389 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3390 #define CAN_F4R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3391 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3392 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3393 #define CAN_F4R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3394 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3395 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3396 #define CAN_F4R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3397 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3398 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3399 #define CAN_F4R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3400 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3401 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3402 #define CAN_F4R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3403 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3404 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3405
AnnaBridge 172:65be27845400 3406 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 172:65be27845400 3407 #define CAN_F5R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3408 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3409 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3410 #define CAN_F5R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3411 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3412 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3413 #define CAN_F5R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3414 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3415 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3416 #define CAN_F5R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3417 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3418 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3419 #define CAN_F5R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3420 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3421 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3422 #define CAN_F5R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3423 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3424 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3425 #define CAN_F5R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3426 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3427 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3428 #define CAN_F5R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3429 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3430 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3431 #define CAN_F5R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3432 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3433 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3434 #define CAN_F5R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3435 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3436 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3437 #define CAN_F5R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3438 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3439 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3440 #define CAN_F5R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3441 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3442 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3443 #define CAN_F5R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3444 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3445 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3446 #define CAN_F5R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3447 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3448 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3449 #define CAN_F5R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3450 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3451 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3452 #define CAN_F5R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3453 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3454 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3455 #define CAN_F5R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3456 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3457 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3458 #define CAN_F5R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3459 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3460 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3461 #define CAN_F5R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3462 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3463 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3464 #define CAN_F5R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3465 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3466 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3467 #define CAN_F5R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3468 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3469 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3470 #define CAN_F5R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3471 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3472 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3473 #define CAN_F5R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3474 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3475 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3476 #define CAN_F5R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3477 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3478 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3479 #define CAN_F5R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3480 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3481 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3482 #define CAN_F5R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3483 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3484 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3485 #define CAN_F5R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3486 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3487 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3488 #define CAN_F5R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3489 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3490 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3491 #define CAN_F5R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3492 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3493 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3494 #define CAN_F5R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3495 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3496 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3497 #define CAN_F5R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3498 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3499 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3500 #define CAN_F5R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3501 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3502 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3503
AnnaBridge 172:65be27845400 3504 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 172:65be27845400 3505 #define CAN_F6R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3506 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3507 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3508 #define CAN_F6R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3509 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3510 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3511 #define CAN_F6R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3512 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3513 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3514 #define CAN_F6R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3515 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3516 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3517 #define CAN_F6R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3518 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3519 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3520 #define CAN_F6R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3521 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3522 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3523 #define CAN_F6R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3524 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3525 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3526 #define CAN_F6R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3527 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3528 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3529 #define CAN_F6R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3530 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3531 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3532 #define CAN_F6R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3533 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3534 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3535 #define CAN_F6R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3536 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3537 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3538 #define CAN_F6R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3539 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3540 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3541 #define CAN_F6R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3542 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3543 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3544 #define CAN_F6R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3545 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3546 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3547 #define CAN_F6R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3548 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3549 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3550 #define CAN_F6R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3551 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3552 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3553 #define CAN_F6R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3554 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3555 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3556 #define CAN_F6R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3557 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3558 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3559 #define CAN_F6R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3560 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3561 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3562 #define CAN_F6R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3563 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3564 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3565 #define CAN_F6R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3566 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3567 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3568 #define CAN_F6R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3569 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3570 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3571 #define CAN_F6R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3572 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3573 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3574 #define CAN_F6R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3575 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3576 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3577 #define CAN_F6R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3578 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3579 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3580 #define CAN_F6R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3581 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3582 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3583 #define CAN_F6R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3584 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3585 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3586 #define CAN_F6R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3587 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3588 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3589 #define CAN_F6R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3590 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3591 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3592 #define CAN_F6R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3593 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3594 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3595 #define CAN_F6R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3596 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3597 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3598 #define CAN_F6R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3599 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3600 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3601
AnnaBridge 172:65be27845400 3602 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 172:65be27845400 3603 #define CAN_F7R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3604 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3605 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3606 #define CAN_F7R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3607 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3608 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3609 #define CAN_F7R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3610 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3611 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3612 #define CAN_F7R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3613 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3614 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3615 #define CAN_F7R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3616 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3617 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3618 #define CAN_F7R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3619 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3620 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3621 #define CAN_F7R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3622 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3623 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3624 #define CAN_F7R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3625 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3626 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3627 #define CAN_F7R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3628 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3629 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3630 #define CAN_F7R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3631 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3632 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3633 #define CAN_F7R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3634 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3635 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3636 #define CAN_F7R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3637 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3638 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3639 #define CAN_F7R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3640 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3641 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3642 #define CAN_F7R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3643 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3644 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3645 #define CAN_F7R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3646 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3647 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3648 #define CAN_F7R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3649 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3650 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3651 #define CAN_F7R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3652 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3653 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3654 #define CAN_F7R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3655 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3656 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3657 #define CAN_F7R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3658 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3659 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3660 #define CAN_F7R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3661 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3662 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3663 #define CAN_F7R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3664 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3665 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3666 #define CAN_F7R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3667 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3668 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3669 #define CAN_F7R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3670 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3671 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3672 #define CAN_F7R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3673 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3674 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3675 #define CAN_F7R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3676 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3677 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3678 #define CAN_F7R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3679 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3680 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3681 #define CAN_F7R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3682 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3683 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3684 #define CAN_F7R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3685 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3686 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3687 #define CAN_F7R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3688 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3689 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3690 #define CAN_F7R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3691 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3692 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3693 #define CAN_F7R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3694 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3695 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3696 #define CAN_F7R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3697 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3698 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3699
AnnaBridge 172:65be27845400 3700 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 172:65be27845400 3701 #define CAN_F8R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3702 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3703 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3704 #define CAN_F8R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3705 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3706 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3707 #define CAN_F8R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3708 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3709 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3710 #define CAN_F8R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3711 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3712 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3713 #define CAN_F8R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3714 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3715 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3716 #define CAN_F8R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3717 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3718 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3719 #define CAN_F8R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3720 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3721 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3722 #define CAN_F8R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3723 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3724 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3725 #define CAN_F8R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3726 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3727 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3728 #define CAN_F8R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3729 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3730 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3731 #define CAN_F8R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3732 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3733 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3734 #define CAN_F8R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3735 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3736 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3737 #define CAN_F8R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3738 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3739 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3740 #define CAN_F8R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3741 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3742 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3743 #define CAN_F8R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3744 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3745 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3746 #define CAN_F8R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3747 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3748 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3749 #define CAN_F8R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3750 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3751 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3752 #define CAN_F8R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3753 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3754 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3755 #define CAN_F8R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3756 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3757 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3758 #define CAN_F8R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3759 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3760 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3761 #define CAN_F8R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3762 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3763 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3764 #define CAN_F8R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3765 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3766 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3767 #define CAN_F8R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3768 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3769 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3770 #define CAN_F8R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3771 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3772 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3773 #define CAN_F8R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3774 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3775 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3776 #define CAN_F8R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3777 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3778 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3779 #define CAN_F8R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3780 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3781 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3782 #define CAN_F8R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3783 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3784 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3785 #define CAN_F8R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3786 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3787 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3788 #define CAN_F8R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3789 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3790 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3791 #define CAN_F8R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3792 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3793 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3794 #define CAN_F8R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3795 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3796 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3797
AnnaBridge 172:65be27845400 3798 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 172:65be27845400 3799 #define CAN_F9R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3800 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3801 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3802 #define CAN_F9R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3803 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3804 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3805 #define CAN_F9R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3806 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3807 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3808 #define CAN_F9R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3809 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3810 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3811 #define CAN_F9R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3812 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3813 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3814 #define CAN_F9R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3815 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3816 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3817 #define CAN_F9R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3818 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3819 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3820 #define CAN_F9R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3821 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3822 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3823 #define CAN_F9R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3824 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3825 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3826 #define CAN_F9R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3827 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3828 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3829 #define CAN_F9R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3830 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3831 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3832 #define CAN_F9R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3833 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3834 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3835 #define CAN_F9R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3836 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3837 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3838 #define CAN_F9R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3839 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3840 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3841 #define CAN_F9R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3842 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3843 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3844 #define CAN_F9R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3845 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3846 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3847 #define CAN_F9R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3848 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3849 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3850 #define CAN_F9R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3851 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3852 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3853 #define CAN_F9R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3854 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3855 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3856 #define CAN_F9R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3857 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3858 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3859 #define CAN_F9R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3860 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3861 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3862 #define CAN_F9R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3863 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3864 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3865 #define CAN_F9R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3866 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3867 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3868 #define CAN_F9R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3869 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3870 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3871 #define CAN_F9R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3872 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3873 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3874 #define CAN_F9R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3875 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3876 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3877 #define CAN_F9R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3878 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3879 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3880 #define CAN_F9R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3881 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3882 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3883 #define CAN_F9R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3884 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3885 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3886 #define CAN_F9R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3887 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3888 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3889 #define CAN_F9R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3890 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3891 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3892 #define CAN_F9R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3893 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3894 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3895
AnnaBridge 172:65be27845400 3896 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 172:65be27845400 3897 #define CAN_F10R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3898 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3899 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3900 #define CAN_F10R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3901 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3902 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 3903 #define CAN_F10R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 3904 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3905 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 3906 #define CAN_F10R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 3907 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3908 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 3909 #define CAN_F10R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 3910 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3911 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 3912 #define CAN_F10R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 3913 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3914 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 3915 #define CAN_F10R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 3916 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3917 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 3918 #define CAN_F10R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 3919 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3920 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 3921 #define CAN_F10R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 3922 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3923 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 3924 #define CAN_F10R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 3925 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3926 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 3927 #define CAN_F10R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 3928 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3929 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 3930 #define CAN_F10R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 3931 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3932 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 3933 #define CAN_F10R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 3934 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3935 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 3936 #define CAN_F10R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 3937 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3938 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 3939 #define CAN_F10R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 3940 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3941 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 3942 #define CAN_F10R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 3943 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3944 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 3945 #define CAN_F10R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 3946 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3947 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 3948 #define CAN_F10R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 3949 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3950 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 3951 #define CAN_F10R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 3952 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3953 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 3954 #define CAN_F10R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 3955 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3956 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 3957 #define CAN_F10R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 3958 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3959 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 3960 #define CAN_F10R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 3961 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3962 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 3963 #define CAN_F10R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 3964 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3965 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 3966 #define CAN_F10R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 3967 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3968 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 3969 #define CAN_F10R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 3970 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3971 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 3972 #define CAN_F10R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 3973 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3974 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 3975 #define CAN_F10R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 3976 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3977 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 3978 #define CAN_F10R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 3979 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3980 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 3981 #define CAN_F10R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 3982 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3983 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 3984 #define CAN_F10R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 3985 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3986 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 3987 #define CAN_F10R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 3988 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3989 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 3990 #define CAN_F10R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 3991 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3992 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 3993
AnnaBridge 172:65be27845400 3994 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 172:65be27845400 3995 #define CAN_F11R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 3996 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3997 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 3998 #define CAN_F11R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 3999 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4000 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4001 #define CAN_F11R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4002 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4003 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4004 #define CAN_F11R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4005 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4006 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4007 #define CAN_F11R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4008 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4009 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4010 #define CAN_F11R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4011 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4012 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4013 #define CAN_F11R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4014 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4015 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4016 #define CAN_F11R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4017 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4018 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4019 #define CAN_F11R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4020 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4021 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4022 #define CAN_F11R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4023 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4024 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4025 #define CAN_F11R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4026 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4027 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4028 #define CAN_F11R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4029 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4030 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4031 #define CAN_F11R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4032 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4033 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4034 #define CAN_F11R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4035 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4036 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4037 #define CAN_F11R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4038 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4039 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4040 #define CAN_F11R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4041 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4042 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4043 #define CAN_F11R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4044 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4045 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4046 #define CAN_F11R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4047 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4048 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4049 #define CAN_F11R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4050 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4051 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4052 #define CAN_F11R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4053 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4054 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4055 #define CAN_F11R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4056 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4057 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4058 #define CAN_F11R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4059 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4060 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4061 #define CAN_F11R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4062 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4063 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4064 #define CAN_F11R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4065 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4066 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4067 #define CAN_F11R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4068 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4069 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4070 #define CAN_F11R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4071 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4072 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4073 #define CAN_F11R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4074 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4075 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4076 #define CAN_F11R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4077 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4078 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4079 #define CAN_F11R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4080 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4081 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4082 #define CAN_F11R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4083 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4084 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4085 #define CAN_F11R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4086 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4087 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4088 #define CAN_F11R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4089 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4090 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4091
AnnaBridge 172:65be27845400 4092 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 172:65be27845400 4093 #define CAN_F12R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4094 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4095 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4096 #define CAN_F12R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4097 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4098 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4099 #define CAN_F12R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4100 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4101 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4102 #define CAN_F12R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4103 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4104 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4105 #define CAN_F12R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4106 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4107 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4108 #define CAN_F12R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4109 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4110 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4111 #define CAN_F12R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4112 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4113 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4114 #define CAN_F12R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4115 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4116 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4117 #define CAN_F12R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4118 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4119 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4120 #define CAN_F12R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4121 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4122 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4123 #define CAN_F12R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4124 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4125 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4126 #define CAN_F12R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4127 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4128 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4129 #define CAN_F12R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4130 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4131 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4132 #define CAN_F12R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4133 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4134 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4135 #define CAN_F12R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4136 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4137 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4138 #define CAN_F12R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4139 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4140 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4141 #define CAN_F12R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4142 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4143 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4144 #define CAN_F12R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4145 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4146 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4147 #define CAN_F12R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4148 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4149 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4150 #define CAN_F12R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4151 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4152 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4153 #define CAN_F12R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4154 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4155 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4156 #define CAN_F12R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4157 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4158 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4159 #define CAN_F12R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4160 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4161 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4162 #define CAN_F12R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4163 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4164 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4165 #define CAN_F12R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4166 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4167 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4168 #define CAN_F12R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4169 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4170 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4171 #define CAN_F12R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4172 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4173 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4174 #define CAN_F12R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4175 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4176 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4177 #define CAN_F12R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4178 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4179 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4180 #define CAN_F12R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4181 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4182 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4183 #define CAN_F12R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4184 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4185 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4186 #define CAN_F12R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4187 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4188 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4189
AnnaBridge 172:65be27845400 4190 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 172:65be27845400 4191 #define CAN_F13R1_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4192 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4193 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4194 #define CAN_F13R1_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4195 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4196 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4197 #define CAN_F13R1_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4198 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4199 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4200 #define CAN_F13R1_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4201 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4202 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4203 #define CAN_F13R1_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4204 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4205 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4206 #define CAN_F13R1_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4207 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4208 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4209 #define CAN_F13R1_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4210 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4211 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4212 #define CAN_F13R1_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4213 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4214 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4215 #define CAN_F13R1_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4216 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4217 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4218 #define CAN_F13R1_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4219 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4220 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4221 #define CAN_F13R1_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4222 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4223 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4224 #define CAN_F13R1_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4225 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4226 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4227 #define CAN_F13R1_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4228 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4229 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4230 #define CAN_F13R1_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4231 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4232 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4233 #define CAN_F13R1_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4234 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4235 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4236 #define CAN_F13R1_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4237 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4238 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4239 #define CAN_F13R1_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4240 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4241 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4242 #define CAN_F13R1_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4243 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4244 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4245 #define CAN_F13R1_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4246 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4247 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4248 #define CAN_F13R1_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4249 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4250 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4251 #define CAN_F13R1_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4252 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4253 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4254 #define CAN_F13R1_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4255 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4256 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4257 #define CAN_F13R1_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4258 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4259 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4260 #define CAN_F13R1_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4261 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4262 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4263 #define CAN_F13R1_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4264 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4265 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4266 #define CAN_F13R1_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4267 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4268 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4269 #define CAN_F13R1_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4270 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4271 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4272 #define CAN_F13R1_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4273 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4274 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4275 #define CAN_F13R1_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4276 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4277 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4278 #define CAN_F13R1_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4279 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4280 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4281 #define CAN_F13R1_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4282 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4283 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4284 #define CAN_F13R1_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4285 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4286 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4287
AnnaBridge 172:65be27845400 4288 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 172:65be27845400 4289 #define CAN_F0R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4290 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4291 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4292 #define CAN_F0R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4293 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4294 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4295 #define CAN_F0R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4296 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4297 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4298 #define CAN_F0R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4299 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4300 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4301 #define CAN_F0R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4302 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4303 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4304 #define CAN_F0R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4305 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4306 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4307 #define CAN_F0R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4308 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4309 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4310 #define CAN_F0R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4311 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4312 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4313 #define CAN_F0R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4314 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4315 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4316 #define CAN_F0R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4317 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4318 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4319 #define CAN_F0R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4320 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4321 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4322 #define CAN_F0R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4323 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4324 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4325 #define CAN_F0R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4326 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4327 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4328 #define CAN_F0R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4329 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4330 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4331 #define CAN_F0R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4332 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4333 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4334 #define CAN_F0R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4335 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4336 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4337 #define CAN_F0R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4338 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4339 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4340 #define CAN_F0R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4341 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4342 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4343 #define CAN_F0R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4344 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4345 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4346 #define CAN_F0R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4347 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4348 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4349 #define CAN_F0R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4350 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4351 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4352 #define CAN_F0R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4353 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4354 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4355 #define CAN_F0R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4356 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4357 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4358 #define CAN_F0R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4359 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4360 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4361 #define CAN_F0R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4362 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4363 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4364 #define CAN_F0R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4365 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4366 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4367 #define CAN_F0R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4368 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4369 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4370 #define CAN_F0R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4371 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4372 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4373 #define CAN_F0R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4374 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4375 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4376 #define CAN_F0R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4377 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4378 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4379 #define CAN_F0R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4380 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4381 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4382 #define CAN_F0R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4383 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4384 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4385
AnnaBridge 172:65be27845400 4386 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 172:65be27845400 4387 #define CAN_F1R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4388 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4389 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4390 #define CAN_F1R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4391 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4392 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4393 #define CAN_F1R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4394 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4395 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4396 #define CAN_F1R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4397 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4398 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4399 #define CAN_F1R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4400 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4401 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4402 #define CAN_F1R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4403 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4404 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4405 #define CAN_F1R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4406 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4407 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4408 #define CAN_F1R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4409 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4410 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4411 #define CAN_F1R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4412 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4413 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4414 #define CAN_F1R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4415 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4416 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4417 #define CAN_F1R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4418 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4419 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4420 #define CAN_F1R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4421 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4422 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4423 #define CAN_F1R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4424 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4425 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4426 #define CAN_F1R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4427 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4428 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4429 #define CAN_F1R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4430 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4431 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4432 #define CAN_F1R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4433 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4434 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4435 #define CAN_F1R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4436 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4437 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4438 #define CAN_F1R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4439 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4440 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4441 #define CAN_F1R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4442 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4443 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4444 #define CAN_F1R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4445 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4446 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4447 #define CAN_F1R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4448 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4449 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4450 #define CAN_F1R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4451 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4452 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4453 #define CAN_F1R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4454 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4455 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4456 #define CAN_F1R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4457 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4458 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4459 #define CAN_F1R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4460 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4461 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4462 #define CAN_F1R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4463 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4464 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4465 #define CAN_F1R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4466 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4467 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4468 #define CAN_F1R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4469 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4470 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4471 #define CAN_F1R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4472 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4473 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4474 #define CAN_F1R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4475 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4476 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4477 #define CAN_F1R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4478 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4479 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4480 #define CAN_F1R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4481 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4482 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4483
AnnaBridge 172:65be27845400 4484 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 172:65be27845400 4485 #define CAN_F2R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4486 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4487 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4488 #define CAN_F2R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4489 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4490 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4491 #define CAN_F2R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4492 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4493 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4494 #define CAN_F2R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4495 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4496 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4497 #define CAN_F2R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4498 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4499 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4500 #define CAN_F2R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4501 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4502 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4503 #define CAN_F2R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4504 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4505 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4506 #define CAN_F2R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4507 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4508 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4509 #define CAN_F2R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4510 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4511 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4512 #define CAN_F2R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4513 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4514 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4515 #define CAN_F2R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4516 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4517 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4518 #define CAN_F2R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4519 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4520 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4521 #define CAN_F2R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4522 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4523 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4524 #define CAN_F2R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4525 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4526 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4527 #define CAN_F2R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4528 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4529 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4530 #define CAN_F2R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4531 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4532 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4533 #define CAN_F2R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4534 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4535 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4536 #define CAN_F2R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4537 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4538 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4539 #define CAN_F2R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4540 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4541 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4542 #define CAN_F2R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4543 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4544 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4545 #define CAN_F2R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4546 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4547 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4548 #define CAN_F2R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4549 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4550 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4551 #define CAN_F2R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4552 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4553 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4554 #define CAN_F2R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4555 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4556 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4557 #define CAN_F2R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4558 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4559 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4560 #define CAN_F2R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4561 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4562 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4563 #define CAN_F2R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4564 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4565 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4566 #define CAN_F2R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4567 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4568 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4569 #define CAN_F2R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4570 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4571 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4572 #define CAN_F2R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4573 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4574 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4575 #define CAN_F2R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4576 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4577 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4578 #define CAN_F2R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4579 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4580 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4581
AnnaBridge 172:65be27845400 4582 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 172:65be27845400 4583 #define CAN_F3R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4584 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4585 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4586 #define CAN_F3R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4587 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4588 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4589 #define CAN_F3R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4590 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4591 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4592 #define CAN_F3R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4593 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4594 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4595 #define CAN_F3R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4596 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4597 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4598 #define CAN_F3R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4599 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4600 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4601 #define CAN_F3R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4602 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4603 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4604 #define CAN_F3R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4605 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4606 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4607 #define CAN_F3R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4608 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4609 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4610 #define CAN_F3R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4611 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4612 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4613 #define CAN_F3R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4614 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4615 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4616 #define CAN_F3R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4617 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4618 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4619 #define CAN_F3R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4620 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4621 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4622 #define CAN_F3R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4623 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4624 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4625 #define CAN_F3R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4626 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4627 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4628 #define CAN_F3R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4629 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4630 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4631 #define CAN_F3R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4632 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4633 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4634 #define CAN_F3R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4635 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4636 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4637 #define CAN_F3R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4638 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4639 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4640 #define CAN_F3R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4641 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4642 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4643 #define CAN_F3R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4644 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4645 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4646 #define CAN_F3R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4647 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4648 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4649 #define CAN_F3R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4650 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4651 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4652 #define CAN_F3R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4653 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4654 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4655 #define CAN_F3R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4656 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4657 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4658 #define CAN_F3R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4659 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4660 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4661 #define CAN_F3R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4662 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4663 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4664 #define CAN_F3R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4665 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4666 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4667 #define CAN_F3R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4668 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4669 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4670 #define CAN_F3R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4671 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4672 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4673 #define CAN_F3R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4674 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4675 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4676 #define CAN_F3R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4677 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4678 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4679
AnnaBridge 172:65be27845400 4680 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 172:65be27845400 4681 #define CAN_F4R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4682 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4683 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4684 #define CAN_F4R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4685 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4686 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4687 #define CAN_F4R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4688 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4689 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4690 #define CAN_F4R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4691 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4692 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4693 #define CAN_F4R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4694 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4695 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4696 #define CAN_F4R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4697 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4698 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4699 #define CAN_F4R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4700 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4701 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4702 #define CAN_F4R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4703 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4704 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4705 #define CAN_F4R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4706 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4707 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4708 #define CAN_F4R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4709 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4710 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4711 #define CAN_F4R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4712 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4713 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4714 #define CAN_F4R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4715 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4716 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4717 #define CAN_F4R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4718 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4719 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4720 #define CAN_F4R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4721 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4722 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4723 #define CAN_F4R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4724 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4725 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4726 #define CAN_F4R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4727 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4728 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4729 #define CAN_F4R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4730 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4731 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4732 #define CAN_F4R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4733 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4734 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4735 #define CAN_F4R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4736 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4737 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4738 #define CAN_F4R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4739 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4740 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4741 #define CAN_F4R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4742 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4743 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4744 #define CAN_F4R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4745 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4746 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4747 #define CAN_F4R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4748 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4749 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4750 #define CAN_F4R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4751 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4752 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4753 #define CAN_F4R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4754 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4755 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4756 #define CAN_F4R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4757 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4758 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4759 #define CAN_F4R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4760 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4761 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4762 #define CAN_F4R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4763 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4764 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4765 #define CAN_F4R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4766 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4767 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4768 #define CAN_F4R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4769 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4770 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4771 #define CAN_F4R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4772 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4773 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4774 #define CAN_F4R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4775 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4776 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4777
AnnaBridge 172:65be27845400 4778 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 172:65be27845400 4779 #define CAN_F5R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4780 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4781 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4782 #define CAN_F5R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4783 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4784 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4785 #define CAN_F5R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4786 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4787 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4788 #define CAN_F5R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4789 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4790 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4791 #define CAN_F5R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4792 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4793 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4794 #define CAN_F5R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4795 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4796 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4797 #define CAN_F5R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4798 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4799 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4800 #define CAN_F5R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4801 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4802 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4803 #define CAN_F5R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4804 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4805 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4806 #define CAN_F5R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4807 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4808 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4809 #define CAN_F5R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4810 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4811 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4812 #define CAN_F5R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4813 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4814 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4815 #define CAN_F5R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4816 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4817 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4818 #define CAN_F5R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4819 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4820 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4821 #define CAN_F5R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4822 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4823 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4824 #define CAN_F5R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4825 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4826 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4827 #define CAN_F5R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4828 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4829 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4830 #define CAN_F5R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4831 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4832 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4833 #define CAN_F5R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4834 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4835 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4836 #define CAN_F5R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4837 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4838 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4839 #define CAN_F5R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4840 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4841 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4842 #define CAN_F5R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4843 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4844 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4845 #define CAN_F5R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4846 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4847 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4848 #define CAN_F5R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4849 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4850 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4851 #define CAN_F5R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4852 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4853 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4854 #define CAN_F5R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4855 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4856 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4857 #define CAN_F5R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4858 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4859 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4860 #define CAN_F5R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4861 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4862 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4863 #define CAN_F5R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4864 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4865 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4866 #define CAN_F5R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4867 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4868 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4869 #define CAN_F5R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4870 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4871 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4872 #define CAN_F5R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4873 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4874 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4875
AnnaBridge 172:65be27845400 4876 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 172:65be27845400 4877 #define CAN_F6R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4878 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4879 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4880 #define CAN_F6R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4881 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4882 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4883 #define CAN_F6R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4884 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4885 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4886 #define CAN_F6R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4887 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4888 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4889 #define CAN_F6R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4890 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4891 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4892 #define CAN_F6R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4893 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4894 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4895 #define CAN_F6R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4896 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4897 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4898 #define CAN_F6R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4899 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4900 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4901 #define CAN_F6R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 4902 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4903 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 4904 #define CAN_F6R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 4905 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4906 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 4907 #define CAN_F6R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 4908 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4909 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 4910 #define CAN_F6R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 4911 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4912 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 4913 #define CAN_F6R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 4914 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4915 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 4916 #define CAN_F6R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 4917 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4918 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 4919 #define CAN_F6R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 4920 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4921 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 4922 #define CAN_F6R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 4923 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4924 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 4925 #define CAN_F6R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 4926 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4927 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 4928 #define CAN_F6R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 4929 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4930 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 4931 #define CAN_F6R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 4932 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4933 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 4934 #define CAN_F6R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 4935 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4936 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 4937 #define CAN_F6R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 4938 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4939 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 4940 #define CAN_F6R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 4941 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4942 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 4943 #define CAN_F6R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 4944 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4945 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 4946 #define CAN_F6R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 4947 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4948 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 4949 #define CAN_F6R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 4950 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4951 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 4952 #define CAN_F6R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 4953 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4954 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 4955 #define CAN_F6R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 4956 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4957 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 4958 #define CAN_F6R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 4959 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4960 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 4961 #define CAN_F6R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 4962 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4963 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 4964 #define CAN_F6R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 4965 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4966 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 4967 #define CAN_F6R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 4968 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4969 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 4970 #define CAN_F6R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 4971 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4972 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 4973
AnnaBridge 172:65be27845400 4974 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 172:65be27845400 4975 #define CAN_F7R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 4976 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4977 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 4978 #define CAN_F7R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 4979 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4980 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 4981 #define CAN_F7R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 4982 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4983 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 4984 #define CAN_F7R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 4985 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4986 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 4987 #define CAN_F7R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 4988 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4989 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 4990 #define CAN_F7R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 4991 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4992 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 4993 #define CAN_F7R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 4994 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4995 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 4996 #define CAN_F7R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 4997 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4998 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 4999 #define CAN_F7R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 5000 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5001 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 5002 #define CAN_F7R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 5003 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5004 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 5005 #define CAN_F7R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 5006 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5007 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 5008 #define CAN_F7R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 5009 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5010 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 5011 #define CAN_F7R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 5012 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5013 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 5014 #define CAN_F7R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 5015 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5016 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 5017 #define CAN_F7R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 5018 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5019 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 5020 #define CAN_F7R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 5021 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5022 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 5023 #define CAN_F7R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 5024 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5025 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 5026 #define CAN_F7R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 5027 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5028 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 5029 #define CAN_F7R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 5030 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5031 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 5032 #define CAN_F7R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 5033 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5034 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 5035 #define CAN_F7R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 5036 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5037 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 5038 #define CAN_F7R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 5039 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5040 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 5041 #define CAN_F7R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 5042 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5043 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 5044 #define CAN_F7R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 5045 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5046 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 5047 #define CAN_F7R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 5048 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5049 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 5050 #define CAN_F7R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 5051 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5052 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 5053 #define CAN_F7R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 5054 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5055 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 5056 #define CAN_F7R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 5057 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5058 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 5059 #define CAN_F7R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 5060 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5061 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 5062 #define CAN_F7R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 5063 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5064 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 5065 #define CAN_F7R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 5066 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5067 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 5068 #define CAN_F7R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 5069 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5070 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 5071
AnnaBridge 172:65be27845400 5072 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 172:65be27845400 5073 #define CAN_F8R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 5074 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5075 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 5076 #define CAN_F8R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 5077 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5078 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 5079 #define CAN_F8R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 5080 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5081 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 5082 #define CAN_F8R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 5083 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5084 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 5085 #define CAN_F8R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 5086 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5087 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 5088 #define CAN_F8R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 5089 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5090 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 5091 #define CAN_F8R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 5092 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5093 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 5094 #define CAN_F8R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 5095 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5096 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 5097 #define CAN_F8R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 5098 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5099 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 5100 #define CAN_F8R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 5101 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5102 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 5103 #define CAN_F8R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 5104 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5105 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 5106 #define CAN_F8R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 5107 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5108 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 5109 #define CAN_F8R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 5110 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5111 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 5112 #define CAN_F8R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 5113 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5114 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 5115 #define CAN_F8R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 5116 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5117 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 5118 #define CAN_F8R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 5119 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5120 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 5121 #define CAN_F8R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 5122 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5123 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 5124 #define CAN_F8R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 5125 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5126 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 5127 #define CAN_F8R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 5128 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5129 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 5130 #define CAN_F8R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 5131 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5132 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 5133 #define CAN_F8R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 5134 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5135 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 5136 #define CAN_F8R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 5137 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5138 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 5139 #define CAN_F8R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 5140 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5141 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 5142 #define CAN_F8R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 5143 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5144 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 5145 #define CAN_F8R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 5146 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5147 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 5148 #define CAN_F8R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 5149 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5150 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 5151 #define CAN_F8R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 5152 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5153 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 5154 #define CAN_F8R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 5155 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5156 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 5157 #define CAN_F8R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 5158 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5159 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 5160 #define CAN_F8R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 5161 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5162 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 5163 #define CAN_F8R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 5164 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5165 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 5166 #define CAN_F8R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 5167 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5168 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 5169
AnnaBridge 172:65be27845400 5170 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 172:65be27845400 5171 #define CAN_F9R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 5172 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5173 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 5174 #define CAN_F9R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 5175 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5176 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 5177 #define CAN_F9R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 5178 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5179 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 5180 #define CAN_F9R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 5181 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5182 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 5183 #define CAN_F9R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 5184 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5185 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 5186 #define CAN_F9R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 5187 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5188 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 5189 #define CAN_F9R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 5190 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5191 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 5192 #define CAN_F9R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 5193 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5194 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 5195 #define CAN_F9R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 5196 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5197 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 5198 #define CAN_F9R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 5199 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5200 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 5201 #define CAN_F9R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 5202 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5203 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 5204 #define CAN_F9R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 5205 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5206 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 5207 #define CAN_F9R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 5208 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5209 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 5210 #define CAN_F9R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 5211 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5212 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 5213 #define CAN_F9R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 5214 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5215 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 5216 #define CAN_F9R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 5217 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5218 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 5219 #define CAN_F9R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 5220 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5221 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 5222 #define CAN_F9R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 5223 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5224 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 5225 #define CAN_F9R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 5226 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5227 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 5228 #define CAN_F9R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 5229 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5230 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 5231 #define CAN_F9R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 5232 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5233 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 5234 #define CAN_F9R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 5235 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5236 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 5237 #define CAN_F9R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 5238 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5239 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 5240 #define CAN_F9R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 5241 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5242 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 5243 #define CAN_F9R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 5244 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5245 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 5246 #define CAN_F9R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 5247 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5248 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 5249 #define CAN_F9R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 5250 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5251 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 5252 #define CAN_F9R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 5253 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5254 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 5255 #define CAN_F9R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 5256 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5257 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 5258 #define CAN_F9R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 5259 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5260 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 5261 #define CAN_F9R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 5262 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5263 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 5264 #define CAN_F9R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 5265 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5266 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 5267
AnnaBridge 172:65be27845400 5268 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 172:65be27845400 5269 #define CAN_F10R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 5270 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5271 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 5272 #define CAN_F10R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 5273 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5274 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 5275 #define CAN_F10R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 5276 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5277 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 5278 #define CAN_F10R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 5279 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5280 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 5281 #define CAN_F10R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 5282 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5283 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 5284 #define CAN_F10R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 5285 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5286 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 5287 #define CAN_F10R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 5288 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5289 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 5290 #define CAN_F10R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 5291 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5292 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 5293 #define CAN_F10R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 5294 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5295 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 5296 #define CAN_F10R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 5297 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5298 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 5299 #define CAN_F10R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 5300 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5301 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 5302 #define CAN_F10R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 5303 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5304 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 5305 #define CAN_F10R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 5306 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5307 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 5308 #define CAN_F10R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 5309 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5310 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 5311 #define CAN_F10R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 5312 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5313 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 5314 #define CAN_F10R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 5315 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5316 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 5317 #define CAN_F10R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 5318 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5319 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 5320 #define CAN_F10R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 5321 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5322 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 5323 #define CAN_F10R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 5324 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5325 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 5326 #define CAN_F10R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 5327 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5328 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 5329 #define CAN_F10R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 5330 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5331 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 5332 #define CAN_F10R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 5333 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5334 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 5335 #define CAN_F10R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 5336 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5337 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 5338 #define CAN_F10R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 5339 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5340 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 5341 #define CAN_F10R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 5342 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5343 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 5344 #define CAN_F10R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 5345 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5346 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 5347 #define CAN_F10R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 5348 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5349 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 5350 #define CAN_F10R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 5351 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5352 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 5353 #define CAN_F10R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 5354 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5355 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 5356 #define CAN_F10R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 5357 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5358 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 5359 #define CAN_F10R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 5360 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5361 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 5362 #define CAN_F10R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 5363 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5364 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 5365
AnnaBridge 172:65be27845400 5366 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 172:65be27845400 5367 #define CAN_F11R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 5368 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5369 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 5370 #define CAN_F11R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 5371 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5372 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 5373 #define CAN_F11R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 5374 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5375 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 5376 #define CAN_F11R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 5377 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5378 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 5379 #define CAN_F11R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 5380 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5381 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 5382 #define CAN_F11R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 5383 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5384 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 5385 #define CAN_F11R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 5386 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5387 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 5388 #define CAN_F11R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 5389 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5390 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 5391 #define CAN_F11R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 5392 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5393 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 5394 #define CAN_F11R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 5395 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5396 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 5397 #define CAN_F11R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 5398 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5399 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 5400 #define CAN_F11R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 5401 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5402 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 5403 #define CAN_F11R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 5404 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5405 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 5406 #define CAN_F11R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 5407 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5408 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 5409 #define CAN_F11R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 5410 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5411 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 5412 #define CAN_F11R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 5413 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5414 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 5415 #define CAN_F11R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 5416 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5417 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 5418 #define CAN_F11R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 5419 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5420 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 5421 #define CAN_F11R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 5422 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5423 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 5424 #define CAN_F11R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 5425 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5426 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 5427 #define CAN_F11R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 5428 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5429 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 5430 #define CAN_F11R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 5431 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5432 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 5433 #define CAN_F11R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 5434 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5435 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 5436 #define CAN_F11R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 5437 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5438 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 5439 #define CAN_F11R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 5440 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5441 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 5442 #define CAN_F11R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 5443 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5444 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 5445 #define CAN_F11R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 5446 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5447 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 5448 #define CAN_F11R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 5449 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5450 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 5451 #define CAN_F11R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 5452 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5453 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 5454 #define CAN_F11R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 5455 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5456 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 5457 #define CAN_F11R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 5458 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5459 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 5460 #define CAN_F11R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 5461 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5462 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 5463
AnnaBridge 172:65be27845400 5464 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 172:65be27845400 5465 #define CAN_F12R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 5466 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5467 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 5468 #define CAN_F12R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 5469 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5470 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 5471 #define CAN_F12R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 5472 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5473 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 5474 #define CAN_F12R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 5475 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5476 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 5477 #define CAN_F12R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 5478 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5479 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 5480 #define CAN_F12R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 5481 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5482 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 5483 #define CAN_F12R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 5484 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5485 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 5486 #define CAN_F12R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 5487 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5488 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 5489 #define CAN_F12R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 5490 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5491 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 5492 #define CAN_F12R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 5493 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5494 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 5495 #define CAN_F12R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 5496 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5497 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 5498 #define CAN_F12R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 5499 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5500 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 5501 #define CAN_F12R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 5502 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5503 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 5504 #define CAN_F12R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 5505 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5506 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 5507 #define CAN_F12R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 5508 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5509 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 5510 #define CAN_F12R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 5511 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5512 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 5513 #define CAN_F12R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 5514 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5515 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 5516 #define CAN_F12R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 5517 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5518 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 5519 #define CAN_F12R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 5520 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5521 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 5522 #define CAN_F12R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 5523 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5524 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 5525 #define CAN_F12R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 5526 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5527 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 5528 #define CAN_F12R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 5529 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5530 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 5531 #define CAN_F12R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 5532 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5533 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 5534 #define CAN_F12R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 5535 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5536 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 5537 #define CAN_F12R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 5538 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5539 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 5540 #define CAN_F12R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 5541 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5542 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 5543 #define CAN_F12R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 5544 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5545 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 5546 #define CAN_F12R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 5547 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5548 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 5549 #define CAN_F12R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 5550 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5551 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 5552 #define CAN_F12R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 5553 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5554 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 5555 #define CAN_F12R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 5556 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5557 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 5558 #define CAN_F12R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 5559 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5560 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 5561
AnnaBridge 172:65be27845400 5562 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 172:65be27845400 5563 #define CAN_F13R2_FB0_Pos (0U)
AnnaBridge 172:65be27845400 5564 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5565 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 172:65be27845400 5566 #define CAN_F13R2_FB1_Pos (1U)
AnnaBridge 172:65be27845400 5567 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5568 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 172:65be27845400 5569 #define CAN_F13R2_FB2_Pos (2U)
AnnaBridge 172:65be27845400 5570 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5571 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 172:65be27845400 5572 #define CAN_F13R2_FB3_Pos (3U)
AnnaBridge 172:65be27845400 5573 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5574 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 172:65be27845400 5575 #define CAN_F13R2_FB4_Pos (4U)
AnnaBridge 172:65be27845400 5576 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5577 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 172:65be27845400 5578 #define CAN_F13R2_FB5_Pos (5U)
AnnaBridge 172:65be27845400 5579 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5580 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 172:65be27845400 5581 #define CAN_F13R2_FB6_Pos (6U)
AnnaBridge 172:65be27845400 5582 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5583 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 172:65be27845400 5584 #define CAN_F13R2_FB7_Pos (7U)
AnnaBridge 172:65be27845400 5585 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5586 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 172:65be27845400 5587 #define CAN_F13R2_FB8_Pos (8U)
AnnaBridge 172:65be27845400 5588 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5589 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 172:65be27845400 5590 #define CAN_F13R2_FB9_Pos (9U)
AnnaBridge 172:65be27845400 5591 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5592 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 172:65be27845400 5593 #define CAN_F13R2_FB10_Pos (10U)
AnnaBridge 172:65be27845400 5594 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5595 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 172:65be27845400 5596 #define CAN_F13R2_FB11_Pos (11U)
AnnaBridge 172:65be27845400 5597 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5598 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 172:65be27845400 5599 #define CAN_F13R2_FB12_Pos (12U)
AnnaBridge 172:65be27845400 5600 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5601 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 172:65be27845400 5602 #define CAN_F13R2_FB13_Pos (13U)
AnnaBridge 172:65be27845400 5603 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5604 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 172:65be27845400 5605 #define CAN_F13R2_FB14_Pos (14U)
AnnaBridge 172:65be27845400 5606 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5607 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 172:65be27845400 5608 #define CAN_F13R2_FB15_Pos (15U)
AnnaBridge 172:65be27845400 5609 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5610 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 172:65be27845400 5611 #define CAN_F13R2_FB16_Pos (16U)
AnnaBridge 172:65be27845400 5612 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5613 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 172:65be27845400 5614 #define CAN_F13R2_FB17_Pos (17U)
AnnaBridge 172:65be27845400 5615 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5616 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 172:65be27845400 5617 #define CAN_F13R2_FB18_Pos (18U)
AnnaBridge 172:65be27845400 5618 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5619 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 172:65be27845400 5620 #define CAN_F13R2_FB19_Pos (19U)
AnnaBridge 172:65be27845400 5621 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5622 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 172:65be27845400 5623 #define CAN_F13R2_FB20_Pos (20U)
AnnaBridge 172:65be27845400 5624 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5625 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 172:65be27845400 5626 #define CAN_F13R2_FB21_Pos (21U)
AnnaBridge 172:65be27845400 5627 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5628 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 172:65be27845400 5629 #define CAN_F13R2_FB22_Pos (22U)
AnnaBridge 172:65be27845400 5630 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5631 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 172:65be27845400 5632 #define CAN_F13R2_FB23_Pos (23U)
AnnaBridge 172:65be27845400 5633 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5634 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 172:65be27845400 5635 #define CAN_F13R2_FB24_Pos (24U)
AnnaBridge 172:65be27845400 5636 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5637 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 172:65be27845400 5638 #define CAN_F13R2_FB25_Pos (25U)
AnnaBridge 172:65be27845400 5639 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5640 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 172:65be27845400 5641 #define CAN_F13R2_FB26_Pos (26U)
AnnaBridge 172:65be27845400 5642 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5643 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 172:65be27845400 5644 #define CAN_F13R2_FB27_Pos (27U)
AnnaBridge 172:65be27845400 5645 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5646 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 172:65be27845400 5647 #define CAN_F13R2_FB28_Pos (28U)
AnnaBridge 172:65be27845400 5648 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5649 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 172:65be27845400 5650 #define CAN_F13R2_FB29_Pos (29U)
AnnaBridge 172:65be27845400 5651 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5652 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 172:65be27845400 5653 #define CAN_F13R2_FB30_Pos (30U)
AnnaBridge 172:65be27845400 5654 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5655 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 172:65be27845400 5656 #define CAN_F13R2_FB31_Pos (31U)
AnnaBridge 172:65be27845400 5657 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5658 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
AnnaBridge 172:65be27845400 5659
AnnaBridge 172:65be27845400 5660 /******************************************************************************/
AnnaBridge 172:65be27845400 5661 /* */
AnnaBridge 172:65be27845400 5662 /* CRC calculation unit */
AnnaBridge 172:65be27845400 5663 /* */
AnnaBridge 172:65be27845400 5664 /******************************************************************************/
AnnaBridge 172:65be27845400 5665 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 172:65be27845400 5666 #define CRC_DR_DR_Pos (0U)
AnnaBridge 172:65be27845400 5667 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 5668 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 172:65be27845400 5669
AnnaBridge 172:65be27845400 5670
AnnaBridge 172:65be27845400 5671 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 172:65be27845400 5672 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 172:65be27845400 5673 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5674 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 172:65be27845400 5675
AnnaBridge 172:65be27845400 5676
AnnaBridge 172:65be27845400 5677 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 172:65be27845400 5678 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 172:65be27845400 5679 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5680 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
AnnaBridge 172:65be27845400 5681
AnnaBridge 172:65be27845400 5682 /******************************************************************************/
AnnaBridge 172:65be27845400 5683 /* */
AnnaBridge 172:65be27845400 5684 /* Crypto Processor */
AnnaBridge 172:65be27845400 5685 /* */
AnnaBridge 172:65be27845400 5686 /******************************************************************************/
AnnaBridge 172:65be27845400 5687 /******************* Bits definition for CRYP_CR register ********************/
AnnaBridge 172:65be27845400 5688 #define CRYP_CR_ALGODIR_Pos (2U)
AnnaBridge 172:65be27845400 5689 #define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5690 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
AnnaBridge 172:65be27845400 5691
AnnaBridge 172:65be27845400 5692 #define CRYP_CR_ALGOMODE_Pos (3U)
AnnaBridge 172:65be27845400 5693 #define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
AnnaBridge 172:65be27845400 5694 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
AnnaBridge 172:65be27845400 5695 #define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5696 #define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5697 #define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5698 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
AnnaBridge 172:65be27845400 5699 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
AnnaBridge 172:65be27845400 5700 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5701 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
AnnaBridge 172:65be27845400 5702 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
AnnaBridge 172:65be27845400 5703 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5704 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
AnnaBridge 172:65be27845400 5705 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
AnnaBridge 172:65be27845400 5706 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 5707 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
AnnaBridge 172:65be27845400 5708 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
AnnaBridge 172:65be27845400 5709 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5710 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
AnnaBridge 172:65be27845400 5711 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
AnnaBridge 172:65be27845400 5712 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
AnnaBridge 172:65be27845400 5713 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
AnnaBridge 172:65be27845400 5714 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
AnnaBridge 172:65be27845400 5715 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 5716 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
AnnaBridge 172:65be27845400 5717 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
AnnaBridge 172:65be27845400 5718 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 5719 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
AnnaBridge 172:65be27845400 5720
AnnaBridge 172:65be27845400 5721 #define CRYP_CR_DATATYPE_Pos (6U)
AnnaBridge 172:65be27845400 5722 #define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 5723 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
AnnaBridge 172:65be27845400 5724 #define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5725 #define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5726 #define CRYP_CR_KEYSIZE_Pos (8U)
AnnaBridge 172:65be27845400 5727 #define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 5728 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
AnnaBridge 172:65be27845400 5729 #define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5730 #define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5731 #define CRYP_CR_FFLUSH_Pos (14U)
AnnaBridge 172:65be27845400 5732 #define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5733 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
AnnaBridge 172:65be27845400 5734 #define CRYP_CR_CRYPEN_Pos (15U)
AnnaBridge 172:65be27845400 5735 #define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5736 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
AnnaBridge 172:65be27845400 5737
AnnaBridge 172:65be27845400 5738 #define CRYP_CR_GCM_CCMPH_Pos (16U)
AnnaBridge 172:65be27845400 5739 #define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 5740 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
AnnaBridge 172:65be27845400 5741 #define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5742 #define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5743 #define CRYP_CR_ALGOMODE_3 0x00080000U
AnnaBridge 172:65be27845400 5744
AnnaBridge 172:65be27845400 5745 /****************** Bits definition for CRYP_SR register *********************/
AnnaBridge 172:65be27845400 5746 #define CRYP_SR_IFEM_Pos (0U)
AnnaBridge 172:65be27845400 5747 #define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5748 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
AnnaBridge 172:65be27845400 5749 #define CRYP_SR_IFNF_Pos (1U)
AnnaBridge 172:65be27845400 5750 #define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5751 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
AnnaBridge 172:65be27845400 5752 #define CRYP_SR_OFNE_Pos (2U)
AnnaBridge 172:65be27845400 5753 #define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5754 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
AnnaBridge 172:65be27845400 5755 #define CRYP_SR_OFFU_Pos (3U)
AnnaBridge 172:65be27845400 5756 #define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5757 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
AnnaBridge 172:65be27845400 5758 #define CRYP_SR_BUSY_Pos (4U)
AnnaBridge 172:65be27845400 5759 #define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5760 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
AnnaBridge 172:65be27845400 5761 /****************** Bits definition for CRYP_DMACR register ******************/
AnnaBridge 172:65be27845400 5762 #define CRYP_DMACR_DIEN_Pos (0U)
AnnaBridge 172:65be27845400 5763 #define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5764 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
AnnaBridge 172:65be27845400 5765 #define CRYP_DMACR_DOEN_Pos (1U)
AnnaBridge 172:65be27845400 5766 #define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5767 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
AnnaBridge 172:65be27845400 5768 /***************** Bits definition for CRYP_IMSCR register ******************/
AnnaBridge 172:65be27845400 5769 #define CRYP_IMSCR_INIM_Pos (0U)
AnnaBridge 172:65be27845400 5770 #define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5771 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
AnnaBridge 172:65be27845400 5772 #define CRYP_IMSCR_OUTIM_Pos (1U)
AnnaBridge 172:65be27845400 5773 #define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5774 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
AnnaBridge 172:65be27845400 5775 /****************** Bits definition for CRYP_RISR register *******************/
AnnaBridge 172:65be27845400 5776 #define CRYP_RISR_OUTRIS_Pos (0U)
AnnaBridge 172:65be27845400 5777 #define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5778 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
AnnaBridge 172:65be27845400 5779 #define CRYP_RISR_INRIS_Pos (1U)
AnnaBridge 172:65be27845400 5780 #define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5781 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
AnnaBridge 172:65be27845400 5782 /****************** Bits definition for CRYP_MISR register *******************/
AnnaBridge 172:65be27845400 5783 #define CRYP_MISR_INMIS_Pos (0U)
AnnaBridge 172:65be27845400 5784 #define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5785 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
AnnaBridge 172:65be27845400 5786 #define CRYP_MISR_OUTMIS_Pos (1U)
AnnaBridge 172:65be27845400 5787 #define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5788 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
AnnaBridge 172:65be27845400 5789
AnnaBridge 172:65be27845400 5790 /******************************************************************************/
AnnaBridge 172:65be27845400 5791 /* */
AnnaBridge 172:65be27845400 5792 /* Digital to Analog Converter */
AnnaBridge 172:65be27845400 5793 /* */
AnnaBridge 172:65be27845400 5794 /******************************************************************************/
AnnaBridge 172:65be27845400 5795 /*
AnnaBridge 172:65be27845400 5796 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 172:65be27845400 5797 */
AnnaBridge 172:65be27845400 5798 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
AnnaBridge 172:65be27845400 5799 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 172:65be27845400 5800 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 172:65be27845400 5801 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5802 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 172:65be27845400 5803 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 172:65be27845400 5804 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5805 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
AnnaBridge 172:65be27845400 5806 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 172:65be27845400 5807 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5808 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 172:65be27845400 5809
AnnaBridge 172:65be27845400 5810 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 172:65be27845400 5811 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 5812 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 172:65be27845400 5813 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5814 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5815 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5816
AnnaBridge 172:65be27845400 5817 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 172:65be27845400 5818 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 5819 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 172:65be27845400 5820 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5821 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5822
AnnaBridge 172:65be27845400 5823 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 172:65be27845400 5824 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 5825 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 172:65be27845400 5826 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5827 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5828 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5829 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5830
AnnaBridge 172:65be27845400 5831 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 172:65be27845400 5832 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5833 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 172:65be27845400 5834 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 172:65be27845400 5835 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5836 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
AnnaBridge 172:65be27845400 5837 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 172:65be27845400 5838 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5839 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 172:65be27845400 5840 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 172:65be27845400 5841 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5842 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
AnnaBridge 172:65be27845400 5843 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 172:65be27845400 5844 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5845 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 172:65be27845400 5846
AnnaBridge 172:65be27845400 5847 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 172:65be27845400 5848 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 172:65be27845400 5849 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 172:65be27845400 5850 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5851 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5852 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5853
AnnaBridge 172:65be27845400 5854 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 172:65be27845400 5855 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 5856 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 172:65be27845400 5857 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5858 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5859
AnnaBridge 172:65be27845400 5860 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 172:65be27845400 5861 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 5862 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 172:65be27845400 5863 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5864 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5865 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5866 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5867
AnnaBridge 172:65be27845400 5868 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 172:65be27845400 5869 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5870 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 172:65be27845400 5871 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 172:65be27845400 5872 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5873 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
AnnaBridge 172:65be27845400 5874
AnnaBridge 172:65be27845400 5875 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 172:65be27845400 5876 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 172:65be27845400 5877 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5878 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 172:65be27845400 5879 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 172:65be27845400 5880 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5881 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 172:65be27845400 5882
AnnaBridge 172:65be27845400 5883 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 172:65be27845400 5884 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5885 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5886 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5887
AnnaBridge 172:65be27845400 5888 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 172:65be27845400 5889 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 172:65be27845400 5890 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 5891 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5892
AnnaBridge 172:65be27845400 5893 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 172:65be27845400 5894 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5895 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5896 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5897
AnnaBridge 172:65be27845400 5898 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 172:65be27845400 5899 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 172:65be27845400 5900 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5901 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5902
AnnaBridge 172:65be27845400 5903 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 172:65be27845400 5904 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 172:65be27845400 5905 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 5906 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5907
AnnaBridge 172:65be27845400 5908 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 172:65be27845400 5909 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 172:65be27845400 5910 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5911 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5912
AnnaBridge 172:65be27845400 5913 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 172:65be27845400 5914 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5915 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5916 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5917 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 172:65be27845400 5918 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 5919 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5920
AnnaBridge 172:65be27845400 5921 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 172:65be27845400 5922 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 172:65be27845400 5923 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 5924 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5925 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 172:65be27845400 5926 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 172:65be27845400 5927 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5928
AnnaBridge 172:65be27845400 5929 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 172:65be27845400 5930 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5931 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5932 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5933 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 172:65be27845400 5934 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 5935 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5936
AnnaBridge 172:65be27845400 5937 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 172:65be27845400 5938 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 172:65be27845400 5939 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5940 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 172:65be27845400 5941
AnnaBridge 172:65be27845400 5942 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 172:65be27845400 5943 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 172:65be27845400 5944 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5945 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 172:65be27845400 5946
AnnaBridge 172:65be27845400 5947 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 172:65be27845400 5948 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 172:65be27845400 5949 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5950 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 172:65be27845400 5951 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 172:65be27845400 5952 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5953 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 172:65be27845400 5954
AnnaBridge 172:65be27845400 5955 /******************************************************************************/
AnnaBridge 172:65be27845400 5956 /* */
AnnaBridge 172:65be27845400 5957 /* DCMI */
AnnaBridge 172:65be27845400 5958 /* */
AnnaBridge 172:65be27845400 5959 /******************************************************************************/
AnnaBridge 172:65be27845400 5960 /******************** Bits definition for DCMI_CR register ******************/
AnnaBridge 172:65be27845400 5961 #define DCMI_CR_CAPTURE_Pos (0U)
AnnaBridge 172:65be27845400 5962 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5963 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
AnnaBridge 172:65be27845400 5964 #define DCMI_CR_CM_Pos (1U)
AnnaBridge 172:65be27845400 5965 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5966 #define DCMI_CR_CM DCMI_CR_CM_Msk
AnnaBridge 172:65be27845400 5967 #define DCMI_CR_CROP_Pos (2U)
AnnaBridge 172:65be27845400 5968 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5969 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
AnnaBridge 172:65be27845400 5970 #define DCMI_CR_JPEG_Pos (3U)
AnnaBridge 172:65be27845400 5971 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5972 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
AnnaBridge 172:65be27845400 5973 #define DCMI_CR_ESS_Pos (4U)
AnnaBridge 172:65be27845400 5974 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5975 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
AnnaBridge 172:65be27845400 5976 #define DCMI_CR_PCKPOL_Pos (5U)
AnnaBridge 172:65be27845400 5977 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5978 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
AnnaBridge 172:65be27845400 5979 #define DCMI_CR_HSPOL_Pos (6U)
AnnaBridge 172:65be27845400 5980 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5981 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
AnnaBridge 172:65be27845400 5982 #define DCMI_CR_VSPOL_Pos (7U)
AnnaBridge 172:65be27845400 5983 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5984 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
AnnaBridge 172:65be27845400 5985 #define DCMI_CR_FCRC_0 0x00000100U
AnnaBridge 172:65be27845400 5986 #define DCMI_CR_FCRC_1 0x00000200U
AnnaBridge 172:65be27845400 5987 #define DCMI_CR_EDM_0 0x00000400U
AnnaBridge 172:65be27845400 5988 #define DCMI_CR_EDM_1 0x00000800U
AnnaBridge 172:65be27845400 5989 #define DCMI_CR_ENABLE_Pos (14U)
AnnaBridge 172:65be27845400 5990 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5991 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
AnnaBridge 172:65be27845400 5992
AnnaBridge 172:65be27845400 5993 /******************** Bits definition for DCMI_SR register ******************/
AnnaBridge 172:65be27845400 5994 #define DCMI_SR_HSYNC_Pos (0U)
AnnaBridge 172:65be27845400 5995 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5996 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
AnnaBridge 172:65be27845400 5997 #define DCMI_SR_VSYNC_Pos (1U)
AnnaBridge 172:65be27845400 5998 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5999 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
AnnaBridge 172:65be27845400 6000 #define DCMI_SR_FNE_Pos (2U)
AnnaBridge 172:65be27845400 6001 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6002 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
AnnaBridge 172:65be27845400 6003
AnnaBridge 172:65be27845400 6004 /******************** Bits definition for DCMI_RIS register *****************/
AnnaBridge 172:65be27845400 6005 #define DCMI_RIS_FRAME_RIS_Pos (0U)
AnnaBridge 172:65be27845400 6006 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6007 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
AnnaBridge 172:65be27845400 6008 #define DCMI_RIS_OVR_RIS_Pos (1U)
AnnaBridge 172:65be27845400 6009 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6010 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
AnnaBridge 172:65be27845400 6011 #define DCMI_RIS_ERR_RIS_Pos (2U)
AnnaBridge 172:65be27845400 6012 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6013 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
AnnaBridge 172:65be27845400 6014 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
AnnaBridge 172:65be27845400 6015 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6016 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
AnnaBridge 172:65be27845400 6017 #define DCMI_RIS_LINE_RIS_Pos (4U)
AnnaBridge 172:65be27845400 6018 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6019 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
AnnaBridge 172:65be27845400 6020 /* Legacy defines */
AnnaBridge 172:65be27845400 6021 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
AnnaBridge 172:65be27845400 6022 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
AnnaBridge 172:65be27845400 6023 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
AnnaBridge 172:65be27845400 6024 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
AnnaBridge 172:65be27845400 6025 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
AnnaBridge 172:65be27845400 6026 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
AnnaBridge 172:65be27845400 6027
AnnaBridge 172:65be27845400 6028 /******************** Bits definition for DCMI_IER register *****************/
AnnaBridge 172:65be27845400 6029 #define DCMI_IER_FRAME_IE_Pos (0U)
AnnaBridge 172:65be27845400 6030 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6031 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
AnnaBridge 172:65be27845400 6032 #define DCMI_IER_OVR_IE_Pos (1U)
AnnaBridge 172:65be27845400 6033 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6034 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
AnnaBridge 172:65be27845400 6035 #define DCMI_IER_ERR_IE_Pos (2U)
AnnaBridge 172:65be27845400 6036 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6037 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
AnnaBridge 172:65be27845400 6038 #define DCMI_IER_VSYNC_IE_Pos (3U)
AnnaBridge 172:65be27845400 6039 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6040 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
AnnaBridge 172:65be27845400 6041 #define DCMI_IER_LINE_IE_Pos (4U)
AnnaBridge 172:65be27845400 6042 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6043 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
AnnaBridge 172:65be27845400 6044 /* Legacy defines */
AnnaBridge 172:65be27845400 6045 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
AnnaBridge 172:65be27845400 6046
AnnaBridge 172:65be27845400 6047 /******************** Bits definition for DCMI_MIS register *****************/
AnnaBridge 172:65be27845400 6048 #define DCMI_MIS_FRAME_MIS_Pos (0U)
AnnaBridge 172:65be27845400 6049 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6050 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
AnnaBridge 172:65be27845400 6051 #define DCMI_MIS_OVR_MIS_Pos (1U)
AnnaBridge 172:65be27845400 6052 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6053 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
AnnaBridge 172:65be27845400 6054 #define DCMI_MIS_ERR_MIS_Pos (2U)
AnnaBridge 172:65be27845400 6055 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6056 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
AnnaBridge 172:65be27845400 6057 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
AnnaBridge 172:65be27845400 6058 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6059 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
AnnaBridge 172:65be27845400 6060 #define DCMI_MIS_LINE_MIS_Pos (4U)
AnnaBridge 172:65be27845400 6061 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6062 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
AnnaBridge 172:65be27845400 6063
AnnaBridge 172:65be27845400 6064 /* Legacy defines */
AnnaBridge 172:65be27845400 6065 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
AnnaBridge 172:65be27845400 6066 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
AnnaBridge 172:65be27845400 6067 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
AnnaBridge 172:65be27845400 6068 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
AnnaBridge 172:65be27845400 6069 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
AnnaBridge 172:65be27845400 6070
AnnaBridge 172:65be27845400 6071 /******************** Bits definition for DCMI_ICR register *****************/
AnnaBridge 172:65be27845400 6072 #define DCMI_ICR_FRAME_ISC_Pos (0U)
AnnaBridge 172:65be27845400 6073 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6074 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
AnnaBridge 172:65be27845400 6075 #define DCMI_ICR_OVR_ISC_Pos (1U)
AnnaBridge 172:65be27845400 6076 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6077 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
AnnaBridge 172:65be27845400 6078 #define DCMI_ICR_ERR_ISC_Pos (2U)
AnnaBridge 172:65be27845400 6079 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6080 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
AnnaBridge 172:65be27845400 6081 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
AnnaBridge 172:65be27845400 6082 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6083 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
AnnaBridge 172:65be27845400 6084 #define DCMI_ICR_LINE_ISC_Pos (4U)
AnnaBridge 172:65be27845400 6085 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6086 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
AnnaBridge 172:65be27845400 6087
AnnaBridge 172:65be27845400 6088 /* Legacy defines */
AnnaBridge 172:65be27845400 6089 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
AnnaBridge 172:65be27845400 6090
AnnaBridge 172:65be27845400 6091 /******************** Bits definition for DCMI_ESCR register ******************/
AnnaBridge 172:65be27845400 6092 #define DCMI_ESCR_FSC_Pos (0U)
AnnaBridge 172:65be27845400 6093 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6094 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
AnnaBridge 172:65be27845400 6095 #define DCMI_ESCR_LSC_Pos (8U)
AnnaBridge 172:65be27845400 6096 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6097 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
AnnaBridge 172:65be27845400 6098 #define DCMI_ESCR_LEC_Pos (16U)
AnnaBridge 172:65be27845400 6099 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6100 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
AnnaBridge 172:65be27845400 6101 #define DCMI_ESCR_FEC_Pos (24U)
AnnaBridge 172:65be27845400 6102 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6103 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
AnnaBridge 172:65be27845400 6104
AnnaBridge 172:65be27845400 6105 /******************** Bits definition for DCMI_ESUR register ******************/
AnnaBridge 172:65be27845400 6106 #define DCMI_ESUR_FSU_Pos (0U)
AnnaBridge 172:65be27845400 6107 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6108 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
AnnaBridge 172:65be27845400 6109 #define DCMI_ESUR_LSU_Pos (8U)
AnnaBridge 172:65be27845400 6110 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6111 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
AnnaBridge 172:65be27845400 6112 #define DCMI_ESUR_LEU_Pos (16U)
AnnaBridge 172:65be27845400 6113 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6114 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
AnnaBridge 172:65be27845400 6115 #define DCMI_ESUR_FEU_Pos (24U)
AnnaBridge 172:65be27845400 6116 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6117 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
AnnaBridge 172:65be27845400 6118
AnnaBridge 172:65be27845400 6119 /******************** Bits definition for DCMI_CWSTRT register ******************/
AnnaBridge 172:65be27845400 6120 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
AnnaBridge 172:65be27845400 6121 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6122 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
AnnaBridge 172:65be27845400 6123 #define DCMI_CWSTRT_VST_Pos (16U)
AnnaBridge 172:65be27845400 6124 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
AnnaBridge 172:65be27845400 6125 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
AnnaBridge 172:65be27845400 6126
AnnaBridge 172:65be27845400 6127 /******************** Bits definition for DCMI_CWSIZE register ******************/
AnnaBridge 172:65be27845400 6128 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
AnnaBridge 172:65be27845400 6129 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6130 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
AnnaBridge 172:65be27845400 6131 #define DCMI_CWSIZE_VLINE_Pos (16U)
AnnaBridge 172:65be27845400 6132 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
AnnaBridge 172:65be27845400 6133 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
AnnaBridge 172:65be27845400 6134
AnnaBridge 172:65be27845400 6135 /******************** Bits definition for DCMI_DR register *********************/
AnnaBridge 172:65be27845400 6136 #define DCMI_DR_BYTE0_Pos (0U)
AnnaBridge 172:65be27845400 6137 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6138 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
AnnaBridge 172:65be27845400 6139 #define DCMI_DR_BYTE1_Pos (8U)
AnnaBridge 172:65be27845400 6140 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6141 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
AnnaBridge 172:65be27845400 6142 #define DCMI_DR_BYTE2_Pos (16U)
AnnaBridge 172:65be27845400 6143 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6144 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
AnnaBridge 172:65be27845400 6145 #define DCMI_DR_BYTE3_Pos (24U)
AnnaBridge 172:65be27845400 6146 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6147 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
AnnaBridge 172:65be27845400 6148
AnnaBridge 172:65be27845400 6149 /******************************************************************************/
AnnaBridge 172:65be27845400 6150 /* */
AnnaBridge 172:65be27845400 6151 /* DMA Controller */
AnnaBridge 172:65be27845400 6152 /* */
AnnaBridge 172:65be27845400 6153 /******************************************************************************/
AnnaBridge 172:65be27845400 6154 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 172:65be27845400 6155 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 172:65be27845400 6156 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
AnnaBridge 172:65be27845400 6157 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 172:65be27845400 6158 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 172:65be27845400 6159 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 172:65be27845400 6160 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 172:65be27845400 6161 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 172:65be27845400 6162 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 172:65be27845400 6163 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 172:65be27845400 6164 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 6165 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6166 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 172:65be27845400 6167 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 6168 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 172:65be27845400 6169 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6170 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6171 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 172:65be27845400 6172 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6173 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 172:65be27845400 6174 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 172:65be27845400 6175 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6176 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 172:65be27845400 6177 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 172:65be27845400 6178 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6179 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 172:65be27845400 6180 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6181 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6182 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 172:65be27845400 6183 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 6184 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 172:65be27845400 6185 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 172:65be27845400 6186 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 6187 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 172:65be27845400 6188 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6189 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6190 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 172:65be27845400 6191 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 6192 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 172:65be27845400 6193 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6194 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6195 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 172:65be27845400 6196 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6197 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 172:65be27845400 6198 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 172:65be27845400 6199 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6200 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 172:65be27845400 6201 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 172:65be27845400 6202 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6203 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 172:65be27845400 6204 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 172:65be27845400 6205 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 6206 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 172:65be27845400 6207 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6208 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6209 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 172:65be27845400 6210 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6211 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 172:65be27845400 6212 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 172:65be27845400 6213 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6214 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 172:65be27845400 6215 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 172:65be27845400 6216 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6217 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 172:65be27845400 6218 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 172:65be27845400 6219 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6220 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 172:65be27845400 6221 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 172:65be27845400 6222 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6223 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 172:65be27845400 6224 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 172:65be27845400 6225 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6226 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
AnnaBridge 172:65be27845400 6227
AnnaBridge 172:65be27845400 6228 /* Legacy defines */
AnnaBridge 172:65be27845400 6229 #define DMA_SxCR_ACK_Pos (20U)
AnnaBridge 172:65be27845400 6230 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6231 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
AnnaBridge 172:65be27845400 6232
AnnaBridge 172:65be27845400 6233 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 172:65be27845400 6234 #define DMA_SxNDT_Pos (0U)
AnnaBridge 172:65be27845400 6235 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6236 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 172:65be27845400 6237 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6238 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6239 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6240 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6241 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6242 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6243 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6244 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6245 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6246 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6247 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6248 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6249 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6250 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6251 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6252 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 6253
AnnaBridge 172:65be27845400 6254 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 172:65be27845400 6255 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 172:65be27845400 6256 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6257 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 172:65be27845400 6258 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 172:65be27845400 6259 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 6260 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 172:65be27845400 6261 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6262 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6263 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6264 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 172:65be27845400 6265 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6266 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 172:65be27845400 6267 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 172:65be27845400 6268 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 6269 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 172:65be27845400 6270 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6271 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6272
AnnaBridge 172:65be27845400 6273 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 172:65be27845400 6274 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 172:65be27845400 6275 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6276 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 172:65be27845400 6277 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 172:65be27845400 6278 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 6279 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 172:65be27845400 6280 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 172:65be27845400 6281 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 6282 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 172:65be27845400 6283 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 172:65be27845400 6284 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6285 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 172:65be27845400 6286 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 172:65be27845400 6287 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6288 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 172:65be27845400 6289 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 172:65be27845400 6290 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6291 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 172:65be27845400 6292 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 172:65be27845400 6293 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6294 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 172:65be27845400 6295 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 172:65be27845400 6296 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6297 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 172:65be27845400 6298 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 172:65be27845400 6299 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6300 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 172:65be27845400 6301 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 172:65be27845400 6302 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6303 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 172:65be27845400 6304 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 172:65be27845400 6305 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6306 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 172:65be27845400 6307 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 172:65be27845400 6308 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6309 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 172:65be27845400 6310 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 172:65be27845400 6311 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6312 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 172:65be27845400 6313 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 172:65be27845400 6314 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6315 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 172:65be27845400 6316 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 172:65be27845400 6317 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6318 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 172:65be27845400 6319 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 172:65be27845400 6320 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6321 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 172:65be27845400 6322 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 172:65be27845400 6323 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6324 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 172:65be27845400 6325 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 172:65be27845400 6326 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6327 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 172:65be27845400 6328 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 172:65be27845400 6329 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6330 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 172:65be27845400 6331 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 172:65be27845400 6332 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6333 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
AnnaBridge 172:65be27845400 6334
AnnaBridge 172:65be27845400 6335 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 172:65be27845400 6336 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 172:65be27845400 6337 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6338 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 172:65be27845400 6339 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 172:65be27845400 6340 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 6341 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 172:65be27845400 6342 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 172:65be27845400 6343 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 6344 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 172:65be27845400 6345 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 172:65be27845400 6346 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6347 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 172:65be27845400 6348 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 172:65be27845400 6349 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6350 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 172:65be27845400 6351 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 172:65be27845400 6352 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6353 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 172:65be27845400 6354 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 172:65be27845400 6355 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6356 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 172:65be27845400 6357 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 172:65be27845400 6358 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6359 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 172:65be27845400 6360 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 172:65be27845400 6361 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6362 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 172:65be27845400 6363 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 172:65be27845400 6364 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6365 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 172:65be27845400 6366 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 172:65be27845400 6367 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6368 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 172:65be27845400 6369 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 172:65be27845400 6370 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6371 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 172:65be27845400 6372 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 172:65be27845400 6373 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6374 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 172:65be27845400 6375 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 172:65be27845400 6376 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6377 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 172:65be27845400 6378 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 172:65be27845400 6379 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6380 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 172:65be27845400 6381 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 172:65be27845400 6382 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6383 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 172:65be27845400 6384 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 172:65be27845400 6385 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6386 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 172:65be27845400 6387 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 172:65be27845400 6388 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6389 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 172:65be27845400 6390 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 172:65be27845400 6391 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6392 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 172:65be27845400 6393 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 172:65be27845400 6394 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6395 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
AnnaBridge 172:65be27845400 6396
AnnaBridge 172:65be27845400 6397 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 172:65be27845400 6398 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 172:65be27845400 6399 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6400 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 172:65be27845400 6401 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 172:65be27845400 6402 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 6403 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 172:65be27845400 6404 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 172:65be27845400 6405 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 6406 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 172:65be27845400 6407 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 172:65be27845400 6408 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6409 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 172:65be27845400 6410 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 172:65be27845400 6411 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6412 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 172:65be27845400 6413 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 172:65be27845400 6414 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6415 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 172:65be27845400 6416 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 172:65be27845400 6417 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6418 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 172:65be27845400 6419 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 172:65be27845400 6420 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6421 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 172:65be27845400 6422 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 172:65be27845400 6423 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6424 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 172:65be27845400 6425 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 172:65be27845400 6426 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6427 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 172:65be27845400 6428 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 172:65be27845400 6429 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6430 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 172:65be27845400 6431 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 172:65be27845400 6432 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6433 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 172:65be27845400 6434 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 172:65be27845400 6435 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6436 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 172:65be27845400 6437 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 172:65be27845400 6438 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6439 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 172:65be27845400 6440 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 172:65be27845400 6441 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6442 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 172:65be27845400 6443 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 172:65be27845400 6444 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6445 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 172:65be27845400 6446 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 172:65be27845400 6447 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6448 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 172:65be27845400 6449 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 172:65be27845400 6450 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6451 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 172:65be27845400 6452 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 172:65be27845400 6453 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6454 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 172:65be27845400 6455 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 172:65be27845400 6456 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6457 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
AnnaBridge 172:65be27845400 6458
AnnaBridge 172:65be27845400 6459 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 172:65be27845400 6460 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 172:65be27845400 6461 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6462 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 172:65be27845400 6463 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 172:65be27845400 6464 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 6465 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 172:65be27845400 6466 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 172:65be27845400 6467 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 6468 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 172:65be27845400 6469 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 172:65be27845400 6470 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6471 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 172:65be27845400 6472 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 172:65be27845400 6473 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6474 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 172:65be27845400 6475 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 172:65be27845400 6476 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6477 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 172:65be27845400 6478 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 172:65be27845400 6479 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6480 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 172:65be27845400 6481 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 172:65be27845400 6482 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6483 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 172:65be27845400 6484 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 172:65be27845400 6485 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6486 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 172:65be27845400 6487 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 172:65be27845400 6488 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6489 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 172:65be27845400 6490 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 172:65be27845400 6491 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6492 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 172:65be27845400 6493 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 172:65be27845400 6494 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6495 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 172:65be27845400 6496 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 172:65be27845400 6497 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6498 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 172:65be27845400 6499 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 172:65be27845400 6500 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6501 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 172:65be27845400 6502 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 172:65be27845400 6503 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6504 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 172:65be27845400 6505 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 172:65be27845400 6506 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6507 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 172:65be27845400 6508 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 172:65be27845400 6509 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6510 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 172:65be27845400 6511 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 172:65be27845400 6512 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6513 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 172:65be27845400 6514 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 172:65be27845400 6515 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6516 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 172:65be27845400 6517 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 172:65be27845400 6518 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6519 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 172:65be27845400 6520
AnnaBridge 172:65be27845400 6521 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 172:65be27845400 6522 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 172:65be27845400 6523 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6524 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 172:65be27845400 6525
AnnaBridge 172:65be27845400 6526 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 172:65be27845400 6527 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 172:65be27845400 6528 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6529 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6530
AnnaBridge 172:65be27845400 6531 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 172:65be27845400 6532 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 172:65be27845400 6533 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6534 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6535
AnnaBridge 172:65be27845400 6536
AnnaBridge 172:65be27845400 6537 /******************************************************************************/
AnnaBridge 172:65be27845400 6538 /* */
AnnaBridge 172:65be27845400 6539 /* AHB Master DMA2D Controller (DMA2D) */
AnnaBridge 172:65be27845400 6540 /* */
AnnaBridge 172:65be27845400 6541 /******************************************************************************/
AnnaBridge 172:65be27845400 6542
AnnaBridge 172:65be27845400 6543 /******************** Bit definition for DMA2D_CR register ******************/
AnnaBridge 172:65be27845400 6544
AnnaBridge 172:65be27845400 6545 #define DMA2D_CR_START_Pos (0U)
AnnaBridge 172:65be27845400 6546 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6547 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
AnnaBridge 172:65be27845400 6548 #define DMA2D_CR_SUSP_Pos (1U)
AnnaBridge 172:65be27845400 6549 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6550 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
AnnaBridge 172:65be27845400 6551 #define DMA2D_CR_ABORT_Pos (2U)
AnnaBridge 172:65be27845400 6552 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6553 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
AnnaBridge 172:65be27845400 6554 #define DMA2D_CR_TEIE_Pos (8U)
AnnaBridge 172:65be27845400 6555 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6556 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 172:65be27845400 6557 #define DMA2D_CR_TCIE_Pos (9U)
AnnaBridge 172:65be27845400 6558 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6559 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 172:65be27845400 6560 #define DMA2D_CR_TWIE_Pos (10U)
AnnaBridge 172:65be27845400 6561 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6562 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
AnnaBridge 172:65be27845400 6563 #define DMA2D_CR_CAEIE_Pos (11U)
AnnaBridge 172:65be27845400 6564 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6565 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
AnnaBridge 172:65be27845400 6566 #define DMA2D_CR_CTCIE_Pos (12U)
AnnaBridge 172:65be27845400 6567 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6568 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
AnnaBridge 172:65be27845400 6569 #define DMA2D_CR_CEIE_Pos (13U)
AnnaBridge 172:65be27845400 6570 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6571 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
AnnaBridge 172:65be27845400 6572 #define DMA2D_CR_MODE_Pos (16U)
AnnaBridge 172:65be27845400 6573 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6574 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
AnnaBridge 172:65be27845400 6575 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6576 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6577
AnnaBridge 172:65be27845400 6578 /******************** Bit definition for DMA2D_ISR register *****************/
AnnaBridge 172:65be27845400 6579
AnnaBridge 172:65be27845400 6580 #define DMA2D_ISR_TEIF_Pos (0U)
AnnaBridge 172:65be27845400 6581 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6582 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 6583 #define DMA2D_ISR_TCIF_Pos (1U)
AnnaBridge 172:65be27845400 6584 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6585 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 6586 #define DMA2D_ISR_TWIF_Pos (2U)
AnnaBridge 172:65be27845400 6587 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6588 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
AnnaBridge 172:65be27845400 6589 #define DMA2D_ISR_CAEIF_Pos (3U)
AnnaBridge 172:65be27845400 6590 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6591 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
AnnaBridge 172:65be27845400 6592 #define DMA2D_ISR_CTCIF_Pos (4U)
AnnaBridge 172:65be27845400 6593 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6594 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 6595 #define DMA2D_ISR_CEIF_Pos (5U)
AnnaBridge 172:65be27845400 6596 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6597 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
AnnaBridge 172:65be27845400 6598
AnnaBridge 172:65be27845400 6599 /******************** Bit definition for DMA2D_IFCR register ****************/
AnnaBridge 172:65be27845400 6600
AnnaBridge 172:65be27845400 6601 #define DMA2D_IFCR_CTEIF_Pos (0U)
AnnaBridge 172:65be27845400 6602 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6603 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 6604 #define DMA2D_IFCR_CTCIF_Pos (1U)
AnnaBridge 172:65be27845400 6605 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6606 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 6607 #define DMA2D_IFCR_CTWIF_Pos (2U)
AnnaBridge 172:65be27845400 6608 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6609 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 172:65be27845400 6610 #define DMA2D_IFCR_CAECIF_Pos (3U)
AnnaBridge 172:65be27845400 6611 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6612 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 172:65be27845400 6613 #define DMA2D_IFCR_CCTCIF_Pos (4U)
AnnaBridge 172:65be27845400 6614 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6615 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 6616 #define DMA2D_IFCR_CCEIF_Pos (5U)
AnnaBridge 172:65be27845400 6617 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6618 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
AnnaBridge 172:65be27845400 6619
AnnaBridge 172:65be27845400 6620 /* Legacy defines */
AnnaBridge 172:65be27845400 6621 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 6622 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 6623 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 172:65be27845400 6624 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 172:65be27845400 6625 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 6626 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
AnnaBridge 172:65be27845400 6627
AnnaBridge 172:65be27845400 6628 /******************** Bit definition for DMA2D_FGMAR register ***************/
AnnaBridge 172:65be27845400 6629
AnnaBridge 172:65be27845400 6630 #define DMA2D_FGMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 6631 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6632 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6633
AnnaBridge 172:65be27845400 6634 /******************** Bit definition for DMA2D_FGOR register ****************/
AnnaBridge 172:65be27845400 6635
AnnaBridge 172:65be27845400 6636 #define DMA2D_FGOR_LO_Pos (0U)
AnnaBridge 172:65be27845400 6637 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6638 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
AnnaBridge 172:65be27845400 6639
AnnaBridge 172:65be27845400 6640 /******************** Bit definition for DMA2D_BGMAR register ***************/
AnnaBridge 172:65be27845400 6641
AnnaBridge 172:65be27845400 6642 #define DMA2D_BGMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 6643 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6644 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6645
AnnaBridge 172:65be27845400 6646 /******************** Bit definition for DMA2D_BGOR register ****************/
AnnaBridge 172:65be27845400 6647
AnnaBridge 172:65be27845400 6648 #define DMA2D_BGOR_LO_Pos (0U)
AnnaBridge 172:65be27845400 6649 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6650 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
AnnaBridge 172:65be27845400 6651
AnnaBridge 172:65be27845400 6652 /******************** Bit definition for DMA2D_FGPFCCR register *************/
AnnaBridge 172:65be27845400 6653
AnnaBridge 172:65be27845400 6654 #define DMA2D_FGPFCCR_CM_Pos (0U)
AnnaBridge 172:65be27845400 6655 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 6656 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 172:65be27845400 6657 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6658 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6659 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6660 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6661 #define DMA2D_FGPFCCR_CCM_Pos (4U)
AnnaBridge 172:65be27845400 6662 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6663 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 172:65be27845400 6664 #define DMA2D_FGPFCCR_START_Pos (5U)
AnnaBridge 172:65be27845400 6665 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6666 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
AnnaBridge 172:65be27845400 6667 #define DMA2D_FGPFCCR_CS_Pos (8U)
AnnaBridge 172:65be27845400 6668 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6669 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 172:65be27845400 6670 #define DMA2D_FGPFCCR_AM_Pos (16U)
AnnaBridge 172:65be27845400 6671 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6672 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 172:65be27845400 6673 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6674 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6675 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
AnnaBridge 172:65be27845400 6676 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6677 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
AnnaBridge 172:65be27845400 6678
AnnaBridge 172:65be27845400 6679 /******************** Bit definition for DMA2D_FGCOLR register **************/
AnnaBridge 172:65be27845400 6680
AnnaBridge 172:65be27845400 6681 #define DMA2D_FGCOLR_BLUE_Pos (0U)
AnnaBridge 172:65be27845400 6682 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6683 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
AnnaBridge 172:65be27845400 6684 #define DMA2D_FGCOLR_GREEN_Pos (8U)
AnnaBridge 172:65be27845400 6685 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6686 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
AnnaBridge 172:65be27845400 6687 #define DMA2D_FGCOLR_RED_Pos (16U)
AnnaBridge 172:65be27845400 6688 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6689 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
AnnaBridge 172:65be27845400 6690
AnnaBridge 172:65be27845400 6691 /******************** Bit definition for DMA2D_BGPFCCR register *************/
AnnaBridge 172:65be27845400 6692
AnnaBridge 172:65be27845400 6693 #define DMA2D_BGPFCCR_CM_Pos (0U)
AnnaBridge 172:65be27845400 6694 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 6695 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 172:65be27845400 6696 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6697 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6698 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6699 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
AnnaBridge 172:65be27845400 6700 #define DMA2D_BGPFCCR_CCM_Pos (4U)
AnnaBridge 172:65be27845400 6701 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6702 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 172:65be27845400 6703 #define DMA2D_BGPFCCR_START_Pos (5U)
AnnaBridge 172:65be27845400 6704 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6705 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
AnnaBridge 172:65be27845400 6706 #define DMA2D_BGPFCCR_CS_Pos (8U)
AnnaBridge 172:65be27845400 6707 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6708 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 172:65be27845400 6709 #define DMA2D_BGPFCCR_AM_Pos (16U)
AnnaBridge 172:65be27845400 6710 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6711 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 172:65be27845400 6712 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6713 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6714 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
AnnaBridge 172:65be27845400 6715 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6716 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
AnnaBridge 172:65be27845400 6717
AnnaBridge 172:65be27845400 6718 /******************** Bit definition for DMA2D_BGCOLR register **************/
AnnaBridge 172:65be27845400 6719
AnnaBridge 172:65be27845400 6720 #define DMA2D_BGCOLR_BLUE_Pos (0U)
AnnaBridge 172:65be27845400 6721 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6722 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
AnnaBridge 172:65be27845400 6723 #define DMA2D_BGCOLR_GREEN_Pos (8U)
AnnaBridge 172:65be27845400 6724 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6725 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
AnnaBridge 172:65be27845400 6726 #define DMA2D_BGCOLR_RED_Pos (16U)
AnnaBridge 172:65be27845400 6727 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6728 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
AnnaBridge 172:65be27845400 6729
AnnaBridge 172:65be27845400 6730 /******************** Bit definition for DMA2D_FGCMAR register **************/
AnnaBridge 172:65be27845400 6731
AnnaBridge 172:65be27845400 6732 #define DMA2D_FGCMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 6733 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6734 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6735
AnnaBridge 172:65be27845400 6736 /******************** Bit definition for DMA2D_BGCMAR register **************/
AnnaBridge 172:65be27845400 6737
AnnaBridge 172:65be27845400 6738 #define DMA2D_BGCMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 6739 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6740 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6741
AnnaBridge 172:65be27845400 6742 /******************** Bit definition for DMA2D_OPFCCR register **************/
AnnaBridge 172:65be27845400 6743
AnnaBridge 172:65be27845400 6744 #define DMA2D_OPFCCR_CM_Pos (0U)
AnnaBridge 172:65be27845400 6745 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 6746 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
AnnaBridge 172:65be27845400 6747 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6748 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6749 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6750
AnnaBridge 172:65be27845400 6751 /******************** Bit definition for DMA2D_OCOLR register ***************/
AnnaBridge 172:65be27845400 6752
AnnaBridge 172:65be27845400 6753 /*!<Mode_ARGB8888/RGB888 */
AnnaBridge 172:65be27845400 6754
AnnaBridge 172:65be27845400 6755 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
AnnaBridge 172:65be27845400 6756 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
AnnaBridge 172:65be27845400 6757 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
AnnaBridge 172:65be27845400 6758 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
AnnaBridge 172:65be27845400 6759
AnnaBridge 172:65be27845400 6760 /*!<Mode_RGB565 */
AnnaBridge 172:65be27845400 6761 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
AnnaBridge 172:65be27845400 6762 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
AnnaBridge 172:65be27845400 6763 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
AnnaBridge 172:65be27845400 6764
AnnaBridge 172:65be27845400 6765 /*!<Mode_ARGB1555 */
AnnaBridge 172:65be27845400 6766 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
AnnaBridge 172:65be27845400 6767 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
AnnaBridge 172:65be27845400 6768 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
AnnaBridge 172:65be27845400 6769 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
AnnaBridge 172:65be27845400 6770
AnnaBridge 172:65be27845400 6771 /*!<Mode_ARGB4444 */
AnnaBridge 172:65be27845400 6772 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
AnnaBridge 172:65be27845400 6773 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
AnnaBridge 172:65be27845400 6774 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
AnnaBridge 172:65be27845400 6775 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
AnnaBridge 172:65be27845400 6776
AnnaBridge 172:65be27845400 6777 /******************** Bit definition for DMA2D_OMAR register ****************/
AnnaBridge 172:65be27845400 6778
AnnaBridge 172:65be27845400 6779 #define DMA2D_OMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 6780 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6781 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6782
AnnaBridge 172:65be27845400 6783 /******************** Bit definition for DMA2D_OOR register *****************/
AnnaBridge 172:65be27845400 6784
AnnaBridge 172:65be27845400 6785 #define DMA2D_OOR_LO_Pos (0U)
AnnaBridge 172:65be27845400 6786 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6787 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
AnnaBridge 172:65be27845400 6788
AnnaBridge 172:65be27845400 6789 /******************** Bit definition for DMA2D_NLR register *****************/
AnnaBridge 172:65be27845400 6790
AnnaBridge 172:65be27845400 6791 #define DMA2D_NLR_NL_Pos (0U)
AnnaBridge 172:65be27845400 6792 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6793 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
AnnaBridge 172:65be27845400 6794 #define DMA2D_NLR_PL_Pos (16U)
AnnaBridge 172:65be27845400 6795 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
AnnaBridge 172:65be27845400 6796 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
AnnaBridge 172:65be27845400 6797
AnnaBridge 172:65be27845400 6798 /******************** Bit definition for DMA2D_LWR register *****************/
AnnaBridge 172:65be27845400 6799
AnnaBridge 172:65be27845400 6800 #define DMA2D_LWR_LW_Pos (0U)
AnnaBridge 172:65be27845400 6801 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6802 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
AnnaBridge 172:65be27845400 6803
AnnaBridge 172:65be27845400 6804 /******************** Bit definition for DMA2D_AMTCR register ***************/
AnnaBridge 172:65be27845400 6805
AnnaBridge 172:65be27845400 6806 #define DMA2D_AMTCR_EN_Pos (0U)
AnnaBridge 172:65be27845400 6807 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6808 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
AnnaBridge 172:65be27845400 6809 #define DMA2D_AMTCR_DT_Pos (8U)
AnnaBridge 172:65be27845400 6810 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6811 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
AnnaBridge 172:65be27845400 6812
AnnaBridge 172:65be27845400 6813 /******************** Bit definition for DMA2D_FGCLUT register **************/
AnnaBridge 172:65be27845400 6814
AnnaBridge 172:65be27845400 6815 /******************** Bit definition for DMA2D_BGCLUT register **************/
AnnaBridge 172:65be27845400 6816
AnnaBridge 172:65be27845400 6817
AnnaBridge 172:65be27845400 6818 /******************************************************************************/
AnnaBridge 172:65be27845400 6819 /* */
AnnaBridge 172:65be27845400 6820 /* External Interrupt/Event Controller */
AnnaBridge 172:65be27845400 6821 /* */
AnnaBridge 172:65be27845400 6822 /******************************************************************************/
AnnaBridge 172:65be27845400 6823 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 172:65be27845400 6824 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 172:65be27845400 6825 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6826 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 172:65be27845400 6827 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 172:65be27845400 6828 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6829 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 172:65be27845400 6830 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 172:65be27845400 6831 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6832 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 172:65be27845400 6833 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 172:65be27845400 6834 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6835 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 172:65be27845400 6836 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 172:65be27845400 6837 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6838 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 172:65be27845400 6839 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 172:65be27845400 6840 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6841 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 172:65be27845400 6842 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 172:65be27845400 6843 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6844 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 172:65be27845400 6845 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 172:65be27845400 6846 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6847 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 172:65be27845400 6848 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 172:65be27845400 6849 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6850 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 172:65be27845400 6851 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 172:65be27845400 6852 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6853 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 172:65be27845400 6854 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 172:65be27845400 6855 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6856 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 172:65be27845400 6857 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 172:65be27845400 6858 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6859 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 172:65be27845400 6860 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 172:65be27845400 6861 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6862 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 172:65be27845400 6863 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 172:65be27845400 6864 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6865 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 172:65be27845400 6866 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 172:65be27845400 6867 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6868 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 172:65be27845400 6869 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 172:65be27845400 6870 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 6871 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 172:65be27845400 6872 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 172:65be27845400 6873 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6874 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 172:65be27845400 6875 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 172:65be27845400 6876 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6877 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 172:65be27845400 6878 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 172:65be27845400 6879 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6880 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 172:65be27845400 6881 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 172:65be27845400 6882 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6883 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 172:65be27845400 6884 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 172:65be27845400 6885 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6886 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 172:65be27845400 6887 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 172:65be27845400 6888 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6889 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 172:65be27845400 6890 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 172:65be27845400 6891 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6892 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 172:65be27845400 6893
AnnaBridge 172:65be27845400 6894 /* Reference Defines */
AnnaBridge 172:65be27845400 6895 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 172:65be27845400 6896 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 172:65be27845400 6897 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 172:65be27845400 6898 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 172:65be27845400 6899 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 172:65be27845400 6900 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 172:65be27845400 6901 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 172:65be27845400 6902 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 172:65be27845400 6903 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 172:65be27845400 6904 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 172:65be27845400 6905 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 172:65be27845400 6906 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 172:65be27845400 6907 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 172:65be27845400 6908 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 172:65be27845400 6909 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 172:65be27845400 6910 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 172:65be27845400 6911 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 172:65be27845400 6912 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 172:65be27845400 6913 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 172:65be27845400 6914 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 172:65be27845400 6915 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 172:65be27845400 6916 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 172:65be27845400 6917 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 172:65be27845400 6918 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 172:65be27845400 6919 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
AnnaBridge 172:65be27845400 6920 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 172:65be27845400 6921
AnnaBridge 172:65be27845400 6922 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 172:65be27845400 6923 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 172:65be27845400 6924 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6925 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 172:65be27845400 6926 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 172:65be27845400 6927 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6928 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 172:65be27845400 6929 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 172:65be27845400 6930 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6931 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 172:65be27845400 6932 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 172:65be27845400 6933 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6934 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 172:65be27845400 6935 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 172:65be27845400 6936 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6937 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 172:65be27845400 6938 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 172:65be27845400 6939 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6940 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 172:65be27845400 6941 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 172:65be27845400 6942 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6943 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 172:65be27845400 6944 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 172:65be27845400 6945 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6946 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 172:65be27845400 6947 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 172:65be27845400 6948 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6949 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 172:65be27845400 6950 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 172:65be27845400 6951 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6952 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 172:65be27845400 6953 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 172:65be27845400 6954 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6955 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 172:65be27845400 6956 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 172:65be27845400 6957 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6958 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 172:65be27845400 6959 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 172:65be27845400 6960 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6961 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 172:65be27845400 6962 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 172:65be27845400 6963 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6964 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 172:65be27845400 6965 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 172:65be27845400 6966 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6967 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 172:65be27845400 6968 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 172:65be27845400 6969 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 6970 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 172:65be27845400 6971 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 172:65be27845400 6972 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6973 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 172:65be27845400 6974 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 172:65be27845400 6975 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6976 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 172:65be27845400 6977 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 172:65be27845400 6978 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6979 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 172:65be27845400 6980 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 172:65be27845400 6981 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6982 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 172:65be27845400 6983 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 172:65be27845400 6984 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6985 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 172:65be27845400 6986 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 172:65be27845400 6987 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6988 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 172:65be27845400 6989 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 172:65be27845400 6990 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6991 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 172:65be27845400 6992
AnnaBridge 172:65be27845400 6993 /* Reference Defines */
AnnaBridge 172:65be27845400 6994 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 172:65be27845400 6995 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 172:65be27845400 6996 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 172:65be27845400 6997 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 172:65be27845400 6998 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 172:65be27845400 6999 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 172:65be27845400 7000 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 172:65be27845400 7001 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 172:65be27845400 7002 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 172:65be27845400 7003 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 172:65be27845400 7004 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 172:65be27845400 7005 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 172:65be27845400 7006 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 172:65be27845400 7007 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 172:65be27845400 7008 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 172:65be27845400 7009 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 172:65be27845400 7010 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 172:65be27845400 7011 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 172:65be27845400 7012 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 172:65be27845400 7013 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 172:65be27845400 7014 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 172:65be27845400 7015 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 172:65be27845400 7016 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 172:65be27845400 7017
AnnaBridge 172:65be27845400 7018 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 172:65be27845400 7019 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 172:65be27845400 7020 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7021 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 172:65be27845400 7022 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 172:65be27845400 7023 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7024 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 172:65be27845400 7025 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 172:65be27845400 7026 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7027 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 172:65be27845400 7028 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 172:65be27845400 7029 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7030 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 172:65be27845400 7031 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 172:65be27845400 7032 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7033 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 172:65be27845400 7034 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 172:65be27845400 7035 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7036 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 172:65be27845400 7037 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 172:65be27845400 7038 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7039 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 172:65be27845400 7040 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 172:65be27845400 7041 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7042 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 172:65be27845400 7043 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 172:65be27845400 7044 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7045 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 172:65be27845400 7046 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 172:65be27845400 7047 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7048 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 172:65be27845400 7049 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 172:65be27845400 7050 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7051 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 172:65be27845400 7052 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 172:65be27845400 7053 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7054 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 172:65be27845400 7055 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 172:65be27845400 7056 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7057 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 172:65be27845400 7058 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 172:65be27845400 7059 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7060 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 172:65be27845400 7061 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 172:65be27845400 7062 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7063 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 172:65be27845400 7064 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 172:65be27845400 7065 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7066 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 172:65be27845400 7067 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 172:65be27845400 7068 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7069 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 172:65be27845400 7070 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 172:65be27845400 7071 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7072 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 172:65be27845400 7073 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 172:65be27845400 7074 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7075 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 172:65be27845400 7076 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 172:65be27845400 7077 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7078 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 172:65be27845400 7079 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 172:65be27845400 7080 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7081 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 172:65be27845400 7082 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 172:65be27845400 7083 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7084 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 172:65be27845400 7085 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 172:65be27845400 7086 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7087 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 172:65be27845400 7088
AnnaBridge 172:65be27845400 7089 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 172:65be27845400 7090 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 172:65be27845400 7091 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7092 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 172:65be27845400 7093 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 172:65be27845400 7094 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7095 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 172:65be27845400 7096 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 172:65be27845400 7097 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7098 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 172:65be27845400 7099 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 172:65be27845400 7100 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7101 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 172:65be27845400 7102 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 172:65be27845400 7103 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7104 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 172:65be27845400 7105 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 172:65be27845400 7106 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7107 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 172:65be27845400 7108 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 172:65be27845400 7109 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7110 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 172:65be27845400 7111 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 172:65be27845400 7112 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7113 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 172:65be27845400 7114 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 172:65be27845400 7115 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7116 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 172:65be27845400 7117 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 172:65be27845400 7118 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7119 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 172:65be27845400 7120 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 172:65be27845400 7121 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7122 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 172:65be27845400 7123 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 172:65be27845400 7124 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7125 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 172:65be27845400 7126 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 172:65be27845400 7127 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7128 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 172:65be27845400 7129 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 172:65be27845400 7130 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7131 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 172:65be27845400 7132 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 172:65be27845400 7133 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7134 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 172:65be27845400 7135 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 172:65be27845400 7136 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7137 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 172:65be27845400 7138 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 172:65be27845400 7139 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7140 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 172:65be27845400 7141 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 172:65be27845400 7142 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7143 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 172:65be27845400 7144 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 172:65be27845400 7145 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7146 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 172:65be27845400 7147 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 172:65be27845400 7148 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7149 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 172:65be27845400 7150 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 172:65be27845400 7151 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7152 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 172:65be27845400 7153 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 172:65be27845400 7154 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7155 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 172:65be27845400 7156 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 172:65be27845400 7157 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7158 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 172:65be27845400 7159
AnnaBridge 172:65be27845400 7160 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 172:65be27845400 7161 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 172:65be27845400 7162 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7163 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 172:65be27845400 7164 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 172:65be27845400 7165 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7166 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 172:65be27845400 7167 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 172:65be27845400 7168 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7169 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 172:65be27845400 7170 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 172:65be27845400 7171 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7172 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 172:65be27845400 7173 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 172:65be27845400 7174 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7175 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 172:65be27845400 7176 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 172:65be27845400 7177 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7178 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 172:65be27845400 7179 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 172:65be27845400 7180 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7181 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 172:65be27845400 7182 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 172:65be27845400 7183 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7184 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 172:65be27845400 7185 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 172:65be27845400 7186 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7187 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 172:65be27845400 7188 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 172:65be27845400 7189 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7190 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 172:65be27845400 7191 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 172:65be27845400 7192 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7193 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 172:65be27845400 7194 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 172:65be27845400 7195 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7196 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 172:65be27845400 7197 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 172:65be27845400 7198 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7199 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 172:65be27845400 7200 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 172:65be27845400 7201 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7202 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 172:65be27845400 7203 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 172:65be27845400 7204 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7205 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 172:65be27845400 7206 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 172:65be27845400 7207 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7208 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 172:65be27845400 7209 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 172:65be27845400 7210 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7211 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 172:65be27845400 7212 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 172:65be27845400 7213 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7214 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 172:65be27845400 7215 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 172:65be27845400 7216 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7217 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 172:65be27845400 7218 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 172:65be27845400 7219 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7220 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 172:65be27845400 7221 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 172:65be27845400 7222 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7223 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 172:65be27845400 7224 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 172:65be27845400 7225 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7226 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 172:65be27845400 7227 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 172:65be27845400 7228 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7229 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 172:65be27845400 7230
AnnaBridge 172:65be27845400 7231 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 172:65be27845400 7232 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 172:65be27845400 7233 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7234 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 172:65be27845400 7235 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 172:65be27845400 7236 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7237 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 172:65be27845400 7238 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 172:65be27845400 7239 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7240 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 172:65be27845400 7241 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 172:65be27845400 7242 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7243 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 172:65be27845400 7244 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 172:65be27845400 7245 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7246 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 172:65be27845400 7247 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 172:65be27845400 7248 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7249 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 172:65be27845400 7250 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 172:65be27845400 7251 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7252 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 172:65be27845400 7253 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 172:65be27845400 7254 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7255 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 172:65be27845400 7256 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 172:65be27845400 7257 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7258 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 172:65be27845400 7259 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 172:65be27845400 7260 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7261 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 172:65be27845400 7262 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 172:65be27845400 7263 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7264 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 172:65be27845400 7265 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 172:65be27845400 7266 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7267 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 172:65be27845400 7268 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 172:65be27845400 7269 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7270 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 172:65be27845400 7271 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 172:65be27845400 7272 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7273 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 172:65be27845400 7274 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 172:65be27845400 7275 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7276 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 172:65be27845400 7277 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 172:65be27845400 7278 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7279 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 172:65be27845400 7280 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 172:65be27845400 7281 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7282 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 172:65be27845400 7283 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 172:65be27845400 7284 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7285 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 172:65be27845400 7286 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 172:65be27845400 7287 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7288 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 172:65be27845400 7289 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 172:65be27845400 7290 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7291 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 172:65be27845400 7292 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 172:65be27845400 7293 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7294 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 172:65be27845400 7295 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 172:65be27845400 7296 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7297 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 172:65be27845400 7298 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 172:65be27845400 7299 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7300 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 172:65be27845400 7301
AnnaBridge 172:65be27845400 7302 /******************************************************************************/
AnnaBridge 172:65be27845400 7303 /* */
AnnaBridge 172:65be27845400 7304 /* FLASH */
AnnaBridge 172:65be27845400 7305 /* */
AnnaBridge 172:65be27845400 7306 /******************************************************************************/
AnnaBridge 172:65be27845400 7307 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 172:65be27845400 7308 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 172:65be27845400 7309 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7310 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 172:65be27845400 7311 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 172:65be27845400 7312 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 172:65be27845400 7313 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 172:65be27845400 7314 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 172:65be27845400 7315 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 172:65be27845400 7316 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 172:65be27845400 7317 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 172:65be27845400 7318 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 172:65be27845400 7319
AnnaBridge 172:65be27845400 7320 #define FLASH_ACR_LATENCY_8WS 0x00000008U
AnnaBridge 172:65be27845400 7321 #define FLASH_ACR_LATENCY_9WS 0x00000009U
AnnaBridge 172:65be27845400 7322 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
AnnaBridge 172:65be27845400 7323 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
AnnaBridge 172:65be27845400 7324 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
AnnaBridge 172:65be27845400 7325 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
AnnaBridge 172:65be27845400 7326 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
AnnaBridge 172:65be27845400 7327 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
AnnaBridge 172:65be27845400 7328 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 172:65be27845400 7329 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7330 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 172:65be27845400 7331 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 172:65be27845400 7332 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7333 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 172:65be27845400 7334 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 172:65be27845400 7335 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7336 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 172:65be27845400 7337 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 172:65be27845400 7338 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7339 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 172:65be27845400 7340 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 172:65be27845400 7341 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7342 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 172:65be27845400 7343 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
AnnaBridge 172:65be27845400 7344 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
AnnaBridge 172:65be27845400 7345 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
AnnaBridge 172:65be27845400 7346 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
AnnaBridge 172:65be27845400 7347 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
AnnaBridge 172:65be27845400 7348 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
AnnaBridge 172:65be27845400 7349
AnnaBridge 172:65be27845400 7350 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 172:65be27845400 7351 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 172:65be27845400 7352 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7353 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 172:65be27845400 7354 #define FLASH_SR_SOP_Pos (1U)
AnnaBridge 172:65be27845400 7355 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7356 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
AnnaBridge 172:65be27845400 7357 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 172:65be27845400 7358 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7359 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 172:65be27845400 7360 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 172:65be27845400 7361 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7362 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 172:65be27845400 7363 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 172:65be27845400 7364 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7365 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 172:65be27845400 7366 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 172:65be27845400 7367 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7368 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 172:65be27845400 7369 #define FLASH_SR_RDERR_Pos (8U)
AnnaBridge 172:65be27845400 7370 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7371 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
AnnaBridge 172:65be27845400 7372 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 172:65be27845400 7373 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7374 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 172:65be27845400 7375
AnnaBridge 172:65be27845400 7376 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 172:65be27845400 7377 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 172:65be27845400 7378 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7379 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 172:65be27845400 7380 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 172:65be27845400 7381 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7382 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 172:65be27845400 7383 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 172:65be27845400 7384 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7385 #define FLASH_CR_MER FLASH_CR_MER_Msk
AnnaBridge 172:65be27845400 7386 #define FLASH_CR_MER1 FLASH_CR_MER
AnnaBridge 172:65be27845400 7387 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 172:65be27845400 7388 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
AnnaBridge 172:65be27845400 7389 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 172:65be27845400 7390 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7391 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7392 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7393 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7394 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7395 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 172:65be27845400 7396 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 7397 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 172:65be27845400 7398 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7399 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7400 #define FLASH_CR_MER2_Pos (15U)
AnnaBridge 172:65be27845400 7401 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7402 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
AnnaBridge 172:65be27845400 7403 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 172:65be27845400 7404 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7405 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 172:65be27845400 7406 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 172:65be27845400 7407 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7408 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 172:65be27845400 7409 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 172:65be27845400 7410 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7411 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 172:65be27845400 7412
AnnaBridge 172:65be27845400 7413 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 172:65be27845400 7414 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 172:65be27845400 7415 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7416 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 172:65be27845400 7417 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 172:65be27845400 7418 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7419 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 172:65be27845400 7420
AnnaBridge 172:65be27845400 7421 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 172:65be27845400 7422 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 172:65be27845400 7423 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 172:65be27845400 7424 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 7425 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 172:65be27845400 7426 #define FLASH_OPTCR_BFB2_Pos (4U)
AnnaBridge 172:65be27845400 7427 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7428 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
AnnaBridge 172:65be27845400 7429 #define FLASH_OPTCR_WDG_SW_Pos (5U)
AnnaBridge 172:65be27845400 7430 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7431 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
AnnaBridge 172:65be27845400 7432 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 172:65be27845400 7433 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7434 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 172:65be27845400 7435 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 172:65be27845400 7436 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7437 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 172:65be27845400 7438 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 172:65be27845400 7439 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7440 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 172:65be27845400 7441 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7442 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7443 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7444 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7445 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7446 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7447 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7448 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7449 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 172:65be27845400 7450 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 7451 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 172:65be27845400 7452 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 172:65be27845400 7453 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 172:65be27845400 7454 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 172:65be27845400 7455 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 172:65be27845400 7456 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 172:65be27845400 7457 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 172:65be27845400 7458 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 172:65be27845400 7459 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 172:65be27845400 7460 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 172:65be27845400 7461 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 172:65be27845400 7462 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 172:65be27845400 7463 #define FLASH_OPTCR_nWRP_11 0x08000000U
AnnaBridge 172:65be27845400 7464 #define FLASH_OPTCR_DB1M_Pos (30U)
AnnaBridge 172:65be27845400 7465 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 7466 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
AnnaBridge 172:65be27845400 7467 #define FLASH_OPTCR_SPRMOD_Pos (31U)
AnnaBridge 172:65be27845400 7468 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7469 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
AnnaBridge 172:65be27845400 7470
AnnaBridge 172:65be27845400 7471 /****************** Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 172:65be27845400 7472 #define FLASH_OPTCR1_nWRP_Pos (16U)
AnnaBridge 172:65be27845400 7473 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 7474 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
AnnaBridge 172:65be27845400 7475 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7476 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7477 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7478 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7479 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7480 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7481 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7482 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 7483 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7484 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 7485 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7486 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7487
AnnaBridge 172:65be27845400 7488 /******************************************************************************/
AnnaBridge 172:65be27845400 7489 /* */
AnnaBridge 172:65be27845400 7490 /* Flexible Memory Controller */
AnnaBridge 172:65be27845400 7491 /* */
AnnaBridge 172:65be27845400 7492 /******************************************************************************/
AnnaBridge 172:65be27845400 7493 /****************** Bit definition for FMC_BCR1 register *******************/
AnnaBridge 172:65be27845400 7494 #define FMC_BCR1_MBKEN_Pos (0U)
AnnaBridge 172:65be27845400 7495 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7496 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 172:65be27845400 7497 #define FMC_BCR1_MUXEN_Pos (1U)
AnnaBridge 172:65be27845400 7498 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7499 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 172:65be27845400 7500
AnnaBridge 172:65be27845400 7501 #define FMC_BCR1_MTYP_Pos (2U)
AnnaBridge 172:65be27845400 7502 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 7503 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 172:65be27845400 7504 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7505 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7506
AnnaBridge 172:65be27845400 7507 #define FMC_BCR1_MWID_Pos (4U)
AnnaBridge 172:65be27845400 7508 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 7509 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 172:65be27845400 7510 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7511 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7512
AnnaBridge 172:65be27845400 7513 #define FMC_BCR1_FACCEN_Pos (6U)
AnnaBridge 172:65be27845400 7514 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7515 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 172:65be27845400 7516 #define FMC_BCR1_BURSTEN_Pos (8U)
AnnaBridge 172:65be27845400 7517 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7518 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 172:65be27845400 7519 #define FMC_BCR1_WAITPOL_Pos (9U)
AnnaBridge 172:65be27845400 7520 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7521 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 172:65be27845400 7522 #define FMC_BCR1_WRAPMOD_Pos (10U)
AnnaBridge 172:65be27845400 7523 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7524 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 172:65be27845400 7525 #define FMC_BCR1_WAITCFG_Pos (11U)
AnnaBridge 172:65be27845400 7526 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7527 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 172:65be27845400 7528 #define FMC_BCR1_WREN_Pos (12U)
AnnaBridge 172:65be27845400 7529 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7530 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
AnnaBridge 172:65be27845400 7531 #define FMC_BCR1_WAITEN_Pos (13U)
AnnaBridge 172:65be27845400 7532 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7533 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 172:65be27845400 7534 #define FMC_BCR1_EXTMOD_Pos (14U)
AnnaBridge 172:65be27845400 7535 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7536 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 172:65be27845400 7537 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
AnnaBridge 172:65be27845400 7538 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7539 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 172:65be27845400 7540 #define FMC_BCR1_CPSIZE_Pos (16U)
AnnaBridge 172:65be27845400 7541 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 7542 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 172:65be27845400 7543 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7544 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7545 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7546 #define FMC_BCR1_CBURSTRW_Pos (19U)
AnnaBridge 172:65be27845400 7547 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7548 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 172:65be27845400 7549 #define FMC_BCR1_CCLKEN_Pos (20U)
AnnaBridge 172:65be27845400 7550 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7551 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
AnnaBridge 172:65be27845400 7552
AnnaBridge 172:65be27845400 7553 /****************** Bit definition for FMC_BCR2 register *******************/
AnnaBridge 172:65be27845400 7554 #define FMC_BCR2_MBKEN_Pos (0U)
AnnaBridge 172:65be27845400 7555 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7556 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 172:65be27845400 7557 #define FMC_BCR2_MUXEN_Pos (1U)
AnnaBridge 172:65be27845400 7558 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7559 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 172:65be27845400 7560
AnnaBridge 172:65be27845400 7561 #define FMC_BCR2_MTYP_Pos (2U)
AnnaBridge 172:65be27845400 7562 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 7563 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 172:65be27845400 7564 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7565 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7566
AnnaBridge 172:65be27845400 7567 #define FMC_BCR2_MWID_Pos (4U)
AnnaBridge 172:65be27845400 7568 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 7569 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 172:65be27845400 7570 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7571 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7572
AnnaBridge 172:65be27845400 7573 #define FMC_BCR2_FACCEN_Pos (6U)
AnnaBridge 172:65be27845400 7574 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7575 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 172:65be27845400 7576 #define FMC_BCR2_BURSTEN_Pos (8U)
AnnaBridge 172:65be27845400 7577 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7578 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 172:65be27845400 7579 #define FMC_BCR2_WAITPOL_Pos (9U)
AnnaBridge 172:65be27845400 7580 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7581 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 172:65be27845400 7582 #define FMC_BCR2_WRAPMOD_Pos (10U)
AnnaBridge 172:65be27845400 7583 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7584 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 172:65be27845400 7585 #define FMC_BCR2_WAITCFG_Pos (11U)
AnnaBridge 172:65be27845400 7586 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7587 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 172:65be27845400 7588 #define FMC_BCR2_WREN_Pos (12U)
AnnaBridge 172:65be27845400 7589 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7590 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
AnnaBridge 172:65be27845400 7591 #define FMC_BCR2_WAITEN_Pos (13U)
AnnaBridge 172:65be27845400 7592 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7593 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 172:65be27845400 7594 #define FMC_BCR2_EXTMOD_Pos (14U)
AnnaBridge 172:65be27845400 7595 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7596 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 172:65be27845400 7597 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
AnnaBridge 172:65be27845400 7598 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7599 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 172:65be27845400 7600 #define FMC_BCR2_CPSIZE_Pos (16U)
AnnaBridge 172:65be27845400 7601 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 7602 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 172:65be27845400 7603 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7604 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7605 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7606 #define FMC_BCR2_CBURSTRW_Pos (19U)
AnnaBridge 172:65be27845400 7607 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7608 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 172:65be27845400 7609
AnnaBridge 172:65be27845400 7610 /****************** Bit definition for FMC_BCR3 register *******************/
AnnaBridge 172:65be27845400 7611 #define FMC_BCR3_MBKEN_Pos (0U)
AnnaBridge 172:65be27845400 7612 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7613 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 172:65be27845400 7614 #define FMC_BCR3_MUXEN_Pos (1U)
AnnaBridge 172:65be27845400 7615 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7616 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 172:65be27845400 7617
AnnaBridge 172:65be27845400 7618 #define FMC_BCR3_MTYP_Pos (2U)
AnnaBridge 172:65be27845400 7619 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 7620 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 172:65be27845400 7621 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7622 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7623
AnnaBridge 172:65be27845400 7624 #define FMC_BCR3_MWID_Pos (4U)
AnnaBridge 172:65be27845400 7625 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 7626 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 172:65be27845400 7627 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7628 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7629
AnnaBridge 172:65be27845400 7630 #define FMC_BCR3_FACCEN_Pos (6U)
AnnaBridge 172:65be27845400 7631 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7632 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 172:65be27845400 7633 #define FMC_BCR3_BURSTEN_Pos (8U)
AnnaBridge 172:65be27845400 7634 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7635 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 172:65be27845400 7636 #define FMC_BCR3_WAITPOL_Pos (9U)
AnnaBridge 172:65be27845400 7637 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7638 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 172:65be27845400 7639 #define FMC_BCR3_WRAPMOD_Pos (10U)
AnnaBridge 172:65be27845400 7640 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7641 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 172:65be27845400 7642 #define FMC_BCR3_WAITCFG_Pos (11U)
AnnaBridge 172:65be27845400 7643 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7644 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 172:65be27845400 7645 #define FMC_BCR3_WREN_Pos (12U)
AnnaBridge 172:65be27845400 7646 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7647 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
AnnaBridge 172:65be27845400 7648 #define FMC_BCR3_WAITEN_Pos (13U)
AnnaBridge 172:65be27845400 7649 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7650 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 172:65be27845400 7651 #define FMC_BCR3_EXTMOD_Pos (14U)
AnnaBridge 172:65be27845400 7652 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7653 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 172:65be27845400 7654 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
AnnaBridge 172:65be27845400 7655 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7656 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 172:65be27845400 7657 #define FMC_BCR3_CPSIZE_Pos (16U)
AnnaBridge 172:65be27845400 7658 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 7659 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 172:65be27845400 7660 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7661 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7662 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7663 #define FMC_BCR3_CBURSTRW_Pos (19U)
AnnaBridge 172:65be27845400 7664 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7665 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 172:65be27845400 7666
AnnaBridge 172:65be27845400 7667 /****************** Bit definition for FMC_BCR4 register *******************/
AnnaBridge 172:65be27845400 7668 #define FMC_BCR4_MBKEN_Pos (0U)
AnnaBridge 172:65be27845400 7669 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7670 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 172:65be27845400 7671 #define FMC_BCR4_MUXEN_Pos (1U)
AnnaBridge 172:65be27845400 7672 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7673 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 172:65be27845400 7674
AnnaBridge 172:65be27845400 7675 #define FMC_BCR4_MTYP_Pos (2U)
AnnaBridge 172:65be27845400 7676 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 7677 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 172:65be27845400 7678 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7679 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7680
AnnaBridge 172:65be27845400 7681 #define FMC_BCR4_MWID_Pos (4U)
AnnaBridge 172:65be27845400 7682 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 7683 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 172:65be27845400 7684 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7685 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7686
AnnaBridge 172:65be27845400 7687 #define FMC_BCR4_FACCEN_Pos (6U)
AnnaBridge 172:65be27845400 7688 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7689 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 172:65be27845400 7690 #define FMC_BCR4_BURSTEN_Pos (8U)
AnnaBridge 172:65be27845400 7691 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7692 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 172:65be27845400 7693 #define FMC_BCR4_WAITPOL_Pos (9U)
AnnaBridge 172:65be27845400 7694 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7695 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 172:65be27845400 7696 #define FMC_BCR4_WRAPMOD_Pos (10U)
AnnaBridge 172:65be27845400 7697 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7698 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 172:65be27845400 7699 #define FMC_BCR4_WAITCFG_Pos (11U)
AnnaBridge 172:65be27845400 7700 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7701 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 172:65be27845400 7702 #define FMC_BCR4_WREN_Pos (12U)
AnnaBridge 172:65be27845400 7703 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7704 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
AnnaBridge 172:65be27845400 7705 #define FMC_BCR4_WAITEN_Pos (13U)
AnnaBridge 172:65be27845400 7706 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7707 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 172:65be27845400 7708 #define FMC_BCR4_EXTMOD_Pos (14U)
AnnaBridge 172:65be27845400 7709 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7710 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 172:65be27845400 7711 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
AnnaBridge 172:65be27845400 7712 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7713 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 172:65be27845400 7714 #define FMC_BCR4_CPSIZE_Pos (16U)
AnnaBridge 172:65be27845400 7715 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 7716 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 172:65be27845400 7717 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7718 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7719 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7720 #define FMC_BCR4_CBURSTRW_Pos (19U)
AnnaBridge 172:65be27845400 7721 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7722 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 172:65be27845400 7723
AnnaBridge 172:65be27845400 7724 /****************** Bit definition for FMC_BTR1 register ******************/
AnnaBridge 172:65be27845400 7725 #define FMC_BTR1_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 7726 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7727 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 7728 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7729 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7730 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7731 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7732
AnnaBridge 172:65be27845400 7733 #define FMC_BTR1_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 7734 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 7735 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 7736 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7737 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7738 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7739 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7740
AnnaBridge 172:65be27845400 7741 #define FMC_BTR1_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 7742 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7743 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 7744 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7745 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7746 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7747 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7748 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7749 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7750 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7751 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7752
AnnaBridge 172:65be27845400 7753 #define FMC_BTR1_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 7754 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 7755 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 172:65be27845400 7756 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7757 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7758 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7759 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7760
AnnaBridge 172:65be27845400 7761 #define FMC_BTR1_CLKDIV_Pos (20U)
AnnaBridge 172:65be27845400 7762 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 7763 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 172:65be27845400 7764 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7765 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7766 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7767 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 7768
AnnaBridge 172:65be27845400 7769 #define FMC_BTR1_DATLAT_Pos (24U)
AnnaBridge 172:65be27845400 7770 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 7771 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 172:65be27845400 7772 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7773 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 7774 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7775 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7776
AnnaBridge 172:65be27845400 7777 #define FMC_BTR1_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 7778 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 7779 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 7780 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 7781 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 7782
AnnaBridge 172:65be27845400 7783 /****************** Bit definition for FMC_BTR2 register *******************/
AnnaBridge 172:65be27845400 7784 #define FMC_BTR2_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 7785 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7786 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 7787 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7788 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7789 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7790 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7791
AnnaBridge 172:65be27845400 7792 #define FMC_BTR2_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 7793 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 7794 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 7795 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7796 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7797 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7798 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7799
AnnaBridge 172:65be27845400 7800 #define FMC_BTR2_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 7801 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7802 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 7803 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7804 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7805 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7806 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7807 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7808 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7809 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7810 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7811
AnnaBridge 172:65be27845400 7812 #define FMC_BTR2_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 7813 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 7814 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 172:65be27845400 7815 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7816 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7817 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7818 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7819
AnnaBridge 172:65be27845400 7820 #define FMC_BTR2_CLKDIV_Pos (20U)
AnnaBridge 172:65be27845400 7821 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 7822 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 172:65be27845400 7823 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7824 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7825 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7826 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 7827
AnnaBridge 172:65be27845400 7828 #define FMC_BTR2_DATLAT_Pos (24U)
AnnaBridge 172:65be27845400 7829 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 7830 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 172:65be27845400 7831 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7832 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 7833 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7834 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7835
AnnaBridge 172:65be27845400 7836 #define FMC_BTR2_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 7837 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 7838 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 7839 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 7840 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 7841
AnnaBridge 172:65be27845400 7842 /******************* Bit definition for FMC_BTR3 register *******************/
AnnaBridge 172:65be27845400 7843 #define FMC_BTR3_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 7844 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7845 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 7846 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7847 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7848 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7849 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7850
AnnaBridge 172:65be27845400 7851 #define FMC_BTR3_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 7852 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 7853 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 7854 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7855 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7856 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7857 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7858
AnnaBridge 172:65be27845400 7859 #define FMC_BTR3_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 7860 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7861 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 7862 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7863 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7864 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7865 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7866 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7867 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7868 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7869 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7870
AnnaBridge 172:65be27845400 7871 #define FMC_BTR3_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 7872 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 7873 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 172:65be27845400 7874 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7875 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7876 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7877 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7878
AnnaBridge 172:65be27845400 7879 #define FMC_BTR3_CLKDIV_Pos (20U)
AnnaBridge 172:65be27845400 7880 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 7881 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 172:65be27845400 7882 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7883 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7884 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7885 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 7886
AnnaBridge 172:65be27845400 7887 #define FMC_BTR3_DATLAT_Pos (24U)
AnnaBridge 172:65be27845400 7888 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 7889 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 172:65be27845400 7890 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7891 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 7892 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7893 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7894
AnnaBridge 172:65be27845400 7895 #define FMC_BTR3_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 7896 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 7897 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 7898 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 7899 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 7900
AnnaBridge 172:65be27845400 7901 /****************** Bit definition for FMC_BTR4 register *******************/
AnnaBridge 172:65be27845400 7902 #define FMC_BTR4_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 7903 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7904 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 7905 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7906 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7907 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7908 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7909
AnnaBridge 172:65be27845400 7910 #define FMC_BTR4_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 7911 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 7912 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 7913 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7914 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7915 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7916 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7917
AnnaBridge 172:65be27845400 7918 #define FMC_BTR4_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 7919 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7920 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 7921 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7922 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7923 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7924 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7925 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7926 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7927 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7928 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7929
AnnaBridge 172:65be27845400 7930 #define FMC_BTR4_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 7931 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 7932 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 172:65be27845400 7933 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7934 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7935 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7936 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7937
AnnaBridge 172:65be27845400 7938 #define FMC_BTR4_CLKDIV_Pos (20U)
AnnaBridge 172:65be27845400 7939 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 7940 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 172:65be27845400 7941 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7942 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7943 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 7944 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 7945
AnnaBridge 172:65be27845400 7946 #define FMC_BTR4_DATLAT_Pos (24U)
AnnaBridge 172:65be27845400 7947 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 7948 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 172:65be27845400 7949 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7950 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 7951 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7952 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7953
AnnaBridge 172:65be27845400 7954 #define FMC_BTR4_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 7955 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 7956 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 7957 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 7958 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 7959
AnnaBridge 172:65be27845400 7960 /****************** Bit definition for FMC_BWTR1 register ******************/
AnnaBridge 172:65be27845400 7961 #define FMC_BWTR1_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 7962 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7963 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 7964 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7965 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7966 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7967 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7968
AnnaBridge 172:65be27845400 7969 #define FMC_BWTR1_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 7970 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 7971 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 7972 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7973 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7974 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7975 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7976
AnnaBridge 172:65be27845400 7977 #define FMC_BWTR1_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 7978 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7979 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 7980 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7981 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7982 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7983 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7984 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7985 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7986 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7987 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7988
AnnaBridge 172:65be27845400 7989 #define FMC_BWTR1_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 7990 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 7991 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 172:65be27845400 7992 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7993 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7994 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7995 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7996
AnnaBridge 172:65be27845400 7997 #define FMC_BWTR1_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 7998 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 7999 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 8000 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8001 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8002
AnnaBridge 172:65be27845400 8003 /****************** Bit definition for FMC_BWTR2 register ******************/
AnnaBridge 172:65be27845400 8004 #define FMC_BWTR2_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 8005 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 8006 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 8007 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8008 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8009 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8010 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8011
AnnaBridge 172:65be27845400 8012 #define FMC_BWTR2_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 8013 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 8014 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 8015 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8016 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8017 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8018 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8019
AnnaBridge 172:65be27845400 8020 #define FMC_BWTR2_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 8021 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8022 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 8023 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8024 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8025 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8026 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8027 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8028 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8029 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8030 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8031
AnnaBridge 172:65be27845400 8032 #define FMC_BWTR2_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 8033 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 8034 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 172:65be27845400 8035 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8036 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8037 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8038 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8039
AnnaBridge 172:65be27845400 8040 #define FMC_BWTR2_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 8041 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 8042 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 8043 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8044 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8045
AnnaBridge 172:65be27845400 8046 /****************** Bit definition for FMC_BWTR3 register ******************/
AnnaBridge 172:65be27845400 8047 #define FMC_BWTR3_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 8048 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 8049 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 8050 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8051 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8052 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8053 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8054
AnnaBridge 172:65be27845400 8055 #define FMC_BWTR3_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 8056 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 8057 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 8058 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8059 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8060 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8061 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8062
AnnaBridge 172:65be27845400 8063 #define FMC_BWTR3_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 8064 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8065 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 8066 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8067 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8068 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8069 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8070 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8071 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8072 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8073 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8074
AnnaBridge 172:65be27845400 8075 #define FMC_BWTR3_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 8076 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 8077 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 172:65be27845400 8078 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8079 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8080 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8081 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8082
AnnaBridge 172:65be27845400 8083 #define FMC_BWTR3_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 8084 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 8085 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 8086 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8087 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8088
AnnaBridge 172:65be27845400 8089 /****************** Bit definition for FMC_BWTR4 register ******************/
AnnaBridge 172:65be27845400 8090 #define FMC_BWTR4_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 8091 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 8092 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 8093 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8094 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8095 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8096 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8097
AnnaBridge 172:65be27845400 8098 #define FMC_BWTR4_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 8099 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 8100 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 8101 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8102 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8103 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8104 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8105
AnnaBridge 172:65be27845400 8106 #define FMC_BWTR4_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 8107 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8108 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 8109 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8110 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8111 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8112 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8113 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8114 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8115 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8116 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8117
AnnaBridge 172:65be27845400 8118 #define FMC_BWTR4_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 8119 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 8120 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 172:65be27845400 8121 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8122 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8123 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8124 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8125
AnnaBridge 172:65be27845400 8126 #define FMC_BWTR4_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 8127 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 8128 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 8129 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8130 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8131
AnnaBridge 172:65be27845400 8132 /****************** Bit definition for FMC_PCR2 register *******************/
AnnaBridge 172:65be27845400 8133
AnnaBridge 172:65be27845400 8134 #define FMC_PCR2_PWAITEN_Pos (1U)
AnnaBridge 172:65be27845400 8135 #define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8136 #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 172:65be27845400 8137 #define FMC_PCR2_PBKEN_Pos (2U)
AnnaBridge 172:65be27845400 8138 #define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8139 #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 172:65be27845400 8140 #define FMC_PCR2_PTYP_Pos (3U)
AnnaBridge 172:65be27845400 8141 #define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8142 #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
AnnaBridge 172:65be27845400 8143
AnnaBridge 172:65be27845400 8144 #define FMC_PCR2_PWID_Pos (4U)
AnnaBridge 172:65be27845400 8145 #define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8146 #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 172:65be27845400 8147 #define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8148 #define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8149
AnnaBridge 172:65be27845400 8150 #define FMC_PCR2_ECCEN_Pos (6U)
AnnaBridge 172:65be27845400 8151 #define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8152 #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 172:65be27845400 8153
AnnaBridge 172:65be27845400 8154 #define FMC_PCR2_TCLR_Pos (9U)
AnnaBridge 172:65be27845400 8155 #define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 172:65be27845400 8156 #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 172:65be27845400 8157 #define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8158 #define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8159 #define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8160 #define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8161
AnnaBridge 172:65be27845400 8162 #define FMC_PCR2_TAR_Pos (13U)
AnnaBridge 172:65be27845400 8163 #define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 8164 #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 172:65be27845400 8165 #define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8166 #define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8167 #define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8168 #define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8169
AnnaBridge 172:65be27845400 8170 #define FMC_PCR2_ECCPS_Pos (17U)
AnnaBridge 172:65be27845400 8171 #define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 8172 #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
AnnaBridge 172:65be27845400 8173 #define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8174 #define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8175 #define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8176
AnnaBridge 172:65be27845400 8177 /****************** Bit definition for FMC_PCR3 register *******************/
AnnaBridge 172:65be27845400 8178 #define FMC_PCR3_PWAITEN_Pos (1U)
AnnaBridge 172:65be27845400 8179 #define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8180 #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 172:65be27845400 8181 #define FMC_PCR3_PBKEN_Pos (2U)
AnnaBridge 172:65be27845400 8182 #define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8183 #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 172:65be27845400 8184 #define FMC_PCR3_PTYP_Pos (3U)
AnnaBridge 172:65be27845400 8185 #define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8186 #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
AnnaBridge 172:65be27845400 8187
AnnaBridge 172:65be27845400 8188 #define FMC_PCR3_PWID_Pos (4U)
AnnaBridge 172:65be27845400 8189 #define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8190 #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 172:65be27845400 8191 #define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8192 #define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8193
AnnaBridge 172:65be27845400 8194 #define FMC_PCR3_ECCEN_Pos (6U)
AnnaBridge 172:65be27845400 8195 #define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8196 #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 172:65be27845400 8197
AnnaBridge 172:65be27845400 8198 #define FMC_PCR3_TCLR_Pos (9U)
AnnaBridge 172:65be27845400 8199 #define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 172:65be27845400 8200 #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 172:65be27845400 8201 #define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8202 #define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8203 #define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8204 #define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8205
AnnaBridge 172:65be27845400 8206 #define FMC_PCR3_TAR_Pos (13U)
AnnaBridge 172:65be27845400 8207 #define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 8208 #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 172:65be27845400 8209 #define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8210 #define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8211 #define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8212 #define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8213
AnnaBridge 172:65be27845400 8214 #define FMC_PCR3_ECCPS_Pos (17U)
AnnaBridge 172:65be27845400 8215 #define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 8216 #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 172:65be27845400 8217 #define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8218 #define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8219 #define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8220
AnnaBridge 172:65be27845400 8221 /****************** Bit definition for FMC_PCR4 register *******************/
AnnaBridge 172:65be27845400 8222 #define FMC_PCR4_PWAITEN_Pos (1U)
AnnaBridge 172:65be27845400 8223 #define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8224 #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 172:65be27845400 8225 #define FMC_PCR4_PBKEN_Pos (2U)
AnnaBridge 172:65be27845400 8226 #define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8227 #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 172:65be27845400 8228 #define FMC_PCR4_PTYP_Pos (3U)
AnnaBridge 172:65be27845400 8229 #define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8230 #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
AnnaBridge 172:65be27845400 8231
AnnaBridge 172:65be27845400 8232 #define FMC_PCR4_PWID_Pos (4U)
AnnaBridge 172:65be27845400 8233 #define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8234 #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 172:65be27845400 8235 #define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8236 #define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8237
AnnaBridge 172:65be27845400 8238 #define FMC_PCR4_ECCEN_Pos (6U)
AnnaBridge 172:65be27845400 8239 #define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8240 #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 172:65be27845400 8241
AnnaBridge 172:65be27845400 8242 #define FMC_PCR4_TCLR_Pos (9U)
AnnaBridge 172:65be27845400 8243 #define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 172:65be27845400 8244 #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 172:65be27845400 8245 #define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8246 #define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8247 #define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8248 #define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8249
AnnaBridge 172:65be27845400 8250 #define FMC_PCR4_TAR_Pos (13U)
AnnaBridge 172:65be27845400 8251 #define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 8252 #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 172:65be27845400 8253 #define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8254 #define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8255 #define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8256 #define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8257
AnnaBridge 172:65be27845400 8258 #define FMC_PCR4_ECCPS_Pos (17U)
AnnaBridge 172:65be27845400 8259 #define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 8260 #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 172:65be27845400 8261 #define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8262 #define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8263 #define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8264
AnnaBridge 172:65be27845400 8265 /******************* Bit definition for FMC_SR2 register *******************/
AnnaBridge 172:65be27845400 8266 #define FMC_SR2_IRS_Pos (0U)
AnnaBridge 172:65be27845400 8267 #define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8268 #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 172:65be27845400 8269 #define FMC_SR2_ILS_Pos (1U)
AnnaBridge 172:65be27845400 8270 #define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8271 #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 172:65be27845400 8272 #define FMC_SR2_IFS_Pos (2U)
AnnaBridge 172:65be27845400 8273 #define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8274 #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 172:65be27845400 8275 #define FMC_SR2_IREN_Pos (3U)
AnnaBridge 172:65be27845400 8276 #define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8277 #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 172:65be27845400 8278 #define FMC_SR2_ILEN_Pos (4U)
AnnaBridge 172:65be27845400 8279 #define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8280 #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 172:65be27845400 8281 #define FMC_SR2_IFEN_Pos (5U)
AnnaBridge 172:65be27845400 8282 #define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8283 #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 172:65be27845400 8284 #define FMC_SR2_FEMPT_Pos (6U)
AnnaBridge 172:65be27845400 8285 #define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8286 #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 172:65be27845400 8287
AnnaBridge 172:65be27845400 8288 /******************* Bit definition for FMC_SR3 register *******************/
AnnaBridge 172:65be27845400 8289 #define FMC_SR3_IRS_Pos (0U)
AnnaBridge 172:65be27845400 8290 #define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8291 #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 172:65be27845400 8292 #define FMC_SR3_ILS_Pos (1U)
AnnaBridge 172:65be27845400 8293 #define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8294 #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 172:65be27845400 8295 #define FMC_SR3_IFS_Pos (2U)
AnnaBridge 172:65be27845400 8296 #define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8297 #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 172:65be27845400 8298 #define FMC_SR3_IREN_Pos (3U)
AnnaBridge 172:65be27845400 8299 #define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8300 #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 172:65be27845400 8301 #define FMC_SR3_ILEN_Pos (4U)
AnnaBridge 172:65be27845400 8302 #define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8303 #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 172:65be27845400 8304 #define FMC_SR3_IFEN_Pos (5U)
AnnaBridge 172:65be27845400 8305 #define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8306 #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 172:65be27845400 8307 #define FMC_SR3_FEMPT_Pos (6U)
AnnaBridge 172:65be27845400 8308 #define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8309 #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 172:65be27845400 8310
AnnaBridge 172:65be27845400 8311 /******************* Bit definition for FMC_SR4 register *******************/
AnnaBridge 172:65be27845400 8312 #define FMC_SR4_IRS_Pos (0U)
AnnaBridge 172:65be27845400 8313 #define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8314 #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 172:65be27845400 8315 #define FMC_SR4_ILS_Pos (1U)
AnnaBridge 172:65be27845400 8316 #define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8317 #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 172:65be27845400 8318 #define FMC_SR4_IFS_Pos (2U)
AnnaBridge 172:65be27845400 8319 #define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8320 #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 172:65be27845400 8321 #define FMC_SR4_IREN_Pos (3U)
AnnaBridge 172:65be27845400 8322 #define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8323 #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 172:65be27845400 8324 #define FMC_SR4_ILEN_Pos (4U)
AnnaBridge 172:65be27845400 8325 #define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8326 #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 172:65be27845400 8327 #define FMC_SR4_IFEN_Pos (5U)
AnnaBridge 172:65be27845400 8328 #define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8329 #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 172:65be27845400 8330 #define FMC_SR4_FEMPT_Pos (6U)
AnnaBridge 172:65be27845400 8331 #define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8332 #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 172:65be27845400 8333
AnnaBridge 172:65be27845400 8334 /****************** Bit definition for FMC_PMEM2 register ******************/
AnnaBridge 172:65be27845400 8335 #define FMC_PMEM2_MEMSET2_Pos (0U)
AnnaBridge 172:65be27845400 8336 #define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8337 #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
AnnaBridge 172:65be27845400 8338 #define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8339 #define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8340 #define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8341 #define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8342 #define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8343 #define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8344 #define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8345 #define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8346
AnnaBridge 172:65be27845400 8347 #define FMC_PMEM2_MEMWAIT2_Pos (8U)
AnnaBridge 172:65be27845400 8348 #define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8349 #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
AnnaBridge 172:65be27845400 8350 #define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8351 #define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8352 #define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8353 #define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8354 #define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8355 #define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8356 #define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8357 #define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8358
AnnaBridge 172:65be27845400 8359 #define FMC_PMEM2_MEMHOLD2_Pos (16U)
AnnaBridge 172:65be27845400 8360 #define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 8361 #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
AnnaBridge 172:65be27845400 8362 #define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8363 #define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8364 #define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8365 #define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8366 #define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8367 #define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8368 #define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8369 #define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8370
AnnaBridge 172:65be27845400 8371 #define FMC_PMEM2_MEMHIZ2_Pos (24U)
AnnaBridge 172:65be27845400 8372 #define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8373 #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
AnnaBridge 172:65be27845400 8374 #define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8375 #define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8376 #define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8377 #define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8378 #define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8379 #define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8380 #define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 8381 #define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8382
AnnaBridge 172:65be27845400 8383 /****************** Bit definition for FMC_PMEM3 register ******************/
AnnaBridge 172:65be27845400 8384 #define FMC_PMEM3_MEMSET3_Pos (0U)
AnnaBridge 172:65be27845400 8385 #define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8386 #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
AnnaBridge 172:65be27845400 8387 #define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8388 #define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8389 #define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8390 #define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8391 #define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8392 #define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8393 #define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8394 #define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8395
AnnaBridge 172:65be27845400 8396 #define FMC_PMEM3_MEMWAIT3_Pos (8U)
AnnaBridge 172:65be27845400 8397 #define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8398 #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
AnnaBridge 172:65be27845400 8399 #define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8400 #define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8401 #define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8402 #define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8403 #define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8404 #define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8405 #define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8406 #define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8407
AnnaBridge 172:65be27845400 8408 #define FMC_PMEM3_MEMHOLD3_Pos (16U)
AnnaBridge 172:65be27845400 8409 #define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 8410 #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
AnnaBridge 172:65be27845400 8411 #define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8412 #define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8413 #define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8414 #define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8415 #define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8416 #define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8417 #define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8418 #define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8419
AnnaBridge 172:65be27845400 8420 #define FMC_PMEM3_MEMHIZ3_Pos (24U)
AnnaBridge 172:65be27845400 8421 #define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8422 #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
AnnaBridge 172:65be27845400 8423 #define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8424 #define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8425 #define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8426 #define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8427 #define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8428 #define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8429 #define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 8430 #define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8431
AnnaBridge 172:65be27845400 8432 /****************** Bit definition for FMC_PMEM4 register ******************/
AnnaBridge 172:65be27845400 8433 #define FMC_PMEM4_MEMSET4_Pos (0U)
AnnaBridge 172:65be27845400 8434 #define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8435 #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
AnnaBridge 172:65be27845400 8436 #define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8437 #define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8438 #define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8439 #define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8440 #define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8441 #define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8442 #define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8443 #define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8444
AnnaBridge 172:65be27845400 8445 #define FMC_PMEM4_MEMWAIT4_Pos (8U)
AnnaBridge 172:65be27845400 8446 #define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8447 #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
AnnaBridge 172:65be27845400 8448 #define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8449 #define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8450 #define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8451 #define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8452 #define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8453 #define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8454 #define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8455 #define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8456
AnnaBridge 172:65be27845400 8457 #define FMC_PMEM4_MEMHOLD4_Pos (16U)
AnnaBridge 172:65be27845400 8458 #define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 8459 #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
AnnaBridge 172:65be27845400 8460 #define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8461 #define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8462 #define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8463 #define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8464 #define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8465 #define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8466 #define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8467 #define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8468
AnnaBridge 172:65be27845400 8469 #define FMC_PMEM4_MEMHIZ4_Pos (24U)
AnnaBridge 172:65be27845400 8470 #define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8471 #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
AnnaBridge 172:65be27845400 8472 #define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8473 #define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8474 #define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8475 #define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8476 #define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8477 #define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8478 #define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 8479 #define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8480
AnnaBridge 172:65be27845400 8481 /****************** Bit definition for FMC_PATT2 register ******************/
AnnaBridge 172:65be27845400 8482 #define FMC_PATT2_ATTSET2_Pos (0U)
AnnaBridge 172:65be27845400 8483 #define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8484 #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
AnnaBridge 172:65be27845400 8485 #define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8486 #define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8487 #define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8488 #define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8489 #define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8490 #define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8491 #define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8492 #define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8493
AnnaBridge 172:65be27845400 8494 #define FMC_PATT2_ATTWAIT2_Pos (8U)
AnnaBridge 172:65be27845400 8495 #define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8496 #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
AnnaBridge 172:65be27845400 8497 #define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8498 #define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8499 #define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8500 #define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8501 #define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8502 #define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8503 #define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8504 #define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8505
AnnaBridge 172:65be27845400 8506 #define FMC_PATT2_ATTHOLD2_Pos (16U)
AnnaBridge 172:65be27845400 8507 #define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 8508 #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
AnnaBridge 172:65be27845400 8509 #define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8510 #define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8511 #define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8512 #define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8513 #define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8514 #define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8515 #define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8516 #define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8517
AnnaBridge 172:65be27845400 8518 #define FMC_PATT2_ATTHIZ2_Pos (24U)
AnnaBridge 172:65be27845400 8519 #define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8520 #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
AnnaBridge 172:65be27845400 8521 #define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8522 #define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8523 #define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8524 #define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8525 #define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8526 #define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8527 #define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 8528 #define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8529
AnnaBridge 172:65be27845400 8530 /****************** Bit definition for FMC_PATT3 register ******************/
AnnaBridge 172:65be27845400 8531 #define FMC_PATT3_ATTSET3_Pos (0U)
AnnaBridge 172:65be27845400 8532 #define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8533 #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
AnnaBridge 172:65be27845400 8534 #define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8535 #define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8536 #define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8537 #define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8538 #define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8539 #define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8540 #define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8541 #define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8542
AnnaBridge 172:65be27845400 8543 #define FMC_PATT3_ATTWAIT3_Pos (8U)
AnnaBridge 172:65be27845400 8544 #define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8545 #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
AnnaBridge 172:65be27845400 8546 #define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8547 #define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8548 #define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8549 #define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8550 #define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8551 #define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8552 #define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8553 #define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8554
AnnaBridge 172:65be27845400 8555 #define FMC_PATT3_ATTHOLD3_Pos (16U)
AnnaBridge 172:65be27845400 8556 #define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 8557 #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
AnnaBridge 172:65be27845400 8558 #define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8559 #define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8560 #define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8561 #define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8562 #define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8563 #define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8564 #define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8565 #define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8566
AnnaBridge 172:65be27845400 8567 #define FMC_PATT3_ATTHIZ3_Pos (24U)
AnnaBridge 172:65be27845400 8568 #define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8569 #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
AnnaBridge 172:65be27845400 8570 #define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8571 #define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8572 #define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8573 #define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8574 #define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8575 #define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8576 #define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 8577 #define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8578
AnnaBridge 172:65be27845400 8579 /****************** Bit definition for FMC_PATT4 register ******************/
AnnaBridge 172:65be27845400 8580 #define FMC_PATT4_ATTSET4_Pos (0U)
AnnaBridge 172:65be27845400 8581 #define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8582 #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
AnnaBridge 172:65be27845400 8583 #define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8584 #define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8585 #define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8586 #define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8587 #define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8588 #define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8589 #define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8590 #define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8591
AnnaBridge 172:65be27845400 8592 #define FMC_PATT4_ATTWAIT4_Pos (8U)
AnnaBridge 172:65be27845400 8593 #define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8594 #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
AnnaBridge 172:65be27845400 8595 #define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8596 #define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8597 #define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8598 #define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8599 #define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8600 #define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8601 #define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8602 #define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8603
AnnaBridge 172:65be27845400 8604 #define FMC_PATT4_ATTHOLD4_Pos (16U)
AnnaBridge 172:65be27845400 8605 #define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 8606 #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
AnnaBridge 172:65be27845400 8607 #define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8608 #define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8609 #define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8610 #define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8611 #define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8612 #define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8613 #define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8614 #define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8615
AnnaBridge 172:65be27845400 8616 #define FMC_PATT4_ATTHIZ4_Pos (24U)
AnnaBridge 172:65be27845400 8617 #define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8618 #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
AnnaBridge 172:65be27845400 8619 #define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8620 #define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8621 #define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8622 #define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8623 #define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8624 #define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8625 #define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 8626 #define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8627
AnnaBridge 172:65be27845400 8628 /****************** Bit definition for FMC_PIO4 register *******************/
AnnaBridge 172:65be27845400 8629 #define FMC_PIO4_IOSET4_Pos (0U)
AnnaBridge 172:65be27845400 8630 #define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8631 #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
AnnaBridge 172:65be27845400 8632 #define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8633 #define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8634 #define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8635 #define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8636 #define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8637 #define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8638 #define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8639 #define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8640
AnnaBridge 172:65be27845400 8641 #define FMC_PIO4_IOWAIT4_Pos (8U)
AnnaBridge 172:65be27845400 8642 #define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 8643 #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
AnnaBridge 172:65be27845400 8644 #define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8645 #define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8646 #define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8647 #define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8648 #define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8649 #define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8650 #define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8651 #define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8652
AnnaBridge 172:65be27845400 8653 #define FMC_PIO4_IOHOLD4_Pos (16U)
AnnaBridge 172:65be27845400 8654 #define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 8655 #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
AnnaBridge 172:65be27845400 8656 #define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8657 #define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8658 #define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8659 #define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8660 #define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8661 #define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8662 #define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8663 #define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8664
AnnaBridge 172:65be27845400 8665 #define FMC_PIO4_IOHIZ4_Pos (24U)
AnnaBridge 172:65be27845400 8666 #define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8667 #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
AnnaBridge 172:65be27845400 8668 #define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8669 #define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8670 #define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8671 #define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8672 #define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8673 #define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 8674 #define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 8675 #define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8676
AnnaBridge 172:65be27845400 8677
AnnaBridge 172:65be27845400 8678 /****************** Bit definition for FMC_ECCR2 register ******************/
AnnaBridge 172:65be27845400 8679 #define FMC_ECCR2_ECC2_Pos (0U)
AnnaBridge 172:65be27845400 8680 #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8681 #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
AnnaBridge 172:65be27845400 8682
AnnaBridge 172:65be27845400 8683 /****************** Bit definition for FMC_ECCR3 register ******************/
AnnaBridge 172:65be27845400 8684 #define FMC_ECCR3_ECC3_Pos (0U)
AnnaBridge 172:65be27845400 8685 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8686 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
AnnaBridge 172:65be27845400 8687
AnnaBridge 172:65be27845400 8688 /****************** Bit definition for FMC_SDCR1 register ******************/
AnnaBridge 172:65be27845400 8689 #define FMC_SDCR1_NC_Pos (0U)
AnnaBridge 172:65be27845400 8690 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 8691 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 172:65be27845400 8692 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8693 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8694
AnnaBridge 172:65be27845400 8695 #define FMC_SDCR1_NR_Pos (2U)
AnnaBridge 172:65be27845400 8696 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 8697 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 172:65be27845400 8698 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8699 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8700
AnnaBridge 172:65be27845400 8701 #define FMC_SDCR1_MWID_Pos (4U)
AnnaBridge 172:65be27845400 8702 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8703 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 172:65be27845400 8704 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8705 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8706
AnnaBridge 172:65be27845400 8707 #define FMC_SDCR1_NB_Pos (6U)
AnnaBridge 172:65be27845400 8708 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8709 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
AnnaBridge 172:65be27845400 8710
AnnaBridge 172:65be27845400 8711 #define FMC_SDCR1_CAS_Pos (7U)
AnnaBridge 172:65be27845400 8712 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
AnnaBridge 172:65be27845400 8713 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 172:65be27845400 8714 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8715 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8716
AnnaBridge 172:65be27845400 8717 #define FMC_SDCR1_WP_Pos (9U)
AnnaBridge 172:65be27845400 8718 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8719 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
AnnaBridge 172:65be27845400 8720
AnnaBridge 172:65be27845400 8721 #define FMC_SDCR1_SDCLK_Pos (10U)
AnnaBridge 172:65be27845400 8722 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 8723 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
AnnaBridge 172:65be27845400 8724 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8725 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8726
AnnaBridge 172:65be27845400 8727 #define FMC_SDCR1_RBURST_Pos (12U)
AnnaBridge 172:65be27845400 8728 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8729 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
AnnaBridge 172:65be27845400 8730
AnnaBridge 172:65be27845400 8731 #define FMC_SDCR1_RPIPE_Pos (13U)
AnnaBridge 172:65be27845400 8732 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 8733 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
AnnaBridge 172:65be27845400 8734 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8735 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8736
AnnaBridge 172:65be27845400 8737 /****************** Bit definition for FMC_SDCR2 register ******************/
AnnaBridge 172:65be27845400 8738 #define FMC_SDCR2_NC_Pos (0U)
AnnaBridge 172:65be27845400 8739 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 8740 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 172:65be27845400 8741 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8742 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8743
AnnaBridge 172:65be27845400 8744 #define FMC_SDCR2_NR_Pos (2U)
AnnaBridge 172:65be27845400 8745 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 8746 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 172:65be27845400 8747 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8748 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8749
AnnaBridge 172:65be27845400 8750 #define FMC_SDCR2_MWID_Pos (4U)
AnnaBridge 172:65be27845400 8751 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8752 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 172:65be27845400 8753 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8754 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8755
AnnaBridge 172:65be27845400 8756 #define FMC_SDCR2_NB_Pos (6U)
AnnaBridge 172:65be27845400 8757 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8758 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
AnnaBridge 172:65be27845400 8759
AnnaBridge 172:65be27845400 8760 #define FMC_SDCR2_CAS_Pos (7U)
AnnaBridge 172:65be27845400 8761 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
AnnaBridge 172:65be27845400 8762 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 172:65be27845400 8763 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8764 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8765
AnnaBridge 172:65be27845400 8766 #define FMC_SDCR2_WP_Pos (9U)
AnnaBridge 172:65be27845400 8767 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8768 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
AnnaBridge 172:65be27845400 8769
AnnaBridge 172:65be27845400 8770 #define FMC_SDCR2_SDCLK_Pos (10U)
AnnaBridge 172:65be27845400 8771 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 8772 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
AnnaBridge 172:65be27845400 8773 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8774 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8775
AnnaBridge 172:65be27845400 8776 #define FMC_SDCR2_RBURST_Pos (12U)
AnnaBridge 172:65be27845400 8777 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8778 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
AnnaBridge 172:65be27845400 8779
AnnaBridge 172:65be27845400 8780 #define FMC_SDCR2_RPIPE_Pos (13U)
AnnaBridge 172:65be27845400 8781 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 8782 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
AnnaBridge 172:65be27845400 8783 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8784 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8785
AnnaBridge 172:65be27845400 8786 /****************** Bit definition for FMC_SDTR1 register ******************/
AnnaBridge 172:65be27845400 8787 #define FMC_SDTR1_TMRD_Pos (0U)
AnnaBridge 172:65be27845400 8788 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 8789 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 172:65be27845400 8790 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8791 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8792 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8793 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8794
AnnaBridge 172:65be27845400 8795 #define FMC_SDTR1_TXSR_Pos (4U)
AnnaBridge 172:65be27845400 8796 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 8797 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 172:65be27845400 8798 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8799 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8800 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8801 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8802
AnnaBridge 172:65be27845400 8803 #define FMC_SDTR1_TRAS_Pos (8U)
AnnaBridge 172:65be27845400 8804 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 8805 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 172:65be27845400 8806 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8807 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8808 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8809 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8810
AnnaBridge 172:65be27845400 8811 #define FMC_SDTR1_TRC_Pos (12U)
AnnaBridge 172:65be27845400 8812 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 8813 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 172:65be27845400 8814 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8815 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8816 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8817
AnnaBridge 172:65be27845400 8818 #define FMC_SDTR1_TWR_Pos (16U)
AnnaBridge 172:65be27845400 8819 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 8820 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 172:65be27845400 8821 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8822 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8823 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8824
AnnaBridge 172:65be27845400 8825 #define FMC_SDTR1_TRP_Pos (20U)
AnnaBridge 172:65be27845400 8826 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 8827 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 172:65be27845400 8828 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8829 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8830 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8831
AnnaBridge 172:65be27845400 8832 #define FMC_SDTR1_TRCD_Pos (24U)
AnnaBridge 172:65be27845400 8833 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 8834 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 172:65be27845400 8835 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8836 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8837 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8838
AnnaBridge 172:65be27845400 8839 /****************** Bit definition for FMC_SDTR2 register ******************/
AnnaBridge 172:65be27845400 8840 #define FMC_SDTR2_TMRD_Pos (0U)
AnnaBridge 172:65be27845400 8841 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 8842 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 172:65be27845400 8843 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8844 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8845 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8846 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8847
AnnaBridge 172:65be27845400 8848 #define FMC_SDTR2_TXSR_Pos (4U)
AnnaBridge 172:65be27845400 8849 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 8850 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 172:65be27845400 8851 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8852 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8853 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8854 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8855
AnnaBridge 172:65be27845400 8856 #define FMC_SDTR2_TRAS_Pos (8U)
AnnaBridge 172:65be27845400 8857 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 8858 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 172:65be27845400 8859 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8860 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8861 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8862 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8863
AnnaBridge 172:65be27845400 8864 #define FMC_SDTR2_TRC_Pos (12U)
AnnaBridge 172:65be27845400 8865 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 8866 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 172:65be27845400 8867 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8868 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8869 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8870
AnnaBridge 172:65be27845400 8871 #define FMC_SDTR2_TWR_Pos (16U)
AnnaBridge 172:65be27845400 8872 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 8873 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 172:65be27845400 8874 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8875 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8876 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8877
AnnaBridge 172:65be27845400 8878 #define FMC_SDTR2_TRP_Pos (20U)
AnnaBridge 172:65be27845400 8879 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 8880 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 172:65be27845400 8881 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8882 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8883 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8884
AnnaBridge 172:65be27845400 8885 #define FMC_SDTR2_TRCD_Pos (24U)
AnnaBridge 172:65be27845400 8886 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 8887 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 172:65be27845400 8888 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8889 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8890 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8891
AnnaBridge 172:65be27845400 8892 /****************** Bit definition for FMC_SDCMR register ******************/
AnnaBridge 172:65be27845400 8893 #define FMC_SDCMR_MODE_Pos (0U)
AnnaBridge 172:65be27845400 8894 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 8895 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
AnnaBridge 172:65be27845400 8896 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8897 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8898 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8899
AnnaBridge 172:65be27845400 8900 #define FMC_SDCMR_CTB2_Pos (3U)
AnnaBridge 172:65be27845400 8901 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8902 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
AnnaBridge 172:65be27845400 8903
AnnaBridge 172:65be27845400 8904 #define FMC_SDCMR_CTB1_Pos (4U)
AnnaBridge 172:65be27845400 8905 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8906 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
AnnaBridge 172:65be27845400 8907
AnnaBridge 172:65be27845400 8908 #define FMC_SDCMR_NRFS_Pos (5U)
AnnaBridge 172:65be27845400 8909 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
AnnaBridge 172:65be27845400 8910 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
AnnaBridge 172:65be27845400 8911 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8912 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8913 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8914 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8915
AnnaBridge 172:65be27845400 8916 #define FMC_SDCMR_MRD_Pos (9U)
AnnaBridge 172:65be27845400 8917 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
AnnaBridge 172:65be27845400 8918 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
AnnaBridge 172:65be27845400 8919
AnnaBridge 172:65be27845400 8920 /****************** Bit definition for FMC_SDRTR register ******************/
AnnaBridge 172:65be27845400 8921 #define FMC_SDRTR_CRE_Pos (0U)
AnnaBridge 172:65be27845400 8922 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8923 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
AnnaBridge 172:65be27845400 8924
AnnaBridge 172:65be27845400 8925 #define FMC_SDRTR_COUNT_Pos (1U)
AnnaBridge 172:65be27845400 8926 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
AnnaBridge 172:65be27845400 8927 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
AnnaBridge 172:65be27845400 8928
AnnaBridge 172:65be27845400 8929 #define FMC_SDRTR_REIE_Pos (14U)
AnnaBridge 172:65be27845400 8930 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8931 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
AnnaBridge 172:65be27845400 8932
AnnaBridge 172:65be27845400 8933 /****************** Bit definition for FMC_SDSR register ******************/
AnnaBridge 172:65be27845400 8934 #define FMC_SDSR_RE_Pos (0U)
AnnaBridge 172:65be27845400 8935 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8936 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
AnnaBridge 172:65be27845400 8937
AnnaBridge 172:65be27845400 8938 #define FMC_SDSR_MODES1_Pos (1U)
AnnaBridge 172:65be27845400 8939 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 8940 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
AnnaBridge 172:65be27845400 8941 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8942 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8943
AnnaBridge 172:65be27845400 8944 #define FMC_SDSR_MODES2_Pos (3U)
AnnaBridge 172:65be27845400 8945 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 8946 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
AnnaBridge 172:65be27845400 8947 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8948 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8949 #define FMC_SDSR_BUSY_Pos (5U)
AnnaBridge 172:65be27845400 8950 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8951 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
AnnaBridge 172:65be27845400 8952
AnnaBridge 172:65be27845400 8953 /******************************************************************************/
AnnaBridge 172:65be27845400 8954 /* */
AnnaBridge 172:65be27845400 8955 /* General Purpose I/O */
AnnaBridge 172:65be27845400 8956 /* */
AnnaBridge 172:65be27845400 8957 /******************************************************************************/
AnnaBridge 172:65be27845400 8958 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 172:65be27845400 8959 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 172:65be27845400 8960 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 8961 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 172:65be27845400 8962 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8963 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8964 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 172:65be27845400 8965 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 8966 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 172:65be27845400 8967 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8968 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8969 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 172:65be27845400 8970 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8971 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 172:65be27845400 8972 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8973 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8974 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 172:65be27845400 8975 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 8976 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 172:65be27845400 8977 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8978 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8979 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 172:65be27845400 8980 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 8981 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 172:65be27845400 8982 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8983 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8984 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 172:65be27845400 8985 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 8986 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 172:65be27845400 8987 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8988 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8989 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 172:65be27845400 8990 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 8991 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 172:65be27845400 8992 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8993 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8994 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 172:65be27845400 8995 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 8996 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 172:65be27845400 8997 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8998 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8999 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 172:65be27845400 9000 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9001 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 172:65be27845400 9002 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9003 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9004 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 172:65be27845400 9005 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9006 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 172:65be27845400 9007 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9008 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9009 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 172:65be27845400 9010 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 9011 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 172:65be27845400 9012 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9013 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9014 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 172:65be27845400 9015 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 9016 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 172:65be27845400 9017 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9018 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9019 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 172:65be27845400 9020 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 9021 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 172:65be27845400 9022 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9023 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9024 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 172:65be27845400 9025 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 9026 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 172:65be27845400 9027 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9028 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9029 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 172:65be27845400 9030 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 9031 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 172:65be27845400 9032 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9033 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9034 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 172:65be27845400 9035 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 9036 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 172:65be27845400 9037 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9038 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9039
AnnaBridge 172:65be27845400 9040 /* Legacy defines */
AnnaBridge 172:65be27845400 9041 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 172:65be27845400 9042 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 9043 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 172:65be27845400 9044 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9045 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9046 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 172:65be27845400 9047 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 9048 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 172:65be27845400 9049 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9050 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9051 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 172:65be27845400 9052 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 9053 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 172:65be27845400 9054 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9055 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9056 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 172:65be27845400 9057 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9058 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 172:65be27845400 9059 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9060 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9061 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 172:65be27845400 9062 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 9063 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 172:65be27845400 9064 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9065 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9066 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 172:65be27845400 9067 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 9068 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 172:65be27845400 9069 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9070 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9071 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 172:65be27845400 9072 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 9073 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 172:65be27845400 9074 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9075 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9076 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 172:65be27845400 9077 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 9078 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 172:65be27845400 9079 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9080 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9081 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 172:65be27845400 9082 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9083 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 172:65be27845400 9084 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9085 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9086 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 172:65be27845400 9087 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9088 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 172:65be27845400 9089 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9090 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9091 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 172:65be27845400 9092 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 9093 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 172:65be27845400 9094 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9095 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9096 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 172:65be27845400 9097 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 9098 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 172:65be27845400 9099 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9100 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9101 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 172:65be27845400 9102 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 9103 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 172:65be27845400 9104 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9105 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9106 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 172:65be27845400 9107 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 9108 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 172:65be27845400 9109 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9110 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9111 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 172:65be27845400 9112 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 9113 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 172:65be27845400 9114 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9115 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9116 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 172:65be27845400 9117 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 9118 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 172:65be27845400 9119 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9120 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9121
AnnaBridge 172:65be27845400 9122 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 172:65be27845400 9123 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 172:65be27845400 9124 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9125 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 172:65be27845400 9126 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 172:65be27845400 9127 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9128 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 172:65be27845400 9129 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 172:65be27845400 9130 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9131 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 172:65be27845400 9132 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 172:65be27845400 9133 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9134 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 172:65be27845400 9135 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 172:65be27845400 9136 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9137 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 172:65be27845400 9138 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 172:65be27845400 9139 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9140 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 172:65be27845400 9141 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 172:65be27845400 9142 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9143 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 172:65be27845400 9144 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 172:65be27845400 9145 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9146 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 172:65be27845400 9147 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 172:65be27845400 9148 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9149 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 172:65be27845400 9150 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 172:65be27845400 9151 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9152 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 172:65be27845400 9153 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 172:65be27845400 9154 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9155 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 172:65be27845400 9156 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 172:65be27845400 9157 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9158 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 172:65be27845400 9159 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 172:65be27845400 9160 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9161 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 172:65be27845400 9162 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 172:65be27845400 9163 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9164 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 172:65be27845400 9165 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 172:65be27845400 9166 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9167 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 172:65be27845400 9168 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 172:65be27845400 9169 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9170 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 172:65be27845400 9171
AnnaBridge 172:65be27845400 9172 /* Legacy defines */
AnnaBridge 172:65be27845400 9173 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
AnnaBridge 172:65be27845400 9174 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
AnnaBridge 172:65be27845400 9175 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
AnnaBridge 172:65be27845400 9176 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
AnnaBridge 172:65be27845400 9177 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
AnnaBridge 172:65be27845400 9178 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
AnnaBridge 172:65be27845400 9179 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
AnnaBridge 172:65be27845400 9180 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
AnnaBridge 172:65be27845400 9181 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
AnnaBridge 172:65be27845400 9182 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
AnnaBridge 172:65be27845400 9183 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
AnnaBridge 172:65be27845400 9184 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
AnnaBridge 172:65be27845400 9185 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
AnnaBridge 172:65be27845400 9186 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
AnnaBridge 172:65be27845400 9187 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
AnnaBridge 172:65be27845400 9188 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
AnnaBridge 172:65be27845400 9189
AnnaBridge 172:65be27845400 9190 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 172:65be27845400 9191 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 172:65be27845400 9192 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 9193 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 172:65be27845400 9194 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9195 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9196 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 172:65be27845400 9197 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 9198 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 172:65be27845400 9199 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9200 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9201 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 172:65be27845400 9202 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 9203 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 172:65be27845400 9204 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9205 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9206 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 172:65be27845400 9207 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9208 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 172:65be27845400 9209 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9210 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9211 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 172:65be27845400 9212 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 9213 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 172:65be27845400 9214 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9215 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9216 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 172:65be27845400 9217 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 9218 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 172:65be27845400 9219 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9220 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9221 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 172:65be27845400 9222 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 9223 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 172:65be27845400 9224 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9225 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9226 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 172:65be27845400 9227 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 9228 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 172:65be27845400 9229 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9230 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9231 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 172:65be27845400 9232 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9233 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 172:65be27845400 9234 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9235 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9236 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 172:65be27845400 9237 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9238 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 172:65be27845400 9239 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9240 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9241 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 172:65be27845400 9242 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 9243 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 172:65be27845400 9244 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9245 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9246 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 172:65be27845400 9247 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 9248 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 172:65be27845400 9249 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9250 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9251 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 172:65be27845400 9252 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 9253 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 172:65be27845400 9254 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9255 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9256 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 172:65be27845400 9257 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 9258 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 172:65be27845400 9259 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9260 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9261 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 172:65be27845400 9262 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 9263 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 172:65be27845400 9264 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9265 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9266 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 172:65be27845400 9267 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 9268 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 172:65be27845400 9269 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9270 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9271
AnnaBridge 172:65be27845400 9272 /* Legacy defines */
AnnaBridge 172:65be27845400 9273 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
AnnaBridge 172:65be27845400 9274 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
AnnaBridge 172:65be27845400 9275 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
AnnaBridge 172:65be27845400 9276 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
AnnaBridge 172:65be27845400 9277 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
AnnaBridge 172:65be27845400 9278 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
AnnaBridge 172:65be27845400 9279 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
AnnaBridge 172:65be27845400 9280 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
AnnaBridge 172:65be27845400 9281 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
AnnaBridge 172:65be27845400 9282 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
AnnaBridge 172:65be27845400 9283 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
AnnaBridge 172:65be27845400 9284 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
AnnaBridge 172:65be27845400 9285 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
AnnaBridge 172:65be27845400 9286 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
AnnaBridge 172:65be27845400 9287 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
AnnaBridge 172:65be27845400 9288 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
AnnaBridge 172:65be27845400 9289 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
AnnaBridge 172:65be27845400 9290 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
AnnaBridge 172:65be27845400 9291 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
AnnaBridge 172:65be27845400 9292 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
AnnaBridge 172:65be27845400 9293 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
AnnaBridge 172:65be27845400 9294 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
AnnaBridge 172:65be27845400 9295 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
AnnaBridge 172:65be27845400 9296 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
AnnaBridge 172:65be27845400 9297 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
AnnaBridge 172:65be27845400 9298 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
AnnaBridge 172:65be27845400 9299 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
AnnaBridge 172:65be27845400 9300 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
AnnaBridge 172:65be27845400 9301 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
AnnaBridge 172:65be27845400 9302 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
AnnaBridge 172:65be27845400 9303 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
AnnaBridge 172:65be27845400 9304 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
AnnaBridge 172:65be27845400 9305 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
AnnaBridge 172:65be27845400 9306 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
AnnaBridge 172:65be27845400 9307 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
AnnaBridge 172:65be27845400 9308 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
AnnaBridge 172:65be27845400 9309 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
AnnaBridge 172:65be27845400 9310 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
AnnaBridge 172:65be27845400 9311 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
AnnaBridge 172:65be27845400 9312 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
AnnaBridge 172:65be27845400 9313 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
AnnaBridge 172:65be27845400 9314 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
AnnaBridge 172:65be27845400 9315 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
AnnaBridge 172:65be27845400 9316 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
AnnaBridge 172:65be27845400 9317 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
AnnaBridge 172:65be27845400 9318 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
AnnaBridge 172:65be27845400 9319 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
AnnaBridge 172:65be27845400 9320 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
AnnaBridge 172:65be27845400 9321
AnnaBridge 172:65be27845400 9322 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 172:65be27845400 9323 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 172:65be27845400 9324 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 9325 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 172:65be27845400 9326 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9327 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9328 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 172:65be27845400 9329 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 9330 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 172:65be27845400 9331 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9332 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9333 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 172:65be27845400 9334 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 9335 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 172:65be27845400 9336 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9337 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9338 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 172:65be27845400 9339 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9340 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 172:65be27845400 9341 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9342 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9343 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 172:65be27845400 9344 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 9345 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 172:65be27845400 9346 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9347 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9348 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 172:65be27845400 9349 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 9350 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 172:65be27845400 9351 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9352 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9353 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 172:65be27845400 9354 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 9355 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 172:65be27845400 9356 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9357 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9358 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 172:65be27845400 9359 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 9360 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 172:65be27845400 9361 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9362 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9363 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 172:65be27845400 9364 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9365 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 172:65be27845400 9366 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9367 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9368 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 172:65be27845400 9369 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9370 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 172:65be27845400 9371 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9372 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9373 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 172:65be27845400 9374 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 9375 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 172:65be27845400 9376 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9377 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9378 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 172:65be27845400 9379 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 9380 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 172:65be27845400 9381 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9382 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9383 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 172:65be27845400 9384 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 9385 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 172:65be27845400 9386 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9387 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9388 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 172:65be27845400 9389 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 9390 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 172:65be27845400 9391 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9392 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9393 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 172:65be27845400 9394 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 9395 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 172:65be27845400 9396 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9397 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9398 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 172:65be27845400 9399 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 9400 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 172:65be27845400 9401 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9402 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9403
AnnaBridge 172:65be27845400 9404 /* Legacy defines */
AnnaBridge 172:65be27845400 9405 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
AnnaBridge 172:65be27845400 9406 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
AnnaBridge 172:65be27845400 9407 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
AnnaBridge 172:65be27845400 9408 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
AnnaBridge 172:65be27845400 9409 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
AnnaBridge 172:65be27845400 9410 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
AnnaBridge 172:65be27845400 9411 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
AnnaBridge 172:65be27845400 9412 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
AnnaBridge 172:65be27845400 9413 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
AnnaBridge 172:65be27845400 9414 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
AnnaBridge 172:65be27845400 9415 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
AnnaBridge 172:65be27845400 9416 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
AnnaBridge 172:65be27845400 9417 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
AnnaBridge 172:65be27845400 9418 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
AnnaBridge 172:65be27845400 9419 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
AnnaBridge 172:65be27845400 9420 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
AnnaBridge 172:65be27845400 9421 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
AnnaBridge 172:65be27845400 9422 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
AnnaBridge 172:65be27845400 9423 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
AnnaBridge 172:65be27845400 9424 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
AnnaBridge 172:65be27845400 9425 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
AnnaBridge 172:65be27845400 9426 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
AnnaBridge 172:65be27845400 9427 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
AnnaBridge 172:65be27845400 9428 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
AnnaBridge 172:65be27845400 9429 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
AnnaBridge 172:65be27845400 9430 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
AnnaBridge 172:65be27845400 9431 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
AnnaBridge 172:65be27845400 9432 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
AnnaBridge 172:65be27845400 9433 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
AnnaBridge 172:65be27845400 9434 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
AnnaBridge 172:65be27845400 9435 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
AnnaBridge 172:65be27845400 9436 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
AnnaBridge 172:65be27845400 9437 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
AnnaBridge 172:65be27845400 9438 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
AnnaBridge 172:65be27845400 9439 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
AnnaBridge 172:65be27845400 9440 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
AnnaBridge 172:65be27845400 9441 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
AnnaBridge 172:65be27845400 9442 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
AnnaBridge 172:65be27845400 9443 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
AnnaBridge 172:65be27845400 9444 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
AnnaBridge 172:65be27845400 9445 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
AnnaBridge 172:65be27845400 9446 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
AnnaBridge 172:65be27845400 9447 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
AnnaBridge 172:65be27845400 9448 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
AnnaBridge 172:65be27845400 9449 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
AnnaBridge 172:65be27845400 9450 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
AnnaBridge 172:65be27845400 9451 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
AnnaBridge 172:65be27845400 9452 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
AnnaBridge 172:65be27845400 9453
AnnaBridge 172:65be27845400 9454 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 172:65be27845400 9455 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 172:65be27845400 9456 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9457 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 172:65be27845400 9458 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 172:65be27845400 9459 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9460 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 172:65be27845400 9461 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 172:65be27845400 9462 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9463 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 172:65be27845400 9464 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 172:65be27845400 9465 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9466 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 172:65be27845400 9467 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 172:65be27845400 9468 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9469 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 172:65be27845400 9470 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 172:65be27845400 9471 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9472 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 172:65be27845400 9473 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 172:65be27845400 9474 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9475 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 172:65be27845400 9476 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 172:65be27845400 9477 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9478 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 172:65be27845400 9479 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 172:65be27845400 9480 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9481 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 172:65be27845400 9482 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 172:65be27845400 9483 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9484 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 172:65be27845400 9485 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 172:65be27845400 9486 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9487 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 172:65be27845400 9488 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 172:65be27845400 9489 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9490 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 172:65be27845400 9491 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 172:65be27845400 9492 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9493 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 172:65be27845400 9494 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 172:65be27845400 9495 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9496 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 172:65be27845400 9497 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 172:65be27845400 9498 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9499 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 172:65be27845400 9500 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 172:65be27845400 9501 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9502 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 172:65be27845400 9503
AnnaBridge 172:65be27845400 9504 /* Legacy defines */
AnnaBridge 172:65be27845400 9505 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
AnnaBridge 172:65be27845400 9506 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
AnnaBridge 172:65be27845400 9507 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
AnnaBridge 172:65be27845400 9508 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
AnnaBridge 172:65be27845400 9509 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
AnnaBridge 172:65be27845400 9510 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
AnnaBridge 172:65be27845400 9511 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
AnnaBridge 172:65be27845400 9512 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
AnnaBridge 172:65be27845400 9513 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
AnnaBridge 172:65be27845400 9514 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
AnnaBridge 172:65be27845400 9515 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
AnnaBridge 172:65be27845400 9516 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
AnnaBridge 172:65be27845400 9517 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
AnnaBridge 172:65be27845400 9518 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
AnnaBridge 172:65be27845400 9519 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
AnnaBridge 172:65be27845400 9520 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
AnnaBridge 172:65be27845400 9521
AnnaBridge 172:65be27845400 9522 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 172:65be27845400 9523 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 172:65be27845400 9524 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9525 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 172:65be27845400 9526 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 172:65be27845400 9527 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9528 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 172:65be27845400 9529 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 172:65be27845400 9530 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9531 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 172:65be27845400 9532 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 172:65be27845400 9533 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9534 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 172:65be27845400 9535 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 172:65be27845400 9536 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9537 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 172:65be27845400 9538 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 172:65be27845400 9539 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9540 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 172:65be27845400 9541 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 172:65be27845400 9542 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9543 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 172:65be27845400 9544 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 172:65be27845400 9545 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9546 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 172:65be27845400 9547 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 172:65be27845400 9548 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9549 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 172:65be27845400 9550 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 172:65be27845400 9551 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9552 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 172:65be27845400 9553 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 172:65be27845400 9554 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9555 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 172:65be27845400 9556 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 172:65be27845400 9557 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9558 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 172:65be27845400 9559 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 172:65be27845400 9560 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9561 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 172:65be27845400 9562 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 172:65be27845400 9563 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9564 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 172:65be27845400 9565 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 172:65be27845400 9566 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9567 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 172:65be27845400 9568 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 172:65be27845400 9569 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9570 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 172:65be27845400 9571 /* Legacy defines */
AnnaBridge 172:65be27845400 9572 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
AnnaBridge 172:65be27845400 9573 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
AnnaBridge 172:65be27845400 9574 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
AnnaBridge 172:65be27845400 9575 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
AnnaBridge 172:65be27845400 9576 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
AnnaBridge 172:65be27845400 9577 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
AnnaBridge 172:65be27845400 9578 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
AnnaBridge 172:65be27845400 9579 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
AnnaBridge 172:65be27845400 9580 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
AnnaBridge 172:65be27845400 9581 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
AnnaBridge 172:65be27845400 9582 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
AnnaBridge 172:65be27845400 9583 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
AnnaBridge 172:65be27845400 9584 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
AnnaBridge 172:65be27845400 9585 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
AnnaBridge 172:65be27845400 9586 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
AnnaBridge 172:65be27845400 9587 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
AnnaBridge 172:65be27845400 9588
AnnaBridge 172:65be27845400 9589 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 172:65be27845400 9590 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 172:65be27845400 9591 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9592 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 172:65be27845400 9593 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 172:65be27845400 9594 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9595 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 172:65be27845400 9596 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 172:65be27845400 9597 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9598 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 172:65be27845400 9599 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 172:65be27845400 9600 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9601 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 172:65be27845400 9602 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 172:65be27845400 9603 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9604 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 172:65be27845400 9605 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 172:65be27845400 9606 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9607 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 172:65be27845400 9608 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 172:65be27845400 9609 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9610 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 172:65be27845400 9611 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 172:65be27845400 9612 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9613 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 172:65be27845400 9614 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 172:65be27845400 9615 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9616 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 172:65be27845400 9617 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 172:65be27845400 9618 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9619 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 172:65be27845400 9620 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 172:65be27845400 9621 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9622 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 172:65be27845400 9623 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 172:65be27845400 9624 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9625 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 172:65be27845400 9626 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 172:65be27845400 9627 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9628 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 172:65be27845400 9629 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 172:65be27845400 9630 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9631 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 172:65be27845400 9632 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 172:65be27845400 9633 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9634 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 172:65be27845400 9635 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 172:65be27845400 9636 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9637 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 172:65be27845400 9638 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 172:65be27845400 9639 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9640 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 172:65be27845400 9641 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 172:65be27845400 9642 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9643 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 172:65be27845400 9644 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 172:65be27845400 9645 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9646 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 172:65be27845400 9647 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 172:65be27845400 9648 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9649 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 172:65be27845400 9650 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 172:65be27845400 9651 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9652 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 172:65be27845400 9653 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 172:65be27845400 9654 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9655 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 172:65be27845400 9656 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 172:65be27845400 9657 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9658 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 172:65be27845400 9659 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 172:65be27845400 9660 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9661 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 172:65be27845400 9662 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 172:65be27845400 9663 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9664 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 172:65be27845400 9665 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 172:65be27845400 9666 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9667 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 172:65be27845400 9668 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 172:65be27845400 9669 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9670 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 172:65be27845400 9671 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 172:65be27845400 9672 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9673 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 172:65be27845400 9674 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 172:65be27845400 9675 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9676 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 172:65be27845400 9677 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 172:65be27845400 9678 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9679 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 172:65be27845400 9680 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 172:65be27845400 9681 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9682 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 172:65be27845400 9683 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 172:65be27845400 9684 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9685 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 172:65be27845400 9686
AnnaBridge 172:65be27845400 9687 /* Legacy defines */
AnnaBridge 172:65be27845400 9688 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
AnnaBridge 172:65be27845400 9689 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
AnnaBridge 172:65be27845400 9690 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
AnnaBridge 172:65be27845400 9691 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
AnnaBridge 172:65be27845400 9692 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
AnnaBridge 172:65be27845400 9693 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
AnnaBridge 172:65be27845400 9694 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
AnnaBridge 172:65be27845400 9695 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
AnnaBridge 172:65be27845400 9696 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
AnnaBridge 172:65be27845400 9697 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
AnnaBridge 172:65be27845400 9698 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
AnnaBridge 172:65be27845400 9699 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
AnnaBridge 172:65be27845400 9700 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
AnnaBridge 172:65be27845400 9701 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
AnnaBridge 172:65be27845400 9702 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
AnnaBridge 172:65be27845400 9703 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
AnnaBridge 172:65be27845400 9704 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
AnnaBridge 172:65be27845400 9705 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
AnnaBridge 172:65be27845400 9706 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
AnnaBridge 172:65be27845400 9707 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
AnnaBridge 172:65be27845400 9708 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
AnnaBridge 172:65be27845400 9709 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
AnnaBridge 172:65be27845400 9710 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
AnnaBridge 172:65be27845400 9711 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
AnnaBridge 172:65be27845400 9712 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
AnnaBridge 172:65be27845400 9713 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
AnnaBridge 172:65be27845400 9714 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
AnnaBridge 172:65be27845400 9715 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
AnnaBridge 172:65be27845400 9716 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
AnnaBridge 172:65be27845400 9717 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
AnnaBridge 172:65be27845400 9718 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
AnnaBridge 172:65be27845400 9719 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
AnnaBridge 172:65be27845400 9720 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 172:65be27845400 9721 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 172:65be27845400 9722 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9723 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 172:65be27845400 9724 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 172:65be27845400 9725 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9726 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 172:65be27845400 9727 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 172:65be27845400 9728 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9729 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 172:65be27845400 9730 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 172:65be27845400 9731 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9732 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 172:65be27845400 9733 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 172:65be27845400 9734 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9735 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 172:65be27845400 9736 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 172:65be27845400 9737 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9738 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 172:65be27845400 9739 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 172:65be27845400 9740 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9741 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 172:65be27845400 9742 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 172:65be27845400 9743 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9744 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 172:65be27845400 9745 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 172:65be27845400 9746 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9747 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 172:65be27845400 9748 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 172:65be27845400 9749 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9750 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 172:65be27845400 9751 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 172:65be27845400 9752 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9753 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 172:65be27845400 9754 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 172:65be27845400 9755 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9756 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 172:65be27845400 9757 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 172:65be27845400 9758 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9759 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 172:65be27845400 9760 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 172:65be27845400 9761 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9762 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 172:65be27845400 9763 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 172:65be27845400 9764 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9765 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 172:65be27845400 9766 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 172:65be27845400 9767 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9768 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 172:65be27845400 9769 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 172:65be27845400 9770 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9771 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 172:65be27845400 9772 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 172:65be27845400 9773 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 172:65be27845400 9774 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 9775 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 172:65be27845400 9776 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9777 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9778 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9779 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9780 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 172:65be27845400 9781 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 9782 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 172:65be27845400 9783 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9784 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9785 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9786 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9787 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 172:65be27845400 9788 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 9789 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 172:65be27845400 9790 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9791 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9792 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9793 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9794 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 172:65be27845400 9795 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 9796 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 172:65be27845400 9797 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9798 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9799 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9800 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9801 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 172:65be27845400 9802 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 9803 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 172:65be27845400 9804 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9805 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9806 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9807 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9808 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 172:65be27845400 9809 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 9810 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 172:65be27845400 9811 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9812 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9813 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9814 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9815 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 172:65be27845400 9816 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 9817 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 172:65be27845400 9818 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9819 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9820 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9821 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9822 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 172:65be27845400 9823 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 9824 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 172:65be27845400 9825 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9826 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9827 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9828 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9829
AnnaBridge 172:65be27845400 9830 /* Legacy defines */
AnnaBridge 172:65be27845400 9831 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 172:65be27845400 9832 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
AnnaBridge 172:65be27845400 9833 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
AnnaBridge 172:65be27845400 9834 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
AnnaBridge 172:65be27845400 9835 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
AnnaBridge 172:65be27845400 9836 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 172:65be27845400 9837 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
AnnaBridge 172:65be27845400 9838 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
AnnaBridge 172:65be27845400 9839 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
AnnaBridge 172:65be27845400 9840 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
AnnaBridge 172:65be27845400 9841 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 172:65be27845400 9842 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
AnnaBridge 172:65be27845400 9843 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
AnnaBridge 172:65be27845400 9844 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
AnnaBridge 172:65be27845400 9845 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
AnnaBridge 172:65be27845400 9846 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 172:65be27845400 9847 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
AnnaBridge 172:65be27845400 9848 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
AnnaBridge 172:65be27845400 9849 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
AnnaBridge 172:65be27845400 9850 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
AnnaBridge 172:65be27845400 9851 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 172:65be27845400 9852 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
AnnaBridge 172:65be27845400 9853 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
AnnaBridge 172:65be27845400 9854 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
AnnaBridge 172:65be27845400 9855 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
AnnaBridge 172:65be27845400 9856 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 172:65be27845400 9857 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
AnnaBridge 172:65be27845400 9858 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
AnnaBridge 172:65be27845400 9859 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
AnnaBridge 172:65be27845400 9860 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
AnnaBridge 172:65be27845400 9861 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 172:65be27845400 9862 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
AnnaBridge 172:65be27845400 9863 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
AnnaBridge 172:65be27845400 9864 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
AnnaBridge 172:65be27845400 9865 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
AnnaBridge 172:65be27845400 9866 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 172:65be27845400 9867 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
AnnaBridge 172:65be27845400 9868 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
AnnaBridge 172:65be27845400 9869 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
AnnaBridge 172:65be27845400 9870 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
AnnaBridge 172:65be27845400 9871
AnnaBridge 172:65be27845400 9872 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 172:65be27845400 9873 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 172:65be27845400 9874 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 9875 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 172:65be27845400 9876 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9877 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9878 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9879 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9880 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 172:65be27845400 9881 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 9882 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 172:65be27845400 9883 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9884 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9885 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9886 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9887 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 172:65be27845400 9888 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 9889 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 172:65be27845400 9890 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9891 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9892 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9893 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9894 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 172:65be27845400 9895 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 9896 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 172:65be27845400 9897 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9898 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9899 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9900 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9901 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 172:65be27845400 9902 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 9903 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 172:65be27845400 9904 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9905 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9906 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9907 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9908 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 172:65be27845400 9909 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 9910 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 172:65be27845400 9911 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9912 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9913 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9914 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9915 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 172:65be27845400 9916 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 9917 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 172:65be27845400 9918 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9919 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9920 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9921 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9922 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 172:65be27845400 9923 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 9924 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 172:65be27845400 9925 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9926 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9927 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9928 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9929
AnnaBridge 172:65be27845400 9930 /* Legacy defines */
AnnaBridge 172:65be27845400 9931 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 172:65be27845400 9932 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
AnnaBridge 172:65be27845400 9933 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
AnnaBridge 172:65be27845400 9934 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
AnnaBridge 172:65be27845400 9935 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
AnnaBridge 172:65be27845400 9936 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 172:65be27845400 9937 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
AnnaBridge 172:65be27845400 9938 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
AnnaBridge 172:65be27845400 9939 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
AnnaBridge 172:65be27845400 9940 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
AnnaBridge 172:65be27845400 9941 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 172:65be27845400 9942 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
AnnaBridge 172:65be27845400 9943 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
AnnaBridge 172:65be27845400 9944 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
AnnaBridge 172:65be27845400 9945 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
AnnaBridge 172:65be27845400 9946 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 172:65be27845400 9947 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
AnnaBridge 172:65be27845400 9948 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
AnnaBridge 172:65be27845400 9949 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
AnnaBridge 172:65be27845400 9950 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
AnnaBridge 172:65be27845400 9951 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 172:65be27845400 9952 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
AnnaBridge 172:65be27845400 9953 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
AnnaBridge 172:65be27845400 9954 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
AnnaBridge 172:65be27845400 9955 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
AnnaBridge 172:65be27845400 9956 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 172:65be27845400 9957 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
AnnaBridge 172:65be27845400 9958 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
AnnaBridge 172:65be27845400 9959 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
AnnaBridge 172:65be27845400 9960 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
AnnaBridge 172:65be27845400 9961 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 172:65be27845400 9962 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
AnnaBridge 172:65be27845400 9963 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
AnnaBridge 172:65be27845400 9964 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
AnnaBridge 172:65be27845400 9965 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
AnnaBridge 172:65be27845400 9966 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 172:65be27845400 9967 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
AnnaBridge 172:65be27845400 9968 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
AnnaBridge 172:65be27845400 9969 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
AnnaBridge 172:65be27845400 9970 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
AnnaBridge 172:65be27845400 9971
AnnaBridge 172:65be27845400 9972 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 172:65be27845400 9973 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 172:65be27845400 9974 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9975 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 172:65be27845400 9976 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 172:65be27845400 9977 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9978 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 172:65be27845400 9979 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 172:65be27845400 9980 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9981 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 172:65be27845400 9982 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 172:65be27845400 9983 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9984 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 172:65be27845400 9985 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 172:65be27845400 9986 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9987 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 172:65be27845400 9988 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 172:65be27845400 9989 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9990 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 172:65be27845400 9991 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 172:65be27845400 9992 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9993 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 172:65be27845400 9994 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 172:65be27845400 9995 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9996 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 172:65be27845400 9997 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 172:65be27845400 9998 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9999 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 172:65be27845400 10000 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 172:65be27845400 10001 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10002 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 172:65be27845400 10003 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 172:65be27845400 10004 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10005 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 172:65be27845400 10006 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 172:65be27845400 10007 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10008 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 172:65be27845400 10009 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 172:65be27845400 10010 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10011 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 172:65be27845400 10012 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 172:65be27845400 10013 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10014 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 172:65be27845400 10015 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 172:65be27845400 10016 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10017 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 172:65be27845400 10018 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 172:65be27845400 10019 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10020 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 172:65be27845400 10021
AnnaBridge 172:65be27845400 10022
AnnaBridge 172:65be27845400 10023 /******************************************************************************/
AnnaBridge 172:65be27845400 10024 /* */
AnnaBridge 172:65be27845400 10025 /* HASH */
AnnaBridge 172:65be27845400 10026 /* */
AnnaBridge 172:65be27845400 10027 /******************************************************************************/
AnnaBridge 172:65be27845400 10028 /****************** Bits definition for HASH_CR register ********************/
AnnaBridge 172:65be27845400 10029 #define HASH_CR_INIT_Pos (2U)
AnnaBridge 172:65be27845400 10030 #define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10031 #define HASH_CR_INIT HASH_CR_INIT_Msk
AnnaBridge 172:65be27845400 10032 #define HASH_CR_DMAE_Pos (3U)
AnnaBridge 172:65be27845400 10033 #define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10034 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
AnnaBridge 172:65be27845400 10035 #define HASH_CR_DATATYPE_Pos (4U)
AnnaBridge 172:65be27845400 10036 #define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 10037 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
AnnaBridge 172:65be27845400 10038 #define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10039 #define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10040 #define HASH_CR_MODE_Pos (6U)
AnnaBridge 172:65be27845400 10041 #define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10042 #define HASH_CR_MODE HASH_CR_MODE_Msk
AnnaBridge 172:65be27845400 10043 #define HASH_CR_ALGO_Pos (7U)
AnnaBridge 172:65be27845400 10044 #define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
AnnaBridge 172:65be27845400 10045 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
AnnaBridge 172:65be27845400 10046 #define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10047 #define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10048 #define HASH_CR_NBW_Pos (8U)
AnnaBridge 172:65be27845400 10049 #define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 10050 #define HASH_CR_NBW HASH_CR_NBW_Msk
AnnaBridge 172:65be27845400 10051 #define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10052 #define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10053 #define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10054 #define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10055 #define HASH_CR_DINNE_Pos (12U)
AnnaBridge 172:65be27845400 10056 #define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10057 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
AnnaBridge 172:65be27845400 10058 #define HASH_CR_MDMAT_Pos (13U)
AnnaBridge 172:65be27845400 10059 #define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10060 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
AnnaBridge 172:65be27845400 10061 #define HASH_CR_LKEY_Pos (16U)
AnnaBridge 172:65be27845400 10062 #define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10063 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
AnnaBridge 172:65be27845400 10064
AnnaBridge 172:65be27845400 10065 /****************** Bits definition for HASH_STR register *******************/
AnnaBridge 172:65be27845400 10066 #define HASH_STR_NBLW_Pos (0U)
AnnaBridge 172:65be27845400 10067 #define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 10068 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
AnnaBridge 172:65be27845400 10069 #define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10070 #define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10071 #define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10072 #define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10073 #define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10074 #define HASH_STR_DCAL_Pos (8U)
AnnaBridge 172:65be27845400 10075 #define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10076 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
AnnaBridge 172:65be27845400 10077 /* Aliases for HASH_STR register */
AnnaBridge 172:65be27845400 10078 #define HASH_STR_NBW HASH_STR_NBLW
AnnaBridge 172:65be27845400 10079 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
AnnaBridge 172:65be27845400 10080 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
AnnaBridge 172:65be27845400 10081 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
AnnaBridge 172:65be27845400 10082 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
AnnaBridge 172:65be27845400 10083 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
AnnaBridge 172:65be27845400 10084
AnnaBridge 172:65be27845400 10085 /****************** Bits definition for HASH_IMR register *******************/
AnnaBridge 172:65be27845400 10086 #define HASH_IMR_DINIE_Pos (0U)
AnnaBridge 172:65be27845400 10087 #define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10088 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
AnnaBridge 172:65be27845400 10089 #define HASH_IMR_DCIE_Pos (1U)
AnnaBridge 172:65be27845400 10090 #define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10091 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
AnnaBridge 172:65be27845400 10092 /* Aliases for HASH_IMR register */
AnnaBridge 172:65be27845400 10093 #define HASH_IMR_DINIM HASH_IMR_DINIE
AnnaBridge 172:65be27845400 10094 #define HASH_IMR_DCIM HASH_IMR_DCIE
AnnaBridge 172:65be27845400 10095
AnnaBridge 172:65be27845400 10096 /****************** Bits definition for HASH_SR register ********************/
AnnaBridge 172:65be27845400 10097 #define HASH_SR_DINIS_Pos (0U)
AnnaBridge 172:65be27845400 10098 #define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10099 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
AnnaBridge 172:65be27845400 10100 #define HASH_SR_DCIS_Pos (1U)
AnnaBridge 172:65be27845400 10101 #define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10102 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
AnnaBridge 172:65be27845400 10103 #define HASH_SR_DMAS_Pos (2U)
AnnaBridge 172:65be27845400 10104 #define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10105 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
AnnaBridge 172:65be27845400 10106 #define HASH_SR_BUSY_Pos (3U)
AnnaBridge 172:65be27845400 10107 #define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10108 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
AnnaBridge 172:65be27845400 10109
AnnaBridge 172:65be27845400 10110 /******************************************************************************/
AnnaBridge 172:65be27845400 10111 /* */
AnnaBridge 172:65be27845400 10112 /* Inter-integrated Circuit Interface */
AnnaBridge 172:65be27845400 10113 /* */
AnnaBridge 172:65be27845400 10114 /******************************************************************************/
AnnaBridge 172:65be27845400 10115 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 172:65be27845400 10116 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 172:65be27845400 10117 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10118 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
AnnaBridge 172:65be27845400 10119 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 172:65be27845400 10120 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10121 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
AnnaBridge 172:65be27845400 10122 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 172:65be27845400 10123 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10124 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
AnnaBridge 172:65be27845400 10125 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 172:65be27845400 10126 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10127 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
AnnaBridge 172:65be27845400 10128 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 172:65be27845400 10129 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10130 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
AnnaBridge 172:65be27845400 10131 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 172:65be27845400 10132 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10133 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
AnnaBridge 172:65be27845400 10134 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 172:65be27845400 10135 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10136 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
AnnaBridge 172:65be27845400 10137 #define I2C_CR1_START_Pos (8U)
AnnaBridge 172:65be27845400 10138 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10139 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
AnnaBridge 172:65be27845400 10140 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 172:65be27845400 10141 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10142 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
AnnaBridge 172:65be27845400 10143 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 172:65be27845400 10144 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10145 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
AnnaBridge 172:65be27845400 10146 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 172:65be27845400 10147 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10148 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
AnnaBridge 172:65be27845400 10149 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 172:65be27845400 10150 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10151 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
AnnaBridge 172:65be27845400 10152 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 172:65be27845400 10153 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10154 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
AnnaBridge 172:65be27845400 10155 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 172:65be27845400 10156 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10157 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
AnnaBridge 172:65be27845400 10158
AnnaBridge 172:65be27845400 10159 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 172:65be27845400 10160 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 172:65be27845400 10161 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 10162 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 172:65be27845400 10163 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10164 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10165 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10166 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10167 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10168 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10169
AnnaBridge 172:65be27845400 10170 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 172:65be27845400 10171 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10172 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
AnnaBridge 172:65be27845400 10173 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 172:65be27845400 10174 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10175 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
AnnaBridge 172:65be27845400 10176 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 172:65be27845400 10177 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10178 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
AnnaBridge 172:65be27845400 10179 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 172:65be27845400 10180 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10181 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
AnnaBridge 172:65be27845400 10182 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 172:65be27845400 10183 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10184 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
AnnaBridge 172:65be27845400 10185
AnnaBridge 172:65be27845400 10186 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 172:65be27845400 10187 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
AnnaBridge 172:65be27845400 10188 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
AnnaBridge 172:65be27845400 10189
AnnaBridge 172:65be27845400 10190 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 172:65be27845400 10191 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10192 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
AnnaBridge 172:65be27845400 10193 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 172:65be27845400 10194 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10195 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
AnnaBridge 172:65be27845400 10196 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 172:65be27845400 10197 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10198 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
AnnaBridge 172:65be27845400 10199 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 172:65be27845400 10200 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10201 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
AnnaBridge 172:65be27845400 10202 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 172:65be27845400 10203 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10204 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
AnnaBridge 172:65be27845400 10205 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 172:65be27845400 10206 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10207 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
AnnaBridge 172:65be27845400 10208 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 172:65be27845400 10209 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10210 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
AnnaBridge 172:65be27845400 10211 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 172:65be27845400 10212 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10213 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
AnnaBridge 172:65be27845400 10214 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 172:65be27845400 10215 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10216 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
AnnaBridge 172:65be27845400 10217 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 172:65be27845400 10218 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10219 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
AnnaBridge 172:65be27845400 10220
AnnaBridge 172:65be27845400 10221 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 172:65be27845400 10222 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10223 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
AnnaBridge 172:65be27845400 10224
AnnaBridge 172:65be27845400 10225 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 172:65be27845400 10226 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 172:65be27845400 10227 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10228 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
AnnaBridge 172:65be27845400 10229 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 172:65be27845400 10230 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 172:65be27845400 10231 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
AnnaBridge 172:65be27845400 10232
AnnaBridge 172:65be27845400 10233 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 172:65be27845400 10234 #define I2C_DR_DR_Pos (0U)
AnnaBridge 172:65be27845400 10235 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 10236 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
AnnaBridge 172:65be27845400 10237
AnnaBridge 172:65be27845400 10238 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 172:65be27845400 10239 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 172:65be27845400 10240 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10241 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
AnnaBridge 172:65be27845400 10242 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 172:65be27845400 10243 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10244 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
AnnaBridge 172:65be27845400 10245 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 172:65be27845400 10246 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10247 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
AnnaBridge 172:65be27845400 10248 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 172:65be27845400 10249 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10250 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
AnnaBridge 172:65be27845400 10251 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 172:65be27845400 10252 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10253 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
AnnaBridge 172:65be27845400 10254 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 172:65be27845400 10255 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10256 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
AnnaBridge 172:65be27845400 10257 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 172:65be27845400 10258 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10259 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
AnnaBridge 172:65be27845400 10260 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 172:65be27845400 10261 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10262 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
AnnaBridge 172:65be27845400 10263 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 172:65be27845400 10264 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10265 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
AnnaBridge 172:65be27845400 10266 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 172:65be27845400 10267 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10268 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
AnnaBridge 172:65be27845400 10269 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 172:65be27845400 10270 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10271 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
AnnaBridge 172:65be27845400 10272 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 172:65be27845400 10273 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10274 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
AnnaBridge 172:65be27845400 10275 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 172:65be27845400 10276 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10277 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
AnnaBridge 172:65be27845400 10278 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 172:65be27845400 10279 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10280 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
AnnaBridge 172:65be27845400 10281
AnnaBridge 172:65be27845400 10282 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 172:65be27845400 10283 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 172:65be27845400 10284 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10285 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
AnnaBridge 172:65be27845400 10286 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 172:65be27845400 10287 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10288 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
AnnaBridge 172:65be27845400 10289 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 172:65be27845400 10290 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10291 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
AnnaBridge 172:65be27845400 10292 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 172:65be27845400 10293 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10294 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
AnnaBridge 172:65be27845400 10295 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 172:65be27845400 10296 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10297 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
AnnaBridge 172:65be27845400 10298 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 172:65be27845400 10299 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10300 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
AnnaBridge 172:65be27845400 10301 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 172:65be27845400 10302 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10303 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
AnnaBridge 172:65be27845400 10304 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 172:65be27845400 10305 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10306 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
AnnaBridge 172:65be27845400 10307
AnnaBridge 172:65be27845400 10308 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 172:65be27845400 10309 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 172:65be27845400 10310 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 10311 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 172:65be27845400 10312 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 172:65be27845400 10313 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10314 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
AnnaBridge 172:65be27845400 10315 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 172:65be27845400 10316 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10317 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
AnnaBridge 172:65be27845400 10318
AnnaBridge 172:65be27845400 10319 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 172:65be27845400 10320 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 172:65be27845400 10321 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 10322 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
AnnaBridge 172:65be27845400 10323
AnnaBridge 172:65be27845400 10324 /****************** Bit definition for I2C_FLTR register *******************/
AnnaBridge 172:65be27845400 10325 #define I2C_FLTR_DNF_Pos (0U)
AnnaBridge 172:65be27845400 10326 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 10327 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
AnnaBridge 172:65be27845400 10328 #define I2C_FLTR_ANOFF_Pos (4U)
AnnaBridge 172:65be27845400 10329 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10330 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
AnnaBridge 172:65be27845400 10331
AnnaBridge 172:65be27845400 10332 /******************************************************************************/
AnnaBridge 172:65be27845400 10333 /* */
AnnaBridge 172:65be27845400 10334 /* Independent WATCHDOG */
AnnaBridge 172:65be27845400 10335 /* */
AnnaBridge 172:65be27845400 10336 /******************************************************************************/
AnnaBridge 172:65be27845400 10337 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 172:65be27845400 10338 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 172:65be27845400 10339 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 10340 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 172:65be27845400 10341
AnnaBridge 172:65be27845400 10342 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 172:65be27845400 10343 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 172:65be27845400 10344 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 10345 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 172:65be27845400 10346 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 172:65be27845400 10347 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 172:65be27845400 10348 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
AnnaBridge 172:65be27845400 10349
AnnaBridge 172:65be27845400 10350 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 172:65be27845400 10351 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 172:65be27845400 10352 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 10353 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 172:65be27845400 10354
AnnaBridge 172:65be27845400 10355 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 172:65be27845400 10356 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 172:65be27845400 10357 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10358 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
AnnaBridge 172:65be27845400 10359 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 172:65be27845400 10360 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10361 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
AnnaBridge 172:65be27845400 10362
AnnaBridge 172:65be27845400 10363
AnnaBridge 172:65be27845400 10364 /******************************************************************************/
AnnaBridge 172:65be27845400 10365 /* */
AnnaBridge 172:65be27845400 10366 /* LCD-TFT Display Controller (LTDC) */
AnnaBridge 172:65be27845400 10367 /* */
AnnaBridge 172:65be27845400 10368 /******************************************************************************/
AnnaBridge 172:65be27845400 10369
AnnaBridge 172:65be27845400 10370 /******************** Bit definition for LTDC_SSCR register *****************/
AnnaBridge 172:65be27845400 10371
AnnaBridge 172:65be27845400 10372 #define LTDC_SSCR_VSH_Pos (0U)
AnnaBridge 172:65be27845400 10373 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 10374 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
AnnaBridge 172:65be27845400 10375 #define LTDC_SSCR_HSW_Pos (16U)
AnnaBridge 172:65be27845400 10376 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 10377 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
AnnaBridge 172:65be27845400 10378
AnnaBridge 172:65be27845400 10379 /******************** Bit definition for LTDC_BPCR register *****************/
AnnaBridge 172:65be27845400 10380
AnnaBridge 172:65be27845400 10381 #define LTDC_BPCR_AVBP_Pos (0U)
AnnaBridge 172:65be27845400 10382 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 10383 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
AnnaBridge 172:65be27845400 10384 #define LTDC_BPCR_AHBP_Pos (16U)
AnnaBridge 172:65be27845400 10385 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 10386 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
AnnaBridge 172:65be27845400 10387
AnnaBridge 172:65be27845400 10388 /******************** Bit definition for LTDC_AWCR register *****************/
AnnaBridge 172:65be27845400 10389
AnnaBridge 172:65be27845400 10390 #define LTDC_AWCR_AAH_Pos (0U)
AnnaBridge 172:65be27845400 10391 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 10392 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
AnnaBridge 172:65be27845400 10393 #define LTDC_AWCR_AAW_Pos (16U)
AnnaBridge 172:65be27845400 10394 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 10395 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
AnnaBridge 172:65be27845400 10396
AnnaBridge 172:65be27845400 10397 /******************** Bit definition for LTDC_TWCR register *****************/
AnnaBridge 172:65be27845400 10398
AnnaBridge 172:65be27845400 10399 #define LTDC_TWCR_TOTALH_Pos (0U)
AnnaBridge 172:65be27845400 10400 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 10401 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
AnnaBridge 172:65be27845400 10402 #define LTDC_TWCR_TOTALW_Pos (16U)
AnnaBridge 172:65be27845400 10403 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 10404 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
AnnaBridge 172:65be27845400 10405
AnnaBridge 172:65be27845400 10406 /******************** Bit definition for LTDC_GCR register ******************/
AnnaBridge 172:65be27845400 10407
AnnaBridge 172:65be27845400 10408 #define LTDC_GCR_LTDCEN_Pos (0U)
AnnaBridge 172:65be27845400 10409 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10410 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
AnnaBridge 172:65be27845400 10411 #define LTDC_GCR_DBW_Pos (4U)
AnnaBridge 172:65be27845400 10412 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 10413 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
AnnaBridge 172:65be27845400 10414 #define LTDC_GCR_DGW_Pos (8U)
AnnaBridge 172:65be27845400 10415 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 10416 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
AnnaBridge 172:65be27845400 10417 #define LTDC_GCR_DRW_Pos (12U)
AnnaBridge 172:65be27845400 10418 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 10419 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
AnnaBridge 172:65be27845400 10420 #define LTDC_GCR_DEN_Pos (16U)
AnnaBridge 172:65be27845400 10421 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10422 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
AnnaBridge 172:65be27845400 10423 #define LTDC_GCR_PCPOL_Pos (28U)
AnnaBridge 172:65be27845400 10424 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10425 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
AnnaBridge 172:65be27845400 10426 #define LTDC_GCR_DEPOL_Pos (29U)
AnnaBridge 172:65be27845400 10427 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 10428 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
AnnaBridge 172:65be27845400 10429 #define LTDC_GCR_VSPOL_Pos (30U)
AnnaBridge 172:65be27845400 10430 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10431 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
AnnaBridge 172:65be27845400 10432 #define LTDC_GCR_HSPOL_Pos (31U)
AnnaBridge 172:65be27845400 10433 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10434 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
AnnaBridge 172:65be27845400 10435
AnnaBridge 172:65be27845400 10436 /* Legacy defines */
AnnaBridge 172:65be27845400 10437 #define LTDC_GCR_DTEN LTDC_GCR_DEN
AnnaBridge 172:65be27845400 10438
AnnaBridge 172:65be27845400 10439 /******************** Bit definition for LTDC_SRCR register *****************/
AnnaBridge 172:65be27845400 10440
AnnaBridge 172:65be27845400 10441 #define LTDC_SRCR_IMR_Pos (0U)
AnnaBridge 172:65be27845400 10442 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10443 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
AnnaBridge 172:65be27845400 10444 #define LTDC_SRCR_VBR_Pos (1U)
AnnaBridge 172:65be27845400 10445 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10446 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
AnnaBridge 172:65be27845400 10447
AnnaBridge 172:65be27845400 10448 /******************** Bit definition for LTDC_BCCR register *****************/
AnnaBridge 172:65be27845400 10449
AnnaBridge 172:65be27845400 10450 #define LTDC_BCCR_BCBLUE_Pos (0U)
AnnaBridge 172:65be27845400 10451 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 10452 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
AnnaBridge 172:65be27845400 10453 #define LTDC_BCCR_BCGREEN_Pos (8U)
AnnaBridge 172:65be27845400 10454 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10455 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
AnnaBridge 172:65be27845400 10456 #define LTDC_BCCR_BCRED_Pos (16U)
AnnaBridge 172:65be27845400 10457 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 10458 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
AnnaBridge 172:65be27845400 10459
AnnaBridge 172:65be27845400 10460 /******************** Bit definition for LTDC_IER register ******************/
AnnaBridge 172:65be27845400 10461
AnnaBridge 172:65be27845400 10462 #define LTDC_IER_LIE_Pos (0U)
AnnaBridge 172:65be27845400 10463 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10464 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
AnnaBridge 172:65be27845400 10465 #define LTDC_IER_FUIE_Pos (1U)
AnnaBridge 172:65be27845400 10466 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10467 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
AnnaBridge 172:65be27845400 10468 #define LTDC_IER_TERRIE_Pos (2U)
AnnaBridge 172:65be27845400 10469 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10470 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 172:65be27845400 10471 #define LTDC_IER_RRIE_Pos (3U)
AnnaBridge 172:65be27845400 10472 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10473 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
AnnaBridge 172:65be27845400 10474
AnnaBridge 172:65be27845400 10475 /******************** Bit definition for LTDC_ISR register ******************/
AnnaBridge 172:65be27845400 10476
AnnaBridge 172:65be27845400 10477 #define LTDC_ISR_LIF_Pos (0U)
AnnaBridge 172:65be27845400 10478 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10479 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
AnnaBridge 172:65be27845400 10480 #define LTDC_ISR_FUIF_Pos (1U)
AnnaBridge 172:65be27845400 10481 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10482 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
AnnaBridge 172:65be27845400 10483 #define LTDC_ISR_TERRIF_Pos (2U)
AnnaBridge 172:65be27845400 10484 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10485 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 10486 #define LTDC_ISR_RRIF_Pos (3U)
AnnaBridge 172:65be27845400 10487 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10488 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
AnnaBridge 172:65be27845400 10489
AnnaBridge 172:65be27845400 10490 /******************** Bit definition for LTDC_ICR register ******************/
AnnaBridge 172:65be27845400 10491
AnnaBridge 172:65be27845400 10492 #define LTDC_ICR_CLIF_Pos (0U)
AnnaBridge 172:65be27845400 10493 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10494 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
AnnaBridge 172:65be27845400 10495 #define LTDC_ICR_CFUIF_Pos (1U)
AnnaBridge 172:65be27845400 10496 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10497 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
AnnaBridge 172:65be27845400 10498 #define LTDC_ICR_CTERRIF_Pos (2U)
AnnaBridge 172:65be27845400 10499 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10500 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 10501 #define LTDC_ICR_CRRIF_Pos (3U)
AnnaBridge 172:65be27845400 10502 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10503 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
AnnaBridge 172:65be27845400 10504
AnnaBridge 172:65be27845400 10505 /******************** Bit definition for LTDC_LIPCR register ****************/
AnnaBridge 172:65be27845400 10506
AnnaBridge 172:65be27845400 10507 #define LTDC_LIPCR_LIPOS_Pos (0U)
AnnaBridge 172:65be27845400 10508 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 10509 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
AnnaBridge 172:65be27845400 10510
AnnaBridge 172:65be27845400 10511 /******************** Bit definition for LTDC_CPSR register *****************/
AnnaBridge 172:65be27845400 10512
AnnaBridge 172:65be27845400 10513 #define LTDC_CPSR_CYPOS_Pos (0U)
AnnaBridge 172:65be27845400 10514 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 10515 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
AnnaBridge 172:65be27845400 10516 #define LTDC_CPSR_CXPOS_Pos (16U)
AnnaBridge 172:65be27845400 10517 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 10518 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
AnnaBridge 172:65be27845400 10519
AnnaBridge 172:65be27845400 10520 /******************** Bit definition for LTDC_CDSR register *****************/
AnnaBridge 172:65be27845400 10521
AnnaBridge 172:65be27845400 10522 #define LTDC_CDSR_VDES_Pos (0U)
AnnaBridge 172:65be27845400 10523 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10524 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
AnnaBridge 172:65be27845400 10525 #define LTDC_CDSR_HDES_Pos (1U)
AnnaBridge 172:65be27845400 10526 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10527 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
AnnaBridge 172:65be27845400 10528 #define LTDC_CDSR_VSYNCS_Pos (2U)
AnnaBridge 172:65be27845400 10529 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10530 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
AnnaBridge 172:65be27845400 10531 #define LTDC_CDSR_HSYNCS_Pos (3U)
AnnaBridge 172:65be27845400 10532 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10533 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
AnnaBridge 172:65be27845400 10534
AnnaBridge 172:65be27845400 10535 /******************** Bit definition for LTDC_LxCR register *****************/
AnnaBridge 172:65be27845400 10536
AnnaBridge 172:65be27845400 10537 #define LTDC_LxCR_LEN_Pos (0U)
AnnaBridge 172:65be27845400 10538 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10539 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
AnnaBridge 172:65be27845400 10540 #define LTDC_LxCR_COLKEN_Pos (1U)
AnnaBridge 172:65be27845400 10541 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10542 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
AnnaBridge 172:65be27845400 10543 #define LTDC_LxCR_CLUTEN_Pos (4U)
AnnaBridge 172:65be27845400 10544 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10545 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
AnnaBridge 172:65be27845400 10546
AnnaBridge 172:65be27845400 10547 /******************** Bit definition for LTDC_LxWHPCR register **************/
AnnaBridge 172:65be27845400 10548
AnnaBridge 172:65be27845400 10549 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
AnnaBridge 172:65be27845400 10550 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 10551 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
AnnaBridge 172:65be27845400 10552 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
AnnaBridge 172:65be27845400 10553 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 10554 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
AnnaBridge 172:65be27845400 10555
AnnaBridge 172:65be27845400 10556 /******************** Bit definition for LTDC_LxWVPCR register **************/
AnnaBridge 172:65be27845400 10557
AnnaBridge 172:65be27845400 10558 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
AnnaBridge 172:65be27845400 10559 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 10560 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
AnnaBridge 172:65be27845400 10561 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
AnnaBridge 172:65be27845400 10562 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 10563 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
AnnaBridge 172:65be27845400 10564
AnnaBridge 172:65be27845400 10565 /******************** Bit definition for LTDC_LxCKCR register ***************/
AnnaBridge 172:65be27845400 10566
AnnaBridge 172:65be27845400 10567 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
AnnaBridge 172:65be27845400 10568 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 10569 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
AnnaBridge 172:65be27845400 10570 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
AnnaBridge 172:65be27845400 10571 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10572 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
AnnaBridge 172:65be27845400 10573 #define LTDC_LxCKCR_CKRED_Pos (16U)
AnnaBridge 172:65be27845400 10574 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 10575 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
AnnaBridge 172:65be27845400 10576
AnnaBridge 172:65be27845400 10577 /******************** Bit definition for LTDC_LxPFCR register ***************/
AnnaBridge 172:65be27845400 10578
AnnaBridge 172:65be27845400 10579 #define LTDC_LxPFCR_PF_Pos (0U)
AnnaBridge 172:65be27845400 10580 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 10581 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
AnnaBridge 172:65be27845400 10582
AnnaBridge 172:65be27845400 10583 /******************** Bit definition for LTDC_LxCACR register ***************/
AnnaBridge 172:65be27845400 10584
AnnaBridge 172:65be27845400 10585 #define LTDC_LxCACR_CONSTA_Pos (0U)
AnnaBridge 172:65be27845400 10586 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 10587 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
AnnaBridge 172:65be27845400 10588
AnnaBridge 172:65be27845400 10589 /******************** Bit definition for LTDC_LxDCCR register ***************/
AnnaBridge 172:65be27845400 10590
AnnaBridge 172:65be27845400 10591 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
AnnaBridge 172:65be27845400 10592 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 10593 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
AnnaBridge 172:65be27845400 10594 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
AnnaBridge 172:65be27845400 10595 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10596 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
AnnaBridge 172:65be27845400 10597 #define LTDC_LxDCCR_DCRED_Pos (16U)
AnnaBridge 172:65be27845400 10598 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 10599 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
AnnaBridge 172:65be27845400 10600 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
AnnaBridge 172:65be27845400 10601 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 10602 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
AnnaBridge 172:65be27845400 10603
AnnaBridge 172:65be27845400 10604 /******************** Bit definition for LTDC_LxBFCR register ***************/
AnnaBridge 172:65be27845400 10605
AnnaBridge 172:65be27845400 10606 #define LTDC_LxBFCR_BF2_Pos (0U)
AnnaBridge 172:65be27845400 10607 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 10608 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
AnnaBridge 172:65be27845400 10609 #define LTDC_LxBFCR_BF1_Pos (8U)
AnnaBridge 172:65be27845400 10610 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 10611 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
AnnaBridge 172:65be27845400 10612
AnnaBridge 172:65be27845400 10613 /******************** Bit definition for LTDC_LxCFBAR register **************/
AnnaBridge 172:65be27845400 10614
AnnaBridge 172:65be27845400 10615 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
AnnaBridge 172:65be27845400 10616 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 10617 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
AnnaBridge 172:65be27845400 10618
AnnaBridge 172:65be27845400 10619 /******************** Bit definition for LTDC_LxCFBLR register **************/
AnnaBridge 172:65be27845400 10620
AnnaBridge 172:65be27845400 10621 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
AnnaBridge 172:65be27845400 10622 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
AnnaBridge 172:65be27845400 10623 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
AnnaBridge 172:65be27845400 10624 #define LTDC_LxCFBLR_CFBP_Pos (16U)
AnnaBridge 172:65be27845400 10625 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
AnnaBridge 172:65be27845400 10626 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
AnnaBridge 172:65be27845400 10627
AnnaBridge 172:65be27845400 10628 /******************** Bit definition for LTDC_LxCFBLNR register *************/
AnnaBridge 172:65be27845400 10629
AnnaBridge 172:65be27845400 10630 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
AnnaBridge 172:65be27845400 10631 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 10632 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
AnnaBridge 172:65be27845400 10633
AnnaBridge 172:65be27845400 10634 /******************** Bit definition for LTDC_LxCLUTWR register *************/
AnnaBridge 172:65be27845400 10635
AnnaBridge 172:65be27845400 10636 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
AnnaBridge 172:65be27845400 10637 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 10638 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
AnnaBridge 172:65be27845400 10639 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
AnnaBridge 172:65be27845400 10640 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10641 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
AnnaBridge 172:65be27845400 10642 #define LTDC_LxCLUTWR_RED_Pos (16U)
AnnaBridge 172:65be27845400 10643 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 10644 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
AnnaBridge 172:65be27845400 10645 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
AnnaBridge 172:65be27845400 10646 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 10647 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
AnnaBridge 172:65be27845400 10648
AnnaBridge 172:65be27845400 10649
AnnaBridge 172:65be27845400 10650 /******************************************************************************/
AnnaBridge 172:65be27845400 10651 /* */
AnnaBridge 172:65be27845400 10652 /* Power Control */
AnnaBridge 172:65be27845400 10653 /* */
AnnaBridge 172:65be27845400 10654 /******************************************************************************/
AnnaBridge 172:65be27845400 10655 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 172:65be27845400 10656 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 172:65be27845400 10657 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10658 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 172:65be27845400 10659 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 172:65be27845400 10660 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10661 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 172:65be27845400 10662 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 172:65be27845400 10663 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10664 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 172:65be27845400 10665 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 172:65be27845400 10666 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10667 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 172:65be27845400 10668 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 172:65be27845400 10669 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10670 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 172:65be27845400 10671
AnnaBridge 172:65be27845400 10672 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 172:65be27845400 10673 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 172:65be27845400 10674 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 172:65be27845400 10675 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10676 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10677 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10678
AnnaBridge 172:65be27845400 10679 /*!< PVD level configuration */
AnnaBridge 172:65be27845400 10680 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 172:65be27845400 10681 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 172:65be27845400 10682 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 172:65be27845400 10683 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 172:65be27845400 10684 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 172:65be27845400 10685 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 172:65be27845400 10686 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 172:65be27845400 10687 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 172:65be27845400 10688 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 172:65be27845400 10689 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10690 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 172:65be27845400 10691 #define PWR_CR_FPDS_Pos (9U)
AnnaBridge 172:65be27845400 10692 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10693 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 172:65be27845400 10694 #define PWR_CR_LPLVDS_Pos (10U)
AnnaBridge 172:65be27845400 10695 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10696 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
AnnaBridge 172:65be27845400 10697 #define PWR_CR_MRLVDS_Pos (11U)
AnnaBridge 172:65be27845400 10698 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10699 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
AnnaBridge 172:65be27845400 10700 #define PWR_CR_ADCDC1_Pos (13U)
AnnaBridge 172:65be27845400 10701 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10702 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 172:65be27845400 10703 #define PWR_CR_VOS_Pos (14U)
AnnaBridge 172:65be27845400 10704 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 10705 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 172:65be27845400 10706 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
AnnaBridge 172:65be27845400 10707 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
AnnaBridge 172:65be27845400 10708 #define PWR_CR_ODEN_Pos (16U)
AnnaBridge 172:65be27845400 10709 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10710 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
AnnaBridge 172:65be27845400 10711 #define PWR_CR_ODSWEN_Pos (17U)
AnnaBridge 172:65be27845400 10712 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10713 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
AnnaBridge 172:65be27845400 10714 #define PWR_CR_UDEN_Pos (18U)
AnnaBridge 172:65be27845400 10715 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 10716 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
AnnaBridge 172:65be27845400 10717 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10718 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10719
AnnaBridge 172:65be27845400 10720 /* Legacy define */
AnnaBridge 172:65be27845400 10721 #define PWR_CR_PMODE PWR_CR_VOS
AnnaBridge 172:65be27845400 10722 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
AnnaBridge 172:65be27845400 10723 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
AnnaBridge 172:65be27845400 10724
AnnaBridge 172:65be27845400 10725 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 172:65be27845400 10726 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 172:65be27845400 10727 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10728 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 172:65be27845400 10729 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 172:65be27845400 10730 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10731 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 172:65be27845400 10732 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 172:65be27845400 10733 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10734 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 172:65be27845400 10735 #define PWR_CSR_BRR_Pos (3U)
AnnaBridge 172:65be27845400 10736 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10737 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 172:65be27845400 10738 #define PWR_CSR_EWUP_Pos (8U)
AnnaBridge 172:65be27845400 10739 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10740 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
AnnaBridge 172:65be27845400 10741 #define PWR_CSR_BRE_Pos (9U)
AnnaBridge 172:65be27845400 10742 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10743 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 172:65be27845400 10744 #define PWR_CSR_VOSRDY_Pos (14U)
AnnaBridge 172:65be27845400 10745 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10746 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
AnnaBridge 172:65be27845400 10747 #define PWR_CSR_ODRDY_Pos (16U)
AnnaBridge 172:65be27845400 10748 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10749 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
AnnaBridge 172:65be27845400 10750 #define PWR_CSR_ODSWRDY_Pos (17U)
AnnaBridge 172:65be27845400 10751 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10752 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
AnnaBridge 172:65be27845400 10753 #define PWR_CSR_UDRDY_Pos (18U)
AnnaBridge 172:65be27845400 10754 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 10755 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
AnnaBridge 172:65be27845400 10756 /* Legacy define */
AnnaBridge 172:65be27845400 10757 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
AnnaBridge 172:65be27845400 10758
AnnaBridge 172:65be27845400 10759 /* Legacy define */
AnnaBridge 172:65be27845400 10760 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
AnnaBridge 172:65be27845400 10761
AnnaBridge 172:65be27845400 10762 /******************************************************************************/
AnnaBridge 172:65be27845400 10763 /* */
AnnaBridge 172:65be27845400 10764 /* Reset and Clock Control */
AnnaBridge 172:65be27845400 10765 /* */
AnnaBridge 172:65be27845400 10766 /******************************************************************************/
AnnaBridge 172:65be27845400 10767 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 172:65be27845400 10768 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 172:65be27845400 10769 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10770 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 172:65be27845400 10771 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 172:65be27845400 10772 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10773 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 172:65be27845400 10774
AnnaBridge 172:65be27845400 10775 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 172:65be27845400 10776 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 172:65be27845400 10777 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 172:65be27845400 10778 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10779 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10780 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10781 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10782 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10783
AnnaBridge 172:65be27845400 10784 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 172:65be27845400 10785 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10786 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 172:65be27845400 10787 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10788 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10789 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10790 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10791 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10792 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10793 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10794 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10795
AnnaBridge 172:65be27845400 10796 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 172:65be27845400 10797 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10798 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 172:65be27845400 10799 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 172:65be27845400 10800 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10801 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 172:65be27845400 10802 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 172:65be27845400 10803 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10804 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 172:65be27845400 10805 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 172:65be27845400 10806 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10807 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 172:65be27845400 10808 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 172:65be27845400 10809 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10810 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 172:65be27845400 10811 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 172:65be27845400 10812 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10813 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 172:65be27845400 10814 /*
AnnaBridge 172:65be27845400 10815 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 172:65be27845400 10816 */
AnnaBridge 172:65be27845400 10817 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
AnnaBridge 172:65be27845400 10818
AnnaBridge 172:65be27845400 10819 #define RCC_CR_PLLI2SON_Pos (26U)
AnnaBridge 172:65be27845400 10820 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10821 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
AnnaBridge 172:65be27845400 10822 #define RCC_CR_PLLI2SRDY_Pos (27U)
AnnaBridge 172:65be27845400 10823 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10824 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
AnnaBridge 172:65be27845400 10825 /*
AnnaBridge 172:65be27845400 10826 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 172:65be27845400 10827 */
AnnaBridge 172:65be27845400 10828 #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
AnnaBridge 172:65be27845400 10829
AnnaBridge 172:65be27845400 10830 #define RCC_CR_PLLSAION_Pos (28U)
AnnaBridge 172:65be27845400 10831 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10832 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
AnnaBridge 172:65be27845400 10833 #define RCC_CR_PLLSAIRDY_Pos (29U)
AnnaBridge 172:65be27845400 10834 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 10835 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
AnnaBridge 172:65be27845400 10836
AnnaBridge 172:65be27845400 10837 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 172:65be27845400 10838 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 172:65be27845400 10839 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 10840 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 172:65be27845400 10841 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10842 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10843 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10844 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10845 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10846 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10847
AnnaBridge 172:65be27845400 10848 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 172:65be27845400 10849 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 172:65be27845400 10850 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 172:65be27845400 10851 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10852 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10853 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10854 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10855 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10856 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10857 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10858 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10859 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10860
AnnaBridge 172:65be27845400 10861 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 172:65be27845400 10862 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 10863 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 172:65be27845400 10864 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10865 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10866
AnnaBridge 172:65be27845400 10867 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 172:65be27845400 10868 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10869 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 172:65be27845400 10870 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 172:65be27845400 10871 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10872 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 172:65be27845400 10873 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 172:65be27845400 10874
AnnaBridge 172:65be27845400 10875 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 172:65be27845400 10876 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 10877 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 172:65be27845400 10878 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10879 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10880 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10881 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10882
AnnaBridge 172:65be27845400 10883
AnnaBridge 172:65be27845400 10884 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 172:65be27845400 10885 /*!< SW configuration */
AnnaBridge 172:65be27845400 10886 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 172:65be27845400 10887 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 10888 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 172:65be27845400 10889 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10890 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10891
AnnaBridge 172:65be27845400 10892 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 172:65be27845400 10893 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 172:65be27845400 10894 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
AnnaBridge 172:65be27845400 10895
AnnaBridge 172:65be27845400 10896 /*!< SWS configuration */
AnnaBridge 172:65be27845400 10897 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 172:65be27845400 10898 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 10899 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 172:65be27845400 10900 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10901 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10902
AnnaBridge 172:65be27845400 10903 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 172:65be27845400 10904 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 172:65be27845400 10905 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
AnnaBridge 172:65be27845400 10906
AnnaBridge 172:65be27845400 10907 /*!< HPRE configuration */
AnnaBridge 172:65be27845400 10908 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 172:65be27845400 10909 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 10910 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 172:65be27845400 10911 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10912 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10913 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10914 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10915
AnnaBridge 172:65be27845400 10916 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 172:65be27845400 10917 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 172:65be27845400 10918 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 172:65be27845400 10919 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 172:65be27845400 10920 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 172:65be27845400 10921 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 172:65be27845400 10922 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 172:65be27845400 10923 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 172:65be27845400 10924 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
AnnaBridge 172:65be27845400 10925
AnnaBridge 172:65be27845400 10926 /*!< PPRE1 configuration */
AnnaBridge 172:65be27845400 10927 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 172:65be27845400 10928 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 172:65be27845400 10929 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 172:65be27845400 10930 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10931 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10932 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10933
AnnaBridge 172:65be27845400 10934 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 172:65be27845400 10935 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 172:65be27845400 10936 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 172:65be27845400 10937 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 172:65be27845400 10938 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
AnnaBridge 172:65be27845400 10939
AnnaBridge 172:65be27845400 10940 /*!< PPRE2 configuration */
AnnaBridge 172:65be27845400 10941 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 172:65be27845400 10942 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 10943 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 172:65be27845400 10944 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10945 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10946 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10947
AnnaBridge 172:65be27845400 10948 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 172:65be27845400 10949 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 172:65be27845400 10950 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 172:65be27845400 10951 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 172:65be27845400 10952 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
AnnaBridge 172:65be27845400 10953
AnnaBridge 172:65be27845400 10954 /*!< RTCPRE configuration */
AnnaBridge 172:65be27845400 10955 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 172:65be27845400 10956 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 10957 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 172:65be27845400 10958 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10959 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10960 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10961 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10962 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10963
AnnaBridge 172:65be27845400 10964 /*!< MCO1 configuration */
AnnaBridge 172:65be27845400 10965 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 172:65be27845400 10966 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 10967 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 172:65be27845400 10968 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10969 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10970
AnnaBridge 172:65be27845400 10971 #define RCC_CFGR_I2SSRC_Pos (23U)
AnnaBridge 172:65be27845400 10972 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10973 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
AnnaBridge 172:65be27845400 10974
AnnaBridge 172:65be27845400 10975 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 172:65be27845400 10976 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 10977 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 172:65be27845400 10978 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10979 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10980 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10981
AnnaBridge 172:65be27845400 10982 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 172:65be27845400 10983 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 172:65be27845400 10984 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 172:65be27845400 10985 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10986 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10987 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 10988
AnnaBridge 172:65be27845400 10989 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 172:65be27845400 10990 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 10991 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 172:65be27845400 10992 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10993 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10994
AnnaBridge 172:65be27845400 10995 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 172:65be27845400 10996 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 172:65be27845400 10997 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10998 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 172:65be27845400 10999 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 172:65be27845400 11000 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11001 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 172:65be27845400 11002 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 172:65be27845400 11003 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11004 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 172:65be27845400 11005 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 172:65be27845400 11006 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11007 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 172:65be27845400 11008 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 172:65be27845400 11009 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11010 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 172:65be27845400 11011 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
AnnaBridge 172:65be27845400 11012 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11013 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
AnnaBridge 172:65be27845400 11014
AnnaBridge 172:65be27845400 11015 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
AnnaBridge 172:65be27845400 11016 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11017 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
AnnaBridge 172:65be27845400 11018 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 172:65be27845400 11019 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11020 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 172:65be27845400 11021 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 172:65be27845400 11022 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11023 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 172:65be27845400 11024 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 172:65be27845400 11025 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11026 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 172:65be27845400 11027 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 172:65be27845400 11028 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11029 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 172:65be27845400 11030 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 172:65be27845400 11031 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11032 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 172:65be27845400 11033 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 172:65be27845400 11034 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11035 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 172:65be27845400 11036 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
AnnaBridge 172:65be27845400 11037 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11038 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
AnnaBridge 172:65be27845400 11039
AnnaBridge 172:65be27845400 11040 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
AnnaBridge 172:65be27845400 11041 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11042 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
AnnaBridge 172:65be27845400 11043 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 172:65be27845400 11044 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11045 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 172:65be27845400 11046 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 172:65be27845400 11047 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11048 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 172:65be27845400 11049 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 172:65be27845400 11050 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11051 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 172:65be27845400 11052 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 172:65be27845400 11053 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11054 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 172:65be27845400 11055 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 172:65be27845400 11056 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11057 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 172:65be27845400 11058 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
AnnaBridge 172:65be27845400 11059 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11060 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
AnnaBridge 172:65be27845400 11061 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
AnnaBridge 172:65be27845400 11062 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11063 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
AnnaBridge 172:65be27845400 11064
AnnaBridge 172:65be27845400 11065 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 172:65be27845400 11066 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11067 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
AnnaBridge 172:65be27845400 11068
AnnaBridge 172:65be27845400 11069 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 172:65be27845400 11070 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 172:65be27845400 11071 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11072 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 172:65be27845400 11073 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 172:65be27845400 11074 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11075 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 172:65be27845400 11076 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 172:65be27845400 11077 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11078 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 172:65be27845400 11079 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
AnnaBridge 172:65be27845400 11080 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11081 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
AnnaBridge 172:65be27845400 11082 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
AnnaBridge 172:65be27845400 11083 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11084 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
AnnaBridge 172:65be27845400 11085 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
AnnaBridge 172:65be27845400 11086 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11087 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
AnnaBridge 172:65be27845400 11088 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
AnnaBridge 172:65be27845400 11089 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11090 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
AnnaBridge 172:65be27845400 11091 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 172:65be27845400 11092 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11093 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 172:65be27845400 11094 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
AnnaBridge 172:65be27845400 11095 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11096 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
AnnaBridge 172:65be27845400 11097 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
AnnaBridge 172:65be27845400 11098 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11099 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
AnnaBridge 172:65be27845400 11100 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
AnnaBridge 172:65be27845400 11101 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11102 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
AnnaBridge 172:65be27845400 11103 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 172:65be27845400 11104 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11105 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 172:65be27845400 11106 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 172:65be27845400 11107 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11108 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 172:65be27845400 11109 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 172:65be27845400 11110 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11111 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 172:65be27845400 11112 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
AnnaBridge 172:65be27845400 11113 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11114 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
AnnaBridge 172:65be27845400 11115 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
AnnaBridge 172:65be27845400 11116 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11117 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
AnnaBridge 172:65be27845400 11118 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
AnnaBridge 172:65be27845400 11119 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11120 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
AnnaBridge 172:65be27845400 11121
AnnaBridge 172:65be27845400 11122 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 172:65be27845400 11123 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
AnnaBridge 172:65be27845400 11124 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11125 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
AnnaBridge 172:65be27845400 11126 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
AnnaBridge 172:65be27845400 11127 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11128 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
AnnaBridge 172:65be27845400 11129 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
AnnaBridge 172:65be27845400 11130 #define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11131 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
AnnaBridge 172:65be27845400 11132 /* maintained for legacy purpose */
AnnaBridge 172:65be27845400 11133 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
AnnaBridge 172:65be27845400 11134 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
AnnaBridge 172:65be27845400 11135 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11136 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
AnnaBridge 172:65be27845400 11137 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
AnnaBridge 172:65be27845400 11138 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11139 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
AnnaBridge 172:65be27845400 11140 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 172:65be27845400 11141 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
AnnaBridge 172:65be27845400 11142 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11143 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
AnnaBridge 172:65be27845400 11144
AnnaBridge 172:65be27845400 11145
AnnaBridge 172:65be27845400 11146 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 172:65be27845400 11147 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 172:65be27845400 11148 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11149 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
AnnaBridge 172:65be27845400 11150 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 172:65be27845400 11151 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11152 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
AnnaBridge 172:65be27845400 11153 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 172:65be27845400 11154 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11155 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
AnnaBridge 172:65be27845400 11156 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 172:65be27845400 11157 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11158 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 172:65be27845400 11159 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 172:65be27845400 11160 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11161 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
AnnaBridge 172:65be27845400 11162 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 172:65be27845400 11163 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11164 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
AnnaBridge 172:65be27845400 11165 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
AnnaBridge 172:65be27845400 11166 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11167 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
AnnaBridge 172:65be27845400 11168 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
AnnaBridge 172:65be27845400 11169 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11170 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
AnnaBridge 172:65be27845400 11171 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
AnnaBridge 172:65be27845400 11172 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11173 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
AnnaBridge 172:65be27845400 11174 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 172:65be27845400 11175 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11176 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 172:65be27845400 11177 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 172:65be27845400 11178 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11179 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 172:65be27845400 11180 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 172:65be27845400 11181 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11182 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
AnnaBridge 172:65be27845400 11183 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 172:65be27845400 11184 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11185 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 172:65be27845400 11186 #define RCC_APB1RSTR_USART3RST_Pos (18U)
AnnaBridge 172:65be27845400 11187 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11188 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
AnnaBridge 172:65be27845400 11189 #define RCC_APB1RSTR_UART4RST_Pos (19U)
AnnaBridge 172:65be27845400 11190 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11191 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
AnnaBridge 172:65be27845400 11192 #define RCC_APB1RSTR_UART5RST_Pos (20U)
AnnaBridge 172:65be27845400 11193 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11194 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
AnnaBridge 172:65be27845400 11195 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 172:65be27845400 11196 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11197 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 172:65be27845400 11198 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 172:65be27845400 11199 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11200 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 172:65be27845400 11201 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
AnnaBridge 172:65be27845400 11202 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11203 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
AnnaBridge 172:65be27845400 11204 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
AnnaBridge 172:65be27845400 11205 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11206 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
AnnaBridge 172:65be27845400 11207 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
AnnaBridge 172:65be27845400 11208 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11209 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
AnnaBridge 172:65be27845400 11210 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 172:65be27845400 11211 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11212 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
AnnaBridge 172:65be27845400 11213 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 172:65be27845400 11214 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11215 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
AnnaBridge 172:65be27845400 11216 #define RCC_APB1RSTR_UART7RST_Pos (30U)
AnnaBridge 172:65be27845400 11217 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11218 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
AnnaBridge 172:65be27845400 11219 #define RCC_APB1RSTR_UART8RST_Pos (31U)
AnnaBridge 172:65be27845400 11220 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11221 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
AnnaBridge 172:65be27845400 11222
AnnaBridge 172:65be27845400 11223 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 172:65be27845400 11224 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 172:65be27845400 11225 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11226 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 172:65be27845400 11227 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
AnnaBridge 172:65be27845400 11228 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11229 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
AnnaBridge 172:65be27845400 11230 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 172:65be27845400 11231 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11232 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 172:65be27845400 11233 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 172:65be27845400 11234 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11235 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 172:65be27845400 11236 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 172:65be27845400 11237 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11238 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 172:65be27845400 11239 #define RCC_APB2RSTR_SDIORST_Pos (11U)
AnnaBridge 172:65be27845400 11240 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11241 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
AnnaBridge 172:65be27845400 11242 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 172:65be27845400 11243 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11244 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 172:65be27845400 11245 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
AnnaBridge 172:65be27845400 11246 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11247 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
AnnaBridge 172:65be27845400 11248 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 172:65be27845400 11249 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11250 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 172:65be27845400 11251 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 172:65be27845400 11252 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11253 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 172:65be27845400 11254 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
AnnaBridge 172:65be27845400 11255 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11256 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
AnnaBridge 172:65be27845400 11257 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 172:65be27845400 11258 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11259 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
AnnaBridge 172:65be27845400 11260 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
AnnaBridge 172:65be27845400 11261 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11262 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
AnnaBridge 172:65be27845400 11263 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
AnnaBridge 172:65be27845400 11264 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11265 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
AnnaBridge 172:65be27845400 11266 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
AnnaBridge 172:65be27845400 11267 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11268 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
AnnaBridge 172:65be27845400 11269 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
AnnaBridge 172:65be27845400 11270 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11271 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
AnnaBridge 172:65be27845400 11272
AnnaBridge 172:65be27845400 11273 /* Old SPI1RST bit definition, maintained for legacy purpose */
AnnaBridge 172:65be27845400 11274 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
AnnaBridge 172:65be27845400 11275
AnnaBridge 172:65be27845400 11276 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 172:65be27845400 11277 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 172:65be27845400 11278 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11279 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 172:65be27845400 11280 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 172:65be27845400 11281 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11282 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 172:65be27845400 11283 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 172:65be27845400 11284 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11285 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 172:65be27845400 11286 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
AnnaBridge 172:65be27845400 11287 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11288 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
AnnaBridge 172:65be27845400 11289 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
AnnaBridge 172:65be27845400 11290 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11291 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
AnnaBridge 172:65be27845400 11292 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
AnnaBridge 172:65be27845400 11293 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11294 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
AnnaBridge 172:65be27845400 11295 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
AnnaBridge 172:65be27845400 11296 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11297 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
AnnaBridge 172:65be27845400 11298 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 172:65be27845400 11299 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11300 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 172:65be27845400 11301 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
AnnaBridge 172:65be27845400 11302 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11303 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
AnnaBridge 172:65be27845400 11304 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
AnnaBridge 172:65be27845400 11305 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11306 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
AnnaBridge 172:65be27845400 11307 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
AnnaBridge 172:65be27845400 11308 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11309 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
AnnaBridge 172:65be27845400 11310 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 172:65be27845400 11311 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11312 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 172:65be27845400 11313 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
AnnaBridge 172:65be27845400 11314 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11315 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
AnnaBridge 172:65be27845400 11316 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
AnnaBridge 172:65be27845400 11317 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11318 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
AnnaBridge 172:65be27845400 11319 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 172:65be27845400 11320 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11321 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 172:65be27845400 11322 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 172:65be27845400 11323 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11324 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 172:65be27845400 11325 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
AnnaBridge 172:65be27845400 11326 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11327 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
AnnaBridge 172:65be27845400 11328 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
AnnaBridge 172:65be27845400 11329 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11330 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
AnnaBridge 172:65be27845400 11331 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
AnnaBridge 172:65be27845400 11332 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11333 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
AnnaBridge 172:65be27845400 11334 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
AnnaBridge 172:65be27845400 11335 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11336 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
AnnaBridge 172:65be27845400 11337 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
AnnaBridge 172:65be27845400 11338 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11339 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
AnnaBridge 172:65be27845400 11340 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
AnnaBridge 172:65be27845400 11341 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11342 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
AnnaBridge 172:65be27845400 11343 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
AnnaBridge 172:65be27845400 11344 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11345 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
AnnaBridge 172:65be27845400 11346 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 172:65be27845400 11347 /*
AnnaBridge 172:65be27845400 11348 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 172:65be27845400 11349 */
AnnaBridge 172:65be27845400 11350 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
AnnaBridge 172:65be27845400 11351
AnnaBridge 172:65be27845400 11352 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
AnnaBridge 172:65be27845400 11353 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11354 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
AnnaBridge 172:65be27845400 11355 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
AnnaBridge 172:65be27845400 11356 #define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11357 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
AnnaBridge 172:65be27845400 11358 #define RCC_AHB2ENR_HASHEN_Pos (5U)
AnnaBridge 172:65be27845400 11359 #define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11360 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
AnnaBridge 172:65be27845400 11361 #define RCC_AHB2ENR_RNGEN_Pos (6U)
AnnaBridge 172:65be27845400 11362 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11363 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
AnnaBridge 172:65be27845400 11364 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
AnnaBridge 172:65be27845400 11365 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11366 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
AnnaBridge 172:65be27845400 11367
AnnaBridge 172:65be27845400 11368 /******************** Bit definition for RCC_AHB3ENR register ***************/
AnnaBridge 172:65be27845400 11369 /*
AnnaBridge 172:65be27845400 11370 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 172:65be27845400 11371 */
AnnaBridge 172:65be27845400 11372 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
AnnaBridge 172:65be27845400 11373
AnnaBridge 172:65be27845400 11374 #define RCC_AHB3ENR_FMCEN_Pos (0U)
AnnaBridge 172:65be27845400 11375 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11376 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
AnnaBridge 172:65be27845400 11377
AnnaBridge 172:65be27845400 11378 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 172:65be27845400 11379 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 172:65be27845400 11380 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11381 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
AnnaBridge 172:65be27845400 11382 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 172:65be27845400 11383 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11384 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
AnnaBridge 172:65be27845400 11385 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 172:65be27845400 11386 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11387 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
AnnaBridge 172:65be27845400 11388 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 172:65be27845400 11389 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11390 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 172:65be27845400 11391 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 172:65be27845400 11392 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11393 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
AnnaBridge 172:65be27845400 11394 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 172:65be27845400 11395 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11396 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
AnnaBridge 172:65be27845400 11397 #define RCC_APB1ENR_TIM12EN_Pos (6U)
AnnaBridge 172:65be27845400 11398 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11399 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
AnnaBridge 172:65be27845400 11400 #define RCC_APB1ENR_TIM13EN_Pos (7U)
AnnaBridge 172:65be27845400 11401 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11402 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
AnnaBridge 172:65be27845400 11403 #define RCC_APB1ENR_TIM14EN_Pos (8U)
AnnaBridge 172:65be27845400 11404 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11405 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
AnnaBridge 172:65be27845400 11406 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 172:65be27845400 11407 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11408 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 172:65be27845400 11409 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 172:65be27845400 11410 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11411 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 172:65be27845400 11412 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 172:65be27845400 11413 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11414 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
AnnaBridge 172:65be27845400 11415 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 172:65be27845400 11416 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11417 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 172:65be27845400 11418 #define RCC_APB1ENR_USART3EN_Pos (18U)
AnnaBridge 172:65be27845400 11419 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11420 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
AnnaBridge 172:65be27845400 11421 #define RCC_APB1ENR_UART4EN_Pos (19U)
AnnaBridge 172:65be27845400 11422 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11423 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
AnnaBridge 172:65be27845400 11424 #define RCC_APB1ENR_UART5EN_Pos (20U)
AnnaBridge 172:65be27845400 11425 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11426 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
AnnaBridge 172:65be27845400 11427 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 172:65be27845400 11428 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11429 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 172:65be27845400 11430 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 172:65be27845400 11431 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11432 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 172:65be27845400 11433 #define RCC_APB1ENR_I2C3EN_Pos (23U)
AnnaBridge 172:65be27845400 11434 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11435 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
AnnaBridge 172:65be27845400 11436 #define RCC_APB1ENR_CAN1EN_Pos (25U)
AnnaBridge 172:65be27845400 11437 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11438 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
AnnaBridge 172:65be27845400 11439 #define RCC_APB1ENR_CAN2EN_Pos (26U)
AnnaBridge 172:65be27845400 11440 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11441 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
AnnaBridge 172:65be27845400 11442 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 172:65be27845400 11443 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11444 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
AnnaBridge 172:65be27845400 11445 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 172:65be27845400 11446 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11447 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
AnnaBridge 172:65be27845400 11448 #define RCC_APB1ENR_UART7EN_Pos (30U)
AnnaBridge 172:65be27845400 11449 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11450 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
AnnaBridge 172:65be27845400 11451 #define RCC_APB1ENR_UART8EN_Pos (31U)
AnnaBridge 172:65be27845400 11452 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11453 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
AnnaBridge 172:65be27845400 11454
AnnaBridge 172:65be27845400 11455 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 172:65be27845400 11456 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 172:65be27845400 11457 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11458 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 172:65be27845400 11459 #define RCC_APB2ENR_TIM8EN_Pos (1U)
AnnaBridge 172:65be27845400 11460 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11461 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
AnnaBridge 172:65be27845400 11462 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 172:65be27845400 11463 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11464 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 172:65be27845400 11465 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 172:65be27845400 11466 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11467 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 172:65be27845400 11468 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 172:65be27845400 11469 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11470 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 172:65be27845400 11471 #define RCC_APB2ENR_ADC2EN_Pos (9U)
AnnaBridge 172:65be27845400 11472 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11473 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
AnnaBridge 172:65be27845400 11474 #define RCC_APB2ENR_ADC3EN_Pos (10U)
AnnaBridge 172:65be27845400 11475 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11476 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
AnnaBridge 172:65be27845400 11477 #define RCC_APB2ENR_SDIOEN_Pos (11U)
AnnaBridge 172:65be27845400 11478 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11479 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
AnnaBridge 172:65be27845400 11480 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 172:65be27845400 11481 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11482 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 172:65be27845400 11483 #define RCC_APB2ENR_SPI4EN_Pos (13U)
AnnaBridge 172:65be27845400 11484 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11485 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
AnnaBridge 172:65be27845400 11486 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 172:65be27845400 11487 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11488 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 172:65be27845400 11489 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 172:65be27845400 11490 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11491 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 172:65be27845400 11492 #define RCC_APB2ENR_TIM10EN_Pos (17U)
AnnaBridge 172:65be27845400 11493 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11494 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
AnnaBridge 172:65be27845400 11495 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 172:65be27845400 11496 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11497 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
AnnaBridge 172:65be27845400 11498 #define RCC_APB2ENR_SPI5EN_Pos (20U)
AnnaBridge 172:65be27845400 11499 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11500 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
AnnaBridge 172:65be27845400 11501 #define RCC_APB2ENR_SPI6EN_Pos (21U)
AnnaBridge 172:65be27845400 11502 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11503 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
AnnaBridge 172:65be27845400 11504 #define RCC_APB2ENR_SAI1EN_Pos (22U)
AnnaBridge 172:65be27845400 11505 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11506 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
AnnaBridge 172:65be27845400 11507 #define RCC_APB2ENR_LTDCEN_Pos (26U)
AnnaBridge 172:65be27845400 11508 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11509 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
AnnaBridge 172:65be27845400 11510
AnnaBridge 172:65be27845400 11511 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 172:65be27845400 11512 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 172:65be27845400 11513 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11514 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 172:65be27845400 11515 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 172:65be27845400 11516 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11517 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 172:65be27845400 11518 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 172:65be27845400 11519 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11520 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 172:65be27845400 11521 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 172:65be27845400 11522 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11523 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
AnnaBridge 172:65be27845400 11524 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 172:65be27845400 11525 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11526 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
AnnaBridge 172:65be27845400 11527 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
AnnaBridge 172:65be27845400 11528 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11529 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
AnnaBridge 172:65be27845400 11530 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
AnnaBridge 172:65be27845400 11531 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11532 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
AnnaBridge 172:65be27845400 11533 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 172:65be27845400 11534 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11535 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 172:65be27845400 11536 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
AnnaBridge 172:65be27845400 11537 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11538 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
AnnaBridge 172:65be27845400 11539 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
AnnaBridge 172:65be27845400 11540 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11541 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
AnnaBridge 172:65be27845400 11542 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
AnnaBridge 172:65be27845400 11543 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11544 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
AnnaBridge 172:65be27845400 11545 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 172:65be27845400 11546 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11547 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 172:65be27845400 11548 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 172:65be27845400 11549 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11550 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 172:65be27845400 11551 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 172:65be27845400 11552 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11553 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 172:65be27845400 11554 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
AnnaBridge 172:65be27845400 11555 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11556 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
AnnaBridge 172:65be27845400 11557 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
AnnaBridge 172:65be27845400 11558 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11559 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
AnnaBridge 172:65be27845400 11560 #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
AnnaBridge 172:65be27845400 11561 #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11562 #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
AnnaBridge 172:65be27845400 11563 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 172:65be27845400 11564 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11565 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 172:65be27845400 11566 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 172:65be27845400 11567 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11568 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 172:65be27845400 11569 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
AnnaBridge 172:65be27845400 11570 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11571 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
AnnaBridge 172:65be27845400 11572
AnnaBridge 172:65be27845400 11573 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
AnnaBridge 172:65be27845400 11574 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11575 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
AnnaBridge 172:65be27845400 11576 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
AnnaBridge 172:65be27845400 11577 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11578 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
AnnaBridge 172:65be27845400 11579 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
AnnaBridge 172:65be27845400 11580 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11581 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
AnnaBridge 172:65be27845400 11582 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
AnnaBridge 172:65be27845400 11583 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11584 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
AnnaBridge 172:65be27845400 11585 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
AnnaBridge 172:65be27845400 11586 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11587 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
AnnaBridge 172:65be27845400 11588 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
AnnaBridge 172:65be27845400 11589 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11590 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
AnnaBridge 172:65be27845400 11591
AnnaBridge 172:65be27845400 11592 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 172:65be27845400 11593 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
AnnaBridge 172:65be27845400 11594 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11595 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
AnnaBridge 172:65be27845400 11596 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
AnnaBridge 172:65be27845400 11597 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11598 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
AnnaBridge 172:65be27845400 11599 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
AnnaBridge 172:65be27845400 11600 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11601 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
AnnaBridge 172:65be27845400 11602 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
AnnaBridge 172:65be27845400 11603 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11604 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
AnnaBridge 172:65be27845400 11605 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
AnnaBridge 172:65be27845400 11606 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11607 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
AnnaBridge 172:65be27845400 11608
AnnaBridge 172:65be27845400 11609 /******************** Bit definition for RCC_AHB3LPENR register *************/
AnnaBridge 172:65be27845400 11610 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
AnnaBridge 172:65be27845400 11611 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11612 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
AnnaBridge 172:65be27845400 11613
AnnaBridge 172:65be27845400 11614 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 172:65be27845400 11615 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 172:65be27845400 11616 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11617 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
AnnaBridge 172:65be27845400 11618 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 172:65be27845400 11619 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11620 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
AnnaBridge 172:65be27845400 11621 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 172:65be27845400 11622 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11623 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
AnnaBridge 172:65be27845400 11624 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 172:65be27845400 11625 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11626 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 172:65be27845400 11627 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
AnnaBridge 172:65be27845400 11628 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11629 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
AnnaBridge 172:65be27845400 11630 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
AnnaBridge 172:65be27845400 11631 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11632 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
AnnaBridge 172:65be27845400 11633 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
AnnaBridge 172:65be27845400 11634 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11635 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
AnnaBridge 172:65be27845400 11636 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
AnnaBridge 172:65be27845400 11637 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11638 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
AnnaBridge 172:65be27845400 11639 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
AnnaBridge 172:65be27845400 11640 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11641 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
AnnaBridge 172:65be27845400 11642 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 172:65be27845400 11643 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11644 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 172:65be27845400 11645 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 172:65be27845400 11646 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11647 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 172:65be27845400 11648 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 172:65be27845400 11649 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11650 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
AnnaBridge 172:65be27845400 11651 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 172:65be27845400 11652 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11653 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 172:65be27845400 11654 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
AnnaBridge 172:65be27845400 11655 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11656 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
AnnaBridge 172:65be27845400 11657 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
AnnaBridge 172:65be27845400 11658 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11659 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
AnnaBridge 172:65be27845400 11660 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
AnnaBridge 172:65be27845400 11661 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11662 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
AnnaBridge 172:65be27845400 11663 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 172:65be27845400 11664 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11665 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 172:65be27845400 11666 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 172:65be27845400 11667 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11668 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 172:65be27845400 11669 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
AnnaBridge 172:65be27845400 11670 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11671 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
AnnaBridge 172:65be27845400 11672 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
AnnaBridge 172:65be27845400 11673 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11674 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
AnnaBridge 172:65be27845400 11675 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
AnnaBridge 172:65be27845400 11676 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11677 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
AnnaBridge 172:65be27845400 11678 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 172:65be27845400 11679 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11680 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
AnnaBridge 172:65be27845400 11681 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
AnnaBridge 172:65be27845400 11682 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11683 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
AnnaBridge 172:65be27845400 11684 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
AnnaBridge 172:65be27845400 11685 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11686 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
AnnaBridge 172:65be27845400 11687 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
AnnaBridge 172:65be27845400 11688 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11689 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
AnnaBridge 172:65be27845400 11690
AnnaBridge 172:65be27845400 11691 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 172:65be27845400 11692 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 172:65be27845400 11693 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11694 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 172:65be27845400 11695 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
AnnaBridge 172:65be27845400 11696 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11697 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
AnnaBridge 172:65be27845400 11698 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 172:65be27845400 11699 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11700 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 172:65be27845400 11701 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 172:65be27845400 11702 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11703 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 172:65be27845400 11704 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 172:65be27845400 11705 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11706 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 172:65be27845400 11707 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
AnnaBridge 172:65be27845400 11708 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11709 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
AnnaBridge 172:65be27845400 11710 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
AnnaBridge 172:65be27845400 11711 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11712 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
AnnaBridge 172:65be27845400 11713 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
AnnaBridge 172:65be27845400 11714 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11715 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
AnnaBridge 172:65be27845400 11716 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 172:65be27845400 11717 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11718 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 172:65be27845400 11719 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
AnnaBridge 172:65be27845400 11720 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11721 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
AnnaBridge 172:65be27845400 11722 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 172:65be27845400 11723 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11724 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 172:65be27845400 11725 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 172:65be27845400 11726 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11727 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 172:65be27845400 11728 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
AnnaBridge 172:65be27845400 11729 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11730 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
AnnaBridge 172:65be27845400 11731 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 172:65be27845400 11732 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11733 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
AnnaBridge 172:65be27845400 11734 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
AnnaBridge 172:65be27845400 11735 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11736 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
AnnaBridge 172:65be27845400 11737 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
AnnaBridge 172:65be27845400 11738 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11739 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
AnnaBridge 172:65be27845400 11740 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
AnnaBridge 172:65be27845400 11741 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11742 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
AnnaBridge 172:65be27845400 11743 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
AnnaBridge 172:65be27845400 11744 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11745 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
AnnaBridge 172:65be27845400 11746
AnnaBridge 172:65be27845400 11747 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 172:65be27845400 11748 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 172:65be27845400 11749 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11750 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 172:65be27845400 11751 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 172:65be27845400 11752 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11753 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 172:65be27845400 11754 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 172:65be27845400 11755 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11756 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 172:65be27845400 11757
AnnaBridge 172:65be27845400 11758 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 172:65be27845400 11759 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 11760 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 172:65be27845400 11761 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11762 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11763
AnnaBridge 172:65be27845400 11764 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 172:65be27845400 11765 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11766 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 172:65be27845400 11767 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 172:65be27845400 11768 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11769 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 172:65be27845400 11770
AnnaBridge 172:65be27845400 11771 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 172:65be27845400 11772 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 172:65be27845400 11773 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11774 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 172:65be27845400 11775 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 172:65be27845400 11776 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11777 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 172:65be27845400 11778 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 172:65be27845400 11779 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11780 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 172:65be27845400 11781 #define RCC_CSR_BORRSTF_Pos (25U)
AnnaBridge 172:65be27845400 11782 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11783 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 172:65be27845400 11784 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 172:65be27845400 11785 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11786 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 172:65be27845400 11787 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 172:65be27845400 11788 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11789 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 172:65be27845400 11790 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 172:65be27845400 11791 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11792 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 172:65be27845400 11793 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 172:65be27845400 11794 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11795 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 172:65be27845400 11796 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 172:65be27845400 11797 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11798 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 172:65be27845400 11799 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 172:65be27845400 11800 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11801 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 172:65be27845400 11802 /* Legacy defines */
AnnaBridge 172:65be27845400 11803 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
AnnaBridge 172:65be27845400 11804 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
AnnaBridge 172:65be27845400 11805
AnnaBridge 172:65be27845400 11806 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 172:65be27845400 11807 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 172:65be27845400 11808 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 172:65be27845400 11809 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 172:65be27845400 11810 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 172:65be27845400 11811 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 172:65be27845400 11812 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 172:65be27845400 11813 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 172:65be27845400 11814 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11815 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 172:65be27845400 11816 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 172:65be27845400 11817 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11818 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
AnnaBridge 172:65be27845400 11819
AnnaBridge 172:65be27845400 11820 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 172:65be27845400 11821 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
AnnaBridge 172:65be27845400 11822 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
AnnaBridge 172:65be27845400 11823 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
AnnaBridge 172:65be27845400 11824 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11825 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11826 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11827 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11828 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11829 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11830 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11831 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11832 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11833
AnnaBridge 172:65be27845400 11834 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
AnnaBridge 172:65be27845400 11835 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 11836 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
AnnaBridge 172:65be27845400 11837 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11838 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11839 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11840 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11841 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
AnnaBridge 172:65be27845400 11842 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 11843 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
AnnaBridge 172:65be27845400 11844 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11845 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11846 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11847
AnnaBridge 172:65be27845400 11848 /******************** Bit definition for RCC_PLLSAICFGR register ************/
AnnaBridge 172:65be27845400 11849 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
AnnaBridge 172:65be27845400 11850 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
AnnaBridge 172:65be27845400 11851 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
AnnaBridge 172:65be27845400 11852 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11853 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11854 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11855 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11856 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11857 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11858 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11859 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11860 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11861
AnnaBridge 172:65be27845400 11862
AnnaBridge 172:65be27845400 11863 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
AnnaBridge 172:65be27845400 11864 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 11865 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
AnnaBridge 172:65be27845400 11866 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11867 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11868 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11869 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11870
AnnaBridge 172:65be27845400 11871 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
AnnaBridge 172:65be27845400 11872 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 11873 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
AnnaBridge 172:65be27845400 11874 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11875 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11876 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11877
AnnaBridge 172:65be27845400 11878 /******************** Bit definition for RCC_DCKCFGR register ***************/
AnnaBridge 172:65be27845400 11879 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
AnnaBridge 172:65be27845400 11880 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 11881 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
AnnaBridge 172:65be27845400 11882 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11883 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11884 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11885 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11886 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11887
AnnaBridge 172:65be27845400 11888 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
AnnaBridge 172:65be27845400 11889 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 11890 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
AnnaBridge 172:65be27845400 11891 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11892 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11893 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11894 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11895 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11896 #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
AnnaBridge 172:65be27845400 11897 #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 11898 #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
AnnaBridge 172:65be27845400 11899 #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11900 #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11901
AnnaBridge 172:65be27845400 11902 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
AnnaBridge 172:65be27845400 11903 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 11904 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
AnnaBridge 172:65be27845400 11905 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11906 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11907 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
AnnaBridge 172:65be27845400 11908 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 11909 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
AnnaBridge 172:65be27845400 11910 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11911 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11912 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
AnnaBridge 172:65be27845400 11913 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11914 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
AnnaBridge 172:65be27845400 11915
AnnaBridge 172:65be27845400 11916
AnnaBridge 172:65be27845400 11917 /******************************************************************************/
AnnaBridge 172:65be27845400 11918 /* */
AnnaBridge 172:65be27845400 11919 /* RNG */
AnnaBridge 172:65be27845400 11920 /* */
AnnaBridge 172:65be27845400 11921 /******************************************************************************/
AnnaBridge 172:65be27845400 11922 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 172:65be27845400 11923 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 172:65be27845400 11924 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11925 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 172:65be27845400 11926 #define RNG_CR_IE_Pos (3U)
AnnaBridge 172:65be27845400 11927 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11928 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 172:65be27845400 11929
AnnaBridge 172:65be27845400 11930 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 172:65be27845400 11931 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 172:65be27845400 11932 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11933 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 172:65be27845400 11934 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 172:65be27845400 11935 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11936 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 172:65be27845400 11937 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 172:65be27845400 11938 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11939 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 172:65be27845400 11940 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 172:65be27845400 11941 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11942 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 172:65be27845400 11943 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 172:65be27845400 11944 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11945 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 172:65be27845400 11946
AnnaBridge 172:65be27845400 11947 /******************************************************************************/
AnnaBridge 172:65be27845400 11948 /* */
AnnaBridge 172:65be27845400 11949 /* Real-Time Clock (RTC) */
AnnaBridge 172:65be27845400 11950 /* */
AnnaBridge 172:65be27845400 11951 /******************************************************************************/
AnnaBridge 172:65be27845400 11952 /*
AnnaBridge 172:65be27845400 11953 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 172:65be27845400 11954 */
AnnaBridge 172:65be27845400 11955 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
AnnaBridge 172:65be27845400 11956 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
AnnaBridge 172:65be27845400 11957 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 172:65be27845400 11958 #define RTC_TR_PM_Pos (22U)
AnnaBridge 172:65be27845400 11959 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11960 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 172:65be27845400 11961 #define RTC_TR_HT_Pos (20U)
AnnaBridge 172:65be27845400 11962 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 11963 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 172:65be27845400 11964 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11965 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11966 #define RTC_TR_HU_Pos (16U)
AnnaBridge 172:65be27845400 11967 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 11968 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 172:65be27845400 11969 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11970 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11971 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11972 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11973 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 11974 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 11975 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 172:65be27845400 11976 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11977 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11978 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11979 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 11980 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 11981 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 172:65be27845400 11982 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11983 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11984 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11985 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11986 #define RTC_TR_ST_Pos (4U)
AnnaBridge 172:65be27845400 11987 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 11988 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 172:65be27845400 11989 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11990 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11991 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11992 #define RTC_TR_SU_Pos (0U)
AnnaBridge 172:65be27845400 11993 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 11994 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 172:65be27845400 11995 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11996 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11997 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11998 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11999
AnnaBridge 172:65be27845400 12000 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 172:65be27845400 12001 #define RTC_DR_YT_Pos (20U)
AnnaBridge 172:65be27845400 12002 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 12003 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 172:65be27845400 12004 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12005 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12006 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12007 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12008 #define RTC_DR_YU_Pos (16U)
AnnaBridge 172:65be27845400 12009 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 12010 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 172:65be27845400 12011 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12012 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12013 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12014 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12015 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 172:65be27845400 12016 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 12017 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 172:65be27845400 12018 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12019 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12020 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12021 #define RTC_DR_MT_Pos (12U)
AnnaBridge 172:65be27845400 12022 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12023 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 172:65be27845400 12024 #define RTC_DR_MU_Pos (8U)
AnnaBridge 172:65be27845400 12025 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12026 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 172:65be27845400 12027 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12028 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12029 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12030 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12031 #define RTC_DR_DT_Pos (4U)
AnnaBridge 172:65be27845400 12032 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 12033 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 172:65be27845400 12034 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12035 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12036 #define RTC_DR_DU_Pos (0U)
AnnaBridge 172:65be27845400 12037 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 12038 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 172:65be27845400 12039 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12040 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12041 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12042 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12043
AnnaBridge 172:65be27845400 12044 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 172:65be27845400 12045 #define RTC_CR_COE_Pos (23U)
AnnaBridge 172:65be27845400 12046 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12047 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 172:65be27845400 12048 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 172:65be27845400 12049 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 12050 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 172:65be27845400 12051 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12052 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12053 #define RTC_CR_POL_Pos (20U)
AnnaBridge 172:65be27845400 12054 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12055 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 172:65be27845400 12056 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 172:65be27845400 12057 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12058 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 172:65be27845400 12059 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 172:65be27845400 12060 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12061 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 172:65be27845400 12062 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 172:65be27845400 12063 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12064 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 172:65be27845400 12065 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 172:65be27845400 12066 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12067 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 172:65be27845400 12068 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 172:65be27845400 12069 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12070 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 172:65be27845400 12071 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 172:65be27845400 12072 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12073 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 172:65be27845400 12074 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 172:65be27845400 12075 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12076 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 172:65be27845400 12077 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 172:65be27845400 12078 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12079 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 172:65be27845400 12080 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 172:65be27845400 12081 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12082 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 172:65be27845400 12083 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 172:65be27845400 12084 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12085 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 172:65be27845400 12086 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 172:65be27845400 12087 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12088 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 172:65be27845400 12089 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 172:65be27845400 12090 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12091 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 172:65be27845400 12092 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 172:65be27845400 12093 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12094 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 172:65be27845400 12095 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 172:65be27845400 12096 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12097 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 172:65be27845400 12098 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 172:65be27845400 12099 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12100 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 172:65be27845400 12101 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 172:65be27845400 12102 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12103 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 172:65be27845400 12104 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 172:65be27845400 12105 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12106 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 172:65be27845400 12107 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 172:65be27845400 12108 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 12109 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 172:65be27845400 12110 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12111 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12112 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12113
AnnaBridge 172:65be27845400 12114 /* Legacy defines */
AnnaBridge 172:65be27845400 12115 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 172:65be27845400 12116
AnnaBridge 172:65be27845400 12117 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 172:65be27845400 12118 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 172:65be27845400 12119 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12120 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 172:65be27845400 12121 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 172:65be27845400 12122 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12123 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 172:65be27845400 12124 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 172:65be27845400 12125 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12126 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 172:65be27845400 12127 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 172:65be27845400 12128 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12129 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 172:65be27845400 12130 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 172:65be27845400 12131 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12132 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 172:65be27845400 12133 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 172:65be27845400 12134 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12135 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 172:65be27845400 12136 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 172:65be27845400 12137 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12138 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 172:65be27845400 12139 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 172:65be27845400 12140 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12141 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 172:65be27845400 12142 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 172:65be27845400 12143 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12144 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 172:65be27845400 12145 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 172:65be27845400 12146 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12147 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 172:65be27845400 12148 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 172:65be27845400 12149 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12150 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 172:65be27845400 12151 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 172:65be27845400 12152 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12153 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 172:65be27845400 12154 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 172:65be27845400 12155 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12156 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 172:65be27845400 12157 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 172:65be27845400 12158 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12159 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 172:65be27845400 12160 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 172:65be27845400 12161 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12162 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 172:65be27845400 12163 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 172:65be27845400 12164 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12165 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 172:65be27845400 12166
AnnaBridge 172:65be27845400 12167 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 172:65be27845400 12168 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 172:65be27845400 12169 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 12170 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 172:65be27845400 12171 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 172:65be27845400 12172 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 12173 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 172:65be27845400 12174
AnnaBridge 172:65be27845400 12175 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 172:65be27845400 12176 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 172:65be27845400 12177 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 12178 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 172:65be27845400 12179
AnnaBridge 172:65be27845400 12180 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 172:65be27845400 12181 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 172:65be27845400 12182 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12183 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 172:65be27845400 12184 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 172:65be27845400 12185 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 12186 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
AnnaBridge 172:65be27845400 12187
AnnaBridge 172:65be27845400 12188 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 172:65be27845400 12189 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 172:65be27845400 12190 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12191 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 172:65be27845400 12192 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 172:65be27845400 12193 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12194 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 172:65be27845400 12195 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 172:65be27845400 12196 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 12197 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 172:65be27845400 12198 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12199 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12200 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 172:65be27845400 12201 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 12202 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 172:65be27845400 12203 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12204 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12205 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12206 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12207 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 172:65be27845400 12208 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12209 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 172:65be27845400 12210 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 172:65be27845400 12211 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12212 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 172:65be27845400 12213 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 172:65be27845400 12214 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 12215 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 172:65be27845400 12216 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12217 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12218 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 172:65be27845400 12219 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 12220 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 172:65be27845400 12221 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12222 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12223 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12224 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12225 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 172:65be27845400 12226 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12227 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 172:65be27845400 12228 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 12229 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 12230 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 172:65be27845400 12231 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12232 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12233 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12234 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 12235 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12236 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 172:65be27845400 12237 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12238 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12239 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12240 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12241 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 172:65be27845400 12242 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12243 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 172:65be27845400 12244 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 172:65be27845400 12245 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 12246 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 172:65be27845400 12247 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12248 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12249 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12250 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 172:65be27845400 12251 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 12252 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 172:65be27845400 12253 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12254 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12255 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12256 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12257
AnnaBridge 172:65be27845400 12258 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 172:65be27845400 12259 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 172:65be27845400 12260 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12261 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 172:65be27845400 12262 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 172:65be27845400 12263 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12264 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 172:65be27845400 12265 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 172:65be27845400 12266 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 12267 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 172:65be27845400 12268 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12269 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12270 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 172:65be27845400 12271 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 12272 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 172:65be27845400 12273 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12274 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12275 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12276 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12277 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 172:65be27845400 12278 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12279 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 172:65be27845400 12280 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 172:65be27845400 12281 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12282 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 172:65be27845400 12283 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 172:65be27845400 12284 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 12285 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 172:65be27845400 12286 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12287 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12288 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 172:65be27845400 12289 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 12290 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 172:65be27845400 12291 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12292 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12293 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12294 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12295 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 172:65be27845400 12296 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12297 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 172:65be27845400 12298 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 12299 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 12300 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 172:65be27845400 12301 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12302 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12303 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12304 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 12305 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12306 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 172:65be27845400 12307 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12308 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12309 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12310 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12311 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 172:65be27845400 12312 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12313 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 172:65be27845400 12314 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 172:65be27845400 12315 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 12316 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 172:65be27845400 12317 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12318 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12319 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12320 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 172:65be27845400 12321 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 12322 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 172:65be27845400 12323 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12324 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12325 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12326 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12327
AnnaBridge 172:65be27845400 12328 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 172:65be27845400 12329 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 172:65be27845400 12330 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12331 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 172:65be27845400 12332
AnnaBridge 172:65be27845400 12333 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 172:65be27845400 12334 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 12335 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 12336 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 172:65be27845400 12337
AnnaBridge 172:65be27845400 12338 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 172:65be27845400 12339 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 172:65be27845400 12340 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 12341 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 172:65be27845400 12342 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 172:65be27845400 12343 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12344 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 172:65be27845400 12345
AnnaBridge 172:65be27845400 12346 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 172:65be27845400 12347 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 172:65be27845400 12348 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12349 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 172:65be27845400 12350 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 172:65be27845400 12351 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 12352 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 172:65be27845400 12353 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12354 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12355 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 172:65be27845400 12356 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 12357 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 172:65be27845400 12358 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12359 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12360 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12361 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12362 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 12363 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 12364 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 172:65be27845400 12365 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12366 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12367 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12368 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 12369 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12370 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 172:65be27845400 12371 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12372 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12373 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12374 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12375 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 172:65be27845400 12376 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 12377 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 172:65be27845400 12378 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12379 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12380 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12381 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 172:65be27845400 12382 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 12383 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 172:65be27845400 12384 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12385 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12386 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12387 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12388
AnnaBridge 172:65be27845400 12389 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 172:65be27845400 12390 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 172:65be27845400 12391 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 12392 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 172:65be27845400 12393 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12394 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12395 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12396 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 172:65be27845400 12397 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12398 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 172:65be27845400 12399 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 172:65be27845400 12400 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12401 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 172:65be27845400 12402 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12403 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12404 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12405 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12406 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 172:65be27845400 12407 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 12408 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 172:65be27845400 12409 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12410 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12411 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 172:65be27845400 12412 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 12413 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 172:65be27845400 12414 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12415 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12416 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12417 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12418
AnnaBridge 172:65be27845400 12419 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 172:65be27845400 12420 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 12421 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 12422 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 172:65be27845400 12423
AnnaBridge 172:65be27845400 12424 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 172:65be27845400 12425 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 172:65be27845400 12426 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12427 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 172:65be27845400 12428 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 172:65be27845400 12429 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12430 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 172:65be27845400 12431 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 172:65be27845400 12432 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12433 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 172:65be27845400 12434 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 172:65be27845400 12435 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 12436 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 172:65be27845400 12437 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12438 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12439 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12440 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12441 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12442 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12443 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12444 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12445 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12446
AnnaBridge 172:65be27845400 12447 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 172:65be27845400 12448 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 172:65be27845400 12449 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12450 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 172:65be27845400 12451 #define RTC_TAFCR_TSINSEL_Pos (17U)
AnnaBridge 172:65be27845400 12452 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12453 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
AnnaBridge 172:65be27845400 12454 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
AnnaBridge 172:65be27845400 12455 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12456 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
AnnaBridge 172:65be27845400 12457 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 172:65be27845400 12458 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12459 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 172:65be27845400 12460 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 172:65be27845400 12461 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 12462 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 172:65be27845400 12463 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12464 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12465 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 172:65be27845400 12466 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 12467 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 172:65be27845400 12468 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12469 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12470 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 172:65be27845400 12471 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 12472 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 172:65be27845400 12473 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12474 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12475 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12476 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 172:65be27845400 12477 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12478 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 172:65be27845400 12479 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 172:65be27845400 12480 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12481 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 172:65be27845400 12482 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 172:65be27845400 12483 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12484 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 172:65be27845400 12485 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 172:65be27845400 12486 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12487 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 172:65be27845400 12488 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 172:65be27845400 12489 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12490 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 172:65be27845400 12491 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 172:65be27845400 12492 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12493 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 172:65be27845400 12494
AnnaBridge 172:65be27845400 12495 /* Legacy defines */
AnnaBridge 172:65be27845400 12496 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
AnnaBridge 172:65be27845400 12497
AnnaBridge 172:65be27845400 12498 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 172:65be27845400 12499 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 172:65be27845400 12500 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 12501 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 172:65be27845400 12502 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12503 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12504 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12505 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12506 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 12507 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 12508 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 172:65be27845400 12509
AnnaBridge 172:65be27845400 12510 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 172:65be27845400 12511 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 172:65be27845400 12512 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 12513 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 172:65be27845400 12514 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12515 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12516 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12517 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12518 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 12519 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 12520 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 172:65be27845400 12521
AnnaBridge 172:65be27845400 12522 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 172:65be27845400 12523 #define RTC_BKP0R_Pos (0U)
AnnaBridge 172:65be27845400 12524 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12525 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 172:65be27845400 12526
AnnaBridge 172:65be27845400 12527 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 172:65be27845400 12528 #define RTC_BKP1R_Pos (0U)
AnnaBridge 172:65be27845400 12529 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12530 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 172:65be27845400 12531
AnnaBridge 172:65be27845400 12532 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 172:65be27845400 12533 #define RTC_BKP2R_Pos (0U)
AnnaBridge 172:65be27845400 12534 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12535 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 172:65be27845400 12536
AnnaBridge 172:65be27845400 12537 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 172:65be27845400 12538 #define RTC_BKP3R_Pos (0U)
AnnaBridge 172:65be27845400 12539 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12540 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 172:65be27845400 12541
AnnaBridge 172:65be27845400 12542 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 172:65be27845400 12543 #define RTC_BKP4R_Pos (0U)
AnnaBridge 172:65be27845400 12544 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12545 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 172:65be27845400 12546
AnnaBridge 172:65be27845400 12547 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 172:65be27845400 12548 #define RTC_BKP5R_Pos (0U)
AnnaBridge 172:65be27845400 12549 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12550 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 172:65be27845400 12551
AnnaBridge 172:65be27845400 12552 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 172:65be27845400 12553 #define RTC_BKP6R_Pos (0U)
AnnaBridge 172:65be27845400 12554 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12555 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 172:65be27845400 12556
AnnaBridge 172:65be27845400 12557 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 172:65be27845400 12558 #define RTC_BKP7R_Pos (0U)
AnnaBridge 172:65be27845400 12559 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12560 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 172:65be27845400 12561
AnnaBridge 172:65be27845400 12562 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 172:65be27845400 12563 #define RTC_BKP8R_Pos (0U)
AnnaBridge 172:65be27845400 12564 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12565 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 172:65be27845400 12566
AnnaBridge 172:65be27845400 12567 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 172:65be27845400 12568 #define RTC_BKP9R_Pos (0U)
AnnaBridge 172:65be27845400 12569 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12570 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 172:65be27845400 12571
AnnaBridge 172:65be27845400 12572 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 172:65be27845400 12573 #define RTC_BKP10R_Pos (0U)
AnnaBridge 172:65be27845400 12574 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12575 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 172:65be27845400 12576
AnnaBridge 172:65be27845400 12577 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 172:65be27845400 12578 #define RTC_BKP11R_Pos (0U)
AnnaBridge 172:65be27845400 12579 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12580 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 172:65be27845400 12581
AnnaBridge 172:65be27845400 12582 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 172:65be27845400 12583 #define RTC_BKP12R_Pos (0U)
AnnaBridge 172:65be27845400 12584 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12585 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 172:65be27845400 12586
AnnaBridge 172:65be27845400 12587 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 172:65be27845400 12588 #define RTC_BKP13R_Pos (0U)
AnnaBridge 172:65be27845400 12589 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12590 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 172:65be27845400 12591
AnnaBridge 172:65be27845400 12592 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 172:65be27845400 12593 #define RTC_BKP14R_Pos (0U)
AnnaBridge 172:65be27845400 12594 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12595 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 172:65be27845400 12596
AnnaBridge 172:65be27845400 12597 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 172:65be27845400 12598 #define RTC_BKP15R_Pos (0U)
AnnaBridge 172:65be27845400 12599 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12600 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 172:65be27845400 12601
AnnaBridge 172:65be27845400 12602 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 172:65be27845400 12603 #define RTC_BKP16R_Pos (0U)
AnnaBridge 172:65be27845400 12604 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12605 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 172:65be27845400 12606
AnnaBridge 172:65be27845400 12607 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 172:65be27845400 12608 #define RTC_BKP17R_Pos (0U)
AnnaBridge 172:65be27845400 12609 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12610 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 172:65be27845400 12611
AnnaBridge 172:65be27845400 12612 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 172:65be27845400 12613 #define RTC_BKP18R_Pos (0U)
AnnaBridge 172:65be27845400 12614 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12615 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 172:65be27845400 12616
AnnaBridge 172:65be27845400 12617 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 172:65be27845400 12618 #define RTC_BKP19R_Pos (0U)
AnnaBridge 172:65be27845400 12619 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12620 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 172:65be27845400 12621
AnnaBridge 172:65be27845400 12622 /******************** Number of backup registers ******************************/
AnnaBridge 172:65be27845400 12623 #define RTC_BKP_NUMBER 0x000000014U
AnnaBridge 172:65be27845400 12624
AnnaBridge 172:65be27845400 12625 /******************************************************************************/
AnnaBridge 172:65be27845400 12626 /* */
AnnaBridge 172:65be27845400 12627 /* Serial Audio Interface */
AnnaBridge 172:65be27845400 12628 /* */
AnnaBridge 172:65be27845400 12629 /******************************************************************************/
AnnaBridge 172:65be27845400 12630 /******************** Bit definition for SAI_GCR register *******************/
AnnaBridge 172:65be27845400 12631 #define SAI_GCR_SYNCIN_Pos (0U)
AnnaBridge 172:65be27845400 12632 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 12633 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
AnnaBridge 172:65be27845400 12634 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12635 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12636
AnnaBridge 172:65be27845400 12637 #define SAI_GCR_SYNCOUT_Pos (4U)
AnnaBridge 172:65be27845400 12638 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 12639 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
AnnaBridge 172:65be27845400 12640 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12641 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12642
AnnaBridge 172:65be27845400 12643 /******************* Bit definition for SAI_xCR1 register *******************/
AnnaBridge 172:65be27845400 12644 #define SAI_xCR1_MODE_Pos (0U)
AnnaBridge 172:65be27845400 12645 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 12646 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
AnnaBridge 172:65be27845400 12647 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12648 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12649
AnnaBridge 172:65be27845400 12650 #define SAI_xCR1_PRTCFG_Pos (2U)
AnnaBridge 172:65be27845400 12651 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 12652 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
AnnaBridge 172:65be27845400 12653 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12654 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12655
AnnaBridge 172:65be27845400 12656 #define SAI_xCR1_DS_Pos (5U)
AnnaBridge 172:65be27845400 12657 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
AnnaBridge 172:65be27845400 12658 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
AnnaBridge 172:65be27845400 12659 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12660 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12661 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12662
AnnaBridge 172:65be27845400 12663 #define SAI_xCR1_LSBFIRST_Pos (8U)
AnnaBridge 172:65be27845400 12664 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12665 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
AnnaBridge 172:65be27845400 12666 #define SAI_xCR1_CKSTR_Pos (9U)
AnnaBridge 172:65be27845400 12667 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12668 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
AnnaBridge 172:65be27845400 12669
AnnaBridge 172:65be27845400 12670 #define SAI_xCR1_SYNCEN_Pos (10U)
AnnaBridge 172:65be27845400 12671 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 12672 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
AnnaBridge 172:65be27845400 12673 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12674 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12675
AnnaBridge 172:65be27845400 12676 #define SAI_xCR1_MONO_Pos (12U)
AnnaBridge 172:65be27845400 12677 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12678 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
AnnaBridge 172:65be27845400 12679 #define SAI_xCR1_OUTDRIV_Pos (13U)
AnnaBridge 172:65be27845400 12680 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12681 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
AnnaBridge 172:65be27845400 12682 #define SAI_xCR1_SAIEN_Pos (16U)
AnnaBridge 172:65be27845400 12683 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12684 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
AnnaBridge 172:65be27845400 12685 #define SAI_xCR1_DMAEN_Pos (17U)
AnnaBridge 172:65be27845400 12686 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12687 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
AnnaBridge 172:65be27845400 12688 #define SAI_xCR1_NODIV_Pos (19U)
AnnaBridge 172:65be27845400 12689 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12690 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
AnnaBridge 172:65be27845400 12691
AnnaBridge 172:65be27845400 12692 #define SAI_xCR1_MCKDIV_Pos (20U)
AnnaBridge 172:65be27845400 12693 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 12694 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
AnnaBridge 172:65be27845400 12695 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12696 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12697 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12698 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12699
AnnaBridge 172:65be27845400 12700 /******************* Bit definition for SAI_xCR2 register *******************/
AnnaBridge 172:65be27845400 12701 #define SAI_xCR2_FTH_Pos (0U)
AnnaBridge 172:65be27845400 12702 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 12703 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
AnnaBridge 172:65be27845400 12704 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12705 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12706 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12707
AnnaBridge 172:65be27845400 12708 #define SAI_xCR2_FFLUSH_Pos (3U)
AnnaBridge 172:65be27845400 12709 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12710 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
AnnaBridge 172:65be27845400 12711 #define SAI_xCR2_TRIS_Pos (4U)
AnnaBridge 172:65be27845400 12712 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12713 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
AnnaBridge 172:65be27845400 12714 #define SAI_xCR2_MUTE_Pos (5U)
AnnaBridge 172:65be27845400 12715 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12716 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
AnnaBridge 172:65be27845400 12717 #define SAI_xCR2_MUTEVAL_Pos (6U)
AnnaBridge 172:65be27845400 12718 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12719 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
AnnaBridge 172:65be27845400 12720
AnnaBridge 172:65be27845400 12721 #define SAI_xCR2_MUTECNT_Pos (7U)
AnnaBridge 172:65be27845400 12722 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
AnnaBridge 172:65be27845400 12723 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
AnnaBridge 172:65be27845400 12724 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12725 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12726 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12727 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12728 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12729 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12730
AnnaBridge 172:65be27845400 12731 #define SAI_xCR2_CPL_Pos (13U)
AnnaBridge 172:65be27845400 12732 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12733 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
AnnaBridge 172:65be27845400 12734
AnnaBridge 172:65be27845400 12735 #define SAI_xCR2_COMP_Pos (14U)
AnnaBridge 172:65be27845400 12736 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 12737 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
AnnaBridge 172:65be27845400 12738 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12739 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12740
AnnaBridge 172:65be27845400 12741 /****************** Bit definition for SAI_xFRCR register *******************/
AnnaBridge 172:65be27845400 12742 #define SAI_xFRCR_FRL_Pos (0U)
AnnaBridge 172:65be27845400 12743 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12744 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
AnnaBridge 172:65be27845400 12745 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12746 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12747 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12748 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12749 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12750 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12751 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12752 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12753
AnnaBridge 172:65be27845400 12754 #define SAI_xFRCR_FSALL_Pos (8U)
AnnaBridge 172:65be27845400 12755 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
AnnaBridge 172:65be27845400 12756 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
AnnaBridge 172:65be27845400 12757 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12758 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12759 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12760 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12761 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12762 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12763 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12764
AnnaBridge 172:65be27845400 12765 #define SAI_xFRCR_FSDEF_Pos (16U)
AnnaBridge 172:65be27845400 12766 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12767 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
AnnaBridge 172:65be27845400 12768 #define SAI_xFRCR_FSPOL_Pos (17U)
AnnaBridge 172:65be27845400 12769 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12770 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
AnnaBridge 172:65be27845400 12771 #define SAI_xFRCR_FSOFF_Pos (18U)
AnnaBridge 172:65be27845400 12772 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12773 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
AnnaBridge 172:65be27845400 12774 /* Legacy defines */
AnnaBridge 172:65be27845400 12775 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
AnnaBridge 172:65be27845400 12776
AnnaBridge 172:65be27845400 12777 /****************** Bit definition for SAI_xSLOTR register *******************/
AnnaBridge 172:65be27845400 12778 #define SAI_xSLOTR_FBOFF_Pos (0U)
AnnaBridge 172:65be27845400 12779 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 12780 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
AnnaBridge 172:65be27845400 12781 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12782 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12783 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12784 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12785 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12786
AnnaBridge 172:65be27845400 12787 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
AnnaBridge 172:65be27845400 12788 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 12789 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
AnnaBridge 172:65be27845400 12790 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12791 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12792
AnnaBridge 172:65be27845400 12793 #define SAI_xSLOTR_NBSLOT_Pos (8U)
AnnaBridge 172:65be27845400 12794 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12795 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
AnnaBridge 172:65be27845400 12796 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12797 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12798 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12799 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12800
AnnaBridge 172:65be27845400 12801 #define SAI_xSLOTR_SLOTEN_Pos (16U)
AnnaBridge 172:65be27845400 12802 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 12803 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
AnnaBridge 172:65be27845400 12804
AnnaBridge 172:65be27845400 12805 /******************* Bit definition for SAI_xIMR register *******************/
AnnaBridge 172:65be27845400 12806 #define SAI_xIMR_OVRUDRIE_Pos (0U)
AnnaBridge 172:65be27845400 12807 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12808 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
AnnaBridge 172:65be27845400 12809 #define SAI_xIMR_MUTEDETIE_Pos (1U)
AnnaBridge 172:65be27845400 12810 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12811 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
AnnaBridge 172:65be27845400 12812 #define SAI_xIMR_WCKCFGIE_Pos (2U)
AnnaBridge 172:65be27845400 12813 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12814 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
AnnaBridge 172:65be27845400 12815 #define SAI_xIMR_FREQIE_Pos (3U)
AnnaBridge 172:65be27845400 12816 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12817 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
AnnaBridge 172:65be27845400 12818 #define SAI_xIMR_CNRDYIE_Pos (4U)
AnnaBridge 172:65be27845400 12819 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12820 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
AnnaBridge 172:65be27845400 12821 #define SAI_xIMR_AFSDETIE_Pos (5U)
AnnaBridge 172:65be27845400 12822 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12823 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
AnnaBridge 172:65be27845400 12824 #define SAI_xIMR_LFSDETIE_Pos (6U)
AnnaBridge 172:65be27845400 12825 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12826 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
AnnaBridge 172:65be27845400 12827
AnnaBridge 172:65be27845400 12828 /******************** Bit definition for SAI_xSR register *******************/
AnnaBridge 172:65be27845400 12829 #define SAI_xSR_OVRUDR_Pos (0U)
AnnaBridge 172:65be27845400 12830 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12831 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
AnnaBridge 172:65be27845400 12832 #define SAI_xSR_MUTEDET_Pos (1U)
AnnaBridge 172:65be27845400 12833 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12834 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
AnnaBridge 172:65be27845400 12835 #define SAI_xSR_WCKCFG_Pos (2U)
AnnaBridge 172:65be27845400 12836 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12837 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
AnnaBridge 172:65be27845400 12838 #define SAI_xSR_FREQ_Pos (3U)
AnnaBridge 172:65be27845400 12839 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12840 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
AnnaBridge 172:65be27845400 12841 #define SAI_xSR_CNRDY_Pos (4U)
AnnaBridge 172:65be27845400 12842 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12843 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
AnnaBridge 172:65be27845400 12844 #define SAI_xSR_AFSDET_Pos (5U)
AnnaBridge 172:65be27845400 12845 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12846 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
AnnaBridge 172:65be27845400 12847 #define SAI_xSR_LFSDET_Pos (6U)
AnnaBridge 172:65be27845400 12848 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12849 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
AnnaBridge 172:65be27845400 12850
AnnaBridge 172:65be27845400 12851 #define SAI_xSR_FLVL_Pos (16U)
AnnaBridge 172:65be27845400 12852 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 12853 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
AnnaBridge 172:65be27845400 12854 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12855 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12856 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12857
AnnaBridge 172:65be27845400 12858 /****************** Bit definition for SAI_xCLRFR register ******************/
AnnaBridge 172:65be27845400 12859 #define SAI_xCLRFR_COVRUDR_Pos (0U)
AnnaBridge 172:65be27845400 12860 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12861 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
AnnaBridge 172:65be27845400 12862 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
AnnaBridge 172:65be27845400 12863 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12864 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
AnnaBridge 172:65be27845400 12865 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
AnnaBridge 172:65be27845400 12866 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12867 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
AnnaBridge 172:65be27845400 12868 #define SAI_xCLRFR_CFREQ_Pos (3U)
AnnaBridge 172:65be27845400 12869 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12870 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
AnnaBridge 172:65be27845400 12871 #define SAI_xCLRFR_CCNRDY_Pos (4U)
AnnaBridge 172:65be27845400 12872 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12873 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
AnnaBridge 172:65be27845400 12874 #define SAI_xCLRFR_CAFSDET_Pos (5U)
AnnaBridge 172:65be27845400 12875 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12876 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
AnnaBridge 172:65be27845400 12877 #define SAI_xCLRFR_CLFSDET_Pos (6U)
AnnaBridge 172:65be27845400 12878 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12879 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
AnnaBridge 172:65be27845400 12880
AnnaBridge 172:65be27845400 12881 /****************** Bit definition for SAI_xDR register ******************/
AnnaBridge 172:65be27845400 12882 #define SAI_xDR_DATA_Pos (0U)
AnnaBridge 172:65be27845400 12883 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12884 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
AnnaBridge 172:65be27845400 12885
AnnaBridge 172:65be27845400 12886
AnnaBridge 172:65be27845400 12887 /******************************************************************************/
AnnaBridge 172:65be27845400 12888 /* */
AnnaBridge 172:65be27845400 12889 /* SD host Interface */
AnnaBridge 172:65be27845400 12890 /* */
AnnaBridge 172:65be27845400 12891 /******************************************************************************/
AnnaBridge 172:65be27845400 12892 /****************** Bit definition for SDIO_POWER register ******************/
AnnaBridge 172:65be27845400 12893 #define SDIO_POWER_PWRCTRL_Pos (0U)
AnnaBridge 172:65be27845400 12894 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 12895 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 172:65be27845400 12896 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
AnnaBridge 172:65be27845400 12897 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
AnnaBridge 172:65be27845400 12898
AnnaBridge 172:65be27845400 12899 /****************** Bit definition for SDIO_CLKCR register ******************/
AnnaBridge 172:65be27845400 12900 #define SDIO_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 172:65be27845400 12901 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12902 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 172:65be27845400 12903 #define SDIO_CLKCR_CLKEN_Pos (8U)
AnnaBridge 172:65be27845400 12904 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12905 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
AnnaBridge 172:65be27845400 12906 #define SDIO_CLKCR_PWRSAV_Pos (9U)
AnnaBridge 172:65be27845400 12907 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12908 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 172:65be27845400 12909 #define SDIO_CLKCR_BYPASS_Pos (10U)
AnnaBridge 172:65be27845400 12910 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12911 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
AnnaBridge 172:65be27845400 12912
AnnaBridge 172:65be27845400 12913 #define SDIO_CLKCR_WIDBUS_Pos (11U)
AnnaBridge 172:65be27845400 12914 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 12915 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 172:65be27845400 12916 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
AnnaBridge 172:65be27845400 12917 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 12918
AnnaBridge 172:65be27845400 12919 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
AnnaBridge 172:65be27845400 12920 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12921 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
AnnaBridge 172:65be27845400 12922 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
AnnaBridge 172:65be27845400 12923 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12924 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
AnnaBridge 172:65be27845400 12925
AnnaBridge 172:65be27845400 12926 /******************* Bit definition for SDIO_ARG register *******************/
AnnaBridge 172:65be27845400 12927 #define SDIO_ARG_CMDARG_Pos (0U)
AnnaBridge 172:65be27845400 12928 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12929 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
AnnaBridge 172:65be27845400 12930
AnnaBridge 172:65be27845400 12931 /******************* Bit definition for SDIO_CMD register *******************/
AnnaBridge 172:65be27845400 12932 #define SDIO_CMD_CMDINDEX_Pos (0U)
AnnaBridge 172:65be27845400 12933 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 12934 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 172:65be27845400 12935
AnnaBridge 172:65be27845400 12936 #define SDIO_CMD_WAITRESP_Pos (6U)
AnnaBridge 172:65be27845400 12937 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 12938 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 172:65be27845400 12939 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 12940 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 12941
AnnaBridge 172:65be27845400 12942 #define SDIO_CMD_WAITINT_Pos (8U)
AnnaBridge 172:65be27845400 12943 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12944 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 172:65be27845400 12945 #define SDIO_CMD_WAITPEND_Pos (9U)
AnnaBridge 172:65be27845400 12946 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12947 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 172:65be27845400 12948 #define SDIO_CMD_CPSMEN_Pos (10U)
AnnaBridge 172:65be27845400 12949 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12950 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 172:65be27845400 12951 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
AnnaBridge 172:65be27845400 12952 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12953 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
AnnaBridge 172:65be27845400 12954 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
AnnaBridge 172:65be27845400 12955 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12956 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
AnnaBridge 172:65be27845400 12957 #define SDIO_CMD_NIEN_Pos (13U)
AnnaBridge 172:65be27845400 12958 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12959 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
AnnaBridge 172:65be27845400 12960 #define SDIO_CMD_CEATACMD_Pos (14U)
AnnaBridge 172:65be27845400 12961 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12962 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
AnnaBridge 172:65be27845400 12963
AnnaBridge 172:65be27845400 12964 /***************** Bit definition for SDIO_RESPCMD register *****************/
AnnaBridge 172:65be27845400 12965 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 172:65be27845400 12966 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 12967 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
AnnaBridge 172:65be27845400 12968
AnnaBridge 172:65be27845400 12969 /****************** Bit definition for SDIO_RESP0 register ******************/
AnnaBridge 172:65be27845400 12970 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 172:65be27845400 12971 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12972 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 12973
AnnaBridge 172:65be27845400 12974 /****************** Bit definition for SDIO_RESP1 register ******************/
AnnaBridge 172:65be27845400 12975 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 172:65be27845400 12976 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12977 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 12978
AnnaBridge 172:65be27845400 12979 /****************** Bit definition for SDIO_RESP2 register ******************/
AnnaBridge 172:65be27845400 12980 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 172:65be27845400 12981 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12982 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 12983
AnnaBridge 172:65be27845400 12984 /****************** Bit definition for SDIO_RESP3 register ******************/
AnnaBridge 172:65be27845400 12985 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 172:65be27845400 12986 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12987 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 12988
AnnaBridge 172:65be27845400 12989 /****************** Bit definition for SDIO_RESP4 register ******************/
AnnaBridge 172:65be27845400 12990 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 172:65be27845400 12991 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12992 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 12993
AnnaBridge 172:65be27845400 12994 /****************** Bit definition for SDIO_DTIMER register *****************/
AnnaBridge 172:65be27845400 12995 #define SDIO_DTIMER_DATATIME_Pos (0U)
AnnaBridge 172:65be27845400 12996 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 12997 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
AnnaBridge 172:65be27845400 12998
AnnaBridge 172:65be27845400 12999 /****************** Bit definition for SDIO_DLEN register *******************/
AnnaBridge 172:65be27845400 13000 #define SDIO_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 172:65be27845400 13001 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 172:65be27845400 13002 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
AnnaBridge 172:65be27845400 13003
AnnaBridge 172:65be27845400 13004 /****************** Bit definition for SDIO_DCTRL register ******************/
AnnaBridge 172:65be27845400 13005 #define SDIO_DCTRL_DTEN_Pos (0U)
AnnaBridge 172:65be27845400 13006 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13007 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 172:65be27845400 13008 #define SDIO_DCTRL_DTDIR_Pos (1U)
AnnaBridge 172:65be27845400 13009 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13010 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 172:65be27845400 13011 #define SDIO_DCTRL_DTMODE_Pos (2U)
AnnaBridge 172:65be27845400 13012 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13013 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
AnnaBridge 172:65be27845400 13014 #define SDIO_DCTRL_DMAEN_Pos (3U)
AnnaBridge 172:65be27845400 13015 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13016 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
AnnaBridge 172:65be27845400 13017
AnnaBridge 172:65be27845400 13018 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 172:65be27845400 13019 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 13020 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 172:65be27845400 13021 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 13022 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 13023 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 13024 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 13025
AnnaBridge 172:65be27845400 13026 #define SDIO_DCTRL_RWSTART_Pos (8U)
AnnaBridge 172:65be27845400 13027 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13028 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 172:65be27845400 13029 #define SDIO_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 172:65be27845400 13030 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13031 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 172:65be27845400 13032 #define SDIO_DCTRL_RWMOD_Pos (10U)
AnnaBridge 172:65be27845400 13033 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13034 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 172:65be27845400 13035 #define SDIO_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 172:65be27845400 13036 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13037 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
AnnaBridge 172:65be27845400 13038
AnnaBridge 172:65be27845400 13039 /****************** Bit definition for SDIO_DCOUNT register *****************/
AnnaBridge 172:65be27845400 13040 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 172:65be27845400 13041 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 172:65be27845400 13042 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
AnnaBridge 172:65be27845400 13043
AnnaBridge 172:65be27845400 13044 /****************** Bit definition for SDIO_STA register ********************/
AnnaBridge 172:65be27845400 13045 #define SDIO_STA_CCRCFAIL_Pos (0U)
AnnaBridge 172:65be27845400 13046 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13047 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 172:65be27845400 13048 #define SDIO_STA_DCRCFAIL_Pos (1U)
AnnaBridge 172:65be27845400 13049 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13050 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 172:65be27845400 13051 #define SDIO_STA_CTIMEOUT_Pos (2U)
AnnaBridge 172:65be27845400 13052 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13053 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 172:65be27845400 13054 #define SDIO_STA_DTIMEOUT_Pos (3U)
AnnaBridge 172:65be27845400 13055 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13056 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 172:65be27845400 13057 #define SDIO_STA_TXUNDERR_Pos (4U)
AnnaBridge 172:65be27845400 13058 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13059 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 172:65be27845400 13060 #define SDIO_STA_RXOVERR_Pos (5U)
AnnaBridge 172:65be27845400 13061 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13062 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 172:65be27845400 13063 #define SDIO_STA_CMDREND_Pos (6U)
AnnaBridge 172:65be27845400 13064 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13065 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 172:65be27845400 13066 #define SDIO_STA_CMDSENT_Pos (7U)
AnnaBridge 172:65be27845400 13067 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13068 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 172:65be27845400 13069 #define SDIO_STA_DATAEND_Pos (8U)
AnnaBridge 172:65be27845400 13070 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13071 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 172:65be27845400 13072 #define SDIO_STA_STBITERR_Pos (9U)
AnnaBridge 172:65be27845400 13073 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13074 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
AnnaBridge 172:65be27845400 13075 #define SDIO_STA_DBCKEND_Pos (10U)
AnnaBridge 172:65be27845400 13076 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13077 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 172:65be27845400 13078 #define SDIO_STA_CMDACT_Pos (11U)
AnnaBridge 172:65be27845400 13079 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13080 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
AnnaBridge 172:65be27845400 13081 #define SDIO_STA_TXACT_Pos (12U)
AnnaBridge 172:65be27845400 13082 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13083 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
AnnaBridge 172:65be27845400 13084 #define SDIO_STA_RXACT_Pos (13U)
AnnaBridge 172:65be27845400 13085 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13086 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
AnnaBridge 172:65be27845400 13087 #define SDIO_STA_TXFIFOHE_Pos (14U)
AnnaBridge 172:65be27845400 13088 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13089 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 172:65be27845400 13090 #define SDIO_STA_RXFIFOHF_Pos (15U)
AnnaBridge 172:65be27845400 13091 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13092 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 172:65be27845400 13093 #define SDIO_STA_TXFIFOF_Pos (16U)
AnnaBridge 172:65be27845400 13094 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13095 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 172:65be27845400 13096 #define SDIO_STA_RXFIFOF_Pos (17U)
AnnaBridge 172:65be27845400 13097 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13098 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 172:65be27845400 13099 #define SDIO_STA_TXFIFOE_Pos (18U)
AnnaBridge 172:65be27845400 13100 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13101 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 172:65be27845400 13102 #define SDIO_STA_RXFIFOE_Pos (19U)
AnnaBridge 172:65be27845400 13103 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 13104 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 172:65be27845400 13105 #define SDIO_STA_TXDAVL_Pos (20U)
AnnaBridge 172:65be27845400 13106 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 13107 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
AnnaBridge 172:65be27845400 13108 #define SDIO_STA_RXDAVL_Pos (21U)
AnnaBridge 172:65be27845400 13109 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 13110 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
AnnaBridge 172:65be27845400 13111 #define SDIO_STA_SDIOIT_Pos (22U)
AnnaBridge 172:65be27845400 13112 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 13113 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
AnnaBridge 172:65be27845400 13114 #define SDIO_STA_CEATAEND_Pos (23U)
AnnaBridge 172:65be27845400 13115 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 13116 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
AnnaBridge 172:65be27845400 13117
AnnaBridge 172:65be27845400 13118 /******************* Bit definition for SDIO_ICR register *******************/
AnnaBridge 172:65be27845400 13119 #define SDIO_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 172:65be27845400 13120 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13121 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 172:65be27845400 13122 #define SDIO_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 172:65be27845400 13123 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13124 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 172:65be27845400 13125 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 172:65be27845400 13126 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13127 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 172:65be27845400 13128 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 172:65be27845400 13129 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13130 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 172:65be27845400 13131 #define SDIO_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 172:65be27845400 13132 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13133 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 172:65be27845400 13134 #define SDIO_ICR_RXOVERRC_Pos (5U)
AnnaBridge 172:65be27845400 13135 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13136 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 172:65be27845400 13137 #define SDIO_ICR_CMDRENDC_Pos (6U)
AnnaBridge 172:65be27845400 13138 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13139 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 172:65be27845400 13140 #define SDIO_ICR_CMDSENTC_Pos (7U)
AnnaBridge 172:65be27845400 13141 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13142 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 172:65be27845400 13143 #define SDIO_ICR_DATAENDC_Pos (8U)
AnnaBridge 172:65be27845400 13144 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13145 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 172:65be27845400 13146 #define SDIO_ICR_STBITERRC_Pos (9U)
AnnaBridge 172:65be27845400 13147 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13148 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
AnnaBridge 172:65be27845400 13149 #define SDIO_ICR_DBCKENDC_Pos (10U)
AnnaBridge 172:65be27845400 13150 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13151 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 172:65be27845400 13152 #define SDIO_ICR_SDIOITC_Pos (22U)
AnnaBridge 172:65be27845400 13153 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 13154 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
AnnaBridge 172:65be27845400 13155 #define SDIO_ICR_CEATAENDC_Pos (23U)
AnnaBridge 172:65be27845400 13156 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 13157 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
AnnaBridge 172:65be27845400 13158
AnnaBridge 172:65be27845400 13159 /****************** Bit definition for SDIO_MASK register *******************/
AnnaBridge 172:65be27845400 13160 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 172:65be27845400 13161 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13162 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 172:65be27845400 13163 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 172:65be27845400 13164 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13165 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 172:65be27845400 13166 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 172:65be27845400 13167 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13168 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 172:65be27845400 13169 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 172:65be27845400 13170 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13171 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 172:65be27845400 13172 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 172:65be27845400 13173 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13174 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 172:65be27845400 13175 #define SDIO_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 172:65be27845400 13176 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13177 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 172:65be27845400 13178 #define SDIO_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 172:65be27845400 13179 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13180 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 172:65be27845400 13181 #define SDIO_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 172:65be27845400 13182 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13183 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 172:65be27845400 13184 #define SDIO_MASK_DATAENDIE_Pos (8U)
AnnaBridge 172:65be27845400 13185 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13186 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 172:65be27845400 13187 #define SDIO_MASK_STBITERRIE_Pos (9U)
AnnaBridge 172:65be27845400 13188 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13189 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
AnnaBridge 172:65be27845400 13190 #define SDIO_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 172:65be27845400 13191 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13192 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 172:65be27845400 13193 #define SDIO_MASK_CMDACTIE_Pos (11U)
AnnaBridge 172:65be27845400 13194 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13195 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
AnnaBridge 172:65be27845400 13196 #define SDIO_MASK_TXACTIE_Pos (12U)
AnnaBridge 172:65be27845400 13197 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13198 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 172:65be27845400 13199 #define SDIO_MASK_RXACTIE_Pos (13U)
AnnaBridge 172:65be27845400 13200 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13201 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
AnnaBridge 172:65be27845400 13202 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 172:65be27845400 13203 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13204 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 172:65be27845400 13205 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 172:65be27845400 13206 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13207 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 172:65be27845400 13208 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
AnnaBridge 172:65be27845400 13209 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13210 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 172:65be27845400 13211 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 172:65be27845400 13212 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13213 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 172:65be27845400 13214 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 172:65be27845400 13215 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13216 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 172:65be27845400 13217 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
AnnaBridge 172:65be27845400 13218 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 13219 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 172:65be27845400 13220 #define SDIO_MASK_TXDAVLIE_Pos (20U)
AnnaBridge 172:65be27845400 13221 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 13222 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 172:65be27845400 13223 #define SDIO_MASK_RXDAVLIE_Pos (21U)
AnnaBridge 172:65be27845400 13224 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 13225 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 172:65be27845400 13226 #define SDIO_MASK_SDIOITIE_Pos (22U)
AnnaBridge 172:65be27845400 13227 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 13228 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
AnnaBridge 172:65be27845400 13229 #define SDIO_MASK_CEATAENDIE_Pos (23U)
AnnaBridge 172:65be27845400 13230 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 13231 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
AnnaBridge 172:65be27845400 13232
AnnaBridge 172:65be27845400 13233 /***************** Bit definition for SDIO_FIFOCNT register *****************/
AnnaBridge 172:65be27845400 13234 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
AnnaBridge 172:65be27845400 13235 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
AnnaBridge 172:65be27845400 13236 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
AnnaBridge 172:65be27845400 13237
AnnaBridge 172:65be27845400 13238 /****************** Bit definition for SDIO_FIFO register *******************/
AnnaBridge 172:65be27845400 13239 #define SDIO_FIFO_FIFODATA_Pos (0U)
AnnaBridge 172:65be27845400 13240 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13241 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
AnnaBridge 172:65be27845400 13242
AnnaBridge 172:65be27845400 13243 /******************************************************************************/
AnnaBridge 172:65be27845400 13244 /* */
AnnaBridge 172:65be27845400 13245 /* Serial Peripheral Interface */
AnnaBridge 172:65be27845400 13246 /* */
AnnaBridge 172:65be27845400 13247 /******************************************************************************/
AnnaBridge 172:65be27845400 13248 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
AnnaBridge 172:65be27845400 13249
AnnaBridge 172:65be27845400 13250 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 172:65be27845400 13251 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 172:65be27845400 13252 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13253 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 172:65be27845400 13254 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 172:65be27845400 13255 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13256 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 172:65be27845400 13257 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 172:65be27845400 13258 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13259 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 172:65be27845400 13260
AnnaBridge 172:65be27845400 13261 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 172:65be27845400 13262 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 13263 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 172:65be27845400 13264 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13265 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13266 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13267
AnnaBridge 172:65be27845400 13268 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 172:65be27845400 13269 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13270 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 172:65be27845400 13271 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 172:65be27845400 13272 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13273 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 172:65be27845400 13274 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 172:65be27845400 13275 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13276 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 172:65be27845400 13277 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 172:65be27845400 13278 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13279 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 172:65be27845400 13280 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 172:65be27845400 13281 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13282 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 172:65be27845400 13283 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 172:65be27845400 13284 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13285 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
AnnaBridge 172:65be27845400 13286 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 172:65be27845400 13287 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13288 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 172:65be27845400 13289 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 172:65be27845400 13290 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13291 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 172:65be27845400 13292 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 172:65be27845400 13293 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13294 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 172:65be27845400 13295 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 172:65be27845400 13296 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13297 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
AnnaBridge 172:65be27845400 13298
AnnaBridge 172:65be27845400 13299 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 172:65be27845400 13300 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 172:65be27845400 13301 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13302 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
AnnaBridge 172:65be27845400 13303 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 172:65be27845400 13304 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13305 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
AnnaBridge 172:65be27845400 13306 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 172:65be27845400 13307 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13308 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
AnnaBridge 172:65be27845400 13309 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 172:65be27845400 13310 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13311 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
AnnaBridge 172:65be27845400 13312 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 172:65be27845400 13313 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13314 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 172:65be27845400 13315 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 172:65be27845400 13316 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13317 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
AnnaBridge 172:65be27845400 13318 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 172:65be27845400 13319 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13320 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
AnnaBridge 172:65be27845400 13321
AnnaBridge 172:65be27845400 13322 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 172:65be27845400 13323 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 172:65be27845400 13324 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13325 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
AnnaBridge 172:65be27845400 13326 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 172:65be27845400 13327 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13328 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
AnnaBridge 172:65be27845400 13329 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 172:65be27845400 13330 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13331 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
AnnaBridge 172:65be27845400 13332 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 172:65be27845400 13333 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13334 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
AnnaBridge 172:65be27845400 13335 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 172:65be27845400 13336 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13337 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
AnnaBridge 172:65be27845400 13338 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 172:65be27845400 13339 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13340 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
AnnaBridge 172:65be27845400 13341 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 172:65be27845400 13342 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13343 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 172:65be27845400 13344 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 172:65be27845400 13345 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13346 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
AnnaBridge 172:65be27845400 13347 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 172:65be27845400 13348 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13349 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
AnnaBridge 172:65be27845400 13350
AnnaBridge 172:65be27845400 13351 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 172:65be27845400 13352 #define SPI_DR_DR_Pos (0U)
AnnaBridge 172:65be27845400 13353 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 13354 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
AnnaBridge 172:65be27845400 13355
AnnaBridge 172:65be27845400 13356 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 172:65be27845400 13357 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 172:65be27845400 13358 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 13359 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
AnnaBridge 172:65be27845400 13360
AnnaBridge 172:65be27845400 13361 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 172:65be27845400 13362 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 172:65be27845400 13363 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 13364 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
AnnaBridge 172:65be27845400 13365
AnnaBridge 172:65be27845400 13366 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 172:65be27845400 13367 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 172:65be27845400 13368 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 13369 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
AnnaBridge 172:65be27845400 13370
AnnaBridge 172:65be27845400 13371 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 172:65be27845400 13372 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 172:65be27845400 13373 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13374 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 172:65be27845400 13375
AnnaBridge 172:65be27845400 13376 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 172:65be27845400 13377 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 13378 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 172:65be27845400 13379 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13380 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13381
AnnaBridge 172:65be27845400 13382 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 172:65be27845400 13383 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13384 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 172:65be27845400 13385
AnnaBridge 172:65be27845400 13386 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 172:65be27845400 13387 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 13388 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 172:65be27845400 13389 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13390 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13391
AnnaBridge 172:65be27845400 13392 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 172:65be27845400 13393 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13394 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 172:65be27845400 13395
AnnaBridge 172:65be27845400 13396 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 172:65be27845400 13397 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 13398 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 172:65be27845400 13399 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13400 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13401
AnnaBridge 172:65be27845400 13402 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 172:65be27845400 13403 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13404 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 172:65be27845400 13405 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 172:65be27845400 13406 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13407 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 172:65be27845400 13408
AnnaBridge 172:65be27845400 13409 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 172:65be27845400 13410 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 172:65be27845400 13411 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 13412 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 172:65be27845400 13413 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 172:65be27845400 13414 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13415 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 172:65be27845400 13416 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 172:65be27845400 13417 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13418 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 172:65be27845400 13419
AnnaBridge 172:65be27845400 13420 /******************************************************************************/
AnnaBridge 172:65be27845400 13421 /* */
AnnaBridge 172:65be27845400 13422 /* SYSCFG */
AnnaBridge 172:65be27845400 13423 /* */
AnnaBridge 172:65be27845400 13424 /******************************************************************************/
AnnaBridge 172:65be27845400 13425 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 172:65be27845400 13426 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 172:65be27845400 13427 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 13428 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 172:65be27845400 13429 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13430 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13431 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13432 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
AnnaBridge 172:65be27845400 13433 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13434 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
AnnaBridge 172:65be27845400 13435 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
AnnaBridge 172:65be27845400 13436 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 13437 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
AnnaBridge 172:65be27845400 13438 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13439 /* Legacy Defines */
AnnaBridge 172:65be27845400 13440 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
AnnaBridge 172:65be27845400 13441 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 172:65be27845400 13442 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
AnnaBridge 172:65be27845400 13443 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 13444 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 172:65be27845400 13445 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
AnnaBridge 172:65be27845400 13446 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13447 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 172:65be27845400 13448 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
AnnaBridge 172:65be27845400 13449 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13450 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 172:65be27845400 13451 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
AnnaBridge 172:65be27845400 13452 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13453 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 172:65be27845400 13454 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
AnnaBridge 172:65be27845400 13455 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 13456 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
AnnaBridge 172:65be27845400 13457 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
AnnaBridge 172:65be27845400 13458 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
AnnaBridge 172:65be27845400 13459
AnnaBridge 172:65be27845400 13460 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 172:65be27845400 13461 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 172:65be27845400 13462 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 13463 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 172:65be27845400 13464 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 172:65be27845400 13465 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 13466 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 172:65be27845400 13467 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 172:65be27845400 13468 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 13469 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 172:65be27845400 13470 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 172:65be27845400 13471 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 13472 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 172:65be27845400 13473 /**
AnnaBridge 172:65be27845400 13474 * @brief EXTI0 configuration
AnnaBridge 172:65be27845400 13475 */
AnnaBridge 172:65be27845400 13476 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 172:65be27845400 13477 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 172:65be27845400 13478 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 172:65be27845400 13479 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 172:65be27845400 13480 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 172:65be27845400 13481 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
AnnaBridge 172:65be27845400 13482 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
AnnaBridge 172:65be27845400 13483 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 172:65be27845400 13484 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
AnnaBridge 172:65be27845400 13485 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
AnnaBridge 172:65be27845400 13486 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
AnnaBridge 172:65be27845400 13487
AnnaBridge 172:65be27845400 13488 /**
AnnaBridge 172:65be27845400 13489 * @brief EXTI1 configuration
AnnaBridge 172:65be27845400 13490 */
AnnaBridge 172:65be27845400 13491 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 172:65be27845400 13492 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 172:65be27845400 13493 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 172:65be27845400 13494 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 172:65be27845400 13495 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 172:65be27845400 13496 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
AnnaBridge 172:65be27845400 13497 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
AnnaBridge 172:65be27845400 13498 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 172:65be27845400 13499 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
AnnaBridge 172:65be27845400 13500 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
AnnaBridge 172:65be27845400 13501 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
AnnaBridge 172:65be27845400 13502
AnnaBridge 172:65be27845400 13503 /**
AnnaBridge 172:65be27845400 13504 * @brief EXTI2 configuration
AnnaBridge 172:65be27845400 13505 */
AnnaBridge 172:65be27845400 13506 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 172:65be27845400 13507 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 172:65be27845400 13508 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 172:65be27845400 13509 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 172:65be27845400 13510 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 172:65be27845400 13511 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
AnnaBridge 172:65be27845400 13512 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
AnnaBridge 172:65be27845400 13513 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 172:65be27845400 13514 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
AnnaBridge 172:65be27845400 13515 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
AnnaBridge 172:65be27845400 13516 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
AnnaBridge 172:65be27845400 13517
AnnaBridge 172:65be27845400 13518 /**
AnnaBridge 172:65be27845400 13519 * @brief EXTI3 configuration
AnnaBridge 172:65be27845400 13520 */
AnnaBridge 172:65be27845400 13521 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 172:65be27845400 13522 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 172:65be27845400 13523 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 172:65be27845400 13524 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 172:65be27845400 13525 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 172:65be27845400 13526 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
AnnaBridge 172:65be27845400 13527 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
AnnaBridge 172:65be27845400 13528 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 172:65be27845400 13529 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
AnnaBridge 172:65be27845400 13530 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
AnnaBridge 172:65be27845400 13531 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
AnnaBridge 172:65be27845400 13532
AnnaBridge 172:65be27845400 13533 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 172:65be27845400 13534 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 172:65be27845400 13535 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 13536 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 172:65be27845400 13537 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 172:65be27845400 13538 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 13539 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 172:65be27845400 13540 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 172:65be27845400 13541 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 13542 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 172:65be27845400 13543 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 172:65be27845400 13544 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 13545 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 172:65be27845400 13546
AnnaBridge 172:65be27845400 13547 /**
AnnaBridge 172:65be27845400 13548 * @brief EXTI4 configuration
AnnaBridge 172:65be27845400 13549 */
AnnaBridge 172:65be27845400 13550 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 172:65be27845400 13551 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 172:65be27845400 13552 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 172:65be27845400 13553 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 172:65be27845400 13554 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 172:65be27845400 13555 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
AnnaBridge 172:65be27845400 13556 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
AnnaBridge 172:65be27845400 13557 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 172:65be27845400 13558 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
AnnaBridge 172:65be27845400 13559 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
AnnaBridge 172:65be27845400 13560 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
AnnaBridge 172:65be27845400 13561
AnnaBridge 172:65be27845400 13562 /**
AnnaBridge 172:65be27845400 13563 * @brief EXTI5 configuration
AnnaBridge 172:65be27845400 13564 */
AnnaBridge 172:65be27845400 13565 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 172:65be27845400 13566 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 172:65be27845400 13567 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 172:65be27845400 13568 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 172:65be27845400 13569 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 172:65be27845400 13570 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
AnnaBridge 172:65be27845400 13571 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
AnnaBridge 172:65be27845400 13572 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 172:65be27845400 13573 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
AnnaBridge 172:65be27845400 13574 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
AnnaBridge 172:65be27845400 13575 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
AnnaBridge 172:65be27845400 13576
AnnaBridge 172:65be27845400 13577 /**
AnnaBridge 172:65be27845400 13578 * @brief EXTI6 configuration
AnnaBridge 172:65be27845400 13579 */
AnnaBridge 172:65be27845400 13580 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 172:65be27845400 13581 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 172:65be27845400 13582 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 172:65be27845400 13583 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 172:65be27845400 13584 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 172:65be27845400 13585 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
AnnaBridge 172:65be27845400 13586 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
AnnaBridge 172:65be27845400 13587 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 172:65be27845400 13588 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
AnnaBridge 172:65be27845400 13589 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
AnnaBridge 172:65be27845400 13590 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
AnnaBridge 172:65be27845400 13591
AnnaBridge 172:65be27845400 13592 /**
AnnaBridge 172:65be27845400 13593 * @brief EXTI7 configuration
AnnaBridge 172:65be27845400 13594 */
AnnaBridge 172:65be27845400 13595 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 172:65be27845400 13596 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 172:65be27845400 13597 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 172:65be27845400 13598 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 172:65be27845400 13599 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 172:65be27845400 13600 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
AnnaBridge 172:65be27845400 13601 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
AnnaBridge 172:65be27845400 13602 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 172:65be27845400 13603 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
AnnaBridge 172:65be27845400 13604 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
AnnaBridge 172:65be27845400 13605 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
AnnaBridge 172:65be27845400 13606
AnnaBridge 172:65be27845400 13607 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 172:65be27845400 13608 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 172:65be27845400 13609 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 13610 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 172:65be27845400 13611 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 172:65be27845400 13612 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 13613 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 172:65be27845400 13614 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 172:65be27845400 13615 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 13616 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 172:65be27845400 13617 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 172:65be27845400 13618 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 13619 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 172:65be27845400 13620
AnnaBridge 172:65be27845400 13621 /**
AnnaBridge 172:65be27845400 13622 * @brief EXTI8 configuration
AnnaBridge 172:65be27845400 13623 */
AnnaBridge 172:65be27845400 13624 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 172:65be27845400 13625 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 172:65be27845400 13626 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 172:65be27845400 13627 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 172:65be27845400 13628 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 172:65be27845400 13629 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
AnnaBridge 172:65be27845400 13630 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
AnnaBridge 172:65be27845400 13631 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 172:65be27845400 13632 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
AnnaBridge 172:65be27845400 13633 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
AnnaBridge 172:65be27845400 13634
AnnaBridge 172:65be27845400 13635 /**
AnnaBridge 172:65be27845400 13636 * @brief EXTI9 configuration
AnnaBridge 172:65be27845400 13637 */
AnnaBridge 172:65be27845400 13638 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 172:65be27845400 13639 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 172:65be27845400 13640 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 172:65be27845400 13641 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 172:65be27845400 13642 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 172:65be27845400 13643 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
AnnaBridge 172:65be27845400 13644 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
AnnaBridge 172:65be27845400 13645 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 172:65be27845400 13646 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
AnnaBridge 172:65be27845400 13647 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
AnnaBridge 172:65be27845400 13648
AnnaBridge 172:65be27845400 13649 /**
AnnaBridge 172:65be27845400 13650 * @brief EXTI10 configuration
AnnaBridge 172:65be27845400 13651 */
AnnaBridge 172:65be27845400 13652 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 172:65be27845400 13653 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 172:65be27845400 13654 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 172:65be27845400 13655 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 172:65be27845400 13656 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 172:65be27845400 13657 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
AnnaBridge 172:65be27845400 13658 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
AnnaBridge 172:65be27845400 13659 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 172:65be27845400 13660 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
AnnaBridge 172:65be27845400 13661 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
AnnaBridge 172:65be27845400 13662
AnnaBridge 172:65be27845400 13663 /**
AnnaBridge 172:65be27845400 13664 * @brief EXTI11 configuration
AnnaBridge 172:65be27845400 13665 */
AnnaBridge 172:65be27845400 13666 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 172:65be27845400 13667 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 172:65be27845400 13668 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 172:65be27845400 13669 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 172:65be27845400 13670 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 172:65be27845400 13671 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
AnnaBridge 172:65be27845400 13672 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
AnnaBridge 172:65be27845400 13673 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 172:65be27845400 13674 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
AnnaBridge 172:65be27845400 13675 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
AnnaBridge 172:65be27845400 13676
AnnaBridge 172:65be27845400 13677
AnnaBridge 172:65be27845400 13678 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 172:65be27845400 13679 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 172:65be27845400 13680 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 13681 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 172:65be27845400 13682 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 172:65be27845400 13683 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 13684 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 172:65be27845400 13685 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 172:65be27845400 13686 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 13687 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 172:65be27845400 13688 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 172:65be27845400 13689 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 13690 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 172:65be27845400 13691
AnnaBridge 172:65be27845400 13692 /**
AnnaBridge 172:65be27845400 13693 * @brief EXTI12 configuration
AnnaBridge 172:65be27845400 13694 */
AnnaBridge 172:65be27845400 13695 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 172:65be27845400 13696 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 172:65be27845400 13697 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 172:65be27845400 13698 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 172:65be27845400 13699 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 172:65be27845400 13700 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
AnnaBridge 172:65be27845400 13701 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
AnnaBridge 172:65be27845400 13702 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 172:65be27845400 13703 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
AnnaBridge 172:65be27845400 13704 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
AnnaBridge 172:65be27845400 13705
AnnaBridge 172:65be27845400 13706 /**
AnnaBridge 172:65be27845400 13707 * @brief EXTI13 configuration
AnnaBridge 172:65be27845400 13708 */
AnnaBridge 172:65be27845400 13709 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 172:65be27845400 13710 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 172:65be27845400 13711 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 172:65be27845400 13712 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 172:65be27845400 13713 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 172:65be27845400 13714 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
AnnaBridge 172:65be27845400 13715 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
AnnaBridge 172:65be27845400 13716 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 172:65be27845400 13717 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
AnnaBridge 172:65be27845400 13718 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
AnnaBridge 172:65be27845400 13719
AnnaBridge 172:65be27845400 13720 /**
AnnaBridge 172:65be27845400 13721 * @brief EXTI14 configuration
AnnaBridge 172:65be27845400 13722 */
AnnaBridge 172:65be27845400 13723 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 172:65be27845400 13724 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 172:65be27845400 13725 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 172:65be27845400 13726 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 172:65be27845400 13727 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 172:65be27845400 13728 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
AnnaBridge 172:65be27845400 13729 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
AnnaBridge 172:65be27845400 13730 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 172:65be27845400 13731 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
AnnaBridge 172:65be27845400 13732 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
AnnaBridge 172:65be27845400 13733
AnnaBridge 172:65be27845400 13734 /**
AnnaBridge 172:65be27845400 13735 * @brief EXTI15 configuration
AnnaBridge 172:65be27845400 13736 */
AnnaBridge 172:65be27845400 13737 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 172:65be27845400 13738 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 172:65be27845400 13739 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 172:65be27845400 13740 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 172:65be27845400 13741 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 172:65be27845400 13742 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
AnnaBridge 172:65be27845400 13743 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
AnnaBridge 172:65be27845400 13744 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 172:65be27845400 13745 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
AnnaBridge 172:65be27845400 13746 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
AnnaBridge 172:65be27845400 13747
AnnaBridge 172:65be27845400 13748 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 172:65be27845400 13749 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 172:65be27845400 13750 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13751 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
AnnaBridge 172:65be27845400 13752 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 172:65be27845400 13753 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13754 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
AnnaBridge 172:65be27845400 13755
AnnaBridge 172:65be27845400 13756 /******************************************************************************/
AnnaBridge 172:65be27845400 13757 /* */
AnnaBridge 172:65be27845400 13758 /* TIM */
AnnaBridge 172:65be27845400 13759 /* */
AnnaBridge 172:65be27845400 13760 /******************************************************************************/
AnnaBridge 172:65be27845400 13761 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 172:65be27845400 13762 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 172:65be27845400 13763 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13764 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 172:65be27845400 13765 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 172:65be27845400 13766 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13767 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 172:65be27845400 13768 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 172:65be27845400 13769 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13770 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 172:65be27845400 13771 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 172:65be27845400 13772 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13773 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 172:65be27845400 13774 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 172:65be27845400 13775 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13776 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 172:65be27845400 13777
AnnaBridge 172:65be27845400 13778 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 172:65be27845400 13779 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 13780 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 172:65be27845400 13781 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 13782 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 13783
AnnaBridge 172:65be27845400 13784 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 172:65be27845400 13785 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13786 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 172:65be27845400 13787
AnnaBridge 172:65be27845400 13788 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 172:65be27845400 13789 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 13790 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 172:65be27845400 13791 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 172:65be27845400 13792 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
AnnaBridge 172:65be27845400 13793
AnnaBridge 172:65be27845400 13794 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 172:65be27845400 13795 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 172:65be27845400 13796 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13797 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 172:65be27845400 13798 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 172:65be27845400 13799 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13800 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 172:65be27845400 13801 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 172:65be27845400 13802 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13803 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 172:65be27845400 13804
AnnaBridge 172:65be27845400 13805 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 172:65be27845400 13806 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 13807 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 172:65be27845400 13808 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 13809 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 13810 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 13811
AnnaBridge 172:65be27845400 13812 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 172:65be27845400 13813 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13814 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 172:65be27845400 13815 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 172:65be27845400 13816 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13817 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 172:65be27845400 13818 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 172:65be27845400 13819 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13820 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 172:65be27845400 13821 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 172:65be27845400 13822 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13823 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 172:65be27845400 13824 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 172:65be27845400 13825 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13826 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 172:65be27845400 13827 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 172:65be27845400 13828 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13829 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 172:65be27845400 13830 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 172:65be27845400 13831 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13832 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 172:65be27845400 13833 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 172:65be27845400 13834 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13835 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 172:65be27845400 13836
AnnaBridge 172:65be27845400 13837 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 172:65be27845400 13838 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 172:65be27845400 13839 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 13840 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 172:65be27845400 13841 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
AnnaBridge 172:65be27845400 13842 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
AnnaBridge 172:65be27845400 13843 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
AnnaBridge 172:65be27845400 13844
AnnaBridge 172:65be27845400 13845 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 172:65be27845400 13846 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 13847 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 172:65be27845400 13848 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 13849 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 13850 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 13851
AnnaBridge 172:65be27845400 13852 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 172:65be27845400 13853 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13854 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 172:65be27845400 13855
AnnaBridge 172:65be27845400 13856 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 172:65be27845400 13857 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 13858 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 172:65be27845400 13859 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 172:65be27845400 13860 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 172:65be27845400 13861 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 172:65be27845400 13862 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 172:65be27845400 13863
AnnaBridge 172:65be27845400 13864 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 172:65be27845400 13865 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 13866 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 172:65be27845400 13867 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 13868 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 172:65be27845400 13869
AnnaBridge 172:65be27845400 13870 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 172:65be27845400 13871 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13872 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 172:65be27845400 13873 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 172:65be27845400 13874 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13875 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 172:65be27845400 13876
AnnaBridge 172:65be27845400 13877 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 172:65be27845400 13878 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 172:65be27845400 13879 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13880 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 172:65be27845400 13881 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 172:65be27845400 13882 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13883 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 172:65be27845400 13884 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 172:65be27845400 13885 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13886 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 172:65be27845400 13887 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 172:65be27845400 13888 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13889 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 172:65be27845400 13890 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 172:65be27845400 13891 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13892 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 172:65be27845400 13893 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 172:65be27845400 13894 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13895 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 172:65be27845400 13896 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 172:65be27845400 13897 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13898 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 172:65be27845400 13899 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 172:65be27845400 13900 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13901 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 172:65be27845400 13902 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 172:65be27845400 13903 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13904 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 172:65be27845400 13905 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 172:65be27845400 13906 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13907 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 172:65be27845400 13908 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 172:65be27845400 13909 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13910 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 172:65be27845400 13911 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 172:65be27845400 13912 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13913 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 172:65be27845400 13914 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 172:65be27845400 13915 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13916 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 172:65be27845400 13917 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 172:65be27845400 13918 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13919 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 172:65be27845400 13920 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 172:65be27845400 13921 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13922 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 172:65be27845400 13923
AnnaBridge 172:65be27845400 13924 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 172:65be27845400 13925 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 172:65be27845400 13926 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13927 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 172:65be27845400 13928 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 172:65be27845400 13929 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13930 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 172:65be27845400 13931 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 172:65be27845400 13932 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13933 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 172:65be27845400 13934 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 172:65be27845400 13935 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13936 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 172:65be27845400 13937 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 172:65be27845400 13938 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13939 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 172:65be27845400 13940 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 172:65be27845400 13941 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13942 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 172:65be27845400 13943 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 172:65be27845400 13944 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13945 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 172:65be27845400 13946 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 172:65be27845400 13947 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13948 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 172:65be27845400 13949 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 172:65be27845400 13950 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13951 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 172:65be27845400 13952 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 172:65be27845400 13953 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13954 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 172:65be27845400 13955 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 172:65be27845400 13956 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13957 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 172:65be27845400 13958 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 172:65be27845400 13959 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13960 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 172:65be27845400 13961
AnnaBridge 172:65be27845400 13962 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 172:65be27845400 13963 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 172:65be27845400 13964 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13965 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 172:65be27845400 13966 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 172:65be27845400 13967 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13968 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 172:65be27845400 13969 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 172:65be27845400 13970 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13971 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 172:65be27845400 13972 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 172:65be27845400 13973 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13974 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 172:65be27845400 13975 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 172:65be27845400 13976 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13977 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 172:65be27845400 13978 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 172:65be27845400 13979 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13980 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 172:65be27845400 13981 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 172:65be27845400 13982 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13983 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 172:65be27845400 13984 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 172:65be27845400 13985 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13986 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 172:65be27845400 13987
AnnaBridge 172:65be27845400 13988 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 172:65be27845400 13989 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 172:65be27845400 13990 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 13991 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 172:65be27845400 13992 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
AnnaBridge 172:65be27845400 13993 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
AnnaBridge 172:65be27845400 13994
AnnaBridge 172:65be27845400 13995 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 172:65be27845400 13996 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13997 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 172:65be27845400 13998 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 172:65be27845400 13999 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14000 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 172:65be27845400 14001
AnnaBridge 172:65be27845400 14002 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 172:65be27845400 14003 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14004 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 172:65be27845400 14005 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14006 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 14007 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14008
AnnaBridge 172:65be27845400 14009 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 172:65be27845400 14010 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14011 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 172:65be27845400 14012
AnnaBridge 172:65be27845400 14013 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 172:65be27845400 14014 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 14015 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 172:65be27845400 14016 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
AnnaBridge 172:65be27845400 14017 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
AnnaBridge 172:65be27845400 14018
AnnaBridge 172:65be27845400 14019 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 172:65be27845400 14020 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14021 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 172:65be27845400 14022 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 172:65be27845400 14023 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14024 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 172:65be27845400 14025
AnnaBridge 172:65be27845400 14026 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 172:65be27845400 14027 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 14028 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 172:65be27845400 14029 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 14030 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
AnnaBridge 172:65be27845400 14031 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
AnnaBridge 172:65be27845400 14032
AnnaBridge 172:65be27845400 14033 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 172:65be27845400 14034 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14035 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 172:65be27845400 14036
AnnaBridge 172:65be27845400 14037 /*----------------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 14038
AnnaBridge 172:65be27845400 14039 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 172:65be27845400 14040 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 14041 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 172:65be27845400 14042 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 172:65be27845400 14043 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 172:65be27845400 14044
AnnaBridge 172:65be27845400 14045 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 172:65be27845400 14046 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 14047 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 172:65be27845400 14048 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14049 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 14050 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14051 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 14052
AnnaBridge 172:65be27845400 14053 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 172:65be27845400 14054 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 14055 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 172:65be27845400 14056 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 172:65be27845400 14057 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 172:65be27845400 14058
AnnaBridge 172:65be27845400 14059 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 172:65be27845400 14060 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 14061 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 172:65be27845400 14062 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 14063 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 172:65be27845400 14064 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 172:65be27845400 14065 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
AnnaBridge 172:65be27845400 14066
AnnaBridge 172:65be27845400 14067 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 172:65be27845400 14068 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 172:65be27845400 14069 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 14070 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 172:65be27845400 14071 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
AnnaBridge 172:65be27845400 14072 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
AnnaBridge 172:65be27845400 14073
AnnaBridge 172:65be27845400 14074 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 172:65be27845400 14075 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14076 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 172:65be27845400 14077 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 172:65be27845400 14078 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14079 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 172:65be27845400 14080
AnnaBridge 172:65be27845400 14081 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 172:65be27845400 14082 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14083 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 172:65be27845400 14084 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14085 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 14086 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14087
AnnaBridge 172:65be27845400 14088 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 172:65be27845400 14089 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14090 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 172:65be27845400 14091
AnnaBridge 172:65be27845400 14092 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 172:65be27845400 14093 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 14094 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 172:65be27845400 14095 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
AnnaBridge 172:65be27845400 14096 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
AnnaBridge 172:65be27845400 14097
AnnaBridge 172:65be27845400 14098 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 172:65be27845400 14099 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14100 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 172:65be27845400 14101 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 172:65be27845400 14102 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14103 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 172:65be27845400 14104
AnnaBridge 172:65be27845400 14105 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 172:65be27845400 14106 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 14107 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 172:65be27845400 14108 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 14109 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
AnnaBridge 172:65be27845400 14110 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
AnnaBridge 172:65be27845400 14111
AnnaBridge 172:65be27845400 14112 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 172:65be27845400 14113 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14114 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 172:65be27845400 14115
AnnaBridge 172:65be27845400 14116 /*----------------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 14117
AnnaBridge 172:65be27845400 14118 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 172:65be27845400 14119 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 14120 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 172:65be27845400 14121 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 172:65be27845400 14122 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 172:65be27845400 14123
AnnaBridge 172:65be27845400 14124 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 172:65be27845400 14125 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 14126 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 172:65be27845400 14127 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14128 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 14129 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14130 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 14131
AnnaBridge 172:65be27845400 14132 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 172:65be27845400 14133 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 14134 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 172:65be27845400 14135 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 172:65be27845400 14136 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 172:65be27845400 14137
AnnaBridge 172:65be27845400 14138 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 172:65be27845400 14139 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 14140 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 172:65be27845400 14141 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 14142 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 172:65be27845400 14143 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 172:65be27845400 14144 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
AnnaBridge 172:65be27845400 14145
AnnaBridge 172:65be27845400 14146 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 172:65be27845400 14147 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 172:65be27845400 14148 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14149 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 172:65be27845400 14150 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 172:65be27845400 14151 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14152 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 172:65be27845400 14153 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 172:65be27845400 14154 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14155 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 172:65be27845400 14156 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 172:65be27845400 14157 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14158 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 172:65be27845400 14159 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 172:65be27845400 14160 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14161 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 172:65be27845400 14162 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 172:65be27845400 14163 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14164 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 172:65be27845400 14165 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 172:65be27845400 14166 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14167 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 172:65be27845400 14168 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 172:65be27845400 14169 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14170 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 172:65be27845400 14171 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 172:65be27845400 14172 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14173 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 172:65be27845400 14174 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 172:65be27845400 14175 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14176 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 172:65be27845400 14177 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 172:65be27845400 14178 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14179 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 172:65be27845400 14180 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 172:65be27845400 14181 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14182 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 172:65be27845400 14183 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 172:65be27845400 14184 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14185 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 172:65be27845400 14186 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 172:65be27845400 14187 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14188 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 172:65be27845400 14189 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 172:65be27845400 14190 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14191 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 172:65be27845400 14192
AnnaBridge 172:65be27845400 14193 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 172:65be27845400 14194 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 172:65be27845400 14195 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 14196 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 172:65be27845400 14197
AnnaBridge 172:65be27845400 14198 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 172:65be27845400 14199 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 172:65be27845400 14200 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14201 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 172:65be27845400 14202
AnnaBridge 172:65be27845400 14203 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 172:65be27845400 14204 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 172:65be27845400 14205 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 14206 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 172:65be27845400 14207
AnnaBridge 172:65be27845400 14208 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 172:65be27845400 14209 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 172:65be27845400 14210 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 14211 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 172:65be27845400 14212
AnnaBridge 172:65be27845400 14213 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 172:65be27845400 14214 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 172:65be27845400 14215 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14216 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 172:65be27845400 14217
AnnaBridge 172:65be27845400 14218 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 172:65be27845400 14219 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 172:65be27845400 14220 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14221 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 172:65be27845400 14222
AnnaBridge 172:65be27845400 14223 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 172:65be27845400 14224 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 172:65be27845400 14225 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14226 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 172:65be27845400 14227
AnnaBridge 172:65be27845400 14228 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 172:65be27845400 14229 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 172:65be27845400 14230 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14231 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 172:65be27845400 14232
AnnaBridge 172:65be27845400 14233 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 172:65be27845400 14234 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 172:65be27845400 14235 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 14236 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 172:65be27845400 14237 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
AnnaBridge 172:65be27845400 14238 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
AnnaBridge 172:65be27845400 14239 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
AnnaBridge 172:65be27845400 14240 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
AnnaBridge 172:65be27845400 14241 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14242 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 14243 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14244 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 14245
AnnaBridge 172:65be27845400 14246 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 172:65be27845400 14247 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 14248 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 172:65be27845400 14249 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
AnnaBridge 172:65be27845400 14250 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
AnnaBridge 172:65be27845400 14251
AnnaBridge 172:65be27845400 14252 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 172:65be27845400 14253 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14254 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 172:65be27845400 14255 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 172:65be27845400 14256 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14257 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 172:65be27845400 14258 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 172:65be27845400 14259 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14260 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 172:65be27845400 14261 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 172:65be27845400 14262 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14263 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 172:65be27845400 14264 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 172:65be27845400 14265 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14266 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 172:65be27845400 14267 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 172:65be27845400 14268 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14269 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 172:65be27845400 14270
AnnaBridge 172:65be27845400 14271 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 172:65be27845400 14272 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 172:65be27845400 14273 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 14274 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 172:65be27845400 14275 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 172:65be27845400 14276 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 172:65be27845400 14277 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 172:65be27845400 14278 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 172:65be27845400 14279 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14280
AnnaBridge 172:65be27845400 14281 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 172:65be27845400 14282 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 14283 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 172:65be27845400 14284 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 172:65be27845400 14285 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 172:65be27845400 14286 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 172:65be27845400 14287 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 172:65be27845400 14288 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 14289
AnnaBridge 172:65be27845400 14290 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 172:65be27845400 14291 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 172:65be27845400 14292 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14293 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 172:65be27845400 14294
AnnaBridge 172:65be27845400 14295 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 172:65be27845400 14296 #define TIM_OR_TI1_RMP_Pos (0U)
AnnaBridge 172:65be27845400 14297 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 14298 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 172:65be27845400 14299 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14300 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14301
AnnaBridge 172:65be27845400 14302 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 172:65be27845400 14303 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 14304 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 172:65be27845400 14305 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14306 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 14307 #define TIM_OR_ITR1_RMP_Pos (10U)
AnnaBridge 172:65be27845400 14308 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 14309 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 172:65be27845400 14310 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
AnnaBridge 172:65be27845400 14311 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
AnnaBridge 172:65be27845400 14312
AnnaBridge 172:65be27845400 14313
AnnaBridge 172:65be27845400 14314 /******************************************************************************/
AnnaBridge 172:65be27845400 14315 /* */
AnnaBridge 172:65be27845400 14316 /* Universal Synchronous Asynchronous Receiver Transmitter */
AnnaBridge 172:65be27845400 14317 /* */
AnnaBridge 172:65be27845400 14318 /******************************************************************************/
AnnaBridge 172:65be27845400 14319 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 172:65be27845400 14320 #define USART_SR_PE_Pos (0U)
AnnaBridge 172:65be27845400 14321 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14322 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
AnnaBridge 172:65be27845400 14323 #define USART_SR_FE_Pos (1U)
AnnaBridge 172:65be27845400 14324 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14325 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
AnnaBridge 172:65be27845400 14326 #define USART_SR_NE_Pos (2U)
AnnaBridge 172:65be27845400 14327 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14328 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
AnnaBridge 172:65be27845400 14329 #define USART_SR_ORE_Pos (3U)
AnnaBridge 172:65be27845400 14330 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14331 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
AnnaBridge 172:65be27845400 14332 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 172:65be27845400 14333 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14334 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
AnnaBridge 172:65be27845400 14335 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 172:65be27845400 14336 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14337 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
AnnaBridge 172:65be27845400 14338 #define USART_SR_TC_Pos (6U)
AnnaBridge 172:65be27845400 14339 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14340 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
AnnaBridge 172:65be27845400 14341 #define USART_SR_TXE_Pos (7U)
AnnaBridge 172:65be27845400 14342 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14343 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
AnnaBridge 172:65be27845400 14344 #define USART_SR_LBD_Pos (8U)
AnnaBridge 172:65be27845400 14345 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14346 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
AnnaBridge 172:65be27845400 14347 #define USART_SR_CTS_Pos (9U)
AnnaBridge 172:65be27845400 14348 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14349 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
AnnaBridge 172:65be27845400 14350
AnnaBridge 172:65be27845400 14351 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 172:65be27845400 14352 #define USART_DR_DR_Pos (0U)
AnnaBridge 172:65be27845400 14353 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 14354 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
AnnaBridge 172:65be27845400 14355
AnnaBridge 172:65be27845400 14356 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 172:65be27845400 14357 #define USART_BRR_DIV_Fraction_Pos (0U)
AnnaBridge 172:65be27845400 14358 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 14359 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
AnnaBridge 172:65be27845400 14360 #define USART_BRR_DIV_Mantissa_Pos (4U)
AnnaBridge 172:65be27845400 14361 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 14362 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
AnnaBridge 172:65be27845400 14363
AnnaBridge 172:65be27845400 14364 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 172:65be27845400 14365 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 172:65be27845400 14366 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14367 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
AnnaBridge 172:65be27845400 14368 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 172:65be27845400 14369 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14370 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
AnnaBridge 172:65be27845400 14371 #define USART_CR1_RE_Pos (2U)
AnnaBridge 172:65be27845400 14372 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14373 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
AnnaBridge 172:65be27845400 14374 #define USART_CR1_TE_Pos (3U)
AnnaBridge 172:65be27845400 14375 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14376 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
AnnaBridge 172:65be27845400 14377 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 172:65be27845400 14378 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14379 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
AnnaBridge 172:65be27845400 14380 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 172:65be27845400 14381 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14382 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
AnnaBridge 172:65be27845400 14383 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 172:65be27845400 14384 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14385 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
AnnaBridge 172:65be27845400 14386 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 172:65be27845400 14387 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14388 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
AnnaBridge 172:65be27845400 14389 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 172:65be27845400 14390 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14391 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 172:65be27845400 14392 #define USART_CR1_PS_Pos (9U)
AnnaBridge 172:65be27845400 14393 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14394 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
AnnaBridge 172:65be27845400 14395 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 172:65be27845400 14396 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14397 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
AnnaBridge 172:65be27845400 14398 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 172:65be27845400 14399 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14400 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
AnnaBridge 172:65be27845400 14401 #define USART_CR1_M_Pos (12U)
AnnaBridge 172:65be27845400 14402 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14403 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
AnnaBridge 172:65be27845400 14404 #define USART_CR1_UE_Pos (13U)
AnnaBridge 172:65be27845400 14405 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14406 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
AnnaBridge 172:65be27845400 14407 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 172:65be27845400 14408 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14409 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
AnnaBridge 172:65be27845400 14410
AnnaBridge 172:65be27845400 14411 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 172:65be27845400 14412 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 172:65be27845400 14413 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 14414 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
AnnaBridge 172:65be27845400 14415 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 172:65be27845400 14416 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14417 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
AnnaBridge 172:65be27845400 14418 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 172:65be27845400 14419 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14420 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
AnnaBridge 172:65be27845400 14421 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 172:65be27845400 14422 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14423 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
AnnaBridge 172:65be27845400 14424 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 172:65be27845400 14425 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14426 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 172:65be27845400 14427 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 172:65be27845400 14428 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14429 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 172:65be27845400 14430 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 172:65be27845400 14431 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14432 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
AnnaBridge 172:65be27845400 14433
AnnaBridge 172:65be27845400 14434 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 172:65be27845400 14435 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 14436 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
AnnaBridge 172:65be27845400 14437 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
AnnaBridge 172:65be27845400 14438 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
AnnaBridge 172:65be27845400 14439
AnnaBridge 172:65be27845400 14440 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 172:65be27845400 14441 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14442 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
AnnaBridge 172:65be27845400 14443
AnnaBridge 172:65be27845400 14444 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 172:65be27845400 14445 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 172:65be27845400 14446 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14447 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 172:65be27845400 14448 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 172:65be27845400 14449 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14450 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
AnnaBridge 172:65be27845400 14451 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 172:65be27845400 14452 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14453 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
AnnaBridge 172:65be27845400 14454 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 172:65be27845400 14455 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14456 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
AnnaBridge 172:65be27845400 14457 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 172:65be27845400 14458 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14459 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
AnnaBridge 172:65be27845400 14460 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 172:65be27845400 14461 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14462 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
AnnaBridge 172:65be27845400 14463 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 172:65be27845400 14464 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14465 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
AnnaBridge 172:65be27845400 14466 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 172:65be27845400 14467 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14468 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
AnnaBridge 172:65be27845400 14469 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 172:65be27845400 14470 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14471 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
AnnaBridge 172:65be27845400 14472 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 172:65be27845400 14473 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14474 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
AnnaBridge 172:65be27845400 14475 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 172:65be27845400 14476 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14477 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
AnnaBridge 172:65be27845400 14478 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 172:65be27845400 14479 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14480 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
AnnaBridge 172:65be27845400 14481
AnnaBridge 172:65be27845400 14482 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 172:65be27845400 14483 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 172:65be27845400 14484 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 14485 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
AnnaBridge 172:65be27845400 14486 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
AnnaBridge 172:65be27845400 14487 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
AnnaBridge 172:65be27845400 14488 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
AnnaBridge 172:65be27845400 14489 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
AnnaBridge 172:65be27845400 14490 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14491 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 14492 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14493 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 14494
AnnaBridge 172:65be27845400 14495 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 172:65be27845400 14496 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 14497 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
AnnaBridge 172:65be27845400 14498
AnnaBridge 172:65be27845400 14499 /******************************************************************************/
AnnaBridge 172:65be27845400 14500 /* */
AnnaBridge 172:65be27845400 14501 /* Window WATCHDOG */
AnnaBridge 172:65be27845400 14502 /* */
AnnaBridge 172:65be27845400 14503 /******************************************************************************/
AnnaBridge 172:65be27845400 14504 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 172:65be27845400 14505 #define WWDG_CR_T_Pos (0U)
AnnaBridge 172:65be27845400 14506 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 14507 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 172:65be27845400 14508 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 172:65be27845400 14509 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 172:65be27845400 14510 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 172:65be27845400 14511 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 172:65be27845400 14512 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 172:65be27845400 14513 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 172:65be27845400 14514 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
AnnaBridge 172:65be27845400 14515 /* Legacy defines */
AnnaBridge 172:65be27845400 14516 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 172:65be27845400 14517 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 172:65be27845400 14518 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 172:65be27845400 14519 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 172:65be27845400 14520 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 172:65be27845400 14521 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 172:65be27845400 14522 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 172:65be27845400 14523
AnnaBridge 172:65be27845400 14524 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 172:65be27845400 14525 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14526 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 172:65be27845400 14527
AnnaBridge 172:65be27845400 14528 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 172:65be27845400 14529 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 172:65be27845400 14530 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 14531 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 172:65be27845400 14532 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 172:65be27845400 14533 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 172:65be27845400 14534 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 172:65be27845400 14535 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 172:65be27845400 14536 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 172:65be27845400 14537 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 172:65be27845400 14538 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
AnnaBridge 172:65be27845400 14539 /* Legacy defines */
AnnaBridge 172:65be27845400 14540 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 172:65be27845400 14541 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 172:65be27845400 14542 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 172:65be27845400 14543 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 172:65be27845400 14544 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 172:65be27845400 14545 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 172:65be27845400 14546 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 172:65be27845400 14547
AnnaBridge 172:65be27845400 14548 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 172:65be27845400 14549 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 172:65be27845400 14550 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 172:65be27845400 14551 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 172:65be27845400 14552 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
AnnaBridge 172:65be27845400 14553 /* Legacy defines */
AnnaBridge 172:65be27845400 14554 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 172:65be27845400 14555 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 172:65be27845400 14556
AnnaBridge 172:65be27845400 14557 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 172:65be27845400 14558 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14559 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 172:65be27845400 14560
AnnaBridge 172:65be27845400 14561 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 172:65be27845400 14562 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 172:65be27845400 14563 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14564 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 172:65be27845400 14565
AnnaBridge 172:65be27845400 14566
AnnaBridge 172:65be27845400 14567 /******************************************************************************/
AnnaBridge 172:65be27845400 14568 /* */
AnnaBridge 172:65be27845400 14569 /* DBG */
AnnaBridge 172:65be27845400 14570 /* */
AnnaBridge 172:65be27845400 14571 /******************************************************************************/
AnnaBridge 172:65be27845400 14572 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 172:65be27845400 14573 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 172:65be27845400 14574 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 14575 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 172:65be27845400 14576 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 172:65be27845400 14577 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 14578 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 172:65be27845400 14579
AnnaBridge 172:65be27845400 14580 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 172:65be27845400 14581 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 172:65be27845400 14582 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14583 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 172:65be27845400 14584 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 172:65be27845400 14585 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14586 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 172:65be27845400 14587 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 172:65be27845400 14588 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14589 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 172:65be27845400 14590 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 172:65be27845400 14591 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14592 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 172:65be27845400 14593
AnnaBridge 172:65be27845400 14594 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 172:65be27845400 14595 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 14596 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 172:65be27845400 14597 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14598 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14599
AnnaBridge 172:65be27845400 14600 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 172:65be27845400 14601 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 172:65be27845400 14602 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14603 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 172:65be27845400 14604 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 172:65be27845400 14605 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14606 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 172:65be27845400 14607 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 172:65be27845400 14608 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14609 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
AnnaBridge 172:65be27845400 14610 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 172:65be27845400 14611 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14612 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 172:65be27845400 14613 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 172:65be27845400 14614 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14615 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
AnnaBridge 172:65be27845400 14616 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 172:65be27845400 14617 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14618 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
AnnaBridge 172:65be27845400 14619 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
AnnaBridge 172:65be27845400 14620 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14621 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
AnnaBridge 172:65be27845400 14622 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
AnnaBridge 172:65be27845400 14623 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14624 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
AnnaBridge 172:65be27845400 14625 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
AnnaBridge 172:65be27845400 14626 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14627 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
AnnaBridge 172:65be27845400 14628 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 172:65be27845400 14629 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14630 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 172:65be27845400 14631 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 172:65be27845400 14632 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14633 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 172:65be27845400 14634 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 172:65be27845400 14635 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14636 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 172:65be27845400 14637 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 172:65be27845400 14638 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14639 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 172:65be27845400 14640 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 172:65be27845400 14641 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14642 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 172:65be27845400 14643 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
AnnaBridge 172:65be27845400 14644 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14645 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
AnnaBridge 172:65be27845400 14646 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
AnnaBridge 172:65be27845400 14647 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14648 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
AnnaBridge 172:65be27845400 14649 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
AnnaBridge 172:65be27845400 14650 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 14651 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
AnnaBridge 172:65be27845400 14652 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
AnnaBridge 172:65be27845400 14653 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
AnnaBridge 172:65be27845400 14654
AnnaBridge 172:65be27845400 14655 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 172:65be27845400 14656 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 172:65be27845400 14657 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14658 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 172:65be27845400 14659 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
AnnaBridge 172:65be27845400 14660 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14661 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
AnnaBridge 172:65be27845400 14662 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 172:65be27845400 14663 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14664 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 172:65be27845400 14665 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
AnnaBridge 172:65be27845400 14666 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14667 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
AnnaBridge 172:65be27845400 14668 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 172:65be27845400 14669 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14670 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
AnnaBridge 172:65be27845400 14671
AnnaBridge 172:65be27845400 14672 /******************************************************************************/
AnnaBridge 172:65be27845400 14673 /* */
AnnaBridge 172:65be27845400 14674 /* Ethernet MAC Registers bits definitions */
AnnaBridge 172:65be27845400 14675 /* */
AnnaBridge 172:65be27845400 14676 /******************************************************************************/
AnnaBridge 172:65be27845400 14677 /* Bit definition for Ethernet MAC Control Register register */
AnnaBridge 172:65be27845400 14678 #define ETH_MACCR_WD_Pos (23U)
AnnaBridge 172:65be27845400 14679 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14680 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
AnnaBridge 172:65be27845400 14681 #define ETH_MACCR_JD_Pos (22U)
AnnaBridge 172:65be27845400 14682 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14683 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
AnnaBridge 172:65be27845400 14684 #define ETH_MACCR_IFG_Pos (17U)
AnnaBridge 172:65be27845400 14685 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 14686 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
AnnaBridge 172:65be27845400 14687 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
AnnaBridge 172:65be27845400 14688 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
AnnaBridge 172:65be27845400 14689 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
AnnaBridge 172:65be27845400 14690 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
AnnaBridge 172:65be27845400 14691 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
AnnaBridge 172:65be27845400 14692 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
AnnaBridge 172:65be27845400 14693 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
AnnaBridge 172:65be27845400 14694 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
AnnaBridge 172:65be27845400 14695 #define ETH_MACCR_CSD_Pos (16U)
AnnaBridge 172:65be27845400 14696 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14697 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
AnnaBridge 172:65be27845400 14698 #define ETH_MACCR_FES_Pos (14U)
AnnaBridge 172:65be27845400 14699 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14700 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
AnnaBridge 172:65be27845400 14701 #define ETH_MACCR_ROD_Pos (13U)
AnnaBridge 172:65be27845400 14702 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14703 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
AnnaBridge 172:65be27845400 14704 #define ETH_MACCR_LM_Pos (12U)
AnnaBridge 172:65be27845400 14705 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14706 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
AnnaBridge 172:65be27845400 14707 #define ETH_MACCR_DM_Pos (11U)
AnnaBridge 172:65be27845400 14708 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14709 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
AnnaBridge 172:65be27845400 14710 #define ETH_MACCR_IPCO_Pos (10U)
AnnaBridge 172:65be27845400 14711 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14712 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
AnnaBridge 172:65be27845400 14713 #define ETH_MACCR_RD_Pos (9U)
AnnaBridge 172:65be27845400 14714 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14715 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
AnnaBridge 172:65be27845400 14716 #define ETH_MACCR_APCS_Pos (7U)
AnnaBridge 172:65be27845400 14717 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14718 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
AnnaBridge 172:65be27845400 14719 #define ETH_MACCR_BL_Pos (5U)
AnnaBridge 172:65be27845400 14720 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 14721 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
AnnaBridge 172:65be27845400 14722 a transmission attempt during retries after a collision: 0 =< r <2^k */
AnnaBridge 172:65be27845400 14723 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
AnnaBridge 172:65be27845400 14724 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
AnnaBridge 172:65be27845400 14725 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
AnnaBridge 172:65be27845400 14726 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
AnnaBridge 172:65be27845400 14727 #define ETH_MACCR_DC_Pos (4U)
AnnaBridge 172:65be27845400 14728 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14729 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
AnnaBridge 172:65be27845400 14730 #define ETH_MACCR_TE_Pos (3U)
AnnaBridge 172:65be27845400 14731 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14732 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
AnnaBridge 172:65be27845400 14733 #define ETH_MACCR_RE_Pos (2U)
AnnaBridge 172:65be27845400 14734 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14735 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
AnnaBridge 172:65be27845400 14736
AnnaBridge 172:65be27845400 14737 /* Bit definition for Ethernet MAC Frame Filter Register */
AnnaBridge 172:65be27845400 14738 #define ETH_MACFFR_RA_Pos (31U)
AnnaBridge 172:65be27845400 14739 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 14740 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
AnnaBridge 172:65be27845400 14741 #define ETH_MACFFR_HPF_Pos (10U)
AnnaBridge 172:65be27845400 14742 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14743 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
AnnaBridge 172:65be27845400 14744 #define ETH_MACFFR_SAF_Pos (9U)
AnnaBridge 172:65be27845400 14745 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14746 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
AnnaBridge 172:65be27845400 14747 #define ETH_MACFFR_SAIF_Pos (8U)
AnnaBridge 172:65be27845400 14748 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14749 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
AnnaBridge 172:65be27845400 14750 #define ETH_MACFFR_PCF_Pos (6U)
AnnaBridge 172:65be27845400 14751 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 14752 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
AnnaBridge 172:65be27845400 14753 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
AnnaBridge 172:65be27845400 14754 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14755 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
AnnaBridge 172:65be27845400 14756 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
AnnaBridge 172:65be27845400 14757 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14758 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
AnnaBridge 172:65be27845400 14759 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
AnnaBridge 172:65be27845400 14760 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 14761 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
AnnaBridge 172:65be27845400 14762 #define ETH_MACFFR_BFD_Pos (5U)
AnnaBridge 172:65be27845400 14763 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14764 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
AnnaBridge 172:65be27845400 14765 #define ETH_MACFFR_PAM_Pos (4U)
AnnaBridge 172:65be27845400 14766 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14767 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
AnnaBridge 172:65be27845400 14768 #define ETH_MACFFR_DAIF_Pos (3U)
AnnaBridge 172:65be27845400 14769 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14770 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
AnnaBridge 172:65be27845400 14771 #define ETH_MACFFR_HM_Pos (2U)
AnnaBridge 172:65be27845400 14772 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14773 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
AnnaBridge 172:65be27845400 14774 #define ETH_MACFFR_HU_Pos (1U)
AnnaBridge 172:65be27845400 14775 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14776 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
AnnaBridge 172:65be27845400 14777 #define ETH_MACFFR_PM_Pos (0U)
AnnaBridge 172:65be27845400 14778 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14779 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
AnnaBridge 172:65be27845400 14780
AnnaBridge 172:65be27845400 14781 /* Bit definition for Ethernet MAC Hash Table High Register */
AnnaBridge 172:65be27845400 14782 #define ETH_MACHTHR_HTH_Pos (0U)
AnnaBridge 172:65be27845400 14783 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 14784 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
AnnaBridge 172:65be27845400 14785
AnnaBridge 172:65be27845400 14786 /* Bit definition for Ethernet MAC Hash Table Low Register */
AnnaBridge 172:65be27845400 14787 #define ETH_MACHTLR_HTL_Pos (0U)
AnnaBridge 172:65be27845400 14788 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 14789 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
AnnaBridge 172:65be27845400 14790
AnnaBridge 172:65be27845400 14791 /* Bit definition for Ethernet MAC MII Address Register */
AnnaBridge 172:65be27845400 14792 #define ETH_MACMIIAR_PA_Pos (11U)
AnnaBridge 172:65be27845400 14793 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
AnnaBridge 172:65be27845400 14794 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
AnnaBridge 172:65be27845400 14795 #define ETH_MACMIIAR_MR_Pos (6U)
AnnaBridge 172:65be27845400 14796 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 14797 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
AnnaBridge 172:65be27845400 14798 #define ETH_MACMIIAR_CR_Pos (2U)
AnnaBridge 172:65be27845400 14799 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
AnnaBridge 172:65be27845400 14800 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
AnnaBridge 172:65be27845400 14801 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
AnnaBridge 172:65be27845400 14802 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
AnnaBridge 172:65be27845400 14803 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14804 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
AnnaBridge 172:65be27845400 14805 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
AnnaBridge 172:65be27845400 14806 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14807 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
AnnaBridge 172:65be27845400 14808 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
AnnaBridge 172:65be27845400 14809 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 14810 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
AnnaBridge 172:65be27845400 14811 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
AnnaBridge 172:65be27845400 14812 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14813 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
AnnaBridge 172:65be27845400 14814 #define ETH_MACMIIAR_MW_Pos (1U)
AnnaBridge 172:65be27845400 14815 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14816 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
AnnaBridge 172:65be27845400 14817 #define ETH_MACMIIAR_MB_Pos (0U)
AnnaBridge 172:65be27845400 14818 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14819 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
AnnaBridge 172:65be27845400 14820
AnnaBridge 172:65be27845400 14821 /* Bit definition for Ethernet MAC MII Data Register */
AnnaBridge 172:65be27845400 14822 #define ETH_MACMIIDR_MD_Pos (0U)
AnnaBridge 172:65be27845400 14823 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14824 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
AnnaBridge 172:65be27845400 14825
AnnaBridge 172:65be27845400 14826 /* Bit definition for Ethernet MAC Flow Control Register */
AnnaBridge 172:65be27845400 14827 #define ETH_MACFCR_PT_Pos (16U)
AnnaBridge 172:65be27845400 14828 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 14829 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
AnnaBridge 172:65be27845400 14830 #define ETH_MACFCR_ZQPD_Pos (7U)
AnnaBridge 172:65be27845400 14831 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14832 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
AnnaBridge 172:65be27845400 14833 #define ETH_MACFCR_PLT_Pos (4U)
AnnaBridge 172:65be27845400 14834 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 14835 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
AnnaBridge 172:65be27845400 14836 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
AnnaBridge 172:65be27845400 14837 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
AnnaBridge 172:65be27845400 14838 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14839 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
AnnaBridge 172:65be27845400 14840 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
AnnaBridge 172:65be27845400 14841 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14842 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
AnnaBridge 172:65be27845400 14843 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
AnnaBridge 172:65be27845400 14844 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 14845 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
AnnaBridge 172:65be27845400 14846 #define ETH_MACFCR_UPFD_Pos (3U)
AnnaBridge 172:65be27845400 14847 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14848 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
AnnaBridge 172:65be27845400 14849 #define ETH_MACFCR_RFCE_Pos (2U)
AnnaBridge 172:65be27845400 14850 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14851 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
AnnaBridge 172:65be27845400 14852 #define ETH_MACFCR_TFCE_Pos (1U)
AnnaBridge 172:65be27845400 14853 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14854 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
AnnaBridge 172:65be27845400 14855 #define ETH_MACFCR_FCBBPA_Pos (0U)
AnnaBridge 172:65be27845400 14856 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14857 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
AnnaBridge 172:65be27845400 14858
AnnaBridge 172:65be27845400 14859 /* Bit definition for Ethernet MAC VLAN Tag Register */
AnnaBridge 172:65be27845400 14860 #define ETH_MACVLANTR_VLANTC_Pos (16U)
AnnaBridge 172:65be27845400 14861 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14862 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
AnnaBridge 172:65be27845400 14863 #define ETH_MACVLANTR_VLANTI_Pos (0U)
AnnaBridge 172:65be27845400 14864 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 14865 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
AnnaBridge 172:65be27845400 14866
AnnaBridge 172:65be27845400 14867 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
AnnaBridge 172:65be27845400 14868 #define ETH_MACRWUFFR_D_Pos (0U)
AnnaBridge 172:65be27845400 14869 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 14870 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
AnnaBridge 172:65be27845400 14871 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
AnnaBridge 172:65be27845400 14872 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
AnnaBridge 172:65be27845400 14873 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
AnnaBridge 172:65be27845400 14874 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
AnnaBridge 172:65be27845400 14875 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
AnnaBridge 172:65be27845400 14876 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
AnnaBridge 172:65be27845400 14877 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
AnnaBridge 172:65be27845400 14878 RSVD - Filter1 Command - RSVD - Filter0 Command
AnnaBridge 172:65be27845400 14879 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
AnnaBridge 172:65be27845400 14880 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
AnnaBridge 172:65be27845400 14881 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
AnnaBridge 172:65be27845400 14882
AnnaBridge 172:65be27845400 14883 /* Bit definition for Ethernet MAC PMT Control and Status Register */
AnnaBridge 172:65be27845400 14884 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
AnnaBridge 172:65be27845400 14885 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 14886 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
AnnaBridge 172:65be27845400 14887 #define ETH_MACPMTCSR_GU_Pos (9U)
AnnaBridge 172:65be27845400 14888 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14889 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
AnnaBridge 172:65be27845400 14890 #define ETH_MACPMTCSR_WFR_Pos (6U)
AnnaBridge 172:65be27845400 14891 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14892 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
AnnaBridge 172:65be27845400 14893 #define ETH_MACPMTCSR_MPR_Pos (5U)
AnnaBridge 172:65be27845400 14894 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14895 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
AnnaBridge 172:65be27845400 14896 #define ETH_MACPMTCSR_WFE_Pos (2U)
AnnaBridge 172:65be27845400 14897 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14898 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
AnnaBridge 172:65be27845400 14899 #define ETH_MACPMTCSR_MPE_Pos (1U)
AnnaBridge 172:65be27845400 14900 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14901 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
AnnaBridge 172:65be27845400 14902 #define ETH_MACPMTCSR_PD_Pos (0U)
AnnaBridge 172:65be27845400 14903 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14904 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
AnnaBridge 172:65be27845400 14905
AnnaBridge 172:65be27845400 14906 /* Bit definition for Ethernet MAC debug Register */
AnnaBridge 172:65be27845400 14907 #define ETH_MACDBGR_TFF_Pos (25U)
AnnaBridge 172:65be27845400 14908 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14909 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
AnnaBridge 172:65be27845400 14910 #define ETH_MACDBGR_TFNE_Pos (24U)
AnnaBridge 172:65be27845400 14911 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14912 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
AnnaBridge 172:65be27845400 14913 #define ETH_MACDBGR_TFWA_Pos (22U)
AnnaBridge 172:65be27845400 14914 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14915 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
AnnaBridge 172:65be27845400 14916 #define ETH_MACDBGR_TFRS_Pos (20U)
AnnaBridge 172:65be27845400 14917 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 14918 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
AnnaBridge 172:65be27845400 14919 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
AnnaBridge 172:65be27845400 14920 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 14921 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge 172:65be27845400 14922 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
AnnaBridge 172:65be27845400 14923 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14924 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
AnnaBridge 172:65be27845400 14925 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
AnnaBridge 172:65be27845400 14926 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14927 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
AnnaBridge 172:65be27845400 14928 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
AnnaBridge 172:65be27845400 14929 #define ETH_MACDBGR_MTP_Pos (19U)
AnnaBridge 172:65be27845400 14930 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 14931 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
AnnaBridge 172:65be27845400 14932 #define ETH_MACDBGR_MTFCS_Pos (17U)
AnnaBridge 172:65be27845400 14933 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 14934 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
AnnaBridge 172:65be27845400 14935 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
AnnaBridge 172:65be27845400 14936 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 14937 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
AnnaBridge 172:65be27845400 14938 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
AnnaBridge 172:65be27845400 14939 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14940 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge 172:65be27845400 14941 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
AnnaBridge 172:65be27845400 14942 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14943 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge 172:65be27845400 14944 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
AnnaBridge 172:65be27845400 14945 #define ETH_MACDBGR_MMTEA_Pos (16U)
AnnaBridge 172:65be27845400 14946 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14947 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
AnnaBridge 172:65be27845400 14948 #define ETH_MACDBGR_RFFL_Pos (8U)
AnnaBridge 172:65be27845400 14949 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 14950 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
AnnaBridge 172:65be27845400 14951 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
AnnaBridge 172:65be27845400 14952 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 14953 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
AnnaBridge 172:65be27845400 14954 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
AnnaBridge 172:65be27845400 14955 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14956 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
AnnaBridge 172:65be27845400 14957 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
AnnaBridge 172:65be27845400 14958 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14959 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
AnnaBridge 172:65be27845400 14960 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
AnnaBridge 172:65be27845400 14961 #define ETH_MACDBGR_RFRCS_Pos (5U)
AnnaBridge 172:65be27845400 14962 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 14963 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
AnnaBridge 172:65be27845400 14964 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
AnnaBridge 172:65be27845400 14965 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 14966 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
AnnaBridge 172:65be27845400 14967 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
AnnaBridge 172:65be27845400 14968 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14969 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
AnnaBridge 172:65be27845400 14970 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
AnnaBridge 172:65be27845400 14971 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14972 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
AnnaBridge 172:65be27845400 14973 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
AnnaBridge 172:65be27845400 14974 #define ETH_MACDBGR_RFWRA_Pos (4U)
AnnaBridge 172:65be27845400 14975 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14976 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
AnnaBridge 172:65be27845400 14977 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
AnnaBridge 172:65be27845400 14978 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 14979 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
AnnaBridge 172:65be27845400 14980 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14981 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14982 #define ETH_MACDBGR_MMRPEA_Pos (0U)
AnnaBridge 172:65be27845400 14983 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14984 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
AnnaBridge 172:65be27845400 14985
AnnaBridge 172:65be27845400 14986 /* Bit definition for Ethernet MAC Status Register */
AnnaBridge 172:65be27845400 14987 #define ETH_MACSR_TSTS_Pos (9U)
AnnaBridge 172:65be27845400 14988 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14989 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
AnnaBridge 172:65be27845400 14990 #define ETH_MACSR_MMCTS_Pos (6U)
AnnaBridge 172:65be27845400 14991 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14992 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
AnnaBridge 172:65be27845400 14993 #define ETH_MACSR_MMMCRS_Pos (5U)
AnnaBridge 172:65be27845400 14994 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14995 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
AnnaBridge 172:65be27845400 14996 #define ETH_MACSR_MMCS_Pos (4U)
AnnaBridge 172:65be27845400 14997 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14998 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
AnnaBridge 172:65be27845400 14999 #define ETH_MACSR_PMTS_Pos (3U)
AnnaBridge 172:65be27845400 15000 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15001 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
AnnaBridge 172:65be27845400 15002
AnnaBridge 172:65be27845400 15003 /* Bit definition for Ethernet MAC Interrupt Mask Register */
AnnaBridge 172:65be27845400 15004 #define ETH_MACIMR_TSTIM_Pos (9U)
AnnaBridge 172:65be27845400 15005 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15006 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
AnnaBridge 172:65be27845400 15007 #define ETH_MACIMR_PMTIM_Pos (3U)
AnnaBridge 172:65be27845400 15008 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15009 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
AnnaBridge 172:65be27845400 15010
AnnaBridge 172:65be27845400 15011 /* Bit definition for Ethernet MAC Address0 High Register */
AnnaBridge 172:65be27845400 15012 #define ETH_MACA0HR_MACA0H_Pos (0U)
AnnaBridge 172:65be27845400 15013 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15014 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
AnnaBridge 172:65be27845400 15015
AnnaBridge 172:65be27845400 15016 /* Bit definition for Ethernet MAC Address0 Low Register */
AnnaBridge 172:65be27845400 15017 #define ETH_MACA0LR_MACA0L_Pos (0U)
AnnaBridge 172:65be27845400 15018 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15019 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
AnnaBridge 172:65be27845400 15020
AnnaBridge 172:65be27845400 15021 /* Bit definition for Ethernet MAC Address1 High Register */
AnnaBridge 172:65be27845400 15022 #define ETH_MACA1HR_AE_Pos (31U)
AnnaBridge 172:65be27845400 15023 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15024 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
AnnaBridge 172:65be27845400 15025 #define ETH_MACA1HR_SA_Pos (30U)
AnnaBridge 172:65be27845400 15026 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15027 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
AnnaBridge 172:65be27845400 15028 #define ETH_MACA1HR_MBC_Pos (24U)
AnnaBridge 172:65be27845400 15029 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 15030 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
AnnaBridge 172:65be27845400 15031 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 172:65be27845400 15032 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 172:65be27845400 15033 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 172:65be27845400 15034 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 172:65be27845400 15035 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 172:65be27845400 15036 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
AnnaBridge 172:65be27845400 15037 #define ETH_MACA1HR_MACA1H_Pos (0U)
AnnaBridge 172:65be27845400 15038 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15039 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
AnnaBridge 172:65be27845400 15040
AnnaBridge 172:65be27845400 15041 /* Bit definition for Ethernet MAC Address1 Low Register */
AnnaBridge 172:65be27845400 15042 #define ETH_MACA1LR_MACA1L_Pos (0U)
AnnaBridge 172:65be27845400 15043 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15044 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
AnnaBridge 172:65be27845400 15045
AnnaBridge 172:65be27845400 15046 /* Bit definition for Ethernet MAC Address2 High Register */
AnnaBridge 172:65be27845400 15047 #define ETH_MACA2HR_AE_Pos (31U)
AnnaBridge 172:65be27845400 15048 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15049 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
AnnaBridge 172:65be27845400 15050 #define ETH_MACA2HR_SA_Pos (30U)
AnnaBridge 172:65be27845400 15051 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15052 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
AnnaBridge 172:65be27845400 15053 #define ETH_MACA2HR_MBC_Pos (24U)
AnnaBridge 172:65be27845400 15054 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 15055 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
AnnaBridge 172:65be27845400 15056 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 172:65be27845400 15057 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 172:65be27845400 15058 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 172:65be27845400 15059 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 172:65be27845400 15060 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 172:65be27845400 15061 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 172:65be27845400 15062 #define ETH_MACA2HR_MACA2H_Pos (0U)
AnnaBridge 172:65be27845400 15063 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15064 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
AnnaBridge 172:65be27845400 15065
AnnaBridge 172:65be27845400 15066 /* Bit definition for Ethernet MAC Address2 Low Register */
AnnaBridge 172:65be27845400 15067 #define ETH_MACA2LR_MACA2L_Pos (0U)
AnnaBridge 172:65be27845400 15068 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15069 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
AnnaBridge 172:65be27845400 15070
AnnaBridge 172:65be27845400 15071 /* Bit definition for Ethernet MAC Address3 High Register */
AnnaBridge 172:65be27845400 15072 #define ETH_MACA3HR_AE_Pos (31U)
AnnaBridge 172:65be27845400 15073 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15074 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
AnnaBridge 172:65be27845400 15075 #define ETH_MACA3HR_SA_Pos (30U)
AnnaBridge 172:65be27845400 15076 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15077 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
AnnaBridge 172:65be27845400 15078 #define ETH_MACA3HR_MBC_Pos (24U)
AnnaBridge 172:65be27845400 15079 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 15080 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
AnnaBridge 172:65be27845400 15081 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 172:65be27845400 15082 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 172:65be27845400 15083 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 172:65be27845400 15084 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 172:65be27845400 15085 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 172:65be27845400 15086 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 172:65be27845400 15087 #define ETH_MACA3HR_MACA3H_Pos (0U)
AnnaBridge 172:65be27845400 15088 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15089 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
AnnaBridge 172:65be27845400 15090
AnnaBridge 172:65be27845400 15091 /* Bit definition for Ethernet MAC Address3 Low Register */
AnnaBridge 172:65be27845400 15092 #define ETH_MACA3LR_MACA3L_Pos (0U)
AnnaBridge 172:65be27845400 15093 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15094 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
AnnaBridge 172:65be27845400 15095
AnnaBridge 172:65be27845400 15096 /******************************************************************************/
AnnaBridge 172:65be27845400 15097 /* Ethernet MMC Registers bits definition */
AnnaBridge 172:65be27845400 15098 /******************************************************************************/
AnnaBridge 172:65be27845400 15099
AnnaBridge 172:65be27845400 15100 /* Bit definition for Ethernet MMC Contol Register */
AnnaBridge 172:65be27845400 15101 #define ETH_MMCCR_MCFHP_Pos (5U)
AnnaBridge 172:65be27845400 15102 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15103 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
AnnaBridge 172:65be27845400 15104 #define ETH_MMCCR_MCP_Pos (4U)
AnnaBridge 172:65be27845400 15105 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15106 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
AnnaBridge 172:65be27845400 15107 #define ETH_MMCCR_MCF_Pos (3U)
AnnaBridge 172:65be27845400 15108 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15109 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
AnnaBridge 172:65be27845400 15110 #define ETH_MMCCR_ROR_Pos (2U)
AnnaBridge 172:65be27845400 15111 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15112 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
AnnaBridge 172:65be27845400 15113 #define ETH_MMCCR_CSR_Pos (1U)
AnnaBridge 172:65be27845400 15114 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15115 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
AnnaBridge 172:65be27845400 15116 #define ETH_MMCCR_CR_Pos (0U)
AnnaBridge 172:65be27845400 15117 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15118 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
AnnaBridge 172:65be27845400 15119
AnnaBridge 172:65be27845400 15120 /* Bit definition for Ethernet MMC Receive Interrupt Register */
AnnaBridge 172:65be27845400 15121 #define ETH_MMCRIR_RGUFS_Pos (17U)
AnnaBridge 172:65be27845400 15122 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15123 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15124 #define ETH_MMCRIR_RFAES_Pos (6U)
AnnaBridge 172:65be27845400 15125 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15126 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15127 #define ETH_MMCRIR_RFCES_Pos (5U)
AnnaBridge 172:65be27845400 15128 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15129 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15130
AnnaBridge 172:65be27845400 15131 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
AnnaBridge 172:65be27845400 15132 #define ETH_MMCTIR_TGFS_Pos (21U)
AnnaBridge 172:65be27845400 15133 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15134 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15135 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
AnnaBridge 172:65be27845400 15136 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15137 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15138 #define ETH_MMCTIR_TGFSCS_Pos (14U)
AnnaBridge 172:65be27845400 15139 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15140 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15141
AnnaBridge 172:65be27845400 15142 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
AnnaBridge 172:65be27845400 15143 #define ETH_MMCRIMR_RGUFM_Pos (17U)
AnnaBridge 172:65be27845400 15144 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15145 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15146 #define ETH_MMCRIMR_RFAEM_Pos (6U)
AnnaBridge 172:65be27845400 15147 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15148 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15149 #define ETH_MMCRIMR_RFCEM_Pos (5U)
AnnaBridge 172:65be27845400 15150 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15151 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15152
AnnaBridge 172:65be27845400 15153 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
AnnaBridge 172:65be27845400 15154 #define ETH_MMCTIMR_TGFM_Pos (21U)
AnnaBridge 172:65be27845400 15155 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15156 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15157 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
AnnaBridge 172:65be27845400 15158 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15159 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15160 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
AnnaBridge 172:65be27845400 15161 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15162 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
AnnaBridge 172:65be27845400 15163
AnnaBridge 172:65be27845400 15164 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
AnnaBridge 172:65be27845400 15165 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
AnnaBridge 172:65be27845400 15166 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15167 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
AnnaBridge 172:65be27845400 15168
AnnaBridge 172:65be27845400 15169 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
AnnaBridge 172:65be27845400 15170 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
AnnaBridge 172:65be27845400 15171 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15172 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
AnnaBridge 172:65be27845400 15173
AnnaBridge 172:65be27845400 15174 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
AnnaBridge 172:65be27845400 15175 #define ETH_MMCTGFCR_TGFC_Pos (0U)
AnnaBridge 172:65be27845400 15176 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15177 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
AnnaBridge 172:65be27845400 15178
AnnaBridge 172:65be27845400 15179 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
AnnaBridge 172:65be27845400 15180 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
AnnaBridge 172:65be27845400 15181 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15182 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
AnnaBridge 172:65be27845400 15183
AnnaBridge 172:65be27845400 15184 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
AnnaBridge 172:65be27845400 15185 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
AnnaBridge 172:65be27845400 15186 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15187 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
AnnaBridge 172:65be27845400 15188
AnnaBridge 172:65be27845400 15189 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
AnnaBridge 172:65be27845400 15190 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
AnnaBridge 172:65be27845400 15191 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15192 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
AnnaBridge 172:65be27845400 15193
AnnaBridge 172:65be27845400 15194 /******************************************************************************/
AnnaBridge 172:65be27845400 15195 /* Ethernet PTP Registers bits definition */
AnnaBridge 172:65be27845400 15196 /******************************************************************************/
AnnaBridge 172:65be27845400 15197
AnnaBridge 172:65be27845400 15198 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
AnnaBridge 172:65be27845400 15199 #define ETH_PTPTSCR_TSCNT_Pos (16U)
AnnaBridge 172:65be27845400 15200 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 15201 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
AnnaBridge 172:65be27845400 15202 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
AnnaBridge 172:65be27845400 15203 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15204 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
AnnaBridge 172:65be27845400 15205 #define ETH_PTPTSSR_TSSEME_Pos (14U)
AnnaBridge 172:65be27845400 15206 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15207 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
AnnaBridge 172:65be27845400 15208 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
AnnaBridge 172:65be27845400 15209 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 15210 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
AnnaBridge 172:65be27845400 15211 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
AnnaBridge 172:65be27845400 15212 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15213 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
AnnaBridge 172:65be27845400 15214 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
AnnaBridge 172:65be27845400 15215 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15216 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
AnnaBridge 172:65be27845400 15217 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
AnnaBridge 172:65be27845400 15218 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15219 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
AnnaBridge 172:65be27845400 15220 #define ETH_PTPTSSR_TSSSR_Pos (9U)
AnnaBridge 172:65be27845400 15221 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15222 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
AnnaBridge 172:65be27845400 15223 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
AnnaBridge 172:65be27845400 15224 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15225 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
AnnaBridge 172:65be27845400 15226
AnnaBridge 172:65be27845400 15227 #define ETH_PTPTSCR_TSARU_Pos (5U)
AnnaBridge 172:65be27845400 15228 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15229 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
AnnaBridge 172:65be27845400 15230 #define ETH_PTPTSCR_TSITE_Pos (4U)
AnnaBridge 172:65be27845400 15231 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15232 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
AnnaBridge 172:65be27845400 15233 #define ETH_PTPTSCR_TSSTU_Pos (3U)
AnnaBridge 172:65be27845400 15234 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15235 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
AnnaBridge 172:65be27845400 15236 #define ETH_PTPTSCR_TSSTI_Pos (2U)
AnnaBridge 172:65be27845400 15237 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15238 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
AnnaBridge 172:65be27845400 15239 #define ETH_PTPTSCR_TSFCU_Pos (1U)
AnnaBridge 172:65be27845400 15240 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15241 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
AnnaBridge 172:65be27845400 15242 #define ETH_PTPTSCR_TSE_Pos (0U)
AnnaBridge 172:65be27845400 15243 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15244 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
AnnaBridge 172:65be27845400 15245
AnnaBridge 172:65be27845400 15246 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
AnnaBridge 172:65be27845400 15247 #define ETH_PTPSSIR_STSSI_Pos (0U)
AnnaBridge 172:65be27845400 15248 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 15249 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
AnnaBridge 172:65be27845400 15250
AnnaBridge 172:65be27845400 15251 /* Bit definition for Ethernet PTP Time Stamp High Register */
AnnaBridge 172:65be27845400 15252 #define ETH_PTPTSHR_STS_Pos (0U)
AnnaBridge 172:65be27845400 15253 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15254 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
AnnaBridge 172:65be27845400 15255
AnnaBridge 172:65be27845400 15256 /* Bit definition for Ethernet PTP Time Stamp Low Register */
AnnaBridge 172:65be27845400 15257 #define ETH_PTPTSLR_STPNS_Pos (31U)
AnnaBridge 172:65be27845400 15258 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15259 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
AnnaBridge 172:65be27845400 15260 #define ETH_PTPTSLR_STSS_Pos (0U)
AnnaBridge 172:65be27845400 15261 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 172:65be27845400 15262 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
AnnaBridge 172:65be27845400 15263
AnnaBridge 172:65be27845400 15264 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
AnnaBridge 172:65be27845400 15265 #define ETH_PTPTSHUR_TSUS_Pos (0U)
AnnaBridge 172:65be27845400 15266 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15267 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
AnnaBridge 172:65be27845400 15268
AnnaBridge 172:65be27845400 15269 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
AnnaBridge 172:65be27845400 15270 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
AnnaBridge 172:65be27845400 15271 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15272 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
AnnaBridge 172:65be27845400 15273 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
AnnaBridge 172:65be27845400 15274 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 172:65be27845400 15275 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
AnnaBridge 172:65be27845400 15276
AnnaBridge 172:65be27845400 15277 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
AnnaBridge 172:65be27845400 15278 #define ETH_PTPTSAR_TSA_Pos (0U)
AnnaBridge 172:65be27845400 15279 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15280 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
AnnaBridge 172:65be27845400 15281
AnnaBridge 172:65be27845400 15282 /* Bit definition for Ethernet PTP Target Time High Register */
AnnaBridge 172:65be27845400 15283 #define ETH_PTPTTHR_TTSH_Pos (0U)
AnnaBridge 172:65be27845400 15284 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15285 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
AnnaBridge 172:65be27845400 15286
AnnaBridge 172:65be27845400 15287 /* Bit definition for Ethernet PTP Target Time Low Register */
AnnaBridge 172:65be27845400 15288 #define ETH_PTPTTLR_TTSL_Pos (0U)
AnnaBridge 172:65be27845400 15289 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15290 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
AnnaBridge 172:65be27845400 15291
AnnaBridge 172:65be27845400 15292 /* Bit definition for Ethernet PTP Time Stamp Status Register */
AnnaBridge 172:65be27845400 15293 #define ETH_PTPTSSR_TSTTR_Pos (5U)
AnnaBridge 172:65be27845400 15294 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15295 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
AnnaBridge 172:65be27845400 15296 #define ETH_PTPTSSR_TSSO_Pos (4U)
AnnaBridge 172:65be27845400 15297 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15298 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
AnnaBridge 172:65be27845400 15299
AnnaBridge 172:65be27845400 15300 /******************************************************************************/
AnnaBridge 172:65be27845400 15301 /* Ethernet DMA Registers bits definition */
AnnaBridge 172:65be27845400 15302 /******************************************************************************/
AnnaBridge 172:65be27845400 15303
AnnaBridge 172:65be27845400 15304 /* Bit definition for Ethernet DMA Bus Mode Register */
AnnaBridge 172:65be27845400 15305 #define ETH_DMABMR_AAB_Pos (25U)
AnnaBridge 172:65be27845400 15306 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15307 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
AnnaBridge 172:65be27845400 15308 #define ETH_DMABMR_FPM_Pos (24U)
AnnaBridge 172:65be27845400 15309 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15310 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
AnnaBridge 172:65be27845400 15311 #define ETH_DMABMR_USP_Pos (23U)
AnnaBridge 172:65be27845400 15312 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15313 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
AnnaBridge 172:65be27845400 15314 #define ETH_DMABMR_RDP_Pos (17U)
AnnaBridge 172:65be27845400 15315 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
AnnaBridge 172:65be27845400 15316 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
AnnaBridge 172:65be27845400 15317 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
AnnaBridge 172:65be27845400 15318 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
AnnaBridge 172:65be27845400 15319 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 172:65be27845400 15320 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 172:65be27845400 15321 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 172:65be27845400 15322 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 172:65be27845400 15323 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 172:65be27845400 15324 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 172:65be27845400 15325 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 172:65be27845400 15326 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 172:65be27845400 15327 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
AnnaBridge 172:65be27845400 15328 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
AnnaBridge 172:65be27845400 15329 #define ETH_DMABMR_FB_Pos (16U)
AnnaBridge 172:65be27845400 15330 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15331 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
AnnaBridge 172:65be27845400 15332 #define ETH_DMABMR_RTPR_Pos (14U)
AnnaBridge 172:65be27845400 15333 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 15334 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
AnnaBridge 172:65be27845400 15335 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
AnnaBridge 172:65be27845400 15336 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
AnnaBridge 172:65be27845400 15337 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
AnnaBridge 172:65be27845400 15338 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
AnnaBridge 172:65be27845400 15339 #define ETH_DMABMR_PBL_Pos (8U)
AnnaBridge 172:65be27845400 15340 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
AnnaBridge 172:65be27845400 15341 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
AnnaBridge 172:65be27845400 15342 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
AnnaBridge 172:65be27845400 15343 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
AnnaBridge 172:65be27845400 15344 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 172:65be27845400 15345 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 172:65be27845400 15346 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 172:65be27845400 15347 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 172:65be27845400 15348 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 172:65be27845400 15349 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 172:65be27845400 15350 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 172:65be27845400 15351 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 172:65be27845400 15352 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
AnnaBridge 172:65be27845400 15353 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
AnnaBridge 172:65be27845400 15354 #define ETH_DMABMR_EDE_Pos (7U)
AnnaBridge 172:65be27845400 15355 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15356 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
AnnaBridge 172:65be27845400 15357 #define ETH_DMABMR_DSL_Pos (2U)
AnnaBridge 172:65be27845400 15358 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
AnnaBridge 172:65be27845400 15359 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
AnnaBridge 172:65be27845400 15360 #define ETH_DMABMR_DA_Pos (1U)
AnnaBridge 172:65be27845400 15361 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15362 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
AnnaBridge 172:65be27845400 15363 #define ETH_DMABMR_SR_Pos (0U)
AnnaBridge 172:65be27845400 15364 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15365 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
AnnaBridge 172:65be27845400 15366
AnnaBridge 172:65be27845400 15367 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
AnnaBridge 172:65be27845400 15368 #define ETH_DMATPDR_TPD_Pos (0U)
AnnaBridge 172:65be27845400 15369 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15370 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
AnnaBridge 172:65be27845400 15371
AnnaBridge 172:65be27845400 15372 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
AnnaBridge 172:65be27845400 15373 #define ETH_DMARPDR_RPD_Pos (0U)
AnnaBridge 172:65be27845400 15374 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15375 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
AnnaBridge 172:65be27845400 15376
AnnaBridge 172:65be27845400 15377 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
AnnaBridge 172:65be27845400 15378 #define ETH_DMARDLAR_SRL_Pos (0U)
AnnaBridge 172:65be27845400 15379 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15380 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
AnnaBridge 172:65be27845400 15381
AnnaBridge 172:65be27845400 15382 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
AnnaBridge 172:65be27845400 15383 #define ETH_DMATDLAR_STL_Pos (0U)
AnnaBridge 172:65be27845400 15384 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15385 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
AnnaBridge 172:65be27845400 15386
AnnaBridge 172:65be27845400 15387 /* Bit definition for Ethernet DMA Status Register */
AnnaBridge 172:65be27845400 15388 #define ETH_DMASR_TSTS_Pos (29U)
AnnaBridge 172:65be27845400 15389 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15390 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
AnnaBridge 172:65be27845400 15391 #define ETH_DMASR_PMTS_Pos (28U)
AnnaBridge 172:65be27845400 15392 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15393 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
AnnaBridge 172:65be27845400 15394 #define ETH_DMASR_MMCS_Pos (27U)
AnnaBridge 172:65be27845400 15395 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15396 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
AnnaBridge 172:65be27845400 15397 #define ETH_DMASR_EBS_Pos (23U)
AnnaBridge 172:65be27845400 15398 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
AnnaBridge 172:65be27845400 15399 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
AnnaBridge 172:65be27845400 15400 /* combination with EBS[2:0] for GetFlagStatus function */
AnnaBridge 172:65be27845400 15401 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
AnnaBridge 172:65be27845400 15402 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15403 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
AnnaBridge 172:65be27845400 15404 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
AnnaBridge 172:65be27845400 15405 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15406 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
AnnaBridge 172:65be27845400 15407 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
AnnaBridge 172:65be27845400 15408 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15409 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
AnnaBridge 172:65be27845400 15410 #define ETH_DMASR_TPS_Pos (20U)
AnnaBridge 172:65be27845400 15411 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
AnnaBridge 172:65be27845400 15412 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
AnnaBridge 172:65be27845400 15413 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
AnnaBridge 172:65be27845400 15414 #define ETH_DMASR_TPS_Fetching_Pos (20U)
AnnaBridge 172:65be27845400 15415 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15416 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
AnnaBridge 172:65be27845400 15417 #define ETH_DMASR_TPS_Waiting_Pos (21U)
AnnaBridge 172:65be27845400 15418 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15419 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
AnnaBridge 172:65be27845400 15420 #define ETH_DMASR_TPS_Reading_Pos (20U)
AnnaBridge 172:65be27845400 15421 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 15422 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
AnnaBridge 172:65be27845400 15423 #define ETH_DMASR_TPS_Suspended_Pos (21U)
AnnaBridge 172:65be27845400 15424 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 15425 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
AnnaBridge 172:65be27845400 15426 #define ETH_DMASR_TPS_Closing_Pos (20U)
AnnaBridge 172:65be27845400 15427 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
AnnaBridge 172:65be27845400 15428 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
AnnaBridge 172:65be27845400 15429 #define ETH_DMASR_RPS_Pos (17U)
AnnaBridge 172:65be27845400 15430 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 15431 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
AnnaBridge 172:65be27845400 15432 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
AnnaBridge 172:65be27845400 15433 #define ETH_DMASR_RPS_Fetching_Pos (17U)
AnnaBridge 172:65be27845400 15434 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15435 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
AnnaBridge 172:65be27845400 15436 #define ETH_DMASR_RPS_Waiting_Pos (17U)
AnnaBridge 172:65be27845400 15437 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 15438 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
AnnaBridge 172:65be27845400 15439 #define ETH_DMASR_RPS_Suspended_Pos (19U)
AnnaBridge 172:65be27845400 15440 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15441 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
AnnaBridge 172:65be27845400 15442 #define ETH_DMASR_RPS_Closing_Pos (17U)
AnnaBridge 172:65be27845400 15443 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
AnnaBridge 172:65be27845400 15444 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
AnnaBridge 172:65be27845400 15445 #define ETH_DMASR_RPS_Queuing_Pos (17U)
AnnaBridge 172:65be27845400 15446 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 15447 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
AnnaBridge 172:65be27845400 15448 #define ETH_DMASR_NIS_Pos (16U)
AnnaBridge 172:65be27845400 15449 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15450 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
AnnaBridge 172:65be27845400 15451 #define ETH_DMASR_AIS_Pos (15U)
AnnaBridge 172:65be27845400 15452 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15453 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
AnnaBridge 172:65be27845400 15454 #define ETH_DMASR_ERS_Pos (14U)
AnnaBridge 172:65be27845400 15455 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15456 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
AnnaBridge 172:65be27845400 15457 #define ETH_DMASR_FBES_Pos (13U)
AnnaBridge 172:65be27845400 15458 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 15459 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
AnnaBridge 172:65be27845400 15460 #define ETH_DMASR_ETS_Pos (10U)
AnnaBridge 172:65be27845400 15461 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15462 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
AnnaBridge 172:65be27845400 15463 #define ETH_DMASR_RWTS_Pos (9U)
AnnaBridge 172:65be27845400 15464 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15465 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
AnnaBridge 172:65be27845400 15466 #define ETH_DMASR_RPSS_Pos (8U)
AnnaBridge 172:65be27845400 15467 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15468 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
AnnaBridge 172:65be27845400 15469 #define ETH_DMASR_RBUS_Pos (7U)
AnnaBridge 172:65be27845400 15470 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15471 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
AnnaBridge 172:65be27845400 15472 #define ETH_DMASR_RS_Pos (6U)
AnnaBridge 172:65be27845400 15473 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15474 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
AnnaBridge 172:65be27845400 15475 #define ETH_DMASR_TUS_Pos (5U)
AnnaBridge 172:65be27845400 15476 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15477 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
AnnaBridge 172:65be27845400 15478 #define ETH_DMASR_ROS_Pos (4U)
AnnaBridge 172:65be27845400 15479 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15480 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
AnnaBridge 172:65be27845400 15481 #define ETH_DMASR_TJTS_Pos (3U)
AnnaBridge 172:65be27845400 15482 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15483 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
AnnaBridge 172:65be27845400 15484 #define ETH_DMASR_TBUS_Pos (2U)
AnnaBridge 172:65be27845400 15485 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15486 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
AnnaBridge 172:65be27845400 15487 #define ETH_DMASR_TPSS_Pos (1U)
AnnaBridge 172:65be27845400 15488 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15489 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
AnnaBridge 172:65be27845400 15490 #define ETH_DMASR_TS_Pos (0U)
AnnaBridge 172:65be27845400 15491 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15492 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
AnnaBridge 172:65be27845400 15493
AnnaBridge 172:65be27845400 15494 /* Bit definition for Ethernet DMA Operation Mode Register */
AnnaBridge 172:65be27845400 15495 #define ETH_DMAOMR_DTCEFD_Pos (26U)
AnnaBridge 172:65be27845400 15496 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 15497 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
AnnaBridge 172:65be27845400 15498 #define ETH_DMAOMR_RSF_Pos (25U)
AnnaBridge 172:65be27845400 15499 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15500 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
AnnaBridge 172:65be27845400 15501 #define ETH_DMAOMR_DFRF_Pos (24U)
AnnaBridge 172:65be27845400 15502 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15503 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
AnnaBridge 172:65be27845400 15504 #define ETH_DMAOMR_TSF_Pos (21U)
AnnaBridge 172:65be27845400 15505 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15506 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
AnnaBridge 172:65be27845400 15507 #define ETH_DMAOMR_FTF_Pos (20U)
AnnaBridge 172:65be27845400 15508 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15509 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
AnnaBridge 172:65be27845400 15510 #define ETH_DMAOMR_TTC_Pos (14U)
AnnaBridge 172:65be27845400 15511 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
AnnaBridge 172:65be27845400 15512 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
AnnaBridge 172:65be27845400 15513 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
AnnaBridge 172:65be27845400 15514 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
AnnaBridge 172:65be27845400 15515 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
AnnaBridge 172:65be27845400 15516 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
AnnaBridge 172:65be27845400 15517 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
AnnaBridge 172:65be27845400 15518 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
AnnaBridge 172:65be27845400 15519 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
AnnaBridge 172:65be27845400 15520 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
AnnaBridge 172:65be27845400 15521 #define ETH_DMAOMR_ST_Pos (13U)
AnnaBridge 172:65be27845400 15522 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 15523 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
AnnaBridge 172:65be27845400 15524 #define ETH_DMAOMR_FEF_Pos (7U)
AnnaBridge 172:65be27845400 15525 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15526 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
AnnaBridge 172:65be27845400 15527 #define ETH_DMAOMR_FUGF_Pos (6U)
AnnaBridge 172:65be27845400 15528 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15529 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
AnnaBridge 172:65be27845400 15530 #define ETH_DMAOMR_RTC_Pos (3U)
AnnaBridge 172:65be27845400 15531 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 15532 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
AnnaBridge 172:65be27845400 15533 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
AnnaBridge 172:65be27845400 15534 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
AnnaBridge 172:65be27845400 15535 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
AnnaBridge 172:65be27845400 15536 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
AnnaBridge 172:65be27845400 15537 #define ETH_DMAOMR_OSF_Pos (2U)
AnnaBridge 172:65be27845400 15538 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15539 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
AnnaBridge 172:65be27845400 15540 #define ETH_DMAOMR_SR_Pos (1U)
AnnaBridge 172:65be27845400 15541 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15542 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
AnnaBridge 172:65be27845400 15543
AnnaBridge 172:65be27845400 15544 /* Bit definition for Ethernet DMA Interrupt Enable Register */
AnnaBridge 172:65be27845400 15545 #define ETH_DMAIER_NISE_Pos (16U)
AnnaBridge 172:65be27845400 15546 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15547 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
AnnaBridge 172:65be27845400 15548 #define ETH_DMAIER_AISE_Pos (15U)
AnnaBridge 172:65be27845400 15549 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15550 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
AnnaBridge 172:65be27845400 15551 #define ETH_DMAIER_ERIE_Pos (14U)
AnnaBridge 172:65be27845400 15552 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15553 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
AnnaBridge 172:65be27845400 15554 #define ETH_DMAIER_FBEIE_Pos (13U)
AnnaBridge 172:65be27845400 15555 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 15556 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
AnnaBridge 172:65be27845400 15557 #define ETH_DMAIER_ETIE_Pos (10U)
AnnaBridge 172:65be27845400 15558 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15559 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
AnnaBridge 172:65be27845400 15560 #define ETH_DMAIER_RWTIE_Pos (9U)
AnnaBridge 172:65be27845400 15561 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15562 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
AnnaBridge 172:65be27845400 15563 #define ETH_DMAIER_RPSIE_Pos (8U)
AnnaBridge 172:65be27845400 15564 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15565 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
AnnaBridge 172:65be27845400 15566 #define ETH_DMAIER_RBUIE_Pos (7U)
AnnaBridge 172:65be27845400 15567 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15568 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
AnnaBridge 172:65be27845400 15569 #define ETH_DMAIER_RIE_Pos (6U)
AnnaBridge 172:65be27845400 15570 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15571 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
AnnaBridge 172:65be27845400 15572 #define ETH_DMAIER_TUIE_Pos (5U)
AnnaBridge 172:65be27845400 15573 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15574 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
AnnaBridge 172:65be27845400 15575 #define ETH_DMAIER_ROIE_Pos (4U)
AnnaBridge 172:65be27845400 15576 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15577 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
AnnaBridge 172:65be27845400 15578 #define ETH_DMAIER_TJTIE_Pos (3U)
AnnaBridge 172:65be27845400 15579 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15580 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
AnnaBridge 172:65be27845400 15581 #define ETH_DMAIER_TBUIE_Pos (2U)
AnnaBridge 172:65be27845400 15582 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15583 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
AnnaBridge 172:65be27845400 15584 #define ETH_DMAIER_TPSIE_Pos (1U)
AnnaBridge 172:65be27845400 15585 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15586 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
AnnaBridge 172:65be27845400 15587 #define ETH_DMAIER_TIE_Pos (0U)
AnnaBridge 172:65be27845400 15588 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15589 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
AnnaBridge 172:65be27845400 15590
AnnaBridge 172:65be27845400 15591 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
AnnaBridge 172:65be27845400 15592 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
AnnaBridge 172:65be27845400 15593 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15594 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
AnnaBridge 172:65be27845400 15595 #define ETH_DMAMFBOCR_MFA_Pos (17U)
AnnaBridge 172:65be27845400 15596 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
AnnaBridge 172:65be27845400 15597 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
AnnaBridge 172:65be27845400 15598 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
AnnaBridge 172:65be27845400 15599 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15600 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
AnnaBridge 172:65be27845400 15601 #define ETH_DMAMFBOCR_MFC_Pos (0U)
AnnaBridge 172:65be27845400 15602 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15603 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
AnnaBridge 172:65be27845400 15604
AnnaBridge 172:65be27845400 15605 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
AnnaBridge 172:65be27845400 15606 #define ETH_DMACHTDR_HTDAP_Pos (0U)
AnnaBridge 172:65be27845400 15607 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15608 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
AnnaBridge 172:65be27845400 15609
AnnaBridge 172:65be27845400 15610 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
AnnaBridge 172:65be27845400 15611 #define ETH_DMACHRDR_HRDAP_Pos (0U)
AnnaBridge 172:65be27845400 15612 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15613 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
AnnaBridge 172:65be27845400 15614
AnnaBridge 172:65be27845400 15615 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
AnnaBridge 172:65be27845400 15616 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
AnnaBridge 172:65be27845400 15617 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15618 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
AnnaBridge 172:65be27845400 15619
AnnaBridge 172:65be27845400 15620 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
AnnaBridge 172:65be27845400 15621 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
AnnaBridge 172:65be27845400 15622 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 15623 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
AnnaBridge 172:65be27845400 15624
AnnaBridge 172:65be27845400 15625 /******************************************************************************/
AnnaBridge 172:65be27845400 15626 /* */
AnnaBridge 172:65be27845400 15627 /* USB_OTG */
AnnaBridge 172:65be27845400 15628 /* */
AnnaBridge 172:65be27845400 15629 /******************************************************************************/
AnnaBridge 172:65be27845400 15630 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
AnnaBridge 172:65be27845400 15631 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 172:65be27845400 15632 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15633 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 172:65be27845400 15634 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 172:65be27845400 15635 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15636 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 172:65be27845400 15637 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 172:65be27845400 15638 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15639 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 172:65be27845400 15640 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 172:65be27845400 15641 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15642 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 172:65be27845400 15643 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 172:65be27845400 15644 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15645 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 172:65be27845400 15646 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 172:65be27845400 15647 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15648 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 172:65be27845400 15649 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 172:65be27845400 15650 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15651 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 172:65be27845400 15652 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 172:65be27845400 15653 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15654 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 172:65be27845400 15655 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 172:65be27845400 15656 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15657 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 172:65be27845400 15658 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
AnnaBridge 172:65be27845400 15659 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15660 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
AnnaBridge 172:65be27845400 15661
AnnaBridge 172:65be27845400 15662 /******************** Bit definition forUSB_OTG_HCFG register ********************/
AnnaBridge 172:65be27845400 15663
AnnaBridge 172:65be27845400 15664 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 172:65be27845400 15665 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 15666 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 172:65be27845400 15667 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15668 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15669 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 172:65be27845400 15670 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15671 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 172:65be27845400 15672
AnnaBridge 172:65be27845400 15673 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 172:65be27845400 15674
AnnaBridge 172:65be27845400 15675 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 172:65be27845400 15676 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 15677 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 172:65be27845400 15678 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15679 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15680 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 172:65be27845400 15681 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15682 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 172:65be27845400 15683
AnnaBridge 172:65be27845400 15684 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 172:65be27845400 15685 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 172:65be27845400 15686 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 172:65be27845400 15687 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15688 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15689 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15690 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15691 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15692 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15693 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15694
AnnaBridge 172:65be27845400 15695 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 172:65be27845400 15696 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 15697 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 172:65be27845400 15698 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15699 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15700
AnnaBridge 172:65be27845400 15701 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 172:65be27845400 15702 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 15703 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 172:65be27845400 15704 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15705 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15706
AnnaBridge 172:65be27845400 15707 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 172:65be27845400 15708 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 172:65be27845400 15709 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15710 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 172:65be27845400 15711 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 172:65be27845400 15712 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15713 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 172:65be27845400 15714 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 172:65be27845400 15715 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15716 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 172:65be27845400 15717
AnnaBridge 172:65be27845400 15718 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 172:65be27845400 15719 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 172:65be27845400 15720 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15721 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 172:65be27845400 15722 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 172:65be27845400 15723 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15724 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 172:65be27845400 15725 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 172:65be27845400 15726 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15727 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 172:65be27845400 15728 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 172:65be27845400 15729 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15730 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 172:65be27845400 15731 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 172:65be27845400 15732 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15733 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 172:65be27845400 15734 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 172:65be27845400 15735 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15736 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 172:65be27845400 15737
AnnaBridge 172:65be27845400 15738 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 172:65be27845400 15739 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 172:65be27845400 15740 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15741 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 172:65be27845400 15742 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 172:65be27845400 15743 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15744 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 172:65be27845400 15745 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 172:65be27845400 15746 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15747 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 172:65be27845400 15748 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 172:65be27845400 15749 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15750 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 172:65be27845400 15751
AnnaBridge 172:65be27845400 15752 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 172:65be27845400 15753 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 15754 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 172:65be27845400 15755 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15756 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15757 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15758 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 172:65be27845400 15759 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15760 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 172:65be27845400 15761 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 172:65be27845400 15762 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15763 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 172:65be27845400 15764 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 172:65be27845400 15765 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15766 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 172:65be27845400 15767 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 172:65be27845400 15768 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15769 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 172:65be27845400 15770 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 172:65be27845400 15771 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15772 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 172:65be27845400 15773
AnnaBridge 172:65be27845400 15774 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 172:65be27845400 15775 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 172:65be27845400 15776 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15777 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 172:65be27845400 15778
AnnaBridge 172:65be27845400 15779 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 172:65be27845400 15780 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 172:65be27845400 15781 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15782 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 172:65be27845400 15783 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 172:65be27845400 15784 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 15785 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 172:65be27845400 15786
AnnaBridge 172:65be27845400 15787 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 172:65be27845400 15788 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 172:65be27845400 15789 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15790 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 172:65be27845400 15791
AnnaBridge 172:65be27845400 15792 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 172:65be27845400 15793 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 15794 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 172:65be27845400 15795 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15796 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15797 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 172:65be27845400 15798 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15799 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 172:65be27845400 15800 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 172:65be27845400 15801 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 172:65be27845400 15802 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 172:65be27845400 15803
AnnaBridge 172:65be27845400 15804 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 172:65be27845400 15805 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 172:65be27845400 15806 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15807 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 172:65be27845400 15808 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 172:65be27845400 15809 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 172:65be27845400 15810 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 172:65be27845400 15811 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
AnnaBridge 172:65be27845400 15812 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
AnnaBridge 172:65be27845400 15813 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
AnnaBridge 172:65be27845400 15814 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
AnnaBridge 172:65be27845400 15815 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
AnnaBridge 172:65be27845400 15816 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 172:65be27845400 15817 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15818 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 172:65be27845400 15819 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 172:65be27845400 15820 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15821 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 172:65be27845400 15822 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 172:65be27845400 15823 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15824 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 172:65be27845400 15825
AnnaBridge 172:65be27845400 15826 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 172:65be27845400 15827
AnnaBridge 172:65be27845400 15828 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 172:65be27845400 15829 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 15830 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 172:65be27845400 15831 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15832 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15833 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15834 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 172:65be27845400 15835 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15836 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 172:65be27845400 15837 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 172:65be27845400 15838 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15839 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 172:65be27845400 15840 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 172:65be27845400 15841 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15842 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 172:65be27845400 15843 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 172:65be27845400 15844 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 172:65be27845400 15845 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 172:65be27845400 15846 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15847 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15848 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15849 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 15850 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 172:65be27845400 15851 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15852 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 172:65be27845400 15853 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 172:65be27845400 15854 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15855 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 172:65be27845400 15856 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 172:65be27845400 15857 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15858 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 172:65be27845400 15859 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 172:65be27845400 15860 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15861 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 172:65be27845400 15862 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 172:65be27845400 15863 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15864 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 172:65be27845400 15865 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 172:65be27845400 15866 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15867 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 172:65be27845400 15868 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 172:65be27845400 15869 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 15870 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 172:65be27845400 15871 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 172:65be27845400 15872 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15873 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 172:65be27845400 15874 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 172:65be27845400 15875 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15876 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 172:65be27845400 15877 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 172:65be27845400 15878 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15879 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 172:65be27845400 15880 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 172:65be27845400 15881 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15882 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 172:65be27845400 15883 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 172:65be27845400 15884 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15885 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 172:65be27845400 15886 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 172:65be27845400 15887 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15888 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 172:65be27845400 15889
AnnaBridge 172:65be27845400 15890 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 172:65be27845400 15891 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 172:65be27845400 15892 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15893 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 172:65be27845400 15894 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 172:65be27845400 15895 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15896 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 172:65be27845400 15897 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 172:65be27845400 15898 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15899 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 172:65be27845400 15900 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 172:65be27845400 15901 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15902 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 172:65be27845400 15903 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 172:65be27845400 15904 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15905 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 172:65be27845400 15906
AnnaBridge 172:65be27845400 15907
AnnaBridge 172:65be27845400 15908 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 172:65be27845400 15909 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 15910 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 172:65be27845400 15911 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15912 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15913 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15914 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15915 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15916 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 172:65be27845400 15917 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15918 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 172:65be27845400 15919 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 172:65be27845400 15920 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15921 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 172:65be27845400 15922
AnnaBridge 172:65be27845400 15923 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 172:65be27845400 15924 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 15925 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15926 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 15927 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 15928 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15929 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 15930 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 172:65be27845400 15931 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15932 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 172:65be27845400 15933 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 172:65be27845400 15934 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15935 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 172:65be27845400 15936 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 172:65be27845400 15937 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15938 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 172:65be27845400 15939 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 172:65be27845400 15940 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15941 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 172:65be27845400 15942 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 172:65be27845400 15943 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15944 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 172:65be27845400 15945 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 172:65be27845400 15946 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15947 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 15948
AnnaBridge 172:65be27845400 15949 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 172:65be27845400 15950 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 172:65be27845400 15951 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15952 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 172:65be27845400 15953 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 172:65be27845400 15954 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 15955 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 172:65be27845400 15956 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15957 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15958 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15959 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15960 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15961 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15962 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 15963 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15964
AnnaBridge 172:65be27845400 15965 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 172:65be27845400 15966 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 15967 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 172:65be27845400 15968 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15969 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15970 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 15971 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15972 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15973 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15974 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15975 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15976
AnnaBridge 172:65be27845400 15977 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 172:65be27845400 15978 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 172:65be27845400 15979 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 15980 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 172:65be27845400 15981
AnnaBridge 172:65be27845400 15982 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 172:65be27845400 15983 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 15984 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15985 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 15986 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 15987 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15988 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 15989 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 172:65be27845400 15990 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15991 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 172:65be27845400 15992 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 172:65be27845400 15993 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15994 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 172:65be27845400 15995 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 172:65be27845400 15996 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15997 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 172:65be27845400 15998 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 172:65be27845400 15999 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16000 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 172:65be27845400 16001 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 172:65be27845400 16002 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16003 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 16004
AnnaBridge 172:65be27845400 16005 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 172:65be27845400 16006 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 172:65be27845400 16007 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16008 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 172:65be27845400 16009 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 172:65be27845400 16010 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16011 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 172:65be27845400 16012 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 172:65be27845400 16013 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16014 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 172:65be27845400 16015 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 172:65be27845400 16016 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16017 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 172:65be27845400 16018 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 172:65be27845400 16019 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16020 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 172:65be27845400 16021 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 172:65be27845400 16022 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16023 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 172:65be27845400 16024 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 172:65be27845400 16025 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16026 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 172:65be27845400 16027 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 172:65be27845400 16028 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16029 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 172:65be27845400 16030 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 172:65be27845400 16031 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16032 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 172:65be27845400 16033 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 172:65be27845400 16034 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16035 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 172:65be27845400 16036 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 172:65be27845400 16037 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16038 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 172:65be27845400 16039 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 172:65be27845400 16040 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16041 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 172:65be27845400 16042 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 172:65be27845400 16043 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16044 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 172:65be27845400 16045 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 172:65be27845400 16046 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16047 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 172:65be27845400 16048 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 172:65be27845400 16049 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16050 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 172:65be27845400 16051 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 172:65be27845400 16052 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16053 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 172:65be27845400 16054 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 172:65be27845400 16055 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16056 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 172:65be27845400 16057 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 172:65be27845400 16058 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16059 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 172:65be27845400 16060 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 172:65be27845400 16061 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16062 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 172:65be27845400 16063 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 172:65be27845400 16064 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16065 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 172:65be27845400 16066 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 172:65be27845400 16067 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16068 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 172:65be27845400 16069 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 172:65be27845400 16070 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16071 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 172:65be27845400 16072 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 172:65be27845400 16073 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16074 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 172:65be27845400 16075 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 172:65be27845400 16076 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16077 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 172:65be27845400 16078 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 172:65be27845400 16079 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16080 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 172:65be27845400 16081 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 172:65be27845400 16082 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16083 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 172:65be27845400 16084
AnnaBridge 172:65be27845400 16085 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 172:65be27845400 16086 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 172:65be27845400 16087 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16088 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 172:65be27845400 16089 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 172:65be27845400 16090 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16091 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 172:65be27845400 16092 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 172:65be27845400 16093 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16094 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 172:65be27845400 16095 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 172:65be27845400 16096 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16097 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 172:65be27845400 16098 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 172:65be27845400 16099 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16100 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 172:65be27845400 16101 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 172:65be27845400 16102 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16103 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 172:65be27845400 16104 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 172:65be27845400 16105 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16106 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 172:65be27845400 16107 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 172:65be27845400 16108 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16109 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 172:65be27845400 16110 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 172:65be27845400 16111 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16112 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 172:65be27845400 16113 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 172:65be27845400 16114 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16115 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 172:65be27845400 16116 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 172:65be27845400 16117 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16118 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 172:65be27845400 16119 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 172:65be27845400 16120 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16121 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 172:65be27845400 16122 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 172:65be27845400 16123 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16124 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 172:65be27845400 16125 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 172:65be27845400 16126 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16127 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 172:65be27845400 16128 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 172:65be27845400 16129 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16130 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 172:65be27845400 16131 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 172:65be27845400 16132 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16133 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 172:65be27845400 16134 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 172:65be27845400 16135 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16136 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 172:65be27845400 16137 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 172:65be27845400 16138 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16139 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 172:65be27845400 16140 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 172:65be27845400 16141 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16142 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 172:65be27845400 16143 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 172:65be27845400 16144 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16145 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 172:65be27845400 16146 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 172:65be27845400 16147 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16148 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 172:65be27845400 16149 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 172:65be27845400 16150 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16151 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 172:65be27845400 16152 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 172:65be27845400 16153 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16154 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 172:65be27845400 16155 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 172:65be27845400 16156 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16157 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 172:65be27845400 16158 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 172:65be27845400 16159 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16160 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 172:65be27845400 16161 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 172:65be27845400 16162 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16163 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 172:65be27845400 16164
AnnaBridge 172:65be27845400 16165 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 172:65be27845400 16166 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 172:65be27845400 16167 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16168 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 172:65be27845400 16169 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 172:65be27845400 16170 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 16171 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 172:65be27845400 16172
AnnaBridge 172:65be27845400 16173 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 172:65be27845400 16174 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 172:65be27845400 16175 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16176 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
AnnaBridge 172:65be27845400 16177
AnnaBridge 172:65be27845400 16178 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 172:65be27845400 16179 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 172:65be27845400 16180 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16181 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 172:65be27845400 16182 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 172:65be27845400 16183 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 172:65be27845400 16184 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 16185 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 172:65be27845400 16186 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 172:65be27845400 16187 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 16188 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 172:65be27845400 16189 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 172:65be27845400 16190 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 16191
AnnaBridge 172:65be27845400 16192 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 172:65be27845400 16193 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 172:65be27845400 16194 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16195 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 172:65be27845400 16196 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 172:65be27845400 16197 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 16198 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 16199
AnnaBridge 172:65be27845400 16200 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 172:65be27845400 16201 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 172:65be27845400 16202 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16203 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 172:65be27845400 16204
AnnaBridge 172:65be27845400 16205 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 172:65be27845400 16206 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 172:65be27845400 16207 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16208 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
AnnaBridge 172:65be27845400 16209
AnnaBridge 172:65be27845400 16210 /******************** Bit definition for OTG register ********************/
AnnaBridge 172:65be27845400 16211 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 172:65be27845400 16212 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16213 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 172:65be27845400 16214 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 172:65be27845400 16215 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 16216 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 172:65be27845400 16217 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 172:65be27845400 16218 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16219 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 172:65be27845400 16220 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 172:65be27845400 16221 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 16222 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
AnnaBridge 172:65be27845400 16223
AnnaBridge 172:65be27845400 16224 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
AnnaBridge 172:65be27845400 16225 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 172:65be27845400 16226 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 16227 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 172:65be27845400 16228
AnnaBridge 172:65be27845400 16229 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 172:65be27845400 16230 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 172:65be27845400 16231 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16232 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 172:65be27845400 16233
AnnaBridge 172:65be27845400 16234 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 172:65be27845400 16235 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 16236 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 172:65be27845400 16237 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16238 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16239 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16240 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16241 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16242 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16243 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16244 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16245
AnnaBridge 172:65be27845400 16246 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 172:65be27845400 16247 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 172:65be27845400 16248 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 172:65be27845400 16249 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16250 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16251 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16252 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16253 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16254 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16255 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16256
AnnaBridge 172:65be27845400 16257 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 172:65be27845400 16258 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 172:65be27845400 16259 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16260 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 172:65be27845400 16261 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 172:65be27845400 16262 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16263 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 172:65be27845400 16264
AnnaBridge 172:65be27845400 16265 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 172:65be27845400 16266 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 172:65be27845400 16267 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 172:65be27845400 16268 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16269 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16270 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16271 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16272 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16273 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16274 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16275 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16276 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16277 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 172:65be27845400 16278 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16279 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 172:65be27845400 16280
AnnaBridge 172:65be27845400 16281 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 172:65be27845400 16282 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 172:65be27845400 16283 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 172:65be27845400 16284 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16285 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16286 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16287 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16288 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16289 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16290 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16291 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16292 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16293 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 172:65be27845400 16294 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16295 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 172:65be27845400 16296
AnnaBridge 172:65be27845400 16297 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 172:65be27845400 16298 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 172:65be27845400 16299 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16300 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 172:65be27845400 16301
AnnaBridge 172:65be27845400 16302 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 172:65be27845400 16303 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 172:65be27845400 16304 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16305 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 172:65be27845400 16306 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 172:65be27845400 16307 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16308 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 172:65be27845400 16309
AnnaBridge 172:65be27845400 16310 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 172:65be27845400 16311 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 172:65be27845400 16312 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16313 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 172:65be27845400 16314 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
AnnaBridge 172:65be27845400 16315 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16316 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
AnnaBridge 172:65be27845400 16317 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
AnnaBridge 172:65be27845400 16318 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16319 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 172:65be27845400 16320 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
AnnaBridge 172:65be27845400 16321 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16322 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 172:65be27845400 16323 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
AnnaBridge 172:65be27845400 16324 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16325 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
AnnaBridge 172:65be27845400 16326 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
AnnaBridge 172:65be27845400 16327 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16328 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
AnnaBridge 172:65be27845400 16329
AnnaBridge 172:65be27845400 16330 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
AnnaBridge 172:65be27845400 16331 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 172:65be27845400 16332 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16333 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 172:65be27845400 16334 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 172:65be27845400 16335 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16336 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 172:65be27845400 16337
AnnaBridge 172:65be27845400 16338 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 172:65be27845400 16339 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 172:65be27845400 16340 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16341 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 172:65be27845400 16342
AnnaBridge 172:65be27845400 16343 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 172:65be27845400 16344 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 16345 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16346 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 16347 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 16348 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16349 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 16350 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 172:65be27845400 16351 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16352 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 172:65be27845400 16353 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 172:65be27845400 16354 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16355 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 172:65be27845400 16356 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 172:65be27845400 16357 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16358 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 172:65be27845400 16359 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 172:65be27845400 16360 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16361 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 172:65be27845400 16362 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 172:65be27845400 16363 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16364 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 172:65be27845400 16365 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 172:65be27845400 16366 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16367 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 16368 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 172:65be27845400 16369 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16370 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 172:65be27845400 16371
AnnaBridge 172:65be27845400 16372 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 172:65be27845400 16373 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 172:65be27845400 16374 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16375 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 172:65be27845400 16376 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 172:65be27845400 16377 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16378 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 172:65be27845400 16379 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 172:65be27845400 16380 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16381 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 172:65be27845400 16382 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 172:65be27845400 16383 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16384 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 172:65be27845400 16385 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 172:65be27845400 16386 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16387 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 172:65be27845400 16388 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 172:65be27845400 16389 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16390 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 172:65be27845400 16391 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 172:65be27845400 16392 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16393 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 172:65be27845400 16394 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 172:65be27845400 16395 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16396 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 172:65be27845400 16397 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 172:65be27845400 16398 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16399 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 172:65be27845400 16400
AnnaBridge 172:65be27845400 16401 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 172:65be27845400 16402 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 16403 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 172:65be27845400 16404 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16405 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16406 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 172:65be27845400 16407 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16408 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 172:65be27845400 16409
AnnaBridge 172:65be27845400 16410 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 172:65be27845400 16411 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 16412 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 172:65be27845400 16413 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16414 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16415 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16416 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16417
AnnaBridge 172:65be27845400 16418 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 172:65be27845400 16419 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 16420 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 172:65be27845400 16421 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16422 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16423
AnnaBridge 172:65be27845400 16424 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 172:65be27845400 16425 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 16426 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16427 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 16428 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 16429 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16430 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 16431 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 172:65be27845400 16432 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16433 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 172:65be27845400 16434 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 172:65be27845400 16435 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16436 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 172:65be27845400 16437 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 172:65be27845400 16438 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16439 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 172:65be27845400 16440 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 172:65be27845400 16441 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16442 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 172:65be27845400 16443 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 172:65be27845400 16444 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16445 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 172:65be27845400 16446 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 172:65be27845400 16447 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16448 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 16449 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 172:65be27845400 16450 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16451 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 172:65be27845400 16452 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 172:65be27845400 16453 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16454 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 172:65be27845400 16455 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 172:65be27845400 16456 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16457 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 172:65be27845400 16458
AnnaBridge 172:65be27845400 16459 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 172:65be27845400 16460 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 172:65be27845400 16461 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16462 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 172:65be27845400 16463 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 172:65be27845400 16464 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 16465 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 172:65be27845400 16466
AnnaBridge 172:65be27845400 16467 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 172:65be27845400 16468 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 172:65be27845400 16469 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 16470 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 172:65be27845400 16471 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 172:65be27845400 16472 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16473 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 172:65be27845400 16474 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 172:65be27845400 16475 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16476 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 172:65be27845400 16477 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 172:65be27845400 16478 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16479 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 172:65be27845400 16480
AnnaBridge 172:65be27845400 16481 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 172:65be27845400 16482 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 16483 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 172:65be27845400 16484 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16485 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16486 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 172:65be27845400 16487 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16488 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 172:65be27845400 16489
AnnaBridge 172:65be27845400 16490 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 172:65be27845400 16491 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 172:65be27845400 16492 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 172:65be27845400 16493 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16494 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16495 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16496 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16497 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 172:65be27845400 16498 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16499 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 172:65be27845400 16500 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 172:65be27845400 16501 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16502 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 172:65be27845400 16503 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 172:65be27845400 16504 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16505 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 172:65be27845400 16506 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 172:65be27845400 16507 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16508 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 172:65be27845400 16509 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 172:65be27845400 16510 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16511 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 172:65be27845400 16512 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 172:65be27845400 16513 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16514 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 172:65be27845400 16515
AnnaBridge 172:65be27845400 16516 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 172:65be27845400 16517 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 172:65be27845400 16518 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 16519 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 172:65be27845400 16520
AnnaBridge 172:65be27845400 16521 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 172:65be27845400 16522 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 172:65be27845400 16523 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 172:65be27845400 16524 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16525 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16526 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16527 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16528 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 172:65be27845400 16529 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16530 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 172:65be27845400 16531 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 172:65be27845400 16532 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16533 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 172:65be27845400 16534
AnnaBridge 172:65be27845400 16535 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 172:65be27845400 16536 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 16537 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 172:65be27845400 16538 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16539 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16540
AnnaBridge 172:65be27845400 16541 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 172:65be27845400 16542 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 16543 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 172:65be27845400 16544 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16545 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16546
AnnaBridge 172:65be27845400 16547 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 172:65be27845400 16548 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 172:65be27845400 16549 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 172:65be27845400 16550 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16551 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16552 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16553 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16554 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16555 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16556 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16557 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 172:65be27845400 16558 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16559 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 172:65be27845400 16560 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 172:65be27845400 16561 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16562 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 172:65be27845400 16563 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 172:65be27845400 16564 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16565 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 172:65be27845400 16566
AnnaBridge 172:65be27845400 16567 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 172:65be27845400 16568
AnnaBridge 172:65be27845400 16569 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 172:65be27845400 16570 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 16571 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 172:65be27845400 16572 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16573 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16574 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16575 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16576 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16577 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16578 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16579
AnnaBridge 172:65be27845400 16580 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 172:65be27845400 16581 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 172:65be27845400 16582 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 172:65be27845400 16583 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16584 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16585 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16586 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16587 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16588 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16589 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16590
AnnaBridge 172:65be27845400 16591 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 172:65be27845400 16592 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 16593 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 172:65be27845400 16594 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16595 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16596 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 172:65be27845400 16597 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16598 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 172:65be27845400 16599 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 172:65be27845400 16600 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16601 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 172:65be27845400 16602
AnnaBridge 172:65be27845400 16603 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 172:65be27845400 16604 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 172:65be27845400 16605 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16606 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 172:65be27845400 16607 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 172:65be27845400 16608 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16609 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 172:65be27845400 16610 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 172:65be27845400 16611 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16612 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 172:65be27845400 16613 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 172:65be27845400 16614 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16615 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 172:65be27845400 16616 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 172:65be27845400 16617 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16618 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 172:65be27845400 16619 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 172:65be27845400 16620 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16621 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 172:65be27845400 16622 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 172:65be27845400 16623 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16624 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 172:65be27845400 16625 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 172:65be27845400 16626 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16627 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 172:65be27845400 16628 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 172:65be27845400 16629 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16630 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 172:65be27845400 16631 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 172:65be27845400 16632 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16633 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 172:65be27845400 16634 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 172:65be27845400 16635 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16636 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 172:65be27845400 16637
AnnaBridge 172:65be27845400 16638 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 172:65be27845400 16639 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 172:65be27845400 16640 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16641 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 172:65be27845400 16642 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 172:65be27845400 16643 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16644 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 172:65be27845400 16645 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 172:65be27845400 16646 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16647 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 172:65be27845400 16648 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 172:65be27845400 16649 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16650 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 172:65be27845400 16651 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 172:65be27845400 16652 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16653 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 172:65be27845400 16654 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 172:65be27845400 16655 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16656 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 172:65be27845400 16657 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 172:65be27845400 16658 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16659 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 172:65be27845400 16660 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 172:65be27845400 16661 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16662 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 172:65be27845400 16663 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 172:65be27845400 16664 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16665 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 172:65be27845400 16666 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 172:65be27845400 16667 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16668 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 172:65be27845400 16669 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 172:65be27845400 16670 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16671 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
AnnaBridge 172:65be27845400 16672
AnnaBridge 172:65be27845400 16673 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
AnnaBridge 172:65be27845400 16674 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 16675 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16676 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 172:65be27845400 16677 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 172:65be27845400 16678 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16679 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 172:65be27845400 16680 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 172:65be27845400 16681 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16682 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 172:65be27845400 16683 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 172:65be27845400 16684 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16685 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 172:65be27845400 16686 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 172:65be27845400 16687 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16688 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 172:65be27845400 16689 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 172:65be27845400 16690 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16691 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 172:65be27845400 16692 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 172:65be27845400 16693 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16694 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 172:65be27845400 16695 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 172:65be27845400 16696 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16697 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 172:65be27845400 16698 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 172:65be27845400 16699 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16700 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 172:65be27845400 16701 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 172:65be27845400 16702 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16703 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 172:65be27845400 16704 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 172:65be27845400 16705 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16706 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
AnnaBridge 172:65be27845400 16707
AnnaBridge 172:65be27845400 16708 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
AnnaBridge 172:65be27845400 16709
AnnaBridge 172:65be27845400 16710 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 172:65be27845400 16711 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 172:65be27845400 16712 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 172:65be27845400 16713 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 172:65be27845400 16714 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 172:65be27845400 16715 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 16716 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 172:65be27845400 16717 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 172:65be27845400 16718 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 16719 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 172:65be27845400 16720 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 172:65be27845400 16721 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 172:65be27845400 16722 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 172:65be27845400 16723 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 172:65be27845400 16724 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 172:65be27845400 16725 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 16726 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 172:65be27845400 16727 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16728 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 172:65be27845400 16729 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 172:65be27845400 16730 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 172:65be27845400 16731 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 172:65be27845400 16732 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16733 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16734
AnnaBridge 172:65be27845400 16735 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 172:65be27845400 16736 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 172:65be27845400 16737 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16738 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 172:65be27845400 16739
AnnaBridge 172:65be27845400 16740 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 172:65be27845400 16741 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 172:65be27845400 16742 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16743 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 172:65be27845400 16744
AnnaBridge 172:65be27845400 16745 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 172:65be27845400 16746 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 172:65be27845400 16747 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16748 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 172:65be27845400 16749
AnnaBridge 172:65be27845400 16750 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 172:65be27845400 16751 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 172:65be27845400 16752 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16753 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 172:65be27845400 16754 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 172:65be27845400 16755 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 16756 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 172:65be27845400 16757
AnnaBridge 172:65be27845400 16758 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 172:65be27845400 16759
AnnaBridge 172:65be27845400 16760 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 172:65be27845400 16761 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 16762 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 172:65be27845400 16763 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 172:65be27845400 16764 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16765 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 172:65be27845400 16766 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 172:65be27845400 16767 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16768 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 172:65be27845400 16769 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 172:65be27845400 16770 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16771 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 172:65be27845400 16772 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 172:65be27845400 16773 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16774 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 172:65be27845400 16775 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 172:65be27845400 16776 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 16777 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 172:65be27845400 16778 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16779 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16780 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 172:65be27845400 16781 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16782 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 172:65be27845400 16783 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 172:65be27845400 16784 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16785 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 172:65be27845400 16786 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 172:65be27845400 16787 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16788 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 172:65be27845400 16789 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 172:65be27845400 16790 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16791 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 172:65be27845400 16792 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 172:65be27845400 16793 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16794 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 172:65be27845400 16795 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 172:65be27845400 16796 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16797 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 172:65be27845400 16798
AnnaBridge 172:65be27845400 16799 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 172:65be27845400 16800 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 172:65be27845400 16801 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16802 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 172:65be27845400 16803 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 172:65be27845400 16804 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16805 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 172:65be27845400 16806 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 172:65be27845400 16807 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16808 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 172:65be27845400 16809 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 172:65be27845400 16810 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16811 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 172:65be27845400 16812 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 172:65be27845400 16813 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16814 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 172:65be27845400 16815 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 172:65be27845400 16816 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16817 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 172:65be27845400 16818
AnnaBridge 172:65be27845400 16819 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 172:65be27845400 16820
AnnaBridge 172:65be27845400 16821 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 172:65be27845400 16822 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 172:65be27845400 16823 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 172:65be27845400 16824 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 172:65be27845400 16825 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 172:65be27845400 16826 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 16827
AnnaBridge 172:65be27845400 16828 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 172:65be27845400 16829 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 172:65be27845400 16830 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 172:65be27845400 16831 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16832 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16833
AnnaBridge 172:65be27845400 16834 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 172:65be27845400 16835 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 172:65be27845400 16836 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16837 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 172:65be27845400 16838 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 172:65be27845400 16839 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16840 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 172:65be27845400 16841 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 172:65be27845400 16842 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16843 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
AnnaBridge 172:65be27845400 16844
AnnaBridge 172:65be27845400 16845 /* Legacy define */
AnnaBridge 172:65be27845400 16846 /******************** Bit definition for OTG register ********************/
AnnaBridge 172:65be27845400 16847 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 172:65be27845400 16848 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16849 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 172:65be27845400 16850 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16851 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16852 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16853 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16854 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 172:65be27845400 16855 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 172:65be27845400 16856 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 172:65be27845400 16857
AnnaBridge 172:65be27845400 16858 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 172:65be27845400 16859 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 172:65be27845400 16860 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 172:65be27845400 16861 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16862 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16863
AnnaBridge 172:65be27845400 16864 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 172:65be27845400 16865 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 172:65be27845400 16866 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 172:65be27845400 16867 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16868 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16869 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16870 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16871
AnnaBridge 172:65be27845400 16872 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 172:65be27845400 16873 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16874 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 172:65be27845400 16875 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16876 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16877 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16878 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16879
AnnaBridge 172:65be27845400 16880 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 172:65be27845400 16881 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 172:65be27845400 16882 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 172:65be27845400 16883 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16884 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16885 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16886 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16887 /**
AnnaBridge 172:65be27845400 16888 * @}
AnnaBridge 172:65be27845400 16889 */
AnnaBridge 172:65be27845400 16890
AnnaBridge 172:65be27845400 16891 /**
AnnaBridge 172:65be27845400 16892 * @}
AnnaBridge 172:65be27845400 16893 */
AnnaBridge 172:65be27845400 16894
AnnaBridge 172:65be27845400 16895 /** @addtogroup Exported_macros
AnnaBridge 172:65be27845400 16896 * @{
AnnaBridge 172:65be27845400 16897 */
AnnaBridge 172:65be27845400 16898
AnnaBridge 172:65be27845400 16899 /******************************* ADC Instances ********************************/
AnnaBridge 172:65be27845400 16900 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
AnnaBridge 172:65be27845400 16901 ((INSTANCE) == ADC2) || \
AnnaBridge 172:65be27845400 16902 ((INSTANCE) == ADC3))
AnnaBridge 172:65be27845400 16903
AnnaBridge 172:65be27845400 16904 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 172:65be27845400 16905
AnnaBridge 172:65be27845400 16906 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
AnnaBridge 172:65be27845400 16907
AnnaBridge 172:65be27845400 16908 /******************************* CAN Instances ********************************/
AnnaBridge 172:65be27845400 16909 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
AnnaBridge 172:65be27845400 16910 ((INSTANCE) == CAN2))
AnnaBridge 172:65be27845400 16911 /******************************* CRC Instances ********************************/
AnnaBridge 172:65be27845400 16912 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 172:65be27845400 16913
AnnaBridge 172:65be27845400 16914 /******************************* DAC Instances ********************************/
AnnaBridge 172:65be27845400 16915 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
AnnaBridge 172:65be27845400 16916
AnnaBridge 172:65be27845400 16917 /******************************* DCMI Instances *******************************/
AnnaBridge 172:65be27845400 16918 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
AnnaBridge 172:65be27845400 16919
AnnaBridge 172:65be27845400 16920 /******************************* DMA2D Instances *******************************/
AnnaBridge 172:65be27845400 16921 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
AnnaBridge 172:65be27845400 16922
AnnaBridge 172:65be27845400 16923 /******************************** DMA Instances *******************************/
AnnaBridge 172:65be27845400 16924 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 172:65be27845400 16925 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 172:65be27845400 16926 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 172:65be27845400 16927 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 172:65be27845400 16928 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 172:65be27845400 16929 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 172:65be27845400 16930 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 172:65be27845400 16931 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 172:65be27845400 16932 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 172:65be27845400 16933 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 172:65be27845400 16934 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 172:65be27845400 16935 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 172:65be27845400 16936 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 172:65be27845400 16937 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 172:65be27845400 16938 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 172:65be27845400 16939 ((INSTANCE) == DMA2_Stream7))
AnnaBridge 172:65be27845400 16940
AnnaBridge 172:65be27845400 16941 /******************************* GPIO Instances *******************************/
AnnaBridge 172:65be27845400 16942 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 172:65be27845400 16943 ((INSTANCE) == GPIOB) || \
AnnaBridge 172:65be27845400 16944 ((INSTANCE) == GPIOC) || \
AnnaBridge 172:65be27845400 16945 ((INSTANCE) == GPIOD) || \
AnnaBridge 172:65be27845400 16946 ((INSTANCE) == GPIOE) || \
AnnaBridge 172:65be27845400 16947 ((INSTANCE) == GPIOF) || \
AnnaBridge 172:65be27845400 16948 ((INSTANCE) == GPIOG) || \
AnnaBridge 172:65be27845400 16949 ((INSTANCE) == GPIOH) || \
AnnaBridge 172:65be27845400 16950 ((INSTANCE) == GPIOI) || \
AnnaBridge 172:65be27845400 16951 ((INSTANCE) == GPIOJ) || \
AnnaBridge 172:65be27845400 16952 ((INSTANCE) == GPIOK))
AnnaBridge 172:65be27845400 16953
AnnaBridge 172:65be27845400 16954 /******************************** I2C Instances *******************************/
AnnaBridge 172:65be27845400 16955 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 172:65be27845400 16956 ((INSTANCE) == I2C2) || \
AnnaBridge 172:65be27845400 16957 ((INSTANCE) == I2C3))
AnnaBridge 172:65be27845400 16958
AnnaBridge 172:65be27845400 16959 /******************************* SMBUS Instances ******************************/
AnnaBridge 172:65be27845400 16960 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
AnnaBridge 172:65be27845400 16961
AnnaBridge 172:65be27845400 16962 /******************************** I2S Instances *******************************/
AnnaBridge 172:65be27845400 16963
AnnaBridge 172:65be27845400 16964 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
AnnaBridge 172:65be27845400 16965 ((INSTANCE) == SPI3))
AnnaBridge 172:65be27845400 16966
AnnaBridge 172:65be27845400 16967 /*************************** I2S Extended Instances ***************************/
AnnaBridge 172:65be27845400 16968 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
AnnaBridge 172:65be27845400 16969 ((INSTANCE) == I2S3ext))
AnnaBridge 172:65be27845400 16970 /* Legacy Defines */
AnnaBridge 172:65be27845400 16971 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
AnnaBridge 172:65be27845400 16972
AnnaBridge 172:65be27845400 16973 /****************************** LTDC Instances ********************************/
AnnaBridge 172:65be27845400 16974 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
AnnaBridge 172:65be27845400 16975 /******************************* RNG Instances ********************************/
AnnaBridge 172:65be27845400 16976 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
AnnaBridge 172:65be27845400 16977
AnnaBridge 172:65be27845400 16978 /****************************** RTC Instances *********************************/
AnnaBridge 172:65be27845400 16979 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 172:65be27845400 16980
AnnaBridge 172:65be27845400 16981 /******************************* SAI Instances ********************************/
AnnaBridge 172:65be27845400 16982 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
AnnaBridge 172:65be27845400 16983 ((PERIPH) == SAI1_Block_B))
AnnaBridge 172:65be27845400 16984 /* Legacy define */
AnnaBridge 172:65be27845400 16985
AnnaBridge 172:65be27845400 16986 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
AnnaBridge 172:65be27845400 16987
AnnaBridge 172:65be27845400 16988 /******************************** SPI Instances *******************************/
AnnaBridge 172:65be27845400 16989 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 172:65be27845400 16990 ((INSTANCE) == SPI2) || \
AnnaBridge 172:65be27845400 16991 ((INSTANCE) == SPI3) || \
AnnaBridge 172:65be27845400 16992 ((INSTANCE) == SPI4) || \
AnnaBridge 172:65be27845400 16993 ((INSTANCE) == SPI5) || \
AnnaBridge 172:65be27845400 16994 ((INSTANCE) == SPI6))
AnnaBridge 172:65be27845400 16995
AnnaBridge 172:65be27845400 16996
AnnaBridge 172:65be27845400 16997 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 172:65be27845400 16998 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 16999 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17000 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17001 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17002 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17003 ((INSTANCE) == TIM6) || \
AnnaBridge 172:65be27845400 17004 ((INSTANCE) == TIM7) || \
AnnaBridge 172:65be27845400 17005 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 17006 ((INSTANCE) == TIM9) || \
AnnaBridge 172:65be27845400 17007 ((INSTANCE) == TIM10)|| \
AnnaBridge 172:65be27845400 17008 ((INSTANCE) == TIM11)|| \
AnnaBridge 172:65be27845400 17009 ((INSTANCE) == TIM12)|| \
AnnaBridge 172:65be27845400 17010 ((INSTANCE) == TIM13)|| \
AnnaBridge 172:65be27845400 17011 ((INSTANCE) == TIM14))
AnnaBridge 172:65be27845400 17012
AnnaBridge 172:65be27845400 17013 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 172:65be27845400 17014 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17015 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17016 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17017 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17018 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17019 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 17020 ((INSTANCE) == TIM9) || \
AnnaBridge 172:65be27845400 17021 ((INSTANCE) == TIM10) || \
AnnaBridge 172:65be27845400 17022 ((INSTANCE) == TIM11) || \
AnnaBridge 172:65be27845400 17023 ((INSTANCE) == TIM12) || \
AnnaBridge 172:65be27845400 17024 ((INSTANCE) == TIM13) || \
AnnaBridge 172:65be27845400 17025 ((INSTANCE) == TIM14))
AnnaBridge 172:65be27845400 17026
AnnaBridge 172:65be27845400 17027 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 172:65be27845400 17028 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17029 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17030 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17031 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17032 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17033 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 17034 ((INSTANCE) == TIM9) || \
AnnaBridge 172:65be27845400 17035 ((INSTANCE) == TIM12))
AnnaBridge 172:65be27845400 17036
AnnaBridge 172:65be27845400 17037 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 172:65be27845400 17038 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17039 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17040 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17041 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17042 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17043 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17044
AnnaBridge 172:65be27845400 17045 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 172:65be27845400 17046 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17047 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17048 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17049 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17050 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17051 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17052
AnnaBridge 172:65be27845400 17053 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 172:65be27845400 17054 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17055 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17056
AnnaBridge 172:65be27845400 17057 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 172:65be27845400 17058 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17059 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17060 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17061 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17062 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17063 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17064
AnnaBridge 172:65be27845400 17065 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 172:65be27845400 17066 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17067 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17068 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17069 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17070 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17071 ((INSTANCE) == TIM6) || \
AnnaBridge 172:65be27845400 17072 ((INSTANCE) == TIM7) || \
AnnaBridge 172:65be27845400 17073 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17074
AnnaBridge 172:65be27845400 17075 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 172:65be27845400 17076 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17077 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17078 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17079 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17080 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17081 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17082
AnnaBridge 172:65be27845400 17083 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 172:65be27845400 17084 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17085 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17086 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17087 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17088 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17089 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17090
AnnaBridge 172:65be27845400 17091 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 172:65be27845400 17092 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17093 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17094 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17095 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17096 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17097 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17098
AnnaBridge 172:65be27845400 17099 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 172:65be27845400 17100 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17101 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17102 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17103 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17104 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17105 ((INSTANCE) == TIM6) || \
AnnaBridge 172:65be27845400 17106 ((INSTANCE) == TIM7) || \
AnnaBridge 172:65be27845400 17107 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17108
AnnaBridge 172:65be27845400 17109 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
AnnaBridge 172:65be27845400 17110 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17111 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17112 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17113 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17114 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17115 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 17116 ((INSTANCE) == TIM9) || \
AnnaBridge 172:65be27845400 17117 ((INSTANCE) == TIM12))
AnnaBridge 172:65be27845400 17118
AnnaBridge 172:65be27845400 17119 /********************** TIM Instances : 32 bit Counter ************************/
AnnaBridge 172:65be27845400 17120 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17121 ((INSTANCE) == TIM5))
AnnaBridge 172:65be27845400 17122
AnnaBridge 172:65be27845400 17123 /***************** TIM Instances : external trigger input availabe ************/
AnnaBridge 172:65be27845400 17124 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17125 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17126 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17127 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17128 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17129 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17130
AnnaBridge 172:65be27845400 17131 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 172:65be27845400 17132 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17133 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17134 ((INSTANCE) == TIM11))
AnnaBridge 172:65be27845400 17135
AnnaBridge 172:65be27845400 17136 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 172:65be27845400 17137 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 172:65be27845400 17138 ((((INSTANCE) == TIM1) && \
AnnaBridge 172:65be27845400 17139 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17140 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17141 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 17142 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 17143 || \
AnnaBridge 172:65be27845400 17144 (((INSTANCE) == TIM2) && \
AnnaBridge 172:65be27845400 17145 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17146 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17147 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 17148 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 17149 || \
AnnaBridge 172:65be27845400 17150 (((INSTANCE) == TIM3) && \
AnnaBridge 172:65be27845400 17151 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17152 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17153 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 17154 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 17155 || \
AnnaBridge 172:65be27845400 17156 (((INSTANCE) == TIM4) && \
AnnaBridge 172:65be27845400 17157 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17158 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17159 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 17160 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 17161 || \
AnnaBridge 172:65be27845400 17162 (((INSTANCE) == TIM5) && \
AnnaBridge 172:65be27845400 17163 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17164 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17165 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 17166 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 17167 || \
AnnaBridge 172:65be27845400 17168 (((INSTANCE) == TIM8) && \
AnnaBridge 172:65be27845400 17169 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17170 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17171 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 17172 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 17173 || \
AnnaBridge 172:65be27845400 17174 (((INSTANCE) == TIM9) && \
AnnaBridge 172:65be27845400 17175 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17176 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 172:65be27845400 17177 || \
AnnaBridge 172:65be27845400 17178 (((INSTANCE) == TIM10) && \
AnnaBridge 172:65be27845400 17179 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 172:65be27845400 17180 || \
AnnaBridge 172:65be27845400 17181 (((INSTANCE) == TIM11) && \
AnnaBridge 172:65be27845400 17182 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 172:65be27845400 17183 || \
AnnaBridge 172:65be27845400 17184 (((INSTANCE) == TIM12) && \
AnnaBridge 172:65be27845400 17185 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17186 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 172:65be27845400 17187 || \
AnnaBridge 172:65be27845400 17188 (((INSTANCE) == TIM13) && \
AnnaBridge 172:65be27845400 17189 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 172:65be27845400 17190 || \
AnnaBridge 172:65be27845400 17191 (((INSTANCE) == TIM14) && \
AnnaBridge 172:65be27845400 17192 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 172:65be27845400 17193
AnnaBridge 172:65be27845400 17194 /************ TIM Instances : complementary output(s) available ***************/
AnnaBridge 172:65be27845400 17195 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 172:65be27845400 17196 ((((INSTANCE) == TIM1) && \
AnnaBridge 172:65be27845400 17197 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17198 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17199 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 172:65be27845400 17200 || \
AnnaBridge 172:65be27845400 17201 (((INSTANCE) == TIM8) && \
AnnaBridge 172:65be27845400 17202 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 17203 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 17204 ((CHANNEL) == TIM_CHANNEL_3))))
AnnaBridge 172:65be27845400 17205
AnnaBridge 172:65be27845400 17206 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 172:65be27845400 17207 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17208 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17209 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17210 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17211 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17212 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17213
AnnaBridge 172:65be27845400 17214 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 172:65be27845400 17215 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17216 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17217 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17218 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17219 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17220 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 17221 ((INSTANCE) == TIM9) || \
AnnaBridge 172:65be27845400 17222 ((INSTANCE) == TIM10)|| \
AnnaBridge 172:65be27845400 17223 ((INSTANCE) == TIM11)|| \
AnnaBridge 172:65be27845400 17224 ((INSTANCE) == TIM12)|| \
AnnaBridge 172:65be27845400 17225 ((INSTANCE) == TIM13)|| \
AnnaBridge 172:65be27845400 17226 ((INSTANCE) == TIM14))
AnnaBridge 172:65be27845400 17227
AnnaBridge 172:65be27845400 17228 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 172:65be27845400 17229 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
AnnaBridge 172:65be27845400 17230 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17231
AnnaBridge 172:65be27845400 17232
AnnaBridge 172:65be27845400 17233 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 172:65be27845400 17234 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17235 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17236 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17237 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17238 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17239 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17240
AnnaBridge 172:65be27845400 17241 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 172:65be27845400 17242 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17243 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17244 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17245 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17246 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17247 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 17248 ((INSTANCE) == TIM9) || \
AnnaBridge 172:65be27845400 17249 ((INSTANCE) == TIM12))
AnnaBridge 172:65be27845400 17250
AnnaBridge 172:65be27845400 17251 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 172:65be27845400 17252 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17253 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17254 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17255 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17256 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17257 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17258
AnnaBridge 172:65be27845400 17259 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 172:65be27845400 17260 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17261 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17262
AnnaBridge 172:65be27845400 17263 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 172:65be27845400 17264 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17265 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17266 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17267 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17268 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17269 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 17270 ((INSTANCE) == TIM9) || \
AnnaBridge 172:65be27845400 17271 ((INSTANCE) == TIM12))
AnnaBridge 172:65be27845400 17272 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 172:65be27845400 17273 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17274 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 17275 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 17276 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 17277 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 17278 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17279 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 172:65be27845400 17280 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 17281 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 17282
AnnaBridge 172:65be27845400 17283 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 172:65be27845400 17284 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 17285 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 17286 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 17287 ((INSTANCE) == USART6))
AnnaBridge 172:65be27845400 17288
AnnaBridge 172:65be27845400 17289 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 172:65be27845400 17290 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 17291 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 17292 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 17293 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 17294 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 17295 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 17296 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 17297 ((INSTANCE) == UART8))
AnnaBridge 172:65be27845400 17298
AnnaBridge 172:65be27845400 17299 /* Legacy defines */
AnnaBridge 172:65be27845400 17300 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 172:65be27845400 17301
AnnaBridge 172:65be27845400 17302 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 172:65be27845400 17303 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 17304 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 17305 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 17306 ((INSTANCE) == USART6))
AnnaBridge 172:65be27845400 17307 /******************** UART Instances : LIN mode **********************/
AnnaBridge 172:65be27845400 17308 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 172:65be27845400 17309
AnnaBridge 172:65be27845400 17310 /********************* UART Instances : Smart card mode ***********************/
AnnaBridge 172:65be27845400 17311 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 17312 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 17313 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 17314 ((INSTANCE) == USART6))
AnnaBridge 172:65be27845400 17315
AnnaBridge 172:65be27845400 17316 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 172:65be27845400 17317 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 17318 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 17319 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 17320 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 17321 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 17322 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 17323 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 17324 ((INSTANCE) == UART8))
AnnaBridge 172:65be27845400 17325
AnnaBridge 172:65be27845400 17326 /*********************** PCD Instances ****************************************/
AnnaBridge 172:65be27845400 17327 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
AnnaBridge 172:65be27845400 17328 ((INSTANCE) == USB_OTG_HS))
AnnaBridge 172:65be27845400 17329
AnnaBridge 172:65be27845400 17330 /*********************** HCD Instances ****************************************/
AnnaBridge 172:65be27845400 17331 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
AnnaBridge 172:65be27845400 17332 ((INSTANCE) == USB_OTG_HS))
AnnaBridge 172:65be27845400 17333
AnnaBridge 172:65be27845400 17334 /****************************** SDIO Instances ********************************/
AnnaBridge 172:65be27845400 17335 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
AnnaBridge 172:65be27845400 17336
AnnaBridge 172:65be27845400 17337 /****************************** IWDG Instances ********************************/
AnnaBridge 172:65be27845400 17338 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 172:65be27845400 17339
AnnaBridge 172:65be27845400 17340 /****************************** WWDG Instances ********************************/
AnnaBridge 172:65be27845400 17341 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 172:65be27845400 17342
AnnaBridge 172:65be27845400 17343 /****************************** USB Exported Constants ************************/
AnnaBridge 172:65be27845400 17344 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
AnnaBridge 172:65be27845400 17345 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
AnnaBridge 172:65be27845400 17346 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
AnnaBridge 172:65be27845400 17347 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
AnnaBridge 172:65be27845400 17348
AnnaBridge 172:65be27845400 17349 /*
AnnaBridge 172:65be27845400 17350 * @brief Specific devices reset values definitions
AnnaBridge 172:65be27845400 17351 */
AnnaBridge 172:65be27845400 17352 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
AnnaBridge 172:65be27845400 17353 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
AnnaBridge 172:65be27845400 17354 #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
AnnaBridge 172:65be27845400 17355
AnnaBridge 172:65be27845400 17356 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
AnnaBridge 172:65be27845400 17357 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
AnnaBridge 172:65be27845400 17358 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
AnnaBridge 172:65be27845400 17359 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
AnnaBridge 172:65be27845400 17360 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 172:65be27845400 17361 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 172:65be27845400 17362 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 172:65be27845400 17363 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 172:65be27845400 17364
AnnaBridge 172:65be27845400 17365 #define RCC_PLLN_MIN_VALUE 50U
AnnaBridge 172:65be27845400 17366 #define RCC_PLLN_MAX_VALUE 432U
AnnaBridge 172:65be27845400 17367
AnnaBridge 172:65be27845400 17368 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
AnnaBridge 172:65be27845400 17369 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
AnnaBridge 172:65be27845400 17370 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
AnnaBridge 172:65be27845400 17371 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
AnnaBridge 172:65be27845400 17372 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
AnnaBridge 172:65be27845400 17373
AnnaBridge 172:65be27845400 17374 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
AnnaBridge 172:65be27845400 17375 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
AnnaBridge 172:65be27845400 17376 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
AnnaBridge 172:65be27845400 17377 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
AnnaBridge 172:65be27845400 17378 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
AnnaBridge 172:65be27845400 17379
AnnaBridge 172:65be27845400 17380 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
AnnaBridge 172:65be27845400 17381 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
AnnaBridge 172:65be27845400 17382 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
AnnaBridge 172:65be27845400 17383
AnnaBridge 172:65be27845400 17384 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
AnnaBridge 172:65be27845400 17385 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
AnnaBridge 172:65be27845400 17386 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
AnnaBridge 172:65be27845400 17387 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
AnnaBridge 172:65be27845400 17388 /******************************************************************************/
AnnaBridge 172:65be27845400 17389 /* For a painless codes migration between the STM32F4xx device product */
AnnaBridge 172:65be27845400 17390 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 172:65be27845400 17391 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 172:65be27845400 17392 /* No need to update developed interrupt code when moving across */
AnnaBridge 172:65be27845400 17393 /* product lines within the same STM32F4 Family */
AnnaBridge 172:65be27845400 17394 /******************************************************************************/
AnnaBridge 172:65be27845400 17395 /* Aliases for __IRQn */
AnnaBridge 172:65be27845400 17396 #define FSMC_IRQn FMC_IRQn
AnnaBridge 172:65be27845400 17397
AnnaBridge 172:65be27845400 17398 /* Aliases for __IRQHandler */
AnnaBridge 172:65be27845400 17399 #define FSMC_IRQHandler FMC_IRQHandler
AnnaBridge 172:65be27845400 17400
AnnaBridge 172:65be27845400 17401 /**
AnnaBridge 172:65be27845400 17402 * @}
AnnaBridge 172:65be27845400 17403 */
AnnaBridge 172:65be27845400 17404
AnnaBridge 172:65be27845400 17405 /**
AnnaBridge 172:65be27845400 17406 * @}
AnnaBridge 172:65be27845400 17407 */
AnnaBridge 172:65be27845400 17408
AnnaBridge 172:65be27845400 17409 /**
AnnaBridge 172:65be27845400 17410 * @}
AnnaBridge 172:65be27845400 17411 */
AnnaBridge 172:65be27845400 17412
AnnaBridge 172:65be27845400 17413 #ifdef __cplusplus
AnnaBridge 172:65be27845400 17414 }
AnnaBridge 172:65be27845400 17415 #endif /* __cplusplus */
AnnaBridge 172:65be27845400 17416
AnnaBridge 172:65be27845400 17417 #endif /* __STM32F439xx_H */
AnnaBridge 172:65be27845400 17418
AnnaBridge 172:65be27845400 17419
AnnaBridge 172:65be27845400 17420
AnnaBridge 172:65be27845400 17421 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/