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TARGET_WALLBOT_BLE/TOOLCHAIN_GCC_ARM/nrf51_bitfields.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/*
AnnaBridge	171:3a7713b1edbc	2	* Copyright (c) Nordic Semiconductor ASA
AnnaBridge	171:3a7713b1edbc	3	* All rights reserved.
AnnaBridge	171:3a7713b1edbc	4	*
AnnaBridge	171:3a7713b1edbc	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	6	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	7	*
AnnaBridge	171:3a7713b1edbc	8	* 1. Redistributions of source code must retain the above copyright notice, this
AnnaBridge	171:3a7713b1edbc	9	* list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	171:3a7713b1edbc	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	171:3a7713b1edbc	13	* other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	14	*
AnnaBridge	171:3a7713b1edbc	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
AnnaBridge	171:3a7713b1edbc	16	* contributors to this software may be used to endorse or promote products
AnnaBridge	171:3a7713b1edbc	17	* derived from this software without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	18	*
AnnaBridge	171:3a7713b1edbc	19	*
AnnaBridge	171:3a7713b1edbc	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	171:3a7713b1edbc	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	171:3a7713b1edbc	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	171:3a7713b1edbc	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	171:3a7713b1edbc	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	171:3a7713b1edbc	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	171:3a7713b1edbc	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	171:3a7713b1edbc	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	171:3a7713b1edbc	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	30	*
AnnaBridge	171:3a7713b1edbc	31	*/
AnnaBridge	171:3a7713b1edbc	32	#ifndef __NRF51_BITS_H
AnnaBridge	171:3a7713b1edbc	33	#define __NRF51_BITS_H
AnnaBridge	171:3a7713b1edbc	34
AnnaBridge	171:3a7713b1edbc	35	/lint ++flb "Enter library region" /
AnnaBridge	171:3a7713b1edbc	36
AnnaBridge	171:3a7713b1edbc	37	/* Peripheral: AAR */
AnnaBridge	171:3a7713b1edbc	38	/* Description: Accelerated Address Resolver. */
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	/* Register: AAR_INTENSET */
AnnaBridge	171:3a7713b1edbc	41	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	42
AnnaBridge	171:3a7713b1edbc	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
AnnaBridge	171:3a7713b1edbc	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
AnnaBridge	171:3a7713b1edbc	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
AnnaBridge	171:3a7713b1edbc	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	49
AnnaBridge	171:3a7713b1edbc	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
AnnaBridge	171:3a7713b1edbc	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
AnnaBridge	171:3a7713b1edbc	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
AnnaBridge	171:3a7713b1edbc	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Bit 0 : Enable interrupt on END event. */
AnnaBridge	171:3a7713b1edbc	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	63
AnnaBridge	171:3a7713b1edbc	64	/* Register: AAR_INTENCLR */
AnnaBridge	171:3a7713b1edbc	65	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	66
AnnaBridge	171:3a7713b1edbc	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
AnnaBridge	171:3a7713b1edbc	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
AnnaBridge	171:3a7713b1edbc	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
AnnaBridge	171:3a7713b1edbc	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	73
AnnaBridge	171:3a7713b1edbc	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
AnnaBridge	171:3a7713b1edbc	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
AnnaBridge	171:3a7713b1edbc	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
AnnaBridge	171:3a7713b1edbc	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
AnnaBridge	171:3a7713b1edbc	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	87
AnnaBridge	171:3a7713b1edbc	88	/* Register: AAR_STATUS */
AnnaBridge	171:3a7713b1edbc	89	/* Description: Resolution status. */
AnnaBridge	171:3a7713b1edbc	90
AnnaBridge	171:3a7713b1edbc	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
AnnaBridge	171:3a7713b1edbc	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
AnnaBridge	171:3a7713b1edbc	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	/* Register: AAR_ENABLE */
AnnaBridge	171:3a7713b1edbc	96	/* Description: Enable AAR. */
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	/* Bits 1..0 : Enable AAR. */
AnnaBridge	171:3a7713b1edbc	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
AnnaBridge	171:3a7713b1edbc	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	/* Register: AAR_NIRK */
AnnaBridge	171:3a7713b1edbc	105	/* Description: Number of Identity root Keys in the IRK data structure. */
AnnaBridge	171:3a7713b1edbc	106
AnnaBridge	171:3a7713b1edbc	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
AnnaBridge	171:3a7713b1edbc	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
AnnaBridge	171:3a7713b1edbc	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	/* Register: AAR_POWER */
AnnaBridge	171:3a7713b1edbc	112	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	113
AnnaBridge	171:3a7713b1edbc	114	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	119
AnnaBridge	171:3a7713b1edbc	120
AnnaBridge	171:3a7713b1edbc	121	/* Peripheral: ADC */
AnnaBridge	171:3a7713b1edbc	122	/* Description: Analog to digital converter. */
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	/* Register: ADC_INTENSET */
AnnaBridge	171:3a7713b1edbc	125	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	126
AnnaBridge	171:3a7713b1edbc	127	/* Bit 0 : Enable interrupt on END event. */
AnnaBridge	171:3a7713b1edbc	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	133
AnnaBridge	171:3a7713b1edbc	134	/* Register: ADC_INTENCLR */
AnnaBridge	171:3a7713b1edbc	135	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	136
AnnaBridge	171:3a7713b1edbc	137	/* Bit 0 : Disable interrupt on END event. */
AnnaBridge	171:3a7713b1edbc	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	143
AnnaBridge	171:3a7713b1edbc	144	/* Register: ADC_BUSY */
AnnaBridge	171:3a7713b1edbc	145	/* Description: ADC busy register. */
AnnaBridge	171:3a7713b1edbc	146
AnnaBridge	171:3a7713b1edbc	147	/* Bit 0 : ADC busy register. */
AnnaBridge	171:3a7713b1edbc	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
AnnaBridge	171:3a7713b1edbc	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
AnnaBridge	171:3a7713b1edbc	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
AnnaBridge	171:3a7713b1edbc	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
AnnaBridge	171:3a7713b1edbc	152
AnnaBridge	171:3a7713b1edbc	153	/* Register: ADC_ENABLE */
AnnaBridge	171:3a7713b1edbc	154	/* Description: ADC enable. */
AnnaBridge	171:3a7713b1edbc	155
AnnaBridge	171:3a7713b1edbc	156	/* Bits 1..0 : ADC enable. */
AnnaBridge	171:3a7713b1edbc	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
AnnaBridge	171:3a7713b1edbc	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
AnnaBridge	171:3a7713b1edbc	161
AnnaBridge	171:3a7713b1edbc	162	/* Register: ADC_CONFIG */
AnnaBridge	171:3a7713b1edbc	163	/* Description: ADC configuration register. */
AnnaBridge	171:3a7713b1edbc	164
AnnaBridge	171:3a7713b1edbc	165	/* Bits 17..16 : ADC external reference pin selection. */
AnnaBridge	171:3a7713b1edbc	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
AnnaBridge	171:3a7713b1edbc	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
AnnaBridge	171:3a7713b1edbc	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
AnnaBridge	171:3a7713b1edbc	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
AnnaBridge	171:3a7713b1edbc	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
AnnaBridge	171:3a7713b1edbc	171
AnnaBridge	171:3a7713b1edbc	172	/* Bits 15..8 : ADC analog pin selection. */
AnnaBridge	171:3a7713b1edbc	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
AnnaBridge	171:3a7713b1edbc	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
AnnaBridge	171:3a7713b1edbc	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
AnnaBridge	171:3a7713b1edbc	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
AnnaBridge	171:3a7713b1edbc	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
AnnaBridge	171:3a7713b1edbc	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
AnnaBridge	171:3a7713b1edbc	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
AnnaBridge	171:3a7713b1edbc	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
AnnaBridge	171:3a7713b1edbc	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
AnnaBridge	171:3a7713b1edbc	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
AnnaBridge	171:3a7713b1edbc	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
AnnaBridge	171:3a7713b1edbc	184
AnnaBridge	171:3a7713b1edbc	185	/* Bits 6..5 : ADC reference selection. */
AnnaBridge	171:3a7713b1edbc	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
AnnaBridge	171:3a7713b1edbc	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
AnnaBridge	171:3a7713b1edbc	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
AnnaBridge	171:3a7713b1edbc	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
AnnaBridge	171:3a7713b1edbc	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
AnnaBridge	171:3a7713b1edbc	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
AnnaBridge	171:3a7713b1edbc	192
AnnaBridge	171:3a7713b1edbc	193	/* Bits 4..2 : ADC input selection. */
AnnaBridge	171:3a7713b1edbc	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
AnnaBridge	171:3a7713b1edbc	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
AnnaBridge	171:3a7713b1edbc	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
AnnaBridge	171:3a7713b1edbc	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
AnnaBridge	171:3a7713b1edbc	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
AnnaBridge	171:3a7713b1edbc	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
AnnaBridge	171:3a7713b1edbc	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
AnnaBridge	171:3a7713b1edbc	201
AnnaBridge	171:3a7713b1edbc	202	/* Bits 1..0 : ADC resolution. */
AnnaBridge	171:3a7713b1edbc	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
AnnaBridge	171:3a7713b1edbc	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
AnnaBridge	171:3a7713b1edbc	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
AnnaBridge	171:3a7713b1edbc	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
AnnaBridge	171:3a7713b1edbc	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
AnnaBridge	171:3a7713b1edbc	208
AnnaBridge	171:3a7713b1edbc	209	/* Register: ADC_RESULT */
AnnaBridge	171:3a7713b1edbc	210	/* Description: Result of ADC conversion. */
AnnaBridge	171:3a7713b1edbc	211
AnnaBridge	171:3a7713b1edbc	212	/* Bits 9..0 : Result of ADC conversion. */
AnnaBridge	171:3a7713b1edbc	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
AnnaBridge	171:3a7713b1edbc	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
AnnaBridge	171:3a7713b1edbc	215
AnnaBridge	171:3a7713b1edbc	216	/* Register: ADC_POWER */
AnnaBridge	171:3a7713b1edbc	217	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	218
AnnaBridge	171:3a7713b1edbc	219	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	224
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	/* Peripheral: AMLI */
AnnaBridge	171:3a7713b1edbc	227	/* Description: AHB Multi-Layer Interface. */
AnnaBridge	171:3a7713b1edbc	228
AnnaBridge	171:3a7713b1edbc	229	/* Register: AMLI_RAMPRI_CPU0 */
AnnaBridge	171:3a7713b1edbc	230	/* Description: Configurable priority configuration register for CPU0. */
AnnaBridge	171:3a7713b1edbc	231
AnnaBridge	171:3a7713b1edbc	232	/* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge	171:3a7713b1edbc	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	243
AnnaBridge	171:3a7713b1edbc	244	/* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge	171:3a7713b1edbc	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	255
AnnaBridge	171:3a7713b1edbc	256	/* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge	171:3a7713b1edbc	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	/* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge	171:3a7713b1edbc	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	279
AnnaBridge	171:3a7713b1edbc	280	/* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge	171:3a7713b1edbc	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	291
AnnaBridge	171:3a7713b1edbc	292	/* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge	171:3a7713b1edbc	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	303
AnnaBridge	171:3a7713b1edbc	304	/* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge	171:3a7713b1edbc	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	315
AnnaBridge	171:3a7713b1edbc	316	/* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge	171:3a7713b1edbc	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	/* Register: AMLI_RAMPRI_SPIS1 */
AnnaBridge	171:3a7713b1edbc	329	/* Description: Configurable priority configuration register for SPIS1. */
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	/* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge	171:3a7713b1edbc	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	342
AnnaBridge	171:3a7713b1edbc	343	/* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge	171:3a7713b1edbc	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	/* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge	171:3a7713b1edbc	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	366
AnnaBridge	171:3a7713b1edbc	367	/* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge	171:3a7713b1edbc	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	378
AnnaBridge	171:3a7713b1edbc	379	/* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge	171:3a7713b1edbc	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	390
AnnaBridge	171:3a7713b1edbc	391	/* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge	171:3a7713b1edbc	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	402
AnnaBridge	171:3a7713b1edbc	403	/* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge	171:3a7713b1edbc	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	414
AnnaBridge	171:3a7713b1edbc	415	/* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge	171:3a7713b1edbc	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	426
AnnaBridge	171:3a7713b1edbc	427	/* Register: AMLI_RAMPRI_RADIO */
AnnaBridge	171:3a7713b1edbc	428	/* Description: Configurable priority configuration register for RADIO. */
AnnaBridge	171:3a7713b1edbc	429
AnnaBridge	171:3a7713b1edbc	430	/* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge	171:3a7713b1edbc	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	441
AnnaBridge	171:3a7713b1edbc	442	/* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge	171:3a7713b1edbc	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	453
AnnaBridge	171:3a7713b1edbc	454	/* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge	171:3a7713b1edbc	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	465
AnnaBridge	171:3a7713b1edbc	466	/* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge	171:3a7713b1edbc	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	477
AnnaBridge	171:3a7713b1edbc	478	/* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge	171:3a7713b1edbc	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	489
AnnaBridge	171:3a7713b1edbc	490	/* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge	171:3a7713b1edbc	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	501
AnnaBridge	171:3a7713b1edbc	502	/* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge	171:3a7713b1edbc	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	513
AnnaBridge	171:3a7713b1edbc	514	/* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge	171:3a7713b1edbc	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	525
AnnaBridge	171:3a7713b1edbc	526	/* Register: AMLI_RAMPRI_ECB */
AnnaBridge	171:3a7713b1edbc	527	/* Description: Configurable priority configuration register for ECB. */
AnnaBridge	171:3a7713b1edbc	528
AnnaBridge	171:3a7713b1edbc	529	/* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge	171:3a7713b1edbc	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	/* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge	171:3a7713b1edbc	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	552
AnnaBridge	171:3a7713b1edbc	553	/* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge	171:3a7713b1edbc	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	/* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge	171:3a7713b1edbc	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	576
AnnaBridge	171:3a7713b1edbc	577	/* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge	171:3a7713b1edbc	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	/* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge	171:3a7713b1edbc	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	600
AnnaBridge	171:3a7713b1edbc	601	/* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge	171:3a7713b1edbc	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	612
AnnaBridge	171:3a7713b1edbc	613	/* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge	171:3a7713b1edbc	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	624
AnnaBridge	171:3a7713b1edbc	625	/* Register: AMLI_RAMPRI_CCM */
AnnaBridge	171:3a7713b1edbc	626	/* Description: Configurable priority configuration register for CCM. */
AnnaBridge	171:3a7713b1edbc	627
AnnaBridge	171:3a7713b1edbc	628	/* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge	171:3a7713b1edbc	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	639
AnnaBridge	171:3a7713b1edbc	640	/* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge	171:3a7713b1edbc	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge	171:3a7713b1edbc	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	663
AnnaBridge	171:3a7713b1edbc	664	/* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge	171:3a7713b1edbc	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	675
AnnaBridge	171:3a7713b1edbc	676	/* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge	171:3a7713b1edbc	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	687
AnnaBridge	171:3a7713b1edbc	688	/* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge	171:3a7713b1edbc	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	699
AnnaBridge	171:3a7713b1edbc	700	/* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge	171:3a7713b1edbc	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	711
AnnaBridge	171:3a7713b1edbc	712	/* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge	171:3a7713b1edbc	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	723
AnnaBridge	171:3a7713b1edbc	724	/* Register: AMLI_RAMPRI_AAR */
AnnaBridge	171:3a7713b1edbc	725	/* Description: Configurable priority configuration register for AAR. */
AnnaBridge	171:3a7713b1edbc	726
AnnaBridge	171:3a7713b1edbc	727	/* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge	171:3a7713b1edbc	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
AnnaBridge	171:3a7713b1edbc	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	738
AnnaBridge	171:3a7713b1edbc	739	/* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge	171:3a7713b1edbc	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
AnnaBridge	171:3a7713b1edbc	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	750
AnnaBridge	171:3a7713b1edbc	751	/* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge	171:3a7713b1edbc	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
AnnaBridge	171:3a7713b1edbc	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	762
AnnaBridge	171:3a7713b1edbc	763	/* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge	171:3a7713b1edbc	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
AnnaBridge	171:3a7713b1edbc	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	774
AnnaBridge	171:3a7713b1edbc	775	/* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge	171:3a7713b1edbc	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
AnnaBridge	171:3a7713b1edbc	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	786
AnnaBridge	171:3a7713b1edbc	787	/* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge	171:3a7713b1edbc	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
AnnaBridge	171:3a7713b1edbc	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	798
AnnaBridge	171:3a7713b1edbc	799	/* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge	171:3a7713b1edbc	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
AnnaBridge	171:3a7713b1edbc	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	810
AnnaBridge	171:3a7713b1edbc	811	/* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge	171:3a7713b1edbc	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
AnnaBridge	171:3a7713b1edbc	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
AnnaBridge	171:3a7713b1edbc	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
AnnaBridge	171:3a7713b1edbc	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
AnnaBridge	171:3a7713b1edbc	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
AnnaBridge	171:3a7713b1edbc	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
AnnaBridge	171:3a7713b1edbc	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
AnnaBridge	171:3a7713b1edbc	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
AnnaBridge	171:3a7713b1edbc	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
AnnaBridge	171:3a7713b1edbc	822
AnnaBridge	171:3a7713b1edbc	823
AnnaBridge	171:3a7713b1edbc	824	/* Peripheral: CCM */
AnnaBridge	171:3a7713b1edbc	825	/* Description: AES CCM Mode Encryption. */
AnnaBridge	171:3a7713b1edbc	826
AnnaBridge	171:3a7713b1edbc	827	/* Register: CCM_SHORTS */
AnnaBridge	171:3a7713b1edbc	828	/* Description: Shortcuts for the CCM. */
AnnaBridge	171:3a7713b1edbc	829
AnnaBridge	171:3a7713b1edbc	830	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
AnnaBridge	171:3a7713b1edbc	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
AnnaBridge	171:3a7713b1edbc	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
AnnaBridge	171:3a7713b1edbc	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	834	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	835
AnnaBridge	171:3a7713b1edbc	836	/* Register: CCM_INTENSET */
AnnaBridge	171:3a7713b1edbc	837	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	838
AnnaBridge	171:3a7713b1edbc	839	/* Bit 2 : Enable interrupt on ERROR event. */
AnnaBridge	171:3a7713b1edbc	840	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
AnnaBridge	171:3a7713b1edbc	841	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
AnnaBridge	171:3a7713b1edbc	842	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	843	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	844	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	845
AnnaBridge	171:3a7713b1edbc	846	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
AnnaBridge	171:3a7713b1edbc	847	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
AnnaBridge	171:3a7713b1edbc	848	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
AnnaBridge	171:3a7713b1edbc	849	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	850	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	851	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	852
AnnaBridge	171:3a7713b1edbc	853	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
AnnaBridge	171:3a7713b1edbc	854	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
AnnaBridge	171:3a7713b1edbc	855	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
AnnaBridge	171:3a7713b1edbc	856	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	857	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	858	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	859
AnnaBridge	171:3a7713b1edbc	860	/* Register: CCM_INTENCLR */
AnnaBridge	171:3a7713b1edbc	861	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863	/* Bit 2 : Disable interrupt on ERROR event. */
AnnaBridge	171:3a7713b1edbc	864	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
AnnaBridge	171:3a7713b1edbc	865	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
AnnaBridge	171:3a7713b1edbc	866	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	867	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	868	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	869
AnnaBridge	171:3a7713b1edbc	870	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
AnnaBridge	171:3a7713b1edbc	871	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
AnnaBridge	171:3a7713b1edbc	872	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
AnnaBridge	171:3a7713b1edbc	873	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	874	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	875	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	876
AnnaBridge	171:3a7713b1edbc	877	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
AnnaBridge	171:3a7713b1edbc	878	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
AnnaBridge	171:3a7713b1edbc	879	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
AnnaBridge	171:3a7713b1edbc	880	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	881	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	882	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	883
AnnaBridge	171:3a7713b1edbc	884	/* Register: CCM_MICSTATUS */
AnnaBridge	171:3a7713b1edbc	885	/* Description: CCM RX MIC check result. */
AnnaBridge	171:3a7713b1edbc	886
AnnaBridge	171:3a7713b1edbc	887	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
AnnaBridge	171:3a7713b1edbc	888	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
AnnaBridge	171:3a7713b1edbc	889	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
AnnaBridge	171:3a7713b1edbc	890	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
AnnaBridge	171:3a7713b1edbc	891	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893	/* Register: CCM_ENABLE */
AnnaBridge	171:3a7713b1edbc	894	/* Description: CCM enable. */
AnnaBridge	171:3a7713b1edbc	895
AnnaBridge	171:3a7713b1edbc	896	/* Bits 1..0 : CCM enable. */
AnnaBridge	171:3a7713b1edbc	897	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	898	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	899	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
AnnaBridge	171:3a7713b1edbc	900	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
AnnaBridge	171:3a7713b1edbc	901
AnnaBridge	171:3a7713b1edbc	902	/* Register: CCM_MODE */
AnnaBridge	171:3a7713b1edbc	903	/* Description: Operation mode. */
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	/* Bit 0 : CCM mode operation. */
AnnaBridge	171:3a7713b1edbc	906	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
AnnaBridge	171:3a7713b1edbc	907	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
AnnaBridge	171:3a7713b1edbc	908	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
AnnaBridge	171:3a7713b1edbc	909	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
AnnaBridge	171:3a7713b1edbc	910
AnnaBridge	171:3a7713b1edbc	911	/* Register: CCM_POWER */
AnnaBridge	171:3a7713b1edbc	912	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	913
AnnaBridge	171:3a7713b1edbc	914	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	915	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	916	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	917	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	918	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	919
AnnaBridge	171:3a7713b1edbc	920
AnnaBridge	171:3a7713b1edbc	921	/* Peripheral: CLOCK */
AnnaBridge	171:3a7713b1edbc	922	/* Description: Clock control. */
AnnaBridge	171:3a7713b1edbc	923
AnnaBridge	171:3a7713b1edbc	924	/* Register: CLOCK_INTENSET */
AnnaBridge	171:3a7713b1edbc	925	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	926
AnnaBridge	171:3a7713b1edbc	927	/* Bit 4 : Enable interrupt on CTTO event. */
AnnaBridge	171:3a7713b1edbc	928	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
AnnaBridge	171:3a7713b1edbc	929	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
AnnaBridge	171:3a7713b1edbc	930	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	931	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	932	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	933
AnnaBridge	171:3a7713b1edbc	934	/* Bit 3 : Enable interrupt on DONE event. */
AnnaBridge	171:3a7713b1edbc	935	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
AnnaBridge	171:3a7713b1edbc	936	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
AnnaBridge	171:3a7713b1edbc	937	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	938	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	939	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	940
AnnaBridge	171:3a7713b1edbc	941	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
AnnaBridge	171:3a7713b1edbc	942	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	943	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	944	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	945	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	946	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	947
AnnaBridge	171:3a7713b1edbc	948	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
AnnaBridge	171:3a7713b1edbc	949	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	950	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	951	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	952	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	953	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	954
AnnaBridge	171:3a7713b1edbc	955	/* Register: CLOCK_INTENCLR */
AnnaBridge	171:3a7713b1edbc	956	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	957
AnnaBridge	171:3a7713b1edbc	958	/* Bit 4 : Disable interrupt on CTTO event. */
AnnaBridge	171:3a7713b1edbc	959	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
AnnaBridge	171:3a7713b1edbc	960	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
AnnaBridge	171:3a7713b1edbc	961	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	962	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	963	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	964
AnnaBridge	171:3a7713b1edbc	965	/* Bit 3 : Disable interrupt on DONE event. */
AnnaBridge	171:3a7713b1edbc	966	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
AnnaBridge	171:3a7713b1edbc	967	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
AnnaBridge	171:3a7713b1edbc	968	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	969	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	970	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	971
AnnaBridge	171:3a7713b1edbc	972	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
AnnaBridge	171:3a7713b1edbc	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	977	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	978
AnnaBridge	171:3a7713b1edbc	979	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
AnnaBridge	171:3a7713b1edbc	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
AnnaBridge	171:3a7713b1edbc	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	984	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	985
AnnaBridge	171:3a7713b1edbc	986	/* Register: CLOCK_HFCLKRUN */
AnnaBridge	171:3a7713b1edbc	987	/* Description: Task HFCLKSTART trigger status. */
AnnaBridge	171:3a7713b1edbc	988
AnnaBridge	171:3a7713b1edbc	989	/* Bit 0 : Task HFCLKSTART trigger status. */
AnnaBridge	171:3a7713b1edbc	990	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
AnnaBridge	171:3a7713b1edbc	991	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
AnnaBridge	171:3a7713b1edbc	992	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
AnnaBridge	171:3a7713b1edbc	993	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
AnnaBridge	171:3a7713b1edbc	994
AnnaBridge	171:3a7713b1edbc	995	/* Register: CLOCK_HFCLKSTAT */
AnnaBridge	171:3a7713b1edbc	996	/* Description: High frequency clock status. */
AnnaBridge	171:3a7713b1edbc	997
AnnaBridge	171:3a7713b1edbc	998	/* Bit 16 : State for the HFCLK. */
AnnaBridge	171:3a7713b1edbc	999	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
AnnaBridge	171:3a7713b1edbc	1000	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
AnnaBridge	171:3a7713b1edbc	1001	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
AnnaBridge	171:3a7713b1edbc	1002	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
AnnaBridge	171:3a7713b1edbc	1003
AnnaBridge	171:3a7713b1edbc	1004	/* Bit 0 : Active clock source for the HF clock. */
AnnaBridge	171:3a7713b1edbc	1005	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
AnnaBridge	171:3a7713b1edbc	1006	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
AnnaBridge	171:3a7713b1edbc	1007	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
AnnaBridge	171:3a7713b1edbc	1008	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
AnnaBridge	171:3a7713b1edbc	1009
AnnaBridge	171:3a7713b1edbc	1010	/* Register: CLOCK_LFCLKRUN */
AnnaBridge	171:3a7713b1edbc	1011	/* Description: Task LFCLKSTART triggered status. */
AnnaBridge	171:3a7713b1edbc	1012
AnnaBridge	171:3a7713b1edbc	1013	/* Bit 0 : Task LFCLKSTART triggered status. */
AnnaBridge	171:3a7713b1edbc	1014	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
AnnaBridge	171:3a7713b1edbc	1015	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
AnnaBridge	171:3a7713b1edbc	1016	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
AnnaBridge	171:3a7713b1edbc	1017	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
AnnaBridge	171:3a7713b1edbc	1018
AnnaBridge	171:3a7713b1edbc	1019	/* Register: CLOCK_LFCLKSTAT */
AnnaBridge	171:3a7713b1edbc	1020	/* Description: Low frequency clock status. */
AnnaBridge	171:3a7713b1edbc	1021
AnnaBridge	171:3a7713b1edbc	1022	/* Bit 16 : State for the LF clock. */
AnnaBridge	171:3a7713b1edbc	1023	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
AnnaBridge	171:3a7713b1edbc	1024	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
AnnaBridge	171:3a7713b1edbc	1025	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
AnnaBridge	171:3a7713b1edbc	1026	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
AnnaBridge	171:3a7713b1edbc	1027
AnnaBridge	171:3a7713b1edbc	1028	/* Bits 1..0 : Active clock source for the LF clock. */
AnnaBridge	171:3a7713b1edbc	1029	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
AnnaBridge	171:3a7713b1edbc	1030	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
AnnaBridge	171:3a7713b1edbc	1031	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
AnnaBridge	171:3a7713b1edbc	1032	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
AnnaBridge	171:3a7713b1edbc	1033	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
AnnaBridge	171:3a7713b1edbc	1034
AnnaBridge	171:3a7713b1edbc	1035	/* Register: CLOCK_LFCLKSRCCOPY */
AnnaBridge	171:3a7713b1edbc	1036	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
AnnaBridge	171:3a7713b1edbc	1037
AnnaBridge	171:3a7713b1edbc	1038	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
AnnaBridge	171:3a7713b1edbc	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
AnnaBridge	171:3a7713b1edbc	1040	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
AnnaBridge	171:3a7713b1edbc	1041	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
AnnaBridge	171:3a7713b1edbc	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
AnnaBridge	171:3a7713b1edbc	1043	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
AnnaBridge	171:3a7713b1edbc	1044
AnnaBridge	171:3a7713b1edbc	1045	/* Register: CLOCK_LFCLKSRC */
AnnaBridge	171:3a7713b1edbc	1046	/* Description: Clock source for the LFCLK clock. */
AnnaBridge	171:3a7713b1edbc	1047
AnnaBridge	171:3a7713b1edbc	1048	/* Bits 1..0 : Clock source. */
AnnaBridge	171:3a7713b1edbc	1049	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
AnnaBridge	171:3a7713b1edbc	1050	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
AnnaBridge	171:3a7713b1edbc	1051	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
AnnaBridge	171:3a7713b1edbc	1052	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
AnnaBridge	171:3a7713b1edbc	1053	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
AnnaBridge	171:3a7713b1edbc	1054
AnnaBridge	171:3a7713b1edbc	1055	/* Register: CLOCK_CTIV */
AnnaBridge	171:3a7713b1edbc	1056	/* Description: Calibration timer interval. */
AnnaBridge	171:3a7713b1edbc	1057
AnnaBridge	171:3a7713b1edbc	1058	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
AnnaBridge	171:3a7713b1edbc	1059	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
AnnaBridge	171:3a7713b1edbc	1060	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
AnnaBridge	171:3a7713b1edbc	1061
AnnaBridge	171:3a7713b1edbc	1062	/* Register: CLOCK_XTALFREQ */
AnnaBridge	171:3a7713b1edbc	1063	/* Description: Crystal frequency. */
AnnaBridge	171:3a7713b1edbc	1064
AnnaBridge	171:3a7713b1edbc	1065	/* Bits 7..0 : External Xtal frequency selection. */
AnnaBridge	171:3a7713b1edbc	1066	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
AnnaBridge	171:3a7713b1edbc	1067	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
AnnaBridge	171:3a7713b1edbc	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
AnnaBridge	171:3a7713b1edbc	1069	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
AnnaBridge	171:3a7713b1edbc	1070
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	/* Peripheral: ECB */
AnnaBridge	171:3a7713b1edbc	1073	/* Description: AES ECB Mode Encryption. */
AnnaBridge	171:3a7713b1edbc	1074
AnnaBridge	171:3a7713b1edbc	1075	/* Register: ECB_INTENSET */
AnnaBridge	171:3a7713b1edbc	1076	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	1077
AnnaBridge	171:3a7713b1edbc	1078	/* Bit 1 : Enable interrupt on ERRORECB event. */
AnnaBridge	171:3a7713b1edbc	1079	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
AnnaBridge	171:3a7713b1edbc	1080	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
AnnaBridge	171:3a7713b1edbc	1081	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	1082	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	1083	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	1084
AnnaBridge	171:3a7713b1edbc	1085	/* Bit 0 : Enable interrupt on ENDECB event. */
AnnaBridge	171:3a7713b1edbc	1086	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
AnnaBridge	171:3a7713b1edbc	1087	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
AnnaBridge	171:3a7713b1edbc	1088	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	1089	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	1090	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	1091
AnnaBridge	171:3a7713b1edbc	1092	/* Register: ECB_INTENCLR */
AnnaBridge	171:3a7713b1edbc	1093	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	1094
AnnaBridge	171:3a7713b1edbc	1095	/* Bit 1 : Disable interrupt on ERRORECB event. */
AnnaBridge	171:3a7713b1edbc	1096	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
AnnaBridge	171:3a7713b1edbc	1097	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
AnnaBridge	171:3a7713b1edbc	1098	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	1099	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	1100	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	1101
AnnaBridge	171:3a7713b1edbc	1102	/* Bit 0 : Disable interrupt on ENDECB event. */
AnnaBridge	171:3a7713b1edbc	1103	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
AnnaBridge	171:3a7713b1edbc	1104	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
AnnaBridge	171:3a7713b1edbc	1105	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	1106	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	1107	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	1108
AnnaBridge	171:3a7713b1edbc	1109	/* Register: ECB_POWER */
AnnaBridge	171:3a7713b1edbc	1110	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	1111
AnnaBridge	171:3a7713b1edbc	1112	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	1113	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	1114	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	1115	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	1116	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118
AnnaBridge	171:3a7713b1edbc	1119	/* Peripheral: FICR */
AnnaBridge	171:3a7713b1edbc	1120	/* Description: Factory Information Configuration. */
AnnaBridge	171:3a7713b1edbc	1121
AnnaBridge	171:3a7713b1edbc	1122	/* Register: FICR_PPFC */
AnnaBridge	171:3a7713b1edbc	1123	/* Description: Pre-programmed factory code present. */
AnnaBridge	171:3a7713b1edbc	1124
AnnaBridge	171:3a7713b1edbc	1125	/* Bits 7..0 : Pre-programmed factory code present. */
AnnaBridge	171:3a7713b1edbc	1126	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
AnnaBridge	171:3a7713b1edbc	1127	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
AnnaBridge	171:3a7713b1edbc	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
AnnaBridge	171:3a7713b1edbc	1129	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
AnnaBridge	171:3a7713b1edbc	1130
AnnaBridge	171:3a7713b1edbc	1131	/* Register: FICR_CONFIGID */
AnnaBridge	171:3a7713b1edbc	1132	/* Description: Configuration identifier. */
AnnaBridge	171:3a7713b1edbc	1133
AnnaBridge	171:3a7713b1edbc	1134	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
AnnaBridge	171:3a7713b1edbc	1135	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
AnnaBridge	171:3a7713b1edbc	1136	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
AnnaBridge	171:3a7713b1edbc	1137
AnnaBridge	171:3a7713b1edbc	1138	/* Bits 15..0 : Hardware Identification Number. */
AnnaBridge	171:3a7713b1edbc	1139	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
AnnaBridge	171:3a7713b1edbc	1140	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
AnnaBridge	171:3a7713b1edbc	1141
AnnaBridge	171:3a7713b1edbc	1142	/* Register: FICR_DEVICEADDRTYPE */
AnnaBridge	171:3a7713b1edbc	1143	/* Description: Device address type. */
AnnaBridge	171:3a7713b1edbc	1144
AnnaBridge	171:3a7713b1edbc	1145	/* Bit 0 : Device address type. */
AnnaBridge	171:3a7713b1edbc	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
AnnaBridge	171:3a7713b1edbc	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
AnnaBridge	171:3a7713b1edbc	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
AnnaBridge	171:3a7713b1edbc	1149	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
AnnaBridge	171:3a7713b1edbc	1150
AnnaBridge	171:3a7713b1edbc	1151	/* Register: FICR_OVERRIDEEN */
AnnaBridge	171:3a7713b1edbc	1152	/* Description: Radio calibration override enable. */
AnnaBridge	171:3a7713b1edbc	1153
AnnaBridge	171:3a7713b1edbc	1154	/* Bit 3 : Override default values for BLE_1Mbit mode. */
AnnaBridge	171:3a7713b1edbc	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
AnnaBridge	171:3a7713b1edbc	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
AnnaBridge	171:3a7713b1edbc	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
AnnaBridge	171:3a7713b1edbc	1158	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
AnnaBridge	171:3a7713b1edbc	1159
AnnaBridge	171:3a7713b1edbc	1160	/* Bit 0 : Override default values for NRF_1Mbit mode. */
AnnaBridge	171:3a7713b1edbc	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
AnnaBridge	171:3a7713b1edbc	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
AnnaBridge	171:3a7713b1edbc	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
AnnaBridge	171:3a7713b1edbc	1164	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
AnnaBridge	171:3a7713b1edbc	1165
AnnaBridge	171:3a7713b1edbc	1166
AnnaBridge	171:3a7713b1edbc	1167	/* Peripheral: GPIO */
AnnaBridge	171:3a7713b1edbc	1168	/* Description: General purpose input and output. */
AnnaBridge	171:3a7713b1edbc	1169
AnnaBridge	171:3a7713b1edbc	1170	/* Register: GPIO_OUT */
AnnaBridge	171:3a7713b1edbc	1171	/* Description: Write GPIO port. */
AnnaBridge	171:3a7713b1edbc	1172
AnnaBridge	171:3a7713b1edbc	1173	/* Bit 31 : Pin 31. */
AnnaBridge	171:3a7713b1edbc	1174	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1175	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1176	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1177	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1178
AnnaBridge	171:3a7713b1edbc	1179	/* Bit 30 : Pin 30. */
AnnaBridge	171:3a7713b1edbc	1180	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1181	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1182	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1183	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1184
AnnaBridge	171:3a7713b1edbc	1185	/* Bit 29 : Pin 29. */
AnnaBridge	171:3a7713b1edbc	1186	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1187	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1188	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1189	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1190
AnnaBridge	171:3a7713b1edbc	1191	/* Bit 28 : Pin 28. */
AnnaBridge	171:3a7713b1edbc	1192	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1193	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1194	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1195	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1196
AnnaBridge	171:3a7713b1edbc	1197	/* Bit 27 : Pin 27. */
AnnaBridge	171:3a7713b1edbc	1198	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1199	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1200	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1201	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1202
AnnaBridge	171:3a7713b1edbc	1203	/* Bit 26 : Pin 26. */
AnnaBridge	171:3a7713b1edbc	1204	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1205	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1206	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1207	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1208
AnnaBridge	171:3a7713b1edbc	1209	/* Bit 25 : Pin 25. */
AnnaBridge	171:3a7713b1edbc	1210	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1211	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1212	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1213	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1214
AnnaBridge	171:3a7713b1edbc	1215	/* Bit 24 : Pin 24. */
AnnaBridge	171:3a7713b1edbc	1216	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1217	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1218	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1219	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1220
AnnaBridge	171:3a7713b1edbc	1221	/* Bit 23 : Pin 23. */
AnnaBridge	171:3a7713b1edbc	1222	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1223	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1224	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1225	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1226
AnnaBridge	171:3a7713b1edbc	1227	/* Bit 22 : Pin 22. */
AnnaBridge	171:3a7713b1edbc	1228	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1229	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1230	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1231	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1232
AnnaBridge	171:3a7713b1edbc	1233	/* Bit 21 : Pin 21. */
AnnaBridge	171:3a7713b1edbc	1234	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1235	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1236	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1237	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1238
AnnaBridge	171:3a7713b1edbc	1239	/* Bit 20 : Pin 20. */
AnnaBridge	171:3a7713b1edbc	1240	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1241	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1242	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1243	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1244
AnnaBridge	171:3a7713b1edbc	1245	/* Bit 19 : Pin 19. */
AnnaBridge	171:3a7713b1edbc	1246	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1247	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1248	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1249	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1250
AnnaBridge	171:3a7713b1edbc	1251	/* Bit 18 : Pin 18. */
AnnaBridge	171:3a7713b1edbc	1252	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1253	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1254	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1255	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1256
AnnaBridge	171:3a7713b1edbc	1257	/* Bit 17 : Pin 17. */
AnnaBridge	171:3a7713b1edbc	1258	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1259	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1260	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1261	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1262
AnnaBridge	171:3a7713b1edbc	1263	/* Bit 16 : Pin 16. */
AnnaBridge	171:3a7713b1edbc	1264	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1265	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1266	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1267	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1268
AnnaBridge	171:3a7713b1edbc	1269	/* Bit 15 : Pin 15. */
AnnaBridge	171:3a7713b1edbc	1270	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1271	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1272	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1273	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1274
AnnaBridge	171:3a7713b1edbc	1275	/* Bit 14 : Pin 14. */
AnnaBridge	171:3a7713b1edbc	1276	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1277	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1278	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1279	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1280
AnnaBridge	171:3a7713b1edbc	1281	/* Bit 13 : Pin 13. */
AnnaBridge	171:3a7713b1edbc	1282	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1283	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1284	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1285	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1286
AnnaBridge	171:3a7713b1edbc	1287	/* Bit 12 : Pin 12. */
AnnaBridge	171:3a7713b1edbc	1288	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1289	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1290	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1291	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1292
AnnaBridge	171:3a7713b1edbc	1293	/* Bit 11 : Pin 11. */
AnnaBridge	171:3a7713b1edbc	1294	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1295	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1296	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1297	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1298
AnnaBridge	171:3a7713b1edbc	1299	/* Bit 10 : Pin 10. */
AnnaBridge	171:3a7713b1edbc	1300	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1301	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1302	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1303	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1304
AnnaBridge	171:3a7713b1edbc	1305	/* Bit 9 : Pin 9. */
AnnaBridge	171:3a7713b1edbc	1306	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1307	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1308	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1309	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1310
AnnaBridge	171:3a7713b1edbc	1311	/* Bit 8 : Pin 8. */
AnnaBridge	171:3a7713b1edbc	1312	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1313	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1314	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1315	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1316
AnnaBridge	171:3a7713b1edbc	1317	/* Bit 7 : Pin 7. */
AnnaBridge	171:3a7713b1edbc	1318	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1319	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1320	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1321	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1322
AnnaBridge	171:3a7713b1edbc	1323	/* Bit 6 : Pin 6. */
AnnaBridge	171:3a7713b1edbc	1324	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1325	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1326	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1327	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1328
AnnaBridge	171:3a7713b1edbc	1329	/* Bit 5 : Pin 5. */
AnnaBridge	171:3a7713b1edbc	1330	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1331	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1332	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1333	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1334
AnnaBridge	171:3a7713b1edbc	1335	/* Bit 4 : Pin 4. */
AnnaBridge	171:3a7713b1edbc	1336	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1337	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1338	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1339	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1340
AnnaBridge	171:3a7713b1edbc	1341	/* Bit 3 : Pin 3. */
AnnaBridge	171:3a7713b1edbc	1342	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1343	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1344	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1345	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1346
AnnaBridge	171:3a7713b1edbc	1347	/* Bit 2 : Pin 2. */
AnnaBridge	171:3a7713b1edbc	1348	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1349	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1350	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1351	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1352
AnnaBridge	171:3a7713b1edbc	1353	/* Bit 1 : Pin 1. */
AnnaBridge	171:3a7713b1edbc	1354	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	1355	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	1356	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1357	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1358
AnnaBridge	171:3a7713b1edbc	1359	/* Bit 0 : Pin 0. */
AnnaBridge	171:3a7713b1edbc	1360	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	1361	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	1362	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1363	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1364
AnnaBridge	171:3a7713b1edbc	1365	/* Register: GPIO_OUTSET */
AnnaBridge	171:3a7713b1edbc	1366	/* Description: Set individual bits in GPIO port. */
AnnaBridge	171:3a7713b1edbc	1367
AnnaBridge	171:3a7713b1edbc	1368	/* Bit 31 : Pin 31. */
AnnaBridge	171:3a7713b1edbc	1369	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1370	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1371	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1372	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1373	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1374
AnnaBridge	171:3a7713b1edbc	1375	/* Bit 30 : Pin 30. */
AnnaBridge	171:3a7713b1edbc	1376	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1377	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1378	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1379	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1380	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1381
AnnaBridge	171:3a7713b1edbc	1382	/* Bit 29 : Pin 29. */
AnnaBridge	171:3a7713b1edbc	1383	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1384	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1385	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1386	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1387	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1388
AnnaBridge	171:3a7713b1edbc	1389	/* Bit 28 : Pin 28. */
AnnaBridge	171:3a7713b1edbc	1390	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1391	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1392	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1393	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1394	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1395
AnnaBridge	171:3a7713b1edbc	1396	/* Bit 27 : Pin 27. */
AnnaBridge	171:3a7713b1edbc	1397	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1398	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1399	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1400	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1401	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1402
AnnaBridge	171:3a7713b1edbc	1403	/* Bit 26 : Pin 26. */
AnnaBridge	171:3a7713b1edbc	1404	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1405	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1406	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1407	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1408	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1409
AnnaBridge	171:3a7713b1edbc	1410	/* Bit 25 : Pin 25. */
AnnaBridge	171:3a7713b1edbc	1411	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1412	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1413	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1414	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1415	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1416
AnnaBridge	171:3a7713b1edbc	1417	/* Bit 24 : Pin 24. */
AnnaBridge	171:3a7713b1edbc	1418	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1419	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1420	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1421	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1422	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1423
AnnaBridge	171:3a7713b1edbc	1424	/* Bit 23 : Pin 23. */
AnnaBridge	171:3a7713b1edbc	1425	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1426	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1427	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1428	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1429	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1430
AnnaBridge	171:3a7713b1edbc	1431	/* Bit 22 : Pin 22. */
AnnaBridge	171:3a7713b1edbc	1432	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1433	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1434	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1435	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1436	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1437
AnnaBridge	171:3a7713b1edbc	1438	/* Bit 21 : Pin 21. */
AnnaBridge	171:3a7713b1edbc	1439	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1440	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1441	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1442	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1443	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1444
AnnaBridge	171:3a7713b1edbc	1445	/* Bit 20 : Pin 20. */
AnnaBridge	171:3a7713b1edbc	1446	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1447	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1448	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1449	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1450	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1451
AnnaBridge	171:3a7713b1edbc	1452	/* Bit 19 : Pin 19. */
AnnaBridge	171:3a7713b1edbc	1453	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1454	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1455	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1456	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1457	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1458
AnnaBridge	171:3a7713b1edbc	1459	/* Bit 18 : Pin 18. */
AnnaBridge	171:3a7713b1edbc	1460	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1461	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1462	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1463	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1464	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1465
AnnaBridge	171:3a7713b1edbc	1466	/* Bit 17 : Pin 17. */
AnnaBridge	171:3a7713b1edbc	1467	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1468	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1469	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1470	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1471	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1472
AnnaBridge	171:3a7713b1edbc	1473	/* Bit 16 : Pin 16. */
AnnaBridge	171:3a7713b1edbc	1474	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1475	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1476	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1477	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1478	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1479
AnnaBridge	171:3a7713b1edbc	1480	/* Bit 15 : Pin 15. */
AnnaBridge	171:3a7713b1edbc	1481	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1482	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1483	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1484	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1485	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1486
AnnaBridge	171:3a7713b1edbc	1487	/* Bit 14 : Pin 14. */
AnnaBridge	171:3a7713b1edbc	1488	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1489	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1490	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1491	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1492	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1493
AnnaBridge	171:3a7713b1edbc	1494	/* Bit 13 : Pin 13. */
AnnaBridge	171:3a7713b1edbc	1495	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1496	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1497	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1498	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1499	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1500
AnnaBridge	171:3a7713b1edbc	1501	/* Bit 12 : Pin 12. */
AnnaBridge	171:3a7713b1edbc	1502	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1503	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1504	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1505	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1506	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1507
AnnaBridge	171:3a7713b1edbc	1508	/* Bit 11 : Pin 11. */
AnnaBridge	171:3a7713b1edbc	1509	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1510	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1511	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1512	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1513	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1514
AnnaBridge	171:3a7713b1edbc	1515	/* Bit 10 : Pin 10. */
AnnaBridge	171:3a7713b1edbc	1516	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1517	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1518	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1519	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1520	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1521
AnnaBridge	171:3a7713b1edbc	1522	/* Bit 9 : Pin 9. */
AnnaBridge	171:3a7713b1edbc	1523	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1524	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1525	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1526	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1527	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1528
AnnaBridge	171:3a7713b1edbc	1529	/* Bit 8 : Pin 8. */
AnnaBridge	171:3a7713b1edbc	1530	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1531	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1532	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1533	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1534	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1535
AnnaBridge	171:3a7713b1edbc	1536	/* Bit 7 : Pin 7. */
AnnaBridge	171:3a7713b1edbc	1537	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1538	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1539	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1540	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1541	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1542
AnnaBridge	171:3a7713b1edbc	1543	/* Bit 6 : Pin 6. */
AnnaBridge	171:3a7713b1edbc	1544	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1545	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1546	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1547	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1548	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1549
AnnaBridge	171:3a7713b1edbc	1550	/* Bit 5 : Pin 5. */
AnnaBridge	171:3a7713b1edbc	1551	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1552	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1553	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1554	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1555	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1556
AnnaBridge	171:3a7713b1edbc	1557	/* Bit 4 : Pin 4. */
AnnaBridge	171:3a7713b1edbc	1558	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1559	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1560	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1561	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1562	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1563
AnnaBridge	171:3a7713b1edbc	1564	/* Bit 3 : Pin 3. */
AnnaBridge	171:3a7713b1edbc	1565	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1566	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1567	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1568	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1569	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1570
AnnaBridge	171:3a7713b1edbc	1571	/* Bit 2 : Pin 2. */
AnnaBridge	171:3a7713b1edbc	1572	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1573	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1574	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1575	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1576	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1577
AnnaBridge	171:3a7713b1edbc	1578	/* Bit 1 : Pin 1. */
AnnaBridge	171:3a7713b1edbc	1579	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	1580	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	1581	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1582	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1583	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1584
AnnaBridge	171:3a7713b1edbc	1585	/* Bit 0 : Pin 0. */
AnnaBridge	171:3a7713b1edbc	1586	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	1587	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	1588	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1589	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1590	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
AnnaBridge	171:3a7713b1edbc	1591
AnnaBridge	171:3a7713b1edbc	1592	/* Register: GPIO_OUTCLR */
AnnaBridge	171:3a7713b1edbc	1593	/* Description: Clear individual bits in GPIO port. */
AnnaBridge	171:3a7713b1edbc	1594
AnnaBridge	171:3a7713b1edbc	1595	/* Bit 31 : Pin 31. */
AnnaBridge	171:3a7713b1edbc	1596	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1597	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1598	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1599	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1600	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1601
AnnaBridge	171:3a7713b1edbc	1602	/* Bit 30 : Pin 30. */
AnnaBridge	171:3a7713b1edbc	1603	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1604	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1605	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1606	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1607	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1608
AnnaBridge	171:3a7713b1edbc	1609	/* Bit 29 : Pin 29. */
AnnaBridge	171:3a7713b1edbc	1610	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1611	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1612	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1613	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1614	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1615
AnnaBridge	171:3a7713b1edbc	1616	/* Bit 28 : Pin 28. */
AnnaBridge	171:3a7713b1edbc	1617	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1618	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1619	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1620	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1621	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1622
AnnaBridge	171:3a7713b1edbc	1623	/* Bit 27 : Pin 27. */
AnnaBridge	171:3a7713b1edbc	1624	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1625	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1626	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1627	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1628	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1629
AnnaBridge	171:3a7713b1edbc	1630	/* Bit 26 : Pin 26. */
AnnaBridge	171:3a7713b1edbc	1631	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1632	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1633	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1634	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1635	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1636
AnnaBridge	171:3a7713b1edbc	1637	/* Bit 25 : Pin 25. */
AnnaBridge	171:3a7713b1edbc	1638	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1639	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1640	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1641	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1642	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1643
AnnaBridge	171:3a7713b1edbc	1644	/* Bit 24 : Pin 24. */
AnnaBridge	171:3a7713b1edbc	1645	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1646	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1647	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1648	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1649	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1650
AnnaBridge	171:3a7713b1edbc	1651	/* Bit 23 : Pin 23. */
AnnaBridge	171:3a7713b1edbc	1652	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1653	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1654	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1655	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1656	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1657
AnnaBridge	171:3a7713b1edbc	1658	/* Bit 22 : Pin 22. */
AnnaBridge	171:3a7713b1edbc	1659	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1660	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1661	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1662	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1663	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1664
AnnaBridge	171:3a7713b1edbc	1665	/* Bit 21 : Pin 21. */
AnnaBridge	171:3a7713b1edbc	1666	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1667	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1668	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1669	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1670	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1671
AnnaBridge	171:3a7713b1edbc	1672	/* Bit 20 : Pin 20. */
AnnaBridge	171:3a7713b1edbc	1673	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1674	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1675	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1676	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1677	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1678
AnnaBridge	171:3a7713b1edbc	1679	/* Bit 19 : Pin 19. */
AnnaBridge	171:3a7713b1edbc	1680	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1681	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1682	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1683	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1684	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1685
AnnaBridge	171:3a7713b1edbc	1686	/* Bit 18 : Pin 18. */
AnnaBridge	171:3a7713b1edbc	1687	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1688	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1689	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1690	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1691	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1692
AnnaBridge	171:3a7713b1edbc	1693	/* Bit 17 : Pin 17. */
AnnaBridge	171:3a7713b1edbc	1694	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1695	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1696	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1697	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1698	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1699
AnnaBridge	171:3a7713b1edbc	1700	/* Bit 16 : Pin 16. */
AnnaBridge	171:3a7713b1edbc	1701	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1702	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1703	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1704	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1705	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1706
AnnaBridge	171:3a7713b1edbc	1707	/* Bit 15 : Pin 15. */
AnnaBridge	171:3a7713b1edbc	1708	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1709	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1710	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1711	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1712	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1713
AnnaBridge	171:3a7713b1edbc	1714	/* Bit 14 : Pin 14. */
AnnaBridge	171:3a7713b1edbc	1715	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1716	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1717	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1718	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1719	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1720
AnnaBridge	171:3a7713b1edbc	1721	/* Bit 13 : Pin 13. */
AnnaBridge	171:3a7713b1edbc	1722	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1723	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1724	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1725	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1726	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1727
AnnaBridge	171:3a7713b1edbc	1728	/* Bit 12 : Pin 12. */
AnnaBridge	171:3a7713b1edbc	1729	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1730	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1731	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1732	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1733	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1734
AnnaBridge	171:3a7713b1edbc	1735	/* Bit 11 : Pin 11. */
AnnaBridge	171:3a7713b1edbc	1736	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1737	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1738	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1739	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1740	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1741
AnnaBridge	171:3a7713b1edbc	1742	/* Bit 10 : Pin 10. */
AnnaBridge	171:3a7713b1edbc	1743	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1744	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1745	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1746	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1747	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1748
AnnaBridge	171:3a7713b1edbc	1749	/* Bit 9 : Pin 9. */
AnnaBridge	171:3a7713b1edbc	1750	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1751	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1752	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1753	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1754	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1755
AnnaBridge	171:3a7713b1edbc	1756	/* Bit 8 : Pin 8. */
AnnaBridge	171:3a7713b1edbc	1757	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1758	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1759	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1760	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1761	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1762
AnnaBridge	171:3a7713b1edbc	1763	/* Bit 7 : Pin 7. */
AnnaBridge	171:3a7713b1edbc	1764	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1765	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1766	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1767	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1768	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1769
AnnaBridge	171:3a7713b1edbc	1770	/* Bit 6 : Pin 6. */
AnnaBridge	171:3a7713b1edbc	1771	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1772	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1773	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1774	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1775	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1776
AnnaBridge	171:3a7713b1edbc	1777	/* Bit 5 : Pin 5. */
AnnaBridge	171:3a7713b1edbc	1778	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1779	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1780	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1781	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1782	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1783
AnnaBridge	171:3a7713b1edbc	1784	/* Bit 4 : Pin 4. */
AnnaBridge	171:3a7713b1edbc	1785	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1786	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1787	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1788	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1789	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1790
AnnaBridge	171:3a7713b1edbc	1791	/* Bit 3 : Pin 3. */
AnnaBridge	171:3a7713b1edbc	1792	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1793	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1794	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1795	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1796	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1797
AnnaBridge	171:3a7713b1edbc	1798	/* Bit 2 : Pin 2. */
AnnaBridge	171:3a7713b1edbc	1799	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1800	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1801	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1802	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1803	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1804
AnnaBridge	171:3a7713b1edbc	1805	/* Bit 1 : Pin 1. */
AnnaBridge	171:3a7713b1edbc	1806	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	1807	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	1808	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1809	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1810	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1811
AnnaBridge	171:3a7713b1edbc	1812	/* Bit 0 : Pin 0. */
AnnaBridge	171:3a7713b1edbc	1813	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	1814	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	1815	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
AnnaBridge	171:3a7713b1edbc	1816	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
AnnaBridge	171:3a7713b1edbc	1817	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
AnnaBridge	171:3a7713b1edbc	1818
AnnaBridge	171:3a7713b1edbc	1819	/* Register: GPIO_IN */
AnnaBridge	171:3a7713b1edbc	1820	/* Description: Read GPIO port. */
AnnaBridge	171:3a7713b1edbc	1821
AnnaBridge	171:3a7713b1edbc	1822	/* Bit 31 : Pin 31. */
AnnaBridge	171:3a7713b1edbc	1823	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1824	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	1825	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1826	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1827
AnnaBridge	171:3a7713b1edbc	1828	/* Bit 30 : Pin 30. */
AnnaBridge	171:3a7713b1edbc	1829	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1830	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	1831	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1832	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1833
AnnaBridge	171:3a7713b1edbc	1834	/* Bit 29 : Pin 29. */
AnnaBridge	171:3a7713b1edbc	1835	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1836	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	1837	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1838	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1839
AnnaBridge	171:3a7713b1edbc	1840	/* Bit 28 : Pin 28. */
AnnaBridge	171:3a7713b1edbc	1841	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1842	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	1843	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1844	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1845
AnnaBridge	171:3a7713b1edbc	1846	/* Bit 27 : Pin 27. */
AnnaBridge	171:3a7713b1edbc	1847	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1848	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	1849	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1850	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1851
AnnaBridge	171:3a7713b1edbc	1852	/* Bit 26 : Pin 26. */
AnnaBridge	171:3a7713b1edbc	1853	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1854	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	1855	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1856	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1857
AnnaBridge	171:3a7713b1edbc	1858	/* Bit 25 : Pin 25. */
AnnaBridge	171:3a7713b1edbc	1859	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1860	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	1861	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1862	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1863
AnnaBridge	171:3a7713b1edbc	1864	/* Bit 24 : Pin 24. */
AnnaBridge	171:3a7713b1edbc	1865	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1866	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	1867	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1868	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1869
AnnaBridge	171:3a7713b1edbc	1870	/* Bit 23 : Pin 23. */
AnnaBridge	171:3a7713b1edbc	1871	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1872	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	1873	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1874	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1875
AnnaBridge	171:3a7713b1edbc	1876	/* Bit 22 : Pin 22. */
AnnaBridge	171:3a7713b1edbc	1877	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1878	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	1879	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1880	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1881
AnnaBridge	171:3a7713b1edbc	1882	/* Bit 21 : Pin 21. */
AnnaBridge	171:3a7713b1edbc	1883	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1884	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	1885	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1886	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1887
AnnaBridge	171:3a7713b1edbc	1888	/* Bit 20 : Pin 20. */
AnnaBridge	171:3a7713b1edbc	1889	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1890	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	1891	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1892	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1893
AnnaBridge	171:3a7713b1edbc	1894	/* Bit 19 : Pin 19. */
AnnaBridge	171:3a7713b1edbc	1895	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1896	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	1897	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1898	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1899
AnnaBridge	171:3a7713b1edbc	1900	/* Bit 18 : Pin 18. */
AnnaBridge	171:3a7713b1edbc	1901	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1902	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	1903	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1904	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1905
AnnaBridge	171:3a7713b1edbc	1906	/* Bit 17 : Pin 17. */
AnnaBridge	171:3a7713b1edbc	1907	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1908	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	1909	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1910	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1911
AnnaBridge	171:3a7713b1edbc	1912	/* Bit 16 : Pin 16. */
AnnaBridge	171:3a7713b1edbc	1913	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1914	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	1915	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1916	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1917
AnnaBridge	171:3a7713b1edbc	1918	/* Bit 15 : Pin 15. */
AnnaBridge	171:3a7713b1edbc	1919	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1920	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	1921	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1922	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1923
AnnaBridge	171:3a7713b1edbc	1924	/* Bit 14 : Pin 14. */
AnnaBridge	171:3a7713b1edbc	1925	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1926	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	1927	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1928	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1929
AnnaBridge	171:3a7713b1edbc	1930	/* Bit 13 : Pin 13. */
AnnaBridge	171:3a7713b1edbc	1931	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1932	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	1933	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1934	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1935
AnnaBridge	171:3a7713b1edbc	1936	/* Bit 12 : Pin 12. */
AnnaBridge	171:3a7713b1edbc	1937	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1938	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	1939	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1940	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1941
AnnaBridge	171:3a7713b1edbc	1942	/* Bit 11 : Pin 11. */
AnnaBridge	171:3a7713b1edbc	1943	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1944	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	1945	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1946	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1947
AnnaBridge	171:3a7713b1edbc	1948	/* Bit 10 : Pin 10. */
AnnaBridge	171:3a7713b1edbc	1949	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1950	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	1951	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1952	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1953
AnnaBridge	171:3a7713b1edbc	1954	/* Bit 9 : Pin 9. */
AnnaBridge	171:3a7713b1edbc	1955	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1956	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	1957	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1958	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1959
AnnaBridge	171:3a7713b1edbc	1960	/* Bit 8 : Pin 8. */
AnnaBridge	171:3a7713b1edbc	1961	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1962	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	1963	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1964	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1965
AnnaBridge	171:3a7713b1edbc	1966	/* Bit 7 : Pin 7. */
AnnaBridge	171:3a7713b1edbc	1967	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1968	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	1969	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1970	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1971
AnnaBridge	171:3a7713b1edbc	1972	/* Bit 6 : Pin 6. */
AnnaBridge	171:3a7713b1edbc	1973	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1974	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	1975	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1976	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1977
AnnaBridge	171:3a7713b1edbc	1978	/* Bit 5 : Pin 5. */
AnnaBridge	171:3a7713b1edbc	1979	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1980	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	1981	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1982	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1983
AnnaBridge	171:3a7713b1edbc	1984	/* Bit 4 : Pin 4. */
AnnaBridge	171:3a7713b1edbc	1985	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1986	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	1987	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1988	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1989
AnnaBridge	171:3a7713b1edbc	1990	/* Bit 3 : Pin 3. */
AnnaBridge	171:3a7713b1edbc	1991	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1992	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	1993	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	1994	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	1995
AnnaBridge	171:3a7713b1edbc	1996	/* Bit 2 : Pin 2. */
AnnaBridge	171:3a7713b1edbc	1997	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1998	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	1999	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	2000	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	2001
AnnaBridge	171:3a7713b1edbc	2002	/* Bit 1 : Pin 1. */
AnnaBridge	171:3a7713b1edbc	2003	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2004	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2005	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	2006	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	2007
AnnaBridge	171:3a7713b1edbc	2008	/* Bit 0 : Pin 0. */
AnnaBridge	171:3a7713b1edbc	2009	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2010	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2011	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
AnnaBridge	171:3a7713b1edbc	2012	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
AnnaBridge	171:3a7713b1edbc	2013
AnnaBridge	171:3a7713b1edbc	2014	/* Register: GPIO_DIR */
AnnaBridge	171:3a7713b1edbc	2015	/* Description: Direction of GPIO pins. */
AnnaBridge	171:3a7713b1edbc	2016
AnnaBridge	171:3a7713b1edbc	2017	/* Bit 31 : Pin 31. */
AnnaBridge	171:3a7713b1edbc	2018	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	2019	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	2020	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2021	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2022
AnnaBridge	171:3a7713b1edbc	2023	/* Bit 30 : Pin 30. */
AnnaBridge	171:3a7713b1edbc	2024	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	2025	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	2026	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2027	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2028
AnnaBridge	171:3a7713b1edbc	2029	/* Bit 29 : Pin 29. */
AnnaBridge	171:3a7713b1edbc	2030	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	2031	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	2032	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2033	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2034
AnnaBridge	171:3a7713b1edbc	2035	/* Bit 28 : Pin 28. */
AnnaBridge	171:3a7713b1edbc	2036	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	2037	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	2038	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2039	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2040
AnnaBridge	171:3a7713b1edbc	2041	/* Bit 27 : Pin 27. */
AnnaBridge	171:3a7713b1edbc	2042	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	2043	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	2044	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2045	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2046
AnnaBridge	171:3a7713b1edbc	2047	/* Bit 26 : Pin 26. */
AnnaBridge	171:3a7713b1edbc	2048	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	2049	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	2050	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2051	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2052
AnnaBridge	171:3a7713b1edbc	2053	/* Bit 25 : Pin 25. */
AnnaBridge	171:3a7713b1edbc	2054	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	2055	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	2056	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2057	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2058
AnnaBridge	171:3a7713b1edbc	2059	/* Bit 24 : Pin 24. */
AnnaBridge	171:3a7713b1edbc	2060	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	2061	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	2062	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2063	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2064
AnnaBridge	171:3a7713b1edbc	2065	/* Bit 23 : Pin 23. */
AnnaBridge	171:3a7713b1edbc	2066	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	2067	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	2068	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2069	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2070
AnnaBridge	171:3a7713b1edbc	2071	/* Bit 22 : Pin 22. */
AnnaBridge	171:3a7713b1edbc	2072	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	2073	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	2074	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2075	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2076
AnnaBridge	171:3a7713b1edbc	2077	/* Bit 21 : Pin 21. */
AnnaBridge	171:3a7713b1edbc	2078	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	2079	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	2080	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2081	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2082
AnnaBridge	171:3a7713b1edbc	2083	/* Bit 20 : Pin 20. */
AnnaBridge	171:3a7713b1edbc	2084	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	2085	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	2086	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2087	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2088
AnnaBridge	171:3a7713b1edbc	2089	/* Bit 19 : Pin 19. */
AnnaBridge	171:3a7713b1edbc	2090	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	2091	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	2092	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2093	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2094
AnnaBridge	171:3a7713b1edbc	2095	/* Bit 18 : Pin 18. */
AnnaBridge	171:3a7713b1edbc	2096	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	2097	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	2098	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2099	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2100
AnnaBridge	171:3a7713b1edbc	2101	/* Bit 17 : Pin 17. */
AnnaBridge	171:3a7713b1edbc	2102	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	2103	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	2104	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2105	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2106
AnnaBridge	171:3a7713b1edbc	2107	/* Bit 16 : Pin 16. */
AnnaBridge	171:3a7713b1edbc	2108	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	2109	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	2110	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2111	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2112
AnnaBridge	171:3a7713b1edbc	2113	/* Bit 15 : Pin 15. */
AnnaBridge	171:3a7713b1edbc	2114	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	2115	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	2116	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2117	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2118
AnnaBridge	171:3a7713b1edbc	2119	/* Bit 14 : Pin 14. */
AnnaBridge	171:3a7713b1edbc	2120	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	2121	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	2122	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2123	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2124
AnnaBridge	171:3a7713b1edbc	2125	/* Bit 13 : Pin 13. */
AnnaBridge	171:3a7713b1edbc	2126	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	2127	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	2128	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2129	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2130
AnnaBridge	171:3a7713b1edbc	2131	/* Bit 12 : Pin 12. */
AnnaBridge	171:3a7713b1edbc	2132	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	2133	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	2134	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2135	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2136
AnnaBridge	171:3a7713b1edbc	2137	/* Bit 11 : Pin 11. */
AnnaBridge	171:3a7713b1edbc	2138	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	2139	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	2140	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2141	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2142
AnnaBridge	171:3a7713b1edbc	2143	/* Bit 10 : Pin 10. */
AnnaBridge	171:3a7713b1edbc	2144	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	2145	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	2146	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2147	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2148
AnnaBridge	171:3a7713b1edbc	2149	/* Bit 9 : Pin 9. */
AnnaBridge	171:3a7713b1edbc	2150	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	2151	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	2152	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2153	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2154
AnnaBridge	171:3a7713b1edbc	2155	/* Bit 8 : Pin 8. */
AnnaBridge	171:3a7713b1edbc	2156	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	2157	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	2158	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2159	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2160
AnnaBridge	171:3a7713b1edbc	2161	/* Bit 7 : Pin 7. */
AnnaBridge	171:3a7713b1edbc	2162	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	2163	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	2164	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2165	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2166
AnnaBridge	171:3a7713b1edbc	2167	/* Bit 6 : Pin 6. */
AnnaBridge	171:3a7713b1edbc	2168	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	2169	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	2170	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2171	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2172
AnnaBridge	171:3a7713b1edbc	2173	/* Bit 5 : Pin 5. */
AnnaBridge	171:3a7713b1edbc	2174	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	2175	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	2176	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2177	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2178
AnnaBridge	171:3a7713b1edbc	2179	/* Bit 4 : Pin 4. */
AnnaBridge	171:3a7713b1edbc	2180	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	2181	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	2182	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2183	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2184
AnnaBridge	171:3a7713b1edbc	2185	/* Bit 3 : Pin 3. */
AnnaBridge	171:3a7713b1edbc	2186	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	2187	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	2188	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2189	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2190
AnnaBridge	171:3a7713b1edbc	2191	/* Bit 2 : Pin 2. */
AnnaBridge	171:3a7713b1edbc	2192	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	2193	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	2194	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2195	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2196
AnnaBridge	171:3a7713b1edbc	2197	/* Bit 1 : Pin 1. */
AnnaBridge	171:3a7713b1edbc	2198	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2199	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2200	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2201	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2202
AnnaBridge	171:3a7713b1edbc	2203	/* Bit 0 : Pin 0. */
AnnaBridge	171:3a7713b1edbc	2204	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2205	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2206	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2207	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2208
AnnaBridge	171:3a7713b1edbc	2209	/* Register: GPIO_DIRSET */
AnnaBridge	171:3a7713b1edbc	2210	/* Description: DIR set register. */
AnnaBridge	171:3a7713b1edbc	2211
AnnaBridge	171:3a7713b1edbc	2212	/* Bit 31 : Set as output pin 31. */
AnnaBridge	171:3a7713b1edbc	2213	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	2214	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	2215	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2216	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2217	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2218
AnnaBridge	171:3a7713b1edbc	2219	/* Bit 30 : Set as output pin 30. */
AnnaBridge	171:3a7713b1edbc	2220	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	2221	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	2222	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2223	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2224	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2225
AnnaBridge	171:3a7713b1edbc	2226	/* Bit 29 : Set as output pin 29. */
AnnaBridge	171:3a7713b1edbc	2227	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	2228	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	2229	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2230	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2231	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2232
AnnaBridge	171:3a7713b1edbc	2233	/* Bit 28 : Set as output pin 28. */
AnnaBridge	171:3a7713b1edbc	2234	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	2235	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	2236	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2237	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2238	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2239
AnnaBridge	171:3a7713b1edbc	2240	/* Bit 27 : Set as output pin 27. */
AnnaBridge	171:3a7713b1edbc	2241	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	2242	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	2243	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2244	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2245	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2246
AnnaBridge	171:3a7713b1edbc	2247	/* Bit 26 : Set as output pin 26. */
AnnaBridge	171:3a7713b1edbc	2248	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	2249	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	2250	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2251	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2252	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2253
AnnaBridge	171:3a7713b1edbc	2254	/* Bit 25 : Set as output pin 25. */
AnnaBridge	171:3a7713b1edbc	2255	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	2256	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	2257	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2258	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2259	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2260
AnnaBridge	171:3a7713b1edbc	2261	/* Bit 24 : Set as output pin 24. */
AnnaBridge	171:3a7713b1edbc	2262	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	2263	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	2264	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2265	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2266	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2267
AnnaBridge	171:3a7713b1edbc	2268	/* Bit 23 : Set as output pin 23. */
AnnaBridge	171:3a7713b1edbc	2269	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	2270	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	2271	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2272	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2273	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2274
AnnaBridge	171:3a7713b1edbc	2275	/* Bit 22 : Set as output pin 22. */
AnnaBridge	171:3a7713b1edbc	2276	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	2277	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	2278	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2279	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2280	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2281
AnnaBridge	171:3a7713b1edbc	2282	/* Bit 21 : Set as output pin 21. */
AnnaBridge	171:3a7713b1edbc	2283	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	2284	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	2285	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2286	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2287	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2288
AnnaBridge	171:3a7713b1edbc	2289	/* Bit 20 : Set as output pin 20. */
AnnaBridge	171:3a7713b1edbc	2290	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	2291	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	2292	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2293	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2294	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2295
AnnaBridge	171:3a7713b1edbc	2296	/* Bit 19 : Set as output pin 19. */
AnnaBridge	171:3a7713b1edbc	2297	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	2298	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	2299	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2300	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2301	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2302
AnnaBridge	171:3a7713b1edbc	2303	/* Bit 18 : Set as output pin 18. */
AnnaBridge	171:3a7713b1edbc	2304	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	2305	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	2306	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2307	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2308	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2309
AnnaBridge	171:3a7713b1edbc	2310	/* Bit 17 : Set as output pin 17. */
AnnaBridge	171:3a7713b1edbc	2311	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	2312	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	2313	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2314	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2315	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2316
AnnaBridge	171:3a7713b1edbc	2317	/* Bit 16 : Set as output pin 16. */
AnnaBridge	171:3a7713b1edbc	2318	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	2319	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	2320	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2321	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2322	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2323
AnnaBridge	171:3a7713b1edbc	2324	/* Bit 15 : Set as output pin 15. */
AnnaBridge	171:3a7713b1edbc	2325	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	2326	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	2327	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2328	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2329	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2330
AnnaBridge	171:3a7713b1edbc	2331	/* Bit 14 : Set as output pin 14. */
AnnaBridge	171:3a7713b1edbc	2332	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	2333	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	2334	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2335	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2336	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2337
AnnaBridge	171:3a7713b1edbc	2338	/* Bit 13 : Set as output pin 13. */
AnnaBridge	171:3a7713b1edbc	2339	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	2340	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	2341	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2342	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2343	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2344
AnnaBridge	171:3a7713b1edbc	2345	/* Bit 12 : Set as output pin 12. */
AnnaBridge	171:3a7713b1edbc	2346	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	2347	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	2348	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2349	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2350	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2351
AnnaBridge	171:3a7713b1edbc	2352	/* Bit 11 : Set as output pin 11. */
AnnaBridge	171:3a7713b1edbc	2353	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	2354	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	2355	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2356	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2357	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2358
AnnaBridge	171:3a7713b1edbc	2359	/* Bit 10 : Set as output pin 10. */
AnnaBridge	171:3a7713b1edbc	2360	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	2361	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	2362	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2363	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2364	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2365
AnnaBridge	171:3a7713b1edbc	2366	/* Bit 9 : Set as output pin 9. */
AnnaBridge	171:3a7713b1edbc	2367	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	2368	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	2369	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2370	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2371	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2372
AnnaBridge	171:3a7713b1edbc	2373	/* Bit 8 : Set as output pin 8. */
AnnaBridge	171:3a7713b1edbc	2374	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	2375	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	2376	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2377	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2378	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2379
AnnaBridge	171:3a7713b1edbc	2380	/* Bit 7 : Set as output pin 7. */
AnnaBridge	171:3a7713b1edbc	2381	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	2382	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	2383	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2384	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2385	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2386
AnnaBridge	171:3a7713b1edbc	2387	/* Bit 6 : Set as output pin 6. */
AnnaBridge	171:3a7713b1edbc	2388	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	2389	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	2390	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2391	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2392	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2393
AnnaBridge	171:3a7713b1edbc	2394	/* Bit 5 : Set as output pin 5. */
AnnaBridge	171:3a7713b1edbc	2395	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	2396	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	2397	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2398	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2399	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2400
AnnaBridge	171:3a7713b1edbc	2401	/* Bit 4 : Set as output pin 4. */
AnnaBridge	171:3a7713b1edbc	2402	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	2403	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	2404	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2405	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2406	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2407
AnnaBridge	171:3a7713b1edbc	2408	/* Bit 3 : Set as output pin 3. */
AnnaBridge	171:3a7713b1edbc	2409	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	2410	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	2411	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2412	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2413	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2414
AnnaBridge	171:3a7713b1edbc	2415	/* Bit 2 : Set as output pin 2. */
AnnaBridge	171:3a7713b1edbc	2416	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	2417	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	2418	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2419	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2420	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2421
AnnaBridge	171:3a7713b1edbc	2422	/* Bit 1 : Set as output pin 1. */
AnnaBridge	171:3a7713b1edbc	2423	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2424	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2425	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2426	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2427	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2428
AnnaBridge	171:3a7713b1edbc	2429	/* Bit 0 : Set as output pin 0. */
AnnaBridge	171:3a7713b1edbc	2430	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2431	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2432	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2433	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2434	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
AnnaBridge	171:3a7713b1edbc	2435
AnnaBridge	171:3a7713b1edbc	2436	/* Register: GPIO_DIRCLR */
AnnaBridge	171:3a7713b1edbc	2437	/* Description: DIR clear register. */
AnnaBridge	171:3a7713b1edbc	2438
AnnaBridge	171:3a7713b1edbc	2439	/* Bit 31 : Set as input pin 31. */
AnnaBridge	171:3a7713b1edbc	2440	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	2441	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
AnnaBridge	171:3a7713b1edbc	2442	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2443	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2444	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2445
AnnaBridge	171:3a7713b1edbc	2446	/* Bit 30 : Set as input pin 30. */
AnnaBridge	171:3a7713b1edbc	2447	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	2448	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
AnnaBridge	171:3a7713b1edbc	2449	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2450	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2451	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2452
AnnaBridge	171:3a7713b1edbc	2453	/* Bit 29 : Set as input pin 29. */
AnnaBridge	171:3a7713b1edbc	2454	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	2455	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
AnnaBridge	171:3a7713b1edbc	2456	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2457	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2458	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2459
AnnaBridge	171:3a7713b1edbc	2460	/* Bit 28 : Set as input pin 28. */
AnnaBridge	171:3a7713b1edbc	2461	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	2462	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
AnnaBridge	171:3a7713b1edbc	2463	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2464	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2465	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2466
AnnaBridge	171:3a7713b1edbc	2467	/* Bit 27 : Set as input pin 27. */
AnnaBridge	171:3a7713b1edbc	2468	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	2469	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
AnnaBridge	171:3a7713b1edbc	2470	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2471	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2472	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2473
AnnaBridge	171:3a7713b1edbc	2474	/* Bit 26 : Set as input pin 26. */
AnnaBridge	171:3a7713b1edbc	2475	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	2476	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
AnnaBridge	171:3a7713b1edbc	2477	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2478	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2479	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2480
AnnaBridge	171:3a7713b1edbc	2481	/* Bit 25 : Set as input pin 25. */
AnnaBridge	171:3a7713b1edbc	2482	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	2483	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
AnnaBridge	171:3a7713b1edbc	2484	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2485	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2486	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2487
AnnaBridge	171:3a7713b1edbc	2488	/* Bit 24 : Set as input pin 24. */
AnnaBridge	171:3a7713b1edbc	2489	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	2490	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
AnnaBridge	171:3a7713b1edbc	2491	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2492	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2493	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2494
AnnaBridge	171:3a7713b1edbc	2495	/* Bit 23 : Set as input pin 23. */
AnnaBridge	171:3a7713b1edbc	2496	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	2497	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
AnnaBridge	171:3a7713b1edbc	2498	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2499	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2500	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2501
AnnaBridge	171:3a7713b1edbc	2502	/* Bit 22 : Set as input pin 22. */
AnnaBridge	171:3a7713b1edbc	2503	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	2504	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
AnnaBridge	171:3a7713b1edbc	2505	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2506	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2507	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2508
AnnaBridge	171:3a7713b1edbc	2509	/* Bit 21 : Set as input pin 21. */
AnnaBridge	171:3a7713b1edbc	2510	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	2511	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
AnnaBridge	171:3a7713b1edbc	2512	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2513	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2514	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2515
AnnaBridge	171:3a7713b1edbc	2516	/* Bit 20 : Set as input pin 20. */
AnnaBridge	171:3a7713b1edbc	2517	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	2518	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
AnnaBridge	171:3a7713b1edbc	2519	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2520	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2521	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2522
AnnaBridge	171:3a7713b1edbc	2523	/* Bit 19 : Set as input pin 19. */
AnnaBridge	171:3a7713b1edbc	2524	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	2525	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
AnnaBridge	171:3a7713b1edbc	2526	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2527	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2528	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2529
AnnaBridge	171:3a7713b1edbc	2530	/* Bit 18 : Set as input pin 18. */
AnnaBridge	171:3a7713b1edbc	2531	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	2532	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
AnnaBridge	171:3a7713b1edbc	2533	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2534	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2535	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2536
AnnaBridge	171:3a7713b1edbc	2537	/* Bit 17 : Set as input pin 17. */
AnnaBridge	171:3a7713b1edbc	2538	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	2539	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
AnnaBridge	171:3a7713b1edbc	2540	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2541	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2542	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2543
AnnaBridge	171:3a7713b1edbc	2544	/* Bit 16 : Set as input pin 16. */
AnnaBridge	171:3a7713b1edbc	2545	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	2546	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
AnnaBridge	171:3a7713b1edbc	2547	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2548	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2549	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2550
AnnaBridge	171:3a7713b1edbc	2551	/* Bit 15 : Set as input pin 15. */
AnnaBridge	171:3a7713b1edbc	2552	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	2553	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
AnnaBridge	171:3a7713b1edbc	2554	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2555	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2556	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2557
AnnaBridge	171:3a7713b1edbc	2558	/* Bit 14 : Set as input pin 14. */
AnnaBridge	171:3a7713b1edbc	2559	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	2560	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
AnnaBridge	171:3a7713b1edbc	2561	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2562	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2563	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2564
AnnaBridge	171:3a7713b1edbc	2565	/* Bit 13 : Set as input pin 13. */
AnnaBridge	171:3a7713b1edbc	2566	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	2567	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
AnnaBridge	171:3a7713b1edbc	2568	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2569	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2570	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2571
AnnaBridge	171:3a7713b1edbc	2572	/* Bit 12 : Set as input pin 12. */
AnnaBridge	171:3a7713b1edbc	2573	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	2574	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
AnnaBridge	171:3a7713b1edbc	2575	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2576	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2577	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2578
AnnaBridge	171:3a7713b1edbc	2579	/* Bit 11 : Set as input pin 11. */
AnnaBridge	171:3a7713b1edbc	2580	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	2581	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
AnnaBridge	171:3a7713b1edbc	2582	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2583	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2584	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2585
AnnaBridge	171:3a7713b1edbc	2586	/* Bit 10 : Set as input pin 10. */
AnnaBridge	171:3a7713b1edbc	2587	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	2588	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
AnnaBridge	171:3a7713b1edbc	2589	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2590	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2591	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2592
AnnaBridge	171:3a7713b1edbc	2593	/* Bit 9 : Set as input pin 9. */
AnnaBridge	171:3a7713b1edbc	2594	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	2595	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
AnnaBridge	171:3a7713b1edbc	2596	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2597	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2598	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2599
AnnaBridge	171:3a7713b1edbc	2600	/* Bit 8 : Set as input pin 8. */
AnnaBridge	171:3a7713b1edbc	2601	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	2602	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
AnnaBridge	171:3a7713b1edbc	2603	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2604	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2605	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2606
AnnaBridge	171:3a7713b1edbc	2607	/* Bit 7 : Set as input pin 7. */
AnnaBridge	171:3a7713b1edbc	2608	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	2609	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
AnnaBridge	171:3a7713b1edbc	2610	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2611	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2612	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2613
AnnaBridge	171:3a7713b1edbc	2614	/* Bit 6 : Set as input pin 6. */
AnnaBridge	171:3a7713b1edbc	2615	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	2616	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
AnnaBridge	171:3a7713b1edbc	2617	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2618	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2619	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2620
AnnaBridge	171:3a7713b1edbc	2621	/* Bit 5 : Set as input pin 5. */
AnnaBridge	171:3a7713b1edbc	2622	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	2623	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
AnnaBridge	171:3a7713b1edbc	2624	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2625	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2626	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2627
AnnaBridge	171:3a7713b1edbc	2628	/* Bit 4 : Set as input pin 4. */
AnnaBridge	171:3a7713b1edbc	2629	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	2630	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
AnnaBridge	171:3a7713b1edbc	2631	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2632	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2633	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2634
AnnaBridge	171:3a7713b1edbc	2635	/* Bit 3 : Set as input pin 3. */
AnnaBridge	171:3a7713b1edbc	2636	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	2637	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
AnnaBridge	171:3a7713b1edbc	2638	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2639	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2640	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2641
AnnaBridge	171:3a7713b1edbc	2642	/* Bit 2 : Set as input pin 2. */
AnnaBridge	171:3a7713b1edbc	2643	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	2644	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
AnnaBridge	171:3a7713b1edbc	2645	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2646	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2647	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2648
AnnaBridge	171:3a7713b1edbc	2649	/* Bit 1 : Set as input pin 1. */
AnnaBridge	171:3a7713b1edbc	2650	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2651	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
AnnaBridge	171:3a7713b1edbc	2652	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2653	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2654	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2655
AnnaBridge	171:3a7713b1edbc	2656	/* Bit 0 : Set as input pin 0. */
AnnaBridge	171:3a7713b1edbc	2657	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2658	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
AnnaBridge	171:3a7713b1edbc	2659	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
AnnaBridge	171:3a7713b1edbc	2660	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
AnnaBridge	171:3a7713b1edbc	2661	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
AnnaBridge	171:3a7713b1edbc	2662
AnnaBridge	171:3a7713b1edbc	2663	/* Register: GPIO_PIN_CNF */
AnnaBridge	171:3a7713b1edbc	2664	/* Description: Configuration of GPIO pins. */
AnnaBridge	171:3a7713b1edbc	2665
AnnaBridge	171:3a7713b1edbc	2666	/* Bits 17..16 : Pin sensing mechanism. */
AnnaBridge	171:3a7713b1edbc	2667	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
AnnaBridge	171:3a7713b1edbc	2668	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
AnnaBridge	171:3a7713b1edbc	2669	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	2670	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
AnnaBridge	171:3a7713b1edbc	2671	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
AnnaBridge	171:3a7713b1edbc	2672
AnnaBridge	171:3a7713b1edbc	2673	/* Bits 10..8 : Drive configuration. */
AnnaBridge	171:3a7713b1edbc	2674	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
AnnaBridge	171:3a7713b1edbc	2675	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
AnnaBridge	171:3a7713b1edbc	2676	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
AnnaBridge	171:3a7713b1edbc	2677	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
AnnaBridge	171:3a7713b1edbc	2678	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
AnnaBridge	171:3a7713b1edbc	2679	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
AnnaBridge	171:3a7713b1edbc	2680	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
AnnaBridge	171:3a7713b1edbc	2681	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
AnnaBridge	171:3a7713b1edbc	2682	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
AnnaBridge	171:3a7713b1edbc	2683	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
AnnaBridge	171:3a7713b1edbc	2684
AnnaBridge	171:3a7713b1edbc	2685	/* Bits 3..2 : Pull-up or -down configuration. */
AnnaBridge	171:3a7713b1edbc	2686	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
AnnaBridge	171:3a7713b1edbc	2687	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
AnnaBridge	171:3a7713b1edbc	2688	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
AnnaBridge	171:3a7713b1edbc	2689	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
AnnaBridge	171:3a7713b1edbc	2690	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
AnnaBridge	171:3a7713b1edbc	2691
AnnaBridge	171:3a7713b1edbc	2692	/* Bit 1 : Connect or disconnect input path. */
AnnaBridge	171:3a7713b1edbc	2693	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
AnnaBridge	171:3a7713b1edbc	2694	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
AnnaBridge	171:3a7713b1edbc	2695	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
AnnaBridge	171:3a7713b1edbc	2696	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
AnnaBridge	171:3a7713b1edbc	2697
AnnaBridge	171:3a7713b1edbc	2698	/* Bit 0 : Pin direction. */
AnnaBridge	171:3a7713b1edbc	2699	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
AnnaBridge	171:3a7713b1edbc	2700	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
AnnaBridge	171:3a7713b1edbc	2701	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
AnnaBridge	171:3a7713b1edbc	2702	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
AnnaBridge	171:3a7713b1edbc	2703
AnnaBridge	171:3a7713b1edbc	2704
AnnaBridge	171:3a7713b1edbc	2705	/* Peripheral: GPIOTE */
AnnaBridge	171:3a7713b1edbc	2706	/* Description: GPIO tasks and events. */
AnnaBridge	171:3a7713b1edbc	2707
AnnaBridge	171:3a7713b1edbc	2708	/* Register: GPIOTE_INTENSET */
AnnaBridge	171:3a7713b1edbc	2709	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	2710
AnnaBridge	171:3a7713b1edbc	2711	/* Bit 31 : Enable interrupt on PORT event. */
AnnaBridge	171:3a7713b1edbc	2712	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
AnnaBridge	171:3a7713b1edbc	2713	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
AnnaBridge	171:3a7713b1edbc	2714	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2715	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2716	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2717
AnnaBridge	171:3a7713b1edbc	2718	/* Bit 3 : Enable interrupt on IN[3] event. */
AnnaBridge	171:3a7713b1edbc	2719	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
AnnaBridge	171:3a7713b1edbc	2720	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
AnnaBridge	171:3a7713b1edbc	2721	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2722	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2723	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2724
AnnaBridge	171:3a7713b1edbc	2725	/* Bit 2 : Enable interrupt on IN[2] event. */
AnnaBridge	171:3a7713b1edbc	2726	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
AnnaBridge	171:3a7713b1edbc	2727	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
AnnaBridge	171:3a7713b1edbc	2728	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2729	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2730	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2731
AnnaBridge	171:3a7713b1edbc	2732	/* Bit 1 : Enable interrupt on IN[1] event. */
AnnaBridge	171:3a7713b1edbc	2733	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
AnnaBridge	171:3a7713b1edbc	2734	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
AnnaBridge	171:3a7713b1edbc	2735	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2736	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2737	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2738
AnnaBridge	171:3a7713b1edbc	2739	/* Bit 0 : Enable interrupt on IN[0] event. */
AnnaBridge	171:3a7713b1edbc	2740	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
AnnaBridge	171:3a7713b1edbc	2741	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
AnnaBridge	171:3a7713b1edbc	2742	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2743	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2744	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2745
AnnaBridge	171:3a7713b1edbc	2746	/* Register: GPIOTE_INTENCLR */
AnnaBridge	171:3a7713b1edbc	2747	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	2748
AnnaBridge	171:3a7713b1edbc	2749	/* Bit 31 : Disable interrupt on PORT event. */
AnnaBridge	171:3a7713b1edbc	2750	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
AnnaBridge	171:3a7713b1edbc	2751	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
AnnaBridge	171:3a7713b1edbc	2752	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2753	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2754	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2755
AnnaBridge	171:3a7713b1edbc	2756	/* Bit 3 : Disable interrupt on IN[3] event. */
AnnaBridge	171:3a7713b1edbc	2757	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
AnnaBridge	171:3a7713b1edbc	2758	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
AnnaBridge	171:3a7713b1edbc	2759	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2760	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2761	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2762
AnnaBridge	171:3a7713b1edbc	2763	/* Bit 2 : Disable interrupt on IN[2] event. */
AnnaBridge	171:3a7713b1edbc	2764	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
AnnaBridge	171:3a7713b1edbc	2765	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
AnnaBridge	171:3a7713b1edbc	2766	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2767	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2768	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2769
AnnaBridge	171:3a7713b1edbc	2770	/* Bit 1 : Disable interrupt on IN[1] event. */
AnnaBridge	171:3a7713b1edbc	2771	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
AnnaBridge	171:3a7713b1edbc	2772	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
AnnaBridge	171:3a7713b1edbc	2773	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2774	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2775	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2776
AnnaBridge	171:3a7713b1edbc	2777	/* Bit 0 : Disable interrupt on IN[0] event. */
AnnaBridge	171:3a7713b1edbc	2778	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
AnnaBridge	171:3a7713b1edbc	2779	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
AnnaBridge	171:3a7713b1edbc	2780	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2781	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2782	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2783
AnnaBridge	171:3a7713b1edbc	2784	/* Register: GPIOTE_CONFIG */
AnnaBridge	171:3a7713b1edbc	2785	/* Description: Channel configuration registers. */
AnnaBridge	171:3a7713b1edbc	2786
AnnaBridge	171:3a7713b1edbc	2787	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
AnnaBridge	171:3a7713b1edbc	2788	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
AnnaBridge	171:3a7713b1edbc	2789	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
AnnaBridge	171:3a7713b1edbc	2790	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
AnnaBridge	171:3a7713b1edbc	2791	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
AnnaBridge	171:3a7713b1edbc	2792
AnnaBridge	171:3a7713b1edbc	2793	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
AnnaBridge	171:3a7713b1edbc	2794	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
AnnaBridge	171:3a7713b1edbc	2795	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
AnnaBridge	171:3a7713b1edbc	2796	#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /!< No task or event. /
AnnaBridge	171:3a7713b1edbc	2797	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
AnnaBridge	171:3a7713b1edbc	2798	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
AnnaBridge	171:3a7713b1edbc	2799	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
AnnaBridge	171:3a7713b1edbc	2800
AnnaBridge	171:3a7713b1edbc	2801	/* Bits 12..8 : Pin select. */
AnnaBridge	171:3a7713b1edbc	2802	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
AnnaBridge	171:3a7713b1edbc	2803	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
AnnaBridge	171:3a7713b1edbc	2804
AnnaBridge	171:3a7713b1edbc	2805	/* Bits 1..0 : Mode */
AnnaBridge	171:3a7713b1edbc	2806	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
AnnaBridge	171:3a7713b1edbc	2807	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
AnnaBridge	171:3a7713b1edbc	2808	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	2809	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
AnnaBridge	171:3a7713b1edbc	2810	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
AnnaBridge	171:3a7713b1edbc	2811
AnnaBridge	171:3a7713b1edbc	2812	/* Register: GPIOTE_POWER */
AnnaBridge	171:3a7713b1edbc	2813	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	2814
AnnaBridge	171:3a7713b1edbc	2815	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	2816	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	2817	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	2818	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	2819	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	2820
AnnaBridge	171:3a7713b1edbc	2821
AnnaBridge	171:3a7713b1edbc	2822	/* Peripheral: LPCOMP */
AnnaBridge	171:3a7713b1edbc	2823	/* Description: Low power comparator. */
AnnaBridge	171:3a7713b1edbc	2824
AnnaBridge	171:3a7713b1edbc	2825	/* Register: LPCOMP_SHORTS */
AnnaBridge	171:3a7713b1edbc	2826	/* Description: Shortcuts for the LPCOMP. */
AnnaBridge	171:3a7713b1edbc	2827
AnnaBridge	171:3a7713b1edbc	2828	/* Bit 4 : Shortcut between CROSS event and STOP task. */
AnnaBridge	171:3a7713b1edbc	2829	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
AnnaBridge	171:3a7713b1edbc	2830	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
AnnaBridge	171:3a7713b1edbc	2831	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	2832	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	2833
AnnaBridge	171:3a7713b1edbc	2834	/* Bit 3 : Shortcut between UP event and STOP task. */
AnnaBridge	171:3a7713b1edbc	2835	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
AnnaBridge	171:3a7713b1edbc	2836	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
AnnaBridge	171:3a7713b1edbc	2837	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	2838	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	2839
AnnaBridge	171:3a7713b1edbc	2840	/* Bit 2 : Shortcut between DOWN event and STOP task. */
AnnaBridge	171:3a7713b1edbc	2841	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
AnnaBridge	171:3a7713b1edbc	2842	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
AnnaBridge	171:3a7713b1edbc	2843	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	2844	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	2845
AnnaBridge	171:3a7713b1edbc	2846	/* Bit 1 : Shortcut between RADY event and STOP task. */
AnnaBridge	171:3a7713b1edbc	2847	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
AnnaBridge	171:3a7713b1edbc	2848	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
AnnaBridge	171:3a7713b1edbc	2849	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	2850	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	2851
AnnaBridge	171:3a7713b1edbc	2852	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
AnnaBridge	171:3a7713b1edbc	2853	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
AnnaBridge	171:3a7713b1edbc	2854	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
AnnaBridge	171:3a7713b1edbc	2855	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	2856	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	2857
AnnaBridge	171:3a7713b1edbc	2858	/* Register: LPCOMP_INTENSET */
AnnaBridge	171:3a7713b1edbc	2859	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	2860
AnnaBridge	171:3a7713b1edbc	2861	/* Bit 3 : Enable interrupt on CROSS event. */
AnnaBridge	171:3a7713b1edbc	2862	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
AnnaBridge	171:3a7713b1edbc	2863	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
AnnaBridge	171:3a7713b1edbc	2864	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2865	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2866	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2867
AnnaBridge	171:3a7713b1edbc	2868	/* Bit 2 : Enable interrupt on UP event. */
AnnaBridge	171:3a7713b1edbc	2869	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
AnnaBridge	171:3a7713b1edbc	2870	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
AnnaBridge	171:3a7713b1edbc	2871	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2872	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2873	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2874
AnnaBridge	171:3a7713b1edbc	2875	/* Bit 1 : Enable interrupt on DOWN event. */
AnnaBridge	171:3a7713b1edbc	2876	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
AnnaBridge	171:3a7713b1edbc	2877	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
AnnaBridge	171:3a7713b1edbc	2878	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2879	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2880	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2881
AnnaBridge	171:3a7713b1edbc	2882	/* Bit 0 : Enable interrupt on READY event. */
AnnaBridge	171:3a7713b1edbc	2883	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
AnnaBridge	171:3a7713b1edbc	2884	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
AnnaBridge	171:3a7713b1edbc	2885	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2886	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2887	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2888
AnnaBridge	171:3a7713b1edbc	2889	/* Register: LPCOMP_INTENCLR */
AnnaBridge	171:3a7713b1edbc	2890	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	2891
AnnaBridge	171:3a7713b1edbc	2892	/* Bit 3 : Disable interrupt on CROSS event. */
AnnaBridge	171:3a7713b1edbc	2893	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
AnnaBridge	171:3a7713b1edbc	2894	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
AnnaBridge	171:3a7713b1edbc	2895	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2896	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2897	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2898
AnnaBridge	171:3a7713b1edbc	2899	/* Bit 2 : Disable interrupt on UP event. */
AnnaBridge	171:3a7713b1edbc	2900	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
AnnaBridge	171:3a7713b1edbc	2901	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
AnnaBridge	171:3a7713b1edbc	2902	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2903	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2904	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2905
AnnaBridge	171:3a7713b1edbc	2906	/* Bit 1 : Disable interrupt on DOWN event. */
AnnaBridge	171:3a7713b1edbc	2907	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
AnnaBridge	171:3a7713b1edbc	2908	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
AnnaBridge	171:3a7713b1edbc	2909	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2910	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2911	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2912
AnnaBridge	171:3a7713b1edbc	2913	/* Bit 0 : Disable interrupt on READY event. */
AnnaBridge	171:3a7713b1edbc	2914	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
AnnaBridge	171:3a7713b1edbc	2915	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
AnnaBridge	171:3a7713b1edbc	2916	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	2917	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	2918	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	2919
AnnaBridge	171:3a7713b1edbc	2920	/* Register: LPCOMP_RESULT */
AnnaBridge	171:3a7713b1edbc	2921	/* Description: Result of last compare. */
AnnaBridge	171:3a7713b1edbc	2922
AnnaBridge	171:3a7713b1edbc	2923	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
AnnaBridge	171:3a7713b1edbc	2924	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
AnnaBridge	171:3a7713b1edbc	2925	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
AnnaBridge	171:3a7713b1edbc	2926	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
AnnaBridge	171:3a7713b1edbc	2927	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
AnnaBridge	171:3a7713b1edbc	2928
AnnaBridge	171:3a7713b1edbc	2929	/* Register: LPCOMP_ENABLE */
AnnaBridge	171:3a7713b1edbc	2930	/* Description: Enable the LPCOMP. */
AnnaBridge	171:3a7713b1edbc	2931
AnnaBridge	171:3a7713b1edbc	2932	/* Bits 1..0 : Enable or disable LPCOMP. */
AnnaBridge	171:3a7713b1edbc	2933	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	2934	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	2935	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
AnnaBridge	171:3a7713b1edbc	2936	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
AnnaBridge	171:3a7713b1edbc	2937
AnnaBridge	171:3a7713b1edbc	2938	/* Register: LPCOMP_PSEL */
AnnaBridge	171:3a7713b1edbc	2939	/* Description: Input pin select. */
AnnaBridge	171:3a7713b1edbc	2940
AnnaBridge	171:3a7713b1edbc	2941	/* Bits 2..0 : Analog input pin select. */
AnnaBridge	171:3a7713b1edbc	2942	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
AnnaBridge	171:3a7713b1edbc	2943	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
AnnaBridge	171:3a7713b1edbc	2944	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
AnnaBridge	171:3a7713b1edbc	2945	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
AnnaBridge	171:3a7713b1edbc	2946	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
AnnaBridge	171:3a7713b1edbc	2947	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
AnnaBridge	171:3a7713b1edbc	2948	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
AnnaBridge	171:3a7713b1edbc	2949	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
AnnaBridge	171:3a7713b1edbc	2950	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
AnnaBridge	171:3a7713b1edbc	2951	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
AnnaBridge	171:3a7713b1edbc	2952
AnnaBridge	171:3a7713b1edbc	2953	/* Register: LPCOMP_REFSEL */
AnnaBridge	171:3a7713b1edbc	2954	/* Description: Reference select. */
AnnaBridge	171:3a7713b1edbc	2955
AnnaBridge	171:3a7713b1edbc	2956	/* Bits 2..0 : Reference select. */
AnnaBridge	171:3a7713b1edbc	2957	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
AnnaBridge	171:3a7713b1edbc	2958	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
AnnaBridge	171:3a7713b1edbc	2959	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
AnnaBridge	171:3a7713b1edbc	2960	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
AnnaBridge	171:3a7713b1edbc	2961	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
AnnaBridge	171:3a7713b1edbc	2962	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
AnnaBridge	171:3a7713b1edbc	2963	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
AnnaBridge	171:3a7713b1edbc	2964	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
AnnaBridge	171:3a7713b1edbc	2965	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
AnnaBridge	171:3a7713b1edbc	2966	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
AnnaBridge	171:3a7713b1edbc	2967
AnnaBridge	171:3a7713b1edbc	2968	/* Register: LPCOMP_EXTREFSEL */
AnnaBridge	171:3a7713b1edbc	2969	/* Description: External reference select. */
AnnaBridge	171:3a7713b1edbc	2970
AnnaBridge	171:3a7713b1edbc	2971	/* Bit 0 : External analog reference pin selection. */
AnnaBridge	171:3a7713b1edbc	2972	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
AnnaBridge	171:3a7713b1edbc	2973	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
AnnaBridge	171:3a7713b1edbc	2974	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
AnnaBridge	171:3a7713b1edbc	2975	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
AnnaBridge	171:3a7713b1edbc	2976
AnnaBridge	171:3a7713b1edbc	2977	/* Register: LPCOMP_ANADETECT */
AnnaBridge	171:3a7713b1edbc	2978	/* Description: Analog detect configuration. */
AnnaBridge	171:3a7713b1edbc	2979
AnnaBridge	171:3a7713b1edbc	2980	/* Bits 1..0 : Analog detect configuration. */
AnnaBridge	171:3a7713b1edbc	2981	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
AnnaBridge	171:3a7713b1edbc	2982	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
AnnaBridge	171:3a7713b1edbc	2983	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
AnnaBridge	171:3a7713b1edbc	2984	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
AnnaBridge	171:3a7713b1edbc	2985	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
AnnaBridge	171:3a7713b1edbc	2986
AnnaBridge	171:3a7713b1edbc	2987	/* Register: LPCOMP_POWER */
AnnaBridge	171:3a7713b1edbc	2988	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	2989
AnnaBridge	171:3a7713b1edbc	2990	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	2991	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	2992	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	2993	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	2994	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	2995
AnnaBridge	171:3a7713b1edbc	2996
AnnaBridge	171:3a7713b1edbc	2997	/* Peripheral: MPU */
AnnaBridge	171:3a7713b1edbc	2998	/* Description: Memory Protection Unit. */
AnnaBridge	171:3a7713b1edbc	2999
AnnaBridge	171:3a7713b1edbc	3000	/* Register: MPU_PERR0 */
AnnaBridge	171:3a7713b1edbc	3001	/* Description: Configuration of peripherals in mpu regions. */
AnnaBridge	171:3a7713b1edbc	3002
AnnaBridge	171:3a7713b1edbc	3003	/* Bit 31 : PPI region configuration. */
AnnaBridge	171:3a7713b1edbc	3004	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
AnnaBridge	171:3a7713b1edbc	3005	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
AnnaBridge	171:3a7713b1edbc	3006	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3007	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3008
AnnaBridge	171:3a7713b1edbc	3009	/* Bit 30 : NVMC region configuration. */
AnnaBridge	171:3a7713b1edbc	3010	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
AnnaBridge	171:3a7713b1edbc	3011	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
AnnaBridge	171:3a7713b1edbc	3012	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3013	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3014
AnnaBridge	171:3a7713b1edbc	3015	/* Bit 19 : LPCOMP region configuration. */
AnnaBridge	171:3a7713b1edbc	3016	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
AnnaBridge	171:3a7713b1edbc	3017	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
AnnaBridge	171:3a7713b1edbc	3018	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3019	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3020
AnnaBridge	171:3a7713b1edbc	3021	/* Bit 18 : QDEC region configuration. */
AnnaBridge	171:3a7713b1edbc	3022	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
AnnaBridge	171:3a7713b1edbc	3023	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
AnnaBridge	171:3a7713b1edbc	3024	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3025	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3026
AnnaBridge	171:3a7713b1edbc	3027	/* Bit 17 : RTC1 region configuration. */
AnnaBridge	171:3a7713b1edbc	3028	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
AnnaBridge	171:3a7713b1edbc	3029	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
AnnaBridge	171:3a7713b1edbc	3030	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3031	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3032
AnnaBridge	171:3a7713b1edbc	3033	/* Bit 16 : WDT region configuration. */
AnnaBridge	171:3a7713b1edbc	3034	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
AnnaBridge	171:3a7713b1edbc	3035	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
AnnaBridge	171:3a7713b1edbc	3036	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3037	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3038
AnnaBridge	171:3a7713b1edbc	3039	/* Bit 15 : CCM and AAR region configuration. */
AnnaBridge	171:3a7713b1edbc	3040	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
AnnaBridge	171:3a7713b1edbc	3041	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
AnnaBridge	171:3a7713b1edbc	3042	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3043	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3044
AnnaBridge	171:3a7713b1edbc	3045	/* Bit 14 : ECB region configuration. */
AnnaBridge	171:3a7713b1edbc	3046	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
AnnaBridge	171:3a7713b1edbc	3047	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
AnnaBridge	171:3a7713b1edbc	3048	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3049	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3050
AnnaBridge	171:3a7713b1edbc	3051	/* Bit 13 : RNG region configuration. */
AnnaBridge	171:3a7713b1edbc	3052	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
AnnaBridge	171:3a7713b1edbc	3053	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
AnnaBridge	171:3a7713b1edbc	3054	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3055	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3056
AnnaBridge	171:3a7713b1edbc	3057	/* Bit 12 : TEMP region configuration. */
AnnaBridge	171:3a7713b1edbc	3058	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
AnnaBridge	171:3a7713b1edbc	3059	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
AnnaBridge	171:3a7713b1edbc	3060	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3061	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3062
AnnaBridge	171:3a7713b1edbc	3063	/* Bit 11 : RTC0 region configuration. */
AnnaBridge	171:3a7713b1edbc	3064	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
AnnaBridge	171:3a7713b1edbc	3065	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
AnnaBridge	171:3a7713b1edbc	3066	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3067	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3068
AnnaBridge	171:3a7713b1edbc	3069	/* Bit 10 : TIMER2 region configuration. */
AnnaBridge	171:3a7713b1edbc	3070	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
AnnaBridge	171:3a7713b1edbc	3071	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
AnnaBridge	171:3a7713b1edbc	3072	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3073	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3074
AnnaBridge	171:3a7713b1edbc	3075	/* Bit 9 : TIMER1 region configuration. */
AnnaBridge	171:3a7713b1edbc	3076	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
AnnaBridge	171:3a7713b1edbc	3077	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
AnnaBridge	171:3a7713b1edbc	3078	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3079	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3080
AnnaBridge	171:3a7713b1edbc	3081	/* Bit 8 : TIMER0 region configuration. */
AnnaBridge	171:3a7713b1edbc	3082	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
AnnaBridge	171:3a7713b1edbc	3083	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
AnnaBridge	171:3a7713b1edbc	3084	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3085	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3086
AnnaBridge	171:3a7713b1edbc	3087	/* Bit 7 : ADC region configuration. */
AnnaBridge	171:3a7713b1edbc	3088	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
AnnaBridge	171:3a7713b1edbc	3089	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
AnnaBridge	171:3a7713b1edbc	3090	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3091	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3092
AnnaBridge	171:3a7713b1edbc	3093	/* Bit 6 : GPIOTE region configuration. */
AnnaBridge	171:3a7713b1edbc	3094	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
AnnaBridge	171:3a7713b1edbc	3095	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
AnnaBridge	171:3a7713b1edbc	3096	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3097	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3098
AnnaBridge	171:3a7713b1edbc	3099	/* Bit 4 : SPI1 and TWI1 region configuration. */
AnnaBridge	171:3a7713b1edbc	3100	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
AnnaBridge	171:3a7713b1edbc	3101	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
AnnaBridge	171:3a7713b1edbc	3102	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3103	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3104
AnnaBridge	171:3a7713b1edbc	3105	/* Bit 3 : SPI0 and TWI0 region configuration. */
AnnaBridge	171:3a7713b1edbc	3106	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
AnnaBridge	171:3a7713b1edbc	3107	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
AnnaBridge	171:3a7713b1edbc	3108	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3109	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3110
AnnaBridge	171:3a7713b1edbc	3111	/* Bit 2 : UART0 region configuration. */
AnnaBridge	171:3a7713b1edbc	3112	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
AnnaBridge	171:3a7713b1edbc	3113	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
AnnaBridge	171:3a7713b1edbc	3114	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3115	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3116
AnnaBridge	171:3a7713b1edbc	3117	/* Bit 1 : RADIO region configuration. */
AnnaBridge	171:3a7713b1edbc	3118	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
AnnaBridge	171:3a7713b1edbc	3119	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
AnnaBridge	171:3a7713b1edbc	3120	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3121	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3122
AnnaBridge	171:3a7713b1edbc	3123	/* Bit 0 : POWER_CLOCK region configuration. */
AnnaBridge	171:3a7713b1edbc	3124	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
AnnaBridge	171:3a7713b1edbc	3125	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
AnnaBridge	171:3a7713b1edbc	3126	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
AnnaBridge	171:3a7713b1edbc	3127	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
AnnaBridge	171:3a7713b1edbc	3128
AnnaBridge	171:3a7713b1edbc	3129	/* Register: MPU_PROTENSET0 */
AnnaBridge	171:3a7713b1edbc	3130	/* Description: Erase and write protection bit enable set register. */
AnnaBridge	171:3a7713b1edbc	3131
AnnaBridge	171:3a7713b1edbc	3132	/* Bit 31 : Protection enable for region 31. */
AnnaBridge	171:3a7713b1edbc	3133	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
AnnaBridge	171:3a7713b1edbc	3134	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
AnnaBridge	171:3a7713b1edbc	3135	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3136	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3137	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3138
AnnaBridge	171:3a7713b1edbc	3139	/* Bit 30 : Protection enable for region 30. */
AnnaBridge	171:3a7713b1edbc	3140	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
AnnaBridge	171:3a7713b1edbc	3141	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
AnnaBridge	171:3a7713b1edbc	3142	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3143	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3144	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3145
AnnaBridge	171:3a7713b1edbc	3146	/* Bit 29 : Protection enable for region 29. */
AnnaBridge	171:3a7713b1edbc	3147	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
AnnaBridge	171:3a7713b1edbc	3148	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
AnnaBridge	171:3a7713b1edbc	3149	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3150	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3151	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3152
AnnaBridge	171:3a7713b1edbc	3153	/* Bit 28 : Protection enable for region 28. */
AnnaBridge	171:3a7713b1edbc	3154	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
AnnaBridge	171:3a7713b1edbc	3155	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
AnnaBridge	171:3a7713b1edbc	3156	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3157	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3158	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3159
AnnaBridge	171:3a7713b1edbc	3160	/* Bit 27 : Protection enable for region 27. */
AnnaBridge	171:3a7713b1edbc	3161	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
AnnaBridge	171:3a7713b1edbc	3162	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
AnnaBridge	171:3a7713b1edbc	3163	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3164	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3165	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3166
AnnaBridge	171:3a7713b1edbc	3167	/* Bit 26 : Protection enable for region 26. */
AnnaBridge	171:3a7713b1edbc	3168	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
AnnaBridge	171:3a7713b1edbc	3169	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
AnnaBridge	171:3a7713b1edbc	3170	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3171	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3172	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3173
AnnaBridge	171:3a7713b1edbc	3174	/* Bit 25 : Protection enable for region 25. */
AnnaBridge	171:3a7713b1edbc	3175	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
AnnaBridge	171:3a7713b1edbc	3176	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
AnnaBridge	171:3a7713b1edbc	3177	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3178	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3179	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3180
AnnaBridge	171:3a7713b1edbc	3181	/* Bit 24 : Protection enable for region 24. */
AnnaBridge	171:3a7713b1edbc	3182	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
AnnaBridge	171:3a7713b1edbc	3183	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
AnnaBridge	171:3a7713b1edbc	3184	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3185	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3186	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3187
AnnaBridge	171:3a7713b1edbc	3188	/* Bit 23 : Protection enable for region 23. */
AnnaBridge	171:3a7713b1edbc	3189	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
AnnaBridge	171:3a7713b1edbc	3190	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
AnnaBridge	171:3a7713b1edbc	3191	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3192	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3193	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3194
AnnaBridge	171:3a7713b1edbc	3195	/* Bit 22 : Protection enable for region 22. */
AnnaBridge	171:3a7713b1edbc	3196	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
AnnaBridge	171:3a7713b1edbc	3197	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
AnnaBridge	171:3a7713b1edbc	3198	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3199	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3200	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3201
AnnaBridge	171:3a7713b1edbc	3202	/* Bit 21 : Protection enable for region 21. */
AnnaBridge	171:3a7713b1edbc	3203	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
AnnaBridge	171:3a7713b1edbc	3204	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
AnnaBridge	171:3a7713b1edbc	3205	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3206	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3207	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3208
AnnaBridge	171:3a7713b1edbc	3209	/* Bit 20 : Protection enable for region 20. */
AnnaBridge	171:3a7713b1edbc	3210	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
AnnaBridge	171:3a7713b1edbc	3211	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
AnnaBridge	171:3a7713b1edbc	3212	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3213	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3214	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3215
AnnaBridge	171:3a7713b1edbc	3216	/* Bit 19 : Protection enable for region 19. */
AnnaBridge	171:3a7713b1edbc	3217	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
AnnaBridge	171:3a7713b1edbc	3218	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
AnnaBridge	171:3a7713b1edbc	3219	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3220	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3221	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3222
AnnaBridge	171:3a7713b1edbc	3223	/* Bit 18 : Protection enable for region 18. */
AnnaBridge	171:3a7713b1edbc	3224	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
AnnaBridge	171:3a7713b1edbc	3225	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
AnnaBridge	171:3a7713b1edbc	3226	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3227	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3228	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3229
AnnaBridge	171:3a7713b1edbc	3230	/* Bit 17 : Protection enable for region 17. */
AnnaBridge	171:3a7713b1edbc	3231	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
AnnaBridge	171:3a7713b1edbc	3232	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
AnnaBridge	171:3a7713b1edbc	3233	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3234	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3235	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3236
AnnaBridge	171:3a7713b1edbc	3237	/* Bit 16 : Protection enable for region 16. */
AnnaBridge	171:3a7713b1edbc	3238	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
AnnaBridge	171:3a7713b1edbc	3239	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
AnnaBridge	171:3a7713b1edbc	3240	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3241	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3242	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3243
AnnaBridge	171:3a7713b1edbc	3244	/* Bit 15 : Protection enable for region 15. */
AnnaBridge	171:3a7713b1edbc	3245	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
AnnaBridge	171:3a7713b1edbc	3246	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
AnnaBridge	171:3a7713b1edbc	3247	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3248	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3249	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3250
AnnaBridge	171:3a7713b1edbc	3251	/* Bit 14 : Protection enable for region 14. */
AnnaBridge	171:3a7713b1edbc	3252	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
AnnaBridge	171:3a7713b1edbc	3253	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
AnnaBridge	171:3a7713b1edbc	3254	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3255	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3256	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3257
AnnaBridge	171:3a7713b1edbc	3258	/* Bit 13 : Protection enable for region 13. */
AnnaBridge	171:3a7713b1edbc	3259	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
AnnaBridge	171:3a7713b1edbc	3260	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
AnnaBridge	171:3a7713b1edbc	3261	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3262	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3263	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3264
AnnaBridge	171:3a7713b1edbc	3265	/* Bit 12 : Protection enable for region 12. */
AnnaBridge	171:3a7713b1edbc	3266	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
AnnaBridge	171:3a7713b1edbc	3267	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
AnnaBridge	171:3a7713b1edbc	3268	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3269	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3270	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3271
AnnaBridge	171:3a7713b1edbc	3272	/* Bit 11 : Protection enable for region 11. */
AnnaBridge	171:3a7713b1edbc	3273	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
AnnaBridge	171:3a7713b1edbc	3274	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
AnnaBridge	171:3a7713b1edbc	3275	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3276	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3277	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3278
AnnaBridge	171:3a7713b1edbc	3279	/* Bit 10 : Protection enable for region 10. */
AnnaBridge	171:3a7713b1edbc	3280	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
AnnaBridge	171:3a7713b1edbc	3281	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
AnnaBridge	171:3a7713b1edbc	3282	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3283	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3284	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3285
AnnaBridge	171:3a7713b1edbc	3286	/* Bit 9 : Protection enable for region 9. */
AnnaBridge	171:3a7713b1edbc	3287	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
AnnaBridge	171:3a7713b1edbc	3288	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
AnnaBridge	171:3a7713b1edbc	3289	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3290	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3291	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3292
AnnaBridge	171:3a7713b1edbc	3293	/* Bit 8 : Protection enable for region 8. */
AnnaBridge	171:3a7713b1edbc	3294	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
AnnaBridge	171:3a7713b1edbc	3295	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
AnnaBridge	171:3a7713b1edbc	3296	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3297	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3298	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3299
AnnaBridge	171:3a7713b1edbc	3300	/* Bit 7 : Protection enable for region 7. */
AnnaBridge	171:3a7713b1edbc	3301	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
AnnaBridge	171:3a7713b1edbc	3302	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
AnnaBridge	171:3a7713b1edbc	3303	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3304	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3305	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3306
AnnaBridge	171:3a7713b1edbc	3307	/* Bit 6 : Protection enable for region 6. */
AnnaBridge	171:3a7713b1edbc	3308	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
AnnaBridge	171:3a7713b1edbc	3309	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
AnnaBridge	171:3a7713b1edbc	3310	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3311	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3312	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3313
AnnaBridge	171:3a7713b1edbc	3314	/* Bit 5 : Protection enable for region 5. */
AnnaBridge	171:3a7713b1edbc	3315	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
AnnaBridge	171:3a7713b1edbc	3316	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
AnnaBridge	171:3a7713b1edbc	3317	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3318	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3319	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3320
AnnaBridge	171:3a7713b1edbc	3321	/* Bit 4 : Protection enable for region 4. */
AnnaBridge	171:3a7713b1edbc	3322	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
AnnaBridge	171:3a7713b1edbc	3323	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
AnnaBridge	171:3a7713b1edbc	3324	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3325	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3326	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3327
AnnaBridge	171:3a7713b1edbc	3328	/* Bit 3 : Protection enable for region 3. */
AnnaBridge	171:3a7713b1edbc	3329	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
AnnaBridge	171:3a7713b1edbc	3330	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
AnnaBridge	171:3a7713b1edbc	3331	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3332	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3333	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3334
AnnaBridge	171:3a7713b1edbc	3335	/* Bit 2 : Protection enable for region 2. */
AnnaBridge	171:3a7713b1edbc	3336	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
AnnaBridge	171:3a7713b1edbc	3337	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
AnnaBridge	171:3a7713b1edbc	3338	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3339	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3340	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3341
AnnaBridge	171:3a7713b1edbc	3342	/* Bit 1 : Protection enable for region 1. */
AnnaBridge	171:3a7713b1edbc	3343	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
AnnaBridge	171:3a7713b1edbc	3344	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
AnnaBridge	171:3a7713b1edbc	3345	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3346	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3347	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3348
AnnaBridge	171:3a7713b1edbc	3349	/* Bit 0 : Protection enable for region 0. */
AnnaBridge	171:3a7713b1edbc	3350	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
AnnaBridge	171:3a7713b1edbc	3351	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
AnnaBridge	171:3a7713b1edbc	3352	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3353	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3354	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3355
AnnaBridge	171:3a7713b1edbc	3356	/* Register: MPU_PROTENSET1 */
AnnaBridge	171:3a7713b1edbc	3357	/* Description: Erase and write protection bit enable set register. */
AnnaBridge	171:3a7713b1edbc	3358
AnnaBridge	171:3a7713b1edbc	3359	/* Bit 31 : Protection enable for region 63. */
AnnaBridge	171:3a7713b1edbc	3360	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
AnnaBridge	171:3a7713b1edbc	3361	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
AnnaBridge	171:3a7713b1edbc	3362	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3363	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3364	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3365
AnnaBridge	171:3a7713b1edbc	3366	/* Bit 30 : Protection enable for region 62. */
AnnaBridge	171:3a7713b1edbc	3367	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
AnnaBridge	171:3a7713b1edbc	3368	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
AnnaBridge	171:3a7713b1edbc	3369	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3370	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3371	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3372
AnnaBridge	171:3a7713b1edbc	3373	/* Bit 29 : Protection enable for region 61. */
AnnaBridge	171:3a7713b1edbc	3374	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
AnnaBridge	171:3a7713b1edbc	3375	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
AnnaBridge	171:3a7713b1edbc	3376	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3377	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3378	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3379
AnnaBridge	171:3a7713b1edbc	3380	/* Bit 28 : Protection enable for region 60. */
AnnaBridge	171:3a7713b1edbc	3381	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
AnnaBridge	171:3a7713b1edbc	3382	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
AnnaBridge	171:3a7713b1edbc	3383	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3384	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3385	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3386
AnnaBridge	171:3a7713b1edbc	3387	/* Bit 27 : Protection enable for region 59. */
AnnaBridge	171:3a7713b1edbc	3388	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
AnnaBridge	171:3a7713b1edbc	3389	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
AnnaBridge	171:3a7713b1edbc	3390	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3391	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3392	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3393
AnnaBridge	171:3a7713b1edbc	3394	/* Bit 26 : Protection enable for region 58. */
AnnaBridge	171:3a7713b1edbc	3395	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
AnnaBridge	171:3a7713b1edbc	3396	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
AnnaBridge	171:3a7713b1edbc	3397	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3398	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3399	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3400
AnnaBridge	171:3a7713b1edbc	3401	/* Bit 25 : Protection enable for region 57. */
AnnaBridge	171:3a7713b1edbc	3402	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
AnnaBridge	171:3a7713b1edbc	3403	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
AnnaBridge	171:3a7713b1edbc	3404	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3405	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3406	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3407
AnnaBridge	171:3a7713b1edbc	3408	/* Bit 24 : Protection enable for region 56. */
AnnaBridge	171:3a7713b1edbc	3409	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
AnnaBridge	171:3a7713b1edbc	3410	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
AnnaBridge	171:3a7713b1edbc	3411	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3412	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3413	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3414
AnnaBridge	171:3a7713b1edbc	3415	/* Bit 23 : Protection enable for region 55. */
AnnaBridge	171:3a7713b1edbc	3416	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
AnnaBridge	171:3a7713b1edbc	3417	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
AnnaBridge	171:3a7713b1edbc	3418	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3419	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3420	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3421
AnnaBridge	171:3a7713b1edbc	3422	/* Bit 22 : Protection enable for region 54. */
AnnaBridge	171:3a7713b1edbc	3423	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
AnnaBridge	171:3a7713b1edbc	3424	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
AnnaBridge	171:3a7713b1edbc	3425	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3426	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3427	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3428
AnnaBridge	171:3a7713b1edbc	3429	/* Bit 21 : Protection enable for region 53. */
AnnaBridge	171:3a7713b1edbc	3430	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
AnnaBridge	171:3a7713b1edbc	3431	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
AnnaBridge	171:3a7713b1edbc	3432	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3433	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3434	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3435
AnnaBridge	171:3a7713b1edbc	3436	/* Bit 20 : Protection enable for region 52. */
AnnaBridge	171:3a7713b1edbc	3437	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
AnnaBridge	171:3a7713b1edbc	3438	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
AnnaBridge	171:3a7713b1edbc	3439	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3440	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3441	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3442
AnnaBridge	171:3a7713b1edbc	3443	/* Bit 19 : Protection enable for region 51. */
AnnaBridge	171:3a7713b1edbc	3444	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
AnnaBridge	171:3a7713b1edbc	3445	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
AnnaBridge	171:3a7713b1edbc	3446	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3447	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3448	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3449
AnnaBridge	171:3a7713b1edbc	3450	/* Bit 18 : Protection enable for region 50. */
AnnaBridge	171:3a7713b1edbc	3451	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
AnnaBridge	171:3a7713b1edbc	3452	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
AnnaBridge	171:3a7713b1edbc	3453	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3454	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3455	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3456
AnnaBridge	171:3a7713b1edbc	3457	/* Bit 17 : Protection enable for region 49. */
AnnaBridge	171:3a7713b1edbc	3458	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
AnnaBridge	171:3a7713b1edbc	3459	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
AnnaBridge	171:3a7713b1edbc	3460	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3461	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3462	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3463
AnnaBridge	171:3a7713b1edbc	3464	/* Bit 16 : Protection enable for region 48. */
AnnaBridge	171:3a7713b1edbc	3465	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
AnnaBridge	171:3a7713b1edbc	3466	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
AnnaBridge	171:3a7713b1edbc	3467	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3468	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3469	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3470
AnnaBridge	171:3a7713b1edbc	3471	/* Bit 15 : Protection enable for region 47. */
AnnaBridge	171:3a7713b1edbc	3472	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
AnnaBridge	171:3a7713b1edbc	3473	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
AnnaBridge	171:3a7713b1edbc	3474	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3475	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3476	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3477
AnnaBridge	171:3a7713b1edbc	3478	/* Bit 14 : Protection enable for region 46. */
AnnaBridge	171:3a7713b1edbc	3479	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
AnnaBridge	171:3a7713b1edbc	3480	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
AnnaBridge	171:3a7713b1edbc	3481	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3482	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3483	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3484
AnnaBridge	171:3a7713b1edbc	3485	/* Bit 13 : Protection enable for region 45. */
AnnaBridge	171:3a7713b1edbc	3486	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
AnnaBridge	171:3a7713b1edbc	3487	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
AnnaBridge	171:3a7713b1edbc	3488	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3489	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3490	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3491
AnnaBridge	171:3a7713b1edbc	3492	/* Bit 12 : Protection enable for region 44. */
AnnaBridge	171:3a7713b1edbc	3493	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
AnnaBridge	171:3a7713b1edbc	3494	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
AnnaBridge	171:3a7713b1edbc	3495	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3496	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3497	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3498
AnnaBridge	171:3a7713b1edbc	3499	/* Bit 11 : Protection enable for region 43. */
AnnaBridge	171:3a7713b1edbc	3500	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
AnnaBridge	171:3a7713b1edbc	3501	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
AnnaBridge	171:3a7713b1edbc	3502	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3503	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3504	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3505
AnnaBridge	171:3a7713b1edbc	3506	/* Bit 10 : Protection enable for region 42. */
AnnaBridge	171:3a7713b1edbc	3507	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
AnnaBridge	171:3a7713b1edbc	3508	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
AnnaBridge	171:3a7713b1edbc	3509	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3510	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3511	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3512
AnnaBridge	171:3a7713b1edbc	3513	/* Bit 9 : Protection enable for region 41. */
AnnaBridge	171:3a7713b1edbc	3514	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
AnnaBridge	171:3a7713b1edbc	3515	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
AnnaBridge	171:3a7713b1edbc	3516	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3517	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3518	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3519
AnnaBridge	171:3a7713b1edbc	3520	/* Bit 8 : Protection enable for region 40. */
AnnaBridge	171:3a7713b1edbc	3521	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
AnnaBridge	171:3a7713b1edbc	3522	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
AnnaBridge	171:3a7713b1edbc	3523	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3524	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3525	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3526
AnnaBridge	171:3a7713b1edbc	3527	/* Bit 7 : Protection enable for region 39. */
AnnaBridge	171:3a7713b1edbc	3528	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
AnnaBridge	171:3a7713b1edbc	3529	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
AnnaBridge	171:3a7713b1edbc	3530	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3531	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3532	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3533
AnnaBridge	171:3a7713b1edbc	3534	/* Bit 6 : Protection enable for region 38. */
AnnaBridge	171:3a7713b1edbc	3535	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
AnnaBridge	171:3a7713b1edbc	3536	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
AnnaBridge	171:3a7713b1edbc	3537	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3538	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3539	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3540
AnnaBridge	171:3a7713b1edbc	3541	/* Bit 5 : Protection enable for region 37. */
AnnaBridge	171:3a7713b1edbc	3542	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
AnnaBridge	171:3a7713b1edbc	3543	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
AnnaBridge	171:3a7713b1edbc	3544	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3545	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3546	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3547
AnnaBridge	171:3a7713b1edbc	3548	/* Bit 4 : Protection enable for region 36. */
AnnaBridge	171:3a7713b1edbc	3549	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
AnnaBridge	171:3a7713b1edbc	3550	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
AnnaBridge	171:3a7713b1edbc	3551	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3552	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3553	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3554
AnnaBridge	171:3a7713b1edbc	3555	/* Bit 3 : Protection enable for region 35. */
AnnaBridge	171:3a7713b1edbc	3556	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
AnnaBridge	171:3a7713b1edbc	3557	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
AnnaBridge	171:3a7713b1edbc	3558	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3559	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3560	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3561
AnnaBridge	171:3a7713b1edbc	3562	/* Bit 2 : Protection enable for region 34. */
AnnaBridge	171:3a7713b1edbc	3563	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
AnnaBridge	171:3a7713b1edbc	3564	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
AnnaBridge	171:3a7713b1edbc	3565	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3566	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3567	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3568
AnnaBridge	171:3a7713b1edbc	3569	/* Bit 1 : Protection enable for region 33. */
AnnaBridge	171:3a7713b1edbc	3570	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
AnnaBridge	171:3a7713b1edbc	3571	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
AnnaBridge	171:3a7713b1edbc	3572	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3573	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3574	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3575
AnnaBridge	171:3a7713b1edbc	3576	/* Bit 0 : Protection enable for region 32. */
AnnaBridge	171:3a7713b1edbc	3577	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
AnnaBridge	171:3a7713b1edbc	3578	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
AnnaBridge	171:3a7713b1edbc	3579	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3580	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3581	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
AnnaBridge	171:3a7713b1edbc	3582
AnnaBridge	171:3a7713b1edbc	3583	/* Register: MPU_DISABLEINDEBUG */
AnnaBridge	171:3a7713b1edbc	3584	/* Description: Disable erase and write protection mechanism in debug mode. */
AnnaBridge	171:3a7713b1edbc	3585
AnnaBridge	171:3a7713b1edbc	3586	/* Bit 0 : Disable protection mechanism in debug mode. */
AnnaBridge	171:3a7713b1edbc	3587	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
AnnaBridge	171:3a7713b1edbc	3588	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
AnnaBridge	171:3a7713b1edbc	3589	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
AnnaBridge	171:3a7713b1edbc	3590	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
AnnaBridge	171:3a7713b1edbc	3591
AnnaBridge	171:3a7713b1edbc	3592	/* Register: MPU_PROTBLOCKSIZE */
AnnaBridge	171:3a7713b1edbc	3593	/* Description: Erase and write protection block size. */
AnnaBridge	171:3a7713b1edbc	3594
AnnaBridge	171:3a7713b1edbc	3595	/* Bits 1..0 : Erase and write protection block size. */
AnnaBridge	171:3a7713b1edbc	3596	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
AnnaBridge	171:3a7713b1edbc	3597	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
AnnaBridge	171:3a7713b1edbc	3598	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
AnnaBridge	171:3a7713b1edbc	3599
AnnaBridge	171:3a7713b1edbc	3600
AnnaBridge	171:3a7713b1edbc	3601	/* Peripheral: NVMC */
AnnaBridge	171:3a7713b1edbc	3602	/* Description: Non Volatile Memory Controller. */
AnnaBridge	171:3a7713b1edbc	3603
AnnaBridge	171:3a7713b1edbc	3604	/* Register: NVMC_READY */
AnnaBridge	171:3a7713b1edbc	3605	/* Description: Ready flag. */
AnnaBridge	171:3a7713b1edbc	3606
AnnaBridge	171:3a7713b1edbc	3607	/* Bit 0 : NVMC ready. */
AnnaBridge	171:3a7713b1edbc	3608	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
AnnaBridge	171:3a7713b1edbc	3609	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
AnnaBridge	171:3a7713b1edbc	3610	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
AnnaBridge	171:3a7713b1edbc	3611	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
AnnaBridge	171:3a7713b1edbc	3612
AnnaBridge	171:3a7713b1edbc	3613	/* Register: NVMC_CONFIG */
AnnaBridge	171:3a7713b1edbc	3614	/* Description: Configuration register. */
AnnaBridge	171:3a7713b1edbc	3615
AnnaBridge	171:3a7713b1edbc	3616	/* Bits 1..0 : Program write enable. */
AnnaBridge	171:3a7713b1edbc	3617	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
AnnaBridge	171:3a7713b1edbc	3618	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
AnnaBridge	171:3a7713b1edbc	3619	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
AnnaBridge	171:3a7713b1edbc	3620	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
AnnaBridge	171:3a7713b1edbc	3621	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
AnnaBridge	171:3a7713b1edbc	3622
AnnaBridge	171:3a7713b1edbc	3623	/* Register: NVMC_ERASEALL */
AnnaBridge	171:3a7713b1edbc	3624	/* Description: Register for erasing all non-volatile user memory. */
AnnaBridge	171:3a7713b1edbc	3625
AnnaBridge	171:3a7713b1edbc	3626	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
AnnaBridge	171:3a7713b1edbc	3627	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
AnnaBridge	171:3a7713b1edbc	3628	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
AnnaBridge	171:3a7713b1edbc	3629	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
AnnaBridge	171:3a7713b1edbc	3630	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
AnnaBridge	171:3a7713b1edbc	3631
AnnaBridge	171:3a7713b1edbc	3632	/* Register: NVMC_ERASEUICR */
AnnaBridge	171:3a7713b1edbc	3633	/* Description: Register for start erasing User Information Congfiguration Registers. */
AnnaBridge	171:3a7713b1edbc	3634
AnnaBridge	171:3a7713b1edbc	3635	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
AnnaBridge	171:3a7713b1edbc	3636	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
AnnaBridge	171:3a7713b1edbc	3637	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
AnnaBridge	171:3a7713b1edbc	3638	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
AnnaBridge	171:3a7713b1edbc	3639	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
AnnaBridge	171:3a7713b1edbc	3640
AnnaBridge	171:3a7713b1edbc	3641
AnnaBridge	171:3a7713b1edbc	3642	/* Peripheral: POWER */
AnnaBridge	171:3a7713b1edbc	3643	/* Description: Power Control. */
AnnaBridge	171:3a7713b1edbc	3644
AnnaBridge	171:3a7713b1edbc	3645	/* Register: POWER_INTENSET */
AnnaBridge	171:3a7713b1edbc	3646	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	3647
AnnaBridge	171:3a7713b1edbc	3648	/* Bit 2 : Enable interrupt on POFWARN event. */
AnnaBridge	171:3a7713b1edbc	3649	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
AnnaBridge	171:3a7713b1edbc	3650	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
AnnaBridge	171:3a7713b1edbc	3651	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	3652	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	3653	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	3654
AnnaBridge	171:3a7713b1edbc	3655	/* Register: POWER_INTENCLR */
AnnaBridge	171:3a7713b1edbc	3656	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	3657
AnnaBridge	171:3a7713b1edbc	3658	/* Bit 2 : Disable interrupt on POFWARN event. */
AnnaBridge	171:3a7713b1edbc	3659	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
AnnaBridge	171:3a7713b1edbc	3660	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
AnnaBridge	171:3a7713b1edbc	3661	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	3662	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	3663	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	3664
AnnaBridge	171:3a7713b1edbc	3665	/* Register: POWER_RESETREAS */
AnnaBridge	171:3a7713b1edbc	3666	/* Description: Reset reason. */
AnnaBridge	171:3a7713b1edbc	3667
AnnaBridge	171:3a7713b1edbc	3668	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
AnnaBridge	171:3a7713b1edbc	3669	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
AnnaBridge	171:3a7713b1edbc	3670	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
AnnaBridge	171:3a7713b1edbc	3671	#define POWER_RESETREAS_DIF_NotDetected (0UL) /!< Reset not detected. /
AnnaBridge	171:3a7713b1edbc	3672	#define POWER_RESETREAS_DIF_Detected (1UL) /!< Reset detected. /
AnnaBridge	171:3a7713b1edbc	3673
AnnaBridge	171:3a7713b1edbc	3674	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
AnnaBridge	171:3a7713b1edbc	3675	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
AnnaBridge	171:3a7713b1edbc	3676	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
AnnaBridge	171:3a7713b1edbc	3677	#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /!< Reset not detected. /
AnnaBridge	171:3a7713b1edbc	3678	#define POWER_RESETREAS_LPCOMP_Detected (1UL) /!< Reset detected. /
AnnaBridge	171:3a7713b1edbc	3679
AnnaBridge	171:3a7713b1edbc	3680	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
AnnaBridge	171:3a7713b1edbc	3681	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
AnnaBridge	171:3a7713b1edbc	3682	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
AnnaBridge	171:3a7713b1edbc	3683	#define POWER_RESETREAS_OFF_NotDetected (0UL) /!< Reset not detected. /
AnnaBridge	171:3a7713b1edbc	3684	#define POWER_RESETREAS_OFF_Detected (1UL) /!< Reset detected. /
AnnaBridge	171:3a7713b1edbc	3685
AnnaBridge	171:3a7713b1edbc	3686	/* Bit 3 : Reset from CPU lock-up detected. */
AnnaBridge	171:3a7713b1edbc	3687	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
AnnaBridge	171:3a7713b1edbc	3688	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
AnnaBridge	171:3a7713b1edbc	3689	#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /!< Reset not detected. /
AnnaBridge	171:3a7713b1edbc	3690	#define POWER_RESETREAS_LOCKUP_Detected (1UL) /!< Reset detected. /
AnnaBridge	171:3a7713b1edbc	3691
AnnaBridge	171:3a7713b1edbc	3692	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
AnnaBridge	171:3a7713b1edbc	3693	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
AnnaBridge	171:3a7713b1edbc	3694	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
AnnaBridge	171:3a7713b1edbc	3695	#define POWER_RESETREAS_SREQ_NotDetected (0UL) /!< Reset not detected. /
AnnaBridge	171:3a7713b1edbc	3696	#define POWER_RESETREAS_SREQ_Detected (1UL) /!< Reset detected. /
AnnaBridge	171:3a7713b1edbc	3697
AnnaBridge	171:3a7713b1edbc	3698	/* Bit 1 : Reset from watchdog detected. */
AnnaBridge	171:3a7713b1edbc	3699	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
AnnaBridge	171:3a7713b1edbc	3700	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
AnnaBridge	171:3a7713b1edbc	3701	#define POWER_RESETREAS_DOG_NotDetected (0UL) /!< Reset not detected. /
AnnaBridge	171:3a7713b1edbc	3702	#define POWER_RESETREAS_DOG_Detected (1UL) /!< Reset detected. /
AnnaBridge	171:3a7713b1edbc	3703
AnnaBridge	171:3a7713b1edbc	3704	/* Bit 0 : Reset from pin-reset detected. */
AnnaBridge	171:3a7713b1edbc	3705	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
AnnaBridge	171:3a7713b1edbc	3706	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
AnnaBridge	171:3a7713b1edbc	3707	#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /!< Reset not detected. /
AnnaBridge	171:3a7713b1edbc	3708	#define POWER_RESETREAS_RESETPIN_Detected (1UL) /!< Reset detected. /
AnnaBridge	171:3a7713b1edbc	3709
AnnaBridge	171:3a7713b1edbc	3710	/* Register: POWER_RAMSTATUS */
AnnaBridge	171:3a7713b1edbc	3711	/* Description: Ram status register. */
AnnaBridge	171:3a7713b1edbc	3712
AnnaBridge	171:3a7713b1edbc	3713	/* Bit 3 : RAM block 3 status. */
AnnaBridge	171:3a7713b1edbc	3714	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
AnnaBridge	171:3a7713b1edbc	3715	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
AnnaBridge	171:3a7713b1edbc	3716	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
AnnaBridge	171:3a7713b1edbc	3717	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
AnnaBridge	171:3a7713b1edbc	3718
AnnaBridge	171:3a7713b1edbc	3719	/* Bit 2 : RAM block 2 status. */
AnnaBridge	171:3a7713b1edbc	3720	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
AnnaBridge	171:3a7713b1edbc	3721	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
AnnaBridge	171:3a7713b1edbc	3722	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
AnnaBridge	171:3a7713b1edbc	3723	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
AnnaBridge	171:3a7713b1edbc	3724
AnnaBridge	171:3a7713b1edbc	3725	/* Bit 1 : RAM block 1 status. */
AnnaBridge	171:3a7713b1edbc	3726	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
AnnaBridge	171:3a7713b1edbc	3727	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
AnnaBridge	171:3a7713b1edbc	3728	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
AnnaBridge	171:3a7713b1edbc	3729	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
AnnaBridge	171:3a7713b1edbc	3730
AnnaBridge	171:3a7713b1edbc	3731	/* Bit 0 : RAM block 0 status. */
AnnaBridge	171:3a7713b1edbc	3732	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
AnnaBridge	171:3a7713b1edbc	3733	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
AnnaBridge	171:3a7713b1edbc	3734	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
AnnaBridge	171:3a7713b1edbc	3735	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
AnnaBridge	171:3a7713b1edbc	3736
AnnaBridge	171:3a7713b1edbc	3737	/* Register: POWER_SYSTEMOFF */
AnnaBridge	171:3a7713b1edbc	3738	/* Description: System off register. */
AnnaBridge	171:3a7713b1edbc	3739
AnnaBridge	171:3a7713b1edbc	3740	/* Bit 0 : Enter system off mode. */
AnnaBridge	171:3a7713b1edbc	3741	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
AnnaBridge	171:3a7713b1edbc	3742	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
AnnaBridge	171:3a7713b1edbc	3743	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
AnnaBridge	171:3a7713b1edbc	3744
AnnaBridge	171:3a7713b1edbc	3745	/* Register: POWER_POFCON */
AnnaBridge	171:3a7713b1edbc	3746	/* Description: Power failure configuration. */
AnnaBridge	171:3a7713b1edbc	3747
AnnaBridge	171:3a7713b1edbc	3748	/* Bits 2..1 : Set threshold level. */
AnnaBridge	171:3a7713b1edbc	3749	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
AnnaBridge	171:3a7713b1edbc	3750	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
AnnaBridge	171:3a7713b1edbc	3751	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
AnnaBridge	171:3a7713b1edbc	3752	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
AnnaBridge	171:3a7713b1edbc	3753	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
AnnaBridge	171:3a7713b1edbc	3754	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
AnnaBridge	171:3a7713b1edbc	3755
AnnaBridge	171:3a7713b1edbc	3756	/* Bit 0 : Power failure comparator enable. */
AnnaBridge	171:3a7713b1edbc	3757	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
AnnaBridge	171:3a7713b1edbc	3758	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
AnnaBridge	171:3a7713b1edbc	3759	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	3760	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	3761
AnnaBridge	171:3a7713b1edbc	3762	/* Register: POWER_GPREGRET */
AnnaBridge	171:3a7713b1edbc	3763	/* Description: General purpose retention register. This register is a retained register. */
AnnaBridge	171:3a7713b1edbc	3764
AnnaBridge	171:3a7713b1edbc	3765	/* Bits 7..0 : General purpose retention register. */
AnnaBridge	171:3a7713b1edbc	3766	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
AnnaBridge	171:3a7713b1edbc	3767	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
AnnaBridge	171:3a7713b1edbc	3768
AnnaBridge	171:3a7713b1edbc	3769	/* Register: POWER_RAMON */
AnnaBridge	171:3a7713b1edbc	3770	/* Description: Ram on/off. */
AnnaBridge	171:3a7713b1edbc	3771
AnnaBridge	171:3a7713b1edbc	3772	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
AnnaBridge	171:3a7713b1edbc	3773	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
AnnaBridge	171:3a7713b1edbc	3774	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
AnnaBridge	171:3a7713b1edbc	3775	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3776	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3777
AnnaBridge	171:3a7713b1edbc	3778	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
AnnaBridge	171:3a7713b1edbc	3779	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
AnnaBridge	171:3a7713b1edbc	3780	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
AnnaBridge	171:3a7713b1edbc	3781	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3782	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3783
AnnaBridge	171:3a7713b1edbc	3784	/* Bit 1 : RAM block 1 behaviour in ON mode. */
AnnaBridge	171:3a7713b1edbc	3785	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
AnnaBridge	171:3a7713b1edbc	3786	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
AnnaBridge	171:3a7713b1edbc	3787	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
AnnaBridge	171:3a7713b1edbc	3788	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
AnnaBridge	171:3a7713b1edbc	3789
AnnaBridge	171:3a7713b1edbc	3790	/* Bit 0 : RAM block 0 behaviour in ON mode. */
AnnaBridge	171:3a7713b1edbc	3791	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
AnnaBridge	171:3a7713b1edbc	3792	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
AnnaBridge	171:3a7713b1edbc	3793	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
AnnaBridge	171:3a7713b1edbc	3794	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
AnnaBridge	171:3a7713b1edbc	3795
AnnaBridge	171:3a7713b1edbc	3796	/* Register: POWER_RESET */
AnnaBridge	171:3a7713b1edbc	3797	/* Description: Pin reset functionality configuration register. This register is a retained register. */
AnnaBridge	171:3a7713b1edbc	3798
AnnaBridge	171:3a7713b1edbc	3799	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
AnnaBridge	171:3a7713b1edbc	3800	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
AnnaBridge	171:3a7713b1edbc	3801	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
AnnaBridge	171:3a7713b1edbc	3802	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
AnnaBridge	171:3a7713b1edbc	3803	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
AnnaBridge	171:3a7713b1edbc	3804
AnnaBridge	171:3a7713b1edbc	3805	/* Register: POWER_RAMONB */
AnnaBridge	171:3a7713b1edbc	3806	/* Description: Ram on/off. */
AnnaBridge	171:3a7713b1edbc	3807
AnnaBridge	171:3a7713b1edbc	3808	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
AnnaBridge	171:3a7713b1edbc	3809	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
AnnaBridge	171:3a7713b1edbc	3810	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
AnnaBridge	171:3a7713b1edbc	3811	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3812	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3813
AnnaBridge	171:3a7713b1edbc	3814	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
AnnaBridge	171:3a7713b1edbc	3815	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
AnnaBridge	171:3a7713b1edbc	3816	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
AnnaBridge	171:3a7713b1edbc	3817	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3818	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
AnnaBridge	171:3a7713b1edbc	3819
AnnaBridge	171:3a7713b1edbc	3820	/* Bit 1 : RAM block 3 behaviour in ON mode. */
AnnaBridge	171:3a7713b1edbc	3821	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
AnnaBridge	171:3a7713b1edbc	3822	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
AnnaBridge	171:3a7713b1edbc	3823	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
AnnaBridge	171:3a7713b1edbc	3824	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
AnnaBridge	171:3a7713b1edbc	3825
AnnaBridge	171:3a7713b1edbc	3826	/* Bit 0 : RAM block 2 behaviour in ON mode. */
AnnaBridge	171:3a7713b1edbc	3827	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
AnnaBridge	171:3a7713b1edbc	3828	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
AnnaBridge	171:3a7713b1edbc	3829	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
AnnaBridge	171:3a7713b1edbc	3830	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
AnnaBridge	171:3a7713b1edbc	3831
AnnaBridge	171:3a7713b1edbc	3832	/* Register: POWER_DCDCEN */
AnnaBridge	171:3a7713b1edbc	3833	/* Description: DCDC converter enable configuration register. */
AnnaBridge	171:3a7713b1edbc	3834
AnnaBridge	171:3a7713b1edbc	3835	/* Bit 0 : Enable DCDC converter. */
AnnaBridge	171:3a7713b1edbc	3836	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
AnnaBridge	171:3a7713b1edbc	3837	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
AnnaBridge	171:3a7713b1edbc	3838	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
AnnaBridge	171:3a7713b1edbc	3839	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
AnnaBridge	171:3a7713b1edbc	3840
AnnaBridge	171:3a7713b1edbc	3841	/* Register: POWER_DCDCFORCE */
AnnaBridge	171:3a7713b1edbc	3842	/* Description: DCDC power-up force register. */
AnnaBridge	171:3a7713b1edbc	3843
AnnaBridge	171:3a7713b1edbc	3844	/* Bit 1 : DCDC power-up force on. */
AnnaBridge	171:3a7713b1edbc	3845	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
AnnaBridge	171:3a7713b1edbc	3846	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
AnnaBridge	171:3a7713b1edbc	3847	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
AnnaBridge	171:3a7713b1edbc	3848	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
AnnaBridge	171:3a7713b1edbc	3849
AnnaBridge	171:3a7713b1edbc	3850	/* Bit 0 : DCDC power-up force off. */
AnnaBridge	171:3a7713b1edbc	3851	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
AnnaBridge	171:3a7713b1edbc	3852	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
AnnaBridge	171:3a7713b1edbc	3853	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
AnnaBridge	171:3a7713b1edbc	3854	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
AnnaBridge	171:3a7713b1edbc	3855
AnnaBridge	171:3a7713b1edbc	3856
AnnaBridge	171:3a7713b1edbc	3857	/* Peripheral: PPI */
AnnaBridge	171:3a7713b1edbc	3858	/* Description: PPI controller. */
AnnaBridge	171:3a7713b1edbc	3859
AnnaBridge	171:3a7713b1edbc	3860	/* Register: PPI_CHEN */
AnnaBridge	171:3a7713b1edbc	3861	/* Description: Channel enable. */
AnnaBridge	171:3a7713b1edbc	3862
AnnaBridge	171:3a7713b1edbc	3863	/* Bit 31 : Enable PPI channel 31. */
AnnaBridge	171:3a7713b1edbc	3864	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
AnnaBridge	171:3a7713b1edbc	3865	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
AnnaBridge	171:3a7713b1edbc	3866	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3867	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3868
AnnaBridge	171:3a7713b1edbc	3869	/* Bit 30 : Enable PPI channel 30. */
AnnaBridge	171:3a7713b1edbc	3870	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
AnnaBridge	171:3a7713b1edbc	3871	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
AnnaBridge	171:3a7713b1edbc	3872	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3873	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3874
AnnaBridge	171:3a7713b1edbc	3875	/* Bit 29 : Enable PPI channel 29. */
AnnaBridge	171:3a7713b1edbc	3876	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
AnnaBridge	171:3a7713b1edbc	3877	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
AnnaBridge	171:3a7713b1edbc	3878	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3879	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3880
AnnaBridge	171:3a7713b1edbc	3881	/* Bit 28 : Enable PPI channel 28. */
AnnaBridge	171:3a7713b1edbc	3882	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
AnnaBridge	171:3a7713b1edbc	3883	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
AnnaBridge	171:3a7713b1edbc	3884	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3885	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3886
AnnaBridge	171:3a7713b1edbc	3887	/* Bit 27 : Enable PPI channel 27. */
AnnaBridge	171:3a7713b1edbc	3888	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
AnnaBridge	171:3a7713b1edbc	3889	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
AnnaBridge	171:3a7713b1edbc	3890	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3891	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3892
AnnaBridge	171:3a7713b1edbc	3893	/* Bit 26 : Enable PPI channel 26. */
AnnaBridge	171:3a7713b1edbc	3894	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
AnnaBridge	171:3a7713b1edbc	3895	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
AnnaBridge	171:3a7713b1edbc	3896	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3897	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3898
AnnaBridge	171:3a7713b1edbc	3899	/* Bit 25 : Enable PPI channel 25. */
AnnaBridge	171:3a7713b1edbc	3900	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
AnnaBridge	171:3a7713b1edbc	3901	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
AnnaBridge	171:3a7713b1edbc	3902	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3903	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3904
AnnaBridge	171:3a7713b1edbc	3905	/* Bit 24 : Enable PPI channel 24. */
AnnaBridge	171:3a7713b1edbc	3906	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
AnnaBridge	171:3a7713b1edbc	3907	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
AnnaBridge	171:3a7713b1edbc	3908	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3909	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3910
AnnaBridge	171:3a7713b1edbc	3911	/* Bit 23 : Enable PPI channel 23. */
AnnaBridge	171:3a7713b1edbc	3912	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
AnnaBridge	171:3a7713b1edbc	3913	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
AnnaBridge	171:3a7713b1edbc	3914	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3915	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3916
AnnaBridge	171:3a7713b1edbc	3917	/* Bit 22 : Enable PPI channel 22. */
AnnaBridge	171:3a7713b1edbc	3918	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
AnnaBridge	171:3a7713b1edbc	3919	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
AnnaBridge	171:3a7713b1edbc	3920	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3921	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3922
AnnaBridge	171:3a7713b1edbc	3923	/* Bit 21 : Enable PPI channel 21. */
AnnaBridge	171:3a7713b1edbc	3924	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
AnnaBridge	171:3a7713b1edbc	3925	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
AnnaBridge	171:3a7713b1edbc	3926	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3927	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3928
AnnaBridge	171:3a7713b1edbc	3929	/* Bit 20 : Enable PPI channel 20. */
AnnaBridge	171:3a7713b1edbc	3930	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
AnnaBridge	171:3a7713b1edbc	3931	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
AnnaBridge	171:3a7713b1edbc	3932	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3933	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3934
AnnaBridge	171:3a7713b1edbc	3935	/* Bit 15 : Enable PPI channel 15. */
AnnaBridge	171:3a7713b1edbc	3936	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
AnnaBridge	171:3a7713b1edbc	3937	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
AnnaBridge	171:3a7713b1edbc	3938	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3939	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3940
AnnaBridge	171:3a7713b1edbc	3941	/* Bit 14 : Enable PPI channel 14. */
AnnaBridge	171:3a7713b1edbc	3942	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
AnnaBridge	171:3a7713b1edbc	3943	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
AnnaBridge	171:3a7713b1edbc	3944	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3945	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3946
AnnaBridge	171:3a7713b1edbc	3947	/* Bit 13 : Enable PPI channel 13. */
AnnaBridge	171:3a7713b1edbc	3948	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
AnnaBridge	171:3a7713b1edbc	3949	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
AnnaBridge	171:3a7713b1edbc	3950	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3951	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3952
AnnaBridge	171:3a7713b1edbc	3953	/* Bit 12 : Enable PPI channel 12. */
AnnaBridge	171:3a7713b1edbc	3954	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
AnnaBridge	171:3a7713b1edbc	3955	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
AnnaBridge	171:3a7713b1edbc	3956	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3957	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3958
AnnaBridge	171:3a7713b1edbc	3959	/* Bit 11 : Enable PPI channel 11. */
AnnaBridge	171:3a7713b1edbc	3960	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
AnnaBridge	171:3a7713b1edbc	3961	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
AnnaBridge	171:3a7713b1edbc	3962	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3963	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3964
AnnaBridge	171:3a7713b1edbc	3965	/* Bit 10 : Enable PPI channel 10. */
AnnaBridge	171:3a7713b1edbc	3966	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
AnnaBridge	171:3a7713b1edbc	3967	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
AnnaBridge	171:3a7713b1edbc	3968	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3969	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3970
AnnaBridge	171:3a7713b1edbc	3971	/* Bit 9 : Enable PPI channel 9. */
AnnaBridge	171:3a7713b1edbc	3972	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
AnnaBridge	171:3a7713b1edbc	3973	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
AnnaBridge	171:3a7713b1edbc	3974	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3975	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3976
AnnaBridge	171:3a7713b1edbc	3977	/* Bit 8 : Enable PPI channel 8. */
AnnaBridge	171:3a7713b1edbc	3978	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
AnnaBridge	171:3a7713b1edbc	3979	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
AnnaBridge	171:3a7713b1edbc	3980	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3981	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3982
AnnaBridge	171:3a7713b1edbc	3983	/* Bit 7 : Enable PPI channel 7. */
AnnaBridge	171:3a7713b1edbc	3984	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
AnnaBridge	171:3a7713b1edbc	3985	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
AnnaBridge	171:3a7713b1edbc	3986	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3987	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3988
AnnaBridge	171:3a7713b1edbc	3989	/* Bit 6 : Enable PPI channel 6. */
AnnaBridge	171:3a7713b1edbc	3990	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
AnnaBridge	171:3a7713b1edbc	3991	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
AnnaBridge	171:3a7713b1edbc	3992	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3993	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	3994
AnnaBridge	171:3a7713b1edbc	3995	/* Bit 5 : Enable PPI channel 5. */
AnnaBridge	171:3a7713b1edbc	3996	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
AnnaBridge	171:3a7713b1edbc	3997	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
AnnaBridge	171:3a7713b1edbc	3998	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	3999	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4000
AnnaBridge	171:3a7713b1edbc	4001	/* Bit 4 : Enable PPI channel 4. */
AnnaBridge	171:3a7713b1edbc	4002	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4003	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4004	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4005	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4006
AnnaBridge	171:3a7713b1edbc	4007	/* Bit 3 : Enable PPI channel 3. */
AnnaBridge	171:3a7713b1edbc	4008	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4009	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4010	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
AnnaBridge	171:3a7713b1edbc	4011	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
AnnaBridge	171:3a7713b1edbc	4012
AnnaBridge	171:3a7713b1edbc	4013	/* Bit 2 : Enable PPI channel 2. */
AnnaBridge	171:3a7713b1edbc	4014	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4015	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4016	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4017	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4018
AnnaBridge	171:3a7713b1edbc	4019	/* Bit 1 : Enable PPI channel 1. */
AnnaBridge	171:3a7713b1edbc	4020	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4021	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4022	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4023	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4024
AnnaBridge	171:3a7713b1edbc	4025	/* Bit 0 : Enable PPI channel 0. */
AnnaBridge	171:3a7713b1edbc	4026	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4027	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4028	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4029	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4030
AnnaBridge	171:3a7713b1edbc	4031	/* Register: PPI_CHENSET */
AnnaBridge	171:3a7713b1edbc	4032	/* Description: Channel enable set. */
AnnaBridge	171:3a7713b1edbc	4033
AnnaBridge	171:3a7713b1edbc	4034	/* Bit 31 : Enable PPI channel 31. */
AnnaBridge	171:3a7713b1edbc	4035	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
AnnaBridge	171:3a7713b1edbc	4036	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
AnnaBridge	171:3a7713b1edbc	4037	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4038	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4039	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4040
AnnaBridge	171:3a7713b1edbc	4041	/* Bit 30 : Enable PPI channel 30. */
AnnaBridge	171:3a7713b1edbc	4042	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
AnnaBridge	171:3a7713b1edbc	4043	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
AnnaBridge	171:3a7713b1edbc	4044	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4045	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4046	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4047
AnnaBridge	171:3a7713b1edbc	4048	/* Bit 29 : Enable PPI channel 29. */
AnnaBridge	171:3a7713b1edbc	4049	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
AnnaBridge	171:3a7713b1edbc	4050	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
AnnaBridge	171:3a7713b1edbc	4051	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4052	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4053	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4054
AnnaBridge	171:3a7713b1edbc	4055	/* Bit 28 : Enable PPI channel 28. */
AnnaBridge	171:3a7713b1edbc	4056	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
AnnaBridge	171:3a7713b1edbc	4057	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
AnnaBridge	171:3a7713b1edbc	4058	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4059	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4060	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4061
AnnaBridge	171:3a7713b1edbc	4062	/* Bit 27 : Enable PPI channel 27. */
AnnaBridge	171:3a7713b1edbc	4063	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
AnnaBridge	171:3a7713b1edbc	4064	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
AnnaBridge	171:3a7713b1edbc	4065	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4066	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4067	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4068
AnnaBridge	171:3a7713b1edbc	4069	/* Bit 26 : Enable PPI channel 26. */
AnnaBridge	171:3a7713b1edbc	4070	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
AnnaBridge	171:3a7713b1edbc	4071	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
AnnaBridge	171:3a7713b1edbc	4072	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4073	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4074	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4075
AnnaBridge	171:3a7713b1edbc	4076	/* Bit 25 : Enable PPI channel 25. */
AnnaBridge	171:3a7713b1edbc	4077	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
AnnaBridge	171:3a7713b1edbc	4078	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
AnnaBridge	171:3a7713b1edbc	4079	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4080	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4081	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4082
AnnaBridge	171:3a7713b1edbc	4083	/* Bit 24 : Enable PPI channel 24. */
AnnaBridge	171:3a7713b1edbc	4084	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
AnnaBridge	171:3a7713b1edbc	4085	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
AnnaBridge	171:3a7713b1edbc	4086	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4087	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4088	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4089
AnnaBridge	171:3a7713b1edbc	4090	/* Bit 23 : Enable PPI channel 23. */
AnnaBridge	171:3a7713b1edbc	4091	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
AnnaBridge	171:3a7713b1edbc	4092	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
AnnaBridge	171:3a7713b1edbc	4093	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4094	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4095	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4096
AnnaBridge	171:3a7713b1edbc	4097	/* Bit 22 : Enable PPI channel 22. */
AnnaBridge	171:3a7713b1edbc	4098	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
AnnaBridge	171:3a7713b1edbc	4099	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
AnnaBridge	171:3a7713b1edbc	4100	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4101	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4102	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4103
AnnaBridge	171:3a7713b1edbc	4104	/* Bit 21 : Enable PPI channel 21. */
AnnaBridge	171:3a7713b1edbc	4105	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
AnnaBridge	171:3a7713b1edbc	4106	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
AnnaBridge	171:3a7713b1edbc	4107	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4108	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4109	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4110
AnnaBridge	171:3a7713b1edbc	4111	/* Bit 20 : Enable PPI channel 20. */
AnnaBridge	171:3a7713b1edbc	4112	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
AnnaBridge	171:3a7713b1edbc	4113	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
AnnaBridge	171:3a7713b1edbc	4114	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4115	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4116	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4117
AnnaBridge	171:3a7713b1edbc	4118	/* Bit 15 : Enable PPI channel 15. */
AnnaBridge	171:3a7713b1edbc	4119	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
AnnaBridge	171:3a7713b1edbc	4120	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
AnnaBridge	171:3a7713b1edbc	4121	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4122	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4123	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4124
AnnaBridge	171:3a7713b1edbc	4125	/* Bit 14 : Enable PPI channel 14. */
AnnaBridge	171:3a7713b1edbc	4126	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
AnnaBridge	171:3a7713b1edbc	4127	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
AnnaBridge	171:3a7713b1edbc	4128	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4129	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4130	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4131
AnnaBridge	171:3a7713b1edbc	4132	/* Bit 13 : Enable PPI channel 13. */
AnnaBridge	171:3a7713b1edbc	4133	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
AnnaBridge	171:3a7713b1edbc	4134	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
AnnaBridge	171:3a7713b1edbc	4135	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4136	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4137	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4138
AnnaBridge	171:3a7713b1edbc	4139	/* Bit 12 : Enable PPI channel 12. */
AnnaBridge	171:3a7713b1edbc	4140	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
AnnaBridge	171:3a7713b1edbc	4141	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
AnnaBridge	171:3a7713b1edbc	4142	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4143	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4144	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4145
AnnaBridge	171:3a7713b1edbc	4146	/* Bit 11 : Enable PPI channel 11. */
AnnaBridge	171:3a7713b1edbc	4147	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
AnnaBridge	171:3a7713b1edbc	4148	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
AnnaBridge	171:3a7713b1edbc	4149	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4150	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4151	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4152
AnnaBridge	171:3a7713b1edbc	4153	/* Bit 10 : Enable PPI channel 10. */
AnnaBridge	171:3a7713b1edbc	4154	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
AnnaBridge	171:3a7713b1edbc	4155	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
AnnaBridge	171:3a7713b1edbc	4156	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4157	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4158	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4159
AnnaBridge	171:3a7713b1edbc	4160	/* Bit 9 : Enable PPI channel 9. */
AnnaBridge	171:3a7713b1edbc	4161	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
AnnaBridge	171:3a7713b1edbc	4162	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
AnnaBridge	171:3a7713b1edbc	4163	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4164	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4165	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4166
AnnaBridge	171:3a7713b1edbc	4167	/* Bit 8 : Enable PPI channel 8. */
AnnaBridge	171:3a7713b1edbc	4168	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
AnnaBridge	171:3a7713b1edbc	4169	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
AnnaBridge	171:3a7713b1edbc	4170	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4171	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4172	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4173
AnnaBridge	171:3a7713b1edbc	4174	/* Bit 7 : Enable PPI channel 7. */
AnnaBridge	171:3a7713b1edbc	4175	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
AnnaBridge	171:3a7713b1edbc	4176	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
AnnaBridge	171:3a7713b1edbc	4177	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4178	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4179	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4180
AnnaBridge	171:3a7713b1edbc	4181	/* Bit 6 : Enable PPI channel 6. */
AnnaBridge	171:3a7713b1edbc	4182	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
AnnaBridge	171:3a7713b1edbc	4183	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
AnnaBridge	171:3a7713b1edbc	4184	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4185	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4186	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4187
AnnaBridge	171:3a7713b1edbc	4188	/* Bit 5 : Enable PPI channel 5. */
AnnaBridge	171:3a7713b1edbc	4189	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
AnnaBridge	171:3a7713b1edbc	4190	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
AnnaBridge	171:3a7713b1edbc	4191	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4192	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4193	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4194
AnnaBridge	171:3a7713b1edbc	4195	/* Bit 4 : Enable PPI channel 4. */
AnnaBridge	171:3a7713b1edbc	4196	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4197	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4198	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4199	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4200	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4201
AnnaBridge	171:3a7713b1edbc	4202	/* Bit 3 : Enable PPI channel 3. */
AnnaBridge	171:3a7713b1edbc	4203	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4204	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4205	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4206	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4207	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4208
AnnaBridge	171:3a7713b1edbc	4209	/* Bit 2 : Enable PPI channel 2. */
AnnaBridge	171:3a7713b1edbc	4210	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4211	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4212	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4213	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4214	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4215
AnnaBridge	171:3a7713b1edbc	4216	/* Bit 1 : Enable PPI channel 1. */
AnnaBridge	171:3a7713b1edbc	4217	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4218	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4219	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4220	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4221	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4222
AnnaBridge	171:3a7713b1edbc	4223	/* Bit 0 : Enable PPI channel 0. */
AnnaBridge	171:3a7713b1edbc	4224	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4225	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4226	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4227	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4228	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
AnnaBridge	171:3a7713b1edbc	4229
AnnaBridge	171:3a7713b1edbc	4230	/* Register: PPI_CHENCLR */
AnnaBridge	171:3a7713b1edbc	4231	/* Description: Channel enable clear. */
AnnaBridge	171:3a7713b1edbc	4232
AnnaBridge	171:3a7713b1edbc	4233	/* Bit 31 : Disable PPI channel 31. */
AnnaBridge	171:3a7713b1edbc	4234	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
AnnaBridge	171:3a7713b1edbc	4235	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
AnnaBridge	171:3a7713b1edbc	4236	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4237	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4238	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4239
AnnaBridge	171:3a7713b1edbc	4240	/* Bit 30 : Disable PPI channel 30. */
AnnaBridge	171:3a7713b1edbc	4241	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
AnnaBridge	171:3a7713b1edbc	4242	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
AnnaBridge	171:3a7713b1edbc	4243	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4244	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4245	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4246
AnnaBridge	171:3a7713b1edbc	4247	/* Bit 29 : Disable PPI channel 29. */
AnnaBridge	171:3a7713b1edbc	4248	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
AnnaBridge	171:3a7713b1edbc	4249	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
AnnaBridge	171:3a7713b1edbc	4250	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4251	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4252	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4253
AnnaBridge	171:3a7713b1edbc	4254	/* Bit 28 : Disable PPI channel 28. */
AnnaBridge	171:3a7713b1edbc	4255	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
AnnaBridge	171:3a7713b1edbc	4256	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
AnnaBridge	171:3a7713b1edbc	4257	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4258	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4259	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4260
AnnaBridge	171:3a7713b1edbc	4261	/* Bit 27 : Disable PPI channel 27. */
AnnaBridge	171:3a7713b1edbc	4262	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
AnnaBridge	171:3a7713b1edbc	4263	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
AnnaBridge	171:3a7713b1edbc	4264	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4265	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4266	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4267
AnnaBridge	171:3a7713b1edbc	4268	/* Bit 26 : Disable PPI channel 26. */
AnnaBridge	171:3a7713b1edbc	4269	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
AnnaBridge	171:3a7713b1edbc	4270	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
AnnaBridge	171:3a7713b1edbc	4271	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4272	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4273	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4274
AnnaBridge	171:3a7713b1edbc	4275	/* Bit 25 : Disable PPI channel 25. */
AnnaBridge	171:3a7713b1edbc	4276	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
AnnaBridge	171:3a7713b1edbc	4277	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
AnnaBridge	171:3a7713b1edbc	4278	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4279	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4280	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4281
AnnaBridge	171:3a7713b1edbc	4282	/* Bit 24 : Disable PPI channel 24. */
AnnaBridge	171:3a7713b1edbc	4283	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
AnnaBridge	171:3a7713b1edbc	4284	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
AnnaBridge	171:3a7713b1edbc	4285	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4286	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4287	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4288
AnnaBridge	171:3a7713b1edbc	4289	/* Bit 23 : Disable PPI channel 23. */
AnnaBridge	171:3a7713b1edbc	4290	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
AnnaBridge	171:3a7713b1edbc	4291	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
AnnaBridge	171:3a7713b1edbc	4292	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4293	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4294	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4295
AnnaBridge	171:3a7713b1edbc	4296	/* Bit 22 : Disable PPI channel 22. */
AnnaBridge	171:3a7713b1edbc	4297	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
AnnaBridge	171:3a7713b1edbc	4298	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
AnnaBridge	171:3a7713b1edbc	4299	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4300	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4301	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4302
AnnaBridge	171:3a7713b1edbc	4303	/* Bit 21 : Disable PPI channel 21. */
AnnaBridge	171:3a7713b1edbc	4304	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
AnnaBridge	171:3a7713b1edbc	4305	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
AnnaBridge	171:3a7713b1edbc	4306	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4307	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4308	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4309
AnnaBridge	171:3a7713b1edbc	4310	/* Bit 20 : Disable PPI channel 20. */
AnnaBridge	171:3a7713b1edbc	4311	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
AnnaBridge	171:3a7713b1edbc	4312	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
AnnaBridge	171:3a7713b1edbc	4313	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4314	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4315	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4316
AnnaBridge	171:3a7713b1edbc	4317	/* Bit 15 : Disable PPI channel 15. */
AnnaBridge	171:3a7713b1edbc	4318	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
AnnaBridge	171:3a7713b1edbc	4319	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
AnnaBridge	171:3a7713b1edbc	4320	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4321	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4322	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4323
AnnaBridge	171:3a7713b1edbc	4324	/* Bit 14 : Disable PPI channel 14. */
AnnaBridge	171:3a7713b1edbc	4325	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
AnnaBridge	171:3a7713b1edbc	4326	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
AnnaBridge	171:3a7713b1edbc	4327	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4328	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4329	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4330
AnnaBridge	171:3a7713b1edbc	4331	/* Bit 13 : Disable PPI channel 13. */
AnnaBridge	171:3a7713b1edbc	4332	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
AnnaBridge	171:3a7713b1edbc	4333	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
AnnaBridge	171:3a7713b1edbc	4334	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4335	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4336	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4337
AnnaBridge	171:3a7713b1edbc	4338	/* Bit 12 : Disable PPI channel 12. */
AnnaBridge	171:3a7713b1edbc	4339	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
AnnaBridge	171:3a7713b1edbc	4340	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
AnnaBridge	171:3a7713b1edbc	4341	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4342	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4343	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4344
AnnaBridge	171:3a7713b1edbc	4345	/* Bit 11 : Disable PPI channel 11. */
AnnaBridge	171:3a7713b1edbc	4346	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
AnnaBridge	171:3a7713b1edbc	4347	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
AnnaBridge	171:3a7713b1edbc	4348	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4349	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4350	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4351
AnnaBridge	171:3a7713b1edbc	4352	/* Bit 10 : Disable PPI channel 10. */
AnnaBridge	171:3a7713b1edbc	4353	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
AnnaBridge	171:3a7713b1edbc	4354	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
AnnaBridge	171:3a7713b1edbc	4355	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4356	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4357	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4358
AnnaBridge	171:3a7713b1edbc	4359	/* Bit 9 : Disable PPI channel 9. */
AnnaBridge	171:3a7713b1edbc	4360	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
AnnaBridge	171:3a7713b1edbc	4361	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
AnnaBridge	171:3a7713b1edbc	4362	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4363	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4364	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4365
AnnaBridge	171:3a7713b1edbc	4366	/* Bit 8 : Disable PPI channel 8. */
AnnaBridge	171:3a7713b1edbc	4367	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
AnnaBridge	171:3a7713b1edbc	4368	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
AnnaBridge	171:3a7713b1edbc	4369	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4370	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4371	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4372
AnnaBridge	171:3a7713b1edbc	4373	/* Bit 7 : Disable PPI channel 7. */
AnnaBridge	171:3a7713b1edbc	4374	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
AnnaBridge	171:3a7713b1edbc	4375	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
AnnaBridge	171:3a7713b1edbc	4376	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4377	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4378	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4379
AnnaBridge	171:3a7713b1edbc	4380	/* Bit 6 : Disable PPI channel 6. */
AnnaBridge	171:3a7713b1edbc	4381	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
AnnaBridge	171:3a7713b1edbc	4382	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
AnnaBridge	171:3a7713b1edbc	4383	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4384	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4385	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4386
AnnaBridge	171:3a7713b1edbc	4387	/* Bit 5 : Disable PPI channel 5. */
AnnaBridge	171:3a7713b1edbc	4388	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
AnnaBridge	171:3a7713b1edbc	4389	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
AnnaBridge	171:3a7713b1edbc	4390	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4391	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4392	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4393
AnnaBridge	171:3a7713b1edbc	4394	/* Bit 4 : Disable PPI channel 4. */
AnnaBridge	171:3a7713b1edbc	4395	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4396	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4397	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4398	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4399	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4400
AnnaBridge	171:3a7713b1edbc	4401	/* Bit 3 : Disable PPI channel 3. */
AnnaBridge	171:3a7713b1edbc	4402	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4403	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4404	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4405	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4406	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4407
AnnaBridge	171:3a7713b1edbc	4408	/* Bit 2 : Disable PPI channel 2. */
AnnaBridge	171:3a7713b1edbc	4409	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4410	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4411	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4412	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4413	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4414
AnnaBridge	171:3a7713b1edbc	4415	/* Bit 1 : Disable PPI channel 1. */
AnnaBridge	171:3a7713b1edbc	4416	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4417	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4418	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4419	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4420	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4421
AnnaBridge	171:3a7713b1edbc	4422	/* Bit 0 : Disable PPI channel 0. */
AnnaBridge	171:3a7713b1edbc	4423	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4424	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4425	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
AnnaBridge	171:3a7713b1edbc	4426	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
AnnaBridge	171:3a7713b1edbc	4427	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
AnnaBridge	171:3a7713b1edbc	4428
AnnaBridge	171:3a7713b1edbc	4429	/* Register: PPI_CHG */
AnnaBridge	171:3a7713b1edbc	4430	/* Description: Channel group configuration. */
AnnaBridge	171:3a7713b1edbc	4431
AnnaBridge	171:3a7713b1edbc	4432	/* Bit 31 : Include CH31 in channel group. */
AnnaBridge	171:3a7713b1edbc	4433	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
AnnaBridge	171:3a7713b1edbc	4434	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
AnnaBridge	171:3a7713b1edbc	4435	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4436	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4437
AnnaBridge	171:3a7713b1edbc	4438	/* Bit 30 : Include CH30 in channel group. */
AnnaBridge	171:3a7713b1edbc	4439	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
AnnaBridge	171:3a7713b1edbc	4440	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
AnnaBridge	171:3a7713b1edbc	4441	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4442	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4443
AnnaBridge	171:3a7713b1edbc	4444	/* Bit 29 : Include CH29 in channel group. */
AnnaBridge	171:3a7713b1edbc	4445	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
AnnaBridge	171:3a7713b1edbc	4446	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
AnnaBridge	171:3a7713b1edbc	4447	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4448	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4449
AnnaBridge	171:3a7713b1edbc	4450	/* Bit 28 : Include CH28 in channel group. */
AnnaBridge	171:3a7713b1edbc	4451	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
AnnaBridge	171:3a7713b1edbc	4452	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
AnnaBridge	171:3a7713b1edbc	4453	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4454	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4455
AnnaBridge	171:3a7713b1edbc	4456	/* Bit 27 : Include CH27 in channel group. */
AnnaBridge	171:3a7713b1edbc	4457	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
AnnaBridge	171:3a7713b1edbc	4458	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
AnnaBridge	171:3a7713b1edbc	4459	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4460	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4461
AnnaBridge	171:3a7713b1edbc	4462	/* Bit 26 : Include CH26 in channel group. */
AnnaBridge	171:3a7713b1edbc	4463	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
AnnaBridge	171:3a7713b1edbc	4464	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
AnnaBridge	171:3a7713b1edbc	4465	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4466	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4467
AnnaBridge	171:3a7713b1edbc	4468	/* Bit 25 : Include CH25 in channel group. */
AnnaBridge	171:3a7713b1edbc	4469	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
AnnaBridge	171:3a7713b1edbc	4470	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
AnnaBridge	171:3a7713b1edbc	4471	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4472	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4473
AnnaBridge	171:3a7713b1edbc	4474	/* Bit 24 : Include CH24 in channel group. */
AnnaBridge	171:3a7713b1edbc	4475	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
AnnaBridge	171:3a7713b1edbc	4476	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
AnnaBridge	171:3a7713b1edbc	4477	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4478	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4479
AnnaBridge	171:3a7713b1edbc	4480	/* Bit 23 : Include CH23 in channel group. */
AnnaBridge	171:3a7713b1edbc	4481	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
AnnaBridge	171:3a7713b1edbc	4482	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
AnnaBridge	171:3a7713b1edbc	4483	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4484	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4485
AnnaBridge	171:3a7713b1edbc	4486	/* Bit 22 : Include CH22 in channel group. */
AnnaBridge	171:3a7713b1edbc	4487	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
AnnaBridge	171:3a7713b1edbc	4488	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
AnnaBridge	171:3a7713b1edbc	4489	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4490	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4491
AnnaBridge	171:3a7713b1edbc	4492	/* Bit 21 : Include CH21 in channel group. */
AnnaBridge	171:3a7713b1edbc	4493	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
AnnaBridge	171:3a7713b1edbc	4494	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
AnnaBridge	171:3a7713b1edbc	4495	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4496	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4497
AnnaBridge	171:3a7713b1edbc	4498	/* Bit 20 : Include CH20 in channel group. */
AnnaBridge	171:3a7713b1edbc	4499	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
AnnaBridge	171:3a7713b1edbc	4500	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
AnnaBridge	171:3a7713b1edbc	4501	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4502	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4503
AnnaBridge	171:3a7713b1edbc	4504	/* Bit 15 : Include CH15 in channel group. */
AnnaBridge	171:3a7713b1edbc	4505	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
AnnaBridge	171:3a7713b1edbc	4506	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
AnnaBridge	171:3a7713b1edbc	4507	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4508	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4509
AnnaBridge	171:3a7713b1edbc	4510	/* Bit 14 : Include CH14 in channel group. */
AnnaBridge	171:3a7713b1edbc	4511	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
AnnaBridge	171:3a7713b1edbc	4512	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
AnnaBridge	171:3a7713b1edbc	4513	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4514	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4515
AnnaBridge	171:3a7713b1edbc	4516	/* Bit 13 : Include CH13 in channel group. */
AnnaBridge	171:3a7713b1edbc	4517	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
AnnaBridge	171:3a7713b1edbc	4518	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
AnnaBridge	171:3a7713b1edbc	4519	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4520	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4521
AnnaBridge	171:3a7713b1edbc	4522	/* Bit 12 : Include CH12 in channel group. */
AnnaBridge	171:3a7713b1edbc	4523	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
AnnaBridge	171:3a7713b1edbc	4524	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
AnnaBridge	171:3a7713b1edbc	4525	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4526	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4527
AnnaBridge	171:3a7713b1edbc	4528	/* Bit 11 : Include CH11 in channel group. */
AnnaBridge	171:3a7713b1edbc	4529	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
AnnaBridge	171:3a7713b1edbc	4530	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
AnnaBridge	171:3a7713b1edbc	4531	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4532	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4533
AnnaBridge	171:3a7713b1edbc	4534	/* Bit 10 : Include CH10 in channel group. */
AnnaBridge	171:3a7713b1edbc	4535	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
AnnaBridge	171:3a7713b1edbc	4536	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
AnnaBridge	171:3a7713b1edbc	4537	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4538	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4539
AnnaBridge	171:3a7713b1edbc	4540	/* Bit 9 : Include CH9 in channel group. */
AnnaBridge	171:3a7713b1edbc	4541	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
AnnaBridge	171:3a7713b1edbc	4542	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
AnnaBridge	171:3a7713b1edbc	4543	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4544	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4545
AnnaBridge	171:3a7713b1edbc	4546	/* Bit 8 : Include CH8 in channel group. */
AnnaBridge	171:3a7713b1edbc	4547	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
AnnaBridge	171:3a7713b1edbc	4548	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
AnnaBridge	171:3a7713b1edbc	4549	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4550	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4551
AnnaBridge	171:3a7713b1edbc	4552	/* Bit 7 : Include CH7 in channel group. */
AnnaBridge	171:3a7713b1edbc	4553	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
AnnaBridge	171:3a7713b1edbc	4554	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
AnnaBridge	171:3a7713b1edbc	4555	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4556	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4557
AnnaBridge	171:3a7713b1edbc	4558	/* Bit 6 : Include CH6 in channel group. */
AnnaBridge	171:3a7713b1edbc	4559	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
AnnaBridge	171:3a7713b1edbc	4560	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
AnnaBridge	171:3a7713b1edbc	4561	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4562	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4563
AnnaBridge	171:3a7713b1edbc	4564	/* Bit 5 : Include CH5 in channel group. */
AnnaBridge	171:3a7713b1edbc	4565	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
AnnaBridge	171:3a7713b1edbc	4566	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
AnnaBridge	171:3a7713b1edbc	4567	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4568	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4569
AnnaBridge	171:3a7713b1edbc	4570	/* Bit 4 : Include CH4 in channel group. */
AnnaBridge	171:3a7713b1edbc	4571	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4572	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
AnnaBridge	171:3a7713b1edbc	4573	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4574	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4575
AnnaBridge	171:3a7713b1edbc	4576	/* Bit 3 : Include CH3 in channel group. */
AnnaBridge	171:3a7713b1edbc	4577	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4578	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
AnnaBridge	171:3a7713b1edbc	4579	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4580	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4581
AnnaBridge	171:3a7713b1edbc	4582	/* Bit 2 : Include CH2 in channel group. */
AnnaBridge	171:3a7713b1edbc	4583	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4584	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
AnnaBridge	171:3a7713b1edbc	4585	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4586	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4587
AnnaBridge	171:3a7713b1edbc	4588	/* Bit 1 : Include CH1 in channel group. */
AnnaBridge	171:3a7713b1edbc	4589	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4590	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
AnnaBridge	171:3a7713b1edbc	4591	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4592	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4593
AnnaBridge	171:3a7713b1edbc	4594	/* Bit 0 : Include CH0 in channel group. */
AnnaBridge	171:3a7713b1edbc	4595	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4596	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
AnnaBridge	171:3a7713b1edbc	4597	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
AnnaBridge	171:3a7713b1edbc	4598	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
AnnaBridge	171:3a7713b1edbc	4599
AnnaBridge	171:3a7713b1edbc	4600
AnnaBridge	171:3a7713b1edbc	4601	/* Peripheral: QDEC */
AnnaBridge	171:3a7713b1edbc	4602	/* Description: Rotary decoder. */
AnnaBridge	171:3a7713b1edbc	4603
AnnaBridge	171:3a7713b1edbc	4604	/* Register: QDEC_SHORTS */
AnnaBridge	171:3a7713b1edbc	4605	/* Description: Shortcuts for the QDEC. */
AnnaBridge	171:3a7713b1edbc	4606
AnnaBridge	171:3a7713b1edbc	4607	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
AnnaBridge	171:3a7713b1edbc	4608	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
AnnaBridge	171:3a7713b1edbc	4609	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
AnnaBridge	171:3a7713b1edbc	4610	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4611	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4612
AnnaBridge	171:3a7713b1edbc	4613	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
AnnaBridge	171:3a7713b1edbc	4614	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
AnnaBridge	171:3a7713b1edbc	4615	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
AnnaBridge	171:3a7713b1edbc	4616	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4617	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4618
AnnaBridge	171:3a7713b1edbc	4619	/* Register: QDEC_INTENSET */
AnnaBridge	171:3a7713b1edbc	4620	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	4621
AnnaBridge	171:3a7713b1edbc	4622	/* Bit 2 : Enable interrupt on ACCOF event. */
AnnaBridge	171:3a7713b1edbc	4623	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
AnnaBridge	171:3a7713b1edbc	4624	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
AnnaBridge	171:3a7713b1edbc	4625	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4626	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4627	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4628
AnnaBridge	171:3a7713b1edbc	4629	/* Bit 1 : Enable interrupt on REPORTRDY event. */
AnnaBridge	171:3a7713b1edbc	4630	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
AnnaBridge	171:3a7713b1edbc	4631	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
AnnaBridge	171:3a7713b1edbc	4632	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4633	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4634	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4635
AnnaBridge	171:3a7713b1edbc	4636	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
AnnaBridge	171:3a7713b1edbc	4637	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
AnnaBridge	171:3a7713b1edbc	4638	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
AnnaBridge	171:3a7713b1edbc	4639	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4640	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4641	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4642
AnnaBridge	171:3a7713b1edbc	4643	/* Register: QDEC_INTENCLR */
AnnaBridge	171:3a7713b1edbc	4644	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	4645
AnnaBridge	171:3a7713b1edbc	4646	/* Bit 2 : Disable interrupt on ACCOF event. */
AnnaBridge	171:3a7713b1edbc	4647	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
AnnaBridge	171:3a7713b1edbc	4648	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
AnnaBridge	171:3a7713b1edbc	4649	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4650	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4651	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4652
AnnaBridge	171:3a7713b1edbc	4653	/* Bit 1 : Disable interrupt on REPORTRDY event. */
AnnaBridge	171:3a7713b1edbc	4654	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
AnnaBridge	171:3a7713b1edbc	4655	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
AnnaBridge	171:3a7713b1edbc	4656	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4657	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4658	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4659
AnnaBridge	171:3a7713b1edbc	4660	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
AnnaBridge	171:3a7713b1edbc	4661	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
AnnaBridge	171:3a7713b1edbc	4662	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
AnnaBridge	171:3a7713b1edbc	4663	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4664	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4665	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4666
AnnaBridge	171:3a7713b1edbc	4667	/* Register: QDEC_ENABLE */
AnnaBridge	171:3a7713b1edbc	4668	/* Description: Enable the QDEC. */
AnnaBridge	171:3a7713b1edbc	4669
AnnaBridge	171:3a7713b1edbc	4670	/* Bit 0 : Enable or disable QDEC. */
AnnaBridge	171:3a7713b1edbc	4671	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	4672	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	4673	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
AnnaBridge	171:3a7713b1edbc	4674	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
AnnaBridge	171:3a7713b1edbc	4675
AnnaBridge	171:3a7713b1edbc	4676	/* Register: QDEC_LEDPOL */
AnnaBridge	171:3a7713b1edbc	4677	/* Description: LED output pin polarity. */
AnnaBridge	171:3a7713b1edbc	4678
AnnaBridge	171:3a7713b1edbc	4679	/* Bit 0 : LED output pin polarity. */
AnnaBridge	171:3a7713b1edbc	4680	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
AnnaBridge	171:3a7713b1edbc	4681	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
AnnaBridge	171:3a7713b1edbc	4682	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
AnnaBridge	171:3a7713b1edbc	4683	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
AnnaBridge	171:3a7713b1edbc	4684
AnnaBridge	171:3a7713b1edbc	4685	/* Register: QDEC_SAMPLEPER */
AnnaBridge	171:3a7713b1edbc	4686	/* Description: Sample period. */
AnnaBridge	171:3a7713b1edbc	4687
AnnaBridge	171:3a7713b1edbc	4688	/* Bits 2..0 : Sample period. */
AnnaBridge	171:3a7713b1edbc	4689	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
AnnaBridge	171:3a7713b1edbc	4690	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
AnnaBridge	171:3a7713b1edbc	4691	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
AnnaBridge	171:3a7713b1edbc	4692	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
AnnaBridge	171:3a7713b1edbc	4693	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
AnnaBridge	171:3a7713b1edbc	4694	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
AnnaBridge	171:3a7713b1edbc	4695	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
AnnaBridge	171:3a7713b1edbc	4696	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
AnnaBridge	171:3a7713b1edbc	4697	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
AnnaBridge	171:3a7713b1edbc	4698	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
AnnaBridge	171:3a7713b1edbc	4699
AnnaBridge	171:3a7713b1edbc	4700	/* Register: QDEC_SAMPLE */
AnnaBridge	171:3a7713b1edbc	4701	/* Description: Motion sample value. */
AnnaBridge	171:3a7713b1edbc	4702
AnnaBridge	171:3a7713b1edbc	4703	/* Bits 31..0 : Last sample taken in compliment to 2. */
AnnaBridge	171:3a7713b1edbc	4704	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
AnnaBridge	171:3a7713b1edbc	4705	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
AnnaBridge	171:3a7713b1edbc	4706
AnnaBridge	171:3a7713b1edbc	4707	/* Register: QDEC_REPORTPER */
AnnaBridge	171:3a7713b1edbc	4708	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
AnnaBridge	171:3a7713b1edbc	4709
AnnaBridge	171:3a7713b1edbc	4710	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
AnnaBridge	171:3a7713b1edbc	4711	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
AnnaBridge	171:3a7713b1edbc	4712	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
AnnaBridge	171:3a7713b1edbc	4713	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
AnnaBridge	171:3a7713b1edbc	4714	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
AnnaBridge	171:3a7713b1edbc	4715	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
AnnaBridge	171:3a7713b1edbc	4716	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
AnnaBridge	171:3a7713b1edbc	4717	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
AnnaBridge	171:3a7713b1edbc	4718	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
AnnaBridge	171:3a7713b1edbc	4719	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
AnnaBridge	171:3a7713b1edbc	4720	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
AnnaBridge	171:3a7713b1edbc	4721
AnnaBridge	171:3a7713b1edbc	4722	/* Register: QDEC_DBFEN */
AnnaBridge	171:3a7713b1edbc	4723	/* Description: Enable debouncer input filters. */
AnnaBridge	171:3a7713b1edbc	4724
AnnaBridge	171:3a7713b1edbc	4725	/* Bit 0 : Enable debounce input filters. */
AnnaBridge	171:3a7713b1edbc	4726	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
AnnaBridge	171:3a7713b1edbc	4727	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
AnnaBridge	171:3a7713b1edbc	4728	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
AnnaBridge	171:3a7713b1edbc	4729	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
AnnaBridge	171:3a7713b1edbc	4730
AnnaBridge	171:3a7713b1edbc	4731	/* Register: QDEC_LEDPRE */
AnnaBridge	171:3a7713b1edbc	4732	/* Description: Time LED is switched ON before the sample. */
AnnaBridge	171:3a7713b1edbc	4733
AnnaBridge	171:3a7713b1edbc	4734	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
AnnaBridge	171:3a7713b1edbc	4735	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
AnnaBridge	171:3a7713b1edbc	4736	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
AnnaBridge	171:3a7713b1edbc	4737
AnnaBridge	171:3a7713b1edbc	4738	/* Register: QDEC_ACCDBL */
AnnaBridge	171:3a7713b1edbc	4739	/* Description: Accumulated double (error) transitions register. */
AnnaBridge	171:3a7713b1edbc	4740
AnnaBridge	171:3a7713b1edbc	4741	/* Bits 3..0 : Accumulated double (error) transitions. */
AnnaBridge	171:3a7713b1edbc	4742	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
AnnaBridge	171:3a7713b1edbc	4743	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
AnnaBridge	171:3a7713b1edbc	4744
AnnaBridge	171:3a7713b1edbc	4745	/* Register: QDEC_ACCDBLREAD */
AnnaBridge	171:3a7713b1edbc	4746	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
AnnaBridge	171:3a7713b1edbc	4747
AnnaBridge	171:3a7713b1edbc	4748	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
AnnaBridge	171:3a7713b1edbc	4749	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
AnnaBridge	171:3a7713b1edbc	4750	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
AnnaBridge	171:3a7713b1edbc	4751
AnnaBridge	171:3a7713b1edbc	4752	/* Register: QDEC_POWER */
AnnaBridge	171:3a7713b1edbc	4753	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	4754
AnnaBridge	171:3a7713b1edbc	4755	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	4756	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	4757	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	4758	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	4759	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	4760
AnnaBridge	171:3a7713b1edbc	4761
AnnaBridge	171:3a7713b1edbc	4762	/* Peripheral: RADIO */
AnnaBridge	171:3a7713b1edbc	4763	/* Description: The radio. */
AnnaBridge	171:3a7713b1edbc	4764
AnnaBridge	171:3a7713b1edbc	4765	/* Register: RADIO_SHORTS */
AnnaBridge	171:3a7713b1edbc	4766	/* Description: Shortcuts for the radio. */
AnnaBridge	171:3a7713b1edbc	4767
AnnaBridge	171:3a7713b1edbc	4768	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
AnnaBridge	171:3a7713b1edbc	4769	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
AnnaBridge	171:3a7713b1edbc	4770	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
AnnaBridge	171:3a7713b1edbc	4771	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4772	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4773
AnnaBridge	171:3a7713b1edbc	4774	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
AnnaBridge	171:3a7713b1edbc	4775	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
AnnaBridge	171:3a7713b1edbc	4776	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
AnnaBridge	171:3a7713b1edbc	4777	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4778	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4779
AnnaBridge	171:3a7713b1edbc	4780	/* Bit 5 : Shortcut between END event and START task. */
AnnaBridge	171:3a7713b1edbc	4781	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
AnnaBridge	171:3a7713b1edbc	4782	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
AnnaBridge	171:3a7713b1edbc	4783	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4784	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4785
AnnaBridge	171:3a7713b1edbc	4786	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
AnnaBridge	171:3a7713b1edbc	4787	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
AnnaBridge	171:3a7713b1edbc	4788	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
AnnaBridge	171:3a7713b1edbc	4789	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4790	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4791
AnnaBridge	171:3a7713b1edbc	4792	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
AnnaBridge	171:3a7713b1edbc	4793	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
AnnaBridge	171:3a7713b1edbc	4794	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
AnnaBridge	171:3a7713b1edbc	4795	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4796	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4797
AnnaBridge	171:3a7713b1edbc	4798	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
AnnaBridge	171:3a7713b1edbc	4799	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
AnnaBridge	171:3a7713b1edbc	4800	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
AnnaBridge	171:3a7713b1edbc	4801	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4802	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4803
AnnaBridge	171:3a7713b1edbc	4804	/* Bit 1 : Shortcut between END event and DISABLE task. */
AnnaBridge	171:3a7713b1edbc	4805	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
AnnaBridge	171:3a7713b1edbc	4806	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
AnnaBridge	171:3a7713b1edbc	4807	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4808	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4809
AnnaBridge	171:3a7713b1edbc	4810	/* Bit 0 : Shortcut between READY event and START task. */
AnnaBridge	171:3a7713b1edbc	4811	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
AnnaBridge	171:3a7713b1edbc	4812	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
AnnaBridge	171:3a7713b1edbc	4813	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	4814	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	4815
AnnaBridge	171:3a7713b1edbc	4816	/* Register: RADIO_INTENSET */
AnnaBridge	171:3a7713b1edbc	4817	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	4818
AnnaBridge	171:3a7713b1edbc	4819	/* Bit 10 : Enable interrupt on BCMATCH event. */
AnnaBridge	171:3a7713b1edbc	4820	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
AnnaBridge	171:3a7713b1edbc	4821	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
AnnaBridge	171:3a7713b1edbc	4822	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4823	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4824	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4825
AnnaBridge	171:3a7713b1edbc	4826	/* Bit 7 : Enable interrupt on RSSIEND event. */
AnnaBridge	171:3a7713b1edbc	4827	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
AnnaBridge	171:3a7713b1edbc	4828	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
AnnaBridge	171:3a7713b1edbc	4829	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4830	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4831	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4832
AnnaBridge	171:3a7713b1edbc	4833	/* Bit 6 : Enable interrupt on DEVMISS event. */
AnnaBridge	171:3a7713b1edbc	4834	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
AnnaBridge	171:3a7713b1edbc	4835	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
AnnaBridge	171:3a7713b1edbc	4836	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4837	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4838	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4839
AnnaBridge	171:3a7713b1edbc	4840	/* Bit 5 : Enable interrupt on DEVMATCH event. */
AnnaBridge	171:3a7713b1edbc	4841	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
AnnaBridge	171:3a7713b1edbc	4842	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
AnnaBridge	171:3a7713b1edbc	4843	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4844	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4845	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4846
AnnaBridge	171:3a7713b1edbc	4847	/* Bit 4 : Enable interrupt on DISABLED event. */
AnnaBridge	171:3a7713b1edbc	4848	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
AnnaBridge	171:3a7713b1edbc	4849	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
AnnaBridge	171:3a7713b1edbc	4850	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4851	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4852	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4853
AnnaBridge	171:3a7713b1edbc	4854	/* Bit 3 : Enable interrupt on END event. */
AnnaBridge	171:3a7713b1edbc	4855	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	4856	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	4857	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4858	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4859	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4860
AnnaBridge	171:3a7713b1edbc	4861	/* Bit 2 : Enable interrupt on PAYLOAD event. */
AnnaBridge	171:3a7713b1edbc	4862	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
AnnaBridge	171:3a7713b1edbc	4863	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
AnnaBridge	171:3a7713b1edbc	4864	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4865	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4866	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4867
AnnaBridge	171:3a7713b1edbc	4868	/* Bit 1 : Enable interrupt on ADDRESS event. */
AnnaBridge	171:3a7713b1edbc	4869	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
AnnaBridge	171:3a7713b1edbc	4870	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
AnnaBridge	171:3a7713b1edbc	4871	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4872	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4873	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4874
AnnaBridge	171:3a7713b1edbc	4875	/* Bit 0 : Enable interrupt on READY event. */
AnnaBridge	171:3a7713b1edbc	4876	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
AnnaBridge	171:3a7713b1edbc	4877	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
AnnaBridge	171:3a7713b1edbc	4878	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4879	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4880	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4881
AnnaBridge	171:3a7713b1edbc	4882	/* Register: RADIO_INTENCLR */
AnnaBridge	171:3a7713b1edbc	4883	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	4884
AnnaBridge	171:3a7713b1edbc	4885	/* Bit 10 : Disable interrupt on BCMATCH event. */
AnnaBridge	171:3a7713b1edbc	4886	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
AnnaBridge	171:3a7713b1edbc	4887	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
AnnaBridge	171:3a7713b1edbc	4888	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4889	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4890	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4891
AnnaBridge	171:3a7713b1edbc	4892	/* Bit 7 : Disable interrupt on RSSIEND event. */
AnnaBridge	171:3a7713b1edbc	4893	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
AnnaBridge	171:3a7713b1edbc	4894	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
AnnaBridge	171:3a7713b1edbc	4895	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4896	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4897	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4898
AnnaBridge	171:3a7713b1edbc	4899	/* Bit 6 : Disable interrupt on DEVMISS event. */
AnnaBridge	171:3a7713b1edbc	4900	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
AnnaBridge	171:3a7713b1edbc	4901	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
AnnaBridge	171:3a7713b1edbc	4902	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4903	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4904	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4905
AnnaBridge	171:3a7713b1edbc	4906	/* Bit 5 : Disable interrupt on DEVMATCH event. */
AnnaBridge	171:3a7713b1edbc	4907	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
AnnaBridge	171:3a7713b1edbc	4908	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
AnnaBridge	171:3a7713b1edbc	4909	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4910	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4911	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4912
AnnaBridge	171:3a7713b1edbc	4913	/* Bit 4 : Disable interrupt on DISABLED event. */
AnnaBridge	171:3a7713b1edbc	4914	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
AnnaBridge	171:3a7713b1edbc	4915	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
AnnaBridge	171:3a7713b1edbc	4916	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4917	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4918	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4919
AnnaBridge	171:3a7713b1edbc	4920	/* Bit 3 : Disable interrupt on END event. */
AnnaBridge	171:3a7713b1edbc	4921	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	4922	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	4923	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4924	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4925	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4926
AnnaBridge	171:3a7713b1edbc	4927	/* Bit 2 : Disable interrupt on PAYLOAD event. */
AnnaBridge	171:3a7713b1edbc	4928	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
AnnaBridge	171:3a7713b1edbc	4929	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
AnnaBridge	171:3a7713b1edbc	4930	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4931	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4932	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4933
AnnaBridge	171:3a7713b1edbc	4934	/* Bit 1 : Disable interrupt on ADDRESS event. */
AnnaBridge	171:3a7713b1edbc	4935	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
AnnaBridge	171:3a7713b1edbc	4936	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
AnnaBridge	171:3a7713b1edbc	4937	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4938	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4939	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4940
AnnaBridge	171:3a7713b1edbc	4941	/* Bit 0 : Disable interrupt on READY event. */
AnnaBridge	171:3a7713b1edbc	4942	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
AnnaBridge	171:3a7713b1edbc	4943	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
AnnaBridge	171:3a7713b1edbc	4944	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	4945	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	4946	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	4947
AnnaBridge	171:3a7713b1edbc	4948	/* Register: RADIO_CRCSTATUS */
AnnaBridge	171:3a7713b1edbc	4949	/* Description: CRC status of received packet. */
AnnaBridge	171:3a7713b1edbc	4950
AnnaBridge	171:3a7713b1edbc	4951	/* Bit 0 : CRC status of received packet. */
AnnaBridge	171:3a7713b1edbc	4952	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
AnnaBridge	171:3a7713b1edbc	4953	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
AnnaBridge	171:3a7713b1edbc	4954	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
AnnaBridge	171:3a7713b1edbc	4955	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
AnnaBridge	171:3a7713b1edbc	4956
AnnaBridge	171:3a7713b1edbc	4957	/* Register: RADIO_RXMATCH */
AnnaBridge	171:3a7713b1edbc	4958	/* Description: Received address. */
AnnaBridge	171:3a7713b1edbc	4959
AnnaBridge	171:3a7713b1edbc	4960	/* Bits 2..0 : Logical address in which previous packet was received. */
AnnaBridge	171:3a7713b1edbc	4961	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
AnnaBridge	171:3a7713b1edbc	4962	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
AnnaBridge	171:3a7713b1edbc	4963
AnnaBridge	171:3a7713b1edbc	4964	/* Register: RADIO_RXCRC */
AnnaBridge	171:3a7713b1edbc	4965	/* Description: Received CRC. */
AnnaBridge	171:3a7713b1edbc	4966
AnnaBridge	171:3a7713b1edbc	4967	/* Bits 23..0 : CRC field of previously received packet. */
AnnaBridge	171:3a7713b1edbc	4968	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
AnnaBridge	171:3a7713b1edbc	4969	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
AnnaBridge	171:3a7713b1edbc	4970
AnnaBridge	171:3a7713b1edbc	4971	/* Register: RADIO_DAI */
AnnaBridge	171:3a7713b1edbc	4972	/* Description: Device address match index. */
AnnaBridge	171:3a7713b1edbc	4973
AnnaBridge	171:3a7713b1edbc	4974	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
AnnaBridge	171:3a7713b1edbc	4975	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
AnnaBridge	171:3a7713b1edbc	4976	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
AnnaBridge	171:3a7713b1edbc	4977
AnnaBridge	171:3a7713b1edbc	4978	/* Register: RADIO_FREQUENCY */
AnnaBridge	171:3a7713b1edbc	4979	/* Description: Frequency. */
AnnaBridge	171:3a7713b1edbc	4980
AnnaBridge	171:3a7713b1edbc	4981	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
AnnaBridge	171:3a7713b1edbc	4982	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	4983	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	4984
AnnaBridge	171:3a7713b1edbc	4985	/* Register: RADIO_TXPOWER */
AnnaBridge	171:3a7713b1edbc	4986	/* Description: Output power. */
AnnaBridge	171:3a7713b1edbc	4987
AnnaBridge	171:3a7713b1edbc	4988	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
AnnaBridge	171:3a7713b1edbc	4989	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
AnnaBridge	171:3a7713b1edbc	4990	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
AnnaBridge	171:3a7713b1edbc	4991	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
AnnaBridge	171:3a7713b1edbc	4992	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
AnnaBridge	171:3a7713b1edbc	4993	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
AnnaBridge	171:3a7713b1edbc	4994	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
AnnaBridge	171:3a7713b1edbc	4995	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
AnnaBridge	171:3a7713b1edbc	4996	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
AnnaBridge	171:3a7713b1edbc	4997	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
AnnaBridge	171:3a7713b1edbc	4998	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
AnnaBridge	171:3a7713b1edbc	4999
AnnaBridge	171:3a7713b1edbc	5000	/* Register: RADIO_MODE */
AnnaBridge	171:3a7713b1edbc	5001	/* Description: Data rate and modulation. */
AnnaBridge	171:3a7713b1edbc	5002
AnnaBridge	171:3a7713b1edbc	5003	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
AnnaBridge	171:3a7713b1edbc	5004	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
AnnaBridge	171:3a7713b1edbc	5005	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
AnnaBridge	171:3a7713b1edbc	5006	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
AnnaBridge	171:3a7713b1edbc	5007	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
AnnaBridge	171:3a7713b1edbc	5008	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
AnnaBridge	171:3a7713b1edbc	5009	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
AnnaBridge	171:3a7713b1edbc	5010
AnnaBridge	171:3a7713b1edbc	5011	/* Register: RADIO_PCNF0 */
AnnaBridge	171:3a7713b1edbc	5012	/* Description: Packet configuration 0. */
AnnaBridge	171:3a7713b1edbc	5013
AnnaBridge	171:3a7713b1edbc	5014	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5015	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
AnnaBridge	171:3a7713b1edbc	5016	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
AnnaBridge	171:3a7713b1edbc	5017
AnnaBridge	171:3a7713b1edbc	5018	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5019	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
AnnaBridge	171:3a7713b1edbc	5020	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
AnnaBridge	171:3a7713b1edbc	5021
AnnaBridge	171:3a7713b1edbc	5022	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5023	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
AnnaBridge	171:3a7713b1edbc	5024	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
AnnaBridge	171:3a7713b1edbc	5025
AnnaBridge	171:3a7713b1edbc	5026	/* Register: RADIO_PCNF1 */
AnnaBridge	171:3a7713b1edbc	5027	/* Description: Packet configuration 1. */
AnnaBridge	171:3a7713b1edbc	5028
AnnaBridge	171:3a7713b1edbc	5029	/* Bit 25 : Packet whitening enable. */
AnnaBridge	171:3a7713b1edbc	5030	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
AnnaBridge	171:3a7713b1edbc	5031	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
AnnaBridge	171:3a7713b1edbc	5032	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
AnnaBridge	171:3a7713b1edbc	5033	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
AnnaBridge	171:3a7713b1edbc	5034
AnnaBridge	171:3a7713b1edbc	5035	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5036	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
AnnaBridge	171:3a7713b1edbc	5037	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
AnnaBridge	171:3a7713b1edbc	5038	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
AnnaBridge	171:3a7713b1edbc	5039	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
AnnaBridge	171:3a7713b1edbc	5040
AnnaBridge	171:3a7713b1edbc	5041	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5042	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
AnnaBridge	171:3a7713b1edbc	5043	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
AnnaBridge	171:3a7713b1edbc	5044
AnnaBridge	171:3a7713b1edbc	5045	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5046	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
AnnaBridge	171:3a7713b1edbc	5047	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
AnnaBridge	171:3a7713b1edbc	5048
AnnaBridge	171:3a7713b1edbc	5049	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
AnnaBridge	171:3a7713b1edbc	5050	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
AnnaBridge	171:3a7713b1edbc	5051	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
AnnaBridge	171:3a7713b1edbc	5052
AnnaBridge	171:3a7713b1edbc	5053	/* Register: RADIO_PREFIX0 */
AnnaBridge	171:3a7713b1edbc	5054	/* Description: Prefixes bytes for logical addresses 0 to 3. */
AnnaBridge	171:3a7713b1edbc	5055
AnnaBridge	171:3a7713b1edbc	5056	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5057	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
AnnaBridge	171:3a7713b1edbc	5058	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
AnnaBridge	171:3a7713b1edbc	5059
AnnaBridge	171:3a7713b1edbc	5060	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5061	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
AnnaBridge	171:3a7713b1edbc	5062	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
AnnaBridge	171:3a7713b1edbc	5063
AnnaBridge	171:3a7713b1edbc	5064	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5065	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
AnnaBridge	171:3a7713b1edbc	5066	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
AnnaBridge	171:3a7713b1edbc	5067
AnnaBridge	171:3a7713b1edbc	5068	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5069	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
AnnaBridge	171:3a7713b1edbc	5070	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
AnnaBridge	171:3a7713b1edbc	5071
AnnaBridge	171:3a7713b1edbc	5072	/* Register: RADIO_PREFIX1 */
AnnaBridge	171:3a7713b1edbc	5073	/* Description: Prefixes bytes for logical addresses 4 to 7. */
AnnaBridge	171:3a7713b1edbc	5074
AnnaBridge	171:3a7713b1edbc	5075	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5076	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
AnnaBridge	171:3a7713b1edbc	5077	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
AnnaBridge	171:3a7713b1edbc	5078
AnnaBridge	171:3a7713b1edbc	5079	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5080	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
AnnaBridge	171:3a7713b1edbc	5081	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
AnnaBridge	171:3a7713b1edbc	5082
AnnaBridge	171:3a7713b1edbc	5083	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5084	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
AnnaBridge	171:3a7713b1edbc	5085	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
AnnaBridge	171:3a7713b1edbc	5086
AnnaBridge	171:3a7713b1edbc	5087	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5088	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
AnnaBridge	171:3a7713b1edbc	5089	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
AnnaBridge	171:3a7713b1edbc	5090
AnnaBridge	171:3a7713b1edbc	5091	/* Register: RADIO_TXADDRESS */
AnnaBridge	171:3a7713b1edbc	5092	/* Description: Transmit address select. */
AnnaBridge	171:3a7713b1edbc	5093
AnnaBridge	171:3a7713b1edbc	5094	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5095	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
AnnaBridge	171:3a7713b1edbc	5096	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
AnnaBridge	171:3a7713b1edbc	5097
AnnaBridge	171:3a7713b1edbc	5098	/* Register: RADIO_RXADDRESSES */
AnnaBridge	171:3a7713b1edbc	5099	/* Description: Receive address select. */
AnnaBridge	171:3a7713b1edbc	5100
AnnaBridge	171:3a7713b1edbc	5101	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5102	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
AnnaBridge	171:3a7713b1edbc	5103	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
AnnaBridge	171:3a7713b1edbc	5104	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5105	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5106
AnnaBridge	171:3a7713b1edbc	5107	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5108	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
AnnaBridge	171:3a7713b1edbc	5109	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
AnnaBridge	171:3a7713b1edbc	5110	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5111	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5112
AnnaBridge	171:3a7713b1edbc	5113	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5114	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
AnnaBridge	171:3a7713b1edbc	5115	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
AnnaBridge	171:3a7713b1edbc	5116	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5117	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5118
AnnaBridge	171:3a7713b1edbc	5119	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5120	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
AnnaBridge	171:3a7713b1edbc	5121	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
AnnaBridge	171:3a7713b1edbc	5122	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5123	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5124
AnnaBridge	171:3a7713b1edbc	5125	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5126	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
AnnaBridge	171:3a7713b1edbc	5127	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
AnnaBridge	171:3a7713b1edbc	5128	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5129	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5130
AnnaBridge	171:3a7713b1edbc	5131	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5132	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
AnnaBridge	171:3a7713b1edbc	5133	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
AnnaBridge	171:3a7713b1edbc	5134	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5135	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5136
AnnaBridge	171:3a7713b1edbc	5137	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5138	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
AnnaBridge	171:3a7713b1edbc	5139	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
AnnaBridge	171:3a7713b1edbc	5140	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5141	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5142
AnnaBridge	171:3a7713b1edbc	5143	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5144	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
AnnaBridge	171:3a7713b1edbc	5145	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
AnnaBridge	171:3a7713b1edbc	5146	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
AnnaBridge	171:3a7713b1edbc	5147	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
AnnaBridge	171:3a7713b1edbc	5148
AnnaBridge	171:3a7713b1edbc	5149	/* Register: RADIO_CRCCNF */
AnnaBridge	171:3a7713b1edbc	5150	/* Description: CRC configuration. */
AnnaBridge	171:3a7713b1edbc	5151
AnnaBridge	171:3a7713b1edbc	5152	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5153	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
AnnaBridge	171:3a7713b1edbc	5154	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
AnnaBridge	171:3a7713b1edbc	5155	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
AnnaBridge	171:3a7713b1edbc	5156	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
AnnaBridge	171:3a7713b1edbc	5157
AnnaBridge	171:3a7713b1edbc	5158	/* Bits 1..0 : CRC length. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5159	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
AnnaBridge	171:3a7713b1edbc	5160	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
AnnaBridge	171:3a7713b1edbc	5161	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
AnnaBridge	171:3a7713b1edbc	5162	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
AnnaBridge	171:3a7713b1edbc	5163	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
AnnaBridge	171:3a7713b1edbc	5164	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
AnnaBridge	171:3a7713b1edbc	5165
AnnaBridge	171:3a7713b1edbc	5166	/* Register: RADIO_CRCPOLY */
AnnaBridge	171:3a7713b1edbc	5167	/* Description: CRC polynomial. */
AnnaBridge	171:3a7713b1edbc	5168
AnnaBridge	171:3a7713b1edbc	5169	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5170	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
AnnaBridge	171:3a7713b1edbc	5171	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
AnnaBridge	171:3a7713b1edbc	5172
AnnaBridge	171:3a7713b1edbc	5173	/* Register: RADIO_CRCINIT */
AnnaBridge	171:3a7713b1edbc	5174	/* Description: CRC initial value. */
AnnaBridge	171:3a7713b1edbc	5175
AnnaBridge	171:3a7713b1edbc	5176	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
AnnaBridge	171:3a7713b1edbc	5177	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
AnnaBridge	171:3a7713b1edbc	5178	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
AnnaBridge	171:3a7713b1edbc	5179
AnnaBridge	171:3a7713b1edbc	5180	/* Register: RADIO_TEST */
AnnaBridge	171:3a7713b1edbc	5181	/* Description: Test features enable register. */
AnnaBridge	171:3a7713b1edbc	5182
AnnaBridge	171:3a7713b1edbc	5183	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
AnnaBridge	171:3a7713b1edbc	5184	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
AnnaBridge	171:3a7713b1edbc	5185	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
AnnaBridge	171:3a7713b1edbc	5186	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
AnnaBridge	171:3a7713b1edbc	5187	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
AnnaBridge	171:3a7713b1edbc	5188
AnnaBridge	171:3a7713b1edbc	5189	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
AnnaBridge	171:3a7713b1edbc	5190	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
AnnaBridge	171:3a7713b1edbc	5191	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
AnnaBridge	171:3a7713b1edbc	5192	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
AnnaBridge	171:3a7713b1edbc	5193	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
AnnaBridge	171:3a7713b1edbc	5194
AnnaBridge	171:3a7713b1edbc	5195	/* Register: RADIO_TIFS */
AnnaBridge	171:3a7713b1edbc	5196	/* Description: Inter Frame Spacing in microseconds. */
AnnaBridge	171:3a7713b1edbc	5197
AnnaBridge	171:3a7713b1edbc	5198	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
AnnaBridge	171:3a7713b1edbc	5199	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
AnnaBridge	171:3a7713b1edbc	5200	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
AnnaBridge	171:3a7713b1edbc	5201
AnnaBridge	171:3a7713b1edbc	5202	/* Register: RADIO_RSSISAMPLE */
AnnaBridge	171:3a7713b1edbc	5203	/* Description: RSSI sample. */
AnnaBridge	171:3a7713b1edbc	5204
AnnaBridge	171:3a7713b1edbc	5205	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
AnnaBridge	171:3a7713b1edbc	5206	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
AnnaBridge	171:3a7713b1edbc	5207	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
AnnaBridge	171:3a7713b1edbc	5208
AnnaBridge	171:3a7713b1edbc	5209	/* Register: RADIO_STATE */
AnnaBridge	171:3a7713b1edbc	5210	/* Description: Current radio state. */
AnnaBridge	171:3a7713b1edbc	5211
AnnaBridge	171:3a7713b1edbc	5212	/* Bits 3..0 : Current radio state. */
AnnaBridge	171:3a7713b1edbc	5213	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
AnnaBridge	171:3a7713b1edbc	5214	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
AnnaBridge	171:3a7713b1edbc	5215	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
AnnaBridge	171:3a7713b1edbc	5216	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
AnnaBridge	171:3a7713b1edbc	5217	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
AnnaBridge	171:3a7713b1edbc	5218	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
AnnaBridge	171:3a7713b1edbc	5219	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
AnnaBridge	171:3a7713b1edbc	5220	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
AnnaBridge	171:3a7713b1edbc	5221	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
AnnaBridge	171:3a7713b1edbc	5222	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
AnnaBridge	171:3a7713b1edbc	5223	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
AnnaBridge	171:3a7713b1edbc	5224
AnnaBridge	171:3a7713b1edbc	5225	/* Register: RADIO_DATAWHITEIV */
AnnaBridge	171:3a7713b1edbc	5226	/* Description: Data whitening initial value. */
AnnaBridge	171:3a7713b1edbc	5227
AnnaBridge	171:3a7713b1edbc	5228	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
AnnaBridge	171:3a7713b1edbc	5229	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
AnnaBridge	171:3a7713b1edbc	5230	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
AnnaBridge	171:3a7713b1edbc	5231
AnnaBridge	171:3a7713b1edbc	5232	/* Register: RADIO_DAP */
AnnaBridge	171:3a7713b1edbc	5233	/* Description: Device address prefix. */
AnnaBridge	171:3a7713b1edbc	5234
AnnaBridge	171:3a7713b1edbc	5235	/* Bits 15..0 : Device address prefix. */
AnnaBridge	171:3a7713b1edbc	5236	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
AnnaBridge	171:3a7713b1edbc	5237	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
AnnaBridge	171:3a7713b1edbc	5238
AnnaBridge	171:3a7713b1edbc	5239	/* Register: RADIO_DACNF */
AnnaBridge	171:3a7713b1edbc	5240	/* Description: Device address match configuration. */
AnnaBridge	171:3a7713b1edbc	5241
AnnaBridge	171:3a7713b1edbc	5242	/* Bit 15 : TxAdd for device address 7. */
AnnaBridge	171:3a7713b1edbc	5243	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
AnnaBridge	171:3a7713b1edbc	5244	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
AnnaBridge	171:3a7713b1edbc	5245
AnnaBridge	171:3a7713b1edbc	5246	/* Bit 14 : TxAdd for device address 6. */
AnnaBridge	171:3a7713b1edbc	5247	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
AnnaBridge	171:3a7713b1edbc	5248	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
AnnaBridge	171:3a7713b1edbc	5249
AnnaBridge	171:3a7713b1edbc	5250	/* Bit 13 : TxAdd for device address 5. */
AnnaBridge	171:3a7713b1edbc	5251	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
AnnaBridge	171:3a7713b1edbc	5252	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
AnnaBridge	171:3a7713b1edbc	5253
AnnaBridge	171:3a7713b1edbc	5254	/* Bit 12 : TxAdd for device address 4. */
AnnaBridge	171:3a7713b1edbc	5255	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
AnnaBridge	171:3a7713b1edbc	5256	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
AnnaBridge	171:3a7713b1edbc	5257
AnnaBridge	171:3a7713b1edbc	5258	/* Bit 11 : TxAdd for device address 3. */
AnnaBridge	171:3a7713b1edbc	5259	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
AnnaBridge	171:3a7713b1edbc	5260	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
AnnaBridge	171:3a7713b1edbc	5261
AnnaBridge	171:3a7713b1edbc	5262	/* Bit 10 : TxAdd for device address 2. */
AnnaBridge	171:3a7713b1edbc	5263	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
AnnaBridge	171:3a7713b1edbc	5264	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
AnnaBridge	171:3a7713b1edbc	5265
AnnaBridge	171:3a7713b1edbc	5266	/* Bit 9 : TxAdd for device address 1. */
AnnaBridge	171:3a7713b1edbc	5267	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
AnnaBridge	171:3a7713b1edbc	5268	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
AnnaBridge	171:3a7713b1edbc	5269
AnnaBridge	171:3a7713b1edbc	5270	/* Bit 8 : TxAdd for device address 0. */
AnnaBridge	171:3a7713b1edbc	5271	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
AnnaBridge	171:3a7713b1edbc	5272	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
AnnaBridge	171:3a7713b1edbc	5273
AnnaBridge	171:3a7713b1edbc	5274	/* Bit 7 : Enable or disable device address matching using device address 7. */
AnnaBridge	171:3a7713b1edbc	5275	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
AnnaBridge	171:3a7713b1edbc	5276	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
AnnaBridge	171:3a7713b1edbc	5277	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5278	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5279
AnnaBridge	171:3a7713b1edbc	5280	/* Bit 6 : Enable or disable device address matching using device address 6. */
AnnaBridge	171:3a7713b1edbc	5281	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
AnnaBridge	171:3a7713b1edbc	5282	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
AnnaBridge	171:3a7713b1edbc	5283	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5284	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5285
AnnaBridge	171:3a7713b1edbc	5286	/* Bit 5 : Enable or disable device address matching using device address 5. */
AnnaBridge	171:3a7713b1edbc	5287	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
AnnaBridge	171:3a7713b1edbc	5288	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
AnnaBridge	171:3a7713b1edbc	5289	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5290	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5291
AnnaBridge	171:3a7713b1edbc	5292	/* Bit 4 : Enable or disable device address matching using device address 4. */
AnnaBridge	171:3a7713b1edbc	5293	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
AnnaBridge	171:3a7713b1edbc	5294	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
AnnaBridge	171:3a7713b1edbc	5295	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5296	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5297
AnnaBridge	171:3a7713b1edbc	5298	/* Bit 3 : Enable or disable device address matching using device address 3. */
AnnaBridge	171:3a7713b1edbc	5299	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
AnnaBridge	171:3a7713b1edbc	5300	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
AnnaBridge	171:3a7713b1edbc	5301	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5302	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5303
AnnaBridge	171:3a7713b1edbc	5304	/* Bit 2 : Enable or disable device address matching using device address 2. */
AnnaBridge	171:3a7713b1edbc	5305	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
AnnaBridge	171:3a7713b1edbc	5306	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
AnnaBridge	171:3a7713b1edbc	5307	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5308	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5309
AnnaBridge	171:3a7713b1edbc	5310	/* Bit 1 : Enable or disable device address matching using device address 1. */
AnnaBridge	171:3a7713b1edbc	5311	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
AnnaBridge	171:3a7713b1edbc	5312	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
AnnaBridge	171:3a7713b1edbc	5313	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5314	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5315
AnnaBridge	171:3a7713b1edbc	5316	/* Bit 0 : Enable or disable device address matching using device address 0. */
AnnaBridge	171:3a7713b1edbc	5317	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
AnnaBridge	171:3a7713b1edbc	5318	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
AnnaBridge	171:3a7713b1edbc	5319	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	5320	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	5321
AnnaBridge	171:3a7713b1edbc	5322	/* Register: RADIO_OVERRIDE0 */
AnnaBridge	171:3a7713b1edbc	5323	/* Description: Trim value override register 0. */
AnnaBridge	171:3a7713b1edbc	5324
AnnaBridge	171:3a7713b1edbc	5325	/* Bits 31..0 : Trim value override 0. */
AnnaBridge	171:3a7713b1edbc	5326	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
AnnaBridge	171:3a7713b1edbc	5327	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
AnnaBridge	171:3a7713b1edbc	5328
AnnaBridge	171:3a7713b1edbc	5329	/* Register: RADIO_OVERRIDE1 */
AnnaBridge	171:3a7713b1edbc	5330	/* Description: Trim value override register 1. */
AnnaBridge	171:3a7713b1edbc	5331
AnnaBridge	171:3a7713b1edbc	5332	/* Bits 31..0 : Trim value override 1. */
AnnaBridge	171:3a7713b1edbc	5333	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
AnnaBridge	171:3a7713b1edbc	5334	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
AnnaBridge	171:3a7713b1edbc	5335
AnnaBridge	171:3a7713b1edbc	5336	/* Register: RADIO_OVERRIDE2 */
AnnaBridge	171:3a7713b1edbc	5337	/* Description: Trim value override register 2. */
AnnaBridge	171:3a7713b1edbc	5338
AnnaBridge	171:3a7713b1edbc	5339	/* Bits 31..0 : Trim value override 2. */
AnnaBridge	171:3a7713b1edbc	5340	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
AnnaBridge	171:3a7713b1edbc	5341	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
AnnaBridge	171:3a7713b1edbc	5342
AnnaBridge	171:3a7713b1edbc	5343	/* Register: RADIO_OVERRIDE3 */
AnnaBridge	171:3a7713b1edbc	5344	/* Description: Trim value override register 3. */
AnnaBridge	171:3a7713b1edbc	5345
AnnaBridge	171:3a7713b1edbc	5346	/* Bits 31..0 : Trim value override 3. */
AnnaBridge	171:3a7713b1edbc	5347	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
AnnaBridge	171:3a7713b1edbc	5348	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
AnnaBridge	171:3a7713b1edbc	5349
AnnaBridge	171:3a7713b1edbc	5350	/* Register: RADIO_OVERRIDE4 */
AnnaBridge	171:3a7713b1edbc	5351	/* Description: Trim value override register 4. */
AnnaBridge	171:3a7713b1edbc	5352
AnnaBridge	171:3a7713b1edbc	5353	/* Bit 31 : Enable or disable override of default trim values. */
AnnaBridge	171:3a7713b1edbc	5354	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	5355	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	5356	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
AnnaBridge	171:3a7713b1edbc	5357	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
AnnaBridge	171:3a7713b1edbc	5358
AnnaBridge	171:3a7713b1edbc	5359	/* Bits 27..0 : Trim value override 4. */
AnnaBridge	171:3a7713b1edbc	5360	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
AnnaBridge	171:3a7713b1edbc	5361	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
AnnaBridge	171:3a7713b1edbc	5362
AnnaBridge	171:3a7713b1edbc	5363	/* Register: RADIO_POWER */
AnnaBridge	171:3a7713b1edbc	5364	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5365
AnnaBridge	171:3a7713b1edbc	5366	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5367	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	5368	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	5369	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	5370	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	5371
AnnaBridge	171:3a7713b1edbc	5372
AnnaBridge	171:3a7713b1edbc	5373	/* Peripheral: RNG */
AnnaBridge	171:3a7713b1edbc	5374	/* Description: Random Number Generator. */
AnnaBridge	171:3a7713b1edbc	5375
AnnaBridge	171:3a7713b1edbc	5376	/* Register: RNG_SHORTS */
AnnaBridge	171:3a7713b1edbc	5377	/* Description: Shortcuts for the RNG. */
AnnaBridge	171:3a7713b1edbc	5378
AnnaBridge	171:3a7713b1edbc	5379	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
AnnaBridge	171:3a7713b1edbc	5380	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
AnnaBridge	171:3a7713b1edbc	5381	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
AnnaBridge	171:3a7713b1edbc	5382	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	5383	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	5384
AnnaBridge	171:3a7713b1edbc	5385	/* Register: RNG_INTENSET */
AnnaBridge	171:3a7713b1edbc	5386	/* Description: Interrupt enable set register */
AnnaBridge	171:3a7713b1edbc	5387
AnnaBridge	171:3a7713b1edbc	5388	/* Bit 0 : Enable interrupt on VALRDY event. */
AnnaBridge	171:3a7713b1edbc	5389	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
AnnaBridge	171:3a7713b1edbc	5390	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
AnnaBridge	171:3a7713b1edbc	5391	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5392	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5393	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5394
AnnaBridge	171:3a7713b1edbc	5395	/* Register: RNG_INTENCLR */
AnnaBridge	171:3a7713b1edbc	5396	/* Description: Interrupt enable clear register */
AnnaBridge	171:3a7713b1edbc	5397
AnnaBridge	171:3a7713b1edbc	5398	/* Bit 0 : Disable interrupt on VALRDY event. */
AnnaBridge	171:3a7713b1edbc	5399	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
AnnaBridge	171:3a7713b1edbc	5400	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
AnnaBridge	171:3a7713b1edbc	5401	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5402	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5403	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5404
AnnaBridge	171:3a7713b1edbc	5405	/* Register: RNG_CONFIG */
AnnaBridge	171:3a7713b1edbc	5406	/* Description: Configuration register. */
AnnaBridge	171:3a7713b1edbc	5407
AnnaBridge	171:3a7713b1edbc	5408	/* Bit 0 : Digital error correction enable. */
AnnaBridge	171:3a7713b1edbc	5409	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
AnnaBridge	171:3a7713b1edbc	5410	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
AnnaBridge	171:3a7713b1edbc	5411	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
AnnaBridge	171:3a7713b1edbc	5412	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
AnnaBridge	171:3a7713b1edbc	5413
AnnaBridge	171:3a7713b1edbc	5414	/* Register: RNG_VALUE */
AnnaBridge	171:3a7713b1edbc	5415	/* Description: RNG random number. */
AnnaBridge	171:3a7713b1edbc	5416
AnnaBridge	171:3a7713b1edbc	5417	/* Bits 7..0 : Generated random number. */
AnnaBridge	171:3a7713b1edbc	5418	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
AnnaBridge	171:3a7713b1edbc	5419	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
AnnaBridge	171:3a7713b1edbc	5420
AnnaBridge	171:3a7713b1edbc	5421	/* Register: RNG_POWER */
AnnaBridge	171:3a7713b1edbc	5422	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5423
AnnaBridge	171:3a7713b1edbc	5424	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5425	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	5426	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	5427	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	5428	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	5429
AnnaBridge	171:3a7713b1edbc	5430
AnnaBridge	171:3a7713b1edbc	5431	/* Peripheral: RTC */
AnnaBridge	171:3a7713b1edbc	5432	/* Description: Real time counter 0. */
AnnaBridge	171:3a7713b1edbc	5433
AnnaBridge	171:3a7713b1edbc	5434	/* Register: RTC_INTENSET */
AnnaBridge	171:3a7713b1edbc	5435	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	5436
AnnaBridge	171:3a7713b1edbc	5437	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
AnnaBridge	171:3a7713b1edbc	5438	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5439	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5440	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5441	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5442	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5443
AnnaBridge	171:3a7713b1edbc	5444	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
AnnaBridge	171:3a7713b1edbc	5445	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5446	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5447	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5448	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5449	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5450
AnnaBridge	171:3a7713b1edbc	5451	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
AnnaBridge	171:3a7713b1edbc	5452	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5453	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5454	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5455	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5456	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5457
AnnaBridge	171:3a7713b1edbc	5458	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
AnnaBridge	171:3a7713b1edbc	5459	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5460	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5461	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5462	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5463	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5464
AnnaBridge	171:3a7713b1edbc	5465	/* Bit 1 : Enable interrupt on OVRFLW event. */
AnnaBridge	171:3a7713b1edbc	5466	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5467	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5468	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5469	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5470	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5471
AnnaBridge	171:3a7713b1edbc	5472	/* Bit 0 : Enable interrupt on TICK event. */
AnnaBridge	171:3a7713b1edbc	5473	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
AnnaBridge	171:3a7713b1edbc	5474	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
AnnaBridge	171:3a7713b1edbc	5475	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5476	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5477	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5478
AnnaBridge	171:3a7713b1edbc	5479	/* Register: RTC_INTENCLR */
AnnaBridge	171:3a7713b1edbc	5480	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	5481
AnnaBridge	171:3a7713b1edbc	5482	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
AnnaBridge	171:3a7713b1edbc	5483	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5484	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5485	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5486	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5487	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5488
AnnaBridge	171:3a7713b1edbc	5489	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
AnnaBridge	171:3a7713b1edbc	5490	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5491	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5492	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5493	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5494	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5495
AnnaBridge	171:3a7713b1edbc	5496	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
AnnaBridge	171:3a7713b1edbc	5497	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5498	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5499	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5500	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5501	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5502
AnnaBridge	171:3a7713b1edbc	5503	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
AnnaBridge	171:3a7713b1edbc	5504	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5505	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5506	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5507	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5508	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5509
AnnaBridge	171:3a7713b1edbc	5510	/* Bit 1 : Disable interrupt on OVRFLW event. */
AnnaBridge	171:3a7713b1edbc	5511	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5512	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5513	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5514	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5515	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5516
AnnaBridge	171:3a7713b1edbc	5517	/* Bit 0 : Disable interrupt on TICK event. */
AnnaBridge	171:3a7713b1edbc	5518	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
AnnaBridge	171:3a7713b1edbc	5519	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
AnnaBridge	171:3a7713b1edbc	5520	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5521	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5522	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5523
AnnaBridge	171:3a7713b1edbc	5524	/* Register: RTC_EVTEN */
AnnaBridge	171:3a7713b1edbc	5525	/* Description: Configures event enable routing to PPI for each RTC event. */
AnnaBridge	171:3a7713b1edbc	5526
AnnaBridge	171:3a7713b1edbc	5527	/* Bit 19 : COMPARE[3] event enable. */
AnnaBridge	171:3a7713b1edbc	5528	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5529	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5530	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5531	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5532
AnnaBridge	171:3a7713b1edbc	5533	/* Bit 18 : COMPARE[2] event enable. */
AnnaBridge	171:3a7713b1edbc	5534	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5535	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5536	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5537	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5538
AnnaBridge	171:3a7713b1edbc	5539	/* Bit 17 : COMPARE[1] event enable. */
AnnaBridge	171:3a7713b1edbc	5540	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5541	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5542	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5543	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5544
AnnaBridge	171:3a7713b1edbc	5545	/* Bit 16 : COMPARE[0] event enable. */
AnnaBridge	171:3a7713b1edbc	5546	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5547	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5548	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5549	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5550
AnnaBridge	171:3a7713b1edbc	5551	/* Bit 1 : OVRFLW event enable. */
AnnaBridge	171:3a7713b1edbc	5552	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5553	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5554	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5555	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5556
AnnaBridge	171:3a7713b1edbc	5557	/* Bit 0 : TICK event enable. */
AnnaBridge	171:3a7713b1edbc	5558	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
AnnaBridge	171:3a7713b1edbc	5559	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
AnnaBridge	171:3a7713b1edbc	5560	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5561	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5562
AnnaBridge	171:3a7713b1edbc	5563	/* Register: RTC_EVTENSET */
AnnaBridge	171:3a7713b1edbc	5564	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
AnnaBridge	171:3a7713b1edbc	5565
AnnaBridge	171:3a7713b1edbc	5566	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
AnnaBridge	171:3a7713b1edbc	5567	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5568	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5569	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5570	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5571	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
AnnaBridge	171:3a7713b1edbc	5572
AnnaBridge	171:3a7713b1edbc	5573	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
AnnaBridge	171:3a7713b1edbc	5574	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5575	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5576	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5577	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5578	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
AnnaBridge	171:3a7713b1edbc	5579
AnnaBridge	171:3a7713b1edbc	5580	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
AnnaBridge	171:3a7713b1edbc	5581	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5582	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5583	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5584	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5585	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
AnnaBridge	171:3a7713b1edbc	5586
AnnaBridge	171:3a7713b1edbc	5587	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
AnnaBridge	171:3a7713b1edbc	5588	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5589	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5590	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5591	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5592	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
AnnaBridge	171:3a7713b1edbc	5593
AnnaBridge	171:3a7713b1edbc	5594	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
AnnaBridge	171:3a7713b1edbc	5595	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5596	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5597	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5598	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5599	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
AnnaBridge	171:3a7713b1edbc	5600
AnnaBridge	171:3a7713b1edbc	5601	/* Bit 0 : Enable routing to PPI of TICK event. */
AnnaBridge	171:3a7713b1edbc	5602	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
AnnaBridge	171:3a7713b1edbc	5603	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
AnnaBridge	171:3a7713b1edbc	5604	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5605	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5606	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
AnnaBridge	171:3a7713b1edbc	5607
AnnaBridge	171:3a7713b1edbc	5608	/* Register: RTC_EVTENCLR */
AnnaBridge	171:3a7713b1edbc	5609	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
AnnaBridge	171:3a7713b1edbc	5610
AnnaBridge	171:3a7713b1edbc	5611	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
AnnaBridge	171:3a7713b1edbc	5612	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5613	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	5614	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5615	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5616	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
AnnaBridge	171:3a7713b1edbc	5617
AnnaBridge	171:3a7713b1edbc	5618	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
AnnaBridge	171:3a7713b1edbc	5619	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5620	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	5621	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5622	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5623	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
AnnaBridge	171:3a7713b1edbc	5624
AnnaBridge	171:3a7713b1edbc	5625	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
AnnaBridge	171:3a7713b1edbc	5626	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5627	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	5628	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5629	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5630	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
AnnaBridge	171:3a7713b1edbc	5631
AnnaBridge	171:3a7713b1edbc	5632	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
AnnaBridge	171:3a7713b1edbc	5633	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5634	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	5635	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5636	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5637	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
AnnaBridge	171:3a7713b1edbc	5638
AnnaBridge	171:3a7713b1edbc	5639	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
AnnaBridge	171:3a7713b1edbc	5640	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5641	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
AnnaBridge	171:3a7713b1edbc	5642	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5643	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5644	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
AnnaBridge	171:3a7713b1edbc	5645
AnnaBridge	171:3a7713b1edbc	5646	/* Bit 0 : Disable routing to PPI of TICK event. */
AnnaBridge	171:3a7713b1edbc	5647	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
AnnaBridge	171:3a7713b1edbc	5648	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
AnnaBridge	171:3a7713b1edbc	5649	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
AnnaBridge	171:3a7713b1edbc	5650	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
AnnaBridge	171:3a7713b1edbc	5651	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
AnnaBridge	171:3a7713b1edbc	5652
AnnaBridge	171:3a7713b1edbc	5653	/* Register: RTC_COUNTER */
AnnaBridge	171:3a7713b1edbc	5654	/* Description: Current COUNTER value. */
AnnaBridge	171:3a7713b1edbc	5655
AnnaBridge	171:3a7713b1edbc	5656	/* Bits 23..0 : Counter value. */
AnnaBridge	171:3a7713b1edbc	5657	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
AnnaBridge	171:3a7713b1edbc	5658	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
AnnaBridge	171:3a7713b1edbc	5659
AnnaBridge	171:3a7713b1edbc	5660	/* Register: RTC_PRESCALER */
AnnaBridge	171:3a7713b1edbc	5661	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
AnnaBridge	171:3a7713b1edbc	5662
AnnaBridge	171:3a7713b1edbc	5663	/* Bits 11..0 : RTC PRESCALER value. */
AnnaBridge	171:3a7713b1edbc	5664	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
AnnaBridge	171:3a7713b1edbc	5665	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
AnnaBridge	171:3a7713b1edbc	5666
AnnaBridge	171:3a7713b1edbc	5667	/* Register: RTC_CC */
AnnaBridge	171:3a7713b1edbc	5668	/* Description: Capture/compare registers. */
AnnaBridge	171:3a7713b1edbc	5669
AnnaBridge	171:3a7713b1edbc	5670	/* Bits 23..0 : Compare value. */
AnnaBridge	171:3a7713b1edbc	5671	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
AnnaBridge	171:3a7713b1edbc	5672	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
AnnaBridge	171:3a7713b1edbc	5673
AnnaBridge	171:3a7713b1edbc	5674	/* Register: RTC_POWER */
AnnaBridge	171:3a7713b1edbc	5675	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5676
AnnaBridge	171:3a7713b1edbc	5677	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5678	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	5679	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	5680	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	5681	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	5682
AnnaBridge	171:3a7713b1edbc	5683
AnnaBridge	171:3a7713b1edbc	5684	/* Peripheral: SPI */
AnnaBridge	171:3a7713b1edbc	5685	/* Description: SPI master 0. */
AnnaBridge	171:3a7713b1edbc	5686
AnnaBridge	171:3a7713b1edbc	5687	/* Register: SPI_INTENSET */
AnnaBridge	171:3a7713b1edbc	5688	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	5689
AnnaBridge	171:3a7713b1edbc	5690	/* Bit 2 : Enable interrupt on READY event. */
AnnaBridge	171:3a7713b1edbc	5691	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
AnnaBridge	171:3a7713b1edbc	5692	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
AnnaBridge	171:3a7713b1edbc	5693	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5694	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5695	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5696
AnnaBridge	171:3a7713b1edbc	5697	/* Register: SPI_INTENCLR */
AnnaBridge	171:3a7713b1edbc	5698	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	5699
AnnaBridge	171:3a7713b1edbc	5700	/* Bit 2 : Disable interrupt on READY event. */
AnnaBridge	171:3a7713b1edbc	5701	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
AnnaBridge	171:3a7713b1edbc	5702	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
AnnaBridge	171:3a7713b1edbc	5703	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5704	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5705	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5706
AnnaBridge	171:3a7713b1edbc	5707	/* Register: SPI_ENABLE */
AnnaBridge	171:3a7713b1edbc	5708	/* Description: Enable SPI. */
AnnaBridge	171:3a7713b1edbc	5709
AnnaBridge	171:3a7713b1edbc	5710	/* Bits 2..0 : Enable or disable SPI. */
AnnaBridge	171:3a7713b1edbc	5711	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	5712	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	5713	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
AnnaBridge	171:3a7713b1edbc	5714	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
AnnaBridge	171:3a7713b1edbc	5715
AnnaBridge	171:3a7713b1edbc	5716	/* Register: SPI_RXD */
AnnaBridge	171:3a7713b1edbc	5717	/* Description: RX data. */
AnnaBridge	171:3a7713b1edbc	5718
AnnaBridge	171:3a7713b1edbc	5719	/* Bits 7..0 : RX data from last transfer. */
AnnaBridge	171:3a7713b1edbc	5720	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
AnnaBridge	171:3a7713b1edbc	5721	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
AnnaBridge	171:3a7713b1edbc	5722
AnnaBridge	171:3a7713b1edbc	5723	/* Register: SPI_TXD */
AnnaBridge	171:3a7713b1edbc	5724	/* Description: TX data. */
AnnaBridge	171:3a7713b1edbc	5725
AnnaBridge	171:3a7713b1edbc	5726	/* Bits 7..0 : TX data for next transfer. */
AnnaBridge	171:3a7713b1edbc	5727	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
AnnaBridge	171:3a7713b1edbc	5728	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
AnnaBridge	171:3a7713b1edbc	5729
AnnaBridge	171:3a7713b1edbc	5730	/* Register: SPI_FREQUENCY */
AnnaBridge	171:3a7713b1edbc	5731	/* Description: SPI frequency */
AnnaBridge	171:3a7713b1edbc	5732
AnnaBridge	171:3a7713b1edbc	5733	/* Bits 31..0 : SPI data rate. */
AnnaBridge	171:3a7713b1edbc	5734	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	5735	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	5736	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
AnnaBridge	171:3a7713b1edbc	5737	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
AnnaBridge	171:3a7713b1edbc	5738	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
AnnaBridge	171:3a7713b1edbc	5739	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
AnnaBridge	171:3a7713b1edbc	5740	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
AnnaBridge	171:3a7713b1edbc	5741	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
AnnaBridge	171:3a7713b1edbc	5742	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
AnnaBridge	171:3a7713b1edbc	5743
AnnaBridge	171:3a7713b1edbc	5744	/* Register: SPI_CONFIG */
AnnaBridge	171:3a7713b1edbc	5745	/* Description: Configuration register. */
AnnaBridge	171:3a7713b1edbc	5746
AnnaBridge	171:3a7713b1edbc	5747	/* Bit 2 : Serial clock (SCK) polarity. */
AnnaBridge	171:3a7713b1edbc	5748	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
AnnaBridge	171:3a7713b1edbc	5749	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
AnnaBridge	171:3a7713b1edbc	5750	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
AnnaBridge	171:3a7713b1edbc	5751	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
AnnaBridge	171:3a7713b1edbc	5752
AnnaBridge	171:3a7713b1edbc	5753	/* Bit 1 : Serial clock (SCK) phase. */
AnnaBridge	171:3a7713b1edbc	5754	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
AnnaBridge	171:3a7713b1edbc	5755	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
AnnaBridge	171:3a7713b1edbc	5756	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
AnnaBridge	171:3a7713b1edbc	5757	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
AnnaBridge	171:3a7713b1edbc	5758
AnnaBridge	171:3a7713b1edbc	5759	/* Bit 0 : Bit order. */
AnnaBridge	171:3a7713b1edbc	5760	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
AnnaBridge	171:3a7713b1edbc	5761	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
AnnaBridge	171:3a7713b1edbc	5762	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
AnnaBridge	171:3a7713b1edbc	5763	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
AnnaBridge	171:3a7713b1edbc	5764
AnnaBridge	171:3a7713b1edbc	5765	/* Register: SPI_POWER */
AnnaBridge	171:3a7713b1edbc	5766	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5767
AnnaBridge	171:3a7713b1edbc	5768	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5769	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	5770	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	5771	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	5772	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	5773
AnnaBridge	171:3a7713b1edbc	5774
AnnaBridge	171:3a7713b1edbc	5775	/* Peripheral: SPIM */
AnnaBridge	171:3a7713b1edbc	5776	/* Description: SPI master with easyDMA 1. */
AnnaBridge	171:3a7713b1edbc	5777
AnnaBridge	171:3a7713b1edbc	5778	/* Register: SPIM_INTENSET */
AnnaBridge	171:3a7713b1edbc	5779	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	5780
AnnaBridge	171:3a7713b1edbc	5781	/* Bit 19 : Enable interrupt on STARTED event. */
AnnaBridge	171:3a7713b1edbc	5782	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
AnnaBridge	171:3a7713b1edbc	5783	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
AnnaBridge	171:3a7713b1edbc	5784	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5785	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5786	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5787
AnnaBridge	171:3a7713b1edbc	5788	/* Bit 8 : Enable interrupt on ENDTX event. */
AnnaBridge	171:3a7713b1edbc	5789	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
AnnaBridge	171:3a7713b1edbc	5790	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
AnnaBridge	171:3a7713b1edbc	5791	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5792	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5793	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5794
AnnaBridge	171:3a7713b1edbc	5795	/* Bit 4 : Enable interrupt on ENDRX event. */
AnnaBridge	171:3a7713b1edbc	5796	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5797	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5798	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5799	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5800	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5801
AnnaBridge	171:3a7713b1edbc	5802	/* Bit 1 : Enable interrupt on STOPPED event. */
AnnaBridge	171:3a7713b1edbc	5803	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	5804	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	5805	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5806	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5807	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5808
AnnaBridge	171:3a7713b1edbc	5809	/* Register: SPIM_INTENCLR */
AnnaBridge	171:3a7713b1edbc	5810	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	5811
AnnaBridge	171:3a7713b1edbc	5812	/* Bit 19 : Disable interrupt on STARTED event. */
AnnaBridge	171:3a7713b1edbc	5813	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
AnnaBridge	171:3a7713b1edbc	5814	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
AnnaBridge	171:3a7713b1edbc	5815	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5816	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5817	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5818
AnnaBridge	171:3a7713b1edbc	5819	/* Bit 8 : Disable interrupt on ENDTX event. */
AnnaBridge	171:3a7713b1edbc	5820	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
AnnaBridge	171:3a7713b1edbc	5821	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
AnnaBridge	171:3a7713b1edbc	5822	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5823	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5824	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5825
AnnaBridge	171:3a7713b1edbc	5826	/* Bit 4 : Disable interrupt on ENDRX event. */
AnnaBridge	171:3a7713b1edbc	5827	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5828	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5829	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5830	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5831	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5832
AnnaBridge	171:3a7713b1edbc	5833	/* Bit 1 : Disable interrupt on STOPPED event. */
AnnaBridge	171:3a7713b1edbc	5834	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	5835	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	5836	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5837	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5838	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5839
AnnaBridge	171:3a7713b1edbc	5840	/* Register: SPIM_ENABLE */
AnnaBridge	171:3a7713b1edbc	5841	/* Description: Enable SPIM. */
AnnaBridge	171:3a7713b1edbc	5842
AnnaBridge	171:3a7713b1edbc	5843	/* Bits 3..0 : Enable or disable SPIM. */
AnnaBridge	171:3a7713b1edbc	5844	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	5845	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	5846	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
AnnaBridge	171:3a7713b1edbc	5847	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
AnnaBridge	171:3a7713b1edbc	5848
AnnaBridge	171:3a7713b1edbc	5849	/* Register: SPIM_FREQUENCY */
AnnaBridge	171:3a7713b1edbc	5850	/* Description: SPI frequency. */
AnnaBridge	171:3a7713b1edbc	5851
AnnaBridge	171:3a7713b1edbc	5852	/* Bits 31..0 : SPI master data rate. */
AnnaBridge	171:3a7713b1edbc	5853	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	5854	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	5855	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
AnnaBridge	171:3a7713b1edbc	5856	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
AnnaBridge	171:3a7713b1edbc	5857	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
AnnaBridge	171:3a7713b1edbc	5858	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
AnnaBridge	171:3a7713b1edbc	5859	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
AnnaBridge	171:3a7713b1edbc	5860	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
AnnaBridge	171:3a7713b1edbc	5861	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
AnnaBridge	171:3a7713b1edbc	5862
AnnaBridge	171:3a7713b1edbc	5863	/* Register: SPIM_RXD_PTR */
AnnaBridge	171:3a7713b1edbc	5864	/* Description: Data pointer. */
AnnaBridge	171:3a7713b1edbc	5865
AnnaBridge	171:3a7713b1edbc	5866	/* Bits 31..0 : Data pointer. */
AnnaBridge	171:3a7713b1edbc	5867	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
AnnaBridge	171:3a7713b1edbc	5868	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
AnnaBridge	171:3a7713b1edbc	5869
AnnaBridge	171:3a7713b1edbc	5870	/* Register: SPIM_RXD_MAXCNT */
AnnaBridge	171:3a7713b1edbc	5871	/* Description: Maximum number of buffer bytes to receive. */
AnnaBridge	171:3a7713b1edbc	5872
AnnaBridge	171:3a7713b1edbc	5873	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
AnnaBridge	171:3a7713b1edbc	5874	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
AnnaBridge	171:3a7713b1edbc	5875	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
AnnaBridge	171:3a7713b1edbc	5876
AnnaBridge	171:3a7713b1edbc	5877	/* Register: SPIM_RXD_AMOUNT */
AnnaBridge	171:3a7713b1edbc	5878	/* Description: Number of bytes received in the last transaction. */
AnnaBridge	171:3a7713b1edbc	5879
AnnaBridge	171:3a7713b1edbc	5880	/* Bits 7..0 : Number of bytes received in the last transaction. */
AnnaBridge	171:3a7713b1edbc	5881	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
AnnaBridge	171:3a7713b1edbc	5882	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
AnnaBridge	171:3a7713b1edbc	5883
AnnaBridge	171:3a7713b1edbc	5884	/* Register: SPIM_TXD_PTR */
AnnaBridge	171:3a7713b1edbc	5885	/* Description: Data pointer. */
AnnaBridge	171:3a7713b1edbc	5886
AnnaBridge	171:3a7713b1edbc	5887	/* Bits 31..0 : Data pointer. */
AnnaBridge	171:3a7713b1edbc	5888	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
AnnaBridge	171:3a7713b1edbc	5889	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
AnnaBridge	171:3a7713b1edbc	5890
AnnaBridge	171:3a7713b1edbc	5891	/* Register: SPIM_TXD_MAXCNT */
AnnaBridge	171:3a7713b1edbc	5892	/* Description: Maximum number of buffer bytes to send. */
AnnaBridge	171:3a7713b1edbc	5893
AnnaBridge	171:3a7713b1edbc	5894	/* Bits 7..0 : Maximum number of buffer bytes to send. */
AnnaBridge	171:3a7713b1edbc	5895	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
AnnaBridge	171:3a7713b1edbc	5896	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
AnnaBridge	171:3a7713b1edbc	5897
AnnaBridge	171:3a7713b1edbc	5898	/* Register: SPIM_TXD_AMOUNT */
AnnaBridge	171:3a7713b1edbc	5899	/* Description: Number of bytes sent in the last transaction. */
AnnaBridge	171:3a7713b1edbc	5900
AnnaBridge	171:3a7713b1edbc	5901	/* Bits 7..0 : Number of bytes sent in the last transaction. */
AnnaBridge	171:3a7713b1edbc	5902	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
AnnaBridge	171:3a7713b1edbc	5903	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
AnnaBridge	171:3a7713b1edbc	5904
AnnaBridge	171:3a7713b1edbc	5905	/* Register: SPIM_CONFIG */
AnnaBridge	171:3a7713b1edbc	5906	/* Description: Configuration register. */
AnnaBridge	171:3a7713b1edbc	5907
AnnaBridge	171:3a7713b1edbc	5908	/* Bit 2 : Serial clock (SCK) polarity. */
AnnaBridge	171:3a7713b1edbc	5909	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
AnnaBridge	171:3a7713b1edbc	5910	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
AnnaBridge	171:3a7713b1edbc	5911	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
AnnaBridge	171:3a7713b1edbc	5912	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
AnnaBridge	171:3a7713b1edbc	5913
AnnaBridge	171:3a7713b1edbc	5914	/* Bit 1 : Serial clock (SCK) phase. */
AnnaBridge	171:3a7713b1edbc	5915	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
AnnaBridge	171:3a7713b1edbc	5916	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
AnnaBridge	171:3a7713b1edbc	5917	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
AnnaBridge	171:3a7713b1edbc	5918	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
AnnaBridge	171:3a7713b1edbc	5919
AnnaBridge	171:3a7713b1edbc	5920	/* Bit 0 : Bit order. */
AnnaBridge	171:3a7713b1edbc	5921	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
AnnaBridge	171:3a7713b1edbc	5922	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
AnnaBridge	171:3a7713b1edbc	5923	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
AnnaBridge	171:3a7713b1edbc	5924	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
AnnaBridge	171:3a7713b1edbc	5925
AnnaBridge	171:3a7713b1edbc	5926	/* Register: SPIM_ORC */
AnnaBridge	171:3a7713b1edbc	5927	/* Description: Over-read character. */
AnnaBridge	171:3a7713b1edbc	5928
AnnaBridge	171:3a7713b1edbc	5929	/* Bits 7..0 : Over-read character. */
AnnaBridge	171:3a7713b1edbc	5930	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
AnnaBridge	171:3a7713b1edbc	5931	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
AnnaBridge	171:3a7713b1edbc	5932
AnnaBridge	171:3a7713b1edbc	5933	/* Register: SPIM_POWER */
AnnaBridge	171:3a7713b1edbc	5934	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5935
AnnaBridge	171:3a7713b1edbc	5936	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	5937	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	5938	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	5939	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	5940	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	5941
AnnaBridge	171:3a7713b1edbc	5942
AnnaBridge	171:3a7713b1edbc	5943	/* Peripheral: SPIS */
AnnaBridge	171:3a7713b1edbc	5944	/* Description: SPI slave 1. */
AnnaBridge	171:3a7713b1edbc	5945
AnnaBridge	171:3a7713b1edbc	5946	/* Register: SPIS_SHORTS */
AnnaBridge	171:3a7713b1edbc	5947	/* Description: Shortcuts for SPIS. */
AnnaBridge	171:3a7713b1edbc	5948
AnnaBridge	171:3a7713b1edbc	5949	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
AnnaBridge	171:3a7713b1edbc	5950	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
AnnaBridge	171:3a7713b1edbc	5951	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
AnnaBridge	171:3a7713b1edbc	5952	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	5953	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	5954
AnnaBridge	171:3a7713b1edbc	5955	/* Register: SPIS_INTENSET */
AnnaBridge	171:3a7713b1edbc	5956	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	5957
AnnaBridge	171:3a7713b1edbc	5958	/* Bit 10 : Enable interrupt on ACQUIRED event. */
AnnaBridge	171:3a7713b1edbc	5959	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
AnnaBridge	171:3a7713b1edbc	5960	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
AnnaBridge	171:3a7713b1edbc	5961	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5962	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5963	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5964
AnnaBridge	171:3a7713b1edbc	5965	/* Bit 4 : enable interrupt on ENDRX event. */
AnnaBridge	171:3a7713b1edbc	5966	#define SPIS_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5967	#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5968	#define SPIS_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5969	#define SPIS_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5970	#define SPIS_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5971
AnnaBridge	171:3a7713b1edbc	5972	/* Bit 1 : Enable interrupt on END event. */
AnnaBridge	171:3a7713b1edbc	5973	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	5974	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	5975	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5976	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5977	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5978
AnnaBridge	171:3a7713b1edbc	5979	/* Register: SPIS_INTENCLR */
AnnaBridge	171:3a7713b1edbc	5980	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	5981
AnnaBridge	171:3a7713b1edbc	5982	/* Bit 10 : Disable interrupt on ACQUIRED event. */
AnnaBridge	171:3a7713b1edbc	5983	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
AnnaBridge	171:3a7713b1edbc	5984	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
AnnaBridge	171:3a7713b1edbc	5985	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5986	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5987	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5988
AnnaBridge	171:3a7713b1edbc	5989	/* Bit 4 : Disable interrupt on ENDRX event. */
AnnaBridge	171:3a7713b1edbc	5990	#define SPIS_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5991	#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
AnnaBridge	171:3a7713b1edbc	5992	#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	5993	#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	5994	#define SPIS_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	5995
AnnaBridge	171:3a7713b1edbc	5996	/* Bit 1 : Disable interrupt on END event. */
AnnaBridge	171:3a7713b1edbc	5997	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
AnnaBridge	171:3a7713b1edbc	5998	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
AnnaBridge	171:3a7713b1edbc	5999	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6000	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6001	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6002
AnnaBridge	171:3a7713b1edbc	6003	/* Register: SPIS_SEMSTAT */
AnnaBridge	171:3a7713b1edbc	6004	/* Description: Semaphore status. */
AnnaBridge	171:3a7713b1edbc	6005
AnnaBridge	171:3a7713b1edbc	6006	/* Bits 1..0 : Semaphore status. */
AnnaBridge	171:3a7713b1edbc	6007	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
AnnaBridge	171:3a7713b1edbc	6008	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
AnnaBridge	171:3a7713b1edbc	6009	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
AnnaBridge	171:3a7713b1edbc	6010	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
AnnaBridge	171:3a7713b1edbc	6011	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
AnnaBridge	171:3a7713b1edbc	6012	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
AnnaBridge	171:3a7713b1edbc	6013
AnnaBridge	171:3a7713b1edbc	6014	/* Register: SPIS_STATUS */
AnnaBridge	171:3a7713b1edbc	6015	/* Description: Status from last transaction. */
AnnaBridge	171:3a7713b1edbc	6016
AnnaBridge	171:3a7713b1edbc	6017	/* Bit 1 : RX buffer overflow detected, and prevented. */
AnnaBridge	171:3a7713b1edbc	6018	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
AnnaBridge	171:3a7713b1edbc	6019	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
AnnaBridge	171:3a7713b1edbc	6020	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6021	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6022	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
AnnaBridge	171:3a7713b1edbc	6023
AnnaBridge	171:3a7713b1edbc	6024	/* Bit 0 : TX buffer overread detected, and prevented. */
AnnaBridge	171:3a7713b1edbc	6025	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
AnnaBridge	171:3a7713b1edbc	6026	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
AnnaBridge	171:3a7713b1edbc	6027	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6028	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6029	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
AnnaBridge	171:3a7713b1edbc	6030
AnnaBridge	171:3a7713b1edbc	6031	/* Register: SPIS_ENABLE */
AnnaBridge	171:3a7713b1edbc	6032	/* Description: Enable SPIS. */
AnnaBridge	171:3a7713b1edbc	6033
AnnaBridge	171:3a7713b1edbc	6034	/* Bits 2..0 : Enable or disable SPIS. */
AnnaBridge	171:3a7713b1edbc	6035	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	6036	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	6037	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
AnnaBridge	171:3a7713b1edbc	6038	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
AnnaBridge	171:3a7713b1edbc	6039
AnnaBridge	171:3a7713b1edbc	6040	/* Register: SPIS_MAXRX */
AnnaBridge	171:3a7713b1edbc	6041	/* Description: Maximum number of bytes in the receive buffer. */
AnnaBridge	171:3a7713b1edbc	6042
AnnaBridge	171:3a7713b1edbc	6043	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
AnnaBridge	171:3a7713b1edbc	6044	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
AnnaBridge	171:3a7713b1edbc	6045	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
AnnaBridge	171:3a7713b1edbc	6046
AnnaBridge	171:3a7713b1edbc	6047	/* Register: SPIS_AMOUNTRX */
AnnaBridge	171:3a7713b1edbc	6048	/* Description: Number of bytes received in last granted transaction. */
AnnaBridge	171:3a7713b1edbc	6049
AnnaBridge	171:3a7713b1edbc	6050	/* Bits 7..0 : Number of bytes received in last granted transaction. */
AnnaBridge	171:3a7713b1edbc	6051	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
AnnaBridge	171:3a7713b1edbc	6052	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
AnnaBridge	171:3a7713b1edbc	6053
AnnaBridge	171:3a7713b1edbc	6054	/* Register: SPIS_MAXTX */
AnnaBridge	171:3a7713b1edbc	6055	/* Description: Maximum number of bytes in the transmit buffer. */
AnnaBridge	171:3a7713b1edbc	6056
AnnaBridge	171:3a7713b1edbc	6057	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
AnnaBridge	171:3a7713b1edbc	6058	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
AnnaBridge	171:3a7713b1edbc	6059	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
AnnaBridge	171:3a7713b1edbc	6060
AnnaBridge	171:3a7713b1edbc	6061	/* Register: SPIS_AMOUNTTX */
AnnaBridge	171:3a7713b1edbc	6062	/* Description: Number of bytes transmitted in last granted transaction. */
AnnaBridge	171:3a7713b1edbc	6063
AnnaBridge	171:3a7713b1edbc	6064	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
AnnaBridge	171:3a7713b1edbc	6065	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
AnnaBridge	171:3a7713b1edbc	6066	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
AnnaBridge	171:3a7713b1edbc	6067
AnnaBridge	171:3a7713b1edbc	6068	/* Register: SPIS_CONFIG */
AnnaBridge	171:3a7713b1edbc	6069	/* Description: Configuration register. */
AnnaBridge	171:3a7713b1edbc	6070
AnnaBridge	171:3a7713b1edbc	6071	/* Bit 2 : Serial clock (SCK) polarity. */
AnnaBridge	171:3a7713b1edbc	6072	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
AnnaBridge	171:3a7713b1edbc	6073	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
AnnaBridge	171:3a7713b1edbc	6074	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
AnnaBridge	171:3a7713b1edbc	6075	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
AnnaBridge	171:3a7713b1edbc	6076
AnnaBridge	171:3a7713b1edbc	6077	/* Bit 1 : Serial clock (SCK) phase. */
AnnaBridge	171:3a7713b1edbc	6078	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
AnnaBridge	171:3a7713b1edbc	6079	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
AnnaBridge	171:3a7713b1edbc	6080	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
AnnaBridge	171:3a7713b1edbc	6081	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
AnnaBridge	171:3a7713b1edbc	6082
AnnaBridge	171:3a7713b1edbc	6083	/* Bit 0 : Bit order. */
AnnaBridge	171:3a7713b1edbc	6084	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
AnnaBridge	171:3a7713b1edbc	6085	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
AnnaBridge	171:3a7713b1edbc	6086	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
AnnaBridge	171:3a7713b1edbc	6087	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
AnnaBridge	171:3a7713b1edbc	6088
AnnaBridge	171:3a7713b1edbc	6089	/* Register: SPIS_DEF */
AnnaBridge	171:3a7713b1edbc	6090	/* Description: Default character. */
AnnaBridge	171:3a7713b1edbc	6091
AnnaBridge	171:3a7713b1edbc	6092	/* Bits 7..0 : Default character. */
AnnaBridge	171:3a7713b1edbc	6093	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
AnnaBridge	171:3a7713b1edbc	6094	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
AnnaBridge	171:3a7713b1edbc	6095
AnnaBridge	171:3a7713b1edbc	6096	/* Register: SPIS_ORC */
AnnaBridge	171:3a7713b1edbc	6097	/* Description: Over-read character. */
AnnaBridge	171:3a7713b1edbc	6098
AnnaBridge	171:3a7713b1edbc	6099	/* Bits 7..0 : Over-read character. */
AnnaBridge	171:3a7713b1edbc	6100	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
AnnaBridge	171:3a7713b1edbc	6101	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
AnnaBridge	171:3a7713b1edbc	6102
AnnaBridge	171:3a7713b1edbc	6103	/* Register: SPIS_POWER */
AnnaBridge	171:3a7713b1edbc	6104	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6105
AnnaBridge	171:3a7713b1edbc	6106	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6107	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	6108	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	6109	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	6110	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	6111
AnnaBridge	171:3a7713b1edbc	6112
AnnaBridge	171:3a7713b1edbc	6113	/* Peripheral: TEMP */
AnnaBridge	171:3a7713b1edbc	6114	/* Description: Temperature Sensor. */
AnnaBridge	171:3a7713b1edbc	6115
AnnaBridge	171:3a7713b1edbc	6116	/* Register: TEMP_INTENSET */
AnnaBridge	171:3a7713b1edbc	6117	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	6118
AnnaBridge	171:3a7713b1edbc	6119	/* Bit 0 : Enable interrupt on DATARDY event. */
AnnaBridge	171:3a7713b1edbc	6120	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
AnnaBridge	171:3a7713b1edbc	6121	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
AnnaBridge	171:3a7713b1edbc	6122	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6123	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6124	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6125
AnnaBridge	171:3a7713b1edbc	6126	/* Register: TEMP_INTENCLR */
AnnaBridge	171:3a7713b1edbc	6127	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	6128
AnnaBridge	171:3a7713b1edbc	6129	/* Bit 0 : Disable interrupt on DATARDY event. */
AnnaBridge	171:3a7713b1edbc	6130	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
AnnaBridge	171:3a7713b1edbc	6131	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
AnnaBridge	171:3a7713b1edbc	6132	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6133	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6134	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6135
AnnaBridge	171:3a7713b1edbc	6136	/* Register: TEMP_POWER */
AnnaBridge	171:3a7713b1edbc	6137	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6138
AnnaBridge	171:3a7713b1edbc	6139	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6140	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	6141	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	6142	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	6143	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	6144
AnnaBridge	171:3a7713b1edbc	6145
AnnaBridge	171:3a7713b1edbc	6146	/* Peripheral: TIMER */
AnnaBridge	171:3a7713b1edbc	6147	/* Description: Timer 0. */
AnnaBridge	171:3a7713b1edbc	6148
AnnaBridge	171:3a7713b1edbc	6149	/* Register: TIMER_SHORTS */
AnnaBridge	171:3a7713b1edbc	6150	/* Description: Shortcuts for Timer. */
AnnaBridge	171:3a7713b1edbc	6151
AnnaBridge	171:3a7713b1edbc	6152	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
AnnaBridge	171:3a7713b1edbc	6153	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
AnnaBridge	171:3a7713b1edbc	6154	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
AnnaBridge	171:3a7713b1edbc	6155	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6156	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6157
AnnaBridge	171:3a7713b1edbc	6158	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
AnnaBridge	171:3a7713b1edbc	6159	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
AnnaBridge	171:3a7713b1edbc	6160	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
AnnaBridge	171:3a7713b1edbc	6161	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6162	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6163
AnnaBridge	171:3a7713b1edbc	6164	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
AnnaBridge	171:3a7713b1edbc	6165	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
AnnaBridge	171:3a7713b1edbc	6166	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
AnnaBridge	171:3a7713b1edbc	6167	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6168	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6169
AnnaBridge	171:3a7713b1edbc	6170	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
AnnaBridge	171:3a7713b1edbc	6171	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
AnnaBridge	171:3a7713b1edbc	6172	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
AnnaBridge	171:3a7713b1edbc	6173	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6174	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6175
AnnaBridge	171:3a7713b1edbc	6176	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
AnnaBridge	171:3a7713b1edbc	6177	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6178	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6179	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6180	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6181
AnnaBridge	171:3a7713b1edbc	6182	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
AnnaBridge	171:3a7713b1edbc	6183	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6184	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6185	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6186	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6187
AnnaBridge	171:3a7713b1edbc	6188	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
AnnaBridge	171:3a7713b1edbc	6189	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6190	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6191	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6192	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6193
AnnaBridge	171:3a7713b1edbc	6194	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
AnnaBridge	171:3a7713b1edbc	6195	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6196	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
AnnaBridge	171:3a7713b1edbc	6197	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6198	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6199
AnnaBridge	171:3a7713b1edbc	6200	/* Register: TIMER_INTENSET */
AnnaBridge	171:3a7713b1edbc	6201	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	6202
AnnaBridge	171:3a7713b1edbc	6203	/* Bit 19 : Enable interrupt on COMPARE[3] */
AnnaBridge	171:3a7713b1edbc	6204	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	6205	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	6206	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6207	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6208	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6209
AnnaBridge	171:3a7713b1edbc	6210	/* Bit 18 : Enable interrupt on COMPARE[2] */
AnnaBridge	171:3a7713b1edbc	6211	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	6212	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	6213	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6214	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6215	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6216
AnnaBridge	171:3a7713b1edbc	6217	/* Bit 17 : Enable interrupt on COMPARE[1] */
AnnaBridge	171:3a7713b1edbc	6218	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	6219	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	6220	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6221	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6222	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6223
AnnaBridge	171:3a7713b1edbc	6224	/* Bit 16 : Enable interrupt on COMPARE[0] */
AnnaBridge	171:3a7713b1edbc	6225	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	6226	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	6227	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6228	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6229	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6230
AnnaBridge	171:3a7713b1edbc	6231	/* Register: TIMER_INTENCLR */
AnnaBridge	171:3a7713b1edbc	6232	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	6233
AnnaBridge	171:3a7713b1edbc	6234	/* Bit 19 : Disable interrupt on COMPARE[3] */
AnnaBridge	171:3a7713b1edbc	6235	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	6236	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
AnnaBridge	171:3a7713b1edbc	6237	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6238	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6239	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6240
AnnaBridge	171:3a7713b1edbc	6241	/* Bit 18 : Disable interrupt on COMPARE[2] */
AnnaBridge	171:3a7713b1edbc	6242	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	6243	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
AnnaBridge	171:3a7713b1edbc	6244	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6245	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6246	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6247
AnnaBridge	171:3a7713b1edbc	6248	/* Bit 17 : Disable interrupt on COMPARE[1] */
AnnaBridge	171:3a7713b1edbc	6249	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	6250	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
AnnaBridge	171:3a7713b1edbc	6251	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6252	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6253	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6254
AnnaBridge	171:3a7713b1edbc	6255	/* Bit 16 : Disable interrupt on COMPARE[0] */
AnnaBridge	171:3a7713b1edbc	6256	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	6257	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
AnnaBridge	171:3a7713b1edbc	6258	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6259	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6260	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6261
AnnaBridge	171:3a7713b1edbc	6262	/* Register: TIMER_MODE */
AnnaBridge	171:3a7713b1edbc	6263	/* Description: Timer Mode selection. */
AnnaBridge	171:3a7713b1edbc	6264
AnnaBridge	171:3a7713b1edbc	6265	/* Bit 0 : Select Normal or Counter mode. */
AnnaBridge	171:3a7713b1edbc	6266	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
AnnaBridge	171:3a7713b1edbc	6267	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
AnnaBridge	171:3a7713b1edbc	6268	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
AnnaBridge	171:3a7713b1edbc	6269	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
AnnaBridge	171:3a7713b1edbc	6270
AnnaBridge	171:3a7713b1edbc	6271	/* Register: TIMER_BITMODE */
AnnaBridge	171:3a7713b1edbc	6272	/* Description: Sets timer behaviour. */
AnnaBridge	171:3a7713b1edbc	6273
AnnaBridge	171:3a7713b1edbc	6274	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
AnnaBridge	171:3a7713b1edbc	6275	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
AnnaBridge	171:3a7713b1edbc	6276	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
AnnaBridge	171:3a7713b1edbc	6277	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
AnnaBridge	171:3a7713b1edbc	6278	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
AnnaBridge	171:3a7713b1edbc	6279	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
AnnaBridge	171:3a7713b1edbc	6280	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
AnnaBridge	171:3a7713b1edbc	6281
AnnaBridge	171:3a7713b1edbc	6282	/* Register: TIMER_PRESCALER */
AnnaBridge	171:3a7713b1edbc	6283	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
AnnaBridge	171:3a7713b1edbc	6284
AnnaBridge	171:3a7713b1edbc	6285	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
AnnaBridge	171:3a7713b1edbc	6286	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
AnnaBridge	171:3a7713b1edbc	6287	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
AnnaBridge	171:3a7713b1edbc	6288
AnnaBridge	171:3a7713b1edbc	6289	/* Register: TIMER_POWER */
AnnaBridge	171:3a7713b1edbc	6290	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6291
AnnaBridge	171:3a7713b1edbc	6292	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6293	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	6294	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	6295	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	6296	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	6297
AnnaBridge	171:3a7713b1edbc	6298
AnnaBridge	171:3a7713b1edbc	6299	/* Peripheral: TWI */
AnnaBridge	171:3a7713b1edbc	6300	/* Description: Two-wire interface master 0. */
AnnaBridge	171:3a7713b1edbc	6301
AnnaBridge	171:3a7713b1edbc	6302	/* Register: TWI_SHORTS */
AnnaBridge	171:3a7713b1edbc	6303	/* Description: Shortcuts for TWI. */
AnnaBridge	171:3a7713b1edbc	6304
AnnaBridge	171:3a7713b1edbc	6305	/* Bit 1 : Shortcut between BB event and the STOP task. */
AnnaBridge	171:3a7713b1edbc	6306	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
AnnaBridge	171:3a7713b1edbc	6307	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
AnnaBridge	171:3a7713b1edbc	6308	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6309	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6310
AnnaBridge	171:3a7713b1edbc	6311	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
AnnaBridge	171:3a7713b1edbc	6312	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
AnnaBridge	171:3a7713b1edbc	6313	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
AnnaBridge	171:3a7713b1edbc	6314	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6315	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6316
AnnaBridge	171:3a7713b1edbc	6317	/* Register: TWI_INTENSET */
AnnaBridge	171:3a7713b1edbc	6318	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	6319
AnnaBridge	171:3a7713b1edbc	6320	/* Bit 18 : Enable interrupt on SUSPENDED event. */
AnnaBridge	171:3a7713b1edbc	6321	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
AnnaBridge	171:3a7713b1edbc	6322	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
AnnaBridge	171:3a7713b1edbc	6323	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6324	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6325	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6326
AnnaBridge	171:3a7713b1edbc	6327	/* Bit 14 : Enable interrupt on BB event. */
AnnaBridge	171:3a7713b1edbc	6328	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
AnnaBridge	171:3a7713b1edbc	6329	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
AnnaBridge	171:3a7713b1edbc	6330	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6331	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6332	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6333
AnnaBridge	171:3a7713b1edbc	6334	/* Bit 9 : Enable interrupt on ERROR event. */
AnnaBridge	171:3a7713b1edbc	6335	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6336	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6337	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6338	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6339	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6340
AnnaBridge	171:3a7713b1edbc	6341	/* Bit 7 : Enable interrupt on TXDSENT event. */
AnnaBridge	171:3a7713b1edbc	6342	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
AnnaBridge	171:3a7713b1edbc	6343	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
AnnaBridge	171:3a7713b1edbc	6344	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6345	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6346	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6347
AnnaBridge	171:3a7713b1edbc	6348	/* Bit 2 : Enable interrupt on READY event. */
AnnaBridge	171:3a7713b1edbc	6349	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
AnnaBridge	171:3a7713b1edbc	6350	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
AnnaBridge	171:3a7713b1edbc	6351	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6352	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6353	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6354
AnnaBridge	171:3a7713b1edbc	6355	/* Bit 1 : Enable interrupt on STOPPED event. */
AnnaBridge	171:3a7713b1edbc	6356	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	6357	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	6358	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6359	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6360	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6361
AnnaBridge	171:3a7713b1edbc	6362	/* Register: TWI_INTENCLR */
AnnaBridge	171:3a7713b1edbc	6363	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	6364
AnnaBridge	171:3a7713b1edbc	6365	/* Bit 18 : Disable interrupt on SUSPENDED event. */
AnnaBridge	171:3a7713b1edbc	6366	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
AnnaBridge	171:3a7713b1edbc	6367	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
AnnaBridge	171:3a7713b1edbc	6368	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6369	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6370	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6371
AnnaBridge	171:3a7713b1edbc	6372	/* Bit 14 : Disable interrupt on BB event. */
AnnaBridge	171:3a7713b1edbc	6373	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
AnnaBridge	171:3a7713b1edbc	6374	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
AnnaBridge	171:3a7713b1edbc	6375	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6376	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6377	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6378
AnnaBridge	171:3a7713b1edbc	6379	/* Bit 9 : Disable interrupt on ERROR event. */
AnnaBridge	171:3a7713b1edbc	6380	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6381	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6382	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6383	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6384	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6385
AnnaBridge	171:3a7713b1edbc	6386	/* Bit 7 : Disable interrupt on TXDSENT event. */
AnnaBridge	171:3a7713b1edbc	6387	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
AnnaBridge	171:3a7713b1edbc	6388	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
AnnaBridge	171:3a7713b1edbc	6389	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6390	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6391	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6392
AnnaBridge	171:3a7713b1edbc	6393	/* Bit 2 : Disable interrupt on RXDREADY event. */
AnnaBridge	171:3a7713b1edbc	6394	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
AnnaBridge	171:3a7713b1edbc	6395	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
AnnaBridge	171:3a7713b1edbc	6396	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6397	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6398	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6399
AnnaBridge	171:3a7713b1edbc	6400	/* Bit 1 : Disable interrupt on STOPPED event. */
AnnaBridge	171:3a7713b1edbc	6401	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	6402	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
AnnaBridge	171:3a7713b1edbc	6403	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6404	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6405	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6406
AnnaBridge	171:3a7713b1edbc	6407	/* Register: TWI_ERRORSRC */
AnnaBridge	171:3a7713b1edbc	6408	/* Description: Two-wire error source. Write error field to 1 to clear error. */
AnnaBridge	171:3a7713b1edbc	6409
AnnaBridge	171:3a7713b1edbc	6410	/* Bit 2 : NACK received after sending a data byte. */
AnnaBridge	171:3a7713b1edbc	6411	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
AnnaBridge	171:3a7713b1edbc	6412	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
AnnaBridge	171:3a7713b1edbc	6413	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6414	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6415	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
AnnaBridge	171:3a7713b1edbc	6416
AnnaBridge	171:3a7713b1edbc	6417	/* Bit 1 : NACK received after sending the address. */
AnnaBridge	171:3a7713b1edbc	6418	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
AnnaBridge	171:3a7713b1edbc	6419	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
AnnaBridge	171:3a7713b1edbc	6420	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6421	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6422	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
AnnaBridge	171:3a7713b1edbc	6423
AnnaBridge	171:3a7713b1edbc	6424	/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
AnnaBridge	171:3a7713b1edbc	6425	#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
AnnaBridge	171:3a7713b1edbc	6426	#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
AnnaBridge	171:3a7713b1edbc	6427	#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6428	#define TWI_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6429	#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
AnnaBridge	171:3a7713b1edbc	6430
AnnaBridge	171:3a7713b1edbc	6431	/* Register: TWI_ENABLE */
AnnaBridge	171:3a7713b1edbc	6432	/* Description: Enable two-wire master. */
AnnaBridge	171:3a7713b1edbc	6433
AnnaBridge	171:3a7713b1edbc	6434	/* Bits 2..0 : Enable or disable W2M */
AnnaBridge	171:3a7713b1edbc	6435	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	6436	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	6437	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	6438	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	6439
AnnaBridge	171:3a7713b1edbc	6440	/* Register: TWI_RXD */
AnnaBridge	171:3a7713b1edbc	6441	/* Description: RX data register. */
AnnaBridge	171:3a7713b1edbc	6442
AnnaBridge	171:3a7713b1edbc	6443	/* Bits 7..0 : RX data from last transfer. */
AnnaBridge	171:3a7713b1edbc	6444	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
AnnaBridge	171:3a7713b1edbc	6445	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
AnnaBridge	171:3a7713b1edbc	6446
AnnaBridge	171:3a7713b1edbc	6447	/* Register: TWI_TXD */
AnnaBridge	171:3a7713b1edbc	6448	/* Description: TX data register. */
AnnaBridge	171:3a7713b1edbc	6449
AnnaBridge	171:3a7713b1edbc	6450	/* Bits 7..0 : TX data for next transfer. */
AnnaBridge	171:3a7713b1edbc	6451	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
AnnaBridge	171:3a7713b1edbc	6452	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
AnnaBridge	171:3a7713b1edbc	6453
AnnaBridge	171:3a7713b1edbc	6454	/* Register: TWI_FREQUENCY */
AnnaBridge	171:3a7713b1edbc	6455	/* Description: Two-wire frequency. */
AnnaBridge	171:3a7713b1edbc	6456
AnnaBridge	171:3a7713b1edbc	6457	/* Bits 31..0 : Two-wire master clock frequency. */
AnnaBridge	171:3a7713b1edbc	6458	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	6459	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
AnnaBridge	171:3a7713b1edbc	6460	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
AnnaBridge	171:3a7713b1edbc	6461	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
AnnaBridge	171:3a7713b1edbc	6462	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
AnnaBridge	171:3a7713b1edbc	6463
AnnaBridge	171:3a7713b1edbc	6464	/* Register: TWI_ADDRESS */
AnnaBridge	171:3a7713b1edbc	6465	/* Description: Address used in the two-wire transfer. */
AnnaBridge	171:3a7713b1edbc	6466
AnnaBridge	171:3a7713b1edbc	6467	/* Bits 6..0 : Two-wire address. */
AnnaBridge	171:3a7713b1edbc	6468	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
AnnaBridge	171:3a7713b1edbc	6469	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
AnnaBridge	171:3a7713b1edbc	6470
AnnaBridge	171:3a7713b1edbc	6471	/* Register: TWI_POWER */
AnnaBridge	171:3a7713b1edbc	6472	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6473
AnnaBridge	171:3a7713b1edbc	6474	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6475	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	6476	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	6477	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	6478	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	6479
AnnaBridge	171:3a7713b1edbc	6480
AnnaBridge	171:3a7713b1edbc	6481	/* Peripheral: UART */
AnnaBridge	171:3a7713b1edbc	6482	/* Description: Universal Asynchronous Receiver/Transmitter. */
AnnaBridge	171:3a7713b1edbc	6483
AnnaBridge	171:3a7713b1edbc	6484	/* Register: UART_SHORTS */
AnnaBridge	171:3a7713b1edbc	6485	/* Description: Shortcuts for UART. */
AnnaBridge	171:3a7713b1edbc	6486
AnnaBridge	171:3a7713b1edbc	6487	/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
AnnaBridge	171:3a7713b1edbc	6488	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
AnnaBridge	171:3a7713b1edbc	6489	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
AnnaBridge	171:3a7713b1edbc	6490	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6491	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6492
AnnaBridge	171:3a7713b1edbc	6493	/* Bit 3 : Shortcut between CTS event and STARTRX task. */
AnnaBridge	171:3a7713b1edbc	6494	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
AnnaBridge	171:3a7713b1edbc	6495	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
AnnaBridge	171:3a7713b1edbc	6496	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
AnnaBridge	171:3a7713b1edbc	6497	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
AnnaBridge	171:3a7713b1edbc	6498
AnnaBridge	171:3a7713b1edbc	6499	/* Register: UART_INTENSET */
AnnaBridge	171:3a7713b1edbc	6500	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	6501
AnnaBridge	171:3a7713b1edbc	6502	/* Bit 17 : Enable interrupt on RXTO event. */
AnnaBridge	171:3a7713b1edbc	6503	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
AnnaBridge	171:3a7713b1edbc	6504	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
AnnaBridge	171:3a7713b1edbc	6505	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6506	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6507	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6508
AnnaBridge	171:3a7713b1edbc	6509	/* Bit 9 : Enable interrupt on ERROR event. */
AnnaBridge	171:3a7713b1edbc	6510	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6511	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6512	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6513	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6514	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6515
AnnaBridge	171:3a7713b1edbc	6516	/* Bit 7 : Enable interrupt on TXRDY event. */
AnnaBridge	171:3a7713b1edbc	6517	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6518	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6519	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6520	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6521	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6522
AnnaBridge	171:3a7713b1edbc	6523	/* Bit 2 : Enable interrupt on RXRDY event. */
AnnaBridge	171:3a7713b1edbc	6524	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6525	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6526	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6527	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6528	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6529
AnnaBridge	171:3a7713b1edbc	6530	/* Bit 1 : Enable interrupt on NCTS event. */
AnnaBridge	171:3a7713b1edbc	6531	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
AnnaBridge	171:3a7713b1edbc	6532	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
AnnaBridge	171:3a7713b1edbc	6533	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6534	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6535	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6536
AnnaBridge	171:3a7713b1edbc	6537	/* Bit 0 : Enable interrupt on CTS event. */
AnnaBridge	171:3a7713b1edbc	6538	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
AnnaBridge	171:3a7713b1edbc	6539	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
AnnaBridge	171:3a7713b1edbc	6540	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6541	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6542	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6543
AnnaBridge	171:3a7713b1edbc	6544	/* Register: UART_INTENCLR */
AnnaBridge	171:3a7713b1edbc	6545	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	6546
AnnaBridge	171:3a7713b1edbc	6547	/* Bit 17 : Disable interrupt on RXTO event. */
AnnaBridge	171:3a7713b1edbc	6548	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
AnnaBridge	171:3a7713b1edbc	6549	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
AnnaBridge	171:3a7713b1edbc	6550	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6551	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6552	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6553
AnnaBridge	171:3a7713b1edbc	6554	/* Bit 9 : Disable interrupt on ERROR event. */
AnnaBridge	171:3a7713b1edbc	6555	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6556	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
AnnaBridge	171:3a7713b1edbc	6557	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6558	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6559	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6560
AnnaBridge	171:3a7713b1edbc	6561	/* Bit 7 : Disable interrupt on TXRDY event. */
AnnaBridge	171:3a7713b1edbc	6562	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6563	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6564	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6565	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6566	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6567
AnnaBridge	171:3a7713b1edbc	6568	/* Bit 2 : Disable interrupt on RXRDY event. */
AnnaBridge	171:3a7713b1edbc	6569	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6570	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
AnnaBridge	171:3a7713b1edbc	6571	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6572	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6573	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6574
AnnaBridge	171:3a7713b1edbc	6575	/* Bit 1 : Disable interrupt on NCTS event. */
AnnaBridge	171:3a7713b1edbc	6576	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
AnnaBridge	171:3a7713b1edbc	6577	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
AnnaBridge	171:3a7713b1edbc	6578	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6579	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6580	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6581
AnnaBridge	171:3a7713b1edbc	6582	/* Bit 0 : Disable interrupt on CTS event. */
AnnaBridge	171:3a7713b1edbc	6583	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
AnnaBridge	171:3a7713b1edbc	6584	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
AnnaBridge	171:3a7713b1edbc	6585	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6586	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6587	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6588
AnnaBridge	171:3a7713b1edbc	6589	/* Register: UART_ERRORSRC */
AnnaBridge	171:3a7713b1edbc	6590	/* Description: Error source. Write error field to 1 to clear error. */
AnnaBridge	171:3a7713b1edbc	6591
AnnaBridge	171:3a7713b1edbc	6592	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
AnnaBridge	171:3a7713b1edbc	6593	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
AnnaBridge	171:3a7713b1edbc	6594	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
AnnaBridge	171:3a7713b1edbc	6595	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6596	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6597	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
AnnaBridge	171:3a7713b1edbc	6598
AnnaBridge	171:3a7713b1edbc	6599	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
AnnaBridge	171:3a7713b1edbc	6600	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
AnnaBridge	171:3a7713b1edbc	6601	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
AnnaBridge	171:3a7713b1edbc	6602	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6603	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6604	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
AnnaBridge	171:3a7713b1edbc	6605
AnnaBridge	171:3a7713b1edbc	6606	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
AnnaBridge	171:3a7713b1edbc	6607	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
AnnaBridge	171:3a7713b1edbc	6608	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
AnnaBridge	171:3a7713b1edbc	6609	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6610	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6611	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
AnnaBridge	171:3a7713b1edbc	6612
AnnaBridge	171:3a7713b1edbc	6613	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
AnnaBridge	171:3a7713b1edbc	6614	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
AnnaBridge	171:3a7713b1edbc	6615	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
AnnaBridge	171:3a7713b1edbc	6616	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
AnnaBridge	171:3a7713b1edbc	6617	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
AnnaBridge	171:3a7713b1edbc	6618	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
AnnaBridge	171:3a7713b1edbc	6619
AnnaBridge	171:3a7713b1edbc	6620	/* Register: UART_ENABLE */
AnnaBridge	171:3a7713b1edbc	6621	/* Description: Enable UART and acquire IOs. */
AnnaBridge	171:3a7713b1edbc	6622
AnnaBridge	171:3a7713b1edbc	6623	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
AnnaBridge	171:3a7713b1edbc	6624	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	6625	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
AnnaBridge	171:3a7713b1edbc	6626	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
AnnaBridge	171:3a7713b1edbc	6627	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
AnnaBridge	171:3a7713b1edbc	6628
AnnaBridge	171:3a7713b1edbc	6629	/* Register: UART_RXD */
AnnaBridge	171:3a7713b1edbc	6630	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
AnnaBridge	171:3a7713b1edbc	6631
AnnaBridge	171:3a7713b1edbc	6632	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
AnnaBridge	171:3a7713b1edbc	6633	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
AnnaBridge	171:3a7713b1edbc	6634	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
AnnaBridge	171:3a7713b1edbc	6635
AnnaBridge	171:3a7713b1edbc	6636	/* Register: UART_TXD */
AnnaBridge	171:3a7713b1edbc	6637	/* Description: TXD register. */
AnnaBridge	171:3a7713b1edbc	6638
AnnaBridge	171:3a7713b1edbc	6639	/* Bits 7..0 : TX data for transfer. */
AnnaBridge	171:3a7713b1edbc	6640	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
AnnaBridge	171:3a7713b1edbc	6641	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
AnnaBridge	171:3a7713b1edbc	6642
AnnaBridge	171:3a7713b1edbc	6643	/* Register: UART_BAUDRATE */
AnnaBridge	171:3a7713b1edbc	6644	/* Description: UART Baudrate. */
AnnaBridge	171:3a7713b1edbc	6645
AnnaBridge	171:3a7713b1edbc	6646	/* Bits 31..0 : UART baudrate. */
AnnaBridge	171:3a7713b1edbc	6647	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
AnnaBridge	171:3a7713b1edbc	6648	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
AnnaBridge	171:3a7713b1edbc	6649	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
AnnaBridge	171:3a7713b1edbc	6650	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
AnnaBridge	171:3a7713b1edbc	6651	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
AnnaBridge	171:3a7713b1edbc	6652	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
AnnaBridge	171:3a7713b1edbc	6653	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
AnnaBridge	171:3a7713b1edbc	6654	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
AnnaBridge	171:3a7713b1edbc	6655	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
AnnaBridge	171:3a7713b1edbc	6656	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
AnnaBridge	171:3a7713b1edbc	6657	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
AnnaBridge	171:3a7713b1edbc	6658	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
AnnaBridge	171:3a7713b1edbc	6659	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
AnnaBridge	171:3a7713b1edbc	6660	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
AnnaBridge	171:3a7713b1edbc	6661	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
AnnaBridge	171:3a7713b1edbc	6662	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
AnnaBridge	171:3a7713b1edbc	6663	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /!< 921600 baud. /
AnnaBridge	171:3a7713b1edbc	6664	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
AnnaBridge	171:3a7713b1edbc	6665
AnnaBridge	171:3a7713b1edbc	6666	/* Register: UART_CONFIG */
AnnaBridge	171:3a7713b1edbc	6667	/* Description: Configuration of parity and hardware flow control register. */
AnnaBridge	171:3a7713b1edbc	6668
AnnaBridge	171:3a7713b1edbc	6669	/* Bits 3..1 : Include parity bit. */
AnnaBridge	171:3a7713b1edbc	6670	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
AnnaBridge	171:3a7713b1edbc	6671	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
AnnaBridge	171:3a7713b1edbc	6672	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
AnnaBridge	171:3a7713b1edbc	6673	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
AnnaBridge	171:3a7713b1edbc	6674
AnnaBridge	171:3a7713b1edbc	6675	/* Bit 0 : Hardware flow control. */
AnnaBridge	171:3a7713b1edbc	6676	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
AnnaBridge	171:3a7713b1edbc	6677	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
AnnaBridge	171:3a7713b1edbc	6678	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
AnnaBridge	171:3a7713b1edbc	6679	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
AnnaBridge	171:3a7713b1edbc	6680
AnnaBridge	171:3a7713b1edbc	6681	/* Register: UART_POWER */
AnnaBridge	171:3a7713b1edbc	6682	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6683
AnnaBridge	171:3a7713b1edbc	6684	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6685	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	6686	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	6687	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	6688	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	6689
AnnaBridge	171:3a7713b1edbc	6690
AnnaBridge	171:3a7713b1edbc	6691	/* Peripheral: UICR */
AnnaBridge	171:3a7713b1edbc	6692	/* Description: User Information Configuration. */
AnnaBridge	171:3a7713b1edbc	6693
AnnaBridge	171:3a7713b1edbc	6694	/* Register: UICR_RBPCONF */
AnnaBridge	171:3a7713b1edbc	6695	/* Description: Readback protection configuration. */
AnnaBridge	171:3a7713b1edbc	6696
AnnaBridge	171:3a7713b1edbc	6697	/* Bits 15..8 : Readback protect all code in the device. */
AnnaBridge	171:3a7713b1edbc	6698	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
AnnaBridge	171:3a7713b1edbc	6699	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
AnnaBridge	171:3a7713b1edbc	6700	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	6701	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	6702
AnnaBridge	171:3a7713b1edbc	6703	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
AnnaBridge	171:3a7713b1edbc	6704	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
AnnaBridge	171:3a7713b1edbc	6705	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
AnnaBridge	171:3a7713b1edbc	6706	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
AnnaBridge	171:3a7713b1edbc	6707	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
AnnaBridge	171:3a7713b1edbc	6708
AnnaBridge	171:3a7713b1edbc	6709	/* Register: UICR_XTALFREQ */
AnnaBridge	171:3a7713b1edbc	6710	/* Description: Reset value for CLOCK XTALFREQ register. */
AnnaBridge	171:3a7713b1edbc	6711
AnnaBridge	171:3a7713b1edbc	6712	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
AnnaBridge	171:3a7713b1edbc	6713	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
AnnaBridge	171:3a7713b1edbc	6714	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
AnnaBridge	171:3a7713b1edbc	6715	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
AnnaBridge	171:3a7713b1edbc	6716	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
AnnaBridge	171:3a7713b1edbc	6717
AnnaBridge	171:3a7713b1edbc	6718	/* Register: UICR_FWID */
AnnaBridge	171:3a7713b1edbc	6719	/* Description: Firmware ID. */
AnnaBridge	171:3a7713b1edbc	6720
AnnaBridge	171:3a7713b1edbc	6721	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
AnnaBridge	171:3a7713b1edbc	6722	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
AnnaBridge	171:3a7713b1edbc	6723	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
AnnaBridge	171:3a7713b1edbc	6724
AnnaBridge	171:3a7713b1edbc	6725
AnnaBridge	171:3a7713b1edbc	6726	/* Peripheral: WDT */
AnnaBridge	171:3a7713b1edbc	6727	/* Description: Watchdog Timer. */
AnnaBridge	171:3a7713b1edbc	6728
AnnaBridge	171:3a7713b1edbc	6729	/* Register: WDT_INTENSET */
AnnaBridge	171:3a7713b1edbc	6730	/* Description: Interrupt enable set register. */
AnnaBridge	171:3a7713b1edbc	6731
AnnaBridge	171:3a7713b1edbc	6732	/* Bit 0 : Enable interrupt on TIMEOUT event. */
AnnaBridge	171:3a7713b1edbc	6733	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
AnnaBridge	171:3a7713b1edbc	6734	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
AnnaBridge	171:3a7713b1edbc	6735	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6736	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6737	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6738
AnnaBridge	171:3a7713b1edbc	6739	/* Register: WDT_INTENCLR */
AnnaBridge	171:3a7713b1edbc	6740	/* Description: Interrupt enable clear register. */
AnnaBridge	171:3a7713b1edbc	6741
AnnaBridge	171:3a7713b1edbc	6742	/* Bit 0 : Disable interrupt on TIMEOUT event. */
AnnaBridge	171:3a7713b1edbc	6743	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
AnnaBridge	171:3a7713b1edbc	6744	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
AnnaBridge	171:3a7713b1edbc	6745	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
AnnaBridge	171:3a7713b1edbc	6746	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
AnnaBridge	171:3a7713b1edbc	6747	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
AnnaBridge	171:3a7713b1edbc	6748
AnnaBridge	171:3a7713b1edbc	6749	/* Register: WDT_RUNSTATUS */
AnnaBridge	171:3a7713b1edbc	6750	/* Description: Watchdog running status. */
AnnaBridge	171:3a7713b1edbc	6751
AnnaBridge	171:3a7713b1edbc	6752	/* Bit 0 : Watchdog running status. */
AnnaBridge	171:3a7713b1edbc	6753	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
AnnaBridge	171:3a7713b1edbc	6754	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
AnnaBridge	171:3a7713b1edbc	6755	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
AnnaBridge	171:3a7713b1edbc	6756	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
AnnaBridge	171:3a7713b1edbc	6757
AnnaBridge	171:3a7713b1edbc	6758	/* Register: WDT_REQSTATUS */
AnnaBridge	171:3a7713b1edbc	6759	/* Description: Request status. */
AnnaBridge	171:3a7713b1edbc	6760
AnnaBridge	171:3a7713b1edbc	6761	/* Bit 7 : Request status for RR[7]. */
AnnaBridge	171:3a7713b1edbc	6762	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
AnnaBridge	171:3a7713b1edbc	6763	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
AnnaBridge	171:3a7713b1edbc	6764	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6765	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6766
AnnaBridge	171:3a7713b1edbc	6767	/* Bit 6 : Request status for RR[6]. */
AnnaBridge	171:3a7713b1edbc	6768	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
AnnaBridge	171:3a7713b1edbc	6769	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
AnnaBridge	171:3a7713b1edbc	6770	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6771	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6772
AnnaBridge	171:3a7713b1edbc	6773	/* Bit 5 : Request status for RR[5]. */
AnnaBridge	171:3a7713b1edbc	6774	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
AnnaBridge	171:3a7713b1edbc	6775	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
AnnaBridge	171:3a7713b1edbc	6776	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6777	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6778
AnnaBridge	171:3a7713b1edbc	6779	/* Bit 4 : Request status for RR[4]. */
AnnaBridge	171:3a7713b1edbc	6780	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
AnnaBridge	171:3a7713b1edbc	6781	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
AnnaBridge	171:3a7713b1edbc	6782	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6783	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6784
AnnaBridge	171:3a7713b1edbc	6785	/* Bit 3 : Request status for RR[3]. */
AnnaBridge	171:3a7713b1edbc	6786	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
AnnaBridge	171:3a7713b1edbc	6787	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
AnnaBridge	171:3a7713b1edbc	6788	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6789	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6790
AnnaBridge	171:3a7713b1edbc	6791	/* Bit 2 : Request status for RR[2]. */
AnnaBridge	171:3a7713b1edbc	6792	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
AnnaBridge	171:3a7713b1edbc	6793	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
AnnaBridge	171:3a7713b1edbc	6794	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6795	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6796
AnnaBridge	171:3a7713b1edbc	6797	/* Bit 1 : Request status for RR[1]. */
AnnaBridge	171:3a7713b1edbc	6798	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
AnnaBridge	171:3a7713b1edbc	6799	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
AnnaBridge	171:3a7713b1edbc	6800	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6801	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6802
AnnaBridge	171:3a7713b1edbc	6803	/* Bit 0 : Request status for RR[0]. */
AnnaBridge	171:3a7713b1edbc	6804	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
AnnaBridge	171:3a7713b1edbc	6805	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
AnnaBridge	171:3a7713b1edbc	6806	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
AnnaBridge	171:3a7713b1edbc	6807	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
AnnaBridge	171:3a7713b1edbc	6808
AnnaBridge	171:3a7713b1edbc	6809	/* Register: WDT_RREN */
AnnaBridge	171:3a7713b1edbc	6810	/* Description: Reload request enable. */
AnnaBridge	171:3a7713b1edbc	6811
AnnaBridge	171:3a7713b1edbc	6812	/* Bit 7 : Enable or disable RR[7] register. */
AnnaBridge	171:3a7713b1edbc	6813	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
AnnaBridge	171:3a7713b1edbc	6814	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
AnnaBridge	171:3a7713b1edbc	6815	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6816	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6817
AnnaBridge	171:3a7713b1edbc	6818	/* Bit 6 : Enable or disable RR[6] register. */
AnnaBridge	171:3a7713b1edbc	6819	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
AnnaBridge	171:3a7713b1edbc	6820	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
AnnaBridge	171:3a7713b1edbc	6821	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6822	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6823
AnnaBridge	171:3a7713b1edbc	6824	/* Bit 5 : Enable or disable RR[5] register. */
AnnaBridge	171:3a7713b1edbc	6825	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
AnnaBridge	171:3a7713b1edbc	6826	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
AnnaBridge	171:3a7713b1edbc	6827	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6828	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6829
AnnaBridge	171:3a7713b1edbc	6830	/* Bit 4 : Enable or disable RR[4] register. */
AnnaBridge	171:3a7713b1edbc	6831	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
AnnaBridge	171:3a7713b1edbc	6832	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
AnnaBridge	171:3a7713b1edbc	6833	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6834	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6835
AnnaBridge	171:3a7713b1edbc	6836	/* Bit 3 : Enable or disable RR[3] register. */
AnnaBridge	171:3a7713b1edbc	6837	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
AnnaBridge	171:3a7713b1edbc	6838	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
AnnaBridge	171:3a7713b1edbc	6839	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6840	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6841
AnnaBridge	171:3a7713b1edbc	6842	/* Bit 2 : Enable or disable RR[2] register. */
AnnaBridge	171:3a7713b1edbc	6843	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
AnnaBridge	171:3a7713b1edbc	6844	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
AnnaBridge	171:3a7713b1edbc	6845	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6846	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6847
AnnaBridge	171:3a7713b1edbc	6848	/* Bit 1 : Enable or disable RR[1] register. */
AnnaBridge	171:3a7713b1edbc	6849	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
AnnaBridge	171:3a7713b1edbc	6850	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
AnnaBridge	171:3a7713b1edbc	6851	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6852	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6853
AnnaBridge	171:3a7713b1edbc	6854	/* Bit 0 : Enable or disable RR[0] register. */
AnnaBridge	171:3a7713b1edbc	6855	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
AnnaBridge	171:3a7713b1edbc	6856	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
AnnaBridge	171:3a7713b1edbc	6857	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
AnnaBridge	171:3a7713b1edbc	6858	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
AnnaBridge	171:3a7713b1edbc	6859
AnnaBridge	171:3a7713b1edbc	6860	/* Register: WDT_CONFIG */
AnnaBridge	171:3a7713b1edbc	6861	/* Description: Configuration register. */
AnnaBridge	171:3a7713b1edbc	6862
AnnaBridge	171:3a7713b1edbc	6863	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
AnnaBridge	171:3a7713b1edbc	6864	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
AnnaBridge	171:3a7713b1edbc	6865	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
AnnaBridge	171:3a7713b1edbc	6866	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
AnnaBridge	171:3a7713b1edbc	6867	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
AnnaBridge	171:3a7713b1edbc	6868
AnnaBridge	171:3a7713b1edbc	6869	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
AnnaBridge	171:3a7713b1edbc	6870	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
AnnaBridge	171:3a7713b1edbc	6871	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
AnnaBridge	171:3a7713b1edbc	6872	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
AnnaBridge	171:3a7713b1edbc	6873	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
AnnaBridge	171:3a7713b1edbc	6874
AnnaBridge	171:3a7713b1edbc	6875	/* Register: WDT_RR */
AnnaBridge	171:3a7713b1edbc	6876	/* Description: Reload requests registers. */
AnnaBridge	171:3a7713b1edbc	6877
AnnaBridge	171:3a7713b1edbc	6878	/* Bits 31..0 : Reload register. */
AnnaBridge	171:3a7713b1edbc	6879	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
AnnaBridge	171:3a7713b1edbc	6880	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
AnnaBridge	171:3a7713b1edbc	6881	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
AnnaBridge	171:3a7713b1edbc	6882
AnnaBridge	171:3a7713b1edbc	6883	/* Register: WDT_POWER */
AnnaBridge	171:3a7713b1edbc	6884	/* Description: Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6885
AnnaBridge	171:3a7713b1edbc	6886	/* Bit 0 : Peripheral power control. */
AnnaBridge	171:3a7713b1edbc	6887	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
AnnaBridge	171:3a7713b1edbc	6888	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
AnnaBridge	171:3a7713b1edbc	6889	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
AnnaBridge	171:3a7713b1edbc	6890	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
AnnaBridge	171:3a7713b1edbc	6891
AnnaBridge	171:3a7713b1edbc	6892
AnnaBridge	171:3a7713b1edbc	6893	/lint --flb "Leave library region" /
AnnaBridge	171:3a7713b1edbc	6894	#endif