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TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VK_RZ_A1H.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 165:d1b4690b3f8b | 1 | /****************************************************************************** |
| AnnaBridge | 165:d1b4690b3f8b | 2 | * @file VK_RZ_A1H.h |
| AnnaBridge | 165:d1b4690b3f8b | 3 | * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File |
| AnnaBridge | 165:d1b4690b3f8b | 4 | * @version V1.00 |
| AnnaBridge | 165:d1b4690b3f8b | 5 | * @data 10 Mar 2017 |
| AnnaBridge | 165:d1b4690b3f8b | 6 | * |
| AnnaBridge | 165:d1b4690b3f8b | 7 | * @note |
| AnnaBridge | 165:d1b4690b3f8b | 8 | * |
| AnnaBridge | 165:d1b4690b3f8b | 9 | ******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 10 | /* |
| AnnaBridge | 165:d1b4690b3f8b | 11 | * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
| AnnaBridge | 165:d1b4690b3f8b | 12 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
| AnnaBridge | 165:d1b4690b3f8b | 13 | * |
| AnnaBridge | 165:d1b4690b3f8b | 14 | * SPDX-License-Identifier: Apache-2.0 |
| AnnaBridge | 165:d1b4690b3f8b | 15 | * |
| AnnaBridge | 165:d1b4690b3f8b | 16 | * Licensed under the Apache License, Version 2.0 (the License); you may |
| AnnaBridge | 165:d1b4690b3f8b | 17 | * not use this file except in compliance with the License. |
| AnnaBridge | 165:d1b4690b3f8b | 18 | * You may obtain a copy of the License at |
| AnnaBridge | 165:d1b4690b3f8b | 19 | * |
| AnnaBridge | 165:d1b4690b3f8b | 20 | * www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 165:d1b4690b3f8b | 21 | * |
| AnnaBridge | 165:d1b4690b3f8b | 22 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 165:d1b4690b3f8b | 23 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| AnnaBridge | 165:d1b4690b3f8b | 24 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 165:d1b4690b3f8b | 25 | * See the License for the specific language governing permissions and |
| AnnaBridge | 165:d1b4690b3f8b | 26 | * limitations under the License. |
| AnnaBridge | 165:d1b4690b3f8b | 27 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 28 | |
| AnnaBridge | 165:d1b4690b3f8b | 29 | #ifndef __VK_RZ_A1H_H__ |
| AnnaBridge | 165:d1b4690b3f8b | 30 | #define __VK_RZ_A1H_H__ |
| AnnaBridge | 165:d1b4690b3f8b | 31 | |
| AnnaBridge | 165:d1b4690b3f8b | 32 | #ifdef __cplusplus |
| AnnaBridge | 165:d1b4690b3f8b | 33 | extern "C" { |
| AnnaBridge | 165:d1b4690b3f8b | 34 | #endif |
| AnnaBridge | 165:d1b4690b3f8b | 35 | |
| AnnaBridge | 165:d1b4690b3f8b | 36 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
| AnnaBridge | 165:d1b4690b3f8b | 37 | |
| AnnaBridge | 165:d1b4690b3f8b | 38 | typedef enum IRQn |
| AnnaBridge | 165:d1b4690b3f8b | 39 | { |
| AnnaBridge | 165:d1b4690b3f8b | 40 | /****** SGI Interrupts Numbers ****************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 41 | SGI0_IRQn = 0, |
| AnnaBridge | 165:d1b4690b3f8b | 42 | SGI1_IRQn = 1, |
| AnnaBridge | 165:d1b4690b3f8b | 43 | SGI2_IRQn = 2, |
| AnnaBridge | 165:d1b4690b3f8b | 44 | SGI3_IRQn = 3, |
| AnnaBridge | 165:d1b4690b3f8b | 45 | SGI4_IRQn = 4, |
| AnnaBridge | 165:d1b4690b3f8b | 46 | SGI5_IRQn = 5, |
| AnnaBridge | 165:d1b4690b3f8b | 47 | SGI6_IRQn = 6, |
| AnnaBridge | 165:d1b4690b3f8b | 48 | SGI7_IRQn = 7, |
| AnnaBridge | 165:d1b4690b3f8b | 49 | SGI8_IRQn = 8, |
| AnnaBridge | 165:d1b4690b3f8b | 50 | SGI9_IRQn = 9, |
| AnnaBridge | 165:d1b4690b3f8b | 51 | SGI10_IRQn = 10, |
| AnnaBridge | 165:d1b4690b3f8b | 52 | SGI11_IRQn = 11, |
| AnnaBridge | 165:d1b4690b3f8b | 53 | SGI12_IRQn = 12, |
| AnnaBridge | 165:d1b4690b3f8b | 54 | SGI13_IRQn = 13, |
| AnnaBridge | 165:d1b4690b3f8b | 55 | SGI14_IRQn = 14, |
| AnnaBridge | 165:d1b4690b3f8b | 56 | SGI15_IRQn = 15, |
| AnnaBridge | 165:d1b4690b3f8b | 57 | |
| AnnaBridge | 165:d1b4690b3f8b | 58 | /****** Cortex-A9 Processor Exceptions Numbers ****************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 59 | /* 16 - 578 */ |
| AnnaBridge | 165:d1b4690b3f8b | 60 | PMUIRQ0_IRQn = 16, |
| AnnaBridge | 165:d1b4690b3f8b | 61 | COMMRX0_IRQn = 17, |
| AnnaBridge | 165:d1b4690b3f8b | 62 | COMMTX0_IRQn = 18, |
| AnnaBridge | 165:d1b4690b3f8b | 63 | CTIIRQ0_IRQn = 19, |
| AnnaBridge | 165:d1b4690b3f8b | 64 | |
| AnnaBridge | 165:d1b4690b3f8b | 65 | IRQ0_IRQn = 32, |
| AnnaBridge | 165:d1b4690b3f8b | 66 | IRQ1_IRQn = 33, |
| AnnaBridge | 165:d1b4690b3f8b | 67 | IRQ2_IRQn = 34, |
| AnnaBridge | 165:d1b4690b3f8b | 68 | IRQ3_IRQn = 35, |
| AnnaBridge | 165:d1b4690b3f8b | 69 | IRQ4_IRQn = 36, |
| AnnaBridge | 165:d1b4690b3f8b | 70 | IRQ5_IRQn = 37, |
| AnnaBridge | 165:d1b4690b3f8b | 71 | IRQ6_IRQn = 38, |
| AnnaBridge | 165:d1b4690b3f8b | 72 | IRQ7_IRQn = 39, |
| AnnaBridge | 165:d1b4690b3f8b | 73 | |
| AnnaBridge | 165:d1b4690b3f8b | 74 | PL310ERR_IRQn = 40, |
| AnnaBridge | 165:d1b4690b3f8b | 75 | |
| AnnaBridge | 165:d1b4690b3f8b | 76 | DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 77 | DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 78 | DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 79 | DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 80 | DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 81 | DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 82 | DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 83 | DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 84 | DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 85 | DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 86 | DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 87 | DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 88 | DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 89 | DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 90 | DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 91 | DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 92 | DMAERR_IRQn = 57, /*!< DMAC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 93 | |
| AnnaBridge | 165:d1b4690b3f8b | 94 | /* 58-72 Reserved */ |
| AnnaBridge | 165:d1b4690b3f8b | 95 | |
| AnnaBridge | 165:d1b4690b3f8b | 96 | USBI0_IRQn = 73, |
| AnnaBridge | 165:d1b4690b3f8b | 97 | USBI1_IRQn = 74, |
| AnnaBridge | 165:d1b4690b3f8b | 98 | |
| AnnaBridge | 165:d1b4690b3f8b | 99 | S0_VI_VSYNC0_IRQn = 75, |
| AnnaBridge | 165:d1b4690b3f8b | 100 | S0_LO_VSYNC0_IRQn = 76, |
| AnnaBridge | 165:d1b4690b3f8b | 101 | S0_VSYNCERR0_IRQn = 77, |
| AnnaBridge | 165:d1b4690b3f8b | 102 | GR3_VLINE0_IRQn = 78, |
| AnnaBridge | 165:d1b4690b3f8b | 103 | S0_VFIELD0_IRQn = 79, |
| AnnaBridge | 165:d1b4690b3f8b | 104 | IV1_VBUFERR0_IRQn = 80, |
| AnnaBridge | 165:d1b4690b3f8b | 105 | IV3_VBUFERR0_IRQn = 81, |
| AnnaBridge | 165:d1b4690b3f8b | 106 | IV5_VBUFERR0_IRQn = 82, |
| AnnaBridge | 165:d1b4690b3f8b | 107 | IV6_VBUFERR0_IRQn = 83, |
| AnnaBridge | 165:d1b4690b3f8b | 108 | S0_WLINE0_IRQn = 84, |
| AnnaBridge | 165:d1b4690b3f8b | 109 | S1_VI_VSYNC0_IRQn = 85, |
| AnnaBridge | 165:d1b4690b3f8b | 110 | S1_LO_VSYNC0_IRQn = 86, |
| AnnaBridge | 165:d1b4690b3f8b | 111 | S1_VSYNCERR0_IRQn = 87, |
| AnnaBridge | 165:d1b4690b3f8b | 112 | S1_VFIELD0_IRQn = 88, |
| AnnaBridge | 165:d1b4690b3f8b | 113 | IV2_VBUFERR0_IRQn = 89, |
| AnnaBridge | 165:d1b4690b3f8b | 114 | IV4_VBUFERR0_IRQn = 90, |
| AnnaBridge | 165:d1b4690b3f8b | 115 | S1_WLINE0_IRQn = 91, |
| AnnaBridge | 165:d1b4690b3f8b | 116 | OIR_VI_VSYNC0_IRQn = 92, |
| AnnaBridge | 165:d1b4690b3f8b | 117 | OIR_LO_VSYNC0_IRQn = 93, |
| AnnaBridge | 165:d1b4690b3f8b | 118 | OIR_VSYNCERR0_IRQn = 94, |
| AnnaBridge | 165:d1b4690b3f8b | 119 | OIR_VFIELD0_IRQn = 95, |
| AnnaBridge | 165:d1b4690b3f8b | 120 | IV7_VBUFERR0_IRQn = 96, |
| AnnaBridge | 165:d1b4690b3f8b | 121 | IV8_VBUFERR0_IRQn = 97, |
| AnnaBridge | 165:d1b4690b3f8b | 122 | /* 98 Reserved */ |
| AnnaBridge | 165:d1b4690b3f8b | 123 | S0_VI_VSYNC1_IRQn = 99, |
| AnnaBridge | 165:d1b4690b3f8b | 124 | S0_LO_VSYNC1_IRQn = 100, |
| AnnaBridge | 165:d1b4690b3f8b | 125 | S0_VSYNCERR1_IRQn = 101, |
| AnnaBridge | 165:d1b4690b3f8b | 126 | GR3_VLINE1_IRQn = 102, |
| AnnaBridge | 165:d1b4690b3f8b | 127 | S0_VFIELD1_IRQn = 103, |
| AnnaBridge | 165:d1b4690b3f8b | 128 | IV1_VBUFERR1_IRQn = 104, |
| AnnaBridge | 165:d1b4690b3f8b | 129 | IV3_VBUFERR1_IRQn = 105, |
| AnnaBridge | 165:d1b4690b3f8b | 130 | IV5_VBUFERR1_IRQn = 106, |
| AnnaBridge | 165:d1b4690b3f8b | 131 | IV6_VBUFERR1_IRQn = 107, |
| AnnaBridge | 165:d1b4690b3f8b | 132 | S0_WLINE1_IRQn = 108, |
| AnnaBridge | 165:d1b4690b3f8b | 133 | S1_VI_VSYNC1_IRQn = 109, |
| AnnaBridge | 165:d1b4690b3f8b | 134 | S1_LO_VSYNC1_IRQn = 110, |
| AnnaBridge | 165:d1b4690b3f8b | 135 | S1_VSYNCERR1_IRQn = 111, |
| AnnaBridge | 165:d1b4690b3f8b | 136 | S1_VFIELD1_IRQn = 112, |
| AnnaBridge | 165:d1b4690b3f8b | 137 | IV2_VBUFERR1_IRQn = 113, |
| AnnaBridge | 165:d1b4690b3f8b | 138 | IV4_VBUFERR1_IRQn = 114, |
| AnnaBridge | 165:d1b4690b3f8b | 139 | S1_WLINE1_IRQn = 115, |
| AnnaBridge | 165:d1b4690b3f8b | 140 | OIR_VI_VSYNC1_IRQn = 116, |
| AnnaBridge | 165:d1b4690b3f8b | 141 | OIR_LO_VSYNC1_IRQn = 117, |
| AnnaBridge | 165:d1b4690b3f8b | 142 | OIR_VSYNCERR1_IRQn = 118, |
| AnnaBridge | 165:d1b4690b3f8b | 143 | OIR_VFIELD1_IRQn = 119, |
| AnnaBridge | 165:d1b4690b3f8b | 144 | IV7_VBUFERR1_IRQn = 120, |
| AnnaBridge | 165:d1b4690b3f8b | 145 | IV8_VBUFERR1_IRQn = 121, |
| AnnaBridge | 165:d1b4690b3f8b | 146 | /* Reserved = 122 */ |
| AnnaBridge | 165:d1b4690b3f8b | 147 | |
| AnnaBridge | 165:d1b4690b3f8b | 148 | IMRDI_IRQn = 123, |
| AnnaBridge | 165:d1b4690b3f8b | 149 | IMR2I0_IRQn = 124, |
| AnnaBridge | 165:d1b4690b3f8b | 150 | IMR2I1_IRQn = 125, |
| AnnaBridge | 165:d1b4690b3f8b | 151 | |
| AnnaBridge | 165:d1b4690b3f8b | 152 | JEDI_IRQn = 126, |
| AnnaBridge | 165:d1b4690b3f8b | 153 | JDTI_IRQn = 127, |
| AnnaBridge | 165:d1b4690b3f8b | 154 | |
| AnnaBridge | 165:d1b4690b3f8b | 155 | CMP0_IRQn = 128, |
| AnnaBridge | 165:d1b4690b3f8b | 156 | CMP1_IRQn = 129, |
| AnnaBridge | 165:d1b4690b3f8b | 157 | |
| AnnaBridge | 165:d1b4690b3f8b | 158 | INT0_IRQn = 130, |
| AnnaBridge | 165:d1b4690b3f8b | 159 | INT1_IRQn = 131, |
| AnnaBridge | 165:d1b4690b3f8b | 160 | INT2_IRQn = 132, |
| AnnaBridge | 165:d1b4690b3f8b | 161 | INT3_IRQn = 133, |
| AnnaBridge | 165:d1b4690b3f8b | 162 | |
| AnnaBridge | 165:d1b4690b3f8b | 163 | OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 164 | OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 165 | |
| AnnaBridge | 165:d1b4690b3f8b | 166 | CMI_IRQn = 136, |
| AnnaBridge | 165:d1b4690b3f8b | 167 | WTOUT_IRQn = 137, |
| AnnaBridge | 165:d1b4690b3f8b | 168 | |
| AnnaBridge | 165:d1b4690b3f8b | 169 | ITI_IRQn = 138, |
| AnnaBridge | 165:d1b4690b3f8b | 170 | |
| AnnaBridge | 165:d1b4690b3f8b | 171 | TGI0A_IRQn = 139, |
| AnnaBridge | 165:d1b4690b3f8b | 172 | TGI0B_IRQn = 140, |
| AnnaBridge | 165:d1b4690b3f8b | 173 | TGI0C_IRQn = 141, |
| AnnaBridge | 165:d1b4690b3f8b | 174 | TGI0D_IRQn = 142, |
| AnnaBridge | 165:d1b4690b3f8b | 175 | TGI0V_IRQn = 143, |
| AnnaBridge | 165:d1b4690b3f8b | 176 | TGI0E_IRQn = 144, |
| AnnaBridge | 165:d1b4690b3f8b | 177 | TGI0F_IRQn = 145, |
| AnnaBridge | 165:d1b4690b3f8b | 178 | TGI1A_IRQn = 146, |
| AnnaBridge | 165:d1b4690b3f8b | 179 | TGI1B_IRQn = 147, |
| AnnaBridge | 165:d1b4690b3f8b | 180 | TGI1V_IRQn = 148, |
| AnnaBridge | 165:d1b4690b3f8b | 181 | TGI1U_IRQn = 149, |
| AnnaBridge | 165:d1b4690b3f8b | 182 | TGI2A_IRQn = 150, |
| AnnaBridge | 165:d1b4690b3f8b | 183 | TGI2B_IRQn = 151, |
| AnnaBridge | 165:d1b4690b3f8b | 184 | TGI2V_IRQn = 152, |
| AnnaBridge | 165:d1b4690b3f8b | 185 | TGI2U_IRQn = 153, |
| AnnaBridge | 165:d1b4690b3f8b | 186 | TGI3A_IRQn = 154, |
| AnnaBridge | 165:d1b4690b3f8b | 187 | TGI3B_IRQn = 155, |
| AnnaBridge | 165:d1b4690b3f8b | 188 | TGI3C_IRQn = 156, |
| AnnaBridge | 165:d1b4690b3f8b | 189 | TGI3D_IRQn = 157, |
| AnnaBridge | 165:d1b4690b3f8b | 190 | TGI3V_IRQn = 158, |
| AnnaBridge | 165:d1b4690b3f8b | 191 | TGI4A_IRQn = 159, |
| AnnaBridge | 165:d1b4690b3f8b | 192 | TGI4B_IRQn = 160, |
| AnnaBridge | 165:d1b4690b3f8b | 193 | TGI4C_IRQn = 161, |
| AnnaBridge | 165:d1b4690b3f8b | 194 | TGI4D_IRQn = 162, |
| AnnaBridge | 165:d1b4690b3f8b | 195 | TGI4V_IRQn = 163, |
| AnnaBridge | 165:d1b4690b3f8b | 196 | |
| AnnaBridge | 165:d1b4690b3f8b | 197 | CMI1_IRQn = 164, |
| AnnaBridge | 165:d1b4690b3f8b | 198 | CMI2_IRQn = 165, |
| AnnaBridge | 165:d1b4690b3f8b | 199 | |
| AnnaBridge | 165:d1b4690b3f8b | 200 | SGDEI0_IRQn = 166, |
| AnnaBridge | 165:d1b4690b3f8b | 201 | SGDEI1_IRQn = 167, |
| AnnaBridge | 165:d1b4690b3f8b | 202 | SGDEI2_IRQn = 168, |
| AnnaBridge | 165:d1b4690b3f8b | 203 | SGDEI3_IRQn = 169, |
| AnnaBridge | 165:d1b4690b3f8b | 204 | |
| AnnaBridge | 165:d1b4690b3f8b | 205 | ADI_IRQn = 170, |
| AnnaBridge | 165:d1b4690b3f8b | 206 | LMTI_IRQn = 171, |
| AnnaBridge | 165:d1b4690b3f8b | 207 | |
| AnnaBridge | 165:d1b4690b3f8b | 208 | SSII0_IRQn = 172, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 209 | SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 210 | SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 211 | SSII1_IRQn = 175, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 212 | SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 213 | SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 214 | SSII2_IRQn = 178, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 215 | SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 216 | SSII3_IRQn = 180, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 217 | SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 218 | SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 219 | SSII4_IRQn = 183, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 220 | SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 221 | SSII5_IRQn = 185, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 222 | SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 223 | SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 224 | |
| AnnaBridge | 165:d1b4690b3f8b | 225 | SPDIFI_IRQn = 188, |
| AnnaBridge | 165:d1b4690b3f8b | 226 | |
| AnnaBridge | 165:d1b4690b3f8b | 227 | INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 228 | INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 229 | INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 230 | INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 231 | INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 232 | INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 233 | INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 234 | INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 235 | INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 236 | INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 237 | INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 238 | INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 239 | INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 240 | INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 241 | INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 242 | INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 243 | INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 244 | INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 245 | INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 246 | INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 247 | INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 248 | INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 249 | INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 250 | INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 251 | INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 252 | INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 253 | INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 254 | INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 255 | INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 256 | INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 257 | INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 258 | INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 259 | |
| AnnaBridge | 165:d1b4690b3f8b | 260 | SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 261 | SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 262 | SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 263 | SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 264 | SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 265 | SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 266 | SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 267 | SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 268 | SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 269 | SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 270 | SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 271 | SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 272 | SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 273 | SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 274 | SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 275 | SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 276 | SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 277 | SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 278 | SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 279 | SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 280 | SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 281 | SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 282 | SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 283 | SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 284 | SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 285 | SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 286 | SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 287 | SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 288 | SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 289 | SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 290 | SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 291 | SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 292 | |
| AnnaBridge | 165:d1b4690b3f8b | 293 | INTRCANGERR_IRQn = 253, |
| AnnaBridge | 165:d1b4690b3f8b | 294 | INTRCANGRECC_IRQn = 254, |
| AnnaBridge | 165:d1b4690b3f8b | 295 | INTRCAN0REC_IRQn = 255, |
| AnnaBridge | 165:d1b4690b3f8b | 296 | INTRCAN0ERR_IRQn = 256, |
| AnnaBridge | 165:d1b4690b3f8b | 297 | INTRCAN0TRX_IRQn = 257, |
| AnnaBridge | 165:d1b4690b3f8b | 298 | INTRCAN1REC_IRQn = 258, |
| AnnaBridge | 165:d1b4690b3f8b | 299 | INTRCAN1ERR_IRQn = 259, |
| AnnaBridge | 165:d1b4690b3f8b | 300 | INTRCAN1TRX_IRQn = 260, |
| AnnaBridge | 165:d1b4690b3f8b | 301 | INTRCAN2REC_IRQn = 261, |
| AnnaBridge | 165:d1b4690b3f8b | 302 | INTRCAN2ERR_IRQn = 262, |
| AnnaBridge | 165:d1b4690b3f8b | 303 | INTRCAN2TRX_IRQn = 263, |
| AnnaBridge | 165:d1b4690b3f8b | 304 | INTRCAN3REC_IRQn = 264, |
| AnnaBridge | 165:d1b4690b3f8b | 305 | INTRCAN3ERR_IRQn = 265, |
| AnnaBridge | 165:d1b4690b3f8b | 306 | INTRCAN3TRX_IRQn = 266, |
| AnnaBridge | 165:d1b4690b3f8b | 307 | INTRCAN4REC_IRQn = 267, |
| AnnaBridge | 165:d1b4690b3f8b | 308 | INTRCAN4ERR_IRQn = 268, |
| AnnaBridge | 165:d1b4690b3f8b | 309 | INTRCAN4TRX_IRQn = 269, |
| AnnaBridge | 165:d1b4690b3f8b | 310 | |
| AnnaBridge | 165:d1b4690b3f8b | 311 | RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 312 | RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 313 | RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 314 | RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 315 | RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 316 | RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 317 | RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 318 | RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 319 | RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 320 | RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 321 | RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 322 | RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 323 | RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 324 | RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 325 | RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ |
| AnnaBridge | 165:d1b4690b3f8b | 326 | |
| AnnaBridge | 165:d1b4690b3f8b | 327 | IEBBTD_IRQn = 285, |
| AnnaBridge | 165:d1b4690b3f8b | 328 | IEBBTERR_IRQn = 286, |
| AnnaBridge | 165:d1b4690b3f8b | 329 | IEBBTSTA_IRQn = 287, |
| AnnaBridge | 165:d1b4690b3f8b | 330 | IEBBTV_IRQn = 288, |
| AnnaBridge | 165:d1b4690b3f8b | 331 | |
| AnnaBridge | 165:d1b4690b3f8b | 332 | ISY_IRQn = 289, |
| AnnaBridge | 165:d1b4690b3f8b | 333 | IERR_IRQn = 290, |
| AnnaBridge | 165:d1b4690b3f8b | 334 | ITARG_IRQn = 291, |
| AnnaBridge | 165:d1b4690b3f8b | 335 | ISEC_IRQn = 292, |
| AnnaBridge | 165:d1b4690b3f8b | 336 | IBUF_IRQn = 293, |
| AnnaBridge | 165:d1b4690b3f8b | 337 | IREADY_IRQn = 294, |
| AnnaBridge | 165:d1b4690b3f8b | 338 | |
| AnnaBridge | 165:d1b4690b3f8b | 339 | STERB_IRQn = 295, |
| AnnaBridge | 165:d1b4690b3f8b | 340 | FLTENDI_IRQn = 296, |
| AnnaBridge | 165:d1b4690b3f8b | 341 | FLTREQ0I_IRQn = 297, |
| AnnaBridge | 165:d1b4690b3f8b | 342 | FLTREQ1I_IRQn = 298, |
| AnnaBridge | 165:d1b4690b3f8b | 343 | |
| AnnaBridge | 165:d1b4690b3f8b | 344 | MMC0_IRQn = 299, |
| AnnaBridge | 165:d1b4690b3f8b | 345 | MMC1_IRQn = 300, |
| AnnaBridge | 165:d1b4690b3f8b | 346 | MMC2_IRQn = 301, |
| AnnaBridge | 165:d1b4690b3f8b | 347 | |
| AnnaBridge | 165:d1b4690b3f8b | 348 | SCHI0_3_IRQn = 302, |
| AnnaBridge | 165:d1b4690b3f8b | 349 | SDHI0_0_IRQn = 303, |
| AnnaBridge | 165:d1b4690b3f8b | 350 | SDHI0_1_IRQn = 304, |
| AnnaBridge | 165:d1b4690b3f8b | 351 | SCHI1_3_IRQn = 305, |
| AnnaBridge | 165:d1b4690b3f8b | 352 | SDHI1_0_IRQn = 306, |
| AnnaBridge | 165:d1b4690b3f8b | 353 | SDHI1_1_IRQn = 307, |
| AnnaBridge | 165:d1b4690b3f8b | 354 | |
| AnnaBridge | 165:d1b4690b3f8b | 355 | ARM_IRQn = 308, |
| AnnaBridge | 165:d1b4690b3f8b | 356 | PRD_IRQn = 309, |
| AnnaBridge | 165:d1b4690b3f8b | 357 | CUP_IRQn = 310, |
| AnnaBridge | 165:d1b4690b3f8b | 358 | |
| AnnaBridge | 165:d1b4690b3f8b | 359 | SCUAI0_IRQn = 311, |
| AnnaBridge | 165:d1b4690b3f8b | 360 | SCUAI1_IRQn = 312, |
| AnnaBridge | 165:d1b4690b3f8b | 361 | SCUFDI0_IRQn = 313, |
| AnnaBridge | 165:d1b4690b3f8b | 362 | SCUFDI1_IRQn = 314, |
| AnnaBridge | 165:d1b4690b3f8b | 363 | SCUFDI2_IRQn = 315, |
| AnnaBridge | 165:d1b4690b3f8b | 364 | SCUFDI3_IRQn = 316, |
| AnnaBridge | 165:d1b4690b3f8b | 365 | SCUFUI0_IRQn = 317, |
| AnnaBridge | 165:d1b4690b3f8b | 366 | SCUFUI1_IRQn = 318, |
| AnnaBridge | 165:d1b4690b3f8b | 367 | SCUFUI2_IRQn = 319, |
| AnnaBridge | 165:d1b4690b3f8b | 368 | SCUFUI3_IRQn = 320, |
| AnnaBridge | 165:d1b4690b3f8b | 369 | SCUDVI0_IRQn = 321, |
| AnnaBridge | 165:d1b4690b3f8b | 370 | SCUDVI1_IRQn = 322, |
| AnnaBridge | 165:d1b4690b3f8b | 371 | SCUDVI2_IRQn = 323, |
| AnnaBridge | 165:d1b4690b3f8b | 372 | SCUDVI3_IRQn = 324, |
| AnnaBridge | 165:d1b4690b3f8b | 373 | |
| AnnaBridge | 165:d1b4690b3f8b | 374 | MLB_CINT_IRQn = 325, |
| AnnaBridge | 165:d1b4690b3f8b | 375 | MLB_SINT_IRQn = 326, |
| AnnaBridge | 165:d1b4690b3f8b | 376 | |
| AnnaBridge | 165:d1b4690b3f8b | 377 | DRC10_IRQn = 327, |
| AnnaBridge | 165:d1b4690b3f8b | 378 | DRC11_IRQn = 328, |
| AnnaBridge | 165:d1b4690b3f8b | 379 | |
| AnnaBridge | 165:d1b4690b3f8b | 380 | /* 329-330 Reserved */ |
| AnnaBridge | 165:d1b4690b3f8b | 381 | |
| AnnaBridge | 165:d1b4690b3f8b | 382 | LINI0_INT_T_IRQn = 331, |
| AnnaBridge | 165:d1b4690b3f8b | 383 | LINI0_INT_R_IRQn = 332, |
| AnnaBridge | 165:d1b4690b3f8b | 384 | LINI0_INT_S_IRQn = 333, |
| AnnaBridge | 165:d1b4690b3f8b | 385 | LINI0_INT_M_IRQn = 334, |
| AnnaBridge | 165:d1b4690b3f8b | 386 | LINI1_INT_T_IRQn = 335, |
| AnnaBridge | 165:d1b4690b3f8b | 387 | LINI1_INT_R_IRQn = 336, |
| AnnaBridge | 165:d1b4690b3f8b | 388 | LINI1_INT_S_IRQn = 337, |
| AnnaBridge | 165:d1b4690b3f8b | 389 | LINI1_INT_M_IRQn = 338, |
| AnnaBridge | 165:d1b4690b3f8b | 390 | |
| AnnaBridge | 165:d1b4690b3f8b | 391 | /* 339-346 Reserved */ |
| AnnaBridge | 165:d1b4690b3f8b | 392 | |
| AnnaBridge | 165:d1b4690b3f8b | 393 | SCIERI0_IRQn = 347, |
| AnnaBridge | 165:d1b4690b3f8b | 394 | SCIRXI0_IRQn = 348, |
| AnnaBridge | 165:d1b4690b3f8b | 395 | SCITXI0_IRQn = 349, |
| AnnaBridge | 165:d1b4690b3f8b | 396 | SCITEI0_IRQn = 350, |
| AnnaBridge | 165:d1b4690b3f8b | 397 | SCIERI1_IRQn = 351, |
| AnnaBridge | 165:d1b4690b3f8b | 398 | SCIRXI1_IRQn = 352, |
| AnnaBridge | 165:d1b4690b3f8b | 399 | SCITXI1_IRQn = 353, |
| AnnaBridge | 165:d1b4690b3f8b | 400 | SCITEI1_IRQn = 354, |
| AnnaBridge | 165:d1b4690b3f8b | 401 | |
| AnnaBridge | 165:d1b4690b3f8b | 402 | AVBI_DATA = 355, |
| AnnaBridge | 165:d1b4690b3f8b | 403 | AVBI_ERROR = 356, |
| AnnaBridge | 165:d1b4690b3f8b | 404 | AVBI_MANAGE = 357, |
| AnnaBridge | 165:d1b4690b3f8b | 405 | AVBI_MAC = 358, |
| AnnaBridge | 165:d1b4690b3f8b | 406 | |
| AnnaBridge | 165:d1b4690b3f8b | 407 | ETHERI_IRQn = 359, |
| AnnaBridge | 165:d1b4690b3f8b | 408 | |
| AnnaBridge | 165:d1b4690b3f8b | 409 | /* 360-363 Reserved */ |
| AnnaBridge | 165:d1b4690b3f8b | 410 | |
| AnnaBridge | 165:d1b4690b3f8b | 411 | CEUI_IRQn = 364, |
| AnnaBridge | 165:d1b4690b3f8b | 412 | |
| AnnaBridge | 165:d1b4690b3f8b | 413 | /* 365-380 Reserved */ |
| AnnaBridge | 165:d1b4690b3f8b | 414 | |
| AnnaBridge | 165:d1b4690b3f8b | 415 | H2XMLB_ERRINT_IRQn = 381, |
| AnnaBridge | 165:d1b4690b3f8b | 416 | H2XIC1_ERRINT_IRQn = 382, |
| AnnaBridge | 165:d1b4690b3f8b | 417 | X2HPERI1_ERRINT_IRQn = 383, |
| AnnaBridge | 165:d1b4690b3f8b | 418 | X2HPERR2_ERRINT_IRQn = 384, |
| AnnaBridge | 165:d1b4690b3f8b | 419 | X2HPERR34_ERRINT_IRQn= 385, |
| AnnaBridge | 165:d1b4690b3f8b | 420 | X2HPERR5_ERRINT_IRQn = 386, |
| AnnaBridge | 165:d1b4690b3f8b | 421 | X2HPERR67_ERRINT_IRQn= 387, |
| AnnaBridge | 165:d1b4690b3f8b | 422 | X2HDBGR_ERRINT_IRQn = 388, |
| AnnaBridge | 165:d1b4690b3f8b | 423 | X2HBSC_ERRINT_IRQn = 389, |
| AnnaBridge | 165:d1b4690b3f8b | 424 | X2HSPI1_ERRINT_IRQn = 390, |
| AnnaBridge | 165:d1b4690b3f8b | 425 | X2HSPI2_ERRINT_IRQn = 391, |
| AnnaBridge | 165:d1b4690b3f8b | 426 | PRRI_IRQn = 392, |
| AnnaBridge | 165:d1b4690b3f8b | 427 | |
| AnnaBridge | 165:d1b4690b3f8b | 428 | IFEI0_IRQn = 393, |
| AnnaBridge | 165:d1b4690b3f8b | 429 | OFFI0_IRQn = 394, |
| AnnaBridge | 165:d1b4690b3f8b | 430 | PFVEI0_IRQn = 395, |
| AnnaBridge | 165:d1b4690b3f8b | 431 | IFEI1_IRQn = 396, |
| AnnaBridge | 165:d1b4690b3f8b | 432 | OFFI1_IRQn = 397, |
| AnnaBridge | 165:d1b4690b3f8b | 433 | PFVEI1_IRQn = 398, |
| AnnaBridge | 165:d1b4690b3f8b | 434 | |
| AnnaBridge | 165:d1b4690b3f8b | 435 | /* 399-415 Reserved */ |
| AnnaBridge | 165:d1b4690b3f8b | 436 | |
| AnnaBridge | 165:d1b4690b3f8b | 437 | TINT0_IRQn = 416, |
| AnnaBridge | 165:d1b4690b3f8b | 438 | TINT1_IRQn = 417, |
| AnnaBridge | 165:d1b4690b3f8b | 439 | TINT2_IRQn = 418, |
| AnnaBridge | 165:d1b4690b3f8b | 440 | TINT3_IRQn = 419, |
| AnnaBridge | 165:d1b4690b3f8b | 441 | TINT4_IRQn = 420, |
| AnnaBridge | 165:d1b4690b3f8b | 442 | TINT5_IRQn = 421, |
| AnnaBridge | 165:d1b4690b3f8b | 443 | TINT6_IRQn = 422, |
| AnnaBridge | 165:d1b4690b3f8b | 444 | TINT7_IRQn = 423, |
| AnnaBridge | 165:d1b4690b3f8b | 445 | TINT8_IRQn = 424, |
| AnnaBridge | 165:d1b4690b3f8b | 446 | TINT9_IRQn = 425, |
| AnnaBridge | 165:d1b4690b3f8b | 447 | TINT10_IRQn = 426, |
| AnnaBridge | 165:d1b4690b3f8b | 448 | TINT11_IRQn = 427, |
| AnnaBridge | 165:d1b4690b3f8b | 449 | TINT12_IRQn = 428, |
| AnnaBridge | 165:d1b4690b3f8b | 450 | TINT13_IRQn = 429, |
| AnnaBridge | 165:d1b4690b3f8b | 451 | TINT14_IRQn = 430, |
| AnnaBridge | 165:d1b4690b3f8b | 452 | TINT15_IRQn = 431, |
| AnnaBridge | 165:d1b4690b3f8b | 453 | TINT16_IRQn = 432, |
| AnnaBridge | 165:d1b4690b3f8b | 454 | TINT17_IRQn = 433, |
| AnnaBridge | 165:d1b4690b3f8b | 455 | TINT18_IRQn = 434, |
| AnnaBridge | 165:d1b4690b3f8b | 456 | TINT19_IRQn = 435, |
| AnnaBridge | 165:d1b4690b3f8b | 457 | TINT20_IRQn = 436, |
| AnnaBridge | 165:d1b4690b3f8b | 458 | TINT21_IRQn = 437, |
| AnnaBridge | 165:d1b4690b3f8b | 459 | TINT22_IRQn = 438, |
| AnnaBridge | 165:d1b4690b3f8b | 460 | TINT23_IRQn = 439, |
| AnnaBridge | 165:d1b4690b3f8b | 461 | TINT24_IRQn = 440, |
| AnnaBridge | 165:d1b4690b3f8b | 462 | TINT25_IRQn = 441, |
| AnnaBridge | 165:d1b4690b3f8b | 463 | TINT26_IRQn = 442, |
| AnnaBridge | 165:d1b4690b3f8b | 464 | TINT27_IRQn = 443, |
| AnnaBridge | 165:d1b4690b3f8b | 465 | TINT28_IRQn = 444, |
| AnnaBridge | 165:d1b4690b3f8b | 466 | TINT29_IRQn = 445, |
| AnnaBridge | 165:d1b4690b3f8b | 467 | TINT30_IRQn = 446, |
| AnnaBridge | 165:d1b4690b3f8b | 468 | TINT31_IRQn = 447, |
| AnnaBridge | 165:d1b4690b3f8b | 469 | TINT32_IRQn = 448, |
| AnnaBridge | 165:d1b4690b3f8b | 470 | TINT33_IRQn = 449, |
| AnnaBridge | 165:d1b4690b3f8b | 471 | TINT34_IRQn = 450, |
| AnnaBridge | 165:d1b4690b3f8b | 472 | TINT35_IRQn = 451, |
| AnnaBridge | 165:d1b4690b3f8b | 473 | TINT36_IRQn = 452, |
| AnnaBridge | 165:d1b4690b3f8b | 474 | TINT37_IRQn = 453, |
| AnnaBridge | 165:d1b4690b3f8b | 475 | TINT38_IRQn = 454, |
| AnnaBridge | 165:d1b4690b3f8b | 476 | TINT39_IRQn = 455, |
| AnnaBridge | 165:d1b4690b3f8b | 477 | TINT40_IRQn = 456, |
| AnnaBridge | 165:d1b4690b3f8b | 478 | TINT41_IRQn = 457, |
| AnnaBridge | 165:d1b4690b3f8b | 479 | TINT42_IRQn = 458, |
| AnnaBridge | 165:d1b4690b3f8b | 480 | TINT43_IRQn = 459, |
| AnnaBridge | 165:d1b4690b3f8b | 481 | TINT44_IRQn = 460, |
| AnnaBridge | 165:d1b4690b3f8b | 482 | TINT45_IRQn = 461, |
| AnnaBridge | 165:d1b4690b3f8b | 483 | TINT46_IRQn = 462, |
| AnnaBridge | 165:d1b4690b3f8b | 484 | TINT47_IRQn = 463, |
| AnnaBridge | 165:d1b4690b3f8b | 485 | TINT48_IRQn = 464, |
| AnnaBridge | 165:d1b4690b3f8b | 486 | TINT49_IRQn = 465, |
| AnnaBridge | 165:d1b4690b3f8b | 487 | TINT50_IRQn = 466, |
| AnnaBridge | 165:d1b4690b3f8b | 488 | TINT51_IRQn = 467, |
| AnnaBridge | 165:d1b4690b3f8b | 489 | TINT52_IRQn = 468, |
| AnnaBridge | 165:d1b4690b3f8b | 490 | TINT53_IRQn = 469, |
| AnnaBridge | 165:d1b4690b3f8b | 491 | TINT54_IRQn = 470, |
| AnnaBridge | 165:d1b4690b3f8b | 492 | TINT55_IRQn = 471, |
| AnnaBridge | 165:d1b4690b3f8b | 493 | TINT56_IRQn = 472, |
| AnnaBridge | 165:d1b4690b3f8b | 494 | TINT57_IRQn = 473, |
| AnnaBridge | 165:d1b4690b3f8b | 495 | TINT58_IRQn = 474, |
| AnnaBridge | 165:d1b4690b3f8b | 496 | TINT59_IRQn = 475, |
| AnnaBridge | 165:d1b4690b3f8b | 497 | TINT60_IRQn = 476, |
| AnnaBridge | 165:d1b4690b3f8b | 498 | TINT61_IRQn = 477, |
| AnnaBridge | 165:d1b4690b3f8b | 499 | TINT62_IRQn = 478, |
| AnnaBridge | 165:d1b4690b3f8b | 500 | TINT63_IRQn = 479, |
| AnnaBridge | 165:d1b4690b3f8b | 501 | TINT64_IRQn = 480, |
| AnnaBridge | 165:d1b4690b3f8b | 502 | TINT65_IRQn = 481, |
| AnnaBridge | 165:d1b4690b3f8b | 503 | TINT66_IRQn = 482, |
| AnnaBridge | 165:d1b4690b3f8b | 504 | TINT67_IRQn = 483, |
| AnnaBridge | 165:d1b4690b3f8b | 505 | TINT68_IRQn = 484, |
| AnnaBridge | 165:d1b4690b3f8b | 506 | TINT69_IRQn = 485, |
| AnnaBridge | 165:d1b4690b3f8b | 507 | TINT70_IRQn = 486, |
| AnnaBridge | 165:d1b4690b3f8b | 508 | TINT71_IRQn = 487, |
| AnnaBridge | 165:d1b4690b3f8b | 509 | TINT72_IRQn = 488, |
| AnnaBridge | 165:d1b4690b3f8b | 510 | TINT73_IRQn = 489, |
| AnnaBridge | 165:d1b4690b3f8b | 511 | TINT74_IRQn = 490, |
| AnnaBridge | 165:d1b4690b3f8b | 512 | TINT75_IRQn = 491, |
| AnnaBridge | 165:d1b4690b3f8b | 513 | TINT76_IRQn = 492, |
| AnnaBridge | 165:d1b4690b3f8b | 514 | TINT77_IRQn = 493, |
| AnnaBridge | 165:d1b4690b3f8b | 515 | TINT78_IRQn = 494, |
| AnnaBridge | 165:d1b4690b3f8b | 516 | TINT79_IRQn = 495, |
| AnnaBridge | 165:d1b4690b3f8b | 517 | TINT80_IRQn = 496, |
| AnnaBridge | 165:d1b4690b3f8b | 518 | TINT81_IRQn = 497, |
| AnnaBridge | 165:d1b4690b3f8b | 519 | TINT82_IRQn = 498, |
| AnnaBridge | 165:d1b4690b3f8b | 520 | TINT83_IRQn = 499, |
| AnnaBridge | 165:d1b4690b3f8b | 521 | TINT84_IRQn = 500, |
| AnnaBridge | 165:d1b4690b3f8b | 522 | TINT85_IRQn = 501, |
| AnnaBridge | 165:d1b4690b3f8b | 523 | TINT86_IRQn = 502, |
| AnnaBridge | 165:d1b4690b3f8b | 524 | TINT87_IRQn = 503, |
| AnnaBridge | 165:d1b4690b3f8b | 525 | TINT88_IRQn = 504, |
| AnnaBridge | 165:d1b4690b3f8b | 526 | TINT89_IRQn = 505, |
| AnnaBridge | 165:d1b4690b3f8b | 527 | TINT90_IRQn = 506, |
| AnnaBridge | 165:d1b4690b3f8b | 528 | TINT91_IRQn = 507, |
| AnnaBridge | 165:d1b4690b3f8b | 529 | TINT92_IRQn = 508, |
| AnnaBridge | 165:d1b4690b3f8b | 530 | TINT93_IRQn = 509, |
| AnnaBridge | 165:d1b4690b3f8b | 531 | TINT94_IRQn = 510, |
| AnnaBridge | 165:d1b4690b3f8b | 532 | TINT95_IRQn = 511, |
| AnnaBridge | 165:d1b4690b3f8b | 533 | TINT96_IRQn = 512, |
| AnnaBridge | 165:d1b4690b3f8b | 534 | TINT97_IRQn = 513, |
| AnnaBridge | 165:d1b4690b3f8b | 535 | TINT98_IRQn = 514, |
| AnnaBridge | 165:d1b4690b3f8b | 536 | TINT99_IRQn = 515, |
| AnnaBridge | 165:d1b4690b3f8b | 537 | TINT100_IRQn = 516, |
| AnnaBridge | 165:d1b4690b3f8b | 538 | TINT101_IRQn = 517, |
| AnnaBridge | 165:d1b4690b3f8b | 539 | TINT102_IRQn = 518, |
| AnnaBridge | 165:d1b4690b3f8b | 540 | TINT103_IRQn = 519, |
| AnnaBridge | 165:d1b4690b3f8b | 541 | TINT104_IRQn = 520, |
| AnnaBridge | 165:d1b4690b3f8b | 542 | TINT105_IRQn = 521, |
| AnnaBridge | 165:d1b4690b3f8b | 543 | TINT106_IRQn = 522, |
| AnnaBridge | 165:d1b4690b3f8b | 544 | TINT107_IRQn = 523, |
| AnnaBridge | 165:d1b4690b3f8b | 545 | TINT108_IRQn = 524, |
| AnnaBridge | 165:d1b4690b3f8b | 546 | TINT109_IRQn = 525, |
| AnnaBridge | 165:d1b4690b3f8b | 547 | TINT110_IRQn = 526, |
| AnnaBridge | 165:d1b4690b3f8b | 548 | TINT111_IRQn = 527, |
| AnnaBridge | 165:d1b4690b3f8b | 549 | TINT112_IRQn = 528, |
| AnnaBridge | 165:d1b4690b3f8b | 550 | TINT113_IRQn = 529, |
| AnnaBridge | 165:d1b4690b3f8b | 551 | TINT114_IRQn = 530, |
| AnnaBridge | 165:d1b4690b3f8b | 552 | TINT115_IRQn = 531, |
| AnnaBridge | 165:d1b4690b3f8b | 553 | TINT116_IRQn = 532, |
| AnnaBridge | 165:d1b4690b3f8b | 554 | TINT117_IRQn = 533, |
| AnnaBridge | 165:d1b4690b3f8b | 555 | TINT118_IRQn = 534, |
| AnnaBridge | 165:d1b4690b3f8b | 556 | TINT119_IRQn = 535, |
| AnnaBridge | 165:d1b4690b3f8b | 557 | TINT120_IRQn = 536, |
| AnnaBridge | 165:d1b4690b3f8b | 558 | TINT121_IRQn = 537, |
| AnnaBridge | 165:d1b4690b3f8b | 559 | TINT122_IRQn = 538, |
| AnnaBridge | 165:d1b4690b3f8b | 560 | TINT123_IRQn = 539, |
| AnnaBridge | 165:d1b4690b3f8b | 561 | TINT124_IRQn = 540, |
| AnnaBridge | 165:d1b4690b3f8b | 562 | TINT125_IRQn = 541, |
| AnnaBridge | 165:d1b4690b3f8b | 563 | TINT126_IRQn = 542, |
| AnnaBridge | 165:d1b4690b3f8b | 564 | TINT127_IRQn = 543, |
| AnnaBridge | 165:d1b4690b3f8b | 565 | TINT128_IRQn = 544, |
| AnnaBridge | 165:d1b4690b3f8b | 566 | TINT129_IRQn = 545, |
| AnnaBridge | 165:d1b4690b3f8b | 567 | TINT130_IRQn = 546, |
| AnnaBridge | 165:d1b4690b3f8b | 568 | TINT131_IRQn = 547, |
| AnnaBridge | 165:d1b4690b3f8b | 569 | TINT132_IRQn = 548, |
| AnnaBridge | 165:d1b4690b3f8b | 570 | TINT133_IRQn = 549, |
| AnnaBridge | 165:d1b4690b3f8b | 571 | TINT134_IRQn = 550, |
| AnnaBridge | 165:d1b4690b3f8b | 572 | TINT135_IRQn = 551, |
| AnnaBridge | 165:d1b4690b3f8b | 573 | TINT136_IRQn = 552, |
| AnnaBridge | 165:d1b4690b3f8b | 574 | TINT137_IRQn = 553, |
| AnnaBridge | 165:d1b4690b3f8b | 575 | TINT138_IRQn = 554, |
| AnnaBridge | 165:d1b4690b3f8b | 576 | TINT139_IRQn = 555, |
| AnnaBridge | 165:d1b4690b3f8b | 577 | TINT140_IRQn = 556, |
| AnnaBridge | 165:d1b4690b3f8b | 578 | TINT141_IRQn = 557, |
| AnnaBridge | 165:d1b4690b3f8b | 579 | TINT142_IRQn = 558, |
| AnnaBridge | 165:d1b4690b3f8b | 580 | TINT143_IRQn = 559, |
| AnnaBridge | 165:d1b4690b3f8b | 581 | TINT144_IRQn = 560, |
| AnnaBridge | 165:d1b4690b3f8b | 582 | TINT145_IRQn = 561, |
| AnnaBridge | 165:d1b4690b3f8b | 583 | TINT146_IRQn = 562, |
| AnnaBridge | 165:d1b4690b3f8b | 584 | TINT147_IRQn = 563, |
| AnnaBridge | 165:d1b4690b3f8b | 585 | TINT148_IRQn = 564, |
| AnnaBridge | 165:d1b4690b3f8b | 586 | TINT149_IRQn = 565, |
| AnnaBridge | 165:d1b4690b3f8b | 587 | TINT150_IRQn = 566, |
| AnnaBridge | 165:d1b4690b3f8b | 588 | TINT151_IRQn = 567, |
| AnnaBridge | 165:d1b4690b3f8b | 589 | TINT152_IRQn = 568, |
| AnnaBridge | 165:d1b4690b3f8b | 590 | TINT153_IRQn = 569, |
| AnnaBridge | 165:d1b4690b3f8b | 591 | TINT154_IRQn = 570, |
| AnnaBridge | 165:d1b4690b3f8b | 592 | TINT155_IRQn = 571, |
| AnnaBridge | 165:d1b4690b3f8b | 593 | TINT156_IRQn = 572, |
| AnnaBridge | 165:d1b4690b3f8b | 594 | TINT157_IRQn = 573, |
| AnnaBridge | 165:d1b4690b3f8b | 595 | TINT158_IRQn = 574, |
| AnnaBridge | 165:d1b4690b3f8b | 596 | TINT159_IRQn = 575, |
| AnnaBridge | 165:d1b4690b3f8b | 597 | TINT160_IRQn = 576, |
| AnnaBridge | 165:d1b4690b3f8b | 598 | TINT161_IRQn = 577, |
| AnnaBridge | 165:d1b4690b3f8b | 599 | TINT162_IRQn = 578, |
| AnnaBridge | 165:d1b4690b3f8b | 600 | TINT163_IRQn = 579, |
| AnnaBridge | 165:d1b4690b3f8b | 601 | TINT164_IRQn = 580, |
| AnnaBridge | 165:d1b4690b3f8b | 602 | TINT165_IRQn = 581, |
| AnnaBridge | 165:d1b4690b3f8b | 603 | TINT166_IRQn = 582, |
| AnnaBridge | 165:d1b4690b3f8b | 604 | TINT167_IRQn = 583, |
| AnnaBridge | 165:d1b4690b3f8b | 605 | TINT168_IRQn = 584, |
| AnnaBridge | 165:d1b4690b3f8b | 606 | TINT169_IRQn = 585, |
| AnnaBridge | 165:d1b4690b3f8b | 607 | TINT170_IRQn = 586 |
| AnnaBridge | 165:d1b4690b3f8b | 608 | |
| AnnaBridge | 165:d1b4690b3f8b | 609 | } IRQn_Type; |
| AnnaBridge | 165:d1b4690b3f8b | 610 | |
| AnnaBridge | 165:d1b4690b3f8b | 611 | #define RZ_A1_IRQ_MAX TINT170_IRQn |
| AnnaBridge | 165:d1b4690b3f8b | 612 | |
| AnnaBridge | 165:d1b4690b3f8b | 613 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 614 | /* Peripheral memory map */ |
| AnnaBridge | 165:d1b4690b3f8b | 615 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 616 | |
| AnnaBridge | 165:d1b4690b3f8b | 617 | #define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 618 | #define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 619 | #define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 620 | #define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 621 | #define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 622 | #define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 623 | #define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 624 | #define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 625 | #define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 626 | #define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 627 | #define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 628 | #define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 629 | #define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 630 | #define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 631 | #define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 632 | #define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 633 | #define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 634 | #define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */ |
| AnnaBridge | 165:d1b4690b3f8b | 635 | #define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE |
| AnnaBridge | 165:d1b4690b3f8b | 636 | #define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE |
| AnnaBridge | 165:d1b4690b3f8b | 637 | #define L2C_310_BASE RZ_A1_PL310_BASE |
| AnnaBridge | 165:d1b4690b3f8b | 638 | #define TIMER_BASE RZ_A1_PRIVATE_TIMER |
| AnnaBridge | 165:d1b4690b3f8b | 639 | |
| AnnaBridge | 165:d1b4690b3f8b | 640 | /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ |
| AnnaBridge | 165:d1b4690b3f8b | 641 | #define __CA_REV 0x0000U /*!< Core revision r0p0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 642 | #define __CORTEX_A 9U /*!< Cortex-A9 Core */ |
| AnnaBridge | 165:d1b4690b3f8b | 643 | #if (__FPU_PRESENT != 1) |
| AnnaBridge | 165:d1b4690b3f8b | 644 | #undef __FPU_PRESENT |
| AnnaBridge | 165:d1b4690b3f8b | 645 | #define __FPU_PRESENT 1U /* FPU present */ |
| AnnaBridge | 165:d1b4690b3f8b | 646 | #endif |
| AnnaBridge | 165:d1b4690b3f8b | 647 | #define __GIC_PRESENT 1U /* GIC present */ |
| AnnaBridge | 165:d1b4690b3f8b | 648 | #define __TIM_PRESENT 0U /* TIM present */ |
| AnnaBridge | 165:d1b4690b3f8b | 649 | #define __L2C_PRESENT 1U /* L2C present */ |
| AnnaBridge | 165:d1b4690b3f8b | 650 | |
| AnnaBridge | 165:d1b4690b3f8b | 651 | #include "core_ca.h" |
| AnnaBridge | 165:d1b4690b3f8b | 652 | #include "nvic_wrapper.h" |
| AnnaBridge | 165:d1b4690b3f8b | 653 | #include <system_VK_RZ_A1H.h> |
| AnnaBridge | 165:d1b4690b3f8b | 654 | #include "iodefine.h" |
| AnnaBridge | 165:d1b4690b3f8b | 655 | |
| AnnaBridge | 165:d1b4690b3f8b | 656 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 657 | /* Clock Settings */ |
| AnnaBridge | 165:d1b4690b3f8b | 658 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 659 | /* |
| AnnaBridge | 165:d1b4690b3f8b | 660 | * Clock Mode 0 settings |
| AnnaBridge | 165:d1b4690b3f8b | 661 | * SW1-4(MD_CLK):ON |
| AnnaBridge | 165:d1b4690b3f8b | 662 | * SW1-5(MD_CLKS):ON |
| AnnaBridge | 165:d1b4690b3f8b | 663 | * FRQCR=0x1035 |
| AnnaBridge | 165:d1b4690b3f8b | 664 | * CLKEN2 = 0b - unstable |
| AnnaBridge | 165:d1b4690b3f8b | 665 | * CLKEN[1:0]=01b - Output, Low, Low |
| AnnaBridge | 165:d1b4690b3f8b | 666 | * IFC[1:0] =00b - CPU clock is 1/1 PLL clock |
| AnnaBridge | 165:d1b4690b3f8b | 667 | * FRQCR2=0x0001 |
| AnnaBridge | 165:d1b4690b3f8b | 668 | * GFC[1:0] =01b - Graphic clock is 2/3 bus clock |
| AnnaBridge | 165:d1b4690b3f8b | 669 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 670 | #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) |
| AnnaBridge | 165:d1b4690b3f8b | 671 | #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) |
| AnnaBridge | 165:d1b4690b3f8b | 672 | #define CM0_RENESAS_RZ_A1_I_CLK (400000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 673 | #define CM0_RENESAS_RZ_A1_G_CLK (266666666u) |
| AnnaBridge | 165:d1b4690b3f8b | 674 | #define CM0_RENESAS_RZ_A1_B_CLK (133333333u) |
| AnnaBridge | 165:d1b4690b3f8b | 675 | #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) |
| AnnaBridge | 165:d1b4690b3f8b | 676 | #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) |
| AnnaBridge | 165:d1b4690b3f8b | 677 | |
| AnnaBridge | 165:d1b4690b3f8b | 678 | /* |
| AnnaBridge | 165:d1b4690b3f8b | 679 | * Clock Mode 1 settings |
| AnnaBridge | 165:d1b4690b3f8b | 680 | * SW1-4(MD_CLK):OFF |
| AnnaBridge | 165:d1b4690b3f8b | 681 | * SW1-5(MD_CLKS):ON |
| AnnaBridge | 165:d1b4690b3f8b | 682 | * FRQCR=0x1335 |
| AnnaBridge | 165:d1b4690b3f8b | 683 | * CLKEN2 = 0b - unstable |
| AnnaBridge | 165:d1b4690b3f8b | 684 | * CLKEN[1:0]=01b - Output, Low, Low |
| AnnaBridge | 165:d1b4690b3f8b | 685 | * IFC[1:0] =11b - CPU clock is 1/3 PLL clock |
| AnnaBridge | 165:d1b4690b3f8b | 686 | * FRQCR2=0x0003 |
| AnnaBridge | 165:d1b4690b3f8b | 687 | * GFC[1:0] =11b - graphic clock is 1/3 bus clock |
| AnnaBridge | 165:d1b4690b3f8b | 688 | */ |
| AnnaBridge | 165:d1b4690b3f8b | 689 | #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 690 | #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 691 | #define CM1_RENESAS_RZ_A1_I_CLK (128000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 692 | #define CM1_RENESAS_RZ_A1_G_CLK (128000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 693 | #define CM1_RENESAS_RZ_A1_B_CLK (128000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 694 | #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 695 | #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) |
| AnnaBridge | 165:d1b4690b3f8b | 696 | |
| AnnaBridge | 165:d1b4690b3f8b | 697 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 698 | /* CPG Settings */ |
| AnnaBridge | 165:d1b4690b3f8b | 699 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 700 | #define CPG_FRQCR_SHIFT_CKOEN2 (14) |
| AnnaBridge | 165:d1b4690b3f8b | 701 | #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) |
| AnnaBridge | 165:d1b4690b3f8b | 702 | #define CPG_FRQCR_SHIFT_CKOEN0 (12) |
| AnnaBridge | 165:d1b4690b3f8b | 703 | #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) |
| AnnaBridge | 165:d1b4690b3f8b | 704 | #define CPG_FRQCR_SHIFT_IFC (8) |
| AnnaBridge | 165:d1b4690b3f8b | 705 | #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) |
| AnnaBridge | 165:d1b4690b3f8b | 706 | |
| AnnaBridge | 165:d1b4690b3f8b | 707 | #define CPG_FRQCR2_SHIFT_GFC (0) |
| AnnaBridge | 165:d1b4690b3f8b | 708 | #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) |
| AnnaBridge | 165:d1b4690b3f8b | 709 | |
| AnnaBridge | 165:d1b4690b3f8b | 710 | |
| AnnaBridge | 165:d1b4690b3f8b | 711 | #define CPG_STBCR1_BIT_STBY (0x80u) |
| AnnaBridge | 165:d1b4690b3f8b | 712 | #define CPG_STBCR1_BIT_DEEP (0x40u) |
| AnnaBridge | 165:d1b4690b3f8b | 713 | #define CPG_STBCR2_BIT_HIZ (0x80u) |
| AnnaBridge | 165:d1b4690b3f8b | 714 | #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ |
| AnnaBridge | 165:d1b4690b3f8b | 715 | #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ |
| AnnaBridge | 165:d1b4690b3f8b | 716 | #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ |
| AnnaBridge | 165:d1b4690b3f8b | 717 | #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 718 | #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 719 | #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ |
| AnnaBridge | 165:d1b4690b3f8b | 720 | #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ |
| AnnaBridge | 165:d1b4690b3f8b | 721 | #define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */ |
| AnnaBridge | 165:d1b4690b3f8b | 722 | #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ |
| AnnaBridge | 165:d1b4690b3f8b | 723 | #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 724 | #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 725 | #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 726 | #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 727 | #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 728 | #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ |
| AnnaBridge | 165:d1b4690b3f8b | 729 | #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ |
| AnnaBridge | 165:d1b4690b3f8b | 730 | #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ |
| AnnaBridge | 165:d1b4690b3f8b | 731 | #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 732 | #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 733 | #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 734 | #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 735 | #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 736 | #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 737 | #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 738 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 739 | #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */ |
| AnnaBridge | 165:d1b4690b3f8b | 740 | #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ |
| AnnaBridge | 165:d1b4690b3f8b | 741 | #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 742 | #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 743 | #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 744 | #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 745 | #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ |
| AnnaBridge | 165:d1b4690b3f8b | 746 | #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ |
| AnnaBridge | 165:d1b4690b3f8b | 747 | #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 748 | #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 749 | #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */ |
| AnnaBridge | 165:d1b4690b3f8b | 750 | #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ |
| AnnaBridge | 165:d1b4690b3f8b | 751 | #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 752 | #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 753 | #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 754 | #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 755 | #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ |
| AnnaBridge | 165:d1b4690b3f8b | 756 | #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ |
| AnnaBridge | 165:d1b4690b3f8b | 757 | #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ |
| AnnaBridge | 165:d1b4690b3f8b | 758 | #define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */ |
| AnnaBridge | 165:d1b4690b3f8b | 759 | #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ |
| AnnaBridge | 165:d1b4690b3f8b | 760 | #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 761 | #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 762 | #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 763 | #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 764 | #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 765 | #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 766 | #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 767 | #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 768 | #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 769 | #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 770 | #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 771 | #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 772 | #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 773 | #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ |
| AnnaBridge | 165:d1b4690b3f8b | 774 | #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ |
| AnnaBridge | 165:d1b4690b3f8b | 775 | #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ |
| AnnaBridge | 165:d1b4690b3f8b | 776 | #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 777 | #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 778 | #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 779 | #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 780 | #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 781 | #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ |
| AnnaBridge | 165:d1b4690b3f8b | 782 | #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ |
| AnnaBridge | 165:d1b4690b3f8b | 783 | #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ |
| AnnaBridge | 165:d1b4690b3f8b | 784 | #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ |
| AnnaBridge | 165:d1b4690b3f8b | 785 | #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ |
| AnnaBridge | 165:d1b4690b3f8b | 786 | #define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 787 | #define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 788 | #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 789 | #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 790 | #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 791 | #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 792 | #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 793 | #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 794 | #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ |
| AnnaBridge | 165:d1b4690b3f8b | 795 | #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ |
| AnnaBridge | 165:d1b4690b3f8b | 796 | #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ |
| AnnaBridge | 165:d1b4690b3f8b | 797 | #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 798 | #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 799 | #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 800 | #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 801 | #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 802 | #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 803 | #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 804 | #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 805 | #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 806 | #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 807 | #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 808 | #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 809 | #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 810 | #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 811 | #define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */ |
| AnnaBridge | 165:d1b4690b3f8b | 812 | #define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */ |
| AnnaBridge | 165:d1b4690b3f8b | 813 | #define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */ |
| AnnaBridge | 165:d1b4690b3f8b | 814 | #define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */ |
| AnnaBridge | 165:d1b4690b3f8b | 815 | #define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */ |
| AnnaBridge | 165:d1b4690b3f8b | 816 | #define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */ |
| AnnaBridge | 165:d1b4690b3f8b | 817 | #define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */ |
| AnnaBridge | 165:d1b4690b3f8b | 818 | #define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 819 | #define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 820 | #define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 821 | #define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 822 | #define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */ |
| AnnaBridge | 165:d1b4690b3f8b | 823 | #define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */ |
| AnnaBridge | 165:d1b4690b3f8b | 824 | #define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */ |
| AnnaBridge | 165:d1b4690b3f8b | 825 | #define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */ |
| AnnaBridge | 165:d1b4690b3f8b | 826 | #define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */ |
| AnnaBridge | 165:d1b4690b3f8b | 827 | #define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */ |
| AnnaBridge | 165:d1b4690b3f8b | 828 | #define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */ |
| AnnaBridge | 165:d1b4690b3f8b | 829 | #define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */ |
| AnnaBridge | 165:d1b4690b3f8b | 830 | #define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 831 | #define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 832 | #define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 833 | #define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 834 | #define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */ |
| AnnaBridge | 165:d1b4690b3f8b | 835 | #define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */ |
| AnnaBridge | 165:d1b4690b3f8b | 836 | #define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 837 | #define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 838 | #define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 839 | #define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */ |
| AnnaBridge | 165:d1b4690b3f8b | 840 | #define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */ |
| AnnaBridge | 165:d1b4690b3f8b | 841 | #define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */ |
| AnnaBridge | 165:d1b4690b3f8b | 842 | #define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 843 | #define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */ |
| AnnaBridge | 165:d1b4690b3f8b | 844 | #define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 845 | #define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */ |
| AnnaBridge | 165:d1b4690b3f8b | 846 | #define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */ |
| AnnaBridge | 165:d1b4690b3f8b | 847 | #define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 848 | #define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */ |
| AnnaBridge | 165:d1b4690b3f8b | 849 | #define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */ |
| AnnaBridge | 165:d1b4690b3f8b | 850 | #define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 851 | #define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */ |
| AnnaBridge | 165:d1b4690b3f8b | 852 | #define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */ |
| AnnaBridge | 165:d1b4690b3f8b | 853 | #define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */ |
| AnnaBridge | 165:d1b4690b3f8b | 854 | #define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 855 | #define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 856 | #define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 857 | #define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */ |
| AnnaBridge | 165:d1b4690b3f8b | 858 | #define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 859 | #define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */ |
| AnnaBridge | 165:d1b4690b3f8b | 860 | #define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */ |
| AnnaBridge | 165:d1b4690b3f8b | 861 | #define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 862 | #define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */ |
| AnnaBridge | 165:d1b4690b3f8b | 863 | #define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 864 | #define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */ |
| AnnaBridge | 165:d1b4690b3f8b | 865 | #define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */ |
| AnnaBridge | 165:d1b4690b3f8b | 866 | #define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */ |
| AnnaBridge | 165:d1b4690b3f8b | 867 | #define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 868 | #define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 869 | #define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */ |
| AnnaBridge | 165:d1b4690b3f8b | 870 | #define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 871 | #define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */ |
| AnnaBridge | 165:d1b4690b3f8b | 872 | #define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 873 | #define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */ |
| AnnaBridge | 165:d1b4690b3f8b | 874 | #define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */ |
| AnnaBridge | 165:d1b4690b3f8b | 875 | #define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */ |
| AnnaBridge | 165:d1b4690b3f8b | 876 | #define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */ |
| AnnaBridge | 165:d1b4690b3f8b | 877 | #define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */ |
| AnnaBridge | 165:d1b4690b3f8b | 878 | #define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 879 | #define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */ |
| AnnaBridge | 165:d1b4690b3f8b | 880 | #define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */ |
| AnnaBridge | 165:d1b4690b3f8b | 881 | #define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */ |
| AnnaBridge | 165:d1b4690b3f8b | 882 | #define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */ |
| AnnaBridge | 165:d1b4690b3f8b | 883 | #define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */ |
| AnnaBridge | 165:d1b4690b3f8b | 884 | #define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */ |
| AnnaBridge | 165:d1b4690b3f8b | 885 | #define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */ |
| AnnaBridge | 165:d1b4690b3f8b | 886 | |
| AnnaBridge | 165:d1b4690b3f8b | 887 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 888 | /* GPIO Settings */ |
| AnnaBridge | 165:d1b4690b3f8b | 889 | /******************************************************************************/ |
| AnnaBridge | 165:d1b4690b3f8b | 890 | #define GPIO_BIT_N0 (1u << 0) |
| AnnaBridge | 165:d1b4690b3f8b | 891 | #define GPIO_BIT_N1 (1u << 1) |
| AnnaBridge | 165:d1b4690b3f8b | 892 | #define GPIO_BIT_N2 (1u << 2) |
| AnnaBridge | 165:d1b4690b3f8b | 893 | #define GPIO_BIT_N3 (1u << 3) |
| AnnaBridge | 165:d1b4690b3f8b | 894 | #define GPIO_BIT_N4 (1u << 4) |
| AnnaBridge | 165:d1b4690b3f8b | 895 | #define GPIO_BIT_N5 (1u << 5) |
| AnnaBridge | 165:d1b4690b3f8b | 896 | #define GPIO_BIT_N6 (1u << 6) |
| AnnaBridge | 165:d1b4690b3f8b | 897 | #define GPIO_BIT_N7 (1u << 7) |
| AnnaBridge | 165:d1b4690b3f8b | 898 | #define GPIO_BIT_N8 (1u << 8) |
| AnnaBridge | 165:d1b4690b3f8b | 899 | #define GPIO_BIT_N9 (1u << 9) |
| AnnaBridge | 165:d1b4690b3f8b | 900 | #define GPIO_BIT_N10 (1u << 10) |
| AnnaBridge | 165:d1b4690b3f8b | 901 | #define GPIO_BIT_N11 (1u << 11) |
| AnnaBridge | 165:d1b4690b3f8b | 902 | #define GPIO_BIT_N12 (1u << 12) |
| AnnaBridge | 165:d1b4690b3f8b | 903 | #define GPIO_BIT_N13 (1u << 13) |
| AnnaBridge | 165:d1b4690b3f8b | 904 | #define GPIO_BIT_N14 (1u << 14) |
| AnnaBridge | 165:d1b4690b3f8b | 905 | #define GPIO_BIT_N15 (1u << 15) |
| AnnaBridge | 165:d1b4690b3f8b | 906 | |
| AnnaBridge | 165:d1b4690b3f8b | 907 | #define MD_BOOT10_MASK (0x3) |
| AnnaBridge | 165:d1b4690b3f8b | 908 | |
| AnnaBridge | 165:d1b4690b3f8b | 909 | #define MD_BOOT10_BM0 (0x0) |
| AnnaBridge | 165:d1b4690b3f8b | 910 | #define MD_BOOT10_BM1 (0x2) |
| AnnaBridge | 165:d1b4690b3f8b | 911 | #define MD_BOOT10_BM3 (0x1) |
| AnnaBridge | 165:d1b4690b3f8b | 912 | #define MD_BOOT10_BM4_5 (0x3) |
| AnnaBridge | 165:d1b4690b3f8b | 913 | |
| AnnaBridge | 165:d1b4690b3f8b | 914 | #define MD_CLK (1u << 2) |
| AnnaBridge | 165:d1b4690b3f8b | 915 | #define MD_CLKS (1u << 3) |
| AnnaBridge | 165:d1b4690b3f8b | 916 | |
| AnnaBridge | 165:d1b4690b3f8b | 917 | |
| AnnaBridge | 165:d1b4690b3f8b | 918 | #ifdef __cplusplus |
| AnnaBridge | 165:d1b4690b3f8b | 919 | } |
| AnnaBridge | 165:d1b4690b3f8b | 920 | #endif |
| AnnaBridge | 165:d1b4690b3f8b | 921 | |
| AnnaBridge | 165:d1b4690b3f8b | 922 | #endif // __VK_RZ_A1H_H__ |
