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TARGET_VBLUNO51/TOOLCHAIN_IAR/nrf52_bitfields.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /*
AnnaBridge 143:86740a56073b 2 * Copyright (c) 2015 Nordic Semiconductor ASA
AnnaBridge 143:86740a56073b 3 * All rights reserved.
AnnaBridge 143:86740a56073b 4 *
AnnaBridge 143:86740a56073b 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 6 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 7 *
AnnaBridge 143:86740a56073b 8 * 1. Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 143:86740a56073b 9 * of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 10 *
AnnaBridge 143:86740a56073b 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
AnnaBridge 143:86740a56073b 12 * integrated circuit in a product or a software update for such product, must reproduce
AnnaBridge 143:86740a56073b 13 * the above copyright notice, this list of conditions and the following disclaimer in
AnnaBridge 143:86740a56073b 14 * the documentation and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 15 *
AnnaBridge 143:86740a56073b 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
AnnaBridge 143:86740a56073b 17 * used to endorse or promote products derived from this software without specific prior
AnnaBridge 143:86740a56073b 18 * written permission.
AnnaBridge 143:86740a56073b 19 *
AnnaBridge 143:86740a56073b 20 * 4. This software, with or without modification, must only be used with a
AnnaBridge 143:86740a56073b 21 * Nordic Semiconductor ASA integrated circuit.
AnnaBridge 143:86740a56073b 22 *
AnnaBridge 143:86740a56073b 23 * 5. Any software provided in binary or object form under this license must not be reverse
AnnaBridge 143:86740a56073b 24 * engineered, decompiled, modified and/or disassembled.
AnnaBridge 143:86740a56073b 25 *
AnnaBridge 143:86740a56073b 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 143:86740a56073b 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 143:86740a56073b 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 143:86740a56073b 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 143:86740a56073b 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 143:86740a56073b 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 143:86740a56073b 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 143:86740a56073b 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 143:86740a56073b 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 36 *
AnnaBridge 143:86740a56073b 37 */
AnnaBridge 143:86740a56073b 38
AnnaBridge 143:86740a56073b 39 #ifndef __NRF52_BITS_H
AnnaBridge 143:86740a56073b 40 #define __NRF52_BITS_H
AnnaBridge 143:86740a56073b 41
AnnaBridge 143:86740a56073b 42 /*lint ++flb "Enter library region" */
AnnaBridge 143:86740a56073b 43
AnnaBridge 143:86740a56073b 44 /* Peripheral: AAR */
AnnaBridge 143:86740a56073b 45 /* Description: Accelerated Address Resolver */
AnnaBridge 143:86740a56073b 46
AnnaBridge 143:86740a56073b 47 /* Register: AAR_INTENSET */
AnnaBridge 143:86740a56073b 48 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 49
AnnaBridge 143:86740a56073b 50 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
AnnaBridge 143:86740a56073b 51 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 52 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 53 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 54 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 55 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 56
AnnaBridge 143:86740a56073b 57 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
AnnaBridge 143:86740a56073b 58 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
AnnaBridge 143:86740a56073b 59 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
AnnaBridge 143:86740a56073b 60 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 61 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 62 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 63
AnnaBridge 143:86740a56073b 64 /* Bit 0 : Write '1' to Enable interrupt for END event */
AnnaBridge 143:86740a56073b 65 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 66 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 67 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 68 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 69 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 70
AnnaBridge 143:86740a56073b 71 /* Register: AAR_INTENCLR */
AnnaBridge 143:86740a56073b 72 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 73
AnnaBridge 143:86740a56073b 74 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
AnnaBridge 143:86740a56073b 75 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 76 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 77 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 78 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 79 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 80
AnnaBridge 143:86740a56073b 81 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
AnnaBridge 143:86740a56073b 82 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
AnnaBridge 143:86740a56073b 83 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
AnnaBridge 143:86740a56073b 84 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 85 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 86 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 87
AnnaBridge 143:86740a56073b 88 /* Bit 0 : Write '1' to Disable interrupt for END event */
AnnaBridge 143:86740a56073b 89 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 90 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 91 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 92 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 93 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 94
AnnaBridge 143:86740a56073b 95 /* Register: AAR_STATUS */
AnnaBridge 143:86740a56073b 96 /* Description: Resolution status */
AnnaBridge 143:86740a56073b 97
AnnaBridge 143:86740a56073b 98 /* Bits 3..0 : The IRK that was used last time an address was resolved */
AnnaBridge 143:86740a56073b 99 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
AnnaBridge 143:86740a56073b 100 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
AnnaBridge 143:86740a56073b 101
AnnaBridge 143:86740a56073b 102 /* Register: AAR_ENABLE */
AnnaBridge 143:86740a56073b 103 /* Description: Enable AAR */
AnnaBridge 143:86740a56073b 104
AnnaBridge 143:86740a56073b 105 /* Bits 1..0 : Enable or disable AAR */
AnnaBridge 143:86740a56073b 106 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 107 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 108 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 109 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
AnnaBridge 143:86740a56073b 110
AnnaBridge 143:86740a56073b 111 /* Register: AAR_NIRK */
AnnaBridge 143:86740a56073b 112 /* Description: Number of IRKs */
AnnaBridge 143:86740a56073b 113
AnnaBridge 143:86740a56073b 114 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
AnnaBridge 143:86740a56073b 115 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
AnnaBridge 143:86740a56073b 116 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
AnnaBridge 143:86740a56073b 117
AnnaBridge 143:86740a56073b 118 /* Register: AAR_IRKPTR */
AnnaBridge 143:86740a56073b 119 /* Description: Pointer to IRK data structure */
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 /* Bits 31..0 : Pointer to the IRK data structure */
AnnaBridge 143:86740a56073b 122 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
AnnaBridge 143:86740a56073b 123 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
AnnaBridge 143:86740a56073b 124
AnnaBridge 143:86740a56073b 125 /* Register: AAR_ADDRPTR */
AnnaBridge 143:86740a56073b 126 /* Description: Pointer to the resolvable address */
AnnaBridge 143:86740a56073b 127
AnnaBridge 143:86740a56073b 128 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
AnnaBridge 143:86740a56073b 129 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
AnnaBridge 143:86740a56073b 130 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
AnnaBridge 143:86740a56073b 131
AnnaBridge 143:86740a56073b 132 /* Register: AAR_SCRATCHPTR */
AnnaBridge 143:86740a56073b 133 /* Description: Pointer to data area used for temporary storage */
AnnaBridge 143:86740a56073b 134
AnnaBridge 143:86740a56073b 135 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
AnnaBridge 143:86740a56073b 136 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
AnnaBridge 143:86740a56073b 137 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
AnnaBridge 143:86740a56073b 138
AnnaBridge 143:86740a56073b 139
AnnaBridge 143:86740a56073b 140 /* Peripheral: AMLI */
AnnaBridge 143:86740a56073b 141 /* Description: AHB Multi-Layer Interface */
AnnaBridge 143:86740a56073b 142
AnnaBridge 143:86740a56073b 143 /* Register: AMLI_RAMPRI_CPU0 */
AnnaBridge 143:86740a56073b 144 /* Description: AHB bus master priority register for CPU0 */
AnnaBridge 143:86740a56073b 145
AnnaBridge 143:86740a56073b 146 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 147 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 148 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 149 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 150 #define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 151 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 152 #define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 153 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 154 #define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 155 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 156 #define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 157 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 158 #define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 159 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 160 #define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 161 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 162 #define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 163 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 164 #define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 165
AnnaBridge 143:86740a56073b 166 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 167 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 168 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 169 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 170 #define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 171 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 172 #define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 173 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 174 #define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 175 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 176 #define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 177 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 178 #define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 179 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 180 #define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 181 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 182 #define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 183 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 184 #define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 185
AnnaBridge 143:86740a56073b 186 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 187 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 188 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 189 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 190 #define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 191 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 192 #define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 193 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 194 #define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 195 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 196 #define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 197 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 198 #define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 199 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 200 #define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 201 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 202 #define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 203 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 204 #define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 205
AnnaBridge 143:86740a56073b 206 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 207 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 208 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 209 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 210 #define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 211 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 212 #define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 213 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 214 #define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 215 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 216 #define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 217 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 218 #define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 219 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 220 #define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 221 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 222 #define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 223 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 224 #define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 225
AnnaBridge 143:86740a56073b 226 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 227 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 228 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 229 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 230 #define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 231 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 232 #define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 233 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 234 #define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 235 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 236 #define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 237 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 238 #define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 239 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 240 #define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 241 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 242 #define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 243 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 244 #define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 245
AnnaBridge 143:86740a56073b 246 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 247 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 248 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 249 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 250 #define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 251 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 252 #define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 253 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 254 #define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 255 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 256 #define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 257 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 258 #define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 259 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 260 #define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 261 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 262 #define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 263 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 264 #define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 265
AnnaBridge 143:86740a56073b 266 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 267 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 268 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 269 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 270 #define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 271 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 272 #define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 273 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 274 #define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 275 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 276 #define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 277 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 278 #define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 279 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 280 #define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 281 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 282 #define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 283 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 284 #define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 285
AnnaBridge 143:86740a56073b 286 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 287 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 288 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 289 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 290 #define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 291 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 292 #define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 293 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 294 #define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 295 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 296 #define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 297 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 298 #define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 299 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 300 #define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 301 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 302 #define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 303 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 304 #define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 305
AnnaBridge 143:86740a56073b 306 /* Register: AMLI_RAMPRI_SPIS1 */
AnnaBridge 143:86740a56073b 307 /* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */
AnnaBridge 143:86740a56073b 308
AnnaBridge 143:86740a56073b 309 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 310 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 311 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 312 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 313 #define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 314 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 315 #define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 316 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 317 #define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 318 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 319 #define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 320 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 321 #define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 322 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 323 #define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 324 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 325 #define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 326 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 327 #define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 328
AnnaBridge 143:86740a56073b 329 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 330 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 331 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 332 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 333 #define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 334 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 335 #define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 336 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 337 #define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 338 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 339 #define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 340 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 341 #define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 342 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 343 #define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 344 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 345 #define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 346 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 347 #define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 348
AnnaBridge 143:86740a56073b 349 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 350 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 351 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 352 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 353 #define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 354 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 355 #define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 356 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 357 #define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 359 #define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 366 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 367 #define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 368
AnnaBridge 143:86740a56073b 369 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 371 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 379 #define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 380 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 381 #define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 382 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 383 #define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 384 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 385 #define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 386 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 387 #define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 388
AnnaBridge 143:86740a56073b 389 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 390 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 391 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 392 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 393 #define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 394 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 395 #define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 396 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 397 #define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 398 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 399 #define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 400 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 401 #define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 402 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 403 #define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 404 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 405 #define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 406 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 407 #define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 408
AnnaBridge 143:86740a56073b 409 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 410 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 411 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 412 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 413 #define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 414 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 415 #define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 416 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 417 #define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 418 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 419 #define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 420 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 421 #define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 422 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 423 #define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 424 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 425 #define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 426 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 427 #define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 428
AnnaBridge 143:86740a56073b 429 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 430 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 431 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 432 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 433 #define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 434 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 435 #define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 436 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 437 #define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 438 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 439 #define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 440 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 441 #define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 442 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 443 #define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 444 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 445 #define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 446 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 447 #define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 448
AnnaBridge 143:86740a56073b 449 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 450 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 451 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 452 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 453 #define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 454 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 455 #define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 456 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 457 #define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 458 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 459 #define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 460 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 461 #define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 462 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 463 #define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 464 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 465 #define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 466 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 467 #define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 468
AnnaBridge 143:86740a56073b 469 /* Register: AMLI_RAMPRI_RADIO */
AnnaBridge 143:86740a56073b 470 /* Description: AHB bus master priority register for RADIO */
AnnaBridge 143:86740a56073b 471
AnnaBridge 143:86740a56073b 472 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 473 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 474 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 475 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 476 #define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 477 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 478 #define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 479 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 480 #define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 481 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 482 #define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 483 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 484 #define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 485 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 486 #define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 487 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 488 #define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 489 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 490 #define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 491
AnnaBridge 143:86740a56073b 492 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 493 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 494 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 495 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 496 #define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 497 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 498 #define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 499 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 500 #define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 501 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 502 #define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 503 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 504 #define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 505 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 506 #define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 507 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 508 #define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 509 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 510 #define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 511
AnnaBridge 143:86740a56073b 512 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 513 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 514 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 515 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 516 #define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 517 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 518 #define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 519 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 520 #define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 521 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 522 #define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 523 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 524 #define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 525 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 526 #define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 527 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 528 #define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 529 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 530 #define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 531
AnnaBridge 143:86740a56073b 532 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 533 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 534 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 535 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 536 #define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 537 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 538 #define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 539 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 540 #define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 541 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 542 #define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 543 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 544 #define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 545 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 546 #define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 547 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 548 #define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 549 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 550 #define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 551
AnnaBridge 143:86740a56073b 552 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 553 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 554 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 555 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 556 #define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 557 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 558 #define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 559 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 560 #define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 561 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 562 #define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 563 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 564 #define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 565 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 566 #define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 567 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 568 #define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 569 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 570 #define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 571
AnnaBridge 143:86740a56073b 572 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 573 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 574 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 575 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 576 #define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 577 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 578 #define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 579 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 580 #define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 581 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 582 #define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 583 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 584 #define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 585 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 586 #define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 587 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 588 #define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 589 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 590 #define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 591
AnnaBridge 143:86740a56073b 592 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 593 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 594 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 595 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 596 #define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 597 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 598 #define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 599 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 600 #define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 601 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 602 #define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 603 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 604 #define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 605 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 606 #define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 607 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 608 #define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 609 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 610 #define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 611
AnnaBridge 143:86740a56073b 612 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 613 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 614 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 615 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 616 #define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 617 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 618 #define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 619 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 620 #define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 621 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 622 #define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 623 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 624 #define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 625 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 626 #define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 627 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 628 #define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 629 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 630 #define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 631
AnnaBridge 143:86740a56073b 632 /* Register: AMLI_RAMPRI_ECB */
AnnaBridge 143:86740a56073b 633 /* Description: AHB bus master priority register for ECB */
AnnaBridge 143:86740a56073b 634
AnnaBridge 143:86740a56073b 635 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 636 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 637 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 638 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 639 #define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 640 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 641 #define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 642 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 643 #define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 644 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 645 #define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 646 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 647 #define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 648 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 649 #define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 650 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 651 #define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 652 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 653 #define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 654
AnnaBridge 143:86740a56073b 655 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 656 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 657 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 658 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 659 #define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 660 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 661 #define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 662 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 663 #define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 664 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 665 #define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 666 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 667 #define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 668 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 669 #define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 670 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 671 #define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 672 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 673 #define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 674
AnnaBridge 143:86740a56073b 675 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 676 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 677 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 678 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 679 #define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 680 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 681 #define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 682 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 683 #define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 684 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 685 #define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 686 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 687 #define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 688 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 689 #define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 690 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 691 #define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 692 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 693 #define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 694
AnnaBridge 143:86740a56073b 695 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 696 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 697 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 698 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 699 #define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 700 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 701 #define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 702 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 703 #define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 704 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 705 #define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 706 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 707 #define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 708 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 709 #define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 710 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 711 #define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 712 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 713 #define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 714
AnnaBridge 143:86740a56073b 715 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 716 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 717 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 718 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 719 #define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 720 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 721 #define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 722 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 723 #define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 724 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 725 #define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 726 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 727 #define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 728 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 729 #define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 730 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 731 #define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 732 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 733 #define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 734
AnnaBridge 143:86740a56073b 735 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 736 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 737 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 738 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 739 #define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 740 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 741 #define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 742 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 743 #define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 744 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 745 #define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 746 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 747 #define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 748 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 749 #define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 750 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 751 #define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 752 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 753 #define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 754
AnnaBridge 143:86740a56073b 755 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 756 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 757 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 758 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 759 #define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 760 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 761 #define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 762 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 763 #define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 764 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 765 #define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 766 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 767 #define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 768 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 769 #define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 770 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 771 #define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 772 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 773 #define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 774
AnnaBridge 143:86740a56073b 775 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 776 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 777 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 778 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 779 #define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 780 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 781 #define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 782 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 783 #define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 784 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 785 #define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 786 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 787 #define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 788 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 789 #define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 790 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 791 #define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 792 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 793 #define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 794
AnnaBridge 143:86740a56073b 795 /* Register: AMLI_RAMPRI_CCM */
AnnaBridge 143:86740a56073b 796 /* Description: AHB bus master priority register for CCM */
AnnaBridge 143:86740a56073b 797
AnnaBridge 143:86740a56073b 798 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 799 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 800 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 801 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 802 #define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 803 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 804 #define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 805 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 806 #define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 807 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 808 #define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 809 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 810 #define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 811 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 812 #define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 813 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 814 #define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 815 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 816 #define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 817
AnnaBridge 143:86740a56073b 818 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 819 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 820 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 821 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 822 #define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 823 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 824 #define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 825 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 826 #define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 827 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 828 #define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 829 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 830 #define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 831 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 832 #define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 833 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 834 #define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 835 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 836 #define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 837
AnnaBridge 143:86740a56073b 838 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 839 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 840 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 841 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 842 #define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 843 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 844 #define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 845 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 846 #define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 847 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 848 #define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 849 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 850 #define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 851 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 852 #define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 853 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 854 #define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 855 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 856 #define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 857
AnnaBridge 143:86740a56073b 858 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 859 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 860 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 861 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 862 #define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 863 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 864 #define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 865 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 866 #define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 867 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 868 #define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 869 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 870 #define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 871 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 872 #define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 873 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 874 #define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 875 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 876 #define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 877
AnnaBridge 143:86740a56073b 878 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 879 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 880 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 881 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 882 #define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 883 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 884 #define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 885 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 886 #define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 887 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 888 #define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 889 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 890 #define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 891 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 892 #define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 893 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 894 #define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 895 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 896 #define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 897
AnnaBridge 143:86740a56073b 898 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 899 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 900 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 901 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 902 #define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 903 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 904 #define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 905 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 906 #define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 907 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 908 #define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 909 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 910 #define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 911 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 912 #define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 913 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 914 #define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 915 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 916 #define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 917
AnnaBridge 143:86740a56073b 918 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 919 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 920 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 921 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 922 #define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 923 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 924 #define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 925 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 926 #define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 927 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 928 #define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 929 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 930 #define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 931 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 932 #define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 933 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 934 #define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 935 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 936 #define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 937
AnnaBridge 143:86740a56073b 938 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 939 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 940 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 941 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 942 #define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 943 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 944 #define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 945 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 946 #define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 947 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 948 #define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 949 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 950 #define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 951 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 952 #define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 953 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 954 #define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 955 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 956 #define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 957
AnnaBridge 143:86740a56073b 958 /* Register: AMLI_RAMPRI_AAR */
AnnaBridge 143:86740a56073b 959 /* Description: AHB bus master priority register for AAR */
AnnaBridge 143:86740a56073b 960
AnnaBridge 143:86740a56073b 961 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 962 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 963 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 964 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 965 #define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 966 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 967 #define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 968 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 969 #define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 970 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 971 #define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 972 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 973 #define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 974 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 975 #define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 976 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 977 #define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 978 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 979 #define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 980
AnnaBridge 143:86740a56073b 981 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 982 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 983 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 984 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 985 #define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 986 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 987 #define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 988 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 989 #define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 990 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 991 #define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 992 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 993 #define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 994 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 995 #define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 996 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 997 #define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 998 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 999 #define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1000
AnnaBridge 143:86740a56073b 1001 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 1002 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 1003 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 1004 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1005 #define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1006 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1007 #define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1008 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1009 #define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1010 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1011 #define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1012 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1013 #define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1014 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1015 #define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1016 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1017 #define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1018 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1019 #define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1020
AnnaBridge 143:86740a56073b 1021 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 1022 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 1023 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 1024 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1025 #define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1026 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1027 #define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1028 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1029 #define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1030 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1031 #define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1032 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1033 #define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1034 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1035 #define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1036 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1037 #define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1038 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1039 #define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1040
AnnaBridge 143:86740a56073b 1041 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 1042 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 1043 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 1044 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1045 #define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1046 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1047 #define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1048 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1049 #define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1050 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1051 #define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1052 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1053 #define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1054 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1055 #define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1056 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1057 #define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1058 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1059 #define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1060
AnnaBridge 143:86740a56073b 1061 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 1062 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 1063 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 1064 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1065 #define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1066 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1067 #define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1068 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1069 #define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1070 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1071 #define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1072 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1073 #define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1074 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1075 #define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1076 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1077 #define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1078 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1079 #define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1080
AnnaBridge 143:86740a56073b 1081 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 1082 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 1083 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 1084 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1085 #define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1086 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1087 #define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1088 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1089 #define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1090 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1091 #define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1092 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1093 #define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1094 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1095 #define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1096 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1097 #define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1098 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1099 #define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1100
AnnaBridge 143:86740a56073b 1101 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 1102 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 1103 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 1104 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1105 #define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1106 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1107 #define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1108 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1109 #define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1110 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1111 #define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1112 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1113 #define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1114 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1115 #define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1116 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1117 #define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1118 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1119 #define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1120
AnnaBridge 143:86740a56073b 1121 /* Register: AMLI_RAMPRI_SAADC */
AnnaBridge 143:86740a56073b 1122 /* Description: AHB bus master priority register for SAADC */
AnnaBridge 143:86740a56073b 1123
AnnaBridge 143:86740a56073b 1124 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 1125 #define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 1126 #define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 1127 #define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1128 #define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1129 #define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1130 #define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1131 #define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1132 #define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1133 #define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1134 #define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1135 #define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1136 #define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1137 #define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1138 #define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1139 #define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1140 #define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1141 #define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1142 #define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1143
AnnaBridge 143:86740a56073b 1144 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 1145 #define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 1146 #define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 1147 #define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1148 #define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1149 #define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1150 #define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1151 #define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1152 #define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1153 #define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1154 #define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1155 #define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1156 #define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1157 #define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1158 #define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1159 #define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1160 #define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1161 #define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1162 #define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1163
AnnaBridge 143:86740a56073b 1164 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 1165 #define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 1166 #define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 1167 #define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1168 #define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1169 #define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1170 #define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1171 #define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1172 #define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1173 #define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1174 #define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1175 #define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1176 #define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1177 #define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1178 #define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1179 #define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1180 #define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1181 #define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1182 #define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1183
AnnaBridge 143:86740a56073b 1184 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 1185 #define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 1186 #define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 1187 #define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1188 #define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1189 #define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1190 #define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1191 #define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1192 #define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1193 #define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1194 #define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1195 #define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1196 #define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1197 #define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1198 #define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1199 #define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1200 #define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1201 #define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1202 #define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1203
AnnaBridge 143:86740a56073b 1204 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 1205 #define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 1206 #define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 1207 #define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1208 #define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1209 #define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1210 #define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1211 #define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1212 #define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1213 #define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1214 #define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1215 #define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1216 #define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1217 #define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1218 #define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1219 #define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1220 #define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1221 #define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1222 #define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1223
AnnaBridge 143:86740a56073b 1224 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 1225 #define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 1226 #define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 1227 #define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1228 #define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1229 #define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1230 #define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1231 #define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1232 #define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1233 #define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1234 #define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1235 #define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1236 #define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1237 #define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1238 #define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1239 #define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1240 #define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1241 #define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1242 #define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1243
AnnaBridge 143:86740a56073b 1244 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 1245 #define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 1246 #define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 1247 #define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1248 #define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1249 #define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1250 #define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1251 #define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1252 #define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1253 #define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1254 #define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1255 #define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1256 #define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1257 #define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1258 #define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1259 #define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1260 #define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1261 #define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1262 #define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1263
AnnaBridge 143:86740a56073b 1264 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 1265 #define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 1266 #define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 1267 #define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1268 #define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1269 #define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1270 #define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1271 #define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1272 #define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1273 #define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1274 #define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1275 #define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1276 #define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1277 #define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1278 #define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1279 #define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1280 #define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1281 #define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1282 #define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1283
AnnaBridge 143:86740a56073b 1284 /* Register: AMLI_RAMPRI_UARTE */
AnnaBridge 143:86740a56073b 1285 /* Description: AHB bus master priority register for UARTE */
AnnaBridge 143:86740a56073b 1286
AnnaBridge 143:86740a56073b 1287 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 1288 #define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 1289 #define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 1290 #define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1291 #define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1292 #define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1293 #define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1294 #define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1295 #define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1296 #define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1297 #define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1298 #define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1299 #define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1300 #define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1301 #define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1302 #define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1303 #define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1304 #define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1305 #define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1306
AnnaBridge 143:86740a56073b 1307 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 1308 #define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 1309 #define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 1310 #define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1311 #define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1312 #define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1313 #define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1314 #define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1315 #define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1316 #define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1317 #define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1318 #define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1319 #define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1320 #define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1321 #define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1322 #define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1323 #define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1324 #define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1325 #define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1326
AnnaBridge 143:86740a56073b 1327 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 1328 #define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 1329 #define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 1330 #define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1331 #define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1332 #define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1333 #define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1334 #define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1335 #define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1336 #define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1337 #define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1338 #define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1339 #define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1340 #define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1341 #define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1342 #define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1343 #define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1344 #define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1345 #define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1346
AnnaBridge 143:86740a56073b 1347 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 1348 #define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 1349 #define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 1350 #define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1351 #define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1352 #define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1353 #define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1354 #define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1355 #define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1356 #define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1357 #define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1358 #define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1359 #define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1360 #define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1361 #define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1362 #define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1363 #define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1364 #define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1365 #define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1366
AnnaBridge 143:86740a56073b 1367 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 1368 #define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 1369 #define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 1370 #define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1371 #define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1372 #define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1373 #define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1374 #define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1375 #define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1376 #define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1377 #define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1378 #define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1379 #define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1380 #define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1381 #define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1382 #define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1383 #define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1384 #define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1385 #define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1386
AnnaBridge 143:86740a56073b 1387 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 1388 #define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 1389 #define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 1390 #define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1391 #define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1392 #define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1393 #define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1394 #define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1395 #define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1396 #define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1397 #define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1398 #define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1399 #define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1400 #define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1401 #define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1402 #define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1403 #define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1404 #define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1405 #define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1406
AnnaBridge 143:86740a56073b 1407 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 1408 #define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 1409 #define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 1410 #define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1411 #define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1412 #define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1413 #define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1414 #define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1415 #define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1416 #define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1417 #define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1418 #define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1419 #define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1420 #define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1421 #define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1422 #define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1423 #define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1424 #define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1425 #define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1426
AnnaBridge 143:86740a56073b 1427 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 1428 #define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 1429 #define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 1430 #define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1431 #define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1432 #define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1433 #define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1434 #define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1435 #define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1436 #define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1437 #define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1438 #define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1439 #define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1440 #define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1441 #define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1442 #define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1443 #define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1444 #define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1445 #define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1446
AnnaBridge 143:86740a56073b 1447 /* Register: AMLI_RAMPRI_SERIAL0 */
AnnaBridge 143:86740a56073b 1448 /* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */
AnnaBridge 143:86740a56073b 1449
AnnaBridge 143:86740a56073b 1450 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 1451 #define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 1452 #define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 1453 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1454 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1455 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1456 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1457 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1458 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1459 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1460 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1461 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1462 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1463 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1464 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1465 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1466 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1467 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1468 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1469
AnnaBridge 143:86740a56073b 1470 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 1471 #define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 1472 #define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 1473 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1474 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1475 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1476 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1477 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1478 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1479 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1480 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1481 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1482 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1483 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1484 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1485 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1486 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1487 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1488 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1489
AnnaBridge 143:86740a56073b 1490 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 1491 #define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 1492 #define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 1493 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1494 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1495 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1496 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1497 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1498 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1499 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1500 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1501 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1502 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1503 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1504 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1505 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1506 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1507 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1508 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1509
AnnaBridge 143:86740a56073b 1510 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 1511 #define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 1512 #define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 1513 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1514 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1515 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1516 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1517 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1518 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1519 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1520 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1521 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1522 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1523 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1524 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1525 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1526 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1527 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1528 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1529
AnnaBridge 143:86740a56073b 1530 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 1531 #define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 1532 #define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 1533 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1534 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1535 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1536 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1537 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1538 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1539 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1540 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1541 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1542 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1543 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1544 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1545 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1546 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1547 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1548 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1549
AnnaBridge 143:86740a56073b 1550 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 1551 #define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 1552 #define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 1553 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1554 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1555 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1556 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1557 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1558 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1559 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1560 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1561 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1562 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1563 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1564 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1565 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1566 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1567 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1568 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1569
AnnaBridge 143:86740a56073b 1570 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 1571 #define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 1572 #define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 1573 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1574 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1575 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1576 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1577 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1578 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1579 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1580 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1581 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1582 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1583 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1584 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1585 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1586 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1587 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1588 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1589
AnnaBridge 143:86740a56073b 1590 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 1591 #define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 1592 #define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 1593 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1594 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1595 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1596 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1597 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1598 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1599 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1600 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1601 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1602 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1603 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1604 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1605 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1606 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1607 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1608 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1609
AnnaBridge 143:86740a56073b 1610 /* Register: AMLI_RAMPRI_SERIAL2 */
AnnaBridge 143:86740a56073b 1611 /* Description: AHB bus master priority register for SPIM2 and SPIS2 */
AnnaBridge 143:86740a56073b 1612
AnnaBridge 143:86740a56073b 1613 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 1614 #define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 1615 #define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 1616 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1617 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1618 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1619 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1620 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1621 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1622 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1623 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1624 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1625 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1626 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1627 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1628 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1629 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1630 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1631 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1632
AnnaBridge 143:86740a56073b 1633 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 1634 #define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 1635 #define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 1636 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1637 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1638 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1639 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1640 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1641 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1642 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1643 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1644 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1645 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1646 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1647 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1648 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1649 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1650 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1651 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1652
AnnaBridge 143:86740a56073b 1653 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 1654 #define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 1655 #define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 1656 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1657 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1658 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1659 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1660 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1661 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1662 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1663 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1664 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1665 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1666 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1667 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1668 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1669 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1670 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1671 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1672
AnnaBridge 143:86740a56073b 1673 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 1674 #define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 1675 #define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 1676 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1677 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1678 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1679 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1680 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1681 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1682 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1683 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1684 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1685 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1686 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1687 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1688 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1689 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1690 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1691 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1692
AnnaBridge 143:86740a56073b 1693 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 1694 #define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 1695 #define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 1696 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1697 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1698 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1699 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1700 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1701 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1702 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1703 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1704 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1705 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1706 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1707 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1708 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1709 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1710 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1711 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1712
AnnaBridge 143:86740a56073b 1713 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 1714 #define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 1715 #define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 1716 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1717 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1718 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1719 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1720 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1721 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1722 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1723 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1724 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1725 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1726 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1727 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1728 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1729 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1730 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1731 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1732
AnnaBridge 143:86740a56073b 1733 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 1734 #define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 1735 #define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 1736 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1737 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1738 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1739 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1740 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1741 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1742 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1743 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1744 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1745 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1746 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1747 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1748 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1749 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1750 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1751 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1752
AnnaBridge 143:86740a56073b 1753 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 1754 #define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 1755 #define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 1756 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1757 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1758 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1759 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1760 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1761 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1762 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1763 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1764 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1765 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1766 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1767 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1768 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1769 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1770 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1771 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1772
AnnaBridge 143:86740a56073b 1773 /* Register: AMLI_RAMPRI_NFCT */
AnnaBridge 143:86740a56073b 1774 /* Description: AHB bus master priority register for NFCT */
AnnaBridge 143:86740a56073b 1775
AnnaBridge 143:86740a56073b 1776 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 1777 #define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 1778 #define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 1779 #define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1780 #define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1781 #define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1782 #define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1783 #define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1784 #define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1785 #define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1786 #define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1787 #define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1788 #define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1789 #define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1790 #define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1791 #define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1792 #define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1793 #define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1794 #define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1795
AnnaBridge 143:86740a56073b 1796 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 1797 #define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 1798 #define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 1799 #define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1800 #define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1801 #define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1802 #define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1803 #define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1804 #define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1805 #define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1806 #define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1807 #define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1808 #define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1809 #define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1810 #define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1811 #define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1812 #define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1813 #define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1814 #define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1815
AnnaBridge 143:86740a56073b 1816 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 1817 #define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 1818 #define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 1819 #define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1820 #define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1821 #define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1822 #define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1823 #define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1824 #define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1825 #define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1826 #define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1827 #define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1828 #define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1829 #define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1830 #define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1831 #define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1832 #define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1833 #define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1834 #define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1835
AnnaBridge 143:86740a56073b 1836 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 1837 #define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 1838 #define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 1839 #define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1840 #define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1841 #define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1842 #define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1843 #define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1844 #define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1845 #define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1846 #define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1847 #define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1848 #define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1849 #define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1850 #define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1851 #define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1852 #define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1853 #define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1854 #define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1855
AnnaBridge 143:86740a56073b 1856 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 1857 #define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 1858 #define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 1859 #define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1860 #define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1861 #define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1862 #define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1863 #define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1864 #define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1865 #define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1866 #define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1867 #define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1868 #define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1869 #define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1870 #define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1871 #define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1872 #define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1873 #define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1874 #define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1875
AnnaBridge 143:86740a56073b 1876 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 1877 #define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 1878 #define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 1879 #define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1880 #define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1881 #define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1882 #define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1883 #define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1884 #define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1885 #define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1886 #define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1887 #define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1888 #define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1889 #define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1890 #define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1891 #define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1892 #define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1893 #define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1894 #define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1895
AnnaBridge 143:86740a56073b 1896 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 1897 #define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 1898 #define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 1899 #define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1900 #define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1901 #define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1902 #define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1903 #define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1904 #define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1905 #define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1906 #define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1907 #define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1908 #define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1909 #define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1910 #define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1911 #define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1912 #define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1913 #define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1914 #define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1915
AnnaBridge 143:86740a56073b 1916 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 1917 #define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 1918 #define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 1919 #define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1920 #define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1921 #define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1922 #define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1923 #define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1924 #define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1925 #define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1926 #define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1927 #define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1928 #define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1929 #define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1930 #define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1931 #define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1932 #define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1933 #define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1934 #define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1935
AnnaBridge 143:86740a56073b 1936 /* Register: AMLI_RAMPRI_I2S */
AnnaBridge 143:86740a56073b 1937 /* Description: AHB bus master priority register for I2S */
AnnaBridge 143:86740a56073b 1938
AnnaBridge 143:86740a56073b 1939 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 1940 #define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 1941 #define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 1942 #define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1943 #define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1944 #define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1945 #define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1946 #define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1947 #define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1948 #define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1949 #define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1950 #define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1951 #define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1952 #define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1953 #define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1954 #define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1955 #define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1956 #define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1957 #define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1958
AnnaBridge 143:86740a56073b 1959 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 1960 #define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 1961 #define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 1962 #define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1963 #define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1964 #define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1965 #define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1966 #define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1967 #define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1968 #define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1969 #define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1970 #define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1971 #define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1972 #define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1973 #define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1974 #define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1975 #define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1976 #define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1977 #define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1978
AnnaBridge 143:86740a56073b 1979 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 1980 #define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 1981 #define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 1982 #define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 1983 #define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 1984 #define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 1985 #define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 1986 #define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 1987 #define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 1988 #define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 1989 #define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 1990 #define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 1991 #define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 1992 #define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 1993 #define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 1994 #define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 1995 #define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 1996 #define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 1997 #define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 1998
AnnaBridge 143:86740a56073b 1999 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 2000 #define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 2001 #define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 2002 #define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2003 #define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2004 #define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2005 #define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2006 #define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2007 #define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2008 #define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2009 #define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2010 #define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2011 #define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2012 #define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2013 #define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2014 #define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2015 #define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2016 #define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2017 #define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2018
AnnaBridge 143:86740a56073b 2019 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 2020 #define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 2021 #define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 2022 #define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2023 #define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2024 #define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2025 #define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2026 #define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2027 #define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2028 #define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2029 #define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2030 #define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2031 #define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2032 #define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2033 #define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2034 #define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2035 #define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2036 #define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2037 #define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2038
AnnaBridge 143:86740a56073b 2039 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 2040 #define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 2041 #define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 2042 #define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2043 #define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2044 #define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2045 #define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2046 #define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2047 #define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2048 #define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2049 #define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2050 #define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2051 #define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2052 #define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2053 #define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2054 #define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2055 #define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2056 #define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2057 #define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2058
AnnaBridge 143:86740a56073b 2059 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 2060 #define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 2061 #define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 2062 #define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2063 #define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2064 #define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2065 #define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2066 #define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2067 #define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2068 #define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2069 #define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2070 #define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2071 #define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2072 #define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2073 #define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2074 #define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2075 #define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2076 #define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2077 #define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2078
AnnaBridge 143:86740a56073b 2079 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 2080 #define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 2081 #define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 2082 #define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2083 #define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2084 #define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2085 #define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2086 #define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2087 #define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2088 #define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2089 #define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2090 #define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2091 #define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2092 #define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2093 #define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2094 #define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2095 #define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2096 #define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2097 #define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2098
AnnaBridge 143:86740a56073b 2099 /* Register: AMLI_RAMPRI_PDM */
AnnaBridge 143:86740a56073b 2100 /* Description: AHB bus master priority register for PDM */
AnnaBridge 143:86740a56073b 2101
AnnaBridge 143:86740a56073b 2102 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 2103 #define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 2104 #define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 2105 #define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2106 #define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2107 #define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2108 #define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2109 #define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2110 #define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2111 #define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2112 #define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2113 #define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2114 #define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2115 #define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2116 #define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2117 #define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2118 #define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2119 #define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2120 #define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2121
AnnaBridge 143:86740a56073b 2122 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 2123 #define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 2124 #define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 2125 #define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2126 #define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2127 #define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2128 #define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2129 #define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2130 #define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2131 #define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2132 #define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2133 #define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2134 #define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2135 #define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2136 #define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2137 #define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2138 #define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2139 #define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2140 #define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2141
AnnaBridge 143:86740a56073b 2142 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 2143 #define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 2144 #define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 2145 #define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2146 #define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2147 #define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2148 #define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2149 #define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2150 #define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2151 #define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2152 #define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2153 #define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2154 #define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2155 #define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2156 #define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2157 #define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2158 #define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2159 #define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2160 #define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2161
AnnaBridge 143:86740a56073b 2162 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 2163 #define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 2164 #define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 2165 #define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2166 #define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2167 #define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2168 #define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2169 #define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2170 #define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2171 #define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2172 #define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2173 #define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2174 #define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2175 #define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2176 #define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2177 #define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2178 #define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2179 #define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2180 #define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2181
AnnaBridge 143:86740a56073b 2182 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 2183 #define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 2184 #define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 2185 #define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2186 #define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2187 #define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2188 #define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2189 #define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2190 #define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2191 #define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2192 #define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2193 #define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2194 #define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2195 #define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2196 #define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2197 #define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2198 #define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2199 #define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2200 #define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2201
AnnaBridge 143:86740a56073b 2202 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 2203 #define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 2204 #define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 2205 #define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2206 #define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2207 #define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2208 #define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2209 #define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2210 #define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2211 #define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2212 #define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2213 #define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2214 #define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2215 #define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2216 #define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2217 #define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2218 #define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2219 #define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2220 #define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2221
AnnaBridge 143:86740a56073b 2222 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 2223 #define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 2224 #define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 2225 #define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2226 #define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2227 #define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2228 #define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2229 #define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2230 #define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2231 #define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2232 #define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2233 #define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2234 #define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2235 #define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2236 #define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2237 #define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2238 #define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2239 #define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2240 #define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2241
AnnaBridge 143:86740a56073b 2242 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 2243 #define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 2244 #define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 2245 #define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2246 #define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2247 #define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2248 #define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2249 #define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2250 #define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2251 #define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2252 #define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2253 #define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2254 #define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2255 #define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2256 #define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2257 #define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2258 #define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2259 #define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2260 #define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2261
AnnaBridge 143:86740a56073b 2262 /* Register: AMLI_RAMPRI_PWM */
AnnaBridge 143:86740a56073b 2263 /* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */
AnnaBridge 143:86740a56073b 2264
AnnaBridge 143:86740a56073b 2265 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
AnnaBridge 143:86740a56073b 2266 #define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 2267 #define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 2268 #define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2269 #define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2270 #define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2271 #define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2272 #define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2273 #define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2274 #define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2275 #define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2276 #define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2277 #define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2278 #define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2279 #define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2280 #define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2281 #define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2282 #define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2283 #define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2284
AnnaBridge 143:86740a56073b 2285 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
AnnaBridge 143:86740a56073b 2286 #define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 2287 #define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 2288 #define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2289 #define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2290 #define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2291 #define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2292 #define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2293 #define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2294 #define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2295 #define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2296 #define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2297 #define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2298 #define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2299 #define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2300 #define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2301 #define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2302 #define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2303 #define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2304
AnnaBridge 143:86740a56073b 2305 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
AnnaBridge 143:86740a56073b 2306 #define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 2307 #define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 2308 #define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2309 #define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2310 #define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2311 #define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2312 #define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2313 #define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2314 #define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2315 #define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2316 #define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2317 #define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2318 #define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2319 #define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2320 #define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2321 #define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2322 #define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2323 #define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2324
AnnaBridge 143:86740a56073b 2325 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
AnnaBridge 143:86740a56073b 2326 #define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 2327 #define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 2328 #define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2329 #define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2330 #define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2331 #define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2332 #define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2333 #define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2334 #define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2335 #define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2336 #define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2337 #define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2338 #define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2339 #define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2340 #define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2341 #define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2342 #define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2343 #define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2344
AnnaBridge 143:86740a56073b 2345 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
AnnaBridge 143:86740a56073b 2346 #define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 2347 #define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 2348 #define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2349 #define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2350 #define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2351 #define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2352 #define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2353 #define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2354 #define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2355 #define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2356 #define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2357 #define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2358 #define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2359 #define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2360 #define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2361 #define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2362 #define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2363 #define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2364
AnnaBridge 143:86740a56073b 2365 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
AnnaBridge 143:86740a56073b 2366 #define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 2367 #define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 2368 #define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2369 #define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2370 #define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2371 #define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2372 #define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2373 #define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2374 #define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2375 #define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2376 #define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2377 #define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2378 #define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2379 #define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2380 #define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2381 #define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2382 #define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2383 #define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2384
AnnaBridge 143:86740a56073b 2385 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
AnnaBridge 143:86740a56073b 2386 #define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 2387 #define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 2388 #define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2389 #define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2390 #define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2391 #define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2392 #define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2393 #define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2394 #define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2395 #define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2396 #define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2397 #define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2398 #define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2399 #define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2400 #define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2401 #define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2402 #define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2403 #define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2404
AnnaBridge 143:86740a56073b 2405 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
AnnaBridge 143:86740a56073b 2406 #define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 2407 #define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 2408 #define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */
AnnaBridge 143:86740a56073b 2409 #define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */
AnnaBridge 143:86740a56073b 2410 #define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */
AnnaBridge 143:86740a56073b 2411 #define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */
AnnaBridge 143:86740a56073b 2412 #define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */
AnnaBridge 143:86740a56073b 2413 #define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */
AnnaBridge 143:86740a56073b 2414 #define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */
AnnaBridge 143:86740a56073b 2415 #define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */
AnnaBridge 143:86740a56073b 2416 #define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */
AnnaBridge 143:86740a56073b 2417 #define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */
AnnaBridge 143:86740a56073b 2418 #define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */
AnnaBridge 143:86740a56073b 2419 #define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */
AnnaBridge 143:86740a56073b 2420 #define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */
AnnaBridge 143:86740a56073b 2421 #define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */
AnnaBridge 143:86740a56073b 2422 #define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */
AnnaBridge 143:86740a56073b 2423 #define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */
AnnaBridge 143:86740a56073b 2424
AnnaBridge 143:86740a56073b 2425
AnnaBridge 143:86740a56073b 2426 /* Peripheral: BPROT */
AnnaBridge 143:86740a56073b 2427 /* Description: Block Protect */
AnnaBridge 143:86740a56073b 2428
AnnaBridge 143:86740a56073b 2429 /* Register: BPROT_CONFIG0 */
AnnaBridge 143:86740a56073b 2430 /* Description: Block protect configuration register 0 */
AnnaBridge 143:86740a56073b 2431
AnnaBridge 143:86740a56073b 2432 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2433 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
AnnaBridge 143:86740a56073b 2434 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
AnnaBridge 143:86740a56073b 2435 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2436 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2437
AnnaBridge 143:86740a56073b 2438 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2439 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
AnnaBridge 143:86740a56073b 2440 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
AnnaBridge 143:86740a56073b 2441 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2442 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2443
AnnaBridge 143:86740a56073b 2444 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2445 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
AnnaBridge 143:86740a56073b 2446 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
AnnaBridge 143:86740a56073b 2447 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2448 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2449
AnnaBridge 143:86740a56073b 2450 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2451 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
AnnaBridge 143:86740a56073b 2452 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
AnnaBridge 143:86740a56073b 2453 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2454 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2455
AnnaBridge 143:86740a56073b 2456 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2457 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
AnnaBridge 143:86740a56073b 2458 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
AnnaBridge 143:86740a56073b 2459 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2460 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2461
AnnaBridge 143:86740a56073b 2462 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2463 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
AnnaBridge 143:86740a56073b 2464 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
AnnaBridge 143:86740a56073b 2465 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2466 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2467
AnnaBridge 143:86740a56073b 2468 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2469 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
AnnaBridge 143:86740a56073b 2470 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
AnnaBridge 143:86740a56073b 2471 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2472 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2473
AnnaBridge 143:86740a56073b 2474 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2475 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
AnnaBridge 143:86740a56073b 2476 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
AnnaBridge 143:86740a56073b 2477 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2478 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2479
AnnaBridge 143:86740a56073b 2480 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2481 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
AnnaBridge 143:86740a56073b 2482 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
AnnaBridge 143:86740a56073b 2483 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2484 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2485
AnnaBridge 143:86740a56073b 2486 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2487 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
AnnaBridge 143:86740a56073b 2488 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
AnnaBridge 143:86740a56073b 2489 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2490 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2491
AnnaBridge 143:86740a56073b 2492 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2493 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
AnnaBridge 143:86740a56073b 2494 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
AnnaBridge 143:86740a56073b 2495 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2496 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2497
AnnaBridge 143:86740a56073b 2498 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2499 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
AnnaBridge 143:86740a56073b 2500 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
AnnaBridge 143:86740a56073b 2501 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2502 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2503
AnnaBridge 143:86740a56073b 2504 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2505 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
AnnaBridge 143:86740a56073b 2506 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
AnnaBridge 143:86740a56073b 2507 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2508 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2509
AnnaBridge 143:86740a56073b 2510 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2511 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
AnnaBridge 143:86740a56073b 2512 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
AnnaBridge 143:86740a56073b 2513 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2514 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2515
AnnaBridge 143:86740a56073b 2516 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2517 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
AnnaBridge 143:86740a56073b 2518 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
AnnaBridge 143:86740a56073b 2519 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2520 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2521
AnnaBridge 143:86740a56073b 2522 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2523 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
AnnaBridge 143:86740a56073b 2524 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
AnnaBridge 143:86740a56073b 2525 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2526 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2527
AnnaBridge 143:86740a56073b 2528 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2529 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
AnnaBridge 143:86740a56073b 2530 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
AnnaBridge 143:86740a56073b 2531 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2532 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2533
AnnaBridge 143:86740a56073b 2534 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2535 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
AnnaBridge 143:86740a56073b 2536 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
AnnaBridge 143:86740a56073b 2537 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2538 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2539
AnnaBridge 143:86740a56073b 2540 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2541 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
AnnaBridge 143:86740a56073b 2542 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
AnnaBridge 143:86740a56073b 2543 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2544 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2545
AnnaBridge 143:86740a56073b 2546 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2547 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
AnnaBridge 143:86740a56073b 2548 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
AnnaBridge 143:86740a56073b 2549 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2550 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2551
AnnaBridge 143:86740a56073b 2552 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2553 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
AnnaBridge 143:86740a56073b 2554 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
AnnaBridge 143:86740a56073b 2555 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2556 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2557
AnnaBridge 143:86740a56073b 2558 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2559 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
AnnaBridge 143:86740a56073b 2560 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
AnnaBridge 143:86740a56073b 2561 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2562 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2563
AnnaBridge 143:86740a56073b 2564 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2565 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
AnnaBridge 143:86740a56073b 2566 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
AnnaBridge 143:86740a56073b 2567 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2568 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2569
AnnaBridge 143:86740a56073b 2570 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2571 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
AnnaBridge 143:86740a56073b 2572 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
AnnaBridge 143:86740a56073b 2573 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2574 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2575
AnnaBridge 143:86740a56073b 2576 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2577 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
AnnaBridge 143:86740a56073b 2578 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
AnnaBridge 143:86740a56073b 2579 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2580 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2581
AnnaBridge 143:86740a56073b 2582 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2583 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
AnnaBridge 143:86740a56073b 2584 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
AnnaBridge 143:86740a56073b 2585 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2586 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2587
AnnaBridge 143:86740a56073b 2588 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2589 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
AnnaBridge 143:86740a56073b 2590 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
AnnaBridge 143:86740a56073b 2591 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2592 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2593
AnnaBridge 143:86740a56073b 2594 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2595 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
AnnaBridge 143:86740a56073b 2596 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
AnnaBridge 143:86740a56073b 2597 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2598 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2599
AnnaBridge 143:86740a56073b 2600 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2601 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
AnnaBridge 143:86740a56073b 2602 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
AnnaBridge 143:86740a56073b 2603 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2604 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2605
AnnaBridge 143:86740a56073b 2606 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2607 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
AnnaBridge 143:86740a56073b 2608 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
AnnaBridge 143:86740a56073b 2609 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2610 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2611
AnnaBridge 143:86740a56073b 2612 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2613 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
AnnaBridge 143:86740a56073b 2614 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
AnnaBridge 143:86740a56073b 2615 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2616 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2617
AnnaBridge 143:86740a56073b 2618 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2619 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
AnnaBridge 143:86740a56073b 2620 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
AnnaBridge 143:86740a56073b 2621 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2622 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
AnnaBridge 143:86740a56073b 2623
AnnaBridge 143:86740a56073b 2624 /* Register: BPROT_CONFIG1 */
AnnaBridge 143:86740a56073b 2625 /* Description: Block protect configuration register 1 */
AnnaBridge 143:86740a56073b 2626
AnnaBridge 143:86740a56073b 2627 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2628 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
AnnaBridge 143:86740a56073b 2629 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
AnnaBridge 143:86740a56073b 2630 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2631 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2632
AnnaBridge 143:86740a56073b 2633 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2634 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
AnnaBridge 143:86740a56073b 2635 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
AnnaBridge 143:86740a56073b 2636 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2637 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2638
AnnaBridge 143:86740a56073b 2639 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2640 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
AnnaBridge 143:86740a56073b 2641 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
AnnaBridge 143:86740a56073b 2642 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2643 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2644
AnnaBridge 143:86740a56073b 2645 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2646 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
AnnaBridge 143:86740a56073b 2647 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
AnnaBridge 143:86740a56073b 2648 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2649 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2650
AnnaBridge 143:86740a56073b 2651 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2652 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
AnnaBridge 143:86740a56073b 2653 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
AnnaBridge 143:86740a56073b 2654 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2655 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2656
AnnaBridge 143:86740a56073b 2657 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2658 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
AnnaBridge 143:86740a56073b 2659 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
AnnaBridge 143:86740a56073b 2660 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2661 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2662
AnnaBridge 143:86740a56073b 2663 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2664 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
AnnaBridge 143:86740a56073b 2665 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
AnnaBridge 143:86740a56073b 2666 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2667 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2668
AnnaBridge 143:86740a56073b 2669 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2670 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
AnnaBridge 143:86740a56073b 2671 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
AnnaBridge 143:86740a56073b 2672 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2673 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2674
AnnaBridge 143:86740a56073b 2675 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2676 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
AnnaBridge 143:86740a56073b 2677 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
AnnaBridge 143:86740a56073b 2678 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2679 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2680
AnnaBridge 143:86740a56073b 2681 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2682 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
AnnaBridge 143:86740a56073b 2683 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
AnnaBridge 143:86740a56073b 2684 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2685 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2686
AnnaBridge 143:86740a56073b 2687 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2688 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
AnnaBridge 143:86740a56073b 2689 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
AnnaBridge 143:86740a56073b 2690 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2691 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2692
AnnaBridge 143:86740a56073b 2693 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2694 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
AnnaBridge 143:86740a56073b 2695 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
AnnaBridge 143:86740a56073b 2696 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2697 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2698
AnnaBridge 143:86740a56073b 2699 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2700 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
AnnaBridge 143:86740a56073b 2701 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
AnnaBridge 143:86740a56073b 2702 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2703 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2704
AnnaBridge 143:86740a56073b 2705 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2706 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
AnnaBridge 143:86740a56073b 2707 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
AnnaBridge 143:86740a56073b 2708 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2709 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2710
AnnaBridge 143:86740a56073b 2711 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2712 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
AnnaBridge 143:86740a56073b 2713 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
AnnaBridge 143:86740a56073b 2714 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2715 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2716
AnnaBridge 143:86740a56073b 2717 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2718 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
AnnaBridge 143:86740a56073b 2719 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
AnnaBridge 143:86740a56073b 2720 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2721 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2722
AnnaBridge 143:86740a56073b 2723 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2724 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
AnnaBridge 143:86740a56073b 2725 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
AnnaBridge 143:86740a56073b 2726 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2727 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2728
AnnaBridge 143:86740a56073b 2729 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2730 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
AnnaBridge 143:86740a56073b 2731 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
AnnaBridge 143:86740a56073b 2732 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2733 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2734
AnnaBridge 143:86740a56073b 2735 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2736 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
AnnaBridge 143:86740a56073b 2737 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
AnnaBridge 143:86740a56073b 2738 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2739 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2740
AnnaBridge 143:86740a56073b 2741 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2742 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
AnnaBridge 143:86740a56073b 2743 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
AnnaBridge 143:86740a56073b 2744 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2745 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2746
AnnaBridge 143:86740a56073b 2747 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2748 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
AnnaBridge 143:86740a56073b 2749 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
AnnaBridge 143:86740a56073b 2750 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2751 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2752
AnnaBridge 143:86740a56073b 2753 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2754 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
AnnaBridge 143:86740a56073b 2755 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
AnnaBridge 143:86740a56073b 2756 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2757 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2758
AnnaBridge 143:86740a56073b 2759 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2760 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
AnnaBridge 143:86740a56073b 2761 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
AnnaBridge 143:86740a56073b 2762 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2763 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2764
AnnaBridge 143:86740a56073b 2765 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2766 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
AnnaBridge 143:86740a56073b 2767 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
AnnaBridge 143:86740a56073b 2768 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2769 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2770
AnnaBridge 143:86740a56073b 2771 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2772 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
AnnaBridge 143:86740a56073b 2773 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
AnnaBridge 143:86740a56073b 2774 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2775 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2776
AnnaBridge 143:86740a56073b 2777 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2778 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
AnnaBridge 143:86740a56073b 2779 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
AnnaBridge 143:86740a56073b 2780 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2781 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2782
AnnaBridge 143:86740a56073b 2783 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2784 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
AnnaBridge 143:86740a56073b 2785 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
AnnaBridge 143:86740a56073b 2786 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2787 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2788
AnnaBridge 143:86740a56073b 2789 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2790 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
AnnaBridge 143:86740a56073b 2791 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
AnnaBridge 143:86740a56073b 2792 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2793 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2794
AnnaBridge 143:86740a56073b 2795 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2796 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
AnnaBridge 143:86740a56073b 2797 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
AnnaBridge 143:86740a56073b 2798 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2799 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2800
AnnaBridge 143:86740a56073b 2801 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2802 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
AnnaBridge 143:86740a56073b 2803 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
AnnaBridge 143:86740a56073b 2804 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2805 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2806
AnnaBridge 143:86740a56073b 2807 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2808 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
AnnaBridge 143:86740a56073b 2809 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
AnnaBridge 143:86740a56073b 2810 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2811 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2812
AnnaBridge 143:86740a56073b 2813 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2814 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
AnnaBridge 143:86740a56073b 2815 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
AnnaBridge 143:86740a56073b 2816 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2817 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2818
AnnaBridge 143:86740a56073b 2819 /* Register: BPROT_DISABLEINDEBUG */
AnnaBridge 143:86740a56073b 2820 /* Description: Disable protection mechanism in debug interface mode */
AnnaBridge 143:86740a56073b 2821
AnnaBridge 143:86740a56073b 2822 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
AnnaBridge 143:86740a56073b 2823 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
AnnaBridge 143:86740a56073b 2824 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
AnnaBridge 143:86740a56073b 2825 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
AnnaBridge 143:86740a56073b 2826 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
AnnaBridge 143:86740a56073b 2827
AnnaBridge 143:86740a56073b 2828 /* Register: BPROT_CONFIG2 */
AnnaBridge 143:86740a56073b 2829 /* Description: Block protect configuration register 2 */
AnnaBridge 143:86740a56073b 2830
AnnaBridge 143:86740a56073b 2831 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2832 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
AnnaBridge 143:86740a56073b 2833 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
AnnaBridge 143:86740a56073b 2834 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2835 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2836
AnnaBridge 143:86740a56073b 2837 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2838 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
AnnaBridge 143:86740a56073b 2839 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
AnnaBridge 143:86740a56073b 2840 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2841 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2842
AnnaBridge 143:86740a56073b 2843 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2844 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
AnnaBridge 143:86740a56073b 2845 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
AnnaBridge 143:86740a56073b 2846 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2847 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2848
AnnaBridge 143:86740a56073b 2849 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2850 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
AnnaBridge 143:86740a56073b 2851 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
AnnaBridge 143:86740a56073b 2852 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2853 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2854
AnnaBridge 143:86740a56073b 2855 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2856 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
AnnaBridge 143:86740a56073b 2857 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
AnnaBridge 143:86740a56073b 2858 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2859 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2860
AnnaBridge 143:86740a56073b 2861 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2862 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
AnnaBridge 143:86740a56073b 2863 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
AnnaBridge 143:86740a56073b 2864 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2865 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2866
AnnaBridge 143:86740a56073b 2867 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2868 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
AnnaBridge 143:86740a56073b 2869 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
AnnaBridge 143:86740a56073b 2870 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2871 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2872
AnnaBridge 143:86740a56073b 2873 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2874 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
AnnaBridge 143:86740a56073b 2875 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
AnnaBridge 143:86740a56073b 2876 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2877 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2878
AnnaBridge 143:86740a56073b 2879 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2880 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
AnnaBridge 143:86740a56073b 2881 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
AnnaBridge 143:86740a56073b 2882 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2883 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2884
AnnaBridge 143:86740a56073b 2885 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2886 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
AnnaBridge 143:86740a56073b 2887 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
AnnaBridge 143:86740a56073b 2888 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2889 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2890
AnnaBridge 143:86740a56073b 2891 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2892 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
AnnaBridge 143:86740a56073b 2893 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
AnnaBridge 143:86740a56073b 2894 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2895 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2896
AnnaBridge 143:86740a56073b 2897 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2898 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
AnnaBridge 143:86740a56073b 2899 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
AnnaBridge 143:86740a56073b 2900 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2901 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2902
AnnaBridge 143:86740a56073b 2903 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2904 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
AnnaBridge 143:86740a56073b 2905 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
AnnaBridge 143:86740a56073b 2906 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2907 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2908
AnnaBridge 143:86740a56073b 2909 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2910 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
AnnaBridge 143:86740a56073b 2911 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
AnnaBridge 143:86740a56073b 2912 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2913 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2914
AnnaBridge 143:86740a56073b 2915 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2916 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
AnnaBridge 143:86740a56073b 2917 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
AnnaBridge 143:86740a56073b 2918 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2919 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2920
AnnaBridge 143:86740a56073b 2921 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2922 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
AnnaBridge 143:86740a56073b 2923 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
AnnaBridge 143:86740a56073b 2924 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2925 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2926
AnnaBridge 143:86740a56073b 2927 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2928 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
AnnaBridge 143:86740a56073b 2929 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
AnnaBridge 143:86740a56073b 2930 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2931 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2932
AnnaBridge 143:86740a56073b 2933 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2934 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
AnnaBridge 143:86740a56073b 2935 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
AnnaBridge 143:86740a56073b 2936 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2937 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2938
AnnaBridge 143:86740a56073b 2939 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2940 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
AnnaBridge 143:86740a56073b 2941 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
AnnaBridge 143:86740a56073b 2942 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2943 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2944
AnnaBridge 143:86740a56073b 2945 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2946 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
AnnaBridge 143:86740a56073b 2947 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
AnnaBridge 143:86740a56073b 2948 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2949 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2950
AnnaBridge 143:86740a56073b 2951 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2952 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
AnnaBridge 143:86740a56073b 2953 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
AnnaBridge 143:86740a56073b 2954 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2955 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2956
AnnaBridge 143:86740a56073b 2957 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2958 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
AnnaBridge 143:86740a56073b 2959 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
AnnaBridge 143:86740a56073b 2960 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2961 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2962
AnnaBridge 143:86740a56073b 2963 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2964 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
AnnaBridge 143:86740a56073b 2965 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
AnnaBridge 143:86740a56073b 2966 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2967 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2968
AnnaBridge 143:86740a56073b 2969 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2970 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
AnnaBridge 143:86740a56073b 2971 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
AnnaBridge 143:86740a56073b 2972 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2973 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2974
AnnaBridge 143:86740a56073b 2975 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2976 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
AnnaBridge 143:86740a56073b 2977 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
AnnaBridge 143:86740a56073b 2978 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2979 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2980
AnnaBridge 143:86740a56073b 2981 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2982 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
AnnaBridge 143:86740a56073b 2983 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
AnnaBridge 143:86740a56073b 2984 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2985 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2986
AnnaBridge 143:86740a56073b 2987 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2988 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
AnnaBridge 143:86740a56073b 2989 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
AnnaBridge 143:86740a56073b 2990 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2991 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2992
AnnaBridge 143:86740a56073b 2993 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 2994 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
AnnaBridge 143:86740a56073b 2995 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
AnnaBridge 143:86740a56073b 2996 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 2997 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 2998
AnnaBridge 143:86740a56073b 2999 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3000 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
AnnaBridge 143:86740a56073b 3001 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
AnnaBridge 143:86740a56073b 3002 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3003 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3004
AnnaBridge 143:86740a56073b 3005 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3006 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
AnnaBridge 143:86740a56073b 3007 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
AnnaBridge 143:86740a56073b 3008 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3009 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3010
AnnaBridge 143:86740a56073b 3011 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3012 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
AnnaBridge 143:86740a56073b 3013 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
AnnaBridge 143:86740a56073b 3014 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3015 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3016
AnnaBridge 143:86740a56073b 3017 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3018 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
AnnaBridge 143:86740a56073b 3019 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
AnnaBridge 143:86740a56073b 3020 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3021 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3022
AnnaBridge 143:86740a56073b 3023 /* Register: BPROT_CONFIG3 */
AnnaBridge 143:86740a56073b 3024 /* Description: Block protect configuration register 3 */
AnnaBridge 143:86740a56073b 3025
AnnaBridge 143:86740a56073b 3026 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3027 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
AnnaBridge 143:86740a56073b 3028 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
AnnaBridge 143:86740a56073b 3029 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3030 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3031
AnnaBridge 143:86740a56073b 3032 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3033 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
AnnaBridge 143:86740a56073b 3034 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
AnnaBridge 143:86740a56073b 3035 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3036 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3037
AnnaBridge 143:86740a56073b 3038 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3039 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
AnnaBridge 143:86740a56073b 3040 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
AnnaBridge 143:86740a56073b 3041 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3042 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3043
AnnaBridge 143:86740a56073b 3044 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3045 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
AnnaBridge 143:86740a56073b 3046 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
AnnaBridge 143:86740a56073b 3047 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3048 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3049
AnnaBridge 143:86740a56073b 3050 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3051 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
AnnaBridge 143:86740a56073b 3052 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
AnnaBridge 143:86740a56073b 3053 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3054 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3055
AnnaBridge 143:86740a56073b 3056 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3057 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
AnnaBridge 143:86740a56073b 3058 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
AnnaBridge 143:86740a56073b 3059 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3060 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3061
AnnaBridge 143:86740a56073b 3062 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3063 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
AnnaBridge 143:86740a56073b 3064 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
AnnaBridge 143:86740a56073b 3065 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3066 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3067
AnnaBridge 143:86740a56073b 3068 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3069 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
AnnaBridge 143:86740a56073b 3070 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
AnnaBridge 143:86740a56073b 3071 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3072 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3073
AnnaBridge 143:86740a56073b 3074 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3075 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
AnnaBridge 143:86740a56073b 3076 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
AnnaBridge 143:86740a56073b 3077 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3078 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3079
AnnaBridge 143:86740a56073b 3080 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3081 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
AnnaBridge 143:86740a56073b 3082 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
AnnaBridge 143:86740a56073b 3083 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3084 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3085
AnnaBridge 143:86740a56073b 3086 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3087 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
AnnaBridge 143:86740a56073b 3088 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
AnnaBridge 143:86740a56073b 3089 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3090 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3091
AnnaBridge 143:86740a56073b 3092 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3093 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
AnnaBridge 143:86740a56073b 3094 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
AnnaBridge 143:86740a56073b 3095 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3096 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3097
AnnaBridge 143:86740a56073b 3098 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3099 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
AnnaBridge 143:86740a56073b 3100 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
AnnaBridge 143:86740a56073b 3101 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3102 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3103
AnnaBridge 143:86740a56073b 3104 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3105 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
AnnaBridge 143:86740a56073b 3106 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
AnnaBridge 143:86740a56073b 3107 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3108 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3109
AnnaBridge 143:86740a56073b 3110 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3111 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
AnnaBridge 143:86740a56073b 3112 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
AnnaBridge 143:86740a56073b 3113 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3114 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3115
AnnaBridge 143:86740a56073b 3116 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3117 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
AnnaBridge 143:86740a56073b 3118 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
AnnaBridge 143:86740a56073b 3119 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3120 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3121
AnnaBridge 143:86740a56073b 3122 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3123 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
AnnaBridge 143:86740a56073b 3124 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
AnnaBridge 143:86740a56073b 3125 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3126 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3127
AnnaBridge 143:86740a56073b 3128 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3129 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
AnnaBridge 143:86740a56073b 3130 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
AnnaBridge 143:86740a56073b 3131 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3132 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3133
AnnaBridge 143:86740a56073b 3134 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3135 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
AnnaBridge 143:86740a56073b 3136 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
AnnaBridge 143:86740a56073b 3137 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3138 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3139
AnnaBridge 143:86740a56073b 3140 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3141 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
AnnaBridge 143:86740a56073b 3142 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
AnnaBridge 143:86740a56073b 3143 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3144 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3145
AnnaBridge 143:86740a56073b 3146 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3147 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
AnnaBridge 143:86740a56073b 3148 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
AnnaBridge 143:86740a56073b 3149 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3150 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3151
AnnaBridge 143:86740a56073b 3152 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3153 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
AnnaBridge 143:86740a56073b 3154 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
AnnaBridge 143:86740a56073b 3155 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3156 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3157
AnnaBridge 143:86740a56073b 3158 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3159 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
AnnaBridge 143:86740a56073b 3160 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
AnnaBridge 143:86740a56073b 3161 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3162 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3163
AnnaBridge 143:86740a56073b 3164 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3165 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
AnnaBridge 143:86740a56073b 3166 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
AnnaBridge 143:86740a56073b 3167 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3168 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3169
AnnaBridge 143:86740a56073b 3170 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3171 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
AnnaBridge 143:86740a56073b 3172 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
AnnaBridge 143:86740a56073b 3173 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3174 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3175
AnnaBridge 143:86740a56073b 3176 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3177 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
AnnaBridge 143:86740a56073b 3178 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
AnnaBridge 143:86740a56073b 3179 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3180 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3181
AnnaBridge 143:86740a56073b 3182 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3183 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
AnnaBridge 143:86740a56073b 3184 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
AnnaBridge 143:86740a56073b 3185 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3186 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3187
AnnaBridge 143:86740a56073b 3188 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3189 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
AnnaBridge 143:86740a56073b 3190 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
AnnaBridge 143:86740a56073b 3191 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3192 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3193
AnnaBridge 143:86740a56073b 3194 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3195 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
AnnaBridge 143:86740a56073b 3196 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
AnnaBridge 143:86740a56073b 3197 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3198 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3199
AnnaBridge 143:86740a56073b 3200 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3201 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
AnnaBridge 143:86740a56073b 3202 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
AnnaBridge 143:86740a56073b 3203 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3204 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3205
AnnaBridge 143:86740a56073b 3206 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3207 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
AnnaBridge 143:86740a56073b 3208 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
AnnaBridge 143:86740a56073b 3209 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3210 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3211
AnnaBridge 143:86740a56073b 3212 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
AnnaBridge 143:86740a56073b 3213 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
AnnaBridge 143:86740a56073b 3214 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
AnnaBridge 143:86740a56073b 3215 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
AnnaBridge 143:86740a56073b 3216 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
AnnaBridge 143:86740a56073b 3217
AnnaBridge 143:86740a56073b 3218
AnnaBridge 143:86740a56073b 3219 /* Peripheral: CCM */
AnnaBridge 143:86740a56073b 3220 /* Description: AES CCM Mode Encryption */
AnnaBridge 143:86740a56073b 3221
AnnaBridge 143:86740a56073b 3222 /* Register: CCM_SHORTS */
AnnaBridge 143:86740a56073b 3223 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 3224
AnnaBridge 143:86740a56073b 3225 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
AnnaBridge 143:86740a56073b 3226 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
AnnaBridge 143:86740a56073b 3227 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
AnnaBridge 143:86740a56073b 3228 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 3229 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 3230
AnnaBridge 143:86740a56073b 3231 /* Register: CCM_INTENSET */
AnnaBridge 143:86740a56073b 3232 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 3233
AnnaBridge 143:86740a56073b 3234 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 3235 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 3236 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 3237 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3238 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3239 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3240
AnnaBridge 143:86740a56073b 3241 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
AnnaBridge 143:86740a56073b 3242 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 3243 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 3244 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3245 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3246 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3247
AnnaBridge 143:86740a56073b 3248 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
AnnaBridge 143:86740a56073b 3249 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 3250 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 3251 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3252 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3253 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3254
AnnaBridge 143:86740a56073b 3255 /* Register: CCM_INTENCLR */
AnnaBridge 143:86740a56073b 3256 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 3257
AnnaBridge 143:86740a56073b 3258 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 3259 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 3260 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 3261 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3262 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3263 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3264
AnnaBridge 143:86740a56073b 3265 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
AnnaBridge 143:86740a56073b 3266 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 3267 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 3268 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3269 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3270 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3271
AnnaBridge 143:86740a56073b 3272 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
AnnaBridge 143:86740a56073b 3273 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 3274 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 3275 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3276 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3277 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3278
AnnaBridge 143:86740a56073b 3279 /* Register: CCM_MICSTATUS */
AnnaBridge 143:86740a56073b 3280 /* Description: MIC check result */
AnnaBridge 143:86740a56073b 3281
AnnaBridge 143:86740a56073b 3282 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
AnnaBridge 143:86740a56073b 3283 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
AnnaBridge 143:86740a56073b 3284 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
AnnaBridge 143:86740a56073b 3285 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
AnnaBridge 143:86740a56073b 3286 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
AnnaBridge 143:86740a56073b 3287
AnnaBridge 143:86740a56073b 3288 /* Register: CCM_ENABLE */
AnnaBridge 143:86740a56073b 3289 /* Description: Enable */
AnnaBridge 143:86740a56073b 3290
AnnaBridge 143:86740a56073b 3291 /* Bits 1..0 : Enable or disable CCM */
AnnaBridge 143:86740a56073b 3292 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 3293 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 3294 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3295 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3296
AnnaBridge 143:86740a56073b 3297 /* Register: CCM_MODE */
AnnaBridge 143:86740a56073b 3298 /* Description: Operation mode */
AnnaBridge 143:86740a56073b 3299
AnnaBridge 143:86740a56073b 3300 /* Bit 24 : Packet length configuration */
AnnaBridge 143:86740a56073b 3301 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
AnnaBridge 143:86740a56073b 3302 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
AnnaBridge 143:86740a56073b 3303 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
AnnaBridge 143:86740a56073b 3304 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
AnnaBridge 143:86740a56073b 3305
AnnaBridge 143:86740a56073b 3306 /* Bit 16 : Data rate that the CCM shall run in synch with */
AnnaBridge 143:86740a56073b 3307 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
AnnaBridge 143:86740a56073b 3308 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
AnnaBridge 143:86740a56073b 3309 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
AnnaBridge 143:86740a56073b 3310 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
AnnaBridge 143:86740a56073b 3311
AnnaBridge 143:86740a56073b 3312 /* Bit 0 : The mode of operation to be used */
AnnaBridge 143:86740a56073b 3313 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 3314 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 3315 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
AnnaBridge 143:86740a56073b 3316 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
AnnaBridge 143:86740a56073b 3317
AnnaBridge 143:86740a56073b 3318 /* Register: CCM_CNFPTR */
AnnaBridge 143:86740a56073b 3319 /* Description: Pointer to data structure holding AES key and NONCE vector */
AnnaBridge 143:86740a56073b 3320
AnnaBridge 143:86740a56073b 3321 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
AnnaBridge 143:86740a56073b 3322 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
AnnaBridge 143:86740a56073b 3323 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
AnnaBridge 143:86740a56073b 3324
AnnaBridge 143:86740a56073b 3325 /* Register: CCM_INPTR */
AnnaBridge 143:86740a56073b 3326 /* Description: Input pointer */
AnnaBridge 143:86740a56073b 3327
AnnaBridge 143:86740a56073b 3328 /* Bits 31..0 : Input pointer */
AnnaBridge 143:86740a56073b 3329 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
AnnaBridge 143:86740a56073b 3330 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
AnnaBridge 143:86740a56073b 3331
AnnaBridge 143:86740a56073b 3332 /* Register: CCM_OUTPTR */
AnnaBridge 143:86740a56073b 3333 /* Description: Output pointer */
AnnaBridge 143:86740a56073b 3334
AnnaBridge 143:86740a56073b 3335 /* Bits 31..0 : Output pointer */
AnnaBridge 143:86740a56073b 3336 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
AnnaBridge 143:86740a56073b 3337 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
AnnaBridge 143:86740a56073b 3338
AnnaBridge 143:86740a56073b 3339 /* Register: CCM_SCRATCHPTR */
AnnaBridge 143:86740a56073b 3340 /* Description: Pointer to data area used for temporary storage */
AnnaBridge 143:86740a56073b 3341
AnnaBridge 143:86740a56073b 3342 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
AnnaBridge 143:86740a56073b 3343 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
AnnaBridge 143:86740a56073b 3344 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
AnnaBridge 143:86740a56073b 3345
AnnaBridge 143:86740a56073b 3346
AnnaBridge 143:86740a56073b 3347 /* Peripheral: CLOCK */
AnnaBridge 143:86740a56073b 3348 /* Description: Clock control */
AnnaBridge 143:86740a56073b 3349
AnnaBridge 143:86740a56073b 3350 /* Register: CLOCK_INTENSET */
AnnaBridge 143:86740a56073b 3351 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 3352
AnnaBridge 143:86740a56073b 3353 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
AnnaBridge 143:86740a56073b 3354 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
AnnaBridge 143:86740a56073b 3355 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
AnnaBridge 143:86740a56073b 3356 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3357 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3358 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3359
AnnaBridge 143:86740a56073b 3360 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
AnnaBridge 143:86740a56073b 3361 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
AnnaBridge 143:86740a56073b 3362 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
AnnaBridge 143:86740a56073b 3363 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3364 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3365 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3366
AnnaBridge 143:86740a56073b 3367 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
AnnaBridge 143:86740a56073b 3368 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3369 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3370 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3371 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3372 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3373
AnnaBridge 143:86740a56073b 3374 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
AnnaBridge 143:86740a56073b 3375 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3376 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3377 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3378 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3379 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3380
AnnaBridge 143:86740a56073b 3381 /* Register: CLOCK_INTENCLR */
AnnaBridge 143:86740a56073b 3382 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 3383
AnnaBridge 143:86740a56073b 3384 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
AnnaBridge 143:86740a56073b 3385 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
AnnaBridge 143:86740a56073b 3386 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
AnnaBridge 143:86740a56073b 3387 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3388 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3389 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3390
AnnaBridge 143:86740a56073b 3391 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
AnnaBridge 143:86740a56073b 3392 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
AnnaBridge 143:86740a56073b 3393 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
AnnaBridge 143:86740a56073b 3394 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3395 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3396 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3397
AnnaBridge 143:86740a56073b 3398 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
AnnaBridge 143:86740a56073b 3399 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3400 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3401 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3402 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3403 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3404
AnnaBridge 143:86740a56073b 3405 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
AnnaBridge 143:86740a56073b 3406 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3407 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 3408 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3409 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3410 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3411
AnnaBridge 143:86740a56073b 3412 /* Register: CLOCK_HFCLKRUN */
AnnaBridge 143:86740a56073b 3413 /* Description: Status indicating that HFCLKSTART task has been triggered */
AnnaBridge 143:86740a56073b 3414
AnnaBridge 143:86740a56073b 3415 /* Bit 0 : HFCLKSTART task triggered or not */
AnnaBridge 143:86740a56073b 3416 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
AnnaBridge 143:86740a56073b 3417 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
AnnaBridge 143:86740a56073b 3418 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
AnnaBridge 143:86740a56073b 3419 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
AnnaBridge 143:86740a56073b 3420
AnnaBridge 143:86740a56073b 3421 /* Register: CLOCK_HFCLKSTAT */
AnnaBridge 143:86740a56073b 3422 /* Description: HFCLK status */
AnnaBridge 143:86740a56073b 3423
AnnaBridge 143:86740a56073b 3424 /* Bit 16 : HFCLK state */
AnnaBridge 143:86740a56073b 3425 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
AnnaBridge 143:86740a56073b 3426 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
AnnaBridge 143:86740a56073b 3427 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
AnnaBridge 143:86740a56073b 3428 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
AnnaBridge 143:86740a56073b 3429
AnnaBridge 143:86740a56073b 3430 /* Bit 0 : Source of HFCLK */
AnnaBridge 143:86740a56073b 3431 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 3432 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 3433 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
AnnaBridge 143:86740a56073b 3434 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
AnnaBridge 143:86740a56073b 3435
AnnaBridge 143:86740a56073b 3436 /* Register: CLOCK_LFCLKRUN */
AnnaBridge 143:86740a56073b 3437 /* Description: Status indicating that LFCLKSTART task has been triggered */
AnnaBridge 143:86740a56073b 3438
AnnaBridge 143:86740a56073b 3439 /* Bit 0 : LFCLKSTART task triggered or not */
AnnaBridge 143:86740a56073b 3440 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
AnnaBridge 143:86740a56073b 3441 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
AnnaBridge 143:86740a56073b 3442 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
AnnaBridge 143:86740a56073b 3443 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
AnnaBridge 143:86740a56073b 3444
AnnaBridge 143:86740a56073b 3445 /* Register: CLOCK_LFCLKSTAT */
AnnaBridge 143:86740a56073b 3446 /* Description: LFCLK status */
AnnaBridge 143:86740a56073b 3447
AnnaBridge 143:86740a56073b 3448 /* Bit 16 : LFCLK state */
AnnaBridge 143:86740a56073b 3449 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
AnnaBridge 143:86740a56073b 3450 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
AnnaBridge 143:86740a56073b 3451 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
AnnaBridge 143:86740a56073b 3452 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
AnnaBridge 143:86740a56073b 3453
AnnaBridge 143:86740a56073b 3454 /* Bits 1..0 : Source of LFCLK */
AnnaBridge 143:86740a56073b 3455 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 3456 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 3457 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
AnnaBridge 143:86740a56073b 3458 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
AnnaBridge 143:86740a56073b 3459 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
AnnaBridge 143:86740a56073b 3460
AnnaBridge 143:86740a56073b 3461 /* Register: CLOCK_LFCLKSRCCOPY */
AnnaBridge 143:86740a56073b 3462 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
AnnaBridge 143:86740a56073b 3463
AnnaBridge 143:86740a56073b 3464 /* Bits 1..0 : Clock source */
AnnaBridge 143:86740a56073b 3465 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 3466 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 3467 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
AnnaBridge 143:86740a56073b 3468 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
AnnaBridge 143:86740a56073b 3469 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
AnnaBridge 143:86740a56073b 3470
AnnaBridge 143:86740a56073b 3471 /* Register: CLOCK_LFCLKSRC */
AnnaBridge 143:86740a56073b 3472 /* Description: Clock source for the LFCLK */
AnnaBridge 143:86740a56073b 3473
AnnaBridge 143:86740a56073b 3474 /* Bits 1..0 : Clock source */
AnnaBridge 143:86740a56073b 3475 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 3476 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 3477 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
AnnaBridge 143:86740a56073b 3478 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
AnnaBridge 143:86740a56073b 3479 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
AnnaBridge 143:86740a56073b 3480
AnnaBridge 143:86740a56073b 3481 /* Register: CLOCK_CTIV */
AnnaBridge 143:86740a56073b 3482 /* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */
AnnaBridge 143:86740a56073b 3483
AnnaBridge 143:86740a56073b 3484 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
AnnaBridge 143:86740a56073b 3485 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
AnnaBridge 143:86740a56073b 3486 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
AnnaBridge 143:86740a56073b 3487
AnnaBridge 143:86740a56073b 3488 /* Register: CLOCK_TRACECONFIG */
AnnaBridge 143:86740a56073b 3489 /* Description: Clocking options for the Trace Port debug interface */
AnnaBridge 143:86740a56073b 3490
AnnaBridge 143:86740a56073b 3491 /* Bits 17..16 : Pin multiplexing of trace signals. */
AnnaBridge 143:86740a56073b 3492 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
AnnaBridge 143:86740a56073b 3493 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
AnnaBridge 143:86740a56073b 3494 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
AnnaBridge 143:86740a56073b 3495 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
AnnaBridge 143:86740a56073b 3496 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
AnnaBridge 143:86740a56073b 3497
AnnaBridge 143:86740a56073b 3498 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
AnnaBridge 143:86740a56073b 3499 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
AnnaBridge 143:86740a56073b 3500 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
AnnaBridge 143:86740a56073b 3501 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
AnnaBridge 143:86740a56073b 3502 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
AnnaBridge 143:86740a56073b 3503 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
AnnaBridge 143:86740a56073b 3504 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
AnnaBridge 143:86740a56073b 3505
AnnaBridge 143:86740a56073b 3506
AnnaBridge 143:86740a56073b 3507 /* Peripheral: COMP */
AnnaBridge 143:86740a56073b 3508 /* Description: Comparator */
AnnaBridge 143:86740a56073b 3509
AnnaBridge 143:86740a56073b 3510 /* Register: COMP_SHORTS */
AnnaBridge 143:86740a56073b 3511 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 3512
AnnaBridge 143:86740a56073b 3513 /* Bit 4 : Shortcut between CROSS event and STOP task */
AnnaBridge 143:86740a56073b 3514 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
AnnaBridge 143:86740a56073b 3515 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
AnnaBridge 143:86740a56073b 3516 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 3517 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 3518
AnnaBridge 143:86740a56073b 3519 /* Bit 3 : Shortcut between UP event and STOP task */
AnnaBridge 143:86740a56073b 3520 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
AnnaBridge 143:86740a56073b 3521 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
AnnaBridge 143:86740a56073b 3522 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 3523 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 3524
AnnaBridge 143:86740a56073b 3525 /* Bit 2 : Shortcut between DOWN event and STOP task */
AnnaBridge 143:86740a56073b 3526 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
AnnaBridge 143:86740a56073b 3527 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
AnnaBridge 143:86740a56073b 3528 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 3529 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 3530
AnnaBridge 143:86740a56073b 3531 /* Bit 1 : Shortcut between READY event and STOP task */
AnnaBridge 143:86740a56073b 3532 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
AnnaBridge 143:86740a56073b 3533 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
AnnaBridge 143:86740a56073b 3534 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 3535 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 3536
AnnaBridge 143:86740a56073b 3537 /* Bit 0 : Shortcut between READY event and SAMPLE task */
AnnaBridge 143:86740a56073b 3538 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
AnnaBridge 143:86740a56073b 3539 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
AnnaBridge 143:86740a56073b 3540 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 3541 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 3542
AnnaBridge 143:86740a56073b 3543 /* Register: COMP_INTEN */
AnnaBridge 143:86740a56073b 3544 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 3545
AnnaBridge 143:86740a56073b 3546 /* Bit 3 : Enable or disable interrupt for CROSS event */
AnnaBridge 143:86740a56073b 3547 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
AnnaBridge 143:86740a56073b 3548 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
AnnaBridge 143:86740a56073b 3549 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3550 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3551
AnnaBridge 143:86740a56073b 3552 /* Bit 2 : Enable or disable interrupt for UP event */
AnnaBridge 143:86740a56073b 3553 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
AnnaBridge 143:86740a56073b 3554 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
AnnaBridge 143:86740a56073b 3555 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3556 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3557
AnnaBridge 143:86740a56073b 3558 /* Bit 1 : Enable or disable interrupt for DOWN event */
AnnaBridge 143:86740a56073b 3559 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
AnnaBridge 143:86740a56073b 3560 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
AnnaBridge 143:86740a56073b 3561 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3562 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3563
AnnaBridge 143:86740a56073b 3564 /* Bit 0 : Enable or disable interrupt for READY event */
AnnaBridge 143:86740a56073b 3565 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 3566 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 3567 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3568 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3569
AnnaBridge 143:86740a56073b 3570 /* Register: COMP_INTENSET */
AnnaBridge 143:86740a56073b 3571 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 3572
AnnaBridge 143:86740a56073b 3573 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
AnnaBridge 143:86740a56073b 3574 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
AnnaBridge 143:86740a56073b 3575 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
AnnaBridge 143:86740a56073b 3576 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3577 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3578 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3579
AnnaBridge 143:86740a56073b 3580 /* Bit 2 : Write '1' to Enable interrupt for UP event */
AnnaBridge 143:86740a56073b 3581 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
AnnaBridge 143:86740a56073b 3582 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
AnnaBridge 143:86740a56073b 3583 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3584 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3585 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3586
AnnaBridge 143:86740a56073b 3587 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
AnnaBridge 143:86740a56073b 3588 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
AnnaBridge 143:86740a56073b 3589 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
AnnaBridge 143:86740a56073b 3590 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3591 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3592 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3593
AnnaBridge 143:86740a56073b 3594 /* Bit 0 : Write '1' to Enable interrupt for READY event */
AnnaBridge 143:86740a56073b 3595 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 3596 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 3597 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3598 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3599 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3600
AnnaBridge 143:86740a56073b 3601 /* Register: COMP_INTENCLR */
AnnaBridge 143:86740a56073b 3602 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 3603
AnnaBridge 143:86740a56073b 3604 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
AnnaBridge 143:86740a56073b 3605 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
AnnaBridge 143:86740a56073b 3606 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
AnnaBridge 143:86740a56073b 3607 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3608 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3609 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3610
AnnaBridge 143:86740a56073b 3611 /* Bit 2 : Write '1' to Disable interrupt for UP event */
AnnaBridge 143:86740a56073b 3612 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
AnnaBridge 143:86740a56073b 3613 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
AnnaBridge 143:86740a56073b 3614 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3615 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3616 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3617
AnnaBridge 143:86740a56073b 3618 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
AnnaBridge 143:86740a56073b 3619 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
AnnaBridge 143:86740a56073b 3620 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
AnnaBridge 143:86740a56073b 3621 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3622 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3623 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3624
AnnaBridge 143:86740a56073b 3625 /* Bit 0 : Write '1' to Disable interrupt for READY event */
AnnaBridge 143:86740a56073b 3626 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 3627 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 3628 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3629 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3630 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3631
AnnaBridge 143:86740a56073b 3632 /* Register: COMP_RESULT */
AnnaBridge 143:86740a56073b 3633 /* Description: Compare result */
AnnaBridge 143:86740a56073b 3634
AnnaBridge 143:86740a56073b 3635 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
AnnaBridge 143:86740a56073b 3636 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
AnnaBridge 143:86740a56073b 3637 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
AnnaBridge 143:86740a56073b 3638 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
AnnaBridge 143:86740a56073b 3639 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
AnnaBridge 143:86740a56073b 3640
AnnaBridge 143:86740a56073b 3641 /* Register: COMP_ENABLE */
AnnaBridge 143:86740a56073b 3642 /* Description: COMP enable */
AnnaBridge 143:86740a56073b 3643
AnnaBridge 143:86740a56073b 3644 /* Bits 1..0 : Enable or disable COMP */
AnnaBridge 143:86740a56073b 3645 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 3646 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 3647 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3648 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3649
AnnaBridge 143:86740a56073b 3650 /* Register: COMP_PSEL */
AnnaBridge 143:86740a56073b 3651 /* Description: Pin select */
AnnaBridge 143:86740a56073b 3652
AnnaBridge 143:86740a56073b 3653 /* Bits 2..0 : Analog pin select */
AnnaBridge 143:86740a56073b 3654 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
AnnaBridge 143:86740a56073b 3655 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
AnnaBridge 143:86740a56073b 3656 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
AnnaBridge 143:86740a56073b 3657 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
AnnaBridge 143:86740a56073b 3658 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
AnnaBridge 143:86740a56073b 3659 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
AnnaBridge 143:86740a56073b 3660 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
AnnaBridge 143:86740a56073b 3661 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
AnnaBridge 143:86740a56073b 3662 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
AnnaBridge 143:86740a56073b 3663 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
AnnaBridge 143:86740a56073b 3664
AnnaBridge 143:86740a56073b 3665 /* Register: COMP_REFSEL */
AnnaBridge 143:86740a56073b 3666 /* Description: Reference source select */
AnnaBridge 143:86740a56073b 3667
AnnaBridge 143:86740a56073b 3668 /* Bits 2..0 : Reference select */
AnnaBridge 143:86740a56073b 3669 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
AnnaBridge 143:86740a56073b 3670 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
AnnaBridge 143:86740a56073b 3671 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
AnnaBridge 143:86740a56073b 3672 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
AnnaBridge 143:86740a56073b 3673 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
AnnaBridge 143:86740a56073b 3674 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
AnnaBridge 143:86740a56073b 3675 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
AnnaBridge 143:86740a56073b 3676
AnnaBridge 143:86740a56073b 3677 /* Register: COMP_EXTREFSEL */
AnnaBridge 143:86740a56073b 3678 /* Description: External reference select */
AnnaBridge 143:86740a56073b 3679
AnnaBridge 143:86740a56073b 3680 /* Bit 0 : External analog reference select */
AnnaBridge 143:86740a56073b 3681 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 3682 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 3683 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
AnnaBridge 143:86740a56073b 3684 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
AnnaBridge 143:86740a56073b 3685
AnnaBridge 143:86740a56073b 3686 /* Register: COMP_TH */
AnnaBridge 143:86740a56073b 3687 /* Description: Threshold configuration for hysteresis unit */
AnnaBridge 143:86740a56073b 3688
AnnaBridge 143:86740a56073b 3689 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
AnnaBridge 143:86740a56073b 3690 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
AnnaBridge 143:86740a56073b 3691 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
AnnaBridge 143:86740a56073b 3692
AnnaBridge 143:86740a56073b 3693 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
AnnaBridge 143:86740a56073b 3694 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
AnnaBridge 143:86740a56073b 3695 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
AnnaBridge 143:86740a56073b 3696
AnnaBridge 143:86740a56073b 3697 /* Register: COMP_MODE */
AnnaBridge 143:86740a56073b 3698 /* Description: Mode configuration */
AnnaBridge 143:86740a56073b 3699
AnnaBridge 143:86740a56073b 3700 /* Bit 8 : Main operation mode */
AnnaBridge 143:86740a56073b 3701 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
AnnaBridge 143:86740a56073b 3702 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
AnnaBridge 143:86740a56073b 3703 #define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
AnnaBridge 143:86740a56073b 3704 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
AnnaBridge 143:86740a56073b 3705
AnnaBridge 143:86740a56073b 3706 /* Bits 1..0 : Speed and power mode */
AnnaBridge 143:86740a56073b 3707 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
AnnaBridge 143:86740a56073b 3708 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
AnnaBridge 143:86740a56073b 3709 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
AnnaBridge 143:86740a56073b 3710 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
AnnaBridge 143:86740a56073b 3711 #define COMP_MODE_SP_High (2UL) /*!< High speed mode */
AnnaBridge 143:86740a56073b 3712
AnnaBridge 143:86740a56073b 3713 /* Register: COMP_HYST */
AnnaBridge 143:86740a56073b 3714 /* Description: Comparator hysteresis enable */
AnnaBridge 143:86740a56073b 3715
AnnaBridge 143:86740a56073b 3716 /* Bit 0 : Comparator hysteresis */
AnnaBridge 143:86740a56073b 3717 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
AnnaBridge 143:86740a56073b 3718 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
AnnaBridge 143:86740a56073b 3719 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
AnnaBridge 143:86740a56073b 3720 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
AnnaBridge 143:86740a56073b 3721
AnnaBridge 143:86740a56073b 3722 /* Register: COMP_ISOURCE */
AnnaBridge 143:86740a56073b 3723 /* Description: Current source select on analog input */
AnnaBridge 143:86740a56073b 3724
AnnaBridge 143:86740a56073b 3725 /* Bits 1..0 : Comparator hysteresis */
AnnaBridge 143:86740a56073b 3726 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
AnnaBridge 143:86740a56073b 3727 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
AnnaBridge 143:86740a56073b 3728 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
AnnaBridge 143:86740a56073b 3729 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
AnnaBridge 143:86740a56073b 3730 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
AnnaBridge 143:86740a56073b 3731 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
AnnaBridge 143:86740a56073b 3732
AnnaBridge 143:86740a56073b 3733
AnnaBridge 143:86740a56073b 3734 /* Peripheral: ECB */
AnnaBridge 143:86740a56073b 3735 /* Description: AES ECB Mode Encryption */
AnnaBridge 143:86740a56073b 3736
AnnaBridge 143:86740a56073b 3737 /* Register: ECB_INTENSET */
AnnaBridge 143:86740a56073b 3738 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 3739
AnnaBridge 143:86740a56073b 3740 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
AnnaBridge 143:86740a56073b 3741 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
AnnaBridge 143:86740a56073b 3742 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
AnnaBridge 143:86740a56073b 3743 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3744 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3745 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3746
AnnaBridge 143:86740a56073b 3747 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
AnnaBridge 143:86740a56073b 3748 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
AnnaBridge 143:86740a56073b 3749 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
AnnaBridge 143:86740a56073b 3750 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3751 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3752 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3753
AnnaBridge 143:86740a56073b 3754 /* Register: ECB_INTENCLR */
AnnaBridge 143:86740a56073b 3755 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 3756
AnnaBridge 143:86740a56073b 3757 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
AnnaBridge 143:86740a56073b 3758 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
AnnaBridge 143:86740a56073b 3759 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
AnnaBridge 143:86740a56073b 3760 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3761 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3762 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3763
AnnaBridge 143:86740a56073b 3764 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
AnnaBridge 143:86740a56073b 3765 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
AnnaBridge 143:86740a56073b 3766 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
AnnaBridge 143:86740a56073b 3767 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3768 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3769 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3770
AnnaBridge 143:86740a56073b 3771 /* Register: ECB_ECBDATAPTR */
AnnaBridge 143:86740a56073b 3772 /* Description: ECB block encrypt memory pointers */
AnnaBridge 143:86740a56073b 3773
AnnaBridge 143:86740a56073b 3774 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
AnnaBridge 143:86740a56073b 3775 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
AnnaBridge 143:86740a56073b 3776 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
AnnaBridge 143:86740a56073b 3777
AnnaBridge 143:86740a56073b 3778
AnnaBridge 143:86740a56073b 3779 /* Peripheral: EGU */
AnnaBridge 143:86740a56073b 3780 /* Description: Event Generator Unit 0 */
AnnaBridge 143:86740a56073b 3781
AnnaBridge 143:86740a56073b 3782 /* Register: EGU_INTEN */
AnnaBridge 143:86740a56073b 3783 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 3784
AnnaBridge 143:86740a56073b 3785 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
AnnaBridge 143:86740a56073b 3786 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
AnnaBridge 143:86740a56073b 3787 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
AnnaBridge 143:86740a56073b 3788 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3789 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3790
AnnaBridge 143:86740a56073b 3791 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
AnnaBridge 143:86740a56073b 3792 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
AnnaBridge 143:86740a56073b 3793 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
AnnaBridge 143:86740a56073b 3794 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3795 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3796
AnnaBridge 143:86740a56073b 3797 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
AnnaBridge 143:86740a56073b 3798 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
AnnaBridge 143:86740a56073b 3799 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
AnnaBridge 143:86740a56073b 3800 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3801 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3802
AnnaBridge 143:86740a56073b 3803 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
AnnaBridge 143:86740a56073b 3804 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
AnnaBridge 143:86740a56073b 3805 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
AnnaBridge 143:86740a56073b 3806 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3807 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3808
AnnaBridge 143:86740a56073b 3809 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
AnnaBridge 143:86740a56073b 3810 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
AnnaBridge 143:86740a56073b 3811 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
AnnaBridge 143:86740a56073b 3812 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3813 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3814
AnnaBridge 143:86740a56073b 3815 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
AnnaBridge 143:86740a56073b 3816 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
AnnaBridge 143:86740a56073b 3817 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
AnnaBridge 143:86740a56073b 3818 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3819 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3820
AnnaBridge 143:86740a56073b 3821 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
AnnaBridge 143:86740a56073b 3822 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
AnnaBridge 143:86740a56073b 3823 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
AnnaBridge 143:86740a56073b 3824 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3825 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3826
AnnaBridge 143:86740a56073b 3827 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
AnnaBridge 143:86740a56073b 3828 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
AnnaBridge 143:86740a56073b 3829 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
AnnaBridge 143:86740a56073b 3830 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3831 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3832
AnnaBridge 143:86740a56073b 3833 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
AnnaBridge 143:86740a56073b 3834 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
AnnaBridge 143:86740a56073b 3835 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
AnnaBridge 143:86740a56073b 3836 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3837 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3838
AnnaBridge 143:86740a56073b 3839 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
AnnaBridge 143:86740a56073b 3840 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
AnnaBridge 143:86740a56073b 3841 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
AnnaBridge 143:86740a56073b 3842 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3843 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3844
AnnaBridge 143:86740a56073b 3845 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
AnnaBridge 143:86740a56073b 3846 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
AnnaBridge 143:86740a56073b 3847 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
AnnaBridge 143:86740a56073b 3848 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3849 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3850
AnnaBridge 143:86740a56073b 3851 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
AnnaBridge 143:86740a56073b 3852 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
AnnaBridge 143:86740a56073b 3853 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
AnnaBridge 143:86740a56073b 3854 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3855 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3856
AnnaBridge 143:86740a56073b 3857 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
AnnaBridge 143:86740a56073b 3858 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
AnnaBridge 143:86740a56073b 3859 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
AnnaBridge 143:86740a56073b 3860 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3861 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3862
AnnaBridge 143:86740a56073b 3863 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
AnnaBridge 143:86740a56073b 3864 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
AnnaBridge 143:86740a56073b 3865 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
AnnaBridge 143:86740a56073b 3866 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3867 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3868
AnnaBridge 143:86740a56073b 3869 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
AnnaBridge 143:86740a56073b 3870 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
AnnaBridge 143:86740a56073b 3871 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
AnnaBridge 143:86740a56073b 3872 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3873 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3874
AnnaBridge 143:86740a56073b 3875 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
AnnaBridge 143:86740a56073b 3876 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
AnnaBridge 143:86740a56073b 3877 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
AnnaBridge 143:86740a56073b 3878 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 3879 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3880
AnnaBridge 143:86740a56073b 3881 /* Register: EGU_INTENSET */
AnnaBridge 143:86740a56073b 3882 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 3883
AnnaBridge 143:86740a56073b 3884 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
AnnaBridge 143:86740a56073b 3885 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
AnnaBridge 143:86740a56073b 3886 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
AnnaBridge 143:86740a56073b 3887 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3888 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3889 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3890
AnnaBridge 143:86740a56073b 3891 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
AnnaBridge 143:86740a56073b 3892 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
AnnaBridge 143:86740a56073b 3893 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
AnnaBridge 143:86740a56073b 3894 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3895 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3896 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3897
AnnaBridge 143:86740a56073b 3898 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
AnnaBridge 143:86740a56073b 3899 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
AnnaBridge 143:86740a56073b 3900 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
AnnaBridge 143:86740a56073b 3901 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3902 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3903 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3904
AnnaBridge 143:86740a56073b 3905 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
AnnaBridge 143:86740a56073b 3906 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
AnnaBridge 143:86740a56073b 3907 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
AnnaBridge 143:86740a56073b 3908 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3909 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3910 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3911
AnnaBridge 143:86740a56073b 3912 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
AnnaBridge 143:86740a56073b 3913 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
AnnaBridge 143:86740a56073b 3914 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
AnnaBridge 143:86740a56073b 3915 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3916 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3917 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3918
AnnaBridge 143:86740a56073b 3919 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
AnnaBridge 143:86740a56073b 3920 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
AnnaBridge 143:86740a56073b 3921 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
AnnaBridge 143:86740a56073b 3922 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3923 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3924 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3925
AnnaBridge 143:86740a56073b 3926 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
AnnaBridge 143:86740a56073b 3927 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
AnnaBridge 143:86740a56073b 3928 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
AnnaBridge 143:86740a56073b 3929 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3930 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3931 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3932
AnnaBridge 143:86740a56073b 3933 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
AnnaBridge 143:86740a56073b 3934 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
AnnaBridge 143:86740a56073b 3935 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
AnnaBridge 143:86740a56073b 3936 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3937 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3938 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3939
AnnaBridge 143:86740a56073b 3940 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
AnnaBridge 143:86740a56073b 3941 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
AnnaBridge 143:86740a56073b 3942 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
AnnaBridge 143:86740a56073b 3943 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3944 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3945 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3946
AnnaBridge 143:86740a56073b 3947 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
AnnaBridge 143:86740a56073b 3948 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
AnnaBridge 143:86740a56073b 3949 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
AnnaBridge 143:86740a56073b 3950 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3951 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3952 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3953
AnnaBridge 143:86740a56073b 3954 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
AnnaBridge 143:86740a56073b 3955 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
AnnaBridge 143:86740a56073b 3956 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
AnnaBridge 143:86740a56073b 3957 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3958 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3959 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3960
AnnaBridge 143:86740a56073b 3961 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
AnnaBridge 143:86740a56073b 3962 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
AnnaBridge 143:86740a56073b 3963 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
AnnaBridge 143:86740a56073b 3964 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3965 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3966 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3967
AnnaBridge 143:86740a56073b 3968 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
AnnaBridge 143:86740a56073b 3969 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
AnnaBridge 143:86740a56073b 3970 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
AnnaBridge 143:86740a56073b 3971 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3972 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3973 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3974
AnnaBridge 143:86740a56073b 3975 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
AnnaBridge 143:86740a56073b 3976 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
AnnaBridge 143:86740a56073b 3977 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
AnnaBridge 143:86740a56073b 3978 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3979 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3980 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3981
AnnaBridge 143:86740a56073b 3982 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
AnnaBridge 143:86740a56073b 3983 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
AnnaBridge 143:86740a56073b 3984 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
AnnaBridge 143:86740a56073b 3985 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3986 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3987 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3988
AnnaBridge 143:86740a56073b 3989 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
AnnaBridge 143:86740a56073b 3990 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
AnnaBridge 143:86740a56073b 3991 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
AnnaBridge 143:86740a56073b 3992 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 3993 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 3994 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 3995
AnnaBridge 143:86740a56073b 3996 /* Register: EGU_INTENCLR */
AnnaBridge 143:86740a56073b 3997 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 3998
AnnaBridge 143:86740a56073b 3999 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
AnnaBridge 143:86740a56073b 4000 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
AnnaBridge 143:86740a56073b 4001 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
AnnaBridge 143:86740a56073b 4002 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4003 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4004 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4005
AnnaBridge 143:86740a56073b 4006 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
AnnaBridge 143:86740a56073b 4007 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
AnnaBridge 143:86740a56073b 4008 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
AnnaBridge 143:86740a56073b 4009 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4010 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4011 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4012
AnnaBridge 143:86740a56073b 4013 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
AnnaBridge 143:86740a56073b 4014 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
AnnaBridge 143:86740a56073b 4015 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
AnnaBridge 143:86740a56073b 4016 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4017 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4018 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4019
AnnaBridge 143:86740a56073b 4020 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
AnnaBridge 143:86740a56073b 4021 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
AnnaBridge 143:86740a56073b 4022 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
AnnaBridge 143:86740a56073b 4023 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4024 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4025 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4026
AnnaBridge 143:86740a56073b 4027 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
AnnaBridge 143:86740a56073b 4028 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
AnnaBridge 143:86740a56073b 4029 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
AnnaBridge 143:86740a56073b 4030 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4031 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4032 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4033
AnnaBridge 143:86740a56073b 4034 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
AnnaBridge 143:86740a56073b 4035 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
AnnaBridge 143:86740a56073b 4036 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
AnnaBridge 143:86740a56073b 4037 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4038 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4039 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4040
AnnaBridge 143:86740a56073b 4041 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
AnnaBridge 143:86740a56073b 4042 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
AnnaBridge 143:86740a56073b 4043 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
AnnaBridge 143:86740a56073b 4044 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4045 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4046 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4047
AnnaBridge 143:86740a56073b 4048 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
AnnaBridge 143:86740a56073b 4049 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
AnnaBridge 143:86740a56073b 4050 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
AnnaBridge 143:86740a56073b 4051 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4052 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4053 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4054
AnnaBridge 143:86740a56073b 4055 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
AnnaBridge 143:86740a56073b 4056 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
AnnaBridge 143:86740a56073b 4057 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
AnnaBridge 143:86740a56073b 4058 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4059 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4060 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4061
AnnaBridge 143:86740a56073b 4062 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
AnnaBridge 143:86740a56073b 4063 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
AnnaBridge 143:86740a56073b 4064 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
AnnaBridge 143:86740a56073b 4065 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4066 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4067 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4068
AnnaBridge 143:86740a56073b 4069 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
AnnaBridge 143:86740a56073b 4070 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
AnnaBridge 143:86740a56073b 4071 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
AnnaBridge 143:86740a56073b 4072 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4073 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4074 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4075
AnnaBridge 143:86740a56073b 4076 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
AnnaBridge 143:86740a56073b 4077 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
AnnaBridge 143:86740a56073b 4078 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
AnnaBridge 143:86740a56073b 4079 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4080 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4081 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4082
AnnaBridge 143:86740a56073b 4083 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
AnnaBridge 143:86740a56073b 4084 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
AnnaBridge 143:86740a56073b 4085 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
AnnaBridge 143:86740a56073b 4086 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4087 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4088 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4089
AnnaBridge 143:86740a56073b 4090 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
AnnaBridge 143:86740a56073b 4091 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
AnnaBridge 143:86740a56073b 4092 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
AnnaBridge 143:86740a56073b 4093 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4094 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4095 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4096
AnnaBridge 143:86740a56073b 4097 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
AnnaBridge 143:86740a56073b 4098 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
AnnaBridge 143:86740a56073b 4099 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
AnnaBridge 143:86740a56073b 4100 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4101 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4102 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4103
AnnaBridge 143:86740a56073b 4104 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
AnnaBridge 143:86740a56073b 4105 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
AnnaBridge 143:86740a56073b 4106 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
AnnaBridge 143:86740a56073b 4107 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4108 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4109 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4110
AnnaBridge 143:86740a56073b 4111
AnnaBridge 143:86740a56073b 4112 /* Peripheral: FICR */
AnnaBridge 143:86740a56073b 4113 /* Description: Factory Information Configuration Registers */
AnnaBridge 143:86740a56073b 4114
AnnaBridge 143:86740a56073b 4115 /* Register: FICR_CODEPAGESIZE */
AnnaBridge 143:86740a56073b 4116 /* Description: Code memory page size */
AnnaBridge 143:86740a56073b 4117
AnnaBridge 143:86740a56073b 4118 /* Bits 31..0 : Code memory page size */
AnnaBridge 143:86740a56073b 4119 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
AnnaBridge 143:86740a56073b 4120 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
AnnaBridge 143:86740a56073b 4121
AnnaBridge 143:86740a56073b 4122 /* Register: FICR_CODESIZE */
AnnaBridge 143:86740a56073b 4123 /* Description: Code memory size */
AnnaBridge 143:86740a56073b 4124
AnnaBridge 143:86740a56073b 4125 /* Bits 31..0 : Code memory size in number of pages */
AnnaBridge 143:86740a56073b 4126 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
AnnaBridge 143:86740a56073b 4127 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
AnnaBridge 143:86740a56073b 4128
AnnaBridge 143:86740a56073b 4129 /* Register: FICR_DEVICEID */
AnnaBridge 143:86740a56073b 4130 /* Description: Description collection[0]: Device identifier */
AnnaBridge 143:86740a56073b 4131
AnnaBridge 143:86740a56073b 4132 /* Bits 31..0 : 64 bit unique device identifier */
AnnaBridge 143:86740a56073b 4133 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
AnnaBridge 143:86740a56073b 4134 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
AnnaBridge 143:86740a56073b 4135
AnnaBridge 143:86740a56073b 4136 /* Register: FICR_ER */
AnnaBridge 143:86740a56073b 4137 /* Description: Description collection[0]: Encryption Root, word 0 */
AnnaBridge 143:86740a56073b 4138
AnnaBridge 143:86740a56073b 4139 /* Bits 31..0 : Encryption Root, word n */
AnnaBridge 143:86740a56073b 4140 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
AnnaBridge 143:86740a56073b 4141 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
AnnaBridge 143:86740a56073b 4142
AnnaBridge 143:86740a56073b 4143 /* Register: FICR_IR */
AnnaBridge 143:86740a56073b 4144 /* Description: Description collection[0]: Identity Root, word 0 */
AnnaBridge 143:86740a56073b 4145
AnnaBridge 143:86740a56073b 4146 /* Bits 31..0 : Identity Root, word n */
AnnaBridge 143:86740a56073b 4147 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
AnnaBridge 143:86740a56073b 4148 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
AnnaBridge 143:86740a56073b 4149
AnnaBridge 143:86740a56073b 4150 /* Register: FICR_DEVICEADDRTYPE */
AnnaBridge 143:86740a56073b 4151 /* Description: Device address type */
AnnaBridge 143:86740a56073b 4152
AnnaBridge 143:86740a56073b 4153 /* Bit 0 : Device address type */
AnnaBridge 143:86740a56073b 4154 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
AnnaBridge 143:86740a56073b 4155 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
AnnaBridge 143:86740a56073b 4156 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
AnnaBridge 143:86740a56073b 4157 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
AnnaBridge 143:86740a56073b 4158
AnnaBridge 143:86740a56073b 4159 /* Register: FICR_DEVICEADDR */
AnnaBridge 143:86740a56073b 4160 /* Description: Description collection[0]: Device address 0 */
AnnaBridge 143:86740a56073b 4161
AnnaBridge 143:86740a56073b 4162 /* Bits 31..0 : 48 bit device address */
AnnaBridge 143:86740a56073b 4163 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
AnnaBridge 143:86740a56073b 4164 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
AnnaBridge 143:86740a56073b 4165
AnnaBridge 143:86740a56073b 4166 /* Register: FICR_INFO_PART */
AnnaBridge 143:86740a56073b 4167 /* Description: Part code */
AnnaBridge 143:86740a56073b 4168
AnnaBridge 143:86740a56073b 4169 /* Bits 31..0 : Part code */
AnnaBridge 143:86740a56073b 4170 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
AnnaBridge 143:86740a56073b 4171 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
AnnaBridge 143:86740a56073b 4172 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
AnnaBridge 143:86740a56073b 4173 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
AnnaBridge 143:86740a56073b 4174
AnnaBridge 143:86740a56073b 4175 /* Register: FICR_INFO_VARIANT */
AnnaBridge 143:86740a56073b 4176 /* Description: Part Variant, Hardware version and Production configuration */
AnnaBridge 143:86740a56073b 4177
AnnaBridge 143:86740a56073b 4178 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
AnnaBridge 143:86740a56073b 4179 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
AnnaBridge 143:86740a56073b 4180 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
AnnaBridge 143:86740a56073b 4181 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
AnnaBridge 143:86740a56073b 4182 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
AnnaBridge 143:86740a56073b 4183 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
AnnaBridge 143:86740a56073b 4184 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
AnnaBridge 143:86740a56073b 4185 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
AnnaBridge 143:86740a56073b 4186
AnnaBridge 143:86740a56073b 4187 /* Register: FICR_INFO_PACKAGE */
AnnaBridge 143:86740a56073b 4188 /* Description: Package option */
AnnaBridge 143:86740a56073b 4189
AnnaBridge 143:86740a56073b 4190 /* Bits 31..0 : Package option */
AnnaBridge 143:86740a56073b 4191 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
AnnaBridge 143:86740a56073b 4192 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
AnnaBridge 143:86740a56073b 4193 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
AnnaBridge 143:86740a56073b 4194 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
AnnaBridge 143:86740a56073b 4195 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
AnnaBridge 143:86740a56073b 4196
AnnaBridge 143:86740a56073b 4197 /* Register: FICR_INFO_RAM */
AnnaBridge 143:86740a56073b 4198 /* Description: RAM variant */
AnnaBridge 143:86740a56073b 4199
AnnaBridge 143:86740a56073b 4200 /* Bits 31..0 : RAM variant */
AnnaBridge 143:86740a56073b 4201 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
AnnaBridge 143:86740a56073b 4202 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
AnnaBridge 143:86740a56073b 4203 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
AnnaBridge 143:86740a56073b 4204 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
AnnaBridge 143:86740a56073b 4205 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
AnnaBridge 143:86740a56073b 4206 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
AnnaBridge 143:86740a56073b 4207
AnnaBridge 143:86740a56073b 4208 /* Register: FICR_INFO_FLASH */
AnnaBridge 143:86740a56073b 4209 /* Description: Flash variant */
AnnaBridge 143:86740a56073b 4210
AnnaBridge 143:86740a56073b 4211 /* Bits 31..0 : Flash variant */
AnnaBridge 143:86740a56073b 4212 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
AnnaBridge 143:86740a56073b 4213 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
AnnaBridge 143:86740a56073b 4214 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
AnnaBridge 143:86740a56073b 4215 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
AnnaBridge 143:86740a56073b 4216 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
AnnaBridge 143:86740a56073b 4217 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
AnnaBridge 143:86740a56073b 4218
AnnaBridge 143:86740a56073b 4219 /* Register: FICR_TEMP_A0 */
AnnaBridge 143:86740a56073b 4220 /* Description: Slope definition A0. */
AnnaBridge 143:86740a56073b 4221
AnnaBridge 143:86740a56073b 4222 /* Bits 11..0 : A (slope definition) register. */
AnnaBridge 143:86740a56073b 4223 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
AnnaBridge 143:86740a56073b 4224 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
AnnaBridge 143:86740a56073b 4225
AnnaBridge 143:86740a56073b 4226 /* Register: FICR_TEMP_A1 */
AnnaBridge 143:86740a56073b 4227 /* Description: Slope definition A1. */
AnnaBridge 143:86740a56073b 4228
AnnaBridge 143:86740a56073b 4229 /* Bits 11..0 : A (slope definition) register. */
AnnaBridge 143:86740a56073b 4230 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
AnnaBridge 143:86740a56073b 4231 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
AnnaBridge 143:86740a56073b 4232
AnnaBridge 143:86740a56073b 4233 /* Register: FICR_TEMP_A2 */
AnnaBridge 143:86740a56073b 4234 /* Description: Slope definition A2. */
AnnaBridge 143:86740a56073b 4235
AnnaBridge 143:86740a56073b 4236 /* Bits 11..0 : A (slope definition) register. */
AnnaBridge 143:86740a56073b 4237 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
AnnaBridge 143:86740a56073b 4238 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
AnnaBridge 143:86740a56073b 4239
AnnaBridge 143:86740a56073b 4240 /* Register: FICR_TEMP_A3 */
AnnaBridge 143:86740a56073b 4241 /* Description: Slope definition A3. */
AnnaBridge 143:86740a56073b 4242
AnnaBridge 143:86740a56073b 4243 /* Bits 11..0 : A (slope definition) register. */
AnnaBridge 143:86740a56073b 4244 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
AnnaBridge 143:86740a56073b 4245 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
AnnaBridge 143:86740a56073b 4246
AnnaBridge 143:86740a56073b 4247 /* Register: FICR_TEMP_A4 */
AnnaBridge 143:86740a56073b 4248 /* Description: Slope definition A4. */
AnnaBridge 143:86740a56073b 4249
AnnaBridge 143:86740a56073b 4250 /* Bits 11..0 : A (slope definition) register. */
AnnaBridge 143:86740a56073b 4251 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
AnnaBridge 143:86740a56073b 4252 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
AnnaBridge 143:86740a56073b 4253
AnnaBridge 143:86740a56073b 4254 /* Register: FICR_TEMP_A5 */
AnnaBridge 143:86740a56073b 4255 /* Description: Slope definition A5. */
AnnaBridge 143:86740a56073b 4256
AnnaBridge 143:86740a56073b 4257 /* Bits 11..0 : A (slope definition) register. */
AnnaBridge 143:86740a56073b 4258 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
AnnaBridge 143:86740a56073b 4259 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
AnnaBridge 143:86740a56073b 4260
AnnaBridge 143:86740a56073b 4261 /* Register: FICR_TEMP_B0 */
AnnaBridge 143:86740a56073b 4262 /* Description: y-intercept B0. */
AnnaBridge 143:86740a56073b 4263
AnnaBridge 143:86740a56073b 4264 /* Bits 13..0 : B (y-intercept) */
AnnaBridge 143:86740a56073b 4265 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
AnnaBridge 143:86740a56073b 4266 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
AnnaBridge 143:86740a56073b 4267
AnnaBridge 143:86740a56073b 4268 /* Register: FICR_TEMP_B1 */
AnnaBridge 143:86740a56073b 4269 /* Description: y-intercept B1. */
AnnaBridge 143:86740a56073b 4270
AnnaBridge 143:86740a56073b 4271 /* Bits 13..0 : B (y-intercept) */
AnnaBridge 143:86740a56073b 4272 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
AnnaBridge 143:86740a56073b 4273 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
AnnaBridge 143:86740a56073b 4274
AnnaBridge 143:86740a56073b 4275 /* Register: FICR_TEMP_B2 */
AnnaBridge 143:86740a56073b 4276 /* Description: y-intercept B2. */
AnnaBridge 143:86740a56073b 4277
AnnaBridge 143:86740a56073b 4278 /* Bits 13..0 : B (y-intercept) */
AnnaBridge 143:86740a56073b 4279 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
AnnaBridge 143:86740a56073b 4280 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
AnnaBridge 143:86740a56073b 4281
AnnaBridge 143:86740a56073b 4282 /* Register: FICR_TEMP_B3 */
AnnaBridge 143:86740a56073b 4283 /* Description: y-intercept B3. */
AnnaBridge 143:86740a56073b 4284
AnnaBridge 143:86740a56073b 4285 /* Bits 13..0 : B (y-intercept) */
AnnaBridge 143:86740a56073b 4286 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
AnnaBridge 143:86740a56073b 4287 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
AnnaBridge 143:86740a56073b 4288
AnnaBridge 143:86740a56073b 4289 /* Register: FICR_TEMP_B4 */
AnnaBridge 143:86740a56073b 4290 /* Description: y-intercept B4. */
AnnaBridge 143:86740a56073b 4291
AnnaBridge 143:86740a56073b 4292 /* Bits 13..0 : B (y-intercept) */
AnnaBridge 143:86740a56073b 4293 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
AnnaBridge 143:86740a56073b 4294 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
AnnaBridge 143:86740a56073b 4295
AnnaBridge 143:86740a56073b 4296 /* Register: FICR_TEMP_B5 */
AnnaBridge 143:86740a56073b 4297 /* Description: y-intercept B5. */
AnnaBridge 143:86740a56073b 4298
AnnaBridge 143:86740a56073b 4299 /* Bits 13..0 : B (y-intercept) */
AnnaBridge 143:86740a56073b 4300 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
AnnaBridge 143:86740a56073b 4301 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
AnnaBridge 143:86740a56073b 4302
AnnaBridge 143:86740a56073b 4303 /* Register: FICR_TEMP_T0 */
AnnaBridge 143:86740a56073b 4304 /* Description: Segment end T0. */
AnnaBridge 143:86740a56073b 4305
AnnaBridge 143:86740a56073b 4306 /* Bits 7..0 : T (segment end)register. */
AnnaBridge 143:86740a56073b 4307 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
AnnaBridge 143:86740a56073b 4308 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
AnnaBridge 143:86740a56073b 4309
AnnaBridge 143:86740a56073b 4310 /* Register: FICR_TEMP_T1 */
AnnaBridge 143:86740a56073b 4311 /* Description: Segment end T1. */
AnnaBridge 143:86740a56073b 4312
AnnaBridge 143:86740a56073b 4313 /* Bits 7..0 : T (segment end)register. */
AnnaBridge 143:86740a56073b 4314 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
AnnaBridge 143:86740a56073b 4315 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
AnnaBridge 143:86740a56073b 4316
AnnaBridge 143:86740a56073b 4317 /* Register: FICR_TEMP_T2 */
AnnaBridge 143:86740a56073b 4318 /* Description: Segment end T2. */
AnnaBridge 143:86740a56073b 4319
AnnaBridge 143:86740a56073b 4320 /* Bits 7..0 : T (segment end)register. */
AnnaBridge 143:86740a56073b 4321 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
AnnaBridge 143:86740a56073b 4322 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
AnnaBridge 143:86740a56073b 4323
AnnaBridge 143:86740a56073b 4324 /* Register: FICR_TEMP_T3 */
AnnaBridge 143:86740a56073b 4325 /* Description: Segment end T3. */
AnnaBridge 143:86740a56073b 4326
AnnaBridge 143:86740a56073b 4327 /* Bits 7..0 : T (segment end)register. */
AnnaBridge 143:86740a56073b 4328 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
AnnaBridge 143:86740a56073b 4329 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
AnnaBridge 143:86740a56073b 4330
AnnaBridge 143:86740a56073b 4331 /* Register: FICR_TEMP_T4 */
AnnaBridge 143:86740a56073b 4332 /* Description: Segment end T4. */
AnnaBridge 143:86740a56073b 4333
AnnaBridge 143:86740a56073b 4334 /* Bits 7..0 : T (segment end)register. */
AnnaBridge 143:86740a56073b 4335 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
AnnaBridge 143:86740a56073b 4336 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
AnnaBridge 143:86740a56073b 4337
AnnaBridge 143:86740a56073b 4338 /* Register: FICR_NFC_TAGHEADER0 */
AnnaBridge 143:86740a56073b 4339 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
AnnaBridge 143:86740a56073b 4340
AnnaBridge 143:86740a56073b 4341 /* Bits 31..24 : Unique identifier byte 3 */
AnnaBridge 143:86740a56073b 4342 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
AnnaBridge 143:86740a56073b 4343 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
AnnaBridge 143:86740a56073b 4344
AnnaBridge 143:86740a56073b 4345 /* Bits 23..16 : Unique identifier byte 2 */
AnnaBridge 143:86740a56073b 4346 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
AnnaBridge 143:86740a56073b 4347 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
AnnaBridge 143:86740a56073b 4348
AnnaBridge 143:86740a56073b 4349 /* Bits 15..8 : Unique identifier byte 1 */
AnnaBridge 143:86740a56073b 4350 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
AnnaBridge 143:86740a56073b 4351 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
AnnaBridge 143:86740a56073b 4352
AnnaBridge 143:86740a56073b 4353 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
AnnaBridge 143:86740a56073b 4354 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
AnnaBridge 143:86740a56073b 4355 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
AnnaBridge 143:86740a56073b 4356
AnnaBridge 143:86740a56073b 4357 /* Register: FICR_NFC_TAGHEADER1 */
AnnaBridge 143:86740a56073b 4358 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
AnnaBridge 143:86740a56073b 4359
AnnaBridge 143:86740a56073b 4360 /* Bits 31..24 : Unique identifier byte 7 */
AnnaBridge 143:86740a56073b 4361 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
AnnaBridge 143:86740a56073b 4362 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
AnnaBridge 143:86740a56073b 4363
AnnaBridge 143:86740a56073b 4364 /* Bits 23..16 : Unique identifier byte 6 */
AnnaBridge 143:86740a56073b 4365 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
AnnaBridge 143:86740a56073b 4366 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
AnnaBridge 143:86740a56073b 4367
AnnaBridge 143:86740a56073b 4368 /* Bits 15..8 : Unique identifier byte 5 */
AnnaBridge 143:86740a56073b 4369 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
AnnaBridge 143:86740a56073b 4370 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
AnnaBridge 143:86740a56073b 4371
AnnaBridge 143:86740a56073b 4372 /* Bits 7..0 : Unique identifier byte 4 */
AnnaBridge 143:86740a56073b 4373 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
AnnaBridge 143:86740a56073b 4374 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
AnnaBridge 143:86740a56073b 4375
AnnaBridge 143:86740a56073b 4376 /* Register: FICR_NFC_TAGHEADER2 */
AnnaBridge 143:86740a56073b 4377 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
AnnaBridge 143:86740a56073b 4378
AnnaBridge 143:86740a56073b 4379 /* Bits 31..24 : Unique identifier byte 11 */
AnnaBridge 143:86740a56073b 4380 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
AnnaBridge 143:86740a56073b 4381 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
AnnaBridge 143:86740a56073b 4382
AnnaBridge 143:86740a56073b 4383 /* Bits 23..16 : Unique identifier byte 10 */
AnnaBridge 143:86740a56073b 4384 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
AnnaBridge 143:86740a56073b 4385 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
AnnaBridge 143:86740a56073b 4386
AnnaBridge 143:86740a56073b 4387 /* Bits 15..8 : Unique identifier byte 9 */
AnnaBridge 143:86740a56073b 4388 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
AnnaBridge 143:86740a56073b 4389 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
AnnaBridge 143:86740a56073b 4390
AnnaBridge 143:86740a56073b 4391 /* Bits 7..0 : Unique identifier byte 8 */
AnnaBridge 143:86740a56073b 4392 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
AnnaBridge 143:86740a56073b 4393 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
AnnaBridge 143:86740a56073b 4394
AnnaBridge 143:86740a56073b 4395 /* Register: FICR_NFC_TAGHEADER3 */
AnnaBridge 143:86740a56073b 4396 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
AnnaBridge 143:86740a56073b 4397
AnnaBridge 143:86740a56073b 4398 /* Bits 31..24 : Unique identifier byte 15 */
AnnaBridge 143:86740a56073b 4399 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
AnnaBridge 143:86740a56073b 4400 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
AnnaBridge 143:86740a56073b 4401
AnnaBridge 143:86740a56073b 4402 /* Bits 23..16 : Unique identifier byte 14 */
AnnaBridge 143:86740a56073b 4403 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
AnnaBridge 143:86740a56073b 4404 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
AnnaBridge 143:86740a56073b 4405
AnnaBridge 143:86740a56073b 4406 /* Bits 15..8 : Unique identifier byte 13 */
AnnaBridge 143:86740a56073b 4407 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
AnnaBridge 143:86740a56073b 4408 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
AnnaBridge 143:86740a56073b 4409
AnnaBridge 143:86740a56073b 4410 /* Bits 7..0 : Unique identifier byte 12 */
AnnaBridge 143:86740a56073b 4411 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
AnnaBridge 143:86740a56073b 4412 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
AnnaBridge 143:86740a56073b 4413
AnnaBridge 143:86740a56073b 4414
AnnaBridge 143:86740a56073b 4415 /* Peripheral: GPIOTE */
AnnaBridge 143:86740a56073b 4416 /* Description: GPIO Tasks and Events */
AnnaBridge 143:86740a56073b 4417
AnnaBridge 143:86740a56073b 4418 /* Register: GPIOTE_INTENSET */
AnnaBridge 143:86740a56073b 4419 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 4420
AnnaBridge 143:86740a56073b 4421 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
AnnaBridge 143:86740a56073b 4422 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
AnnaBridge 143:86740a56073b 4423 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
AnnaBridge 143:86740a56073b 4424 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4425 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4426 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4427
AnnaBridge 143:86740a56073b 4428 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
AnnaBridge 143:86740a56073b 4429 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
AnnaBridge 143:86740a56073b 4430 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
AnnaBridge 143:86740a56073b 4431 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4432 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4433 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4434
AnnaBridge 143:86740a56073b 4435 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
AnnaBridge 143:86740a56073b 4436 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
AnnaBridge 143:86740a56073b 4437 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
AnnaBridge 143:86740a56073b 4438 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4439 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4440 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4441
AnnaBridge 143:86740a56073b 4442 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
AnnaBridge 143:86740a56073b 4443 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
AnnaBridge 143:86740a56073b 4444 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
AnnaBridge 143:86740a56073b 4445 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4446 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4447 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4448
AnnaBridge 143:86740a56073b 4449 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
AnnaBridge 143:86740a56073b 4450 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
AnnaBridge 143:86740a56073b 4451 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
AnnaBridge 143:86740a56073b 4452 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4453 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4454 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4455
AnnaBridge 143:86740a56073b 4456 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
AnnaBridge 143:86740a56073b 4457 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
AnnaBridge 143:86740a56073b 4458 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
AnnaBridge 143:86740a56073b 4459 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4460 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4461 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4462
AnnaBridge 143:86740a56073b 4463 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
AnnaBridge 143:86740a56073b 4464 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
AnnaBridge 143:86740a56073b 4465 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
AnnaBridge 143:86740a56073b 4466 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4467 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4468 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4469
AnnaBridge 143:86740a56073b 4470 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
AnnaBridge 143:86740a56073b 4471 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
AnnaBridge 143:86740a56073b 4472 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
AnnaBridge 143:86740a56073b 4473 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4474 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4475 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4476
AnnaBridge 143:86740a56073b 4477 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
AnnaBridge 143:86740a56073b 4478 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
AnnaBridge 143:86740a56073b 4479 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
AnnaBridge 143:86740a56073b 4480 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4481 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4482 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4483
AnnaBridge 143:86740a56073b 4484 /* Register: GPIOTE_INTENCLR */
AnnaBridge 143:86740a56073b 4485 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 4486
AnnaBridge 143:86740a56073b 4487 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
AnnaBridge 143:86740a56073b 4488 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
AnnaBridge 143:86740a56073b 4489 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
AnnaBridge 143:86740a56073b 4490 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4491 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4492 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4493
AnnaBridge 143:86740a56073b 4494 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
AnnaBridge 143:86740a56073b 4495 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
AnnaBridge 143:86740a56073b 4496 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
AnnaBridge 143:86740a56073b 4497 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4498 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4499 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4500
AnnaBridge 143:86740a56073b 4501 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
AnnaBridge 143:86740a56073b 4502 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
AnnaBridge 143:86740a56073b 4503 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
AnnaBridge 143:86740a56073b 4504 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4505 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4506 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4507
AnnaBridge 143:86740a56073b 4508 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
AnnaBridge 143:86740a56073b 4509 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
AnnaBridge 143:86740a56073b 4510 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
AnnaBridge 143:86740a56073b 4511 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4512 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4513 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4514
AnnaBridge 143:86740a56073b 4515 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
AnnaBridge 143:86740a56073b 4516 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
AnnaBridge 143:86740a56073b 4517 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
AnnaBridge 143:86740a56073b 4518 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4519 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4520 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4521
AnnaBridge 143:86740a56073b 4522 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
AnnaBridge 143:86740a56073b 4523 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
AnnaBridge 143:86740a56073b 4524 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
AnnaBridge 143:86740a56073b 4525 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4526 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4527 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4528
AnnaBridge 143:86740a56073b 4529 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
AnnaBridge 143:86740a56073b 4530 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
AnnaBridge 143:86740a56073b 4531 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
AnnaBridge 143:86740a56073b 4532 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4533 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4534 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4535
AnnaBridge 143:86740a56073b 4536 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
AnnaBridge 143:86740a56073b 4537 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
AnnaBridge 143:86740a56073b 4538 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
AnnaBridge 143:86740a56073b 4539 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4540 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4541 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4542
AnnaBridge 143:86740a56073b 4543 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
AnnaBridge 143:86740a56073b 4544 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
AnnaBridge 143:86740a56073b 4545 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
AnnaBridge 143:86740a56073b 4546 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4547 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4548 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4549
AnnaBridge 143:86740a56073b 4550 /* Register: GPIOTE_CONFIG */
AnnaBridge 143:86740a56073b 4551 /* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
AnnaBridge 143:86740a56073b 4552
AnnaBridge 143:86740a56073b 4553 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
AnnaBridge 143:86740a56073b 4554 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
AnnaBridge 143:86740a56073b 4555 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
AnnaBridge 143:86740a56073b 4556 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
AnnaBridge 143:86740a56073b 4557 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
AnnaBridge 143:86740a56073b 4558
AnnaBridge 143:86740a56073b 4559 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
AnnaBridge 143:86740a56073b 4560 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
AnnaBridge 143:86740a56073b 4561 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
AnnaBridge 143:86740a56073b 4562 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
AnnaBridge 143:86740a56073b 4563 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
AnnaBridge 143:86740a56073b 4564 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
AnnaBridge 143:86740a56073b 4565 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
AnnaBridge 143:86740a56073b 4566
AnnaBridge 143:86740a56073b 4567 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
AnnaBridge 143:86740a56073b 4568 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
AnnaBridge 143:86740a56073b 4569 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
AnnaBridge 143:86740a56073b 4570
AnnaBridge 143:86740a56073b 4571 /* Bits 1..0 : Mode */
AnnaBridge 143:86740a56073b 4572 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 4573 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 4574 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
AnnaBridge 143:86740a56073b 4575 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
AnnaBridge 143:86740a56073b 4576 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
AnnaBridge 143:86740a56073b 4577
AnnaBridge 143:86740a56073b 4578
AnnaBridge 143:86740a56073b 4579 /* Peripheral: I2S */
AnnaBridge 143:86740a56073b 4580 /* Description: Inter-IC Sound */
AnnaBridge 143:86740a56073b 4581
AnnaBridge 143:86740a56073b 4582 /* Register: I2S_INTEN */
AnnaBridge 143:86740a56073b 4583 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 4584
AnnaBridge 143:86740a56073b 4585 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
AnnaBridge 143:86740a56073b 4586 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
AnnaBridge 143:86740a56073b 4587 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
AnnaBridge 143:86740a56073b 4588 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4589 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4590
AnnaBridge 143:86740a56073b 4591 /* Bit 2 : Enable or disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 4592 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 4593 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 4594 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4595 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4596
AnnaBridge 143:86740a56073b 4597 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
AnnaBridge 143:86740a56073b 4598 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
AnnaBridge 143:86740a56073b 4599 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
AnnaBridge 143:86740a56073b 4600 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4601 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4602
AnnaBridge 143:86740a56073b 4603 /* Register: I2S_INTENSET */
AnnaBridge 143:86740a56073b 4604 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 4605
AnnaBridge 143:86740a56073b 4606 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
AnnaBridge 143:86740a56073b 4607 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
AnnaBridge 143:86740a56073b 4608 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
AnnaBridge 143:86740a56073b 4609 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4610 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4611 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4612
AnnaBridge 143:86740a56073b 4613 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 4614 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 4615 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 4616 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4617 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4618 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4619
AnnaBridge 143:86740a56073b 4620 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
AnnaBridge 143:86740a56073b 4621 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
AnnaBridge 143:86740a56073b 4622 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
AnnaBridge 143:86740a56073b 4623 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4624 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4625 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4626
AnnaBridge 143:86740a56073b 4627 /* Register: I2S_INTENCLR */
AnnaBridge 143:86740a56073b 4628 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 4629
AnnaBridge 143:86740a56073b 4630 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
AnnaBridge 143:86740a56073b 4631 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
AnnaBridge 143:86740a56073b 4632 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
AnnaBridge 143:86740a56073b 4633 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4634 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4635 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4636
AnnaBridge 143:86740a56073b 4637 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 4638 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 4639 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 4640 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4641 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4642 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4643
AnnaBridge 143:86740a56073b 4644 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
AnnaBridge 143:86740a56073b 4645 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
AnnaBridge 143:86740a56073b 4646 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
AnnaBridge 143:86740a56073b 4647 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4648 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4649 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4650
AnnaBridge 143:86740a56073b 4651 /* Register: I2S_ENABLE */
AnnaBridge 143:86740a56073b 4652 /* Description: Enable I2S module. */
AnnaBridge 143:86740a56073b 4653
AnnaBridge 143:86740a56073b 4654 /* Bit 0 : Enable I2S module. */
AnnaBridge 143:86740a56073b 4655 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 4656 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 4657 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4658 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4659
AnnaBridge 143:86740a56073b 4660 /* Register: I2S_CONFIG_MODE */
AnnaBridge 143:86740a56073b 4661 /* Description: I2S mode. */
AnnaBridge 143:86740a56073b 4662
AnnaBridge 143:86740a56073b 4663 /* Bit 0 : I2S mode. */
AnnaBridge 143:86740a56073b 4664 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 4665 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 4666 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
AnnaBridge 143:86740a56073b 4667 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
AnnaBridge 143:86740a56073b 4668
AnnaBridge 143:86740a56073b 4669 /* Register: I2S_CONFIG_RXEN */
AnnaBridge 143:86740a56073b 4670 /* Description: Reception (RX) enable. */
AnnaBridge 143:86740a56073b 4671
AnnaBridge 143:86740a56073b 4672 /* Bit 0 : Reception (RX) enable. */
AnnaBridge 143:86740a56073b 4673 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
AnnaBridge 143:86740a56073b 4674 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
AnnaBridge 143:86740a56073b 4675 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
AnnaBridge 143:86740a56073b 4676 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 4677
AnnaBridge 143:86740a56073b 4678 /* Register: I2S_CONFIG_TXEN */
AnnaBridge 143:86740a56073b 4679 /* Description: Transmission (TX) enable. */
AnnaBridge 143:86740a56073b 4680
AnnaBridge 143:86740a56073b 4681 /* Bit 0 : Transmission (TX) enable. */
AnnaBridge 143:86740a56073b 4682 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
AnnaBridge 143:86740a56073b 4683 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
AnnaBridge 143:86740a56073b 4684 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
AnnaBridge 143:86740a56073b 4685 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
AnnaBridge 143:86740a56073b 4686
AnnaBridge 143:86740a56073b 4687 /* Register: I2S_CONFIG_MCKEN */
AnnaBridge 143:86740a56073b 4688 /* Description: Master clock generator enable. */
AnnaBridge 143:86740a56073b 4689
AnnaBridge 143:86740a56073b 4690 /* Bit 0 : Master clock generator enable. */
AnnaBridge 143:86740a56073b 4691 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
AnnaBridge 143:86740a56073b 4692 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
AnnaBridge 143:86740a56073b 4693 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
AnnaBridge 143:86740a56073b 4694 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
AnnaBridge 143:86740a56073b 4695
AnnaBridge 143:86740a56073b 4696 /* Register: I2S_CONFIG_MCKFREQ */
AnnaBridge 143:86740a56073b 4697 /* Description: Master clock generator frequency. */
AnnaBridge 143:86740a56073b 4698
AnnaBridge 143:86740a56073b 4699 /* Bits 31..0 : Master clock generator frequency. */
AnnaBridge 143:86740a56073b 4700 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
AnnaBridge 143:86740a56073b 4701 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
AnnaBridge 143:86740a56073b 4702 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
AnnaBridge 143:86740a56073b 4703 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
AnnaBridge 143:86740a56073b 4704 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
AnnaBridge 143:86740a56073b 4705 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
AnnaBridge 143:86740a56073b 4706 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
AnnaBridge 143:86740a56073b 4707 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
AnnaBridge 143:86740a56073b 4708 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
AnnaBridge 143:86740a56073b 4709 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
AnnaBridge 143:86740a56073b 4710 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
AnnaBridge 143:86740a56073b 4711 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
AnnaBridge 143:86740a56073b 4712 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
AnnaBridge 143:86740a56073b 4713 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
AnnaBridge 143:86740a56073b 4714 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
AnnaBridge 143:86740a56073b 4715 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
AnnaBridge 143:86740a56073b 4716 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
AnnaBridge 143:86740a56073b 4717 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
AnnaBridge 143:86740a56073b 4718 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
AnnaBridge 143:86740a56073b 4719 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
AnnaBridge 143:86740a56073b 4720
AnnaBridge 143:86740a56073b 4721 /* Register: I2S_CONFIG_RATIO */
AnnaBridge 143:86740a56073b 4722 /* Description: MCK / LRCK ratio. */
AnnaBridge 143:86740a56073b 4723
AnnaBridge 143:86740a56073b 4724 /* Bits 3..0 : MCK / LRCK ratio. */
AnnaBridge 143:86740a56073b 4725 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
AnnaBridge 143:86740a56073b 4726 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
AnnaBridge 143:86740a56073b 4727 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
AnnaBridge 143:86740a56073b 4728 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
AnnaBridge 143:86740a56073b 4729 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
AnnaBridge 143:86740a56073b 4730 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
AnnaBridge 143:86740a56073b 4731 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
AnnaBridge 143:86740a56073b 4732 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
AnnaBridge 143:86740a56073b 4733 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
AnnaBridge 143:86740a56073b 4734 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
AnnaBridge 143:86740a56073b 4735 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
AnnaBridge 143:86740a56073b 4736
AnnaBridge 143:86740a56073b 4737 /* Register: I2S_CONFIG_SWIDTH */
AnnaBridge 143:86740a56073b 4738 /* Description: Sample width. */
AnnaBridge 143:86740a56073b 4739
AnnaBridge 143:86740a56073b 4740 /* Bits 1..0 : Sample width. */
AnnaBridge 143:86740a56073b 4741 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
AnnaBridge 143:86740a56073b 4742 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
AnnaBridge 143:86740a56073b 4743 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
AnnaBridge 143:86740a56073b 4744 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
AnnaBridge 143:86740a56073b 4745 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
AnnaBridge 143:86740a56073b 4746
AnnaBridge 143:86740a56073b 4747 /* Register: I2S_CONFIG_ALIGN */
AnnaBridge 143:86740a56073b 4748 /* Description: Alignment of sample within a frame. */
AnnaBridge 143:86740a56073b 4749
AnnaBridge 143:86740a56073b 4750 /* Bit 0 : Alignment of sample within a frame. */
AnnaBridge 143:86740a56073b 4751 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
AnnaBridge 143:86740a56073b 4752 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
AnnaBridge 143:86740a56073b 4753 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
AnnaBridge 143:86740a56073b 4754 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
AnnaBridge 143:86740a56073b 4755
AnnaBridge 143:86740a56073b 4756 /* Register: I2S_CONFIG_FORMAT */
AnnaBridge 143:86740a56073b 4757 /* Description: Frame format. */
AnnaBridge 143:86740a56073b 4758
AnnaBridge 143:86740a56073b 4759 /* Bit 0 : Frame format. */
AnnaBridge 143:86740a56073b 4760 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
AnnaBridge 143:86740a56073b 4761 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
AnnaBridge 143:86740a56073b 4762 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
AnnaBridge 143:86740a56073b 4763 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
AnnaBridge 143:86740a56073b 4764
AnnaBridge 143:86740a56073b 4765 /* Register: I2S_CONFIG_CHANNELS */
AnnaBridge 143:86740a56073b 4766 /* Description: Enable channels. */
AnnaBridge 143:86740a56073b 4767
AnnaBridge 143:86740a56073b 4768 /* Bits 1..0 : Enable channels. */
AnnaBridge 143:86740a56073b 4769 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
AnnaBridge 143:86740a56073b 4770 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
AnnaBridge 143:86740a56073b 4771 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
AnnaBridge 143:86740a56073b 4772 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
AnnaBridge 143:86740a56073b 4773 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
AnnaBridge 143:86740a56073b 4774
AnnaBridge 143:86740a56073b 4775 /* Register: I2S_RXD_PTR */
AnnaBridge 143:86740a56073b 4776 /* Description: Receive buffer RAM start address. */
AnnaBridge 143:86740a56073b 4777
AnnaBridge 143:86740a56073b 4778 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
AnnaBridge 143:86740a56073b 4779 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 4780 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 4781
AnnaBridge 143:86740a56073b 4782 /* Register: I2S_TXD_PTR */
AnnaBridge 143:86740a56073b 4783 /* Description: Transmit buffer RAM start address. */
AnnaBridge 143:86740a56073b 4784
AnnaBridge 143:86740a56073b 4785 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
AnnaBridge 143:86740a56073b 4786 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 4787 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 4788
AnnaBridge 143:86740a56073b 4789 /* Register: I2S_RXTXD_MAXCNT */
AnnaBridge 143:86740a56073b 4790 /* Description: Size of RXD and TXD buffers. */
AnnaBridge 143:86740a56073b 4791
AnnaBridge 143:86740a56073b 4792 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
AnnaBridge 143:86740a56073b 4793 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 4794 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 4795
AnnaBridge 143:86740a56073b 4796 /* Register: I2S_PSEL_MCK */
AnnaBridge 143:86740a56073b 4797 /* Description: Pin select for MCK signal. */
AnnaBridge 143:86740a56073b 4798
AnnaBridge 143:86740a56073b 4799 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 4800 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 4801 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 4802 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 4803 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 4804
AnnaBridge 143:86740a56073b 4805 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 4806 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 4807 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 4808
AnnaBridge 143:86740a56073b 4809 /* Register: I2S_PSEL_SCK */
AnnaBridge 143:86740a56073b 4810 /* Description: Pin select for SCK signal. */
AnnaBridge 143:86740a56073b 4811
AnnaBridge 143:86740a56073b 4812 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 4813 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 4814 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 4815 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 4816 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 4817
AnnaBridge 143:86740a56073b 4818 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 4819 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 4820 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 4821
AnnaBridge 143:86740a56073b 4822 /* Register: I2S_PSEL_LRCK */
AnnaBridge 143:86740a56073b 4823 /* Description: Pin select for LRCK signal. */
AnnaBridge 143:86740a56073b 4824
AnnaBridge 143:86740a56073b 4825 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 4826 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 4827 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 4828 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 4829 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 4830
AnnaBridge 143:86740a56073b 4831 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 4832 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 4833 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 4834
AnnaBridge 143:86740a56073b 4835 /* Register: I2S_PSEL_SDIN */
AnnaBridge 143:86740a56073b 4836 /* Description: Pin select for SDIN signal. */
AnnaBridge 143:86740a56073b 4837
AnnaBridge 143:86740a56073b 4838 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 4839 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 4840 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 4841 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 4842 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 4843
AnnaBridge 143:86740a56073b 4844 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 4845 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 4846 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 4847
AnnaBridge 143:86740a56073b 4848 /* Register: I2S_PSEL_SDOUT */
AnnaBridge 143:86740a56073b 4849 /* Description: Pin select for SDOUT signal. */
AnnaBridge 143:86740a56073b 4850
AnnaBridge 143:86740a56073b 4851 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 4852 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 4853 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 4854 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 4855 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 4856
AnnaBridge 143:86740a56073b 4857 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 4858 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 4859 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 4860
AnnaBridge 143:86740a56073b 4861
AnnaBridge 143:86740a56073b 4862 /* Peripheral: LPCOMP */
AnnaBridge 143:86740a56073b 4863 /* Description: Low Power Comparator */
AnnaBridge 143:86740a56073b 4864
AnnaBridge 143:86740a56073b 4865 /* Register: LPCOMP_SHORTS */
AnnaBridge 143:86740a56073b 4866 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 4867
AnnaBridge 143:86740a56073b 4868 /* Bit 4 : Shortcut between CROSS event and STOP task */
AnnaBridge 143:86740a56073b 4869 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
AnnaBridge 143:86740a56073b 4870 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
AnnaBridge 143:86740a56073b 4871 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 4872 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 4873
AnnaBridge 143:86740a56073b 4874 /* Bit 3 : Shortcut between UP event and STOP task */
AnnaBridge 143:86740a56073b 4875 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
AnnaBridge 143:86740a56073b 4876 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
AnnaBridge 143:86740a56073b 4877 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 4878 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 4879
AnnaBridge 143:86740a56073b 4880 /* Bit 2 : Shortcut between DOWN event and STOP task */
AnnaBridge 143:86740a56073b 4881 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
AnnaBridge 143:86740a56073b 4882 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
AnnaBridge 143:86740a56073b 4883 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 4884 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 4885
AnnaBridge 143:86740a56073b 4886 /* Bit 1 : Shortcut between READY event and STOP task */
AnnaBridge 143:86740a56073b 4887 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
AnnaBridge 143:86740a56073b 4888 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
AnnaBridge 143:86740a56073b 4889 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 4890 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 4891
AnnaBridge 143:86740a56073b 4892 /* Bit 0 : Shortcut between READY event and SAMPLE task */
AnnaBridge 143:86740a56073b 4893 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
AnnaBridge 143:86740a56073b 4894 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
AnnaBridge 143:86740a56073b 4895 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 4896 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 4897
AnnaBridge 143:86740a56073b 4898 /* Register: LPCOMP_INTENSET */
AnnaBridge 143:86740a56073b 4899 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 4900
AnnaBridge 143:86740a56073b 4901 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
AnnaBridge 143:86740a56073b 4902 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
AnnaBridge 143:86740a56073b 4903 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
AnnaBridge 143:86740a56073b 4904 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4905 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4906 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4907
AnnaBridge 143:86740a56073b 4908 /* Bit 2 : Write '1' to Enable interrupt for UP event */
AnnaBridge 143:86740a56073b 4909 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
AnnaBridge 143:86740a56073b 4910 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
AnnaBridge 143:86740a56073b 4911 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4912 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4913 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4914
AnnaBridge 143:86740a56073b 4915 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
AnnaBridge 143:86740a56073b 4916 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
AnnaBridge 143:86740a56073b 4917 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
AnnaBridge 143:86740a56073b 4918 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4919 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4920 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4921
AnnaBridge 143:86740a56073b 4922 /* Bit 0 : Write '1' to Enable interrupt for READY event */
AnnaBridge 143:86740a56073b 4923 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 4924 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 4925 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4926 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4927 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4928
AnnaBridge 143:86740a56073b 4929 /* Register: LPCOMP_INTENCLR */
AnnaBridge 143:86740a56073b 4930 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 4931
AnnaBridge 143:86740a56073b 4932 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
AnnaBridge 143:86740a56073b 4933 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
AnnaBridge 143:86740a56073b 4934 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
AnnaBridge 143:86740a56073b 4935 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4936 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4937 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4938
AnnaBridge 143:86740a56073b 4939 /* Bit 2 : Write '1' to Disable interrupt for UP event */
AnnaBridge 143:86740a56073b 4940 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
AnnaBridge 143:86740a56073b 4941 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
AnnaBridge 143:86740a56073b 4942 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4943 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4944 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4945
AnnaBridge 143:86740a56073b 4946 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
AnnaBridge 143:86740a56073b 4947 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
AnnaBridge 143:86740a56073b 4948 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
AnnaBridge 143:86740a56073b 4949 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4950 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4951 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4952
AnnaBridge 143:86740a56073b 4953 /* Bit 0 : Write '1' to Disable interrupt for READY event */
AnnaBridge 143:86740a56073b 4954 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 4955 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 4956 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 4957 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 4958 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4959
AnnaBridge 143:86740a56073b 4960 /* Register: LPCOMP_RESULT */
AnnaBridge 143:86740a56073b 4961 /* Description: Compare result */
AnnaBridge 143:86740a56073b 4962
AnnaBridge 143:86740a56073b 4963 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
AnnaBridge 143:86740a56073b 4964 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
AnnaBridge 143:86740a56073b 4965 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
AnnaBridge 143:86740a56073b 4966 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
AnnaBridge 143:86740a56073b 4967 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
AnnaBridge 143:86740a56073b 4968
AnnaBridge 143:86740a56073b 4969 /* Register: LPCOMP_ENABLE */
AnnaBridge 143:86740a56073b 4970 /* Description: Enable LPCOMP */
AnnaBridge 143:86740a56073b 4971
AnnaBridge 143:86740a56073b 4972 /* Bits 1..0 : Enable or disable LPCOMP */
AnnaBridge 143:86740a56073b 4973 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 4974 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 4975 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 4976 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 4977
AnnaBridge 143:86740a56073b 4978 /* Register: LPCOMP_PSEL */
AnnaBridge 143:86740a56073b 4979 /* Description: Input pin select */
AnnaBridge 143:86740a56073b 4980
AnnaBridge 143:86740a56073b 4981 /* Bits 2..0 : Analog pin select */
AnnaBridge 143:86740a56073b 4982 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
AnnaBridge 143:86740a56073b 4983 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
AnnaBridge 143:86740a56073b 4984 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
AnnaBridge 143:86740a56073b 4985 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
AnnaBridge 143:86740a56073b 4986 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
AnnaBridge 143:86740a56073b 4987 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
AnnaBridge 143:86740a56073b 4988 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
AnnaBridge 143:86740a56073b 4989 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
AnnaBridge 143:86740a56073b 4990 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
AnnaBridge 143:86740a56073b 4991 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
AnnaBridge 143:86740a56073b 4992
AnnaBridge 143:86740a56073b 4993 /* Register: LPCOMP_REFSEL */
AnnaBridge 143:86740a56073b 4994 /* Description: Reference select */
AnnaBridge 143:86740a56073b 4995
AnnaBridge 143:86740a56073b 4996 /* Bits 3..0 : Reference select */
AnnaBridge 143:86740a56073b 4997 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
AnnaBridge 143:86740a56073b 4998 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
AnnaBridge 143:86740a56073b 4999 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
AnnaBridge 143:86740a56073b 5000 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
AnnaBridge 143:86740a56073b 5001 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
AnnaBridge 143:86740a56073b 5002 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
AnnaBridge 143:86740a56073b 5003 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
AnnaBridge 143:86740a56073b 5004 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
AnnaBridge 143:86740a56073b 5005 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
AnnaBridge 143:86740a56073b 5006 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
AnnaBridge 143:86740a56073b 5007 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
AnnaBridge 143:86740a56073b 5008 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
AnnaBridge 143:86740a56073b 5009 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
AnnaBridge 143:86740a56073b 5010 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
AnnaBridge 143:86740a56073b 5011 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
AnnaBridge 143:86740a56073b 5012 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
AnnaBridge 143:86740a56073b 5013 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
AnnaBridge 143:86740a56073b 5014 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
AnnaBridge 143:86740a56073b 5015
AnnaBridge 143:86740a56073b 5016 /* Register: LPCOMP_EXTREFSEL */
AnnaBridge 143:86740a56073b 5017 /* Description: External reference select */
AnnaBridge 143:86740a56073b 5018
AnnaBridge 143:86740a56073b 5019 /* Bit 0 : External analog reference select */
AnnaBridge 143:86740a56073b 5020 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 5021 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 5022 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
AnnaBridge 143:86740a56073b 5023 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
AnnaBridge 143:86740a56073b 5024
AnnaBridge 143:86740a56073b 5025 /* Register: LPCOMP_ANADETECT */
AnnaBridge 143:86740a56073b 5026 /* Description: Analog detect configuration */
AnnaBridge 143:86740a56073b 5027
AnnaBridge 143:86740a56073b 5028 /* Bits 1..0 : Analog detect configuration */
AnnaBridge 143:86740a56073b 5029 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
AnnaBridge 143:86740a56073b 5030 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
AnnaBridge 143:86740a56073b 5031 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
AnnaBridge 143:86740a56073b 5032 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
AnnaBridge 143:86740a56073b 5033 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
AnnaBridge 143:86740a56073b 5034
AnnaBridge 143:86740a56073b 5035 /* Register: LPCOMP_HYST */
AnnaBridge 143:86740a56073b 5036 /* Description: Comparator hysteresis enable */
AnnaBridge 143:86740a56073b 5037
AnnaBridge 143:86740a56073b 5038 /* Bit 0 : Comparator hysteresis enable */
AnnaBridge 143:86740a56073b 5039 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
AnnaBridge 143:86740a56073b 5040 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
AnnaBridge 143:86740a56073b 5041 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
AnnaBridge 143:86740a56073b 5042 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
AnnaBridge 143:86740a56073b 5043
AnnaBridge 143:86740a56073b 5044
AnnaBridge 143:86740a56073b 5045 /* Peripheral: MWU */
AnnaBridge 143:86740a56073b 5046 /* Description: Memory Watch Unit */
AnnaBridge 143:86740a56073b 5047
AnnaBridge 143:86740a56073b 5048 /* Register: MWU_INTEN */
AnnaBridge 143:86740a56073b 5049 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 5050
AnnaBridge 143:86740a56073b 5051 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
AnnaBridge 143:86740a56073b 5052 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5053 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5054 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5055 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5056
AnnaBridge 143:86740a56073b 5057 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
AnnaBridge 143:86740a56073b 5058 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5059 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5060 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5061 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5062
AnnaBridge 143:86740a56073b 5063 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
AnnaBridge 143:86740a56073b 5064 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5065 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5066 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5067 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5068
AnnaBridge 143:86740a56073b 5069 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
AnnaBridge 143:86740a56073b 5070 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5071 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5072 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5073 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5074
AnnaBridge 143:86740a56073b 5075 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
AnnaBridge 143:86740a56073b 5076 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
AnnaBridge 143:86740a56073b 5077 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
AnnaBridge 143:86740a56073b 5078 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5079 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5080
AnnaBridge 143:86740a56073b 5081 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
AnnaBridge 143:86740a56073b 5082 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
AnnaBridge 143:86740a56073b 5083 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
AnnaBridge 143:86740a56073b 5084 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5085 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5086
AnnaBridge 143:86740a56073b 5087 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
AnnaBridge 143:86740a56073b 5088 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
AnnaBridge 143:86740a56073b 5089 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
AnnaBridge 143:86740a56073b 5090 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5091 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5092
AnnaBridge 143:86740a56073b 5093 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
AnnaBridge 143:86740a56073b 5094 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
AnnaBridge 143:86740a56073b 5095 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
AnnaBridge 143:86740a56073b 5096 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5097 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5098
AnnaBridge 143:86740a56073b 5099 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
AnnaBridge 143:86740a56073b 5100 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
AnnaBridge 143:86740a56073b 5101 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
AnnaBridge 143:86740a56073b 5102 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5103 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5104
AnnaBridge 143:86740a56073b 5105 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
AnnaBridge 143:86740a56073b 5106 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
AnnaBridge 143:86740a56073b 5107 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
AnnaBridge 143:86740a56073b 5108 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5109 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5110
AnnaBridge 143:86740a56073b 5111 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
AnnaBridge 143:86740a56073b 5112 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
AnnaBridge 143:86740a56073b 5113 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
AnnaBridge 143:86740a56073b 5114 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5115 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5116
AnnaBridge 143:86740a56073b 5117 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
AnnaBridge 143:86740a56073b 5118 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
AnnaBridge 143:86740a56073b 5119 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
AnnaBridge 143:86740a56073b 5120 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5121 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5122
AnnaBridge 143:86740a56073b 5123 /* Register: MWU_INTENSET */
AnnaBridge 143:86740a56073b 5124 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 5125
AnnaBridge 143:86740a56073b 5126 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
AnnaBridge 143:86740a56073b 5127 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5128 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5129 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5130 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5131 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5132
AnnaBridge 143:86740a56073b 5133 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
AnnaBridge 143:86740a56073b 5134 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5135 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5136 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5137 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5138 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5139
AnnaBridge 143:86740a56073b 5140 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
AnnaBridge 143:86740a56073b 5141 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5142 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5143 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5144 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5145 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5146
AnnaBridge 143:86740a56073b 5147 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
AnnaBridge 143:86740a56073b 5148 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5149 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5150 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5151 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5152 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5153
AnnaBridge 143:86740a56073b 5154 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
AnnaBridge 143:86740a56073b 5155 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
AnnaBridge 143:86740a56073b 5156 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
AnnaBridge 143:86740a56073b 5157 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5158 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5159 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5160
AnnaBridge 143:86740a56073b 5161 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
AnnaBridge 143:86740a56073b 5162 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
AnnaBridge 143:86740a56073b 5163 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
AnnaBridge 143:86740a56073b 5164 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5165 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5166 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5167
AnnaBridge 143:86740a56073b 5168 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
AnnaBridge 143:86740a56073b 5169 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
AnnaBridge 143:86740a56073b 5170 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
AnnaBridge 143:86740a56073b 5171 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5172 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5173 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5174
AnnaBridge 143:86740a56073b 5175 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
AnnaBridge 143:86740a56073b 5176 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
AnnaBridge 143:86740a56073b 5177 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
AnnaBridge 143:86740a56073b 5178 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5179 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5180 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5181
AnnaBridge 143:86740a56073b 5182 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
AnnaBridge 143:86740a56073b 5183 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
AnnaBridge 143:86740a56073b 5184 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
AnnaBridge 143:86740a56073b 5185 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5186 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5187 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5188
AnnaBridge 143:86740a56073b 5189 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
AnnaBridge 143:86740a56073b 5190 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
AnnaBridge 143:86740a56073b 5191 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
AnnaBridge 143:86740a56073b 5192 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5193 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5194 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5195
AnnaBridge 143:86740a56073b 5196 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
AnnaBridge 143:86740a56073b 5197 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
AnnaBridge 143:86740a56073b 5198 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
AnnaBridge 143:86740a56073b 5199 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5200 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5201 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5202
AnnaBridge 143:86740a56073b 5203 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
AnnaBridge 143:86740a56073b 5204 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
AnnaBridge 143:86740a56073b 5205 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
AnnaBridge 143:86740a56073b 5206 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5207 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5208 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5209
AnnaBridge 143:86740a56073b 5210 /* Register: MWU_INTENCLR */
AnnaBridge 143:86740a56073b 5211 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 5212
AnnaBridge 143:86740a56073b 5213 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
AnnaBridge 143:86740a56073b 5214 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5215 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5216 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5217 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5218 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5219
AnnaBridge 143:86740a56073b 5220 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
AnnaBridge 143:86740a56073b 5221 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5222 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5223 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5224 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5225 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5226
AnnaBridge 143:86740a56073b 5227 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
AnnaBridge 143:86740a56073b 5228 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5229 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5230 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5231 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5232 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5233
AnnaBridge 143:86740a56073b 5234 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
AnnaBridge 143:86740a56073b 5235 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5236 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5237 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5238 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5239 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5240
AnnaBridge 143:86740a56073b 5241 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
AnnaBridge 143:86740a56073b 5242 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
AnnaBridge 143:86740a56073b 5243 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
AnnaBridge 143:86740a56073b 5244 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5245 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5246 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5247
AnnaBridge 143:86740a56073b 5248 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
AnnaBridge 143:86740a56073b 5249 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
AnnaBridge 143:86740a56073b 5250 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
AnnaBridge 143:86740a56073b 5251 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5252 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5253 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5254
AnnaBridge 143:86740a56073b 5255 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
AnnaBridge 143:86740a56073b 5256 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
AnnaBridge 143:86740a56073b 5257 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
AnnaBridge 143:86740a56073b 5258 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5259 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5260 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5261
AnnaBridge 143:86740a56073b 5262 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
AnnaBridge 143:86740a56073b 5263 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
AnnaBridge 143:86740a56073b 5264 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
AnnaBridge 143:86740a56073b 5265 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5266 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5267 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5268
AnnaBridge 143:86740a56073b 5269 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
AnnaBridge 143:86740a56073b 5270 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
AnnaBridge 143:86740a56073b 5271 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
AnnaBridge 143:86740a56073b 5272 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5273 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5274 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5275
AnnaBridge 143:86740a56073b 5276 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
AnnaBridge 143:86740a56073b 5277 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
AnnaBridge 143:86740a56073b 5278 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
AnnaBridge 143:86740a56073b 5279 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5280 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5281 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5282
AnnaBridge 143:86740a56073b 5283 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
AnnaBridge 143:86740a56073b 5284 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
AnnaBridge 143:86740a56073b 5285 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
AnnaBridge 143:86740a56073b 5286 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5287 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5288 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5289
AnnaBridge 143:86740a56073b 5290 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
AnnaBridge 143:86740a56073b 5291 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
AnnaBridge 143:86740a56073b 5292 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
AnnaBridge 143:86740a56073b 5293 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5294 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5295 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5296
AnnaBridge 143:86740a56073b 5297 /* Register: MWU_NMIEN */
AnnaBridge 143:86740a56073b 5298 /* Description: Enable or disable non-maskable interrupt */
AnnaBridge 143:86740a56073b 5299
AnnaBridge 143:86740a56073b 5300 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
AnnaBridge 143:86740a56073b 5301 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5302 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5303 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5304 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5305
AnnaBridge 143:86740a56073b 5306 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
AnnaBridge 143:86740a56073b 5307 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5308 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5309 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5310 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5311
AnnaBridge 143:86740a56073b 5312 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
AnnaBridge 143:86740a56073b 5313 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5314 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5315 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5316 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5317
AnnaBridge 143:86740a56073b 5318 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
AnnaBridge 143:86740a56073b 5319 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5320 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5321 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5322 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5323
AnnaBridge 143:86740a56073b 5324 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
AnnaBridge 143:86740a56073b 5325 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
AnnaBridge 143:86740a56073b 5326 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
AnnaBridge 143:86740a56073b 5327 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5328 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5329
AnnaBridge 143:86740a56073b 5330 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
AnnaBridge 143:86740a56073b 5331 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
AnnaBridge 143:86740a56073b 5332 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
AnnaBridge 143:86740a56073b 5333 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5334 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5335
AnnaBridge 143:86740a56073b 5336 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
AnnaBridge 143:86740a56073b 5337 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
AnnaBridge 143:86740a56073b 5338 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
AnnaBridge 143:86740a56073b 5339 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5340 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5341
AnnaBridge 143:86740a56073b 5342 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
AnnaBridge 143:86740a56073b 5343 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
AnnaBridge 143:86740a56073b 5344 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
AnnaBridge 143:86740a56073b 5345 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5346 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5347
AnnaBridge 143:86740a56073b 5348 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
AnnaBridge 143:86740a56073b 5349 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
AnnaBridge 143:86740a56073b 5350 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
AnnaBridge 143:86740a56073b 5351 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5352 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5353
AnnaBridge 143:86740a56073b 5354 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
AnnaBridge 143:86740a56073b 5355 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
AnnaBridge 143:86740a56073b 5356 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
AnnaBridge 143:86740a56073b 5357 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5358 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5359
AnnaBridge 143:86740a56073b 5360 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
AnnaBridge 143:86740a56073b 5361 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
AnnaBridge 143:86740a56073b 5362 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
AnnaBridge 143:86740a56073b 5363 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5364 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5365
AnnaBridge 143:86740a56073b 5366 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
AnnaBridge 143:86740a56073b 5367 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
AnnaBridge 143:86740a56073b 5368 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
AnnaBridge 143:86740a56073b 5369 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5370 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5371
AnnaBridge 143:86740a56073b 5372 /* Register: MWU_NMIENSET */
AnnaBridge 143:86740a56073b 5373 /* Description: Enable non-maskable interrupt */
AnnaBridge 143:86740a56073b 5374
AnnaBridge 143:86740a56073b 5375 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
AnnaBridge 143:86740a56073b 5376 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5377 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5378 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5379 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5380 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5381
AnnaBridge 143:86740a56073b 5382 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
AnnaBridge 143:86740a56073b 5383 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5384 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5385 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5386 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5387 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5388
AnnaBridge 143:86740a56073b 5389 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
AnnaBridge 143:86740a56073b 5390 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5391 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5392 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5393 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5394 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5395
AnnaBridge 143:86740a56073b 5396 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
AnnaBridge 143:86740a56073b 5397 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5398 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5399 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5400 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5401 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5402
AnnaBridge 143:86740a56073b 5403 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
AnnaBridge 143:86740a56073b 5404 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
AnnaBridge 143:86740a56073b 5405 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
AnnaBridge 143:86740a56073b 5406 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5407 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5408 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5409
AnnaBridge 143:86740a56073b 5410 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
AnnaBridge 143:86740a56073b 5411 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
AnnaBridge 143:86740a56073b 5412 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
AnnaBridge 143:86740a56073b 5413 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5414 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5415 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5416
AnnaBridge 143:86740a56073b 5417 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
AnnaBridge 143:86740a56073b 5418 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
AnnaBridge 143:86740a56073b 5419 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
AnnaBridge 143:86740a56073b 5420 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5421 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5422 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5423
AnnaBridge 143:86740a56073b 5424 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
AnnaBridge 143:86740a56073b 5425 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
AnnaBridge 143:86740a56073b 5426 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
AnnaBridge 143:86740a56073b 5427 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5428 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5429 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5430
AnnaBridge 143:86740a56073b 5431 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
AnnaBridge 143:86740a56073b 5432 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
AnnaBridge 143:86740a56073b 5433 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
AnnaBridge 143:86740a56073b 5434 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5435 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5436 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5437
AnnaBridge 143:86740a56073b 5438 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
AnnaBridge 143:86740a56073b 5439 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
AnnaBridge 143:86740a56073b 5440 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
AnnaBridge 143:86740a56073b 5441 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5442 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5443 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5444
AnnaBridge 143:86740a56073b 5445 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
AnnaBridge 143:86740a56073b 5446 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
AnnaBridge 143:86740a56073b 5447 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
AnnaBridge 143:86740a56073b 5448 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5449 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5450 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5451
AnnaBridge 143:86740a56073b 5452 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
AnnaBridge 143:86740a56073b 5453 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
AnnaBridge 143:86740a56073b 5454 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
AnnaBridge 143:86740a56073b 5455 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5456 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5457 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 5458
AnnaBridge 143:86740a56073b 5459 /* Register: MWU_NMIENCLR */
AnnaBridge 143:86740a56073b 5460 /* Description: Disable non-maskable interrupt */
AnnaBridge 143:86740a56073b 5461
AnnaBridge 143:86740a56073b 5462 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
AnnaBridge 143:86740a56073b 5463 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5464 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
AnnaBridge 143:86740a56073b 5465 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5466 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5467 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5468
AnnaBridge 143:86740a56073b 5469 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
AnnaBridge 143:86740a56073b 5470 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5471 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
AnnaBridge 143:86740a56073b 5472 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5473 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5474 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5475
AnnaBridge 143:86740a56073b 5476 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
AnnaBridge 143:86740a56073b 5477 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5478 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
AnnaBridge 143:86740a56073b 5479 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5480 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5481 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5482
AnnaBridge 143:86740a56073b 5483 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
AnnaBridge 143:86740a56073b 5484 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5485 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
AnnaBridge 143:86740a56073b 5486 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5487 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5488 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5489
AnnaBridge 143:86740a56073b 5490 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
AnnaBridge 143:86740a56073b 5491 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
AnnaBridge 143:86740a56073b 5492 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
AnnaBridge 143:86740a56073b 5493 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5494 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5495 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5496
AnnaBridge 143:86740a56073b 5497 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
AnnaBridge 143:86740a56073b 5498 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
AnnaBridge 143:86740a56073b 5499 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
AnnaBridge 143:86740a56073b 5500 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5501 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5502 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5503
AnnaBridge 143:86740a56073b 5504 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
AnnaBridge 143:86740a56073b 5505 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
AnnaBridge 143:86740a56073b 5506 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
AnnaBridge 143:86740a56073b 5507 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5508 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5509 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5510
AnnaBridge 143:86740a56073b 5511 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
AnnaBridge 143:86740a56073b 5512 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
AnnaBridge 143:86740a56073b 5513 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
AnnaBridge 143:86740a56073b 5514 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5515 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5516 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5517
AnnaBridge 143:86740a56073b 5518 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
AnnaBridge 143:86740a56073b 5519 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
AnnaBridge 143:86740a56073b 5520 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
AnnaBridge 143:86740a56073b 5521 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5522 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5523 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5524
AnnaBridge 143:86740a56073b 5525 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
AnnaBridge 143:86740a56073b 5526 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
AnnaBridge 143:86740a56073b 5527 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
AnnaBridge 143:86740a56073b 5528 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5529 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5530 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5531
AnnaBridge 143:86740a56073b 5532 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
AnnaBridge 143:86740a56073b 5533 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
AnnaBridge 143:86740a56073b 5534 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
AnnaBridge 143:86740a56073b 5535 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5536 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5537 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5538
AnnaBridge 143:86740a56073b 5539 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
AnnaBridge 143:86740a56073b 5540 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
AnnaBridge 143:86740a56073b 5541 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
AnnaBridge 143:86740a56073b 5542 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 5543 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 5544 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 5545
AnnaBridge 143:86740a56073b 5546 /* Register: MWU_PERREGION_SUBSTATWA */
AnnaBridge 143:86740a56073b 5547 /* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
AnnaBridge 143:86740a56073b 5548
AnnaBridge 143:86740a56073b 5549 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5550 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
AnnaBridge 143:86740a56073b 5551 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
AnnaBridge 143:86740a56073b 5552 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5553 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5554
AnnaBridge 143:86740a56073b 5555 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5556 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
AnnaBridge 143:86740a56073b 5557 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
AnnaBridge 143:86740a56073b 5558 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5559 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5560
AnnaBridge 143:86740a56073b 5561 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5562 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
AnnaBridge 143:86740a56073b 5563 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
AnnaBridge 143:86740a56073b 5564 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5565 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5566
AnnaBridge 143:86740a56073b 5567 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5568 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
AnnaBridge 143:86740a56073b 5569 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
AnnaBridge 143:86740a56073b 5570 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5571 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5572
AnnaBridge 143:86740a56073b 5573 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5574 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
AnnaBridge 143:86740a56073b 5575 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
AnnaBridge 143:86740a56073b 5576 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5577 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5578
AnnaBridge 143:86740a56073b 5579 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5580 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
AnnaBridge 143:86740a56073b 5581 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
AnnaBridge 143:86740a56073b 5582 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5583 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5584
AnnaBridge 143:86740a56073b 5585 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5586 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
AnnaBridge 143:86740a56073b 5587 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
AnnaBridge 143:86740a56073b 5588 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5589 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5590
AnnaBridge 143:86740a56073b 5591 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5592 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
AnnaBridge 143:86740a56073b 5593 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
AnnaBridge 143:86740a56073b 5594 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5595 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5596
AnnaBridge 143:86740a56073b 5597 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5598 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
AnnaBridge 143:86740a56073b 5599 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
AnnaBridge 143:86740a56073b 5600 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5601 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5602
AnnaBridge 143:86740a56073b 5603 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5604 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
AnnaBridge 143:86740a56073b 5605 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
AnnaBridge 143:86740a56073b 5606 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5607 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5608
AnnaBridge 143:86740a56073b 5609 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5610 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
AnnaBridge 143:86740a56073b 5611 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
AnnaBridge 143:86740a56073b 5612 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5613 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5614
AnnaBridge 143:86740a56073b 5615 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5616 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
AnnaBridge 143:86740a56073b 5617 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
AnnaBridge 143:86740a56073b 5618 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5619 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5620
AnnaBridge 143:86740a56073b 5621 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5622 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
AnnaBridge 143:86740a56073b 5623 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
AnnaBridge 143:86740a56073b 5624 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5625 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5626
AnnaBridge 143:86740a56073b 5627 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5628 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
AnnaBridge 143:86740a56073b 5629 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
AnnaBridge 143:86740a56073b 5630 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5631 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5632
AnnaBridge 143:86740a56073b 5633 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5634 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
AnnaBridge 143:86740a56073b 5635 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
AnnaBridge 143:86740a56073b 5636 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5637 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5638
AnnaBridge 143:86740a56073b 5639 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5640 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
AnnaBridge 143:86740a56073b 5641 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
AnnaBridge 143:86740a56073b 5642 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5643 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5644
AnnaBridge 143:86740a56073b 5645 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5646 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
AnnaBridge 143:86740a56073b 5647 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
AnnaBridge 143:86740a56073b 5648 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5649 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5650
AnnaBridge 143:86740a56073b 5651 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5652 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
AnnaBridge 143:86740a56073b 5653 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
AnnaBridge 143:86740a56073b 5654 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5655 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5656
AnnaBridge 143:86740a56073b 5657 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5658 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
AnnaBridge 143:86740a56073b 5659 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
AnnaBridge 143:86740a56073b 5660 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5661 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5662
AnnaBridge 143:86740a56073b 5663 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5664 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
AnnaBridge 143:86740a56073b 5665 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
AnnaBridge 143:86740a56073b 5666 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5667 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5668
AnnaBridge 143:86740a56073b 5669 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5670 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
AnnaBridge 143:86740a56073b 5671 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
AnnaBridge 143:86740a56073b 5672 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5673 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5674
AnnaBridge 143:86740a56073b 5675 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5676 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
AnnaBridge 143:86740a56073b 5677 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
AnnaBridge 143:86740a56073b 5678 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5679 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5680
AnnaBridge 143:86740a56073b 5681 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5682 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
AnnaBridge 143:86740a56073b 5683 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
AnnaBridge 143:86740a56073b 5684 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5685 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5686
AnnaBridge 143:86740a56073b 5687 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5688 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
AnnaBridge 143:86740a56073b 5689 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
AnnaBridge 143:86740a56073b 5690 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5691 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5692
AnnaBridge 143:86740a56073b 5693 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5694 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
AnnaBridge 143:86740a56073b 5695 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
AnnaBridge 143:86740a56073b 5696 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5697 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5698
AnnaBridge 143:86740a56073b 5699 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5700 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
AnnaBridge 143:86740a56073b 5701 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
AnnaBridge 143:86740a56073b 5702 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5703 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5704
AnnaBridge 143:86740a56073b 5705 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5706 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
AnnaBridge 143:86740a56073b 5707 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
AnnaBridge 143:86740a56073b 5708 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5709 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5710
AnnaBridge 143:86740a56073b 5711 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5712 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
AnnaBridge 143:86740a56073b 5713 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
AnnaBridge 143:86740a56073b 5714 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5715 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5716
AnnaBridge 143:86740a56073b 5717 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5718 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
AnnaBridge 143:86740a56073b 5719 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
AnnaBridge 143:86740a56073b 5720 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5721 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5722
AnnaBridge 143:86740a56073b 5723 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5724 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
AnnaBridge 143:86740a56073b 5725 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
AnnaBridge 143:86740a56073b 5726 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5727 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5728
AnnaBridge 143:86740a56073b 5729 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5730 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
AnnaBridge 143:86740a56073b 5731 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
AnnaBridge 143:86740a56073b 5732 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5733 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5734
AnnaBridge 143:86740a56073b 5735 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5736 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
AnnaBridge 143:86740a56073b 5737 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
AnnaBridge 143:86740a56073b 5738 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
AnnaBridge 143:86740a56073b 5739 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5740
AnnaBridge 143:86740a56073b 5741 /* Register: MWU_PERREGION_SUBSTATRA */
AnnaBridge 143:86740a56073b 5742 /* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
AnnaBridge 143:86740a56073b 5743
AnnaBridge 143:86740a56073b 5744 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5745 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
AnnaBridge 143:86740a56073b 5746 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
AnnaBridge 143:86740a56073b 5747 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5748 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5749
AnnaBridge 143:86740a56073b 5750 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5751 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
AnnaBridge 143:86740a56073b 5752 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
AnnaBridge 143:86740a56073b 5753 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5754 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5755
AnnaBridge 143:86740a56073b 5756 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5757 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
AnnaBridge 143:86740a56073b 5758 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
AnnaBridge 143:86740a56073b 5759 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5760 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5761
AnnaBridge 143:86740a56073b 5762 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5763 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
AnnaBridge 143:86740a56073b 5764 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
AnnaBridge 143:86740a56073b 5765 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5766 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5767
AnnaBridge 143:86740a56073b 5768 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5769 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
AnnaBridge 143:86740a56073b 5770 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
AnnaBridge 143:86740a56073b 5771 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5772 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5773
AnnaBridge 143:86740a56073b 5774 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5775 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
AnnaBridge 143:86740a56073b 5776 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
AnnaBridge 143:86740a56073b 5777 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5778 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5779
AnnaBridge 143:86740a56073b 5780 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5781 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
AnnaBridge 143:86740a56073b 5782 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
AnnaBridge 143:86740a56073b 5783 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5784 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5785
AnnaBridge 143:86740a56073b 5786 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5787 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
AnnaBridge 143:86740a56073b 5788 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
AnnaBridge 143:86740a56073b 5789 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5790 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5791
AnnaBridge 143:86740a56073b 5792 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5793 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
AnnaBridge 143:86740a56073b 5794 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
AnnaBridge 143:86740a56073b 5795 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5796 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5797
AnnaBridge 143:86740a56073b 5798 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5799 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
AnnaBridge 143:86740a56073b 5800 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
AnnaBridge 143:86740a56073b 5801 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5802 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5803
AnnaBridge 143:86740a56073b 5804 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5805 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
AnnaBridge 143:86740a56073b 5806 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
AnnaBridge 143:86740a56073b 5807 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5808 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5809
AnnaBridge 143:86740a56073b 5810 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5811 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
AnnaBridge 143:86740a56073b 5812 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
AnnaBridge 143:86740a56073b 5813 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5814 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5815
AnnaBridge 143:86740a56073b 5816 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5817 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
AnnaBridge 143:86740a56073b 5818 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
AnnaBridge 143:86740a56073b 5819 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5820 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5821
AnnaBridge 143:86740a56073b 5822 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5823 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
AnnaBridge 143:86740a56073b 5824 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
AnnaBridge 143:86740a56073b 5825 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5826 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5827
AnnaBridge 143:86740a56073b 5828 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5829 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
AnnaBridge 143:86740a56073b 5830 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
AnnaBridge 143:86740a56073b 5831 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5832 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5833
AnnaBridge 143:86740a56073b 5834 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5835 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
AnnaBridge 143:86740a56073b 5836 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
AnnaBridge 143:86740a56073b 5837 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5838 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5839
AnnaBridge 143:86740a56073b 5840 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5841 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
AnnaBridge 143:86740a56073b 5842 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
AnnaBridge 143:86740a56073b 5843 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5844 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5845
AnnaBridge 143:86740a56073b 5846 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5847 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
AnnaBridge 143:86740a56073b 5848 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
AnnaBridge 143:86740a56073b 5849 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5850 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5851
AnnaBridge 143:86740a56073b 5852 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5853 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
AnnaBridge 143:86740a56073b 5854 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
AnnaBridge 143:86740a56073b 5855 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5856 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5857
AnnaBridge 143:86740a56073b 5858 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5859 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
AnnaBridge 143:86740a56073b 5860 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
AnnaBridge 143:86740a56073b 5861 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5862 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5863
AnnaBridge 143:86740a56073b 5864 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5865 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
AnnaBridge 143:86740a56073b 5866 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
AnnaBridge 143:86740a56073b 5867 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5868 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5869
AnnaBridge 143:86740a56073b 5870 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5871 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
AnnaBridge 143:86740a56073b 5872 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
AnnaBridge 143:86740a56073b 5873 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5874 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5875
AnnaBridge 143:86740a56073b 5876 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5877 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
AnnaBridge 143:86740a56073b 5878 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
AnnaBridge 143:86740a56073b 5879 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5880 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5881
AnnaBridge 143:86740a56073b 5882 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5883 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
AnnaBridge 143:86740a56073b 5884 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
AnnaBridge 143:86740a56073b 5885 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5886 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5887
AnnaBridge 143:86740a56073b 5888 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5889 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
AnnaBridge 143:86740a56073b 5890 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
AnnaBridge 143:86740a56073b 5891 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5892 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5893
AnnaBridge 143:86740a56073b 5894 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5895 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
AnnaBridge 143:86740a56073b 5896 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
AnnaBridge 143:86740a56073b 5897 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5898 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5899
AnnaBridge 143:86740a56073b 5900 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5901 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
AnnaBridge 143:86740a56073b 5902 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
AnnaBridge 143:86740a56073b 5903 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5904 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5905
AnnaBridge 143:86740a56073b 5906 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5907 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
AnnaBridge 143:86740a56073b 5908 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
AnnaBridge 143:86740a56073b 5909 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5910 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5911
AnnaBridge 143:86740a56073b 5912 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5913 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
AnnaBridge 143:86740a56073b 5914 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
AnnaBridge 143:86740a56073b 5915 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5916 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5917
AnnaBridge 143:86740a56073b 5918 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5919 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
AnnaBridge 143:86740a56073b 5920 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
AnnaBridge 143:86740a56073b 5921 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5922 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5923
AnnaBridge 143:86740a56073b 5924 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5925 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
AnnaBridge 143:86740a56073b 5926 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
AnnaBridge 143:86740a56073b 5927 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5928 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5929
AnnaBridge 143:86740a56073b 5930 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
AnnaBridge 143:86740a56073b 5931 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
AnnaBridge 143:86740a56073b 5932 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
AnnaBridge 143:86740a56073b 5933 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
AnnaBridge 143:86740a56073b 5934 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
AnnaBridge 143:86740a56073b 5935
AnnaBridge 143:86740a56073b 5936 /* Register: MWU_REGIONEN */
AnnaBridge 143:86740a56073b 5937 /* Description: Enable/disable regions watch */
AnnaBridge 143:86740a56073b 5938
AnnaBridge 143:86740a56073b 5939 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
AnnaBridge 143:86740a56073b 5940 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
AnnaBridge 143:86740a56073b 5941 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
AnnaBridge 143:86740a56073b 5942 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 5943 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 5944
AnnaBridge 143:86740a56073b 5945 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
AnnaBridge 143:86740a56073b 5946 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
AnnaBridge 143:86740a56073b 5947 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
AnnaBridge 143:86740a56073b 5948 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 5949 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 5950
AnnaBridge 143:86740a56073b 5951 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
AnnaBridge 143:86740a56073b 5952 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
AnnaBridge 143:86740a56073b 5953 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
AnnaBridge 143:86740a56073b 5954 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 5955 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 5956
AnnaBridge 143:86740a56073b 5957 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
AnnaBridge 143:86740a56073b 5958 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
AnnaBridge 143:86740a56073b 5959 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
AnnaBridge 143:86740a56073b 5960 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 5961 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 5962
AnnaBridge 143:86740a56073b 5963 /* Bit 7 : Enable/disable read access watch in region[3] */
AnnaBridge 143:86740a56073b 5964 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
AnnaBridge 143:86740a56073b 5965 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
AnnaBridge 143:86740a56073b 5966 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 5967 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 5968
AnnaBridge 143:86740a56073b 5969 /* Bit 6 : Enable/disable write access watch in region[3] */
AnnaBridge 143:86740a56073b 5970 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
AnnaBridge 143:86740a56073b 5971 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
AnnaBridge 143:86740a56073b 5972 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 5973 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 5974
AnnaBridge 143:86740a56073b 5975 /* Bit 5 : Enable/disable read access watch in region[2] */
AnnaBridge 143:86740a56073b 5976 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
AnnaBridge 143:86740a56073b 5977 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
AnnaBridge 143:86740a56073b 5978 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 5979 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 5980
AnnaBridge 143:86740a56073b 5981 /* Bit 4 : Enable/disable write access watch in region[2] */
AnnaBridge 143:86740a56073b 5982 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
AnnaBridge 143:86740a56073b 5983 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
AnnaBridge 143:86740a56073b 5984 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 5985 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 5986
AnnaBridge 143:86740a56073b 5987 /* Bit 3 : Enable/disable read access watch in region[1] */
AnnaBridge 143:86740a56073b 5988 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
AnnaBridge 143:86740a56073b 5989 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
AnnaBridge 143:86740a56073b 5990 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 5991 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 5992
AnnaBridge 143:86740a56073b 5993 /* Bit 2 : Enable/disable write access watch in region[1] */
AnnaBridge 143:86740a56073b 5994 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
AnnaBridge 143:86740a56073b 5995 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
AnnaBridge 143:86740a56073b 5996 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 5997 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 5998
AnnaBridge 143:86740a56073b 5999 /* Bit 1 : Enable/disable read access watch in region[0] */
AnnaBridge 143:86740a56073b 6000 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
AnnaBridge 143:86740a56073b 6001 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
AnnaBridge 143:86740a56073b 6002 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 6003 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 6004
AnnaBridge 143:86740a56073b 6005 /* Bit 0 : Enable/disable write access watch in region[0] */
AnnaBridge 143:86740a56073b 6006 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
AnnaBridge 143:86740a56073b 6007 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
AnnaBridge 143:86740a56073b 6008 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 6009 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 6010
AnnaBridge 143:86740a56073b 6011 /* Register: MWU_REGIONENSET */
AnnaBridge 143:86740a56073b 6012 /* Description: Enable regions watch */
AnnaBridge 143:86740a56073b 6013
AnnaBridge 143:86740a56073b 6014 /* Bit 27 : Enable read access watch in PREGION[1] */
AnnaBridge 143:86740a56073b 6015 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
AnnaBridge 143:86740a56073b 6016 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
AnnaBridge 143:86740a56073b 6017 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6018 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6019 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 6020
AnnaBridge 143:86740a56073b 6021 /* Bit 26 : Enable write access watch in PREGION[1] */
AnnaBridge 143:86740a56073b 6022 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
AnnaBridge 143:86740a56073b 6023 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
AnnaBridge 143:86740a56073b 6024 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6025 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6026 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 6027
AnnaBridge 143:86740a56073b 6028 /* Bit 25 : Enable read access watch in PREGION[0] */
AnnaBridge 143:86740a56073b 6029 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
AnnaBridge 143:86740a56073b 6030 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
AnnaBridge 143:86740a56073b 6031 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6032 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6033 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 6034
AnnaBridge 143:86740a56073b 6035 /* Bit 24 : Enable write access watch in PREGION[0] */
AnnaBridge 143:86740a56073b 6036 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
AnnaBridge 143:86740a56073b 6037 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
AnnaBridge 143:86740a56073b 6038 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6039 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6040 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 6041
AnnaBridge 143:86740a56073b 6042 /* Bit 7 : Enable read access watch in region[3] */
AnnaBridge 143:86740a56073b 6043 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
AnnaBridge 143:86740a56073b 6044 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
AnnaBridge 143:86740a56073b 6045 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6046 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6047 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 6048
AnnaBridge 143:86740a56073b 6049 /* Bit 6 : Enable write access watch in region[3] */
AnnaBridge 143:86740a56073b 6050 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
AnnaBridge 143:86740a56073b 6051 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
AnnaBridge 143:86740a56073b 6052 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6053 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6054 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 6055
AnnaBridge 143:86740a56073b 6056 /* Bit 5 : Enable read access watch in region[2] */
AnnaBridge 143:86740a56073b 6057 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
AnnaBridge 143:86740a56073b 6058 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
AnnaBridge 143:86740a56073b 6059 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6060 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6061 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 6062
AnnaBridge 143:86740a56073b 6063 /* Bit 4 : Enable write access watch in region[2] */
AnnaBridge 143:86740a56073b 6064 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
AnnaBridge 143:86740a56073b 6065 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
AnnaBridge 143:86740a56073b 6066 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6067 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6068 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 6069
AnnaBridge 143:86740a56073b 6070 /* Bit 3 : Enable read access watch in region[1] */
AnnaBridge 143:86740a56073b 6071 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
AnnaBridge 143:86740a56073b 6072 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
AnnaBridge 143:86740a56073b 6073 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6074 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6075 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 6076
AnnaBridge 143:86740a56073b 6077 /* Bit 2 : Enable write access watch in region[1] */
AnnaBridge 143:86740a56073b 6078 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
AnnaBridge 143:86740a56073b 6079 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
AnnaBridge 143:86740a56073b 6080 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6081 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6082 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 6083
AnnaBridge 143:86740a56073b 6084 /* Bit 1 : Enable read access watch in region[0] */
AnnaBridge 143:86740a56073b 6085 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
AnnaBridge 143:86740a56073b 6086 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
AnnaBridge 143:86740a56073b 6087 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6088 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6089 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
AnnaBridge 143:86740a56073b 6090
AnnaBridge 143:86740a56073b 6091 /* Bit 0 : Enable write access watch in region[0] */
AnnaBridge 143:86740a56073b 6092 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
AnnaBridge 143:86740a56073b 6093 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
AnnaBridge 143:86740a56073b 6094 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6095 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6096 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
AnnaBridge 143:86740a56073b 6097
AnnaBridge 143:86740a56073b 6098 /* Register: MWU_REGIONENCLR */
AnnaBridge 143:86740a56073b 6099 /* Description: Disable regions watch */
AnnaBridge 143:86740a56073b 6100
AnnaBridge 143:86740a56073b 6101 /* Bit 27 : Disable read access watch in PREGION[1] */
AnnaBridge 143:86740a56073b 6102 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
AnnaBridge 143:86740a56073b 6103 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
AnnaBridge 143:86740a56073b 6104 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6105 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6106 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 6107
AnnaBridge 143:86740a56073b 6108 /* Bit 26 : Disable write access watch in PREGION[1] */
AnnaBridge 143:86740a56073b 6109 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
AnnaBridge 143:86740a56073b 6110 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
AnnaBridge 143:86740a56073b 6111 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6112 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6113 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 6114
AnnaBridge 143:86740a56073b 6115 /* Bit 25 : Disable read access watch in PREGION[0] */
AnnaBridge 143:86740a56073b 6116 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
AnnaBridge 143:86740a56073b 6117 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
AnnaBridge 143:86740a56073b 6118 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6119 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6120 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
AnnaBridge 143:86740a56073b 6121
AnnaBridge 143:86740a56073b 6122 /* Bit 24 : Disable write access watch in PREGION[0] */
AnnaBridge 143:86740a56073b 6123 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
AnnaBridge 143:86740a56073b 6124 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
AnnaBridge 143:86740a56073b 6125 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
AnnaBridge 143:86740a56073b 6126 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
AnnaBridge 143:86740a56073b 6127 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
AnnaBridge 143:86740a56073b 6128
AnnaBridge 143:86740a56073b 6129 /* Bit 7 : Disable read access watch in region[3] */
AnnaBridge 143:86740a56073b 6130 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
AnnaBridge 143:86740a56073b 6131 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
AnnaBridge 143:86740a56073b 6132 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6133 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6134 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 6135
AnnaBridge 143:86740a56073b 6136 /* Bit 6 : Disable write access watch in region[3] */
AnnaBridge 143:86740a56073b 6137 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
AnnaBridge 143:86740a56073b 6138 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
AnnaBridge 143:86740a56073b 6139 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6140 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6141 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 6142
AnnaBridge 143:86740a56073b 6143 /* Bit 5 : Disable read access watch in region[2] */
AnnaBridge 143:86740a56073b 6144 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
AnnaBridge 143:86740a56073b 6145 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
AnnaBridge 143:86740a56073b 6146 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6147 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6148 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 6149
AnnaBridge 143:86740a56073b 6150 /* Bit 4 : Disable write access watch in region[2] */
AnnaBridge 143:86740a56073b 6151 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
AnnaBridge 143:86740a56073b 6152 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
AnnaBridge 143:86740a56073b 6153 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6154 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6155 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 6156
AnnaBridge 143:86740a56073b 6157 /* Bit 3 : Disable read access watch in region[1] */
AnnaBridge 143:86740a56073b 6158 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
AnnaBridge 143:86740a56073b 6159 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
AnnaBridge 143:86740a56073b 6160 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6161 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6162 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 6163
AnnaBridge 143:86740a56073b 6164 /* Bit 2 : Disable write access watch in region[1] */
AnnaBridge 143:86740a56073b 6165 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
AnnaBridge 143:86740a56073b 6166 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
AnnaBridge 143:86740a56073b 6167 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6168 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6169 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 6170
AnnaBridge 143:86740a56073b 6171 /* Bit 1 : Disable read access watch in region[0] */
AnnaBridge 143:86740a56073b 6172 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
AnnaBridge 143:86740a56073b 6173 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
AnnaBridge 143:86740a56073b 6174 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6175 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6176 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
AnnaBridge 143:86740a56073b 6177
AnnaBridge 143:86740a56073b 6178 /* Bit 0 : Disable write access watch in region[0] */
AnnaBridge 143:86740a56073b 6179 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
AnnaBridge 143:86740a56073b 6180 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
AnnaBridge 143:86740a56073b 6181 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
AnnaBridge 143:86740a56073b 6182 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
AnnaBridge 143:86740a56073b 6183 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
AnnaBridge 143:86740a56073b 6184
AnnaBridge 143:86740a56073b 6185 /* Register: MWU_REGION_START */
AnnaBridge 143:86740a56073b 6186 /* Description: Description cluster[0]: Start address for region 0 */
AnnaBridge 143:86740a56073b 6187
AnnaBridge 143:86740a56073b 6188 /* Bits 31..0 : Start address for region */
AnnaBridge 143:86740a56073b 6189 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
AnnaBridge 143:86740a56073b 6190 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
AnnaBridge 143:86740a56073b 6191
AnnaBridge 143:86740a56073b 6192 /* Register: MWU_REGION_END */
AnnaBridge 143:86740a56073b 6193 /* Description: Description cluster[0]: End address of region 0 */
AnnaBridge 143:86740a56073b 6194
AnnaBridge 143:86740a56073b 6195 /* Bits 31..0 : End address of region. */
AnnaBridge 143:86740a56073b 6196 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 6197 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 6198
AnnaBridge 143:86740a56073b 6199 /* Register: MWU_PREGION_START */
AnnaBridge 143:86740a56073b 6200 /* Description: Description cluster[0]: Reserved for future use */
AnnaBridge 143:86740a56073b 6201
AnnaBridge 143:86740a56073b 6202 /* Bits 31..0 : Reserved for future use */
AnnaBridge 143:86740a56073b 6203 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
AnnaBridge 143:86740a56073b 6204 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
AnnaBridge 143:86740a56073b 6205
AnnaBridge 143:86740a56073b 6206 /* Register: MWU_PREGION_END */
AnnaBridge 143:86740a56073b 6207 /* Description: Description cluster[0]: Reserved for future use */
AnnaBridge 143:86740a56073b 6208
AnnaBridge 143:86740a56073b 6209 /* Bits 31..0 : Reserved for future use */
AnnaBridge 143:86740a56073b 6210 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 6211 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 6212
AnnaBridge 143:86740a56073b 6213 /* Register: MWU_PREGION_SUBS */
AnnaBridge 143:86740a56073b 6214 /* Description: Description cluster[0]: Subregions of region 0 */
AnnaBridge 143:86740a56073b 6215
AnnaBridge 143:86740a56073b 6216 /* Bit 31 : Include or exclude subregion 31 in region */
AnnaBridge 143:86740a56073b 6217 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
AnnaBridge 143:86740a56073b 6218 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
AnnaBridge 143:86740a56073b 6219 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6220 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6221
AnnaBridge 143:86740a56073b 6222 /* Bit 30 : Include or exclude subregion 30 in region */
AnnaBridge 143:86740a56073b 6223 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
AnnaBridge 143:86740a56073b 6224 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
AnnaBridge 143:86740a56073b 6225 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6226 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6227
AnnaBridge 143:86740a56073b 6228 /* Bit 29 : Include or exclude subregion 29 in region */
AnnaBridge 143:86740a56073b 6229 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
AnnaBridge 143:86740a56073b 6230 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
AnnaBridge 143:86740a56073b 6231 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6232 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6233
AnnaBridge 143:86740a56073b 6234 /* Bit 28 : Include or exclude subregion 28 in region */
AnnaBridge 143:86740a56073b 6235 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
AnnaBridge 143:86740a56073b 6236 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
AnnaBridge 143:86740a56073b 6237 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6238 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6239
AnnaBridge 143:86740a56073b 6240 /* Bit 27 : Include or exclude subregion 27 in region */
AnnaBridge 143:86740a56073b 6241 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
AnnaBridge 143:86740a56073b 6242 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
AnnaBridge 143:86740a56073b 6243 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6244 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6245
AnnaBridge 143:86740a56073b 6246 /* Bit 26 : Include or exclude subregion 26 in region */
AnnaBridge 143:86740a56073b 6247 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
AnnaBridge 143:86740a56073b 6248 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
AnnaBridge 143:86740a56073b 6249 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6250 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6251
AnnaBridge 143:86740a56073b 6252 /* Bit 25 : Include or exclude subregion 25 in region */
AnnaBridge 143:86740a56073b 6253 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
AnnaBridge 143:86740a56073b 6254 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
AnnaBridge 143:86740a56073b 6255 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6256 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6257
AnnaBridge 143:86740a56073b 6258 /* Bit 24 : Include or exclude subregion 24 in region */
AnnaBridge 143:86740a56073b 6259 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
AnnaBridge 143:86740a56073b 6260 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
AnnaBridge 143:86740a56073b 6261 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6262 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6263
AnnaBridge 143:86740a56073b 6264 /* Bit 23 : Include or exclude subregion 23 in region */
AnnaBridge 143:86740a56073b 6265 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
AnnaBridge 143:86740a56073b 6266 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
AnnaBridge 143:86740a56073b 6267 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6268 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6269
AnnaBridge 143:86740a56073b 6270 /* Bit 22 : Include or exclude subregion 22 in region */
AnnaBridge 143:86740a56073b 6271 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
AnnaBridge 143:86740a56073b 6272 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
AnnaBridge 143:86740a56073b 6273 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6274 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6275
AnnaBridge 143:86740a56073b 6276 /* Bit 21 : Include or exclude subregion 21 in region */
AnnaBridge 143:86740a56073b 6277 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
AnnaBridge 143:86740a56073b 6278 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
AnnaBridge 143:86740a56073b 6279 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6280 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6281
AnnaBridge 143:86740a56073b 6282 /* Bit 20 : Include or exclude subregion 20 in region */
AnnaBridge 143:86740a56073b 6283 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
AnnaBridge 143:86740a56073b 6284 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
AnnaBridge 143:86740a56073b 6285 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6286 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6287
AnnaBridge 143:86740a56073b 6288 /* Bit 19 : Include or exclude subregion 19 in region */
AnnaBridge 143:86740a56073b 6289 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
AnnaBridge 143:86740a56073b 6290 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
AnnaBridge 143:86740a56073b 6291 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6292 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6293
AnnaBridge 143:86740a56073b 6294 /* Bit 18 : Include or exclude subregion 18 in region */
AnnaBridge 143:86740a56073b 6295 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
AnnaBridge 143:86740a56073b 6296 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
AnnaBridge 143:86740a56073b 6297 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6298 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6299
AnnaBridge 143:86740a56073b 6300 /* Bit 17 : Include or exclude subregion 17 in region */
AnnaBridge 143:86740a56073b 6301 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
AnnaBridge 143:86740a56073b 6302 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
AnnaBridge 143:86740a56073b 6303 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6304 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6305
AnnaBridge 143:86740a56073b 6306 /* Bit 16 : Include or exclude subregion 16 in region */
AnnaBridge 143:86740a56073b 6307 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
AnnaBridge 143:86740a56073b 6308 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
AnnaBridge 143:86740a56073b 6309 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6310 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6311
AnnaBridge 143:86740a56073b 6312 /* Bit 15 : Include or exclude subregion 15 in region */
AnnaBridge 143:86740a56073b 6313 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
AnnaBridge 143:86740a56073b 6314 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
AnnaBridge 143:86740a56073b 6315 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6316 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6317
AnnaBridge 143:86740a56073b 6318 /* Bit 14 : Include or exclude subregion 14 in region */
AnnaBridge 143:86740a56073b 6319 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
AnnaBridge 143:86740a56073b 6320 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
AnnaBridge 143:86740a56073b 6321 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6322 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6323
AnnaBridge 143:86740a56073b 6324 /* Bit 13 : Include or exclude subregion 13 in region */
AnnaBridge 143:86740a56073b 6325 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
AnnaBridge 143:86740a56073b 6326 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
AnnaBridge 143:86740a56073b 6327 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6328 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6329
AnnaBridge 143:86740a56073b 6330 /* Bit 12 : Include or exclude subregion 12 in region */
AnnaBridge 143:86740a56073b 6331 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
AnnaBridge 143:86740a56073b 6332 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
AnnaBridge 143:86740a56073b 6333 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6334 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6335
AnnaBridge 143:86740a56073b 6336 /* Bit 11 : Include or exclude subregion 11 in region */
AnnaBridge 143:86740a56073b 6337 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
AnnaBridge 143:86740a56073b 6338 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
AnnaBridge 143:86740a56073b 6339 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6340 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6341
AnnaBridge 143:86740a56073b 6342 /* Bit 10 : Include or exclude subregion 10 in region */
AnnaBridge 143:86740a56073b 6343 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
AnnaBridge 143:86740a56073b 6344 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
AnnaBridge 143:86740a56073b 6345 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6346 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6347
AnnaBridge 143:86740a56073b 6348 /* Bit 9 : Include or exclude subregion 9 in region */
AnnaBridge 143:86740a56073b 6349 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
AnnaBridge 143:86740a56073b 6350 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
AnnaBridge 143:86740a56073b 6351 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6352 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6353
AnnaBridge 143:86740a56073b 6354 /* Bit 8 : Include or exclude subregion 8 in region */
AnnaBridge 143:86740a56073b 6355 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
AnnaBridge 143:86740a56073b 6356 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
AnnaBridge 143:86740a56073b 6357 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6358 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6359
AnnaBridge 143:86740a56073b 6360 /* Bit 7 : Include or exclude subregion 7 in region */
AnnaBridge 143:86740a56073b 6361 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
AnnaBridge 143:86740a56073b 6362 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
AnnaBridge 143:86740a56073b 6363 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6364 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6365
AnnaBridge 143:86740a56073b 6366 /* Bit 6 : Include or exclude subregion 6 in region */
AnnaBridge 143:86740a56073b 6367 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
AnnaBridge 143:86740a56073b 6368 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
AnnaBridge 143:86740a56073b 6369 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6370 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6371
AnnaBridge 143:86740a56073b 6372 /* Bit 5 : Include or exclude subregion 5 in region */
AnnaBridge 143:86740a56073b 6373 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
AnnaBridge 143:86740a56073b 6374 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
AnnaBridge 143:86740a56073b 6375 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6376 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6377
AnnaBridge 143:86740a56073b 6378 /* Bit 4 : Include or exclude subregion 4 in region */
AnnaBridge 143:86740a56073b 6379 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
AnnaBridge 143:86740a56073b 6380 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
AnnaBridge 143:86740a56073b 6381 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6382 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6383
AnnaBridge 143:86740a56073b 6384 /* Bit 3 : Include or exclude subregion 3 in region */
AnnaBridge 143:86740a56073b 6385 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
AnnaBridge 143:86740a56073b 6386 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
AnnaBridge 143:86740a56073b 6387 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6388 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6389
AnnaBridge 143:86740a56073b 6390 /* Bit 2 : Include or exclude subregion 2 in region */
AnnaBridge 143:86740a56073b 6391 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
AnnaBridge 143:86740a56073b 6392 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
AnnaBridge 143:86740a56073b 6393 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6394 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6395
AnnaBridge 143:86740a56073b 6396 /* Bit 1 : Include or exclude subregion 1 in region */
AnnaBridge 143:86740a56073b 6397 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
AnnaBridge 143:86740a56073b 6398 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
AnnaBridge 143:86740a56073b 6399 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6400 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6401
AnnaBridge 143:86740a56073b 6402 /* Bit 0 : Include or exclude subregion 0 in region */
AnnaBridge 143:86740a56073b 6403 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
AnnaBridge 143:86740a56073b 6404 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
AnnaBridge 143:86740a56073b 6405 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 6406 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 6407
AnnaBridge 143:86740a56073b 6408
AnnaBridge 143:86740a56073b 6409 /* Peripheral: NFCT */
AnnaBridge 143:86740a56073b 6410 /* Description: NFC-A compatible radio */
AnnaBridge 143:86740a56073b 6411
AnnaBridge 143:86740a56073b 6412 /* Register: NFCT_SHORTS */
AnnaBridge 143:86740a56073b 6413 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 6414
AnnaBridge 143:86740a56073b 6415 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
AnnaBridge 143:86740a56073b 6416 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
AnnaBridge 143:86740a56073b 6417 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
AnnaBridge 143:86740a56073b 6418 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 6419 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 6420
AnnaBridge 143:86740a56073b 6421 /* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
AnnaBridge 143:86740a56073b 6422 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
AnnaBridge 143:86740a56073b 6423 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
AnnaBridge 143:86740a56073b 6424 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 6425 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 6426
AnnaBridge 143:86740a56073b 6427 /* Register: NFCT_INTEN */
AnnaBridge 143:86740a56073b 6428 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 6429
AnnaBridge 143:86740a56073b 6430 /* Bit 20 : Enable or disable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 6431 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 6432 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 6433 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6434 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6435
AnnaBridge 143:86740a56073b 6436 /* Bit 19 : Enable or disable interrupt for SELECTED event */
AnnaBridge 143:86740a56073b 6437 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
AnnaBridge 143:86740a56073b 6438 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
AnnaBridge 143:86740a56073b 6439 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6440 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6441
AnnaBridge 143:86740a56073b 6442 /* Bit 18 : Enable or disable interrupt for COLLISION event */
AnnaBridge 143:86740a56073b 6443 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
AnnaBridge 143:86740a56073b 6444 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
AnnaBridge 143:86740a56073b 6445 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6446 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6447
AnnaBridge 143:86740a56073b 6448 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
AnnaBridge 143:86740a56073b 6449 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
AnnaBridge 143:86740a56073b 6450 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
AnnaBridge 143:86740a56073b 6451 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6452 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6453
AnnaBridge 143:86740a56073b 6454 /* Bit 12 : Enable or disable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 6455 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 6456 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 6457 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6458 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6459
AnnaBridge 143:86740a56073b 6460 /* Bit 11 : Enable or disable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 6461 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 6462 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 6463 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6464 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6465
AnnaBridge 143:86740a56073b 6466 /* Bit 10 : Enable or disable interrupt for RXERROR event */
AnnaBridge 143:86740a56073b 6467 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
AnnaBridge 143:86740a56073b 6468 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
AnnaBridge 143:86740a56073b 6469 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6470 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6471
AnnaBridge 143:86740a56073b 6472 /* Bit 7 : Enable or disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 6473 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 6474 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 6475 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6476 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6477
AnnaBridge 143:86740a56073b 6478 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
AnnaBridge 143:86740a56073b 6479 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6480 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6481 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6482 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6483
AnnaBridge 143:86740a56073b 6484 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
AnnaBridge 143:86740a56073b 6485 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6486 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6487 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6488 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6489
AnnaBridge 143:86740a56073b 6490 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
AnnaBridge 143:86740a56073b 6491 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6492 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6493 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6494 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6495
AnnaBridge 143:86740a56073b 6496 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
AnnaBridge 143:86740a56073b 6497 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6498 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6499 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6500 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6501
AnnaBridge 143:86740a56073b 6502 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
AnnaBridge 143:86740a56073b 6503 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
AnnaBridge 143:86740a56073b 6504 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
AnnaBridge 143:86740a56073b 6505 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6506 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6507
AnnaBridge 143:86740a56073b 6508 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
AnnaBridge 143:86740a56073b 6509 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
AnnaBridge 143:86740a56073b 6510 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
AnnaBridge 143:86740a56073b 6511 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6512 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6513
AnnaBridge 143:86740a56073b 6514 /* Bit 0 : Enable or disable interrupt for READY event */
AnnaBridge 143:86740a56073b 6515 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 6516 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 6517 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6518 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6519
AnnaBridge 143:86740a56073b 6520 /* Register: NFCT_INTENSET */
AnnaBridge 143:86740a56073b 6521 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 6522
AnnaBridge 143:86740a56073b 6523 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 6524 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 6525 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 6526 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6527 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6528 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6529
AnnaBridge 143:86740a56073b 6530 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
AnnaBridge 143:86740a56073b 6531 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
AnnaBridge 143:86740a56073b 6532 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
AnnaBridge 143:86740a56073b 6533 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6534 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6535 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6536
AnnaBridge 143:86740a56073b 6537 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
AnnaBridge 143:86740a56073b 6538 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
AnnaBridge 143:86740a56073b 6539 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
AnnaBridge 143:86740a56073b 6540 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6541 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6542 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6543
AnnaBridge 143:86740a56073b 6544 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
AnnaBridge 143:86740a56073b 6545 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
AnnaBridge 143:86740a56073b 6546 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
AnnaBridge 143:86740a56073b 6547 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6548 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6549 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6550
AnnaBridge 143:86740a56073b 6551 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 6552 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 6553 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 6554 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6555 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6556 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6557
AnnaBridge 143:86740a56073b 6558 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 6559 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 6560 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 6561 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6562 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6563 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6564
AnnaBridge 143:86740a56073b 6565 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
AnnaBridge 143:86740a56073b 6566 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
AnnaBridge 143:86740a56073b 6567 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
AnnaBridge 143:86740a56073b 6568 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6569 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6570 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6571
AnnaBridge 143:86740a56073b 6572 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 6573 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 6574 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 6575 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6576 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6577 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6578
AnnaBridge 143:86740a56073b 6579 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
AnnaBridge 143:86740a56073b 6580 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6581 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6582 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6583 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6584 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6585
AnnaBridge 143:86740a56073b 6586 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
AnnaBridge 143:86740a56073b 6587 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6588 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6589 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6590 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6591 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6592
AnnaBridge 143:86740a56073b 6593 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
AnnaBridge 143:86740a56073b 6594 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6595 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6596 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6597 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6598 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6599
AnnaBridge 143:86740a56073b 6600 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
AnnaBridge 143:86740a56073b 6601 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6602 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6603 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6604 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6605 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6606
AnnaBridge 143:86740a56073b 6607 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
AnnaBridge 143:86740a56073b 6608 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
AnnaBridge 143:86740a56073b 6609 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
AnnaBridge 143:86740a56073b 6610 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6611 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6612 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6613
AnnaBridge 143:86740a56073b 6614 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
AnnaBridge 143:86740a56073b 6615 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
AnnaBridge 143:86740a56073b 6616 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
AnnaBridge 143:86740a56073b 6617 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6618 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6619 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6620
AnnaBridge 143:86740a56073b 6621 /* Bit 0 : Write '1' to Enable interrupt for READY event */
AnnaBridge 143:86740a56073b 6622 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 6623 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 6624 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6625 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6626 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 6627
AnnaBridge 143:86740a56073b 6628 /* Register: NFCT_INTENCLR */
AnnaBridge 143:86740a56073b 6629 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 6630
AnnaBridge 143:86740a56073b 6631 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 6632 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 6633 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 6634 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6635 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6636 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6637
AnnaBridge 143:86740a56073b 6638 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
AnnaBridge 143:86740a56073b 6639 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
AnnaBridge 143:86740a56073b 6640 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
AnnaBridge 143:86740a56073b 6641 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6642 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6643 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6644
AnnaBridge 143:86740a56073b 6645 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
AnnaBridge 143:86740a56073b 6646 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
AnnaBridge 143:86740a56073b 6647 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
AnnaBridge 143:86740a56073b 6648 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6649 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6650 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6651
AnnaBridge 143:86740a56073b 6652 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
AnnaBridge 143:86740a56073b 6653 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
AnnaBridge 143:86740a56073b 6654 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
AnnaBridge 143:86740a56073b 6655 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6656 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6657 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6658
AnnaBridge 143:86740a56073b 6659 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 6660 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 6661 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 6662 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6663 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6664 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6665
AnnaBridge 143:86740a56073b 6666 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 6667 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 6668 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 6669 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6670 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6671 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6672
AnnaBridge 143:86740a56073b 6673 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
AnnaBridge 143:86740a56073b 6674 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
AnnaBridge 143:86740a56073b 6675 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
AnnaBridge 143:86740a56073b 6676 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6677 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6678 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6679
AnnaBridge 143:86740a56073b 6680 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 6681 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 6682 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 6683 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6684 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6685 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6686
AnnaBridge 143:86740a56073b 6687 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
AnnaBridge 143:86740a56073b 6688 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6689 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6690 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6691 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6692 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6693
AnnaBridge 143:86740a56073b 6694 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
AnnaBridge 143:86740a56073b 6695 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6696 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6697 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6698 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6699 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6700
AnnaBridge 143:86740a56073b 6701 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
AnnaBridge 143:86740a56073b 6702 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6703 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
AnnaBridge 143:86740a56073b 6704 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6705 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6706 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6707
AnnaBridge 143:86740a56073b 6708 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
AnnaBridge 143:86740a56073b 6709 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6710 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
AnnaBridge 143:86740a56073b 6711 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6712 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6713 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6714
AnnaBridge 143:86740a56073b 6715 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
AnnaBridge 143:86740a56073b 6716 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
AnnaBridge 143:86740a56073b 6717 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
AnnaBridge 143:86740a56073b 6718 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6719 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6720 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6721
AnnaBridge 143:86740a56073b 6722 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
AnnaBridge 143:86740a56073b 6723 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
AnnaBridge 143:86740a56073b 6724 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
AnnaBridge 143:86740a56073b 6725 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6726 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6727 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6728
AnnaBridge 143:86740a56073b 6729 /* Bit 0 : Write '1' to Disable interrupt for READY event */
AnnaBridge 143:86740a56073b 6730 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 6731 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 6732 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 6733 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 6734 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 6735
AnnaBridge 143:86740a56073b 6736 /* Register: NFCT_ERRORSTATUS */
AnnaBridge 143:86740a56073b 6737 /* Description: NFC Error Status register */
AnnaBridge 143:86740a56073b 6738
AnnaBridge 143:86740a56073b 6739 /* Bit 3 : Field level is too low at min load resistance */
AnnaBridge 143:86740a56073b 6740 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
AnnaBridge 143:86740a56073b 6741 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
AnnaBridge 143:86740a56073b 6742
AnnaBridge 143:86740a56073b 6743 /* Bit 2 : Field level is too high at max load resistance */
AnnaBridge 143:86740a56073b 6744 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
AnnaBridge 143:86740a56073b 6745 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
AnnaBridge 143:86740a56073b 6746
AnnaBridge 143:86740a56073b 6747 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
AnnaBridge 143:86740a56073b 6748 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
AnnaBridge 143:86740a56073b 6749 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
AnnaBridge 143:86740a56073b 6750
AnnaBridge 143:86740a56073b 6751 /* Register: NFCT_FRAMESTATUS_RX */
AnnaBridge 143:86740a56073b 6752 /* Description: Result of last incoming frames */
AnnaBridge 143:86740a56073b 6753
AnnaBridge 143:86740a56073b 6754 /* Bit 3 : Overrun detected */
AnnaBridge 143:86740a56073b 6755 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
AnnaBridge 143:86740a56073b 6756 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
AnnaBridge 143:86740a56073b 6757 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
AnnaBridge 143:86740a56073b 6758 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
AnnaBridge 143:86740a56073b 6759
AnnaBridge 143:86740a56073b 6760 /* Bit 2 : Parity status of received frame */
AnnaBridge 143:86740a56073b 6761 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
AnnaBridge 143:86740a56073b 6762 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
AnnaBridge 143:86740a56073b 6763 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
AnnaBridge 143:86740a56073b 6764 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
AnnaBridge 143:86740a56073b 6765
AnnaBridge 143:86740a56073b 6766 /* Bit 0 : No valid End of Frame detected */
AnnaBridge 143:86740a56073b 6767 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
AnnaBridge 143:86740a56073b 6768 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
AnnaBridge 143:86740a56073b 6769 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
AnnaBridge 143:86740a56073b 6770 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
AnnaBridge 143:86740a56073b 6771
AnnaBridge 143:86740a56073b 6772 /* Register: NFCT_CURRENTLOADCTRL */
AnnaBridge 143:86740a56073b 6773 /* Description: Current value driven to the NFC Load Control */
AnnaBridge 143:86740a56073b 6774
AnnaBridge 143:86740a56073b 6775 /* Bits 5..0 : Current value driven to the NFC Load Control */
AnnaBridge 143:86740a56073b 6776 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
AnnaBridge 143:86740a56073b 6777 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
AnnaBridge 143:86740a56073b 6778
AnnaBridge 143:86740a56073b 6779 /* Register: NFCT_FIELDPRESENT */
AnnaBridge 143:86740a56073b 6780 /* Description: Indicates the presence or not of a valid field */
AnnaBridge 143:86740a56073b 6781
AnnaBridge 143:86740a56073b 6782 /* Bit 1 : Indicates if the low level has locked to the field */
AnnaBridge 143:86740a56073b 6783 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
AnnaBridge 143:86740a56073b 6784 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
AnnaBridge 143:86740a56073b 6785 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
AnnaBridge 143:86740a56073b 6786 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
AnnaBridge 143:86740a56073b 6787
AnnaBridge 143:86740a56073b 6788 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
AnnaBridge 143:86740a56073b 6789 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
AnnaBridge 143:86740a56073b 6790 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
AnnaBridge 143:86740a56073b 6791 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
AnnaBridge 143:86740a56073b 6792 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
AnnaBridge 143:86740a56073b 6793
AnnaBridge 143:86740a56073b 6794 /* Register: NFCT_FRAMEDELAYMIN */
AnnaBridge 143:86740a56073b 6795 /* Description: Minimum frame delay */
AnnaBridge 143:86740a56073b 6796
AnnaBridge 143:86740a56073b 6797 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
AnnaBridge 143:86740a56073b 6798 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
AnnaBridge 143:86740a56073b 6799 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
AnnaBridge 143:86740a56073b 6800
AnnaBridge 143:86740a56073b 6801 /* Register: NFCT_FRAMEDELAYMAX */
AnnaBridge 143:86740a56073b 6802 /* Description: Maximum frame delay */
AnnaBridge 143:86740a56073b 6803
AnnaBridge 143:86740a56073b 6804 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
AnnaBridge 143:86740a56073b 6805 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
AnnaBridge 143:86740a56073b 6806 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
AnnaBridge 143:86740a56073b 6807
AnnaBridge 143:86740a56073b 6808 /* Register: NFCT_FRAMEDELAYMODE */
AnnaBridge 143:86740a56073b 6809 /* Description: Configuration register for the Frame Delay Timer */
AnnaBridge 143:86740a56073b 6810
AnnaBridge 143:86740a56073b 6811 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
AnnaBridge 143:86740a56073b 6812 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
AnnaBridge 143:86740a56073b 6813 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
AnnaBridge 143:86740a56073b 6814 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
AnnaBridge 143:86740a56073b 6815 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
AnnaBridge 143:86740a56073b 6816 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
AnnaBridge 143:86740a56073b 6817 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
AnnaBridge 143:86740a56073b 6818
AnnaBridge 143:86740a56073b 6819 /* Register: NFCT_PACKETPTR */
AnnaBridge 143:86740a56073b 6820 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
AnnaBridge 143:86740a56073b 6821
AnnaBridge 143:86740a56073b 6822 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
AnnaBridge 143:86740a56073b 6823 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 6824 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 6825
AnnaBridge 143:86740a56073b 6826 /* Register: NFCT_MAXLEN */
AnnaBridge 143:86740a56073b 6827 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
AnnaBridge 143:86740a56073b 6828
AnnaBridge 143:86740a56073b 6829 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
AnnaBridge 143:86740a56073b 6830 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
AnnaBridge 143:86740a56073b 6831 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
AnnaBridge 143:86740a56073b 6832
AnnaBridge 143:86740a56073b 6833 /* Register: NFCT_TXD_FRAMECONFIG */
AnnaBridge 143:86740a56073b 6834 /* Description: Configuration of outgoing frames */
AnnaBridge 143:86740a56073b 6835
AnnaBridge 143:86740a56073b 6836 /* Bit 4 : CRC mode for outgoing frames */
AnnaBridge 143:86740a56073b 6837 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
AnnaBridge 143:86740a56073b 6838 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
AnnaBridge 143:86740a56073b 6839 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
AnnaBridge 143:86740a56073b 6840 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
AnnaBridge 143:86740a56073b 6841
AnnaBridge 143:86740a56073b 6842 /* Bit 2 : Adding SoF or not in TX frames */
AnnaBridge 143:86740a56073b 6843 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
AnnaBridge 143:86740a56073b 6844 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
AnnaBridge 143:86740a56073b 6845 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
AnnaBridge 143:86740a56073b 6846 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
AnnaBridge 143:86740a56073b 6847
AnnaBridge 143:86740a56073b 6848 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
AnnaBridge 143:86740a56073b 6849 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
AnnaBridge 143:86740a56073b 6850 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
AnnaBridge 143:86740a56073b 6851 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
AnnaBridge 143:86740a56073b 6852 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
AnnaBridge 143:86740a56073b 6853
AnnaBridge 143:86740a56073b 6854 /* Bit 0 : Adding parity or not in the frame */
AnnaBridge 143:86740a56073b 6855 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 6856 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 6857 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
AnnaBridge 143:86740a56073b 6858 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
AnnaBridge 143:86740a56073b 6859
AnnaBridge 143:86740a56073b 6860 /* Register: NFCT_TXD_AMOUNT */
AnnaBridge 143:86740a56073b 6861 /* Description: Size of outgoing frame */
AnnaBridge 143:86740a56073b 6862
AnnaBridge 143:86740a56073b 6863 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
AnnaBridge 143:86740a56073b 6864 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
AnnaBridge 143:86740a56073b 6865 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
AnnaBridge 143:86740a56073b 6866
AnnaBridge 143:86740a56073b 6867 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
AnnaBridge 143:86740a56073b 6868 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
AnnaBridge 143:86740a56073b 6869 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
AnnaBridge 143:86740a56073b 6870
AnnaBridge 143:86740a56073b 6871 /* Register: NFCT_RXD_FRAMECONFIG */
AnnaBridge 143:86740a56073b 6872 /* Description: Configuration of incoming frames */
AnnaBridge 143:86740a56073b 6873
AnnaBridge 143:86740a56073b 6874 /* Bit 4 : CRC mode for incoming frames */
AnnaBridge 143:86740a56073b 6875 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
AnnaBridge 143:86740a56073b 6876 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
AnnaBridge 143:86740a56073b 6877 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
AnnaBridge 143:86740a56073b 6878 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
AnnaBridge 143:86740a56073b 6879
AnnaBridge 143:86740a56073b 6880 /* Bit 2 : SoF expected or not in RX frames */
AnnaBridge 143:86740a56073b 6881 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
AnnaBridge 143:86740a56073b 6882 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
AnnaBridge 143:86740a56073b 6883 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
AnnaBridge 143:86740a56073b 6884 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
AnnaBridge 143:86740a56073b 6885
AnnaBridge 143:86740a56073b 6886 /* Bit 0 : Parity expected or not in RX frame */
AnnaBridge 143:86740a56073b 6887 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 6888 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 6889 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
AnnaBridge 143:86740a56073b 6890 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
AnnaBridge 143:86740a56073b 6891
AnnaBridge 143:86740a56073b 6892 /* Register: NFCT_RXD_AMOUNT */
AnnaBridge 143:86740a56073b 6893 /* Description: Size of last incoming frame */
AnnaBridge 143:86740a56073b 6894
AnnaBridge 143:86740a56073b 6895 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
AnnaBridge 143:86740a56073b 6896 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
AnnaBridge 143:86740a56073b 6897 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
AnnaBridge 143:86740a56073b 6898
AnnaBridge 143:86740a56073b 6899 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
AnnaBridge 143:86740a56073b 6900 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
AnnaBridge 143:86740a56073b 6901 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
AnnaBridge 143:86740a56073b 6902
AnnaBridge 143:86740a56073b 6903 /* Register: NFCT_NFCID1_LAST */
AnnaBridge 143:86740a56073b 6904 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
AnnaBridge 143:86740a56073b 6905
AnnaBridge 143:86740a56073b 6906 /* Bits 31..24 : NFCID1 byte W */
AnnaBridge 143:86740a56073b 6907 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
AnnaBridge 143:86740a56073b 6908 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
AnnaBridge 143:86740a56073b 6909
AnnaBridge 143:86740a56073b 6910 /* Bits 23..16 : NFCID1 byte X */
AnnaBridge 143:86740a56073b 6911 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
AnnaBridge 143:86740a56073b 6912 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
AnnaBridge 143:86740a56073b 6913
AnnaBridge 143:86740a56073b 6914 /* Bits 15..8 : NFCID1 byte Y */
AnnaBridge 143:86740a56073b 6915 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
AnnaBridge 143:86740a56073b 6916 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
AnnaBridge 143:86740a56073b 6917
AnnaBridge 143:86740a56073b 6918 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
AnnaBridge 143:86740a56073b 6919 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
AnnaBridge 143:86740a56073b 6920 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
AnnaBridge 143:86740a56073b 6921
AnnaBridge 143:86740a56073b 6922 /* Register: NFCT_NFCID1_2ND_LAST */
AnnaBridge 143:86740a56073b 6923 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
AnnaBridge 143:86740a56073b 6924
AnnaBridge 143:86740a56073b 6925 /* Bits 23..16 : NFCID1 byte T */
AnnaBridge 143:86740a56073b 6926 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
AnnaBridge 143:86740a56073b 6927 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
AnnaBridge 143:86740a56073b 6928
AnnaBridge 143:86740a56073b 6929 /* Bits 15..8 : NFCID1 byte U */
AnnaBridge 143:86740a56073b 6930 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
AnnaBridge 143:86740a56073b 6931 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
AnnaBridge 143:86740a56073b 6932
AnnaBridge 143:86740a56073b 6933 /* Bits 7..0 : NFCID1 byte V */
AnnaBridge 143:86740a56073b 6934 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
AnnaBridge 143:86740a56073b 6935 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
AnnaBridge 143:86740a56073b 6936
AnnaBridge 143:86740a56073b 6937 /* Register: NFCT_NFCID1_3RD_LAST */
AnnaBridge 143:86740a56073b 6938 /* Description: Third last NFCID1 part (10 bytes ID) */
AnnaBridge 143:86740a56073b 6939
AnnaBridge 143:86740a56073b 6940 /* Bits 23..16 : NFCID1 byte Q */
AnnaBridge 143:86740a56073b 6941 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
AnnaBridge 143:86740a56073b 6942 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
AnnaBridge 143:86740a56073b 6943
AnnaBridge 143:86740a56073b 6944 /* Bits 15..8 : NFCID1 byte R */
AnnaBridge 143:86740a56073b 6945 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
AnnaBridge 143:86740a56073b 6946 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
AnnaBridge 143:86740a56073b 6947
AnnaBridge 143:86740a56073b 6948 /* Bits 7..0 : NFCID1 byte S */
AnnaBridge 143:86740a56073b 6949 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
AnnaBridge 143:86740a56073b 6950 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
AnnaBridge 143:86740a56073b 6951
AnnaBridge 143:86740a56073b 6952 /* Register: NFCT_SENSRES */
AnnaBridge 143:86740a56073b 6953 /* Description: NFC-A SENS_RES auto-response settings */
AnnaBridge 143:86740a56073b 6954
AnnaBridge 143:86740a56073b 6955 /* Bits 15..12 : Reserved for future use. Shall be 0. */
AnnaBridge 143:86740a56073b 6956 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
AnnaBridge 143:86740a56073b 6957 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
AnnaBridge 143:86740a56073b 6958
AnnaBridge 143:86740a56073b 6959 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
AnnaBridge 143:86740a56073b 6960 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
AnnaBridge 143:86740a56073b 6961 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
AnnaBridge 143:86740a56073b 6962
AnnaBridge 143:86740a56073b 6963 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
AnnaBridge 143:86740a56073b 6964 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
AnnaBridge 143:86740a56073b 6965 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
AnnaBridge 143:86740a56073b 6966 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
AnnaBridge 143:86740a56073b 6967 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
AnnaBridge 143:86740a56073b 6968 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
AnnaBridge 143:86740a56073b 6969
AnnaBridge 143:86740a56073b 6970 /* Bit 5 : Reserved for future use. Shall be 0. */
AnnaBridge 143:86740a56073b 6971 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
AnnaBridge 143:86740a56073b 6972 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
AnnaBridge 143:86740a56073b 6973
AnnaBridge 143:86740a56073b 6974 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
AnnaBridge 143:86740a56073b 6975 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
AnnaBridge 143:86740a56073b 6976 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
AnnaBridge 143:86740a56073b 6977 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
AnnaBridge 143:86740a56073b 6978 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
AnnaBridge 143:86740a56073b 6979 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
AnnaBridge 143:86740a56073b 6980 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
AnnaBridge 143:86740a56073b 6981 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
AnnaBridge 143:86740a56073b 6982 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
AnnaBridge 143:86740a56073b 6983
AnnaBridge 143:86740a56073b 6984 /* Register: NFCT_SELRES */
AnnaBridge 143:86740a56073b 6985 /* Description: NFC-A SEL_RES auto-response settings */
AnnaBridge 143:86740a56073b 6986
AnnaBridge 143:86740a56073b 6987 /* Bit 7 : Reserved for future use. Shall be 0. */
AnnaBridge 143:86740a56073b 6988 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
AnnaBridge 143:86740a56073b 6989 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
AnnaBridge 143:86740a56073b 6990
AnnaBridge 143:86740a56073b 6991 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
AnnaBridge 143:86740a56073b 6992 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
AnnaBridge 143:86740a56073b 6993 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
AnnaBridge 143:86740a56073b 6994
AnnaBridge 143:86740a56073b 6995 /* Bits 4..3 : Reserved for future use. Shall be 0. */
AnnaBridge 143:86740a56073b 6996 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
AnnaBridge 143:86740a56073b 6997 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
AnnaBridge 143:86740a56073b 6998
AnnaBridge 143:86740a56073b 6999 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
AnnaBridge 143:86740a56073b 7000 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
AnnaBridge 143:86740a56073b 7001 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
AnnaBridge 143:86740a56073b 7002 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
AnnaBridge 143:86740a56073b 7003 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
AnnaBridge 143:86740a56073b 7004
AnnaBridge 143:86740a56073b 7005 /* Bits 1..0 : Reserved for future use. Shall be 0. */
AnnaBridge 143:86740a56073b 7006 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
AnnaBridge 143:86740a56073b 7007 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
AnnaBridge 143:86740a56073b 7008
AnnaBridge 143:86740a56073b 7009
AnnaBridge 143:86740a56073b 7010 /* Peripheral: NVMC */
AnnaBridge 143:86740a56073b 7011 /* Description: Non Volatile Memory Controller */
AnnaBridge 143:86740a56073b 7012
AnnaBridge 143:86740a56073b 7013 /* Register: NVMC_READY */
AnnaBridge 143:86740a56073b 7014 /* Description: Ready flag */
AnnaBridge 143:86740a56073b 7015
AnnaBridge 143:86740a56073b 7016 /* Bit 0 : NVMC is ready or busy */
AnnaBridge 143:86740a56073b 7017 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 7018 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 7019 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
AnnaBridge 143:86740a56073b 7020 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
AnnaBridge 143:86740a56073b 7021
AnnaBridge 143:86740a56073b 7022 /* Register: NVMC_CONFIG */
AnnaBridge 143:86740a56073b 7023 /* Description: Configuration register */
AnnaBridge 143:86740a56073b 7024
AnnaBridge 143:86740a56073b 7025 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
AnnaBridge 143:86740a56073b 7026 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
AnnaBridge 143:86740a56073b 7027 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
AnnaBridge 143:86740a56073b 7028 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
AnnaBridge 143:86740a56073b 7029 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
AnnaBridge 143:86740a56073b 7030 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
AnnaBridge 143:86740a56073b 7031
AnnaBridge 143:86740a56073b 7032 /* Register: NVMC_ERASEPAGE */
AnnaBridge 143:86740a56073b 7033 /* Description: Register for erasing a page in Code area */
AnnaBridge 143:86740a56073b 7034
AnnaBridge 143:86740a56073b 7035 /* Bits 31..0 : Register for starting erase of a page in Code area */
AnnaBridge 143:86740a56073b 7036 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
AnnaBridge 143:86740a56073b 7037 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
AnnaBridge 143:86740a56073b 7038
AnnaBridge 143:86740a56073b 7039 /* Register: NVMC_ERASEPCR1 */
AnnaBridge 143:86740a56073b 7040 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
AnnaBridge 143:86740a56073b 7041
AnnaBridge 143:86740a56073b 7042 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
AnnaBridge 143:86740a56073b 7043 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
AnnaBridge 143:86740a56073b 7044 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
AnnaBridge 143:86740a56073b 7045
AnnaBridge 143:86740a56073b 7046 /* Register: NVMC_ERASEALL */
AnnaBridge 143:86740a56073b 7047 /* Description: Register for erasing all non-volatile user memory */
AnnaBridge 143:86740a56073b 7048
AnnaBridge 143:86740a56073b 7049 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
AnnaBridge 143:86740a56073b 7050 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
AnnaBridge 143:86740a56073b 7051 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
AnnaBridge 143:86740a56073b 7052 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
AnnaBridge 143:86740a56073b 7053 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
AnnaBridge 143:86740a56073b 7054
AnnaBridge 143:86740a56073b 7055 /* Register: NVMC_ERASEPCR0 */
AnnaBridge 143:86740a56073b 7056 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
AnnaBridge 143:86740a56073b 7057
AnnaBridge 143:86740a56073b 7058 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
AnnaBridge 143:86740a56073b 7059 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
AnnaBridge 143:86740a56073b 7060 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
AnnaBridge 143:86740a56073b 7061
AnnaBridge 143:86740a56073b 7062 /* Register: NVMC_ERASEUICR */
AnnaBridge 143:86740a56073b 7063 /* Description: Register for erasing User Information Configuration Registers */
AnnaBridge 143:86740a56073b 7064
AnnaBridge 143:86740a56073b 7065 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
AnnaBridge 143:86740a56073b 7066 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
AnnaBridge 143:86740a56073b 7067 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
AnnaBridge 143:86740a56073b 7068 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
AnnaBridge 143:86740a56073b 7069 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
AnnaBridge 143:86740a56073b 7070
AnnaBridge 143:86740a56073b 7071 /* Register: NVMC_ICACHECNF */
AnnaBridge 143:86740a56073b 7072 /* Description: I-Code cache configuration register. */
AnnaBridge 143:86740a56073b 7073
AnnaBridge 143:86740a56073b 7074 /* Bit 8 : Cache profiling enable */
AnnaBridge 143:86740a56073b 7075 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
AnnaBridge 143:86740a56073b 7076 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
AnnaBridge 143:86740a56073b 7077 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
AnnaBridge 143:86740a56073b 7078 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
AnnaBridge 143:86740a56073b 7079
AnnaBridge 143:86740a56073b 7080 /* Bit 0 : Cache enable */
AnnaBridge 143:86740a56073b 7081 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
AnnaBridge 143:86740a56073b 7082 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
AnnaBridge 143:86740a56073b 7083 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
AnnaBridge 143:86740a56073b 7084 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
AnnaBridge 143:86740a56073b 7085
AnnaBridge 143:86740a56073b 7086 /* Register: NVMC_IHIT */
AnnaBridge 143:86740a56073b 7087 /* Description: I-Code cache hit counter. */
AnnaBridge 143:86740a56073b 7088
AnnaBridge 143:86740a56073b 7089 /* Bits 31..0 : Number of cache hits */
AnnaBridge 143:86740a56073b 7090 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
AnnaBridge 143:86740a56073b 7091 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
AnnaBridge 143:86740a56073b 7092
AnnaBridge 143:86740a56073b 7093 /* Register: NVMC_IMISS */
AnnaBridge 143:86740a56073b 7094 /* Description: I-Code cache miss counter. */
AnnaBridge 143:86740a56073b 7095
AnnaBridge 143:86740a56073b 7096 /* Bits 31..0 : Number of cache misses */
AnnaBridge 143:86740a56073b 7097 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
AnnaBridge 143:86740a56073b 7098 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
AnnaBridge 143:86740a56073b 7099
AnnaBridge 143:86740a56073b 7100
AnnaBridge 143:86740a56073b 7101 /* Peripheral: GPIO */
AnnaBridge 143:86740a56073b 7102 /* Description: GPIO Port 1 */
AnnaBridge 143:86740a56073b 7103
AnnaBridge 143:86740a56073b 7104 /* Register: GPIO_OUT */
AnnaBridge 143:86740a56073b 7105 /* Description: Write GPIO port */
AnnaBridge 143:86740a56073b 7106
AnnaBridge 143:86740a56073b 7107 /* Bit 31 : P0.31 pin */
AnnaBridge 143:86740a56073b 7108 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 7109 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 7110 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7111 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7112
AnnaBridge 143:86740a56073b 7113 /* Bit 30 : P0.30 pin */
AnnaBridge 143:86740a56073b 7114 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 7115 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 7116 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7117 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7118
AnnaBridge 143:86740a56073b 7119 /* Bit 29 : P0.29 pin */
AnnaBridge 143:86740a56073b 7120 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 7121 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 7122 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7123 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7124
AnnaBridge 143:86740a56073b 7125 /* Bit 28 : P0.28 pin */
AnnaBridge 143:86740a56073b 7126 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 7127 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 7128 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7129 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7130
AnnaBridge 143:86740a56073b 7131 /* Bit 27 : P0.27 pin */
AnnaBridge 143:86740a56073b 7132 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 7133 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 7134 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7135 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7136
AnnaBridge 143:86740a56073b 7137 /* Bit 26 : P0.26 pin */
AnnaBridge 143:86740a56073b 7138 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 7139 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 7140 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7141 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7142
AnnaBridge 143:86740a56073b 7143 /* Bit 25 : P0.25 pin */
AnnaBridge 143:86740a56073b 7144 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 7145 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 7146 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7147 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7148
AnnaBridge 143:86740a56073b 7149 /* Bit 24 : P0.24 pin */
AnnaBridge 143:86740a56073b 7150 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 7151 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 7152 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7153 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7154
AnnaBridge 143:86740a56073b 7155 /* Bit 23 : P0.23 pin */
AnnaBridge 143:86740a56073b 7156 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 7157 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 7158 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7159 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7160
AnnaBridge 143:86740a56073b 7161 /* Bit 22 : P0.22 pin */
AnnaBridge 143:86740a56073b 7162 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 7163 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 7164 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7165 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7166
AnnaBridge 143:86740a56073b 7167 /* Bit 21 : P0.21 pin */
AnnaBridge 143:86740a56073b 7168 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 7169 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 7170 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7171 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7172
AnnaBridge 143:86740a56073b 7173 /* Bit 20 : P0.20 pin */
AnnaBridge 143:86740a56073b 7174 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 7175 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 7176 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7177 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7178
AnnaBridge 143:86740a56073b 7179 /* Bit 19 : P0.19 pin */
AnnaBridge 143:86740a56073b 7180 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 7181 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 7182 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7183 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7184
AnnaBridge 143:86740a56073b 7185 /* Bit 18 : P0.18 pin */
AnnaBridge 143:86740a56073b 7186 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 7187 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 7188 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7189 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7190
AnnaBridge 143:86740a56073b 7191 /* Bit 17 : P0.17 pin */
AnnaBridge 143:86740a56073b 7192 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 7193 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 7194 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7195 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7196
AnnaBridge 143:86740a56073b 7197 /* Bit 16 : P0.16 pin */
AnnaBridge 143:86740a56073b 7198 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 7199 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 7200 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7201 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7202
AnnaBridge 143:86740a56073b 7203 /* Bit 15 : P0.15 pin */
AnnaBridge 143:86740a56073b 7204 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 7205 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 7206 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7207 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7208
AnnaBridge 143:86740a56073b 7209 /* Bit 14 : P0.14 pin */
AnnaBridge 143:86740a56073b 7210 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 7211 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 7212 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7213 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7214
AnnaBridge 143:86740a56073b 7215 /* Bit 13 : P0.13 pin */
AnnaBridge 143:86740a56073b 7216 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 7217 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 7218 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7219 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7220
AnnaBridge 143:86740a56073b 7221 /* Bit 12 : P0.12 pin */
AnnaBridge 143:86740a56073b 7222 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 7223 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 7224 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7225 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7226
AnnaBridge 143:86740a56073b 7227 /* Bit 11 : P0.11 pin */
AnnaBridge 143:86740a56073b 7228 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 7229 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 7230 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7231 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7232
AnnaBridge 143:86740a56073b 7233 /* Bit 10 : P0.10 pin */
AnnaBridge 143:86740a56073b 7234 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 7235 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 7236 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7237 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7238
AnnaBridge 143:86740a56073b 7239 /* Bit 9 : P0.9 pin */
AnnaBridge 143:86740a56073b 7240 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 7241 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 7242 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7243 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7244
AnnaBridge 143:86740a56073b 7245 /* Bit 8 : P0.8 pin */
AnnaBridge 143:86740a56073b 7246 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 7247 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 7248 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7249 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7250
AnnaBridge 143:86740a56073b 7251 /* Bit 7 : P0.7 pin */
AnnaBridge 143:86740a56073b 7252 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 7253 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 7254 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7255 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7256
AnnaBridge 143:86740a56073b 7257 /* Bit 6 : P0.6 pin */
AnnaBridge 143:86740a56073b 7258 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 7259 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 7260 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7261 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7262
AnnaBridge 143:86740a56073b 7263 /* Bit 5 : P0.5 pin */
AnnaBridge 143:86740a56073b 7264 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 7265 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 7266 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7267 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7268
AnnaBridge 143:86740a56073b 7269 /* Bit 4 : P0.4 pin */
AnnaBridge 143:86740a56073b 7270 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 7271 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 7272 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7273 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7274
AnnaBridge 143:86740a56073b 7275 /* Bit 3 : P0.3 pin */
AnnaBridge 143:86740a56073b 7276 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 7277 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 7278 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7279 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7280
AnnaBridge 143:86740a56073b 7281 /* Bit 2 : P0.2 pin */
AnnaBridge 143:86740a56073b 7282 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 7283 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 7284 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7285 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7286
AnnaBridge 143:86740a56073b 7287 /* Bit 1 : P0.1 pin */
AnnaBridge 143:86740a56073b 7288 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 7289 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 7290 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7291 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7292
AnnaBridge 143:86740a56073b 7293 /* Bit 0 : P0.0 pin */
AnnaBridge 143:86740a56073b 7294 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 7295 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 7296 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
AnnaBridge 143:86740a56073b 7297 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
AnnaBridge 143:86740a56073b 7298
AnnaBridge 143:86740a56073b 7299 /* Register: GPIO_OUTSET */
AnnaBridge 143:86740a56073b 7300 /* Description: Set individual bits in GPIO port */
AnnaBridge 143:86740a56073b 7301
AnnaBridge 143:86740a56073b 7302 /* Bit 31 : P0.31 pin */
AnnaBridge 143:86740a56073b 7303 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 7304 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 7305 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7306 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7307 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7308
AnnaBridge 143:86740a56073b 7309 /* Bit 30 : P0.30 pin */
AnnaBridge 143:86740a56073b 7310 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 7311 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 7312 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7313 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7314 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7315
AnnaBridge 143:86740a56073b 7316 /* Bit 29 : P0.29 pin */
AnnaBridge 143:86740a56073b 7317 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 7318 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 7319 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7320 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7321 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7322
AnnaBridge 143:86740a56073b 7323 /* Bit 28 : P0.28 pin */
AnnaBridge 143:86740a56073b 7324 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 7325 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 7326 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7327 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7328 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7329
AnnaBridge 143:86740a56073b 7330 /* Bit 27 : P0.27 pin */
AnnaBridge 143:86740a56073b 7331 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 7332 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 7333 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7334 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7335 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7336
AnnaBridge 143:86740a56073b 7337 /* Bit 26 : P0.26 pin */
AnnaBridge 143:86740a56073b 7338 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 7339 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 7340 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7341 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7342 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7343
AnnaBridge 143:86740a56073b 7344 /* Bit 25 : P0.25 pin */
AnnaBridge 143:86740a56073b 7345 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 7346 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 7347 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7348 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7349 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7350
AnnaBridge 143:86740a56073b 7351 /* Bit 24 : P0.24 pin */
AnnaBridge 143:86740a56073b 7352 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 7353 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 7354 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7355 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7356 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7357
AnnaBridge 143:86740a56073b 7358 /* Bit 23 : P0.23 pin */
AnnaBridge 143:86740a56073b 7359 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 7360 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 7361 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7362 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7363 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7364
AnnaBridge 143:86740a56073b 7365 /* Bit 22 : P0.22 pin */
AnnaBridge 143:86740a56073b 7366 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 7367 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 7368 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7369 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7370 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7371
AnnaBridge 143:86740a56073b 7372 /* Bit 21 : P0.21 pin */
AnnaBridge 143:86740a56073b 7373 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 7374 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 7375 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7376 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7377 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7378
AnnaBridge 143:86740a56073b 7379 /* Bit 20 : P0.20 pin */
AnnaBridge 143:86740a56073b 7380 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 7381 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 7382 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7383 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7384 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7385
AnnaBridge 143:86740a56073b 7386 /* Bit 19 : P0.19 pin */
AnnaBridge 143:86740a56073b 7387 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 7388 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 7389 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7390 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7391 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7392
AnnaBridge 143:86740a56073b 7393 /* Bit 18 : P0.18 pin */
AnnaBridge 143:86740a56073b 7394 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 7395 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 7396 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7397 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7398 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7399
AnnaBridge 143:86740a56073b 7400 /* Bit 17 : P0.17 pin */
AnnaBridge 143:86740a56073b 7401 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 7402 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 7403 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7404 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7405 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7406
AnnaBridge 143:86740a56073b 7407 /* Bit 16 : P0.16 pin */
AnnaBridge 143:86740a56073b 7408 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 7409 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 7410 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7411 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7412 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7413
AnnaBridge 143:86740a56073b 7414 /* Bit 15 : P0.15 pin */
AnnaBridge 143:86740a56073b 7415 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 7416 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 7417 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7418 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7419 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7420
AnnaBridge 143:86740a56073b 7421 /* Bit 14 : P0.14 pin */
AnnaBridge 143:86740a56073b 7422 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 7423 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 7424 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7425 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7426 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7427
AnnaBridge 143:86740a56073b 7428 /* Bit 13 : P0.13 pin */
AnnaBridge 143:86740a56073b 7429 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 7430 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 7431 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7432 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7433 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7434
AnnaBridge 143:86740a56073b 7435 /* Bit 12 : P0.12 pin */
AnnaBridge 143:86740a56073b 7436 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 7437 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 7438 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7439 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7440 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7441
AnnaBridge 143:86740a56073b 7442 /* Bit 11 : P0.11 pin */
AnnaBridge 143:86740a56073b 7443 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 7444 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 7445 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7446 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7447 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7448
AnnaBridge 143:86740a56073b 7449 /* Bit 10 : P0.10 pin */
AnnaBridge 143:86740a56073b 7450 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 7451 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 7452 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7453 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7454 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7455
AnnaBridge 143:86740a56073b 7456 /* Bit 9 : P0.9 pin */
AnnaBridge 143:86740a56073b 7457 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 7458 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 7459 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7460 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7461 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7462
AnnaBridge 143:86740a56073b 7463 /* Bit 8 : P0.8 pin */
AnnaBridge 143:86740a56073b 7464 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 7465 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 7466 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7467 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7468 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7469
AnnaBridge 143:86740a56073b 7470 /* Bit 7 : P0.7 pin */
AnnaBridge 143:86740a56073b 7471 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 7472 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 7473 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7474 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7475 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7476
AnnaBridge 143:86740a56073b 7477 /* Bit 6 : P0.6 pin */
AnnaBridge 143:86740a56073b 7478 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 7479 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 7480 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7481 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7482 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7483
AnnaBridge 143:86740a56073b 7484 /* Bit 5 : P0.5 pin */
AnnaBridge 143:86740a56073b 7485 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 7486 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 7487 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7488 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7489 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7490
AnnaBridge 143:86740a56073b 7491 /* Bit 4 : P0.4 pin */
AnnaBridge 143:86740a56073b 7492 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 7493 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 7494 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7495 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7496 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7497
AnnaBridge 143:86740a56073b 7498 /* Bit 3 : P0.3 pin */
AnnaBridge 143:86740a56073b 7499 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 7500 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 7501 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7502 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7503 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7504
AnnaBridge 143:86740a56073b 7505 /* Bit 2 : P0.2 pin */
AnnaBridge 143:86740a56073b 7506 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 7507 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 7508 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7509 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7510 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7511
AnnaBridge 143:86740a56073b 7512 /* Bit 1 : P0.1 pin */
AnnaBridge 143:86740a56073b 7513 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 7514 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 7515 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7516 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7517 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7518
AnnaBridge 143:86740a56073b 7519 /* Bit 0 : P0.0 pin */
AnnaBridge 143:86740a56073b 7520 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 7521 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 7522 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7523 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7524 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7525
AnnaBridge 143:86740a56073b 7526 /* Register: GPIO_OUTCLR */
AnnaBridge 143:86740a56073b 7527 /* Description: Clear individual bits in GPIO port */
AnnaBridge 143:86740a56073b 7528
AnnaBridge 143:86740a56073b 7529 /* Bit 31 : P0.31 pin */
AnnaBridge 143:86740a56073b 7530 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 7531 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 7532 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7533 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7534 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7535
AnnaBridge 143:86740a56073b 7536 /* Bit 30 : P0.30 pin */
AnnaBridge 143:86740a56073b 7537 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 7538 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 7539 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7540 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7541 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7542
AnnaBridge 143:86740a56073b 7543 /* Bit 29 : P0.29 pin */
AnnaBridge 143:86740a56073b 7544 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 7545 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 7546 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7547 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7548 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7549
AnnaBridge 143:86740a56073b 7550 /* Bit 28 : P0.28 pin */
AnnaBridge 143:86740a56073b 7551 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 7552 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 7553 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7554 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7555 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7556
AnnaBridge 143:86740a56073b 7557 /* Bit 27 : P0.27 pin */
AnnaBridge 143:86740a56073b 7558 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 7559 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 7560 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7561 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7562 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7563
AnnaBridge 143:86740a56073b 7564 /* Bit 26 : P0.26 pin */
AnnaBridge 143:86740a56073b 7565 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 7566 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 7567 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7568 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7569 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7570
AnnaBridge 143:86740a56073b 7571 /* Bit 25 : P0.25 pin */
AnnaBridge 143:86740a56073b 7572 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 7573 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 7574 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7575 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7576 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7577
AnnaBridge 143:86740a56073b 7578 /* Bit 24 : P0.24 pin */
AnnaBridge 143:86740a56073b 7579 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 7580 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 7581 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7582 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7583 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7584
AnnaBridge 143:86740a56073b 7585 /* Bit 23 : P0.23 pin */
AnnaBridge 143:86740a56073b 7586 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 7587 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 7588 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7589 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7590 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7591
AnnaBridge 143:86740a56073b 7592 /* Bit 22 : P0.22 pin */
AnnaBridge 143:86740a56073b 7593 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 7594 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 7595 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7596 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7597 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7598
AnnaBridge 143:86740a56073b 7599 /* Bit 21 : P0.21 pin */
AnnaBridge 143:86740a56073b 7600 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 7601 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 7602 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7603 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7604 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7605
AnnaBridge 143:86740a56073b 7606 /* Bit 20 : P0.20 pin */
AnnaBridge 143:86740a56073b 7607 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 7608 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 7609 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7610 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7611 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7612
AnnaBridge 143:86740a56073b 7613 /* Bit 19 : P0.19 pin */
AnnaBridge 143:86740a56073b 7614 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 7615 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 7616 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7617 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7618 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7619
AnnaBridge 143:86740a56073b 7620 /* Bit 18 : P0.18 pin */
AnnaBridge 143:86740a56073b 7621 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 7622 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 7623 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7624 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7625 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7626
AnnaBridge 143:86740a56073b 7627 /* Bit 17 : P0.17 pin */
AnnaBridge 143:86740a56073b 7628 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 7629 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 7630 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7631 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7632 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7633
AnnaBridge 143:86740a56073b 7634 /* Bit 16 : P0.16 pin */
AnnaBridge 143:86740a56073b 7635 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 7636 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 7637 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7638 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7639 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7640
AnnaBridge 143:86740a56073b 7641 /* Bit 15 : P0.15 pin */
AnnaBridge 143:86740a56073b 7642 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 7643 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 7644 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7645 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7646 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7647
AnnaBridge 143:86740a56073b 7648 /* Bit 14 : P0.14 pin */
AnnaBridge 143:86740a56073b 7649 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 7650 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 7651 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7652 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7653 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7654
AnnaBridge 143:86740a56073b 7655 /* Bit 13 : P0.13 pin */
AnnaBridge 143:86740a56073b 7656 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 7657 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 7658 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7659 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7660 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7661
AnnaBridge 143:86740a56073b 7662 /* Bit 12 : P0.12 pin */
AnnaBridge 143:86740a56073b 7663 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 7664 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 7665 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7666 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7667 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7668
AnnaBridge 143:86740a56073b 7669 /* Bit 11 : P0.11 pin */
AnnaBridge 143:86740a56073b 7670 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 7671 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 7672 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7673 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7674 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7675
AnnaBridge 143:86740a56073b 7676 /* Bit 10 : P0.10 pin */
AnnaBridge 143:86740a56073b 7677 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 7678 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 7679 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7680 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7681 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7682
AnnaBridge 143:86740a56073b 7683 /* Bit 9 : P0.9 pin */
AnnaBridge 143:86740a56073b 7684 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 7685 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 7686 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7687 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7688 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7689
AnnaBridge 143:86740a56073b 7690 /* Bit 8 : P0.8 pin */
AnnaBridge 143:86740a56073b 7691 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 7692 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 7693 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7694 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7695 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7696
AnnaBridge 143:86740a56073b 7697 /* Bit 7 : P0.7 pin */
AnnaBridge 143:86740a56073b 7698 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 7699 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 7700 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7701 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7702 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7703
AnnaBridge 143:86740a56073b 7704 /* Bit 6 : P0.6 pin */
AnnaBridge 143:86740a56073b 7705 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 7706 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 7707 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7708 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7709 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7710
AnnaBridge 143:86740a56073b 7711 /* Bit 5 : P0.5 pin */
AnnaBridge 143:86740a56073b 7712 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 7713 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 7714 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7715 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7716 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7717
AnnaBridge 143:86740a56073b 7718 /* Bit 4 : P0.4 pin */
AnnaBridge 143:86740a56073b 7719 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 7720 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 7721 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7722 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7723 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7724
AnnaBridge 143:86740a56073b 7725 /* Bit 3 : P0.3 pin */
AnnaBridge 143:86740a56073b 7726 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 7727 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 7728 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7729 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7730 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7731
AnnaBridge 143:86740a56073b 7732 /* Bit 2 : P0.2 pin */
AnnaBridge 143:86740a56073b 7733 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 7734 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 7735 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7736 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7737 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7738
AnnaBridge 143:86740a56073b 7739 /* Bit 1 : P0.1 pin */
AnnaBridge 143:86740a56073b 7740 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 7741 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 7742 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7743 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7744 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7745
AnnaBridge 143:86740a56073b 7746 /* Bit 0 : P0.0 pin */
AnnaBridge 143:86740a56073b 7747 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 7748 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 7749 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
AnnaBridge 143:86740a56073b 7750 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
AnnaBridge 143:86740a56073b 7751 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 7752
AnnaBridge 143:86740a56073b 7753 /* Register: GPIO_IN */
AnnaBridge 143:86740a56073b 7754 /* Description: Read GPIO port */
AnnaBridge 143:86740a56073b 7755
AnnaBridge 143:86740a56073b 7756 /* Bit 31 : P0.31 pin */
AnnaBridge 143:86740a56073b 7757 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 7758 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 7759 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7760 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7761
AnnaBridge 143:86740a56073b 7762 /* Bit 30 : P0.30 pin */
AnnaBridge 143:86740a56073b 7763 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 7764 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 7765 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7766 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7767
AnnaBridge 143:86740a56073b 7768 /* Bit 29 : P0.29 pin */
AnnaBridge 143:86740a56073b 7769 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 7770 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 7771 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7772 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7773
AnnaBridge 143:86740a56073b 7774 /* Bit 28 : P0.28 pin */
AnnaBridge 143:86740a56073b 7775 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 7776 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 7777 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7778 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7779
AnnaBridge 143:86740a56073b 7780 /* Bit 27 : P0.27 pin */
AnnaBridge 143:86740a56073b 7781 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 7782 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 7783 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7784 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7785
AnnaBridge 143:86740a56073b 7786 /* Bit 26 : P0.26 pin */
AnnaBridge 143:86740a56073b 7787 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 7788 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 7789 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7790 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7791
AnnaBridge 143:86740a56073b 7792 /* Bit 25 : P0.25 pin */
AnnaBridge 143:86740a56073b 7793 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 7794 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 7795 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7796 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7797
AnnaBridge 143:86740a56073b 7798 /* Bit 24 : P0.24 pin */
AnnaBridge 143:86740a56073b 7799 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 7800 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 7801 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7802 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7803
AnnaBridge 143:86740a56073b 7804 /* Bit 23 : P0.23 pin */
AnnaBridge 143:86740a56073b 7805 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 7806 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 7807 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7808 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7809
AnnaBridge 143:86740a56073b 7810 /* Bit 22 : P0.22 pin */
AnnaBridge 143:86740a56073b 7811 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 7812 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 7813 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7814 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7815
AnnaBridge 143:86740a56073b 7816 /* Bit 21 : P0.21 pin */
AnnaBridge 143:86740a56073b 7817 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 7818 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 7819 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7820 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7821
AnnaBridge 143:86740a56073b 7822 /* Bit 20 : P0.20 pin */
AnnaBridge 143:86740a56073b 7823 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 7824 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 7825 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7826 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7827
AnnaBridge 143:86740a56073b 7828 /* Bit 19 : P0.19 pin */
AnnaBridge 143:86740a56073b 7829 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 7830 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 7831 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7832 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7833
AnnaBridge 143:86740a56073b 7834 /* Bit 18 : P0.18 pin */
AnnaBridge 143:86740a56073b 7835 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 7836 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 7837 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7838 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7839
AnnaBridge 143:86740a56073b 7840 /* Bit 17 : P0.17 pin */
AnnaBridge 143:86740a56073b 7841 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 7842 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 7843 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7844 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7845
AnnaBridge 143:86740a56073b 7846 /* Bit 16 : P0.16 pin */
AnnaBridge 143:86740a56073b 7847 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 7848 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 7849 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7850 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7851
AnnaBridge 143:86740a56073b 7852 /* Bit 15 : P0.15 pin */
AnnaBridge 143:86740a56073b 7853 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 7854 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 7855 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7856 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7857
AnnaBridge 143:86740a56073b 7858 /* Bit 14 : P0.14 pin */
AnnaBridge 143:86740a56073b 7859 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 7860 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 7861 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7862 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7863
AnnaBridge 143:86740a56073b 7864 /* Bit 13 : P0.13 pin */
AnnaBridge 143:86740a56073b 7865 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 7866 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 7867 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7868 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7869
AnnaBridge 143:86740a56073b 7870 /* Bit 12 : P0.12 pin */
AnnaBridge 143:86740a56073b 7871 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 7872 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 7873 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7874 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7875
AnnaBridge 143:86740a56073b 7876 /* Bit 11 : P0.11 pin */
AnnaBridge 143:86740a56073b 7877 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 7878 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 7879 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7880 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7881
AnnaBridge 143:86740a56073b 7882 /* Bit 10 : P0.10 pin */
AnnaBridge 143:86740a56073b 7883 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 7884 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 7885 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7886 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7887
AnnaBridge 143:86740a56073b 7888 /* Bit 9 : P0.9 pin */
AnnaBridge 143:86740a56073b 7889 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 7890 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 7891 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7892 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7893
AnnaBridge 143:86740a56073b 7894 /* Bit 8 : P0.8 pin */
AnnaBridge 143:86740a56073b 7895 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 7896 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 7897 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7898 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7899
AnnaBridge 143:86740a56073b 7900 /* Bit 7 : P0.7 pin */
AnnaBridge 143:86740a56073b 7901 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 7902 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 7903 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7904 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7905
AnnaBridge 143:86740a56073b 7906 /* Bit 6 : P0.6 pin */
AnnaBridge 143:86740a56073b 7907 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 7908 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 7909 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7910 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7911
AnnaBridge 143:86740a56073b 7912 /* Bit 5 : P0.5 pin */
AnnaBridge 143:86740a56073b 7913 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 7914 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 7915 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7916 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7917
AnnaBridge 143:86740a56073b 7918 /* Bit 4 : P0.4 pin */
AnnaBridge 143:86740a56073b 7919 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 7920 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 7921 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7922 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7923
AnnaBridge 143:86740a56073b 7924 /* Bit 3 : P0.3 pin */
AnnaBridge 143:86740a56073b 7925 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 7926 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 7927 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7928 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7929
AnnaBridge 143:86740a56073b 7930 /* Bit 2 : P0.2 pin */
AnnaBridge 143:86740a56073b 7931 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 7932 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 7933 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7934 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7935
AnnaBridge 143:86740a56073b 7936 /* Bit 1 : P0.1 pin */
AnnaBridge 143:86740a56073b 7937 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 7938 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 7939 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7940 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7941
AnnaBridge 143:86740a56073b 7942 /* Bit 0 : P0.0 pin */
AnnaBridge 143:86740a56073b 7943 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 7944 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 7945 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
AnnaBridge 143:86740a56073b 7946 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
AnnaBridge 143:86740a56073b 7947
AnnaBridge 143:86740a56073b 7948 /* Register: GPIO_DIR */
AnnaBridge 143:86740a56073b 7949 /* Description: Direction of GPIO pins */
AnnaBridge 143:86740a56073b 7950
AnnaBridge 143:86740a56073b 7951 /* Bit 31 : P0.31 pin */
AnnaBridge 143:86740a56073b 7952 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 7953 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 7954 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7955 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7956
AnnaBridge 143:86740a56073b 7957 /* Bit 30 : P0.30 pin */
AnnaBridge 143:86740a56073b 7958 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 7959 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 7960 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7961 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7962
AnnaBridge 143:86740a56073b 7963 /* Bit 29 : P0.29 pin */
AnnaBridge 143:86740a56073b 7964 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 7965 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 7966 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7967 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7968
AnnaBridge 143:86740a56073b 7969 /* Bit 28 : P0.28 pin */
AnnaBridge 143:86740a56073b 7970 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 7971 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 7972 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7973 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7974
AnnaBridge 143:86740a56073b 7975 /* Bit 27 : P0.27 pin */
AnnaBridge 143:86740a56073b 7976 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 7977 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 7978 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7979 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7980
AnnaBridge 143:86740a56073b 7981 /* Bit 26 : P0.26 pin */
AnnaBridge 143:86740a56073b 7982 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 7983 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 7984 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7985 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7986
AnnaBridge 143:86740a56073b 7987 /* Bit 25 : P0.25 pin */
AnnaBridge 143:86740a56073b 7988 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 7989 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 7990 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7991 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7992
AnnaBridge 143:86740a56073b 7993 /* Bit 24 : P0.24 pin */
AnnaBridge 143:86740a56073b 7994 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 7995 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 7996 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 7997 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 7998
AnnaBridge 143:86740a56073b 7999 /* Bit 23 : P0.23 pin */
AnnaBridge 143:86740a56073b 8000 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 8001 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 8002 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8003 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8004
AnnaBridge 143:86740a56073b 8005 /* Bit 22 : P0.22 pin */
AnnaBridge 143:86740a56073b 8006 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 8007 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 8008 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8009 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8010
AnnaBridge 143:86740a56073b 8011 /* Bit 21 : P0.21 pin */
AnnaBridge 143:86740a56073b 8012 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 8013 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 8014 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8015 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8016
AnnaBridge 143:86740a56073b 8017 /* Bit 20 : P0.20 pin */
AnnaBridge 143:86740a56073b 8018 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 8019 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 8020 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8021 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8022
AnnaBridge 143:86740a56073b 8023 /* Bit 19 : P0.19 pin */
AnnaBridge 143:86740a56073b 8024 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 8025 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 8026 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8027 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8028
AnnaBridge 143:86740a56073b 8029 /* Bit 18 : P0.18 pin */
AnnaBridge 143:86740a56073b 8030 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 8031 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 8032 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8033 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8034
AnnaBridge 143:86740a56073b 8035 /* Bit 17 : P0.17 pin */
AnnaBridge 143:86740a56073b 8036 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 8037 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 8038 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8039 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8040
AnnaBridge 143:86740a56073b 8041 /* Bit 16 : P0.16 pin */
AnnaBridge 143:86740a56073b 8042 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 8043 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 8044 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8045 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8046
AnnaBridge 143:86740a56073b 8047 /* Bit 15 : P0.15 pin */
AnnaBridge 143:86740a56073b 8048 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 8049 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 8050 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8051 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8052
AnnaBridge 143:86740a56073b 8053 /* Bit 14 : P0.14 pin */
AnnaBridge 143:86740a56073b 8054 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 8055 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 8056 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8057 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8058
AnnaBridge 143:86740a56073b 8059 /* Bit 13 : P0.13 pin */
AnnaBridge 143:86740a56073b 8060 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 8061 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 8062 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8063 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8064
AnnaBridge 143:86740a56073b 8065 /* Bit 12 : P0.12 pin */
AnnaBridge 143:86740a56073b 8066 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 8067 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 8068 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8069 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8070
AnnaBridge 143:86740a56073b 8071 /* Bit 11 : P0.11 pin */
AnnaBridge 143:86740a56073b 8072 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 8073 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 8074 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8075 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8076
AnnaBridge 143:86740a56073b 8077 /* Bit 10 : P0.10 pin */
AnnaBridge 143:86740a56073b 8078 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 8079 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 8080 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8081 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8082
AnnaBridge 143:86740a56073b 8083 /* Bit 9 : P0.9 pin */
AnnaBridge 143:86740a56073b 8084 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 8085 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 8086 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8087 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8088
AnnaBridge 143:86740a56073b 8089 /* Bit 8 : P0.8 pin */
AnnaBridge 143:86740a56073b 8090 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 8091 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 8092 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8093 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8094
AnnaBridge 143:86740a56073b 8095 /* Bit 7 : P0.7 pin */
AnnaBridge 143:86740a56073b 8096 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 8097 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 8098 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8099 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8100
AnnaBridge 143:86740a56073b 8101 /* Bit 6 : P0.6 pin */
AnnaBridge 143:86740a56073b 8102 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 8103 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 8104 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8105 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8106
AnnaBridge 143:86740a56073b 8107 /* Bit 5 : P0.5 pin */
AnnaBridge 143:86740a56073b 8108 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 8109 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 8110 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8111 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8112
AnnaBridge 143:86740a56073b 8113 /* Bit 4 : P0.4 pin */
AnnaBridge 143:86740a56073b 8114 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 8115 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 8116 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8117 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8118
AnnaBridge 143:86740a56073b 8119 /* Bit 3 : P0.3 pin */
AnnaBridge 143:86740a56073b 8120 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 8121 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 8122 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8123 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8124
AnnaBridge 143:86740a56073b 8125 /* Bit 2 : P0.2 pin */
AnnaBridge 143:86740a56073b 8126 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 8127 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 8128 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8129 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8130
AnnaBridge 143:86740a56073b 8131 /* Bit 1 : P0.1 pin */
AnnaBridge 143:86740a56073b 8132 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 8133 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 8134 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8135 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8136
AnnaBridge 143:86740a56073b 8137 /* Bit 0 : P0.0 pin */
AnnaBridge 143:86740a56073b 8138 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 8139 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 8140 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
AnnaBridge 143:86740a56073b 8141 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
AnnaBridge 143:86740a56073b 8142
AnnaBridge 143:86740a56073b 8143 /* Register: GPIO_DIRSET */
AnnaBridge 143:86740a56073b 8144 /* Description: DIR set register */
AnnaBridge 143:86740a56073b 8145
AnnaBridge 143:86740a56073b 8146 /* Bit 31 : Set as output pin 31 */
AnnaBridge 143:86740a56073b 8147 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 8148 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 8149 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8150 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8151 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8152
AnnaBridge 143:86740a56073b 8153 /* Bit 30 : Set as output pin 30 */
AnnaBridge 143:86740a56073b 8154 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 8155 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 8156 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8157 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8158 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8159
AnnaBridge 143:86740a56073b 8160 /* Bit 29 : Set as output pin 29 */
AnnaBridge 143:86740a56073b 8161 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 8162 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 8163 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8164 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8165 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8166
AnnaBridge 143:86740a56073b 8167 /* Bit 28 : Set as output pin 28 */
AnnaBridge 143:86740a56073b 8168 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 8169 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 8170 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8171 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8172 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8173
AnnaBridge 143:86740a56073b 8174 /* Bit 27 : Set as output pin 27 */
AnnaBridge 143:86740a56073b 8175 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 8176 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 8177 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8178 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8179 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8180
AnnaBridge 143:86740a56073b 8181 /* Bit 26 : Set as output pin 26 */
AnnaBridge 143:86740a56073b 8182 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 8183 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 8184 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8185 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8186 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8187
AnnaBridge 143:86740a56073b 8188 /* Bit 25 : Set as output pin 25 */
AnnaBridge 143:86740a56073b 8189 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 8190 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 8191 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8192 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8193 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8194
AnnaBridge 143:86740a56073b 8195 /* Bit 24 : Set as output pin 24 */
AnnaBridge 143:86740a56073b 8196 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 8197 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 8198 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8199 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8200 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8201
AnnaBridge 143:86740a56073b 8202 /* Bit 23 : Set as output pin 23 */
AnnaBridge 143:86740a56073b 8203 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 8204 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 8205 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8206 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8207 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8208
AnnaBridge 143:86740a56073b 8209 /* Bit 22 : Set as output pin 22 */
AnnaBridge 143:86740a56073b 8210 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 8211 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 8212 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8213 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8214 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8215
AnnaBridge 143:86740a56073b 8216 /* Bit 21 : Set as output pin 21 */
AnnaBridge 143:86740a56073b 8217 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 8218 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 8219 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8220 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8221 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8222
AnnaBridge 143:86740a56073b 8223 /* Bit 20 : Set as output pin 20 */
AnnaBridge 143:86740a56073b 8224 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 8225 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 8226 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8227 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8228 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8229
AnnaBridge 143:86740a56073b 8230 /* Bit 19 : Set as output pin 19 */
AnnaBridge 143:86740a56073b 8231 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 8232 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 8233 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8234 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8235 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8236
AnnaBridge 143:86740a56073b 8237 /* Bit 18 : Set as output pin 18 */
AnnaBridge 143:86740a56073b 8238 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 8239 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 8240 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8241 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8242 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8243
AnnaBridge 143:86740a56073b 8244 /* Bit 17 : Set as output pin 17 */
AnnaBridge 143:86740a56073b 8245 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 8246 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 8247 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8248 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8249 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8250
AnnaBridge 143:86740a56073b 8251 /* Bit 16 : Set as output pin 16 */
AnnaBridge 143:86740a56073b 8252 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 8253 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 8254 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8255 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8256 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8257
AnnaBridge 143:86740a56073b 8258 /* Bit 15 : Set as output pin 15 */
AnnaBridge 143:86740a56073b 8259 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 8260 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 8261 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8262 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8263 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8264
AnnaBridge 143:86740a56073b 8265 /* Bit 14 : Set as output pin 14 */
AnnaBridge 143:86740a56073b 8266 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 8267 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 8268 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8269 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8270 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8271
AnnaBridge 143:86740a56073b 8272 /* Bit 13 : Set as output pin 13 */
AnnaBridge 143:86740a56073b 8273 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 8274 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 8275 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8276 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8277 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8278
AnnaBridge 143:86740a56073b 8279 /* Bit 12 : Set as output pin 12 */
AnnaBridge 143:86740a56073b 8280 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 8281 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 8282 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8283 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8284 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8285
AnnaBridge 143:86740a56073b 8286 /* Bit 11 : Set as output pin 11 */
AnnaBridge 143:86740a56073b 8287 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 8288 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 8289 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8290 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8291 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8292
AnnaBridge 143:86740a56073b 8293 /* Bit 10 : Set as output pin 10 */
AnnaBridge 143:86740a56073b 8294 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 8295 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 8296 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8297 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8298 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8299
AnnaBridge 143:86740a56073b 8300 /* Bit 9 : Set as output pin 9 */
AnnaBridge 143:86740a56073b 8301 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 8302 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 8303 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8304 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8305 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8306
AnnaBridge 143:86740a56073b 8307 /* Bit 8 : Set as output pin 8 */
AnnaBridge 143:86740a56073b 8308 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 8309 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 8310 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8311 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8312 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8313
AnnaBridge 143:86740a56073b 8314 /* Bit 7 : Set as output pin 7 */
AnnaBridge 143:86740a56073b 8315 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 8316 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 8317 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8318 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8319 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8320
AnnaBridge 143:86740a56073b 8321 /* Bit 6 : Set as output pin 6 */
AnnaBridge 143:86740a56073b 8322 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 8323 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 8324 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8325 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8326 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8327
AnnaBridge 143:86740a56073b 8328 /* Bit 5 : Set as output pin 5 */
AnnaBridge 143:86740a56073b 8329 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 8330 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 8331 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8332 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8333 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8334
AnnaBridge 143:86740a56073b 8335 /* Bit 4 : Set as output pin 4 */
AnnaBridge 143:86740a56073b 8336 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 8337 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 8338 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8339 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8340 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8341
AnnaBridge 143:86740a56073b 8342 /* Bit 3 : Set as output pin 3 */
AnnaBridge 143:86740a56073b 8343 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 8344 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 8345 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8346 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8347 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8348
AnnaBridge 143:86740a56073b 8349 /* Bit 2 : Set as output pin 2 */
AnnaBridge 143:86740a56073b 8350 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 8351 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 8352 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8353 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8354 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8355
AnnaBridge 143:86740a56073b 8356 /* Bit 1 : Set as output pin 1 */
AnnaBridge 143:86740a56073b 8357 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 8358 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 8359 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8360 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8361 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8362
AnnaBridge 143:86740a56073b 8363 /* Bit 0 : Set as output pin 0 */
AnnaBridge 143:86740a56073b 8364 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 8365 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 8366 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8367 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8368 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8369
AnnaBridge 143:86740a56073b 8370 /* Register: GPIO_DIRCLR */
AnnaBridge 143:86740a56073b 8371 /* Description: DIR clear register */
AnnaBridge 143:86740a56073b 8372
AnnaBridge 143:86740a56073b 8373 /* Bit 31 : Set as input pin 31 */
AnnaBridge 143:86740a56073b 8374 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 8375 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 8376 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8377 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8378 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8379
AnnaBridge 143:86740a56073b 8380 /* Bit 30 : Set as input pin 30 */
AnnaBridge 143:86740a56073b 8381 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 8382 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 8383 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8384 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8385 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8386
AnnaBridge 143:86740a56073b 8387 /* Bit 29 : Set as input pin 29 */
AnnaBridge 143:86740a56073b 8388 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 8389 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 8390 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8391 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8392 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8393
AnnaBridge 143:86740a56073b 8394 /* Bit 28 : Set as input pin 28 */
AnnaBridge 143:86740a56073b 8395 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 8396 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 8397 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8398 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8399 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8400
AnnaBridge 143:86740a56073b 8401 /* Bit 27 : Set as input pin 27 */
AnnaBridge 143:86740a56073b 8402 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 8403 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 8404 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8405 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8406 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8407
AnnaBridge 143:86740a56073b 8408 /* Bit 26 : Set as input pin 26 */
AnnaBridge 143:86740a56073b 8409 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 8410 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 8411 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8412 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8413 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8414
AnnaBridge 143:86740a56073b 8415 /* Bit 25 : Set as input pin 25 */
AnnaBridge 143:86740a56073b 8416 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 8417 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 8418 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8419 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8420 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8421
AnnaBridge 143:86740a56073b 8422 /* Bit 24 : Set as input pin 24 */
AnnaBridge 143:86740a56073b 8423 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 8424 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 8425 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8426 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8427 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8428
AnnaBridge 143:86740a56073b 8429 /* Bit 23 : Set as input pin 23 */
AnnaBridge 143:86740a56073b 8430 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 8431 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 8432 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8433 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8434 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8435
AnnaBridge 143:86740a56073b 8436 /* Bit 22 : Set as input pin 22 */
AnnaBridge 143:86740a56073b 8437 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 8438 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 8439 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8440 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8441 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8442
AnnaBridge 143:86740a56073b 8443 /* Bit 21 : Set as input pin 21 */
AnnaBridge 143:86740a56073b 8444 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 8445 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 8446 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8447 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8448 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8449
AnnaBridge 143:86740a56073b 8450 /* Bit 20 : Set as input pin 20 */
AnnaBridge 143:86740a56073b 8451 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 8452 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 8453 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8454 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8455 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8456
AnnaBridge 143:86740a56073b 8457 /* Bit 19 : Set as input pin 19 */
AnnaBridge 143:86740a56073b 8458 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 8459 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 8460 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8461 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8462 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8463
AnnaBridge 143:86740a56073b 8464 /* Bit 18 : Set as input pin 18 */
AnnaBridge 143:86740a56073b 8465 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 8466 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 8467 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8468 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8469 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8470
AnnaBridge 143:86740a56073b 8471 /* Bit 17 : Set as input pin 17 */
AnnaBridge 143:86740a56073b 8472 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 8473 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 8474 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8475 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8476 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8477
AnnaBridge 143:86740a56073b 8478 /* Bit 16 : Set as input pin 16 */
AnnaBridge 143:86740a56073b 8479 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 8480 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 8481 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8482 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8483 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8484
AnnaBridge 143:86740a56073b 8485 /* Bit 15 : Set as input pin 15 */
AnnaBridge 143:86740a56073b 8486 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 8487 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 8488 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8489 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8490 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8491
AnnaBridge 143:86740a56073b 8492 /* Bit 14 : Set as input pin 14 */
AnnaBridge 143:86740a56073b 8493 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 8494 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 8495 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8496 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8497 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8498
AnnaBridge 143:86740a56073b 8499 /* Bit 13 : Set as input pin 13 */
AnnaBridge 143:86740a56073b 8500 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 8501 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 8502 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8503 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8504 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8505
AnnaBridge 143:86740a56073b 8506 /* Bit 12 : Set as input pin 12 */
AnnaBridge 143:86740a56073b 8507 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 8508 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 8509 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8510 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8511 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8512
AnnaBridge 143:86740a56073b 8513 /* Bit 11 : Set as input pin 11 */
AnnaBridge 143:86740a56073b 8514 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 8515 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 8516 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8517 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8518 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8519
AnnaBridge 143:86740a56073b 8520 /* Bit 10 : Set as input pin 10 */
AnnaBridge 143:86740a56073b 8521 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 8522 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 8523 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8524 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8525 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8526
AnnaBridge 143:86740a56073b 8527 /* Bit 9 : Set as input pin 9 */
AnnaBridge 143:86740a56073b 8528 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 8529 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 8530 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8531 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8532 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8533
AnnaBridge 143:86740a56073b 8534 /* Bit 8 : Set as input pin 8 */
AnnaBridge 143:86740a56073b 8535 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 8536 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 8537 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8538 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8539 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8540
AnnaBridge 143:86740a56073b 8541 /* Bit 7 : Set as input pin 7 */
AnnaBridge 143:86740a56073b 8542 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 8543 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 8544 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8545 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8546 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8547
AnnaBridge 143:86740a56073b 8548 /* Bit 6 : Set as input pin 6 */
AnnaBridge 143:86740a56073b 8549 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 8550 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 8551 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8552 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8553 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8554
AnnaBridge 143:86740a56073b 8555 /* Bit 5 : Set as input pin 5 */
AnnaBridge 143:86740a56073b 8556 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 8557 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 8558 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8559 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8560 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8561
AnnaBridge 143:86740a56073b 8562 /* Bit 4 : Set as input pin 4 */
AnnaBridge 143:86740a56073b 8563 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 8564 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 8565 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8566 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8567 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8568
AnnaBridge 143:86740a56073b 8569 /* Bit 3 : Set as input pin 3 */
AnnaBridge 143:86740a56073b 8570 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 8571 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 8572 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8573 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8574 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8575
AnnaBridge 143:86740a56073b 8576 /* Bit 2 : Set as input pin 2 */
AnnaBridge 143:86740a56073b 8577 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 8578 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 8579 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8580 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8581 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8582
AnnaBridge 143:86740a56073b 8583 /* Bit 1 : Set as input pin 1 */
AnnaBridge 143:86740a56073b 8584 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 8585 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 8586 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8587 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8588 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8589
AnnaBridge 143:86740a56073b 8590 /* Bit 0 : Set as input pin 0 */
AnnaBridge 143:86740a56073b 8591 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 8592 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 8593 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
AnnaBridge 143:86740a56073b 8594 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
AnnaBridge 143:86740a56073b 8595 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
AnnaBridge 143:86740a56073b 8596
AnnaBridge 143:86740a56073b 8597 /* Register: GPIO_LATCH */
AnnaBridge 143:86740a56073b 8598 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
AnnaBridge 143:86740a56073b 8599
AnnaBridge 143:86740a56073b 8600 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8601 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 8602 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 8603 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8604 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8605
AnnaBridge 143:86740a56073b 8606 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8607 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 8608 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 8609 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8610 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8611
AnnaBridge 143:86740a56073b 8612 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8613 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 8614 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 8615 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8616 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8617
AnnaBridge 143:86740a56073b 8618 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8619 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 8620 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 8621 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8622 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8623
AnnaBridge 143:86740a56073b 8624 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8625 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 8626 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 8627 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8628 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8629
AnnaBridge 143:86740a56073b 8630 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8631 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 8632 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 8633 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8634 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8635
AnnaBridge 143:86740a56073b 8636 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8637 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 8638 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 8639 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8640 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8641
AnnaBridge 143:86740a56073b 8642 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8643 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 8644 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 8645 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8646 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8647
AnnaBridge 143:86740a56073b 8648 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8649 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 8650 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 8651 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8652 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8653
AnnaBridge 143:86740a56073b 8654 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8655 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 8656 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 8657 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8658 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8659
AnnaBridge 143:86740a56073b 8660 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8661 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 8662 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 8663 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8664 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8665
AnnaBridge 143:86740a56073b 8666 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8667 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 8668 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 8669 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8670 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8671
AnnaBridge 143:86740a56073b 8672 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8673 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 8674 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 8675 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8676 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8677
AnnaBridge 143:86740a56073b 8678 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8679 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 8680 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 8681 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8682 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8683
AnnaBridge 143:86740a56073b 8684 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8685 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 8686 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 8687 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8688 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8689
AnnaBridge 143:86740a56073b 8690 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8691 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 8692 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 8693 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8694 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8695
AnnaBridge 143:86740a56073b 8696 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8697 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 8698 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 8699 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8700 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8701
AnnaBridge 143:86740a56073b 8702 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8703 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 8704 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 8705 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8706 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8707
AnnaBridge 143:86740a56073b 8708 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8709 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 8710 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 8711 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8712 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8713
AnnaBridge 143:86740a56073b 8714 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8715 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 8716 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 8717 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8718 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8719
AnnaBridge 143:86740a56073b 8720 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8721 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 8722 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 8723 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8724 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8725
AnnaBridge 143:86740a56073b 8726 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8727 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 8728 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 8729 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8730 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8731
AnnaBridge 143:86740a56073b 8732 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8733 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 8734 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 8735 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8736 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8737
AnnaBridge 143:86740a56073b 8738 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8739 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 8740 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 8741 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8742 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8743
AnnaBridge 143:86740a56073b 8744 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8745 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 8746 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 8747 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8748 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8749
AnnaBridge 143:86740a56073b 8750 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8751 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 8752 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 8753 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8754 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8755
AnnaBridge 143:86740a56073b 8756 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8757 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 8758 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 8759 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8760 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8761
AnnaBridge 143:86740a56073b 8762 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8763 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 8764 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 8765 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8766 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8767
AnnaBridge 143:86740a56073b 8768 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8769 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 8770 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 8771 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8772 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8773
AnnaBridge 143:86740a56073b 8774 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8775 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 8776 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 8777 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8778 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8779
AnnaBridge 143:86740a56073b 8780 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8781 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 8782 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 8783 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8784 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8785
AnnaBridge 143:86740a56073b 8786 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
AnnaBridge 143:86740a56073b 8787 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 8788 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 8789 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
AnnaBridge 143:86740a56073b 8790 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
AnnaBridge 143:86740a56073b 8791
AnnaBridge 143:86740a56073b 8792 /* Register: GPIO_DETECTMODE */
AnnaBridge 143:86740a56073b 8793 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
AnnaBridge 143:86740a56073b 8794
AnnaBridge 143:86740a56073b 8795 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
AnnaBridge 143:86740a56073b 8796 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
AnnaBridge 143:86740a56073b 8797 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
AnnaBridge 143:86740a56073b 8798 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
AnnaBridge 143:86740a56073b 8799 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
AnnaBridge 143:86740a56073b 8800
AnnaBridge 143:86740a56073b 8801 /* Register: GPIO_PIN_CNF */
AnnaBridge 143:86740a56073b 8802 /* Description: Description collection[0]: Configuration of GPIO pins */
AnnaBridge 143:86740a56073b 8803
AnnaBridge 143:86740a56073b 8804 /* Bits 17..16 : Pin sensing mechanism */
AnnaBridge 143:86740a56073b 8805 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
AnnaBridge 143:86740a56073b 8806 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
AnnaBridge 143:86740a56073b 8807 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 8808 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
AnnaBridge 143:86740a56073b 8809 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
AnnaBridge 143:86740a56073b 8810
AnnaBridge 143:86740a56073b 8811 /* Bits 10..8 : Drive configuration */
AnnaBridge 143:86740a56073b 8812 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
AnnaBridge 143:86740a56073b 8813 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
AnnaBridge 143:86740a56073b 8814 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
AnnaBridge 143:86740a56073b 8815 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
AnnaBridge 143:86740a56073b 8816 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
AnnaBridge 143:86740a56073b 8817 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
AnnaBridge 143:86740a56073b 8818 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
AnnaBridge 143:86740a56073b 8819 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
AnnaBridge 143:86740a56073b 8820 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
AnnaBridge 143:86740a56073b 8821 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
AnnaBridge 143:86740a56073b 8822
AnnaBridge 143:86740a56073b 8823 /* Bits 3..2 : Pull configuration */
AnnaBridge 143:86740a56073b 8824 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
AnnaBridge 143:86740a56073b 8825 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
AnnaBridge 143:86740a56073b 8826 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
AnnaBridge 143:86740a56073b 8827 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
AnnaBridge 143:86740a56073b 8828 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
AnnaBridge 143:86740a56073b 8829
AnnaBridge 143:86740a56073b 8830 /* Bit 1 : Connect or disconnect input buffer */
AnnaBridge 143:86740a56073b 8831 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
AnnaBridge 143:86740a56073b 8832 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
AnnaBridge 143:86740a56073b 8833 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
AnnaBridge 143:86740a56073b 8834 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
AnnaBridge 143:86740a56073b 8835
AnnaBridge 143:86740a56073b 8836 /* Bit 0 : Pin direction. Same physical register as DIR register */
AnnaBridge 143:86740a56073b 8837 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
AnnaBridge 143:86740a56073b 8838 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
AnnaBridge 143:86740a56073b 8839 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
AnnaBridge 143:86740a56073b 8840 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
AnnaBridge 143:86740a56073b 8841
AnnaBridge 143:86740a56073b 8842
AnnaBridge 143:86740a56073b 8843 /* Peripheral: PDM */
AnnaBridge 143:86740a56073b 8844 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
AnnaBridge 143:86740a56073b 8845
AnnaBridge 143:86740a56073b 8846 /* Register: PDM_INTEN */
AnnaBridge 143:86740a56073b 8847 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 8848
AnnaBridge 143:86740a56073b 8849 /* Bit 2 : Enable or disable interrupt for END event */
AnnaBridge 143:86740a56073b 8850 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 8851 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 8852 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 8853 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 8854
AnnaBridge 143:86740a56073b 8855 /* Bit 1 : Enable or disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 8856 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 8857 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 8858 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 8859 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 8860
AnnaBridge 143:86740a56073b 8861 /* Bit 0 : Enable or disable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 8862 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 8863 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 8864 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 8865 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 8866
AnnaBridge 143:86740a56073b 8867 /* Register: PDM_INTENSET */
AnnaBridge 143:86740a56073b 8868 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 8869
AnnaBridge 143:86740a56073b 8870 /* Bit 2 : Write '1' to Enable interrupt for END event */
AnnaBridge 143:86740a56073b 8871 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 8872 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 8873 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 8874 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 8875 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 8876
AnnaBridge 143:86740a56073b 8877 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 8878 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 8879 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 8880 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 8881 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 8882 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 8883
AnnaBridge 143:86740a56073b 8884 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 8885 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 8886 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 8887 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 8888 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 8889 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 8890
AnnaBridge 143:86740a56073b 8891 /* Register: PDM_INTENCLR */
AnnaBridge 143:86740a56073b 8892 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 8893
AnnaBridge 143:86740a56073b 8894 /* Bit 2 : Write '1' to Disable interrupt for END event */
AnnaBridge 143:86740a56073b 8895 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 8896 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 8897 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 8898 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 8899 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 8900
AnnaBridge 143:86740a56073b 8901 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 8902 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 8903 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 8904 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 8905 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 8906 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 8907
AnnaBridge 143:86740a56073b 8908 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 8909 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 8910 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 8911 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 8912 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 8913 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 8914
AnnaBridge 143:86740a56073b 8915 /* Register: PDM_ENABLE */
AnnaBridge 143:86740a56073b 8916 /* Description: PDM module enable register */
AnnaBridge 143:86740a56073b 8917
AnnaBridge 143:86740a56073b 8918 /* Bit 0 : Enable or disable PDM module */
AnnaBridge 143:86740a56073b 8919 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 8920 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 8921 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 8922 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 8923
AnnaBridge 143:86740a56073b 8924 /* Register: PDM_PDMCLKCTRL */
AnnaBridge 143:86740a56073b 8925 /* Description: PDM clock generator control */
AnnaBridge 143:86740a56073b 8926
AnnaBridge 143:86740a56073b 8927 /* Bits 31..0 : PDM_CLK frequency */
AnnaBridge 143:86740a56073b 8928 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
AnnaBridge 143:86740a56073b 8929 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
AnnaBridge 143:86740a56073b 8930 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
AnnaBridge 143:86740a56073b 8931 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
AnnaBridge 143:86740a56073b 8932 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
AnnaBridge 143:86740a56073b 8933
AnnaBridge 143:86740a56073b 8934 /* Register: PDM_MODE */
AnnaBridge 143:86740a56073b 8935 /* Description: Defines the routing of the connected PDM microphones' signals */
AnnaBridge 143:86740a56073b 8936
AnnaBridge 143:86740a56073b 8937 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
AnnaBridge 143:86740a56073b 8938 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
AnnaBridge 143:86740a56073b 8939 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
AnnaBridge 143:86740a56073b 8940 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
AnnaBridge 143:86740a56073b 8941 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
AnnaBridge 143:86740a56073b 8942
AnnaBridge 143:86740a56073b 8943 /* Bit 0 : Mono or stereo operation */
AnnaBridge 143:86740a56073b 8944 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
AnnaBridge 143:86740a56073b 8945 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
AnnaBridge 143:86740a56073b 8946 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
AnnaBridge 143:86740a56073b 8947 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
AnnaBridge 143:86740a56073b 8948
AnnaBridge 143:86740a56073b 8949 /* Register: PDM_GAINL */
AnnaBridge 143:86740a56073b 8950 /* Description: Left output gain adjustment */
AnnaBridge 143:86740a56073b 8951
AnnaBridge 143:86740a56073b 8952 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
AnnaBridge 143:86740a56073b 8953 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
AnnaBridge 143:86740a56073b 8954 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
AnnaBridge 143:86740a56073b 8955 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
AnnaBridge 143:86740a56073b 8956 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
AnnaBridge 143:86740a56073b 8957 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
AnnaBridge 143:86740a56073b 8958
AnnaBridge 143:86740a56073b 8959 /* Register: PDM_GAINR */
AnnaBridge 143:86740a56073b 8960 /* Description: Right output gain adjustment */
AnnaBridge 143:86740a56073b 8961
AnnaBridge 143:86740a56073b 8962 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
AnnaBridge 143:86740a56073b 8963 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
AnnaBridge 143:86740a56073b 8964 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
AnnaBridge 143:86740a56073b 8965 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
AnnaBridge 143:86740a56073b 8966 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
AnnaBridge 143:86740a56073b 8967 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
AnnaBridge 143:86740a56073b 8968
AnnaBridge 143:86740a56073b 8969 /* Register: PDM_PSEL_CLK */
AnnaBridge 143:86740a56073b 8970 /* Description: Pin number configuration for PDM CLK signal */
AnnaBridge 143:86740a56073b 8971
AnnaBridge 143:86740a56073b 8972 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 8973 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 8974 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 8975 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 8976 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 8977
AnnaBridge 143:86740a56073b 8978 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 8979 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 8980 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 8981
AnnaBridge 143:86740a56073b 8982 /* Register: PDM_PSEL_DIN */
AnnaBridge 143:86740a56073b 8983 /* Description: Pin number configuration for PDM DIN signal */
AnnaBridge 143:86740a56073b 8984
AnnaBridge 143:86740a56073b 8985 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 8986 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 8987 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 8988 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 8989 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 8990
AnnaBridge 143:86740a56073b 8991 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 8992 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 8993 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 8994
AnnaBridge 143:86740a56073b 8995 /* Register: PDM_SAMPLE_PTR */
AnnaBridge 143:86740a56073b 8996 /* Description: RAM address pointer to write samples to with EasyDMA */
AnnaBridge 143:86740a56073b 8997
AnnaBridge 143:86740a56073b 8998 /* Bits 31..0 : Address to write PDM samples to over DMA */
AnnaBridge 143:86740a56073b 8999 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
AnnaBridge 143:86740a56073b 9000 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
AnnaBridge 143:86740a56073b 9001
AnnaBridge 143:86740a56073b 9002 /* Register: PDM_SAMPLE_MAXCNT */
AnnaBridge 143:86740a56073b 9003 /* Description: Number of samples to allocate memory for in EasyDMA mode */
AnnaBridge 143:86740a56073b 9004
AnnaBridge 143:86740a56073b 9005 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
AnnaBridge 143:86740a56073b 9006 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
AnnaBridge 143:86740a56073b 9007 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
AnnaBridge 143:86740a56073b 9008
AnnaBridge 143:86740a56073b 9009
AnnaBridge 143:86740a56073b 9010 /* Peripheral: POWER */
AnnaBridge 143:86740a56073b 9011 /* Description: Power control */
AnnaBridge 143:86740a56073b 9012
AnnaBridge 143:86740a56073b 9013 /* Register: POWER_INTENSET */
AnnaBridge 143:86740a56073b 9014 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 9015
AnnaBridge 143:86740a56073b 9016 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
AnnaBridge 143:86740a56073b 9017 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
AnnaBridge 143:86740a56073b 9018 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
AnnaBridge 143:86740a56073b 9019 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 9020 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 9021 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 9022
AnnaBridge 143:86740a56073b 9023 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
AnnaBridge 143:86740a56073b 9024 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
AnnaBridge 143:86740a56073b 9025 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
AnnaBridge 143:86740a56073b 9026 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 9027 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 9028 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 9029
AnnaBridge 143:86740a56073b 9030 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
AnnaBridge 143:86740a56073b 9031 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
AnnaBridge 143:86740a56073b 9032 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
AnnaBridge 143:86740a56073b 9033 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 9034 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 9035 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 9036
AnnaBridge 143:86740a56073b 9037 /* Register: POWER_INTENCLR */
AnnaBridge 143:86740a56073b 9038 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 9039
AnnaBridge 143:86740a56073b 9040 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
AnnaBridge 143:86740a56073b 9041 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
AnnaBridge 143:86740a56073b 9042 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
AnnaBridge 143:86740a56073b 9043 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 9044 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 9045 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 9046
AnnaBridge 143:86740a56073b 9047 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
AnnaBridge 143:86740a56073b 9048 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
AnnaBridge 143:86740a56073b 9049 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
AnnaBridge 143:86740a56073b 9050 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 9051 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 9052 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 9053
AnnaBridge 143:86740a56073b 9054 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
AnnaBridge 143:86740a56073b 9055 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
AnnaBridge 143:86740a56073b 9056 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
AnnaBridge 143:86740a56073b 9057 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 9058 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 9059 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 9060
AnnaBridge 143:86740a56073b 9061 /* Register: POWER_RESETREAS */
AnnaBridge 143:86740a56073b 9062 /* Description: Reset reason */
AnnaBridge 143:86740a56073b 9063
AnnaBridge 143:86740a56073b 9064 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
AnnaBridge 143:86740a56073b 9065 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
AnnaBridge 143:86740a56073b 9066 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
AnnaBridge 143:86740a56073b 9067 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9068 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9069
AnnaBridge 143:86740a56073b 9070 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
AnnaBridge 143:86740a56073b 9071 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
AnnaBridge 143:86740a56073b 9072 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
AnnaBridge 143:86740a56073b 9073 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9074 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9075
AnnaBridge 143:86740a56073b 9076 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
AnnaBridge 143:86740a56073b 9077 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
AnnaBridge 143:86740a56073b 9078 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
AnnaBridge 143:86740a56073b 9079 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9080 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9081
AnnaBridge 143:86740a56073b 9082 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
AnnaBridge 143:86740a56073b 9083 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
AnnaBridge 143:86740a56073b 9084 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
AnnaBridge 143:86740a56073b 9085 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9086 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9087
AnnaBridge 143:86740a56073b 9088 /* Bit 3 : Reset from CPU lock-up detected */
AnnaBridge 143:86740a56073b 9089 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
AnnaBridge 143:86740a56073b 9090 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
AnnaBridge 143:86740a56073b 9091 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9092 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9093
AnnaBridge 143:86740a56073b 9094 /* Bit 2 : Reset from soft reset detected */
AnnaBridge 143:86740a56073b 9095 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
AnnaBridge 143:86740a56073b 9096 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
AnnaBridge 143:86740a56073b 9097 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9098 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9099
AnnaBridge 143:86740a56073b 9100 /* Bit 1 : Reset from watchdog detected */
AnnaBridge 143:86740a56073b 9101 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
AnnaBridge 143:86740a56073b 9102 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
AnnaBridge 143:86740a56073b 9103 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9104 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9105
AnnaBridge 143:86740a56073b 9106 /* Bit 0 : Reset from pin-reset detected */
AnnaBridge 143:86740a56073b 9107 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
AnnaBridge 143:86740a56073b 9108 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
AnnaBridge 143:86740a56073b 9109 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
AnnaBridge 143:86740a56073b 9110 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
AnnaBridge 143:86740a56073b 9111
AnnaBridge 143:86740a56073b 9112 /* Register: POWER_RAMSTATUS */
AnnaBridge 143:86740a56073b 9113 /* Description: Deprecated register - RAM status register */
AnnaBridge 143:86740a56073b 9114
AnnaBridge 143:86740a56073b 9115 /* Bit 3 : RAM block 3 is on or off/powering up */
AnnaBridge 143:86740a56073b 9116 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
AnnaBridge 143:86740a56073b 9117 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
AnnaBridge 143:86740a56073b 9118 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9119 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9120
AnnaBridge 143:86740a56073b 9121 /* Bit 2 : RAM block 2 is on or off/powering up */
AnnaBridge 143:86740a56073b 9122 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
AnnaBridge 143:86740a56073b 9123 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
AnnaBridge 143:86740a56073b 9124 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9125 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9126
AnnaBridge 143:86740a56073b 9127 /* Bit 1 : RAM block 1 is on or off/powering up */
AnnaBridge 143:86740a56073b 9128 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
AnnaBridge 143:86740a56073b 9129 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
AnnaBridge 143:86740a56073b 9130 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9131 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9132
AnnaBridge 143:86740a56073b 9133 /* Bit 0 : RAM block 0 is on or off/powering up */
AnnaBridge 143:86740a56073b 9134 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
AnnaBridge 143:86740a56073b 9135 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
AnnaBridge 143:86740a56073b 9136 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9137 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9138
AnnaBridge 143:86740a56073b 9139 /* Register: POWER_SYSTEMOFF */
AnnaBridge 143:86740a56073b 9140 /* Description: System OFF register */
AnnaBridge 143:86740a56073b 9141
AnnaBridge 143:86740a56073b 9142 /* Bit 0 : Enable System OFF mode */
AnnaBridge 143:86740a56073b 9143 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
AnnaBridge 143:86740a56073b 9144 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
AnnaBridge 143:86740a56073b 9145 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
AnnaBridge 143:86740a56073b 9146
AnnaBridge 143:86740a56073b 9147 /* Register: POWER_POFCON */
AnnaBridge 143:86740a56073b 9148 /* Description: Power failure comparator configuration */
AnnaBridge 143:86740a56073b 9149
AnnaBridge 143:86740a56073b 9150 /* Bits 4..1 : Power failure comparator threshold setting */
AnnaBridge 143:86740a56073b 9151 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
AnnaBridge 143:86740a56073b 9152 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
AnnaBridge 143:86740a56073b 9153 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
AnnaBridge 143:86740a56073b 9154 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
AnnaBridge 143:86740a56073b 9155 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
AnnaBridge 143:86740a56073b 9156 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
AnnaBridge 143:86740a56073b 9157 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
AnnaBridge 143:86740a56073b 9158 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
AnnaBridge 143:86740a56073b 9159 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
AnnaBridge 143:86740a56073b 9160 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
AnnaBridge 143:86740a56073b 9161 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
AnnaBridge 143:86740a56073b 9162 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
AnnaBridge 143:86740a56073b 9163 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
AnnaBridge 143:86740a56073b 9164 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
AnnaBridge 143:86740a56073b 9165
AnnaBridge 143:86740a56073b 9166 /* Bit 0 : Enable or disable power failure comparator */
AnnaBridge 143:86740a56073b 9167 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
AnnaBridge 143:86740a56073b 9168 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
AnnaBridge 143:86740a56073b 9169 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 9170 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 9171
AnnaBridge 143:86740a56073b 9172 /* Register: POWER_GPREGRET */
AnnaBridge 143:86740a56073b 9173 /* Description: General purpose retention register */
AnnaBridge 143:86740a56073b 9174
AnnaBridge 143:86740a56073b 9175 /* Bits 7..0 : General purpose retention register */
AnnaBridge 143:86740a56073b 9176 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
AnnaBridge 143:86740a56073b 9177 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
AnnaBridge 143:86740a56073b 9178
AnnaBridge 143:86740a56073b 9179 /* Register: POWER_GPREGRET2 */
AnnaBridge 143:86740a56073b 9180 /* Description: General purpose retention register */
AnnaBridge 143:86740a56073b 9181
AnnaBridge 143:86740a56073b 9182 /* Bits 7..0 : General purpose retention register */
AnnaBridge 143:86740a56073b 9183 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
AnnaBridge 143:86740a56073b 9184 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
AnnaBridge 143:86740a56073b 9185
AnnaBridge 143:86740a56073b 9186 /* Register: POWER_RAMON */
AnnaBridge 143:86740a56073b 9187 /* Description: Deprecated register - RAM on/off register (this register is retained) */
AnnaBridge 143:86740a56073b 9188
AnnaBridge 143:86740a56073b 9189 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
AnnaBridge 143:86740a56073b 9190 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
AnnaBridge 143:86740a56073b 9191 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
AnnaBridge 143:86740a56073b 9192 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9193 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9194
AnnaBridge 143:86740a56073b 9195 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
AnnaBridge 143:86740a56073b 9196 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
AnnaBridge 143:86740a56073b 9197 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
AnnaBridge 143:86740a56073b 9198 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9199 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9200
AnnaBridge 143:86740a56073b 9201 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
AnnaBridge 143:86740a56073b 9202 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
AnnaBridge 143:86740a56073b 9203 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
AnnaBridge 143:86740a56073b 9204 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9205 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9206
AnnaBridge 143:86740a56073b 9207 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
AnnaBridge 143:86740a56073b 9208 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
AnnaBridge 143:86740a56073b 9209 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
AnnaBridge 143:86740a56073b 9210 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9211 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9212
AnnaBridge 143:86740a56073b 9213 /* Register: POWER_RAMONB */
AnnaBridge 143:86740a56073b 9214 /* Description: Deprecated register - RAM on/off register (this register is retained) */
AnnaBridge 143:86740a56073b 9215
AnnaBridge 143:86740a56073b 9216 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
AnnaBridge 143:86740a56073b 9217 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
AnnaBridge 143:86740a56073b 9218 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
AnnaBridge 143:86740a56073b 9219 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9220 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9221
AnnaBridge 143:86740a56073b 9222 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
AnnaBridge 143:86740a56073b 9223 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
AnnaBridge 143:86740a56073b 9224 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
AnnaBridge 143:86740a56073b 9225 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9226 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9227
AnnaBridge 143:86740a56073b 9228 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
AnnaBridge 143:86740a56073b 9229 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
AnnaBridge 143:86740a56073b 9230 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
AnnaBridge 143:86740a56073b 9231 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9232 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9233
AnnaBridge 143:86740a56073b 9234 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
AnnaBridge 143:86740a56073b 9235 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
AnnaBridge 143:86740a56073b 9236 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
AnnaBridge 143:86740a56073b 9237 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9238 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9239
AnnaBridge 143:86740a56073b 9240 /* Register: POWER_DCDCEN */
AnnaBridge 143:86740a56073b 9241 /* Description: DC/DC enable register */
AnnaBridge 143:86740a56073b 9242
AnnaBridge 143:86740a56073b 9243 /* Bit 0 : Enable or disable DC/DC converter */
AnnaBridge 143:86740a56073b 9244 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
AnnaBridge 143:86740a56073b 9245 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
AnnaBridge 143:86740a56073b 9246 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 9247 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 9248
AnnaBridge 143:86740a56073b 9249 /* Register: POWER_RAM_POWER */
AnnaBridge 143:86740a56073b 9250 /* Description: Description cluster[0]: RAM0 power control register */
AnnaBridge 143:86740a56073b 9251
AnnaBridge 143:86740a56073b 9252 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
AnnaBridge 143:86740a56073b 9253 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
AnnaBridge 143:86740a56073b 9254 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
AnnaBridge 143:86740a56073b 9255 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9256 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9257
AnnaBridge 143:86740a56073b 9258 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
AnnaBridge 143:86740a56073b 9259 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
AnnaBridge 143:86740a56073b 9260 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
AnnaBridge 143:86740a56073b 9261 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9262 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9263
AnnaBridge 143:86740a56073b 9264 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
AnnaBridge 143:86740a56073b 9265 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
AnnaBridge 143:86740a56073b 9266 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
AnnaBridge 143:86740a56073b 9267 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9268 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9269
AnnaBridge 143:86740a56073b 9270 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
AnnaBridge 143:86740a56073b 9271 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
AnnaBridge 143:86740a56073b 9272 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
AnnaBridge 143:86740a56073b 9273 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
AnnaBridge 143:86740a56073b 9274 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9275
AnnaBridge 143:86740a56073b 9276 /* Register: POWER_RAM_POWERSET */
AnnaBridge 143:86740a56073b 9277 /* Description: Description cluster[0]: RAM0 power control set register */
AnnaBridge 143:86740a56073b 9278
AnnaBridge 143:86740a56073b 9279 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
AnnaBridge 143:86740a56073b 9280 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
AnnaBridge 143:86740a56073b 9281 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
AnnaBridge 143:86740a56073b 9282 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9283
AnnaBridge 143:86740a56073b 9284 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
AnnaBridge 143:86740a56073b 9285 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
AnnaBridge 143:86740a56073b 9286 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
AnnaBridge 143:86740a56073b 9287 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9288
AnnaBridge 143:86740a56073b 9289 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
AnnaBridge 143:86740a56073b 9290 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
AnnaBridge 143:86740a56073b 9291 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
AnnaBridge 143:86740a56073b 9292 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9293
AnnaBridge 143:86740a56073b 9294 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
AnnaBridge 143:86740a56073b 9295 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
AnnaBridge 143:86740a56073b 9296 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
AnnaBridge 143:86740a56073b 9297 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
AnnaBridge 143:86740a56073b 9298
AnnaBridge 143:86740a56073b 9299 /* Register: POWER_RAM_POWERCLR */
AnnaBridge 143:86740a56073b 9300 /* Description: Description cluster[0]: RAM0 power control clear register */
AnnaBridge 143:86740a56073b 9301
AnnaBridge 143:86740a56073b 9302 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
AnnaBridge 143:86740a56073b 9303 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
AnnaBridge 143:86740a56073b 9304 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
AnnaBridge 143:86740a56073b 9305 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
AnnaBridge 143:86740a56073b 9306
AnnaBridge 143:86740a56073b 9307 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
AnnaBridge 143:86740a56073b 9308 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
AnnaBridge 143:86740a56073b 9309 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
AnnaBridge 143:86740a56073b 9310 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
AnnaBridge 143:86740a56073b 9311
AnnaBridge 143:86740a56073b 9312 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
AnnaBridge 143:86740a56073b 9313 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
AnnaBridge 143:86740a56073b 9314 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
AnnaBridge 143:86740a56073b 9315 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
AnnaBridge 143:86740a56073b 9316
AnnaBridge 143:86740a56073b 9317 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
AnnaBridge 143:86740a56073b 9318 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
AnnaBridge 143:86740a56073b 9319 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
AnnaBridge 143:86740a56073b 9320 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
AnnaBridge 143:86740a56073b 9321
AnnaBridge 143:86740a56073b 9322
AnnaBridge 143:86740a56073b 9323 /* Peripheral: PPI */
AnnaBridge 143:86740a56073b 9324 /* Description: Programmable Peripheral Interconnect */
AnnaBridge 143:86740a56073b 9325
AnnaBridge 143:86740a56073b 9326 /* Register: PPI_CHEN */
AnnaBridge 143:86740a56073b 9327 /* Description: Channel enable register */
AnnaBridge 143:86740a56073b 9328
AnnaBridge 143:86740a56073b 9329 /* Bit 31 : Enable or disable channel 31 */
AnnaBridge 143:86740a56073b 9330 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 9331 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 9332 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9333 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9334
AnnaBridge 143:86740a56073b 9335 /* Bit 30 : Enable or disable channel 30 */
AnnaBridge 143:86740a56073b 9336 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 9337 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 9338 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9339 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9340
AnnaBridge 143:86740a56073b 9341 /* Bit 29 : Enable or disable channel 29 */
AnnaBridge 143:86740a56073b 9342 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 9343 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 9344 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9345 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9346
AnnaBridge 143:86740a56073b 9347 /* Bit 28 : Enable or disable channel 28 */
AnnaBridge 143:86740a56073b 9348 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 9349 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 9350 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9351 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9352
AnnaBridge 143:86740a56073b 9353 /* Bit 27 : Enable or disable channel 27 */
AnnaBridge 143:86740a56073b 9354 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 9355 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 9356 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9357 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9358
AnnaBridge 143:86740a56073b 9359 /* Bit 26 : Enable or disable channel 26 */
AnnaBridge 143:86740a56073b 9360 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 9361 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 9362 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9363 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9364
AnnaBridge 143:86740a56073b 9365 /* Bit 25 : Enable or disable channel 25 */
AnnaBridge 143:86740a56073b 9366 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 9367 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 9368 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9369 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9370
AnnaBridge 143:86740a56073b 9371 /* Bit 24 : Enable or disable channel 24 */
AnnaBridge 143:86740a56073b 9372 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 9373 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 9374 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9375 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9376
AnnaBridge 143:86740a56073b 9377 /* Bit 23 : Enable or disable channel 23 */
AnnaBridge 143:86740a56073b 9378 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 9379 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 9380 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9381 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9382
AnnaBridge 143:86740a56073b 9383 /* Bit 22 : Enable or disable channel 22 */
AnnaBridge 143:86740a56073b 9384 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 9385 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 9386 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9387 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9388
AnnaBridge 143:86740a56073b 9389 /* Bit 21 : Enable or disable channel 21 */
AnnaBridge 143:86740a56073b 9390 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 9391 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 9392 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9393 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9394
AnnaBridge 143:86740a56073b 9395 /* Bit 20 : Enable or disable channel 20 */
AnnaBridge 143:86740a56073b 9396 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 9397 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 9398 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9399 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9400
AnnaBridge 143:86740a56073b 9401 /* Bit 19 : Enable or disable channel 19 */
AnnaBridge 143:86740a56073b 9402 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
AnnaBridge 143:86740a56073b 9403 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
AnnaBridge 143:86740a56073b 9404 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9405 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9406
AnnaBridge 143:86740a56073b 9407 /* Bit 18 : Enable or disable channel 18 */
AnnaBridge 143:86740a56073b 9408 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
AnnaBridge 143:86740a56073b 9409 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
AnnaBridge 143:86740a56073b 9410 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9411 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9412
AnnaBridge 143:86740a56073b 9413 /* Bit 17 : Enable or disable channel 17 */
AnnaBridge 143:86740a56073b 9414 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
AnnaBridge 143:86740a56073b 9415 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
AnnaBridge 143:86740a56073b 9416 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9417 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9418
AnnaBridge 143:86740a56073b 9419 /* Bit 16 : Enable or disable channel 16 */
AnnaBridge 143:86740a56073b 9420 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
AnnaBridge 143:86740a56073b 9421 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
AnnaBridge 143:86740a56073b 9422 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9423 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9424
AnnaBridge 143:86740a56073b 9425 /* Bit 15 : Enable or disable channel 15 */
AnnaBridge 143:86740a56073b 9426 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 9427 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 9428 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9429 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9430
AnnaBridge 143:86740a56073b 9431 /* Bit 14 : Enable or disable channel 14 */
AnnaBridge 143:86740a56073b 9432 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 9433 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 9434 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9435 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9436
AnnaBridge 143:86740a56073b 9437 /* Bit 13 : Enable or disable channel 13 */
AnnaBridge 143:86740a56073b 9438 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 9439 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 9440 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9441 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9442
AnnaBridge 143:86740a56073b 9443 /* Bit 12 : Enable or disable channel 12 */
AnnaBridge 143:86740a56073b 9444 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 9445 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 9446 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9447 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9448
AnnaBridge 143:86740a56073b 9449 /* Bit 11 : Enable or disable channel 11 */
AnnaBridge 143:86740a56073b 9450 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 9451 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 9452 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9453 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9454
AnnaBridge 143:86740a56073b 9455 /* Bit 10 : Enable or disable channel 10 */
AnnaBridge 143:86740a56073b 9456 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 9457 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 9458 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9459 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9460
AnnaBridge 143:86740a56073b 9461 /* Bit 9 : Enable or disable channel 9 */
AnnaBridge 143:86740a56073b 9462 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 9463 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 9464 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9465 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9466
AnnaBridge 143:86740a56073b 9467 /* Bit 8 : Enable or disable channel 8 */
AnnaBridge 143:86740a56073b 9468 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 9469 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 9470 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9471 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9472
AnnaBridge 143:86740a56073b 9473 /* Bit 7 : Enable or disable channel 7 */
AnnaBridge 143:86740a56073b 9474 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 9475 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 9476 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9477 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9478
AnnaBridge 143:86740a56073b 9479 /* Bit 6 : Enable or disable channel 6 */
AnnaBridge 143:86740a56073b 9480 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 9481 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 9482 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9483 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9484
AnnaBridge 143:86740a56073b 9485 /* Bit 5 : Enable or disable channel 5 */
AnnaBridge 143:86740a56073b 9486 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 9487 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 9488 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9489 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9490
AnnaBridge 143:86740a56073b 9491 /* Bit 4 : Enable or disable channel 4 */
AnnaBridge 143:86740a56073b 9492 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 9493 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 9494 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9495 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9496
AnnaBridge 143:86740a56073b 9497 /* Bit 3 : Enable or disable channel 3 */
AnnaBridge 143:86740a56073b 9498 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 9499 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 9500 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9501 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9502
AnnaBridge 143:86740a56073b 9503 /* Bit 2 : Enable or disable channel 2 */
AnnaBridge 143:86740a56073b 9504 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 9505 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 9506 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9507 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9508
AnnaBridge 143:86740a56073b 9509 /* Bit 1 : Enable or disable channel 1 */
AnnaBridge 143:86740a56073b 9510 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 9511 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 9512 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9513 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9514
AnnaBridge 143:86740a56073b 9515 /* Bit 0 : Enable or disable channel 0 */
AnnaBridge 143:86740a56073b 9516 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 9517 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 9518 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
AnnaBridge 143:86740a56073b 9519 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
AnnaBridge 143:86740a56073b 9520
AnnaBridge 143:86740a56073b 9521 /* Register: PPI_CHENSET */
AnnaBridge 143:86740a56073b 9522 /* Description: Channel enable set register */
AnnaBridge 143:86740a56073b 9523
AnnaBridge 143:86740a56073b 9524 /* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9525 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 9526 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 9527 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9528 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9529 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9530
AnnaBridge 143:86740a56073b 9531 /* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9532 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 9533 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 9534 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9535 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9536 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9537
AnnaBridge 143:86740a56073b 9538 /* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9539 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 9540 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 9541 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9542 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9543 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9544
AnnaBridge 143:86740a56073b 9545 /* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9546 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 9547 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 9548 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9549 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9550 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9551
AnnaBridge 143:86740a56073b 9552 /* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9553 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 9554 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 9555 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9556 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9557 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9558
AnnaBridge 143:86740a56073b 9559 /* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9560 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 9561 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 9562 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9563 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9564 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9565
AnnaBridge 143:86740a56073b 9566 /* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9567 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 9568 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 9569 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9570 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9571 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9572
AnnaBridge 143:86740a56073b 9573 /* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9574 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 9575 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 9576 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9577 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9578 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9579
AnnaBridge 143:86740a56073b 9580 /* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9581 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 9582 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 9583 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9584 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9585 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9586
AnnaBridge 143:86740a56073b 9587 /* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9588 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 9589 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 9590 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9591 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9592 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9593
AnnaBridge 143:86740a56073b 9594 /* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9595 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 9596 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 9597 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9598 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9599 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9600
AnnaBridge 143:86740a56073b 9601 /* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9602 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 9603 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 9604 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9605 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9606 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9607
AnnaBridge 143:86740a56073b 9608 /* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9609 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
AnnaBridge 143:86740a56073b 9610 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
AnnaBridge 143:86740a56073b 9611 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9612 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9613 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9614
AnnaBridge 143:86740a56073b 9615 /* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9616 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
AnnaBridge 143:86740a56073b 9617 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
AnnaBridge 143:86740a56073b 9618 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9619 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9620 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9621
AnnaBridge 143:86740a56073b 9622 /* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9623 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
AnnaBridge 143:86740a56073b 9624 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
AnnaBridge 143:86740a56073b 9625 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9626 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9627 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9628
AnnaBridge 143:86740a56073b 9629 /* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9630 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
AnnaBridge 143:86740a56073b 9631 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
AnnaBridge 143:86740a56073b 9632 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9633 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9634 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9635
AnnaBridge 143:86740a56073b 9636 /* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9637 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 9638 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 9639 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9640 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9641 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9642
AnnaBridge 143:86740a56073b 9643 /* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9644 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 9645 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 9646 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9647 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9648 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9649
AnnaBridge 143:86740a56073b 9650 /* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9651 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 9652 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 9653 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9654 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9655 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9656
AnnaBridge 143:86740a56073b 9657 /* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9658 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 9659 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 9660 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9661 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9662 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9663
AnnaBridge 143:86740a56073b 9664 /* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9665 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 9666 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 9667 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9668 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9669 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9670
AnnaBridge 143:86740a56073b 9671 /* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9672 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 9673 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 9674 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9675 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9676 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9677
AnnaBridge 143:86740a56073b 9678 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9679 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 9680 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 9681 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9682 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9683 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9684
AnnaBridge 143:86740a56073b 9685 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9686 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 9687 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 9688 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9689 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9690 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9691
AnnaBridge 143:86740a56073b 9692 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9693 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 9694 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 9695 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9696 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9697 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9698
AnnaBridge 143:86740a56073b 9699 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9700 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 9701 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 9702 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9703 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9704 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9705
AnnaBridge 143:86740a56073b 9706 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9707 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 9708 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 9709 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9710 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9711 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9712
AnnaBridge 143:86740a56073b 9713 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9714 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 9715 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 9716 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9717 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9718 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9719
AnnaBridge 143:86740a56073b 9720 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9721 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 9722 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 9723 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9724 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9725 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9726
AnnaBridge 143:86740a56073b 9727 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9728 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 9729 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 9730 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9731 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9732 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9733
AnnaBridge 143:86740a56073b 9734 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9735 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 9736 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 9737 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9738 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9739 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9740
AnnaBridge 143:86740a56073b 9741 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9742 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 9743 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 9744 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9745 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9746 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
AnnaBridge 143:86740a56073b 9747
AnnaBridge 143:86740a56073b 9748 /* Register: PPI_CHENCLR */
AnnaBridge 143:86740a56073b 9749 /* Description: Channel enable clear register */
AnnaBridge 143:86740a56073b 9750
AnnaBridge 143:86740a56073b 9751 /* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9752 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 9753 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 9754 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9755 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9756 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9757
AnnaBridge 143:86740a56073b 9758 /* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9759 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 9760 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 9761 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9762 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9763 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9764
AnnaBridge 143:86740a56073b 9765 /* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9766 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 9767 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 9768 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9769 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9770 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9771
AnnaBridge 143:86740a56073b 9772 /* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9773 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 9774 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 9775 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9776 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9777 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9778
AnnaBridge 143:86740a56073b 9779 /* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9780 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 9781 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 9782 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9783 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9784 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9785
AnnaBridge 143:86740a56073b 9786 /* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9787 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 9788 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 9789 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9790 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9791 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9792
AnnaBridge 143:86740a56073b 9793 /* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9794 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 9795 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 9796 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9797 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9798 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9799
AnnaBridge 143:86740a56073b 9800 /* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9801 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 9802 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 9803 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9804 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9805 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9806
AnnaBridge 143:86740a56073b 9807 /* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9808 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 9809 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 9810 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9811 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9812 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9813
AnnaBridge 143:86740a56073b 9814 /* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9815 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 9816 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 9817 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9818 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9819 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9820
AnnaBridge 143:86740a56073b 9821 /* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9822 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 9823 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 9824 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9825 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9826 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9827
AnnaBridge 143:86740a56073b 9828 /* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9829 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 9830 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 9831 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9832 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9833 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9834
AnnaBridge 143:86740a56073b 9835 /* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9836 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
AnnaBridge 143:86740a56073b 9837 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
AnnaBridge 143:86740a56073b 9838 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9839 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9840 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9841
AnnaBridge 143:86740a56073b 9842 /* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9843 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
AnnaBridge 143:86740a56073b 9844 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
AnnaBridge 143:86740a56073b 9845 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9846 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9847 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9848
AnnaBridge 143:86740a56073b 9849 /* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9850 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
AnnaBridge 143:86740a56073b 9851 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
AnnaBridge 143:86740a56073b 9852 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9853 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9854 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9855
AnnaBridge 143:86740a56073b 9856 /* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9857 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
AnnaBridge 143:86740a56073b 9858 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
AnnaBridge 143:86740a56073b 9859 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9860 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9861 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9862
AnnaBridge 143:86740a56073b 9863 /* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9864 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 9865 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 9866 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9867 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9868 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9869
AnnaBridge 143:86740a56073b 9870 /* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9871 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 9872 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 9873 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9874 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9875 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9876
AnnaBridge 143:86740a56073b 9877 /* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9878 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 9879 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 9880 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9881 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9882 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9883
AnnaBridge 143:86740a56073b 9884 /* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9885 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 9886 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 9887 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9888 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9889 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9890
AnnaBridge 143:86740a56073b 9891 /* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9892 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 9893 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 9894 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9895 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9896 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9897
AnnaBridge 143:86740a56073b 9898 /* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9899 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 9900 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 9901 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9902 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9903 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9904
AnnaBridge 143:86740a56073b 9905 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9906 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 9907 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 9908 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9909 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9910 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9911
AnnaBridge 143:86740a56073b 9912 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9913 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 9914 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 9915 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9916 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9917 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9918
AnnaBridge 143:86740a56073b 9919 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9920 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 9921 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 9922 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9923 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9924 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9925
AnnaBridge 143:86740a56073b 9926 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9927 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 9928 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 9929 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9930 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9931 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9932
AnnaBridge 143:86740a56073b 9933 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9934 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 9935 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 9936 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9937 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9938 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9939
AnnaBridge 143:86740a56073b 9940 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9941 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 9942 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 9943 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9944 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9945 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9946
AnnaBridge 143:86740a56073b 9947 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9948 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 9949 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 9950 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9951 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9952 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9953
AnnaBridge 143:86740a56073b 9954 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9955 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 9956 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 9957 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9958 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9959 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9960
AnnaBridge 143:86740a56073b 9961 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9962 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 9963 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 9964 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9965 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9966 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9967
AnnaBridge 143:86740a56073b 9968 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
AnnaBridge 143:86740a56073b 9969 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 9970 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 9971 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
AnnaBridge 143:86740a56073b 9972 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
AnnaBridge 143:86740a56073b 9973 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
AnnaBridge 143:86740a56073b 9974
AnnaBridge 143:86740a56073b 9975 /* Register: PPI_CH_EEP */
AnnaBridge 143:86740a56073b 9976 /* Description: Description cluster[0]: Channel 0 event end-point */
AnnaBridge 143:86740a56073b 9977
AnnaBridge 143:86740a56073b 9978 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
AnnaBridge 143:86740a56073b 9979 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
AnnaBridge 143:86740a56073b 9980 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
AnnaBridge 143:86740a56073b 9981
AnnaBridge 143:86740a56073b 9982 /* Register: PPI_CH_TEP */
AnnaBridge 143:86740a56073b 9983 /* Description: Description cluster[0]: Channel 0 task end-point */
AnnaBridge 143:86740a56073b 9984
AnnaBridge 143:86740a56073b 9985 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
AnnaBridge 143:86740a56073b 9986 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
AnnaBridge 143:86740a56073b 9987 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
AnnaBridge 143:86740a56073b 9988
AnnaBridge 143:86740a56073b 9989 /* Register: PPI_CHG */
AnnaBridge 143:86740a56073b 9990 /* Description: Description collection[0]: Channel group 0 */
AnnaBridge 143:86740a56073b 9991
AnnaBridge 143:86740a56073b 9992 /* Bit 31 : Include or exclude channel 31 */
AnnaBridge 143:86740a56073b 9993 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 9994 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 9995 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 9996 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 9997
AnnaBridge 143:86740a56073b 9998 /* Bit 30 : Include or exclude channel 30 */
AnnaBridge 143:86740a56073b 9999 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 10000 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 10001 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10002 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10003
AnnaBridge 143:86740a56073b 10004 /* Bit 29 : Include or exclude channel 29 */
AnnaBridge 143:86740a56073b 10005 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 10006 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 10007 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10008 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10009
AnnaBridge 143:86740a56073b 10010 /* Bit 28 : Include or exclude channel 28 */
AnnaBridge 143:86740a56073b 10011 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 10012 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 10013 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10014 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10015
AnnaBridge 143:86740a56073b 10016 /* Bit 27 : Include or exclude channel 27 */
AnnaBridge 143:86740a56073b 10017 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 10018 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 10019 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10020 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10021
AnnaBridge 143:86740a56073b 10022 /* Bit 26 : Include or exclude channel 26 */
AnnaBridge 143:86740a56073b 10023 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 10024 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 10025 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10026 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10027
AnnaBridge 143:86740a56073b 10028 /* Bit 25 : Include or exclude channel 25 */
AnnaBridge 143:86740a56073b 10029 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 10030 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 10031 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10032 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10033
AnnaBridge 143:86740a56073b 10034 /* Bit 24 : Include or exclude channel 24 */
AnnaBridge 143:86740a56073b 10035 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 10036 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 10037 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10038 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10039
AnnaBridge 143:86740a56073b 10040 /* Bit 23 : Include or exclude channel 23 */
AnnaBridge 143:86740a56073b 10041 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 10042 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 10043 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10044 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10045
AnnaBridge 143:86740a56073b 10046 /* Bit 22 : Include or exclude channel 22 */
AnnaBridge 143:86740a56073b 10047 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 10048 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 10049 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10050 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10051
AnnaBridge 143:86740a56073b 10052 /* Bit 21 : Include or exclude channel 21 */
AnnaBridge 143:86740a56073b 10053 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 10054 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 10055 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10056 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10057
AnnaBridge 143:86740a56073b 10058 /* Bit 20 : Include or exclude channel 20 */
AnnaBridge 143:86740a56073b 10059 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 10060 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 10061 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10062 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10063
AnnaBridge 143:86740a56073b 10064 /* Bit 19 : Include or exclude channel 19 */
AnnaBridge 143:86740a56073b 10065 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
AnnaBridge 143:86740a56073b 10066 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
AnnaBridge 143:86740a56073b 10067 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10068 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10069
AnnaBridge 143:86740a56073b 10070 /* Bit 18 : Include or exclude channel 18 */
AnnaBridge 143:86740a56073b 10071 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
AnnaBridge 143:86740a56073b 10072 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
AnnaBridge 143:86740a56073b 10073 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10074 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10075
AnnaBridge 143:86740a56073b 10076 /* Bit 17 : Include or exclude channel 17 */
AnnaBridge 143:86740a56073b 10077 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
AnnaBridge 143:86740a56073b 10078 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
AnnaBridge 143:86740a56073b 10079 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10080 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10081
AnnaBridge 143:86740a56073b 10082 /* Bit 16 : Include or exclude channel 16 */
AnnaBridge 143:86740a56073b 10083 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
AnnaBridge 143:86740a56073b 10084 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
AnnaBridge 143:86740a56073b 10085 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10086 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10087
AnnaBridge 143:86740a56073b 10088 /* Bit 15 : Include or exclude channel 15 */
AnnaBridge 143:86740a56073b 10089 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 10090 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 10091 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10092 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10093
AnnaBridge 143:86740a56073b 10094 /* Bit 14 : Include or exclude channel 14 */
AnnaBridge 143:86740a56073b 10095 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 10096 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 10097 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10098 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10099
AnnaBridge 143:86740a56073b 10100 /* Bit 13 : Include or exclude channel 13 */
AnnaBridge 143:86740a56073b 10101 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 10102 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 10103 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10104 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10105
AnnaBridge 143:86740a56073b 10106 /* Bit 12 : Include or exclude channel 12 */
AnnaBridge 143:86740a56073b 10107 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 10108 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 10109 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10110 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10111
AnnaBridge 143:86740a56073b 10112 /* Bit 11 : Include or exclude channel 11 */
AnnaBridge 143:86740a56073b 10113 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 10114 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 10115 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10116 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10117
AnnaBridge 143:86740a56073b 10118 /* Bit 10 : Include or exclude channel 10 */
AnnaBridge 143:86740a56073b 10119 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 10120 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 10121 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10122 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10123
AnnaBridge 143:86740a56073b 10124 /* Bit 9 : Include or exclude channel 9 */
AnnaBridge 143:86740a56073b 10125 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 10126 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 10127 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10128 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10129
AnnaBridge 143:86740a56073b 10130 /* Bit 8 : Include or exclude channel 8 */
AnnaBridge 143:86740a56073b 10131 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 10132 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 10133 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10134 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10135
AnnaBridge 143:86740a56073b 10136 /* Bit 7 : Include or exclude channel 7 */
AnnaBridge 143:86740a56073b 10137 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 10138 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 10139 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10140 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10141
AnnaBridge 143:86740a56073b 10142 /* Bit 6 : Include or exclude channel 6 */
AnnaBridge 143:86740a56073b 10143 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 10144 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 10145 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10146 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10147
AnnaBridge 143:86740a56073b 10148 /* Bit 5 : Include or exclude channel 5 */
AnnaBridge 143:86740a56073b 10149 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 10150 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 10151 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10152 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10153
AnnaBridge 143:86740a56073b 10154 /* Bit 4 : Include or exclude channel 4 */
AnnaBridge 143:86740a56073b 10155 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 10156 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 10157 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10158 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10159
AnnaBridge 143:86740a56073b 10160 /* Bit 3 : Include or exclude channel 3 */
AnnaBridge 143:86740a56073b 10161 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 10162 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 10163 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10164 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10165
AnnaBridge 143:86740a56073b 10166 /* Bit 2 : Include or exclude channel 2 */
AnnaBridge 143:86740a56073b 10167 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 10168 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 10169 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10170 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10171
AnnaBridge 143:86740a56073b 10172 /* Bit 1 : Include or exclude channel 1 */
AnnaBridge 143:86740a56073b 10173 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 10174 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 10175 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10176 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10177
AnnaBridge 143:86740a56073b 10178 /* Bit 0 : Include or exclude channel 0 */
AnnaBridge 143:86740a56073b 10179 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 10180 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 10181 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
AnnaBridge 143:86740a56073b 10182 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
AnnaBridge 143:86740a56073b 10183
AnnaBridge 143:86740a56073b 10184 /* Register: PPI_FORK_TEP */
AnnaBridge 143:86740a56073b 10185 /* Description: Description cluster[0]: Channel 0 task end-point */
AnnaBridge 143:86740a56073b 10186
AnnaBridge 143:86740a56073b 10187 /* Bits 31..0 : Pointer to task register */
AnnaBridge 143:86740a56073b 10188 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
AnnaBridge 143:86740a56073b 10189 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
AnnaBridge 143:86740a56073b 10190
AnnaBridge 143:86740a56073b 10191
AnnaBridge 143:86740a56073b 10192 /* Peripheral: PWM */
AnnaBridge 143:86740a56073b 10193 /* Description: Pulse Width Modulation Unit 0 */
AnnaBridge 143:86740a56073b 10194
AnnaBridge 143:86740a56073b 10195 /* Register: PWM_SHORTS */
AnnaBridge 143:86740a56073b 10196 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 10197
AnnaBridge 143:86740a56073b 10198 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
AnnaBridge 143:86740a56073b 10199 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
AnnaBridge 143:86740a56073b 10200 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
AnnaBridge 143:86740a56073b 10201 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10202 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10203
AnnaBridge 143:86740a56073b 10204 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
AnnaBridge 143:86740a56073b 10205 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
AnnaBridge 143:86740a56073b 10206 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
AnnaBridge 143:86740a56073b 10207 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10208 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10209
AnnaBridge 143:86740a56073b 10210 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
AnnaBridge 143:86740a56073b 10211 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
AnnaBridge 143:86740a56073b 10212 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
AnnaBridge 143:86740a56073b 10213 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10214 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10215
AnnaBridge 143:86740a56073b 10216 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
AnnaBridge 143:86740a56073b 10217 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
AnnaBridge 143:86740a56073b 10218 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
AnnaBridge 143:86740a56073b 10219 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10220 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10221
AnnaBridge 143:86740a56073b 10222 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
AnnaBridge 143:86740a56073b 10223 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
AnnaBridge 143:86740a56073b 10224 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
AnnaBridge 143:86740a56073b 10225 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10226 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10227
AnnaBridge 143:86740a56073b 10228 /* Register: PWM_INTEN */
AnnaBridge 143:86740a56073b 10229 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 10230
AnnaBridge 143:86740a56073b 10231 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
AnnaBridge 143:86740a56073b 10232 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
AnnaBridge 143:86740a56073b 10233 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
AnnaBridge 143:86740a56073b 10234 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10235 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10236
AnnaBridge 143:86740a56073b 10237 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
AnnaBridge 143:86740a56073b 10238 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
AnnaBridge 143:86740a56073b 10239 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
AnnaBridge 143:86740a56073b 10240 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10241 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10242
AnnaBridge 143:86740a56073b 10243 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
AnnaBridge 143:86740a56073b 10244 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
AnnaBridge 143:86740a56073b 10245 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
AnnaBridge 143:86740a56073b 10246 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10247 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10248
AnnaBridge 143:86740a56073b 10249 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
AnnaBridge 143:86740a56073b 10250 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
AnnaBridge 143:86740a56073b 10251 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
AnnaBridge 143:86740a56073b 10252 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10253 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10254
AnnaBridge 143:86740a56073b 10255 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
AnnaBridge 143:86740a56073b 10256 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
AnnaBridge 143:86740a56073b 10257 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
AnnaBridge 143:86740a56073b 10258 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10259 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10260
AnnaBridge 143:86740a56073b 10261 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
AnnaBridge 143:86740a56073b 10262 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
AnnaBridge 143:86740a56073b 10263 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
AnnaBridge 143:86740a56073b 10264 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10265 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10266
AnnaBridge 143:86740a56073b 10267 /* Bit 1 : Enable or disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 10268 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 10269 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 10270 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10271 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10272
AnnaBridge 143:86740a56073b 10273 /* Register: PWM_INTENSET */
AnnaBridge 143:86740a56073b 10274 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 10275
AnnaBridge 143:86740a56073b 10276 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
AnnaBridge 143:86740a56073b 10277 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
AnnaBridge 143:86740a56073b 10278 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
AnnaBridge 143:86740a56073b 10279 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10280 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10281 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10282
AnnaBridge 143:86740a56073b 10283 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
AnnaBridge 143:86740a56073b 10284 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
AnnaBridge 143:86740a56073b 10285 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
AnnaBridge 143:86740a56073b 10286 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10287 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10288 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10289
AnnaBridge 143:86740a56073b 10290 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
AnnaBridge 143:86740a56073b 10291 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
AnnaBridge 143:86740a56073b 10292 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
AnnaBridge 143:86740a56073b 10293 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10294 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10295 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10296
AnnaBridge 143:86740a56073b 10297 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
AnnaBridge 143:86740a56073b 10298 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
AnnaBridge 143:86740a56073b 10299 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
AnnaBridge 143:86740a56073b 10300 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10301 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10302 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10303
AnnaBridge 143:86740a56073b 10304 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
AnnaBridge 143:86740a56073b 10305 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
AnnaBridge 143:86740a56073b 10306 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
AnnaBridge 143:86740a56073b 10307 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10308 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10309 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10310
AnnaBridge 143:86740a56073b 10311 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
AnnaBridge 143:86740a56073b 10312 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
AnnaBridge 143:86740a56073b 10313 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
AnnaBridge 143:86740a56073b 10314 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10315 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10316 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10317
AnnaBridge 143:86740a56073b 10318 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 10319 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 10320 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 10321 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10322 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10323 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10324
AnnaBridge 143:86740a56073b 10325 /* Register: PWM_INTENCLR */
AnnaBridge 143:86740a56073b 10326 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 10327
AnnaBridge 143:86740a56073b 10328 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
AnnaBridge 143:86740a56073b 10329 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
AnnaBridge 143:86740a56073b 10330 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
AnnaBridge 143:86740a56073b 10331 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10332 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10333 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10334
AnnaBridge 143:86740a56073b 10335 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
AnnaBridge 143:86740a56073b 10336 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
AnnaBridge 143:86740a56073b 10337 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
AnnaBridge 143:86740a56073b 10338 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10339 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10340 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10341
AnnaBridge 143:86740a56073b 10342 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
AnnaBridge 143:86740a56073b 10343 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
AnnaBridge 143:86740a56073b 10344 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
AnnaBridge 143:86740a56073b 10345 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10346 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10347 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10348
AnnaBridge 143:86740a56073b 10349 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
AnnaBridge 143:86740a56073b 10350 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
AnnaBridge 143:86740a56073b 10351 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
AnnaBridge 143:86740a56073b 10352 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10353 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10354 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10355
AnnaBridge 143:86740a56073b 10356 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
AnnaBridge 143:86740a56073b 10357 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
AnnaBridge 143:86740a56073b 10358 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
AnnaBridge 143:86740a56073b 10359 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10360 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10361 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10362
AnnaBridge 143:86740a56073b 10363 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
AnnaBridge 143:86740a56073b 10364 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
AnnaBridge 143:86740a56073b 10365 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
AnnaBridge 143:86740a56073b 10366 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10367 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10368 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10369
AnnaBridge 143:86740a56073b 10370 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 10371 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 10372 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 10373 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10374 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10375 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10376
AnnaBridge 143:86740a56073b 10377 /* Register: PWM_ENABLE */
AnnaBridge 143:86740a56073b 10378 /* Description: PWM module enable register */
AnnaBridge 143:86740a56073b 10379
AnnaBridge 143:86740a56073b 10380 /* Bit 0 : Enable or disable PWM module */
AnnaBridge 143:86740a56073b 10381 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 10382 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 10383 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 10384 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10385
AnnaBridge 143:86740a56073b 10386 /* Register: PWM_MODE */
AnnaBridge 143:86740a56073b 10387 /* Description: Selects operating mode of the wave counter */
AnnaBridge 143:86740a56073b 10388
AnnaBridge 143:86740a56073b 10389 /* Bit 0 : Selects up or up and down as wave counter mode */
AnnaBridge 143:86740a56073b 10390 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
AnnaBridge 143:86740a56073b 10391 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
AnnaBridge 143:86740a56073b 10392 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
AnnaBridge 143:86740a56073b 10393 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
AnnaBridge 143:86740a56073b 10394
AnnaBridge 143:86740a56073b 10395 /* Register: PWM_COUNTERTOP */
AnnaBridge 143:86740a56073b 10396 /* Description: Value up to which the pulse generator counter counts */
AnnaBridge 143:86740a56073b 10397
AnnaBridge 143:86740a56073b 10398 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
AnnaBridge 143:86740a56073b 10399 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
AnnaBridge 143:86740a56073b 10400 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
AnnaBridge 143:86740a56073b 10401
AnnaBridge 143:86740a56073b 10402 /* Register: PWM_PRESCALER */
AnnaBridge 143:86740a56073b 10403 /* Description: Configuration for PWM_CLK */
AnnaBridge 143:86740a56073b 10404
AnnaBridge 143:86740a56073b 10405 /* Bits 2..0 : Pre-scaler of PWM_CLK */
AnnaBridge 143:86740a56073b 10406 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
AnnaBridge 143:86740a56073b 10407 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
AnnaBridge 143:86740a56073b 10408 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */
AnnaBridge 143:86740a56073b 10409 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */
AnnaBridge 143:86740a56073b 10410 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */
AnnaBridge 143:86740a56073b 10411 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */
AnnaBridge 143:86740a56073b 10412 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */
AnnaBridge 143:86740a56073b 10413 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */
AnnaBridge 143:86740a56073b 10414 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */
AnnaBridge 143:86740a56073b 10415 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
AnnaBridge 143:86740a56073b 10416
AnnaBridge 143:86740a56073b 10417 /* Register: PWM_DECODER */
AnnaBridge 143:86740a56073b 10418 /* Description: Configuration of the decoder */
AnnaBridge 143:86740a56073b 10419
AnnaBridge 143:86740a56073b 10420 /* Bit 8 : Selects source for advancing the active sequence */
AnnaBridge 143:86740a56073b 10421 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 10422 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 10423 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
AnnaBridge 143:86740a56073b 10424 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
AnnaBridge 143:86740a56073b 10425
AnnaBridge 143:86740a56073b 10426 /* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
AnnaBridge 143:86740a56073b 10427 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
AnnaBridge 143:86740a56073b 10428 #define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
AnnaBridge 143:86740a56073b 10429 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
AnnaBridge 143:86740a56073b 10430 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
AnnaBridge 143:86740a56073b 10431 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
AnnaBridge 143:86740a56073b 10432 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
AnnaBridge 143:86740a56073b 10433
AnnaBridge 143:86740a56073b 10434 /* Register: PWM_LOOP */
AnnaBridge 143:86740a56073b 10435 /* Description: Amount of playback of a loop */
AnnaBridge 143:86740a56073b 10436
AnnaBridge 143:86740a56073b 10437 /* Bits 15..0 : Amount of playback of pattern cycles */
AnnaBridge 143:86740a56073b 10438 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
AnnaBridge 143:86740a56073b 10439 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
AnnaBridge 143:86740a56073b 10440 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
AnnaBridge 143:86740a56073b 10441
AnnaBridge 143:86740a56073b 10442 /* Register: PWM_SEQ_PTR */
AnnaBridge 143:86740a56073b 10443 /* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */
AnnaBridge 143:86740a56073b 10444
AnnaBridge 143:86740a56073b 10445 /* Bits 31..0 : Beginning address in Data RAM of sequence A */
AnnaBridge 143:86740a56073b 10446 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 10447 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 10448
AnnaBridge 143:86740a56073b 10449 /* Register: PWM_SEQ_CNT */
AnnaBridge 143:86740a56073b 10450 /* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */
AnnaBridge 143:86740a56073b 10451
AnnaBridge 143:86740a56073b 10452 /* Bits 14..0 : Amount of values (duty cycles) in sequence A */
AnnaBridge 143:86740a56073b 10453 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
AnnaBridge 143:86740a56073b 10454 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
AnnaBridge 143:86740a56073b 10455 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
AnnaBridge 143:86740a56073b 10456
AnnaBridge 143:86740a56073b 10457 /* Register: PWM_SEQ_REFRESH */
AnnaBridge 143:86740a56073b 10458 /* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
AnnaBridge 143:86740a56073b 10459
AnnaBridge 143:86740a56073b 10460 /* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
AnnaBridge 143:86740a56073b 10461 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
AnnaBridge 143:86740a56073b 10462 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
AnnaBridge 143:86740a56073b 10463 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
AnnaBridge 143:86740a56073b 10464
AnnaBridge 143:86740a56073b 10465 /* Register: PWM_SEQ_ENDDELAY */
AnnaBridge 143:86740a56073b 10466 /* Description: Description cluster[0]: Time added after the sequence */
AnnaBridge 143:86740a56073b 10467
AnnaBridge 143:86740a56073b 10468 /* Bits 23..0 : Time added after the sequence in PWM periods */
AnnaBridge 143:86740a56073b 10469 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
AnnaBridge 143:86740a56073b 10470 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
AnnaBridge 143:86740a56073b 10471
AnnaBridge 143:86740a56073b 10472 /* Register: PWM_PSEL_OUT */
AnnaBridge 143:86740a56073b 10473 /* Description: Description collection[0]: Output pin select for PWM channel 0 */
AnnaBridge 143:86740a56073b 10474
AnnaBridge 143:86740a56073b 10475 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 10476 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 10477 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 10478 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 10479 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 10480
AnnaBridge 143:86740a56073b 10481 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 10482 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 10483 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 10484
AnnaBridge 143:86740a56073b 10485
AnnaBridge 143:86740a56073b 10486 /* Peripheral: QDEC */
AnnaBridge 143:86740a56073b 10487 /* Description: Quadrature Decoder */
AnnaBridge 143:86740a56073b 10488
AnnaBridge 143:86740a56073b 10489 /* Register: QDEC_SHORTS */
AnnaBridge 143:86740a56073b 10490 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 10491
AnnaBridge 143:86740a56073b 10492 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
AnnaBridge 143:86740a56073b 10493 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
AnnaBridge 143:86740a56073b 10494 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
AnnaBridge 143:86740a56073b 10495 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10496 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10497
AnnaBridge 143:86740a56073b 10498 /* Bit 5 : Shortcut between DBLRDY event and STOP task */
AnnaBridge 143:86740a56073b 10499 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
AnnaBridge 143:86740a56073b 10500 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
AnnaBridge 143:86740a56073b 10501 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10502 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10503
AnnaBridge 143:86740a56073b 10504 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
AnnaBridge 143:86740a56073b 10505 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
AnnaBridge 143:86740a56073b 10506 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
AnnaBridge 143:86740a56073b 10507 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10508 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10509
AnnaBridge 143:86740a56073b 10510 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */
AnnaBridge 143:86740a56073b 10511 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
AnnaBridge 143:86740a56073b 10512 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
AnnaBridge 143:86740a56073b 10513 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10514 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10515
AnnaBridge 143:86740a56073b 10516 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
AnnaBridge 143:86740a56073b 10517 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
AnnaBridge 143:86740a56073b 10518 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
AnnaBridge 143:86740a56073b 10519 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10520 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10521
AnnaBridge 143:86740a56073b 10522 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
AnnaBridge 143:86740a56073b 10523 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
AnnaBridge 143:86740a56073b 10524 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
AnnaBridge 143:86740a56073b 10525 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10526 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10527
AnnaBridge 143:86740a56073b 10528 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
AnnaBridge 143:86740a56073b 10529 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
AnnaBridge 143:86740a56073b 10530 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
AnnaBridge 143:86740a56073b 10531 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10532 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10533
AnnaBridge 143:86740a56073b 10534 /* Register: QDEC_INTENSET */
AnnaBridge 143:86740a56073b 10535 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 10536
AnnaBridge 143:86740a56073b 10537 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 10538 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 10539 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 10540 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10541 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10542 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10543
AnnaBridge 143:86740a56073b 10544 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
AnnaBridge 143:86740a56073b 10545 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
AnnaBridge 143:86740a56073b 10546 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
AnnaBridge 143:86740a56073b 10547 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10548 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10549 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10550
AnnaBridge 143:86740a56073b 10551 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
AnnaBridge 143:86740a56073b 10552 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
AnnaBridge 143:86740a56073b 10553 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
AnnaBridge 143:86740a56073b 10554 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10555 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10556 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10557
AnnaBridge 143:86740a56073b 10558 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
AnnaBridge 143:86740a56073b 10559 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
AnnaBridge 143:86740a56073b 10560 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
AnnaBridge 143:86740a56073b 10561 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10562 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10563 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10564
AnnaBridge 143:86740a56073b 10565 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
AnnaBridge 143:86740a56073b 10566 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 10567 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 10568 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10569 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10570 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10571
AnnaBridge 143:86740a56073b 10572 /* Register: QDEC_INTENCLR */
AnnaBridge 143:86740a56073b 10573 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 10574
AnnaBridge 143:86740a56073b 10575 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 10576 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 10577 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 10578 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10579 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10580 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10581
AnnaBridge 143:86740a56073b 10582 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
AnnaBridge 143:86740a56073b 10583 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
AnnaBridge 143:86740a56073b 10584 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
AnnaBridge 143:86740a56073b 10585 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10586 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10587 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10588
AnnaBridge 143:86740a56073b 10589 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
AnnaBridge 143:86740a56073b 10590 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
AnnaBridge 143:86740a56073b 10591 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
AnnaBridge 143:86740a56073b 10592 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10593 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10594 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10595
AnnaBridge 143:86740a56073b 10596 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
AnnaBridge 143:86740a56073b 10597 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
AnnaBridge 143:86740a56073b 10598 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
AnnaBridge 143:86740a56073b 10599 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10600 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10601 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10602
AnnaBridge 143:86740a56073b 10603 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
AnnaBridge 143:86740a56073b 10604 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 10605 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 10606 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10607 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10608 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10609
AnnaBridge 143:86740a56073b 10610 /* Register: QDEC_ENABLE */
AnnaBridge 143:86740a56073b 10611 /* Description: Enable the quadrature decoder */
AnnaBridge 143:86740a56073b 10612
AnnaBridge 143:86740a56073b 10613 /* Bit 0 : Enable or disable the quadrature decoder */
AnnaBridge 143:86740a56073b 10614 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 10615 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 10616 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10617 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10618
AnnaBridge 143:86740a56073b 10619 /* Register: QDEC_LEDPOL */
AnnaBridge 143:86740a56073b 10620 /* Description: LED output pin polarity */
AnnaBridge 143:86740a56073b 10621
AnnaBridge 143:86740a56073b 10622 /* Bit 0 : LED output pin polarity */
AnnaBridge 143:86740a56073b 10623 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
AnnaBridge 143:86740a56073b 10624 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
AnnaBridge 143:86740a56073b 10625 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
AnnaBridge 143:86740a56073b 10626 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
AnnaBridge 143:86740a56073b 10627
AnnaBridge 143:86740a56073b 10628 /* Register: QDEC_SAMPLEPER */
AnnaBridge 143:86740a56073b 10629 /* Description: Sample period */
AnnaBridge 143:86740a56073b 10630
AnnaBridge 143:86740a56073b 10631 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
AnnaBridge 143:86740a56073b 10632 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
AnnaBridge 143:86740a56073b 10633 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
AnnaBridge 143:86740a56073b 10634 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
AnnaBridge 143:86740a56073b 10635 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
AnnaBridge 143:86740a56073b 10636 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
AnnaBridge 143:86740a56073b 10637 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
AnnaBridge 143:86740a56073b 10638 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
AnnaBridge 143:86740a56073b 10639 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
AnnaBridge 143:86740a56073b 10640 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
AnnaBridge 143:86740a56073b 10641 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
AnnaBridge 143:86740a56073b 10642 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
AnnaBridge 143:86740a56073b 10643 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
AnnaBridge 143:86740a56073b 10644 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
AnnaBridge 143:86740a56073b 10645
AnnaBridge 143:86740a56073b 10646 /* Register: QDEC_SAMPLE */
AnnaBridge 143:86740a56073b 10647 /* Description: Motion sample value */
AnnaBridge 143:86740a56073b 10648
AnnaBridge 143:86740a56073b 10649 /* Bits 31..0 : Last motion sample */
AnnaBridge 143:86740a56073b 10650 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
AnnaBridge 143:86740a56073b 10651 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
AnnaBridge 143:86740a56073b 10652
AnnaBridge 143:86740a56073b 10653 /* Register: QDEC_REPORTPER */
AnnaBridge 143:86740a56073b 10654 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
AnnaBridge 143:86740a56073b 10655
AnnaBridge 143:86740a56073b 10656 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
AnnaBridge 143:86740a56073b 10657 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
AnnaBridge 143:86740a56073b 10658 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
AnnaBridge 143:86740a56073b 10659 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
AnnaBridge 143:86740a56073b 10660 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
AnnaBridge 143:86740a56073b 10661 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
AnnaBridge 143:86740a56073b 10662 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
AnnaBridge 143:86740a56073b 10663 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
AnnaBridge 143:86740a56073b 10664 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
AnnaBridge 143:86740a56073b 10665 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
AnnaBridge 143:86740a56073b 10666 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
AnnaBridge 143:86740a56073b 10667 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
AnnaBridge 143:86740a56073b 10668
AnnaBridge 143:86740a56073b 10669 /* Register: QDEC_ACC */
AnnaBridge 143:86740a56073b 10670 /* Description: Register accumulating the valid transitions */
AnnaBridge 143:86740a56073b 10671
AnnaBridge 143:86740a56073b 10672 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
AnnaBridge 143:86740a56073b 10673 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
AnnaBridge 143:86740a56073b 10674 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
AnnaBridge 143:86740a56073b 10675
AnnaBridge 143:86740a56073b 10676 /* Register: QDEC_ACCREAD */
AnnaBridge 143:86740a56073b 10677 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
AnnaBridge 143:86740a56073b 10678
AnnaBridge 143:86740a56073b 10679 /* Bits 31..0 : Snapshot of the ACC register. */
AnnaBridge 143:86740a56073b 10680 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
AnnaBridge 143:86740a56073b 10681 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
AnnaBridge 143:86740a56073b 10682
AnnaBridge 143:86740a56073b 10683 /* Register: QDEC_PSEL_LED */
AnnaBridge 143:86740a56073b 10684 /* Description: Pin select for LED signal */
AnnaBridge 143:86740a56073b 10685
AnnaBridge 143:86740a56073b 10686 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 10687 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 10688 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 10689 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 10690 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 10691
AnnaBridge 143:86740a56073b 10692 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 10693 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 10694 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 10695
AnnaBridge 143:86740a56073b 10696 /* Register: QDEC_PSEL_A */
AnnaBridge 143:86740a56073b 10697 /* Description: Pin select for A signal */
AnnaBridge 143:86740a56073b 10698
AnnaBridge 143:86740a56073b 10699 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 10700 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 10701 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 10702 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 10703 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 10704
AnnaBridge 143:86740a56073b 10705 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 10706 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 10707 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 10708
AnnaBridge 143:86740a56073b 10709 /* Register: QDEC_PSEL_B */
AnnaBridge 143:86740a56073b 10710 /* Description: Pin select for B signal */
AnnaBridge 143:86740a56073b 10711
AnnaBridge 143:86740a56073b 10712 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 10713 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 10714 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 10715 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 10716 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 10717
AnnaBridge 143:86740a56073b 10718 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 10719 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 10720 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 10721
AnnaBridge 143:86740a56073b 10722 /* Register: QDEC_DBFEN */
AnnaBridge 143:86740a56073b 10723 /* Description: Enable input debounce filters */
AnnaBridge 143:86740a56073b 10724
AnnaBridge 143:86740a56073b 10725 /* Bit 0 : Enable input debounce filters */
AnnaBridge 143:86740a56073b 10726 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
AnnaBridge 143:86740a56073b 10727 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
AnnaBridge 143:86740a56073b 10728 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
AnnaBridge 143:86740a56073b 10729 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
AnnaBridge 143:86740a56073b 10730
AnnaBridge 143:86740a56073b 10731 /* Register: QDEC_LEDPRE */
AnnaBridge 143:86740a56073b 10732 /* Description: Time period the LED is switched ON prior to sampling */
AnnaBridge 143:86740a56073b 10733
AnnaBridge 143:86740a56073b 10734 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
AnnaBridge 143:86740a56073b 10735 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
AnnaBridge 143:86740a56073b 10736 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
AnnaBridge 143:86740a56073b 10737
AnnaBridge 143:86740a56073b 10738 /* Register: QDEC_ACCDBL */
AnnaBridge 143:86740a56073b 10739 /* Description: Register accumulating the number of detected double transitions */
AnnaBridge 143:86740a56073b 10740
AnnaBridge 143:86740a56073b 10741 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
AnnaBridge 143:86740a56073b 10742 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
AnnaBridge 143:86740a56073b 10743 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
AnnaBridge 143:86740a56073b 10744
AnnaBridge 143:86740a56073b 10745 /* Register: QDEC_ACCDBLREAD */
AnnaBridge 143:86740a56073b 10746 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
AnnaBridge 143:86740a56073b 10747
AnnaBridge 143:86740a56073b 10748 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
AnnaBridge 143:86740a56073b 10749 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
AnnaBridge 143:86740a56073b 10750 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
AnnaBridge 143:86740a56073b 10751
AnnaBridge 143:86740a56073b 10752
AnnaBridge 143:86740a56073b 10753 /* Peripheral: RADIO */
AnnaBridge 143:86740a56073b 10754 /* Description: 2.4 GHz Radio */
AnnaBridge 143:86740a56073b 10755
AnnaBridge 143:86740a56073b 10756 /* Register: RADIO_SHORTS */
AnnaBridge 143:86740a56073b 10757 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 10758
AnnaBridge 143:86740a56073b 10759 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
AnnaBridge 143:86740a56073b 10760 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
AnnaBridge 143:86740a56073b 10761 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
AnnaBridge 143:86740a56073b 10762 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10763 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10764
AnnaBridge 143:86740a56073b 10765 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
AnnaBridge 143:86740a56073b 10766 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
AnnaBridge 143:86740a56073b 10767 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
AnnaBridge 143:86740a56073b 10768 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10769 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10770
AnnaBridge 143:86740a56073b 10771 /* Bit 5 : Shortcut between END event and START task */
AnnaBridge 143:86740a56073b 10772 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
AnnaBridge 143:86740a56073b 10773 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
AnnaBridge 143:86740a56073b 10774 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10775 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10776
AnnaBridge 143:86740a56073b 10777 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
AnnaBridge 143:86740a56073b 10778 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
AnnaBridge 143:86740a56073b 10779 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
AnnaBridge 143:86740a56073b 10780 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10781 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10782
AnnaBridge 143:86740a56073b 10783 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
AnnaBridge 143:86740a56073b 10784 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
AnnaBridge 143:86740a56073b 10785 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
AnnaBridge 143:86740a56073b 10786 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10787 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10788
AnnaBridge 143:86740a56073b 10789 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
AnnaBridge 143:86740a56073b 10790 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
AnnaBridge 143:86740a56073b 10791 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
AnnaBridge 143:86740a56073b 10792 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10793 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10794
AnnaBridge 143:86740a56073b 10795 /* Bit 1 : Shortcut between END event and DISABLE task */
AnnaBridge 143:86740a56073b 10796 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
AnnaBridge 143:86740a56073b 10797 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
AnnaBridge 143:86740a56073b 10798 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10799 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10800
AnnaBridge 143:86740a56073b 10801 /* Bit 0 : Shortcut between READY event and START task */
AnnaBridge 143:86740a56073b 10802 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
AnnaBridge 143:86740a56073b 10803 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
AnnaBridge 143:86740a56073b 10804 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 10805 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 10806
AnnaBridge 143:86740a56073b 10807 /* Register: RADIO_INTENSET */
AnnaBridge 143:86740a56073b 10808 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 10809
AnnaBridge 143:86740a56073b 10810 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
AnnaBridge 143:86740a56073b 10811 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
AnnaBridge 143:86740a56073b 10812 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
AnnaBridge 143:86740a56073b 10813 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10814 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10815 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10816
AnnaBridge 143:86740a56073b 10817 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
AnnaBridge 143:86740a56073b 10818 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
AnnaBridge 143:86740a56073b 10819 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
AnnaBridge 143:86740a56073b 10820 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10821 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10822 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10823
AnnaBridge 143:86740a56073b 10824 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
AnnaBridge 143:86740a56073b 10825 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
AnnaBridge 143:86740a56073b 10826 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
AnnaBridge 143:86740a56073b 10827 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10828 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10829 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10830
AnnaBridge 143:86740a56073b 10831 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
AnnaBridge 143:86740a56073b 10832 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
AnnaBridge 143:86740a56073b 10833 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
AnnaBridge 143:86740a56073b 10834 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10835 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10836 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10837
AnnaBridge 143:86740a56073b 10838 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
AnnaBridge 143:86740a56073b 10839 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
AnnaBridge 143:86740a56073b 10840 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
AnnaBridge 143:86740a56073b 10841 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10842 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10843 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10844
AnnaBridge 143:86740a56073b 10845 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
AnnaBridge 143:86740a56073b 10846 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
AnnaBridge 143:86740a56073b 10847 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
AnnaBridge 143:86740a56073b 10848 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10849 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10850 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10851
AnnaBridge 143:86740a56073b 10852 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
AnnaBridge 143:86740a56073b 10853 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
AnnaBridge 143:86740a56073b 10854 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
AnnaBridge 143:86740a56073b 10855 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10856 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10857 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10858
AnnaBridge 143:86740a56073b 10859 /* Bit 3 : Write '1' to Enable interrupt for END event */
AnnaBridge 143:86740a56073b 10860 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 10861 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 10862 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10863 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10864 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10865
AnnaBridge 143:86740a56073b 10866 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
AnnaBridge 143:86740a56073b 10867 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
AnnaBridge 143:86740a56073b 10868 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
AnnaBridge 143:86740a56073b 10869 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10870 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10871 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10872
AnnaBridge 143:86740a56073b 10873 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
AnnaBridge 143:86740a56073b 10874 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 10875 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 10876 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10877 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10878 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10879
AnnaBridge 143:86740a56073b 10880 /* Bit 0 : Write '1' to Enable interrupt for READY event */
AnnaBridge 143:86740a56073b 10881 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 10882 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 10883 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10884 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10885 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 10886
AnnaBridge 143:86740a56073b 10887 /* Register: RADIO_INTENCLR */
AnnaBridge 143:86740a56073b 10888 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 10889
AnnaBridge 143:86740a56073b 10890 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
AnnaBridge 143:86740a56073b 10891 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
AnnaBridge 143:86740a56073b 10892 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
AnnaBridge 143:86740a56073b 10893 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10894 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10895 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10896
AnnaBridge 143:86740a56073b 10897 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
AnnaBridge 143:86740a56073b 10898 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
AnnaBridge 143:86740a56073b 10899 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
AnnaBridge 143:86740a56073b 10900 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10901 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10902 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10903
AnnaBridge 143:86740a56073b 10904 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
AnnaBridge 143:86740a56073b 10905 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
AnnaBridge 143:86740a56073b 10906 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
AnnaBridge 143:86740a56073b 10907 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10908 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10909 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10910
AnnaBridge 143:86740a56073b 10911 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
AnnaBridge 143:86740a56073b 10912 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
AnnaBridge 143:86740a56073b 10913 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
AnnaBridge 143:86740a56073b 10914 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10915 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10916 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10917
AnnaBridge 143:86740a56073b 10918 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
AnnaBridge 143:86740a56073b 10919 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
AnnaBridge 143:86740a56073b 10920 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
AnnaBridge 143:86740a56073b 10921 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10922 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10923 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10924
AnnaBridge 143:86740a56073b 10925 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
AnnaBridge 143:86740a56073b 10926 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
AnnaBridge 143:86740a56073b 10927 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
AnnaBridge 143:86740a56073b 10928 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10929 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10930 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10931
AnnaBridge 143:86740a56073b 10932 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
AnnaBridge 143:86740a56073b 10933 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
AnnaBridge 143:86740a56073b 10934 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
AnnaBridge 143:86740a56073b 10935 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10936 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10937 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10938
AnnaBridge 143:86740a56073b 10939 /* Bit 3 : Write '1' to Disable interrupt for END event */
AnnaBridge 143:86740a56073b 10940 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 10941 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 10942 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10943 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10944 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10945
AnnaBridge 143:86740a56073b 10946 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
AnnaBridge 143:86740a56073b 10947 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
AnnaBridge 143:86740a56073b 10948 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
AnnaBridge 143:86740a56073b 10949 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10950 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10951 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10952
AnnaBridge 143:86740a56073b 10953 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
AnnaBridge 143:86740a56073b 10954 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 10955 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 10956 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10957 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10958 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10959
AnnaBridge 143:86740a56073b 10960 /* Bit 0 : Write '1' to Disable interrupt for READY event */
AnnaBridge 143:86740a56073b 10961 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 10962 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 10963 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 10964 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 10965 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 10966
AnnaBridge 143:86740a56073b 10967 /* Register: RADIO_CRCSTATUS */
AnnaBridge 143:86740a56073b 10968 /* Description: CRC status */
AnnaBridge 143:86740a56073b 10969
AnnaBridge 143:86740a56073b 10970 /* Bit 0 : CRC status of packet received */
AnnaBridge 143:86740a56073b 10971 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
AnnaBridge 143:86740a56073b 10972 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
AnnaBridge 143:86740a56073b 10973 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
AnnaBridge 143:86740a56073b 10974 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
AnnaBridge 143:86740a56073b 10975
AnnaBridge 143:86740a56073b 10976 /* Register: RADIO_RXMATCH */
AnnaBridge 143:86740a56073b 10977 /* Description: Received address */
AnnaBridge 143:86740a56073b 10978
AnnaBridge 143:86740a56073b 10979 /* Bits 2..0 : Received address */
AnnaBridge 143:86740a56073b 10980 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
AnnaBridge 143:86740a56073b 10981 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
AnnaBridge 143:86740a56073b 10982
AnnaBridge 143:86740a56073b 10983 /* Register: RADIO_RXCRC */
AnnaBridge 143:86740a56073b 10984 /* Description: CRC field of previously received packet */
AnnaBridge 143:86740a56073b 10985
AnnaBridge 143:86740a56073b 10986 /* Bits 23..0 : CRC field of previously received packet */
AnnaBridge 143:86740a56073b 10987 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
AnnaBridge 143:86740a56073b 10988 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
AnnaBridge 143:86740a56073b 10989
AnnaBridge 143:86740a56073b 10990 /* Register: RADIO_DAI */
AnnaBridge 143:86740a56073b 10991 /* Description: Device address match index */
AnnaBridge 143:86740a56073b 10992
AnnaBridge 143:86740a56073b 10993 /* Bits 2..0 : Device address match index */
AnnaBridge 143:86740a56073b 10994 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
AnnaBridge 143:86740a56073b 10995 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
AnnaBridge 143:86740a56073b 10996
AnnaBridge 143:86740a56073b 10997 /* Register: RADIO_PACKETPTR */
AnnaBridge 143:86740a56073b 10998 /* Description: Packet pointer */
AnnaBridge 143:86740a56073b 10999
AnnaBridge 143:86740a56073b 11000 /* Bits 31..0 : Packet pointer */
AnnaBridge 143:86740a56073b 11001 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
AnnaBridge 143:86740a56073b 11002 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
AnnaBridge 143:86740a56073b 11003
AnnaBridge 143:86740a56073b 11004 /* Register: RADIO_FREQUENCY */
AnnaBridge 143:86740a56073b 11005 /* Description: Frequency */
AnnaBridge 143:86740a56073b 11006
AnnaBridge 143:86740a56073b 11007 /* Bit 8 : Channel map selection. */
AnnaBridge 143:86740a56073b 11008 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
AnnaBridge 143:86740a56073b 11009 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
AnnaBridge 143:86740a56073b 11010 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
AnnaBridge 143:86740a56073b 11011 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
AnnaBridge 143:86740a56073b 11012
AnnaBridge 143:86740a56073b 11013 /* Bits 6..0 : Radio channel frequency */
AnnaBridge 143:86740a56073b 11014 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 11015 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 11016
AnnaBridge 143:86740a56073b 11017 /* Register: RADIO_TXPOWER */
AnnaBridge 143:86740a56073b 11018 /* Description: Output power */
AnnaBridge 143:86740a56073b 11019
AnnaBridge 143:86740a56073b 11020 /* Bits 7..0 : RADIO output power. */
AnnaBridge 143:86740a56073b 11021 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
AnnaBridge 143:86740a56073b 11022 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
AnnaBridge 143:86740a56073b 11023 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
AnnaBridge 143:86740a56073b 11024 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
AnnaBridge 143:86740a56073b 11025 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
AnnaBridge 143:86740a56073b 11026 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */
AnnaBridge 143:86740a56073b 11027 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
AnnaBridge 143:86740a56073b 11028 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
AnnaBridge 143:86740a56073b 11029 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
AnnaBridge 143:86740a56073b 11030 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
AnnaBridge 143:86740a56073b 11031 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
AnnaBridge 143:86740a56073b 11032 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
AnnaBridge 143:86740a56073b 11033
AnnaBridge 143:86740a56073b 11034 /* Register: RADIO_MODE */
AnnaBridge 143:86740a56073b 11035 /* Description: Data rate and modulation */
AnnaBridge 143:86740a56073b 11036
AnnaBridge 143:86740a56073b 11037 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
AnnaBridge 143:86740a56073b 11038 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 11039 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 11040 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
AnnaBridge 143:86740a56073b 11041 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
AnnaBridge 143:86740a56073b 11042 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */
AnnaBridge 143:86740a56073b 11043 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
AnnaBridge 143:86740a56073b 11044
AnnaBridge 143:86740a56073b 11045 /* Register: RADIO_PCNF0 */
AnnaBridge 143:86740a56073b 11046 /* Description: Packet configuration register 0 */
AnnaBridge 143:86740a56073b 11047
AnnaBridge 143:86740a56073b 11048 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
AnnaBridge 143:86740a56073b 11049 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
AnnaBridge 143:86740a56073b 11050 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
AnnaBridge 143:86740a56073b 11051 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
AnnaBridge 143:86740a56073b 11052 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
AnnaBridge 143:86740a56073b 11053
AnnaBridge 143:86740a56073b 11054 /* Bit 20 : Include or exclude S1 field in RAM */
AnnaBridge 143:86740a56073b 11055 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
AnnaBridge 143:86740a56073b 11056 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
AnnaBridge 143:86740a56073b 11057 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
AnnaBridge 143:86740a56073b 11058 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
AnnaBridge 143:86740a56073b 11059
AnnaBridge 143:86740a56073b 11060 /* Bits 19..16 : Length on air of S1 field in number of bits. */
AnnaBridge 143:86740a56073b 11061 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
AnnaBridge 143:86740a56073b 11062 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
AnnaBridge 143:86740a56073b 11063
AnnaBridge 143:86740a56073b 11064 /* Bit 8 : Length on air of S0 field in number of bytes. */
AnnaBridge 143:86740a56073b 11065 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
AnnaBridge 143:86740a56073b 11066 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
AnnaBridge 143:86740a56073b 11067
AnnaBridge 143:86740a56073b 11068 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
AnnaBridge 143:86740a56073b 11069 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
AnnaBridge 143:86740a56073b 11070 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
AnnaBridge 143:86740a56073b 11071
AnnaBridge 143:86740a56073b 11072 /* Register: RADIO_PCNF1 */
AnnaBridge 143:86740a56073b 11073 /* Description: Packet configuration register 1 */
AnnaBridge 143:86740a56073b 11074
AnnaBridge 143:86740a56073b 11075 /* Bit 25 : Enable or disable packet whitening */
AnnaBridge 143:86740a56073b 11076 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
AnnaBridge 143:86740a56073b 11077 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
AnnaBridge 143:86740a56073b 11078 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11079 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11080
AnnaBridge 143:86740a56073b 11081 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
AnnaBridge 143:86740a56073b 11082 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
AnnaBridge 143:86740a56073b 11083 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
AnnaBridge 143:86740a56073b 11084 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
AnnaBridge 143:86740a56073b 11085 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
AnnaBridge 143:86740a56073b 11086
AnnaBridge 143:86740a56073b 11087 /* Bits 18..16 : Base address length in number of bytes */
AnnaBridge 143:86740a56073b 11088 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
AnnaBridge 143:86740a56073b 11089 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
AnnaBridge 143:86740a56073b 11090
AnnaBridge 143:86740a56073b 11091 /* Bits 15..8 : Static length in number of bytes */
AnnaBridge 143:86740a56073b 11092 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
AnnaBridge 143:86740a56073b 11093 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
AnnaBridge 143:86740a56073b 11094
AnnaBridge 143:86740a56073b 11095 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
AnnaBridge 143:86740a56073b 11096 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
AnnaBridge 143:86740a56073b 11097 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
AnnaBridge 143:86740a56073b 11098
AnnaBridge 143:86740a56073b 11099 /* Register: RADIO_BASE0 */
AnnaBridge 143:86740a56073b 11100 /* Description: Base address 0 */
AnnaBridge 143:86740a56073b 11101
AnnaBridge 143:86740a56073b 11102 /* Bits 31..0 : Base address 0 */
AnnaBridge 143:86740a56073b 11103 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
AnnaBridge 143:86740a56073b 11104 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
AnnaBridge 143:86740a56073b 11105
AnnaBridge 143:86740a56073b 11106 /* Register: RADIO_BASE1 */
AnnaBridge 143:86740a56073b 11107 /* Description: Base address 1 */
AnnaBridge 143:86740a56073b 11108
AnnaBridge 143:86740a56073b 11109 /* Bits 31..0 : Base address 1 */
AnnaBridge 143:86740a56073b 11110 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
AnnaBridge 143:86740a56073b 11111 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
AnnaBridge 143:86740a56073b 11112
AnnaBridge 143:86740a56073b 11113 /* Register: RADIO_PREFIX0 */
AnnaBridge 143:86740a56073b 11114 /* Description: Prefixes bytes for logical addresses 0-3 */
AnnaBridge 143:86740a56073b 11115
AnnaBridge 143:86740a56073b 11116 /* Bits 31..24 : Address prefix 3. */
AnnaBridge 143:86740a56073b 11117 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
AnnaBridge 143:86740a56073b 11118 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
AnnaBridge 143:86740a56073b 11119
AnnaBridge 143:86740a56073b 11120 /* Bits 23..16 : Address prefix 2. */
AnnaBridge 143:86740a56073b 11121 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
AnnaBridge 143:86740a56073b 11122 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
AnnaBridge 143:86740a56073b 11123
AnnaBridge 143:86740a56073b 11124 /* Bits 15..8 : Address prefix 1. */
AnnaBridge 143:86740a56073b 11125 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
AnnaBridge 143:86740a56073b 11126 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
AnnaBridge 143:86740a56073b 11127
AnnaBridge 143:86740a56073b 11128 /* Bits 7..0 : Address prefix 0. */
AnnaBridge 143:86740a56073b 11129 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
AnnaBridge 143:86740a56073b 11130 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
AnnaBridge 143:86740a56073b 11131
AnnaBridge 143:86740a56073b 11132 /* Register: RADIO_PREFIX1 */
AnnaBridge 143:86740a56073b 11133 /* Description: Prefixes bytes for logical addresses 4-7 */
AnnaBridge 143:86740a56073b 11134
AnnaBridge 143:86740a56073b 11135 /* Bits 31..24 : Address prefix 7. */
AnnaBridge 143:86740a56073b 11136 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
AnnaBridge 143:86740a56073b 11137 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
AnnaBridge 143:86740a56073b 11138
AnnaBridge 143:86740a56073b 11139 /* Bits 23..16 : Address prefix 6. */
AnnaBridge 143:86740a56073b 11140 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
AnnaBridge 143:86740a56073b 11141 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
AnnaBridge 143:86740a56073b 11142
AnnaBridge 143:86740a56073b 11143 /* Bits 15..8 : Address prefix 5. */
AnnaBridge 143:86740a56073b 11144 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
AnnaBridge 143:86740a56073b 11145 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
AnnaBridge 143:86740a56073b 11146
AnnaBridge 143:86740a56073b 11147 /* Bits 7..0 : Address prefix 4. */
AnnaBridge 143:86740a56073b 11148 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
AnnaBridge 143:86740a56073b 11149 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
AnnaBridge 143:86740a56073b 11150
AnnaBridge 143:86740a56073b 11151 /* Register: RADIO_TXADDRESS */
AnnaBridge 143:86740a56073b 11152 /* Description: Transmit address select */
AnnaBridge 143:86740a56073b 11153
AnnaBridge 143:86740a56073b 11154 /* Bits 2..0 : Transmit address select */
AnnaBridge 143:86740a56073b 11155 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
AnnaBridge 143:86740a56073b 11156 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
AnnaBridge 143:86740a56073b 11157
AnnaBridge 143:86740a56073b 11158 /* Register: RADIO_RXADDRESSES */
AnnaBridge 143:86740a56073b 11159 /* Description: Receive address select */
AnnaBridge 143:86740a56073b 11160
AnnaBridge 143:86740a56073b 11161 /* Bit 7 : Enable or disable reception on logical address 7. */
AnnaBridge 143:86740a56073b 11162 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
AnnaBridge 143:86740a56073b 11163 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
AnnaBridge 143:86740a56073b 11164 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11165 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11166
AnnaBridge 143:86740a56073b 11167 /* Bit 6 : Enable or disable reception on logical address 6. */
AnnaBridge 143:86740a56073b 11168 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
AnnaBridge 143:86740a56073b 11169 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
AnnaBridge 143:86740a56073b 11170 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11171 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11172
AnnaBridge 143:86740a56073b 11173 /* Bit 5 : Enable or disable reception on logical address 5. */
AnnaBridge 143:86740a56073b 11174 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
AnnaBridge 143:86740a56073b 11175 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
AnnaBridge 143:86740a56073b 11176 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11177 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11178
AnnaBridge 143:86740a56073b 11179 /* Bit 4 : Enable or disable reception on logical address 4. */
AnnaBridge 143:86740a56073b 11180 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
AnnaBridge 143:86740a56073b 11181 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
AnnaBridge 143:86740a56073b 11182 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11183 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11184
AnnaBridge 143:86740a56073b 11185 /* Bit 3 : Enable or disable reception on logical address 3. */
AnnaBridge 143:86740a56073b 11186 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
AnnaBridge 143:86740a56073b 11187 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
AnnaBridge 143:86740a56073b 11188 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11189 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11190
AnnaBridge 143:86740a56073b 11191 /* Bit 2 : Enable or disable reception on logical address 2. */
AnnaBridge 143:86740a56073b 11192 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
AnnaBridge 143:86740a56073b 11193 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
AnnaBridge 143:86740a56073b 11194 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11195 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11196
AnnaBridge 143:86740a56073b 11197 /* Bit 1 : Enable or disable reception on logical address 1. */
AnnaBridge 143:86740a56073b 11198 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
AnnaBridge 143:86740a56073b 11199 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
AnnaBridge 143:86740a56073b 11200 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11201 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11202
AnnaBridge 143:86740a56073b 11203 /* Bit 0 : Enable or disable reception on logical address 0. */
AnnaBridge 143:86740a56073b 11204 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
AnnaBridge 143:86740a56073b 11205 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
AnnaBridge 143:86740a56073b 11206 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11207 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11208
AnnaBridge 143:86740a56073b 11209 /* Register: RADIO_CRCCNF */
AnnaBridge 143:86740a56073b 11210 /* Description: CRC configuration */
AnnaBridge 143:86740a56073b 11211
AnnaBridge 143:86740a56073b 11212 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
AnnaBridge 143:86740a56073b 11213 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
AnnaBridge 143:86740a56073b 11214 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
AnnaBridge 143:86740a56073b 11215 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
AnnaBridge 143:86740a56073b 11216 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
AnnaBridge 143:86740a56073b 11217
AnnaBridge 143:86740a56073b 11218 /* Bits 1..0 : CRC length in number of bytes. */
AnnaBridge 143:86740a56073b 11219 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
AnnaBridge 143:86740a56073b 11220 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
AnnaBridge 143:86740a56073b 11221 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
AnnaBridge 143:86740a56073b 11222 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
AnnaBridge 143:86740a56073b 11223 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
AnnaBridge 143:86740a56073b 11224 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
AnnaBridge 143:86740a56073b 11225
AnnaBridge 143:86740a56073b 11226 /* Register: RADIO_CRCPOLY */
AnnaBridge 143:86740a56073b 11227 /* Description: CRC polynomial */
AnnaBridge 143:86740a56073b 11228
AnnaBridge 143:86740a56073b 11229 /* Bits 23..0 : CRC polynomial */
AnnaBridge 143:86740a56073b 11230 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
AnnaBridge 143:86740a56073b 11231 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
AnnaBridge 143:86740a56073b 11232
AnnaBridge 143:86740a56073b 11233 /* Register: RADIO_CRCINIT */
AnnaBridge 143:86740a56073b 11234 /* Description: CRC initial value */
AnnaBridge 143:86740a56073b 11235
AnnaBridge 143:86740a56073b 11236 /* Bits 23..0 : CRC initial value */
AnnaBridge 143:86740a56073b 11237 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
AnnaBridge 143:86740a56073b 11238 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
AnnaBridge 143:86740a56073b 11239
AnnaBridge 143:86740a56073b 11240 /* Register: RADIO_TIFS */
AnnaBridge 143:86740a56073b 11241 /* Description: Inter Frame Spacing in us */
AnnaBridge 143:86740a56073b 11242
AnnaBridge 143:86740a56073b 11243 /* Bits 7..0 : Inter Frame Spacing in us */
AnnaBridge 143:86740a56073b 11244 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
AnnaBridge 143:86740a56073b 11245 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
AnnaBridge 143:86740a56073b 11246
AnnaBridge 143:86740a56073b 11247 /* Register: RADIO_RSSISAMPLE */
AnnaBridge 143:86740a56073b 11248 /* Description: RSSI sample */
AnnaBridge 143:86740a56073b 11249
AnnaBridge 143:86740a56073b 11250 /* Bits 6..0 : RSSI sample */
AnnaBridge 143:86740a56073b 11251 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
AnnaBridge 143:86740a56073b 11252 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
AnnaBridge 143:86740a56073b 11253
AnnaBridge 143:86740a56073b 11254 /* Register: RADIO_STATE */
AnnaBridge 143:86740a56073b 11255 /* Description: Current radio state */
AnnaBridge 143:86740a56073b 11256
AnnaBridge 143:86740a56073b 11257 /* Bits 3..0 : Current radio state */
AnnaBridge 143:86740a56073b 11258 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
AnnaBridge 143:86740a56073b 11259 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
AnnaBridge 143:86740a56073b 11260 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
AnnaBridge 143:86740a56073b 11261 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
AnnaBridge 143:86740a56073b 11262 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
AnnaBridge 143:86740a56073b 11263 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
AnnaBridge 143:86740a56073b 11264 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
AnnaBridge 143:86740a56073b 11265 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
AnnaBridge 143:86740a56073b 11266 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
AnnaBridge 143:86740a56073b 11267 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
AnnaBridge 143:86740a56073b 11268 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
AnnaBridge 143:86740a56073b 11269
AnnaBridge 143:86740a56073b 11270 /* Register: RADIO_DATAWHITEIV */
AnnaBridge 143:86740a56073b 11271 /* Description: Data whitening initial value */
AnnaBridge 143:86740a56073b 11272
AnnaBridge 143:86740a56073b 11273 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
AnnaBridge 143:86740a56073b 11274 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
AnnaBridge 143:86740a56073b 11275 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
AnnaBridge 143:86740a56073b 11276
AnnaBridge 143:86740a56073b 11277 /* Register: RADIO_BCC */
AnnaBridge 143:86740a56073b 11278 /* Description: Bit counter compare */
AnnaBridge 143:86740a56073b 11279
AnnaBridge 143:86740a56073b 11280 /* Bits 31..0 : Bit counter compare */
AnnaBridge 143:86740a56073b 11281 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
AnnaBridge 143:86740a56073b 11282 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
AnnaBridge 143:86740a56073b 11283
AnnaBridge 143:86740a56073b 11284 /* Register: RADIO_DAB */
AnnaBridge 143:86740a56073b 11285 /* Description: Description collection[0]: Device address base segment 0 */
AnnaBridge 143:86740a56073b 11286
AnnaBridge 143:86740a56073b 11287 /* Bits 31..0 : Device address base segment 0 */
AnnaBridge 143:86740a56073b 11288 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
AnnaBridge 143:86740a56073b 11289 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
AnnaBridge 143:86740a56073b 11290
AnnaBridge 143:86740a56073b 11291 /* Register: RADIO_DAP */
AnnaBridge 143:86740a56073b 11292 /* Description: Description collection[0]: Device address prefix 0 */
AnnaBridge 143:86740a56073b 11293
AnnaBridge 143:86740a56073b 11294 /* Bits 15..0 : Device address prefix 0 */
AnnaBridge 143:86740a56073b 11295 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
AnnaBridge 143:86740a56073b 11296 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
AnnaBridge 143:86740a56073b 11297
AnnaBridge 143:86740a56073b 11298 /* Register: RADIO_DACNF */
AnnaBridge 143:86740a56073b 11299 /* Description: Device address match configuration */
AnnaBridge 143:86740a56073b 11300
AnnaBridge 143:86740a56073b 11301 /* Bit 15 : TxAdd for device address 7 */
AnnaBridge 143:86740a56073b 11302 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
AnnaBridge 143:86740a56073b 11303 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
AnnaBridge 143:86740a56073b 11304
AnnaBridge 143:86740a56073b 11305 /* Bit 14 : TxAdd for device address 6 */
AnnaBridge 143:86740a56073b 11306 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
AnnaBridge 143:86740a56073b 11307 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
AnnaBridge 143:86740a56073b 11308
AnnaBridge 143:86740a56073b 11309 /* Bit 13 : TxAdd for device address 5 */
AnnaBridge 143:86740a56073b 11310 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
AnnaBridge 143:86740a56073b 11311 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
AnnaBridge 143:86740a56073b 11312
AnnaBridge 143:86740a56073b 11313 /* Bit 12 : TxAdd for device address 4 */
AnnaBridge 143:86740a56073b 11314 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
AnnaBridge 143:86740a56073b 11315 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
AnnaBridge 143:86740a56073b 11316
AnnaBridge 143:86740a56073b 11317 /* Bit 11 : TxAdd for device address 3 */
AnnaBridge 143:86740a56073b 11318 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
AnnaBridge 143:86740a56073b 11319 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
AnnaBridge 143:86740a56073b 11320
AnnaBridge 143:86740a56073b 11321 /* Bit 10 : TxAdd for device address 2 */
AnnaBridge 143:86740a56073b 11322 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
AnnaBridge 143:86740a56073b 11323 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
AnnaBridge 143:86740a56073b 11324
AnnaBridge 143:86740a56073b 11325 /* Bit 9 : TxAdd for device address 1 */
AnnaBridge 143:86740a56073b 11326 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
AnnaBridge 143:86740a56073b 11327 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
AnnaBridge 143:86740a56073b 11328
AnnaBridge 143:86740a56073b 11329 /* Bit 8 : TxAdd for device address 0 */
AnnaBridge 143:86740a56073b 11330 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
AnnaBridge 143:86740a56073b 11331 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
AnnaBridge 143:86740a56073b 11332
AnnaBridge 143:86740a56073b 11333 /* Bit 7 : Enable or disable device address matching using device address 7 */
AnnaBridge 143:86740a56073b 11334 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
AnnaBridge 143:86740a56073b 11335 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
AnnaBridge 143:86740a56073b 11336 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11337 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11338
AnnaBridge 143:86740a56073b 11339 /* Bit 6 : Enable or disable device address matching using device address 6 */
AnnaBridge 143:86740a56073b 11340 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
AnnaBridge 143:86740a56073b 11341 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
AnnaBridge 143:86740a56073b 11342 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11343 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11344
AnnaBridge 143:86740a56073b 11345 /* Bit 5 : Enable or disable device address matching using device address 5 */
AnnaBridge 143:86740a56073b 11346 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
AnnaBridge 143:86740a56073b 11347 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
AnnaBridge 143:86740a56073b 11348 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11349 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11350
AnnaBridge 143:86740a56073b 11351 /* Bit 4 : Enable or disable device address matching using device address 4 */
AnnaBridge 143:86740a56073b 11352 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
AnnaBridge 143:86740a56073b 11353 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
AnnaBridge 143:86740a56073b 11354 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11355 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11356
AnnaBridge 143:86740a56073b 11357 /* Bit 3 : Enable or disable device address matching using device address 3 */
AnnaBridge 143:86740a56073b 11358 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
AnnaBridge 143:86740a56073b 11359 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
AnnaBridge 143:86740a56073b 11360 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11361 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11362
AnnaBridge 143:86740a56073b 11363 /* Bit 2 : Enable or disable device address matching using device address 2 */
AnnaBridge 143:86740a56073b 11364 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
AnnaBridge 143:86740a56073b 11365 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
AnnaBridge 143:86740a56073b 11366 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11367 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11368
AnnaBridge 143:86740a56073b 11369 /* Bit 1 : Enable or disable device address matching using device address 1 */
AnnaBridge 143:86740a56073b 11370 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
AnnaBridge 143:86740a56073b 11371 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
AnnaBridge 143:86740a56073b 11372 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11373 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11374
AnnaBridge 143:86740a56073b 11375 /* Bit 0 : Enable or disable device address matching using device address 0 */
AnnaBridge 143:86740a56073b 11376 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
AnnaBridge 143:86740a56073b 11377 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
AnnaBridge 143:86740a56073b 11378 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11379 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11380
AnnaBridge 143:86740a56073b 11381 /* Register: RADIO_MODECNF0 */
AnnaBridge 143:86740a56073b 11382 /* Description: Radio mode configuration register 0 */
AnnaBridge 143:86740a56073b 11383
AnnaBridge 143:86740a56073b 11384 /* Bits 9..8 : Default TX value */
AnnaBridge 143:86740a56073b 11385 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
AnnaBridge 143:86740a56073b 11386 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
AnnaBridge 143:86740a56073b 11387 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
AnnaBridge 143:86740a56073b 11388 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
AnnaBridge 143:86740a56073b 11389 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
AnnaBridge 143:86740a56073b 11390
AnnaBridge 143:86740a56073b 11391 /* Bit 0 : Radio ramp-up time */
AnnaBridge 143:86740a56073b 11392 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
AnnaBridge 143:86740a56073b 11393 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
AnnaBridge 143:86740a56073b 11394 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
AnnaBridge 143:86740a56073b 11395 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
AnnaBridge 143:86740a56073b 11396
AnnaBridge 143:86740a56073b 11397 /* Register: RADIO_POWER */
AnnaBridge 143:86740a56073b 11398 /* Description: Peripheral power control */
AnnaBridge 143:86740a56073b 11399
AnnaBridge 143:86740a56073b 11400 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
AnnaBridge 143:86740a56073b 11401 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 11402 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 11403 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
AnnaBridge 143:86740a56073b 11404 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
AnnaBridge 143:86740a56073b 11405
AnnaBridge 143:86740a56073b 11406
AnnaBridge 143:86740a56073b 11407 /* Peripheral: RNG */
AnnaBridge 143:86740a56073b 11408 /* Description: Random Number Generator */
AnnaBridge 143:86740a56073b 11409
AnnaBridge 143:86740a56073b 11410 /* Register: RNG_SHORTS */
AnnaBridge 143:86740a56073b 11411 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 11412
AnnaBridge 143:86740a56073b 11413 /* Bit 0 : Shortcut between VALRDY event and STOP task */
AnnaBridge 143:86740a56073b 11414 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
AnnaBridge 143:86740a56073b 11415 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
AnnaBridge 143:86740a56073b 11416 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 11417 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 11418
AnnaBridge 143:86740a56073b 11419 /* Register: RNG_INTENSET */
AnnaBridge 143:86740a56073b 11420 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 11421
AnnaBridge 143:86740a56073b 11422 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
AnnaBridge 143:86740a56073b 11423 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
AnnaBridge 143:86740a56073b 11424 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
AnnaBridge 143:86740a56073b 11425 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11426 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11427 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11428
AnnaBridge 143:86740a56073b 11429 /* Register: RNG_INTENCLR */
AnnaBridge 143:86740a56073b 11430 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 11431
AnnaBridge 143:86740a56073b 11432 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
AnnaBridge 143:86740a56073b 11433 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
AnnaBridge 143:86740a56073b 11434 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
AnnaBridge 143:86740a56073b 11435 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11436 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11437 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11438
AnnaBridge 143:86740a56073b 11439 /* Register: RNG_CONFIG */
AnnaBridge 143:86740a56073b 11440 /* Description: Configuration register */
AnnaBridge 143:86740a56073b 11441
AnnaBridge 143:86740a56073b 11442 /* Bit 0 : Bias correction */
AnnaBridge 143:86740a56073b 11443 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
AnnaBridge 143:86740a56073b 11444 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
AnnaBridge 143:86740a56073b 11445 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 11446 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 11447
AnnaBridge 143:86740a56073b 11448 /* Register: RNG_VALUE */
AnnaBridge 143:86740a56073b 11449 /* Description: Output random number */
AnnaBridge 143:86740a56073b 11450
AnnaBridge 143:86740a56073b 11451 /* Bits 7..0 : Generated random number */
AnnaBridge 143:86740a56073b 11452 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
AnnaBridge 143:86740a56073b 11453 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
AnnaBridge 143:86740a56073b 11454
AnnaBridge 143:86740a56073b 11455
AnnaBridge 143:86740a56073b 11456 /* Peripheral: RTC */
AnnaBridge 143:86740a56073b 11457 /* Description: Real time counter 0 */
AnnaBridge 143:86740a56073b 11458
AnnaBridge 143:86740a56073b 11459 /* Register: RTC_INTENSET */
AnnaBridge 143:86740a56073b 11460 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 11461
AnnaBridge 143:86740a56073b 11462 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
AnnaBridge 143:86740a56073b 11463 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11464 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11465 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11466 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11467 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11468
AnnaBridge 143:86740a56073b 11469 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
AnnaBridge 143:86740a56073b 11470 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11471 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11472 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11473 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11474 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11475
AnnaBridge 143:86740a56073b 11476 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
AnnaBridge 143:86740a56073b 11477 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11478 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11479 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11480 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11481 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11482
AnnaBridge 143:86740a56073b 11483 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
AnnaBridge 143:86740a56073b 11484 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11485 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11486 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11487 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11488 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11489
AnnaBridge 143:86740a56073b 11490 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
AnnaBridge 143:86740a56073b 11491 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 11492 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 11493 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11494 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11495 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11496
AnnaBridge 143:86740a56073b 11497 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
AnnaBridge 143:86740a56073b 11498 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 11499 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 11500 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11501 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11502 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11503
AnnaBridge 143:86740a56073b 11504 /* Register: RTC_INTENCLR */
AnnaBridge 143:86740a56073b 11505 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 11506
AnnaBridge 143:86740a56073b 11507 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
AnnaBridge 143:86740a56073b 11508 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11509 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11510 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11511 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11512 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11513
AnnaBridge 143:86740a56073b 11514 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
AnnaBridge 143:86740a56073b 11515 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11516 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11517 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11518 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11519 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11520
AnnaBridge 143:86740a56073b 11521 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
AnnaBridge 143:86740a56073b 11522 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11523 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11524 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11525 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11526 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11527
AnnaBridge 143:86740a56073b 11528 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
AnnaBridge 143:86740a56073b 11529 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11530 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11531 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11532 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11533 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11534
AnnaBridge 143:86740a56073b 11535 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
AnnaBridge 143:86740a56073b 11536 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 11537 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 11538 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11539 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11540 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11541
AnnaBridge 143:86740a56073b 11542 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
AnnaBridge 143:86740a56073b 11543 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 11544 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 11545 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11546 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11547 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11548
AnnaBridge 143:86740a56073b 11549 /* Register: RTC_EVTEN */
AnnaBridge 143:86740a56073b 11550 /* Description: Enable or disable event routing */
AnnaBridge 143:86740a56073b 11551
AnnaBridge 143:86740a56073b 11552 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
AnnaBridge 143:86740a56073b 11553 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11554 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11555 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11556 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11557
AnnaBridge 143:86740a56073b 11558 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
AnnaBridge 143:86740a56073b 11559 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11560 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11561 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11562 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11563
AnnaBridge 143:86740a56073b 11564 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
AnnaBridge 143:86740a56073b 11565 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11566 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11567 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11568 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11569
AnnaBridge 143:86740a56073b 11570 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
AnnaBridge 143:86740a56073b 11571 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11572 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11573 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11574 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11575
AnnaBridge 143:86740a56073b 11576 /* Bit 1 : Enable or disable event routing for OVRFLW event */
AnnaBridge 143:86740a56073b 11577 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 11578 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 11579 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11580 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11581
AnnaBridge 143:86740a56073b 11582 /* Bit 0 : Enable or disable event routing for TICK event */
AnnaBridge 143:86740a56073b 11583 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 11584 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 11585 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11586 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11587
AnnaBridge 143:86740a56073b 11588 /* Register: RTC_EVTENSET */
AnnaBridge 143:86740a56073b 11589 /* Description: Enable event routing */
AnnaBridge 143:86740a56073b 11590
AnnaBridge 143:86740a56073b 11591 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
AnnaBridge 143:86740a56073b 11592 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11593 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11594 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11595 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11596 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11597
AnnaBridge 143:86740a56073b 11598 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
AnnaBridge 143:86740a56073b 11599 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11600 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11601 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11602 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11603 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11604
AnnaBridge 143:86740a56073b 11605 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
AnnaBridge 143:86740a56073b 11606 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11607 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11608 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11609 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11610 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11611
AnnaBridge 143:86740a56073b 11612 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
AnnaBridge 143:86740a56073b 11613 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11614 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11615 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11616 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11617 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11618
AnnaBridge 143:86740a56073b 11619 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
AnnaBridge 143:86740a56073b 11620 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 11621 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 11622 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11623 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11624 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11625
AnnaBridge 143:86740a56073b 11626 /* Bit 0 : Write '1' to Enable event routing for TICK event */
AnnaBridge 143:86740a56073b 11627 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 11628 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 11629 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11630 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11631 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11632
AnnaBridge 143:86740a56073b 11633 /* Register: RTC_EVTENCLR */
AnnaBridge 143:86740a56073b 11634 /* Description: Disable event routing */
AnnaBridge 143:86740a56073b 11635
AnnaBridge 143:86740a56073b 11636 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
AnnaBridge 143:86740a56073b 11637 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11638 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 11639 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11640 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11641 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11642
AnnaBridge 143:86740a56073b 11643 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
AnnaBridge 143:86740a56073b 11644 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11645 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 11646 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11647 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11648 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11649
AnnaBridge 143:86740a56073b 11650 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
AnnaBridge 143:86740a56073b 11651 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11652 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 11653 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11654 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11655 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11656
AnnaBridge 143:86740a56073b 11657 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
AnnaBridge 143:86740a56073b 11658 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11659 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 11660 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11661 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11662 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11663
AnnaBridge 143:86740a56073b 11664 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
AnnaBridge 143:86740a56073b 11665 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 11666 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 11667 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11668 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11669 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11670
AnnaBridge 143:86740a56073b 11671 /* Bit 0 : Write '1' to Disable event routing for TICK event */
AnnaBridge 143:86740a56073b 11672 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 11673 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 11674 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11675 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11676 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11677
AnnaBridge 143:86740a56073b 11678 /* Register: RTC_COUNTER */
AnnaBridge 143:86740a56073b 11679 /* Description: Current COUNTER value */
AnnaBridge 143:86740a56073b 11680
AnnaBridge 143:86740a56073b 11681 /* Bits 23..0 : Counter value */
AnnaBridge 143:86740a56073b 11682 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
AnnaBridge 143:86740a56073b 11683 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
AnnaBridge 143:86740a56073b 11684
AnnaBridge 143:86740a56073b 11685 /* Register: RTC_PRESCALER */
AnnaBridge 143:86740a56073b 11686 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
AnnaBridge 143:86740a56073b 11687
AnnaBridge 143:86740a56073b 11688 /* Bits 11..0 : Prescaler value */
AnnaBridge 143:86740a56073b 11689 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
AnnaBridge 143:86740a56073b 11690 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
AnnaBridge 143:86740a56073b 11691
AnnaBridge 143:86740a56073b 11692 /* Register: RTC_CC */
AnnaBridge 143:86740a56073b 11693 /* Description: Description collection[0]: Compare register 0 */
AnnaBridge 143:86740a56073b 11694
AnnaBridge 143:86740a56073b 11695 /* Bits 23..0 : Compare value */
AnnaBridge 143:86740a56073b 11696 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
AnnaBridge 143:86740a56073b 11697 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
AnnaBridge 143:86740a56073b 11698
AnnaBridge 143:86740a56073b 11699
AnnaBridge 143:86740a56073b 11700 /* Peripheral: SAADC */
AnnaBridge 143:86740a56073b 11701 /* Description: Analog to Digital Converter */
AnnaBridge 143:86740a56073b 11702
AnnaBridge 143:86740a56073b 11703 /* Register: SAADC_INTEN */
AnnaBridge 143:86740a56073b 11704 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 11705
AnnaBridge 143:86740a56073b 11706 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
AnnaBridge 143:86740a56073b 11707 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
AnnaBridge 143:86740a56073b 11708 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
AnnaBridge 143:86740a56073b 11709 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11710 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11711
AnnaBridge 143:86740a56073b 11712 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
AnnaBridge 143:86740a56073b 11713 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
AnnaBridge 143:86740a56073b 11714 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
AnnaBridge 143:86740a56073b 11715 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11716 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11717
AnnaBridge 143:86740a56073b 11718 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
AnnaBridge 143:86740a56073b 11719 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
AnnaBridge 143:86740a56073b 11720 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
AnnaBridge 143:86740a56073b 11721 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11722 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11723
AnnaBridge 143:86740a56073b 11724 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
AnnaBridge 143:86740a56073b 11725 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
AnnaBridge 143:86740a56073b 11726 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
AnnaBridge 143:86740a56073b 11727 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11728 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11729
AnnaBridge 143:86740a56073b 11730 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
AnnaBridge 143:86740a56073b 11731 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
AnnaBridge 143:86740a56073b 11732 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
AnnaBridge 143:86740a56073b 11733 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11734 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11735
AnnaBridge 143:86740a56073b 11736 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
AnnaBridge 143:86740a56073b 11737 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
AnnaBridge 143:86740a56073b 11738 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
AnnaBridge 143:86740a56073b 11739 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11740 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11741
AnnaBridge 143:86740a56073b 11742 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
AnnaBridge 143:86740a56073b 11743 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
AnnaBridge 143:86740a56073b 11744 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
AnnaBridge 143:86740a56073b 11745 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11746 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11747
AnnaBridge 143:86740a56073b 11748 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
AnnaBridge 143:86740a56073b 11749 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
AnnaBridge 143:86740a56073b 11750 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
AnnaBridge 143:86740a56073b 11751 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11752 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11753
AnnaBridge 143:86740a56073b 11754 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
AnnaBridge 143:86740a56073b 11755 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
AnnaBridge 143:86740a56073b 11756 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
AnnaBridge 143:86740a56073b 11757 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11758 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11759
AnnaBridge 143:86740a56073b 11760 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
AnnaBridge 143:86740a56073b 11761 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
AnnaBridge 143:86740a56073b 11762 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
AnnaBridge 143:86740a56073b 11763 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11764 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11765
AnnaBridge 143:86740a56073b 11766 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
AnnaBridge 143:86740a56073b 11767 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
AnnaBridge 143:86740a56073b 11768 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
AnnaBridge 143:86740a56073b 11769 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11770 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11771
AnnaBridge 143:86740a56073b 11772 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
AnnaBridge 143:86740a56073b 11773 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
AnnaBridge 143:86740a56073b 11774 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
AnnaBridge 143:86740a56073b 11775 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11776 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11777
AnnaBridge 143:86740a56073b 11778 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
AnnaBridge 143:86740a56073b 11779 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
AnnaBridge 143:86740a56073b 11780 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
AnnaBridge 143:86740a56073b 11781 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11782 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11783
AnnaBridge 143:86740a56073b 11784 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
AnnaBridge 143:86740a56073b 11785 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
AnnaBridge 143:86740a56073b 11786 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
AnnaBridge 143:86740a56073b 11787 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11788 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11789
AnnaBridge 143:86740a56073b 11790 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
AnnaBridge 143:86740a56073b 11791 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
AnnaBridge 143:86740a56073b 11792 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
AnnaBridge 143:86740a56073b 11793 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11794 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11795
AnnaBridge 143:86740a56073b 11796 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
AnnaBridge 143:86740a56073b 11797 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
AnnaBridge 143:86740a56073b 11798 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
AnnaBridge 143:86740a56073b 11799 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11800 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11801
AnnaBridge 143:86740a56073b 11802 /* Bit 5 : Enable or disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 11803 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 11804 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 11805 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11806 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11807
AnnaBridge 143:86740a56073b 11808 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
AnnaBridge 143:86740a56073b 11809 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
AnnaBridge 143:86740a56073b 11810 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
AnnaBridge 143:86740a56073b 11811 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11812 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11813
AnnaBridge 143:86740a56073b 11814 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
AnnaBridge 143:86740a56073b 11815 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
AnnaBridge 143:86740a56073b 11816 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
AnnaBridge 143:86740a56073b 11817 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11818 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11819
AnnaBridge 143:86740a56073b 11820 /* Bit 2 : Enable or disable interrupt for DONE event */
AnnaBridge 143:86740a56073b 11821 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
AnnaBridge 143:86740a56073b 11822 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
AnnaBridge 143:86740a56073b 11823 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11824 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11825
AnnaBridge 143:86740a56073b 11826 /* Bit 1 : Enable or disable interrupt for END event */
AnnaBridge 143:86740a56073b 11827 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 11828 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 11829 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11830 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11831
AnnaBridge 143:86740a56073b 11832 /* Bit 0 : Enable or disable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 11833 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 11834 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 11835 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 11836 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11837
AnnaBridge 143:86740a56073b 11838 /* Register: SAADC_INTENSET */
AnnaBridge 143:86740a56073b 11839 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 11840
AnnaBridge 143:86740a56073b 11841 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
AnnaBridge 143:86740a56073b 11842 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
AnnaBridge 143:86740a56073b 11843 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
AnnaBridge 143:86740a56073b 11844 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11845 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11846 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11847
AnnaBridge 143:86740a56073b 11848 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
AnnaBridge 143:86740a56073b 11849 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
AnnaBridge 143:86740a56073b 11850 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
AnnaBridge 143:86740a56073b 11851 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11852 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11853 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11854
AnnaBridge 143:86740a56073b 11855 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
AnnaBridge 143:86740a56073b 11856 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
AnnaBridge 143:86740a56073b 11857 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
AnnaBridge 143:86740a56073b 11858 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11859 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11860 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11861
AnnaBridge 143:86740a56073b 11862 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
AnnaBridge 143:86740a56073b 11863 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
AnnaBridge 143:86740a56073b 11864 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
AnnaBridge 143:86740a56073b 11865 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11866 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11867 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11868
AnnaBridge 143:86740a56073b 11869 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
AnnaBridge 143:86740a56073b 11870 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
AnnaBridge 143:86740a56073b 11871 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
AnnaBridge 143:86740a56073b 11872 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11873 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11874 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11875
AnnaBridge 143:86740a56073b 11876 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
AnnaBridge 143:86740a56073b 11877 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
AnnaBridge 143:86740a56073b 11878 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
AnnaBridge 143:86740a56073b 11879 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11880 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11881 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11882
AnnaBridge 143:86740a56073b 11883 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
AnnaBridge 143:86740a56073b 11884 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
AnnaBridge 143:86740a56073b 11885 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
AnnaBridge 143:86740a56073b 11886 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11887 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11888 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11889
AnnaBridge 143:86740a56073b 11890 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
AnnaBridge 143:86740a56073b 11891 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
AnnaBridge 143:86740a56073b 11892 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
AnnaBridge 143:86740a56073b 11893 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11894 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11895 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11896
AnnaBridge 143:86740a56073b 11897 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
AnnaBridge 143:86740a56073b 11898 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
AnnaBridge 143:86740a56073b 11899 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
AnnaBridge 143:86740a56073b 11900 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11901 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11902 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11903
AnnaBridge 143:86740a56073b 11904 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
AnnaBridge 143:86740a56073b 11905 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
AnnaBridge 143:86740a56073b 11906 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
AnnaBridge 143:86740a56073b 11907 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11908 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11909 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11910
AnnaBridge 143:86740a56073b 11911 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
AnnaBridge 143:86740a56073b 11912 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
AnnaBridge 143:86740a56073b 11913 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
AnnaBridge 143:86740a56073b 11914 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11915 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11916 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11917
AnnaBridge 143:86740a56073b 11918 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
AnnaBridge 143:86740a56073b 11919 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
AnnaBridge 143:86740a56073b 11920 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
AnnaBridge 143:86740a56073b 11921 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11922 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11923 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11924
AnnaBridge 143:86740a56073b 11925 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
AnnaBridge 143:86740a56073b 11926 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
AnnaBridge 143:86740a56073b 11927 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
AnnaBridge 143:86740a56073b 11928 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11929 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11930 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11931
AnnaBridge 143:86740a56073b 11932 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
AnnaBridge 143:86740a56073b 11933 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
AnnaBridge 143:86740a56073b 11934 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
AnnaBridge 143:86740a56073b 11935 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11936 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11937 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11938
AnnaBridge 143:86740a56073b 11939 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
AnnaBridge 143:86740a56073b 11940 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
AnnaBridge 143:86740a56073b 11941 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
AnnaBridge 143:86740a56073b 11942 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11943 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11944 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11945
AnnaBridge 143:86740a56073b 11946 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
AnnaBridge 143:86740a56073b 11947 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
AnnaBridge 143:86740a56073b 11948 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
AnnaBridge 143:86740a56073b 11949 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11950 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11951 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11952
AnnaBridge 143:86740a56073b 11953 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 11954 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 11955 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 11956 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11957 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11958 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11959
AnnaBridge 143:86740a56073b 11960 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
AnnaBridge 143:86740a56073b 11961 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
AnnaBridge 143:86740a56073b 11962 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
AnnaBridge 143:86740a56073b 11963 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11964 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11965 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11966
AnnaBridge 143:86740a56073b 11967 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
AnnaBridge 143:86740a56073b 11968 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
AnnaBridge 143:86740a56073b 11969 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
AnnaBridge 143:86740a56073b 11970 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11971 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11972 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11973
AnnaBridge 143:86740a56073b 11974 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
AnnaBridge 143:86740a56073b 11975 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
AnnaBridge 143:86740a56073b 11976 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
AnnaBridge 143:86740a56073b 11977 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11978 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11979 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11980
AnnaBridge 143:86740a56073b 11981 /* Bit 1 : Write '1' to Enable interrupt for END event */
AnnaBridge 143:86740a56073b 11982 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 11983 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 11984 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11985 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11986 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11987
AnnaBridge 143:86740a56073b 11988 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 11989 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 11990 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 11991 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 11992 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 11993 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 11994
AnnaBridge 143:86740a56073b 11995 /* Register: SAADC_INTENCLR */
AnnaBridge 143:86740a56073b 11996 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 11997
AnnaBridge 143:86740a56073b 11998 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
AnnaBridge 143:86740a56073b 11999 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
AnnaBridge 143:86740a56073b 12000 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
AnnaBridge 143:86740a56073b 12001 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12002 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12003 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12004
AnnaBridge 143:86740a56073b 12005 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
AnnaBridge 143:86740a56073b 12006 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
AnnaBridge 143:86740a56073b 12007 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
AnnaBridge 143:86740a56073b 12008 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12009 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12010 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12011
AnnaBridge 143:86740a56073b 12012 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
AnnaBridge 143:86740a56073b 12013 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
AnnaBridge 143:86740a56073b 12014 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
AnnaBridge 143:86740a56073b 12015 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12016 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12017 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12018
AnnaBridge 143:86740a56073b 12019 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
AnnaBridge 143:86740a56073b 12020 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
AnnaBridge 143:86740a56073b 12021 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
AnnaBridge 143:86740a56073b 12022 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12023 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12024 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12025
AnnaBridge 143:86740a56073b 12026 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
AnnaBridge 143:86740a56073b 12027 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
AnnaBridge 143:86740a56073b 12028 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
AnnaBridge 143:86740a56073b 12029 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12030 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12031 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12032
AnnaBridge 143:86740a56073b 12033 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
AnnaBridge 143:86740a56073b 12034 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
AnnaBridge 143:86740a56073b 12035 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
AnnaBridge 143:86740a56073b 12036 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12037 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12038 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12039
AnnaBridge 143:86740a56073b 12040 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
AnnaBridge 143:86740a56073b 12041 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
AnnaBridge 143:86740a56073b 12042 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
AnnaBridge 143:86740a56073b 12043 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12044 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12045 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12046
AnnaBridge 143:86740a56073b 12047 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
AnnaBridge 143:86740a56073b 12048 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
AnnaBridge 143:86740a56073b 12049 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
AnnaBridge 143:86740a56073b 12050 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12051 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12052 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12053
AnnaBridge 143:86740a56073b 12054 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
AnnaBridge 143:86740a56073b 12055 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
AnnaBridge 143:86740a56073b 12056 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
AnnaBridge 143:86740a56073b 12057 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12058 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12059 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12060
AnnaBridge 143:86740a56073b 12061 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
AnnaBridge 143:86740a56073b 12062 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
AnnaBridge 143:86740a56073b 12063 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
AnnaBridge 143:86740a56073b 12064 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12065 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12066 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12067
AnnaBridge 143:86740a56073b 12068 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
AnnaBridge 143:86740a56073b 12069 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
AnnaBridge 143:86740a56073b 12070 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
AnnaBridge 143:86740a56073b 12071 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12072 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12073 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12074
AnnaBridge 143:86740a56073b 12075 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
AnnaBridge 143:86740a56073b 12076 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
AnnaBridge 143:86740a56073b 12077 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
AnnaBridge 143:86740a56073b 12078 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12079 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12080 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12081
AnnaBridge 143:86740a56073b 12082 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
AnnaBridge 143:86740a56073b 12083 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
AnnaBridge 143:86740a56073b 12084 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
AnnaBridge 143:86740a56073b 12085 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12086 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12087 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12088
AnnaBridge 143:86740a56073b 12089 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
AnnaBridge 143:86740a56073b 12090 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
AnnaBridge 143:86740a56073b 12091 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
AnnaBridge 143:86740a56073b 12092 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12093 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12094 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12095
AnnaBridge 143:86740a56073b 12096 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
AnnaBridge 143:86740a56073b 12097 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
AnnaBridge 143:86740a56073b 12098 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
AnnaBridge 143:86740a56073b 12099 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12100 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12101 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12102
AnnaBridge 143:86740a56073b 12103 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
AnnaBridge 143:86740a56073b 12104 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
AnnaBridge 143:86740a56073b 12105 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
AnnaBridge 143:86740a56073b 12106 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12107 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12108 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12109
AnnaBridge 143:86740a56073b 12110 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 12111 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 12112 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 12113 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12114 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12115 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12116
AnnaBridge 143:86740a56073b 12117 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
AnnaBridge 143:86740a56073b 12118 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
AnnaBridge 143:86740a56073b 12119 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
AnnaBridge 143:86740a56073b 12120 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12121 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12122 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12123
AnnaBridge 143:86740a56073b 12124 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
AnnaBridge 143:86740a56073b 12125 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
AnnaBridge 143:86740a56073b 12126 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
AnnaBridge 143:86740a56073b 12127 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12128 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12129 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12130
AnnaBridge 143:86740a56073b 12131 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
AnnaBridge 143:86740a56073b 12132 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
AnnaBridge 143:86740a56073b 12133 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
AnnaBridge 143:86740a56073b 12134 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12135 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12136 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12137
AnnaBridge 143:86740a56073b 12138 /* Bit 1 : Write '1' to Disable interrupt for END event */
AnnaBridge 143:86740a56073b 12139 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 12140 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 12141 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12142 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12143 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12144
AnnaBridge 143:86740a56073b 12145 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 12146 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 12147 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 12148 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12149 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12150 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12151
AnnaBridge 143:86740a56073b 12152 /* Register: SAADC_STATUS */
AnnaBridge 143:86740a56073b 12153 /* Description: Status */
AnnaBridge 143:86740a56073b 12154
AnnaBridge 143:86740a56073b 12155 /* Bit 0 : Status */
AnnaBridge 143:86740a56073b 12156 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
AnnaBridge 143:86740a56073b 12157 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
AnnaBridge 143:86740a56073b 12158 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
AnnaBridge 143:86740a56073b 12159 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
AnnaBridge 143:86740a56073b 12160
AnnaBridge 143:86740a56073b 12161 /* Register: SAADC_ENABLE */
AnnaBridge 143:86740a56073b 12162 /* Description: Enable or disable ADC */
AnnaBridge 143:86740a56073b 12163
AnnaBridge 143:86740a56073b 12164 /* Bit 0 : Enable or disable ADC */
AnnaBridge 143:86740a56073b 12165 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 12166 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 12167 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
AnnaBridge 143:86740a56073b 12168 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
AnnaBridge 143:86740a56073b 12169
AnnaBridge 143:86740a56073b 12170 /* Register: SAADC_CH_PSELP */
AnnaBridge 143:86740a56073b 12171 /* Description: Description cluster[0]: Input positive pin selection for CH[0] */
AnnaBridge 143:86740a56073b 12172
AnnaBridge 143:86740a56073b 12173 /* Bits 4..0 : Analog positive input channel */
AnnaBridge 143:86740a56073b 12174 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
AnnaBridge 143:86740a56073b 12175 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
AnnaBridge 143:86740a56073b 12176 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
AnnaBridge 143:86740a56073b 12177 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
AnnaBridge 143:86740a56073b 12178 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
AnnaBridge 143:86740a56073b 12179 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
AnnaBridge 143:86740a56073b 12180 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
AnnaBridge 143:86740a56073b 12181 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
AnnaBridge 143:86740a56073b 12182 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
AnnaBridge 143:86740a56073b 12183 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
AnnaBridge 143:86740a56073b 12184 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
AnnaBridge 143:86740a56073b 12185 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
AnnaBridge 143:86740a56073b 12186
AnnaBridge 143:86740a56073b 12187 /* Register: SAADC_CH_PSELN */
AnnaBridge 143:86740a56073b 12188 /* Description: Description cluster[0]: Input negative pin selection for CH[0] */
AnnaBridge 143:86740a56073b 12189
AnnaBridge 143:86740a56073b 12190 /* Bits 4..0 : Analog negative input, enables differential channel */
AnnaBridge 143:86740a56073b 12191 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
AnnaBridge 143:86740a56073b 12192 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
AnnaBridge 143:86740a56073b 12193 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
AnnaBridge 143:86740a56073b 12194 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
AnnaBridge 143:86740a56073b 12195 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
AnnaBridge 143:86740a56073b 12196 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
AnnaBridge 143:86740a56073b 12197 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
AnnaBridge 143:86740a56073b 12198 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
AnnaBridge 143:86740a56073b 12199 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
AnnaBridge 143:86740a56073b 12200 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
AnnaBridge 143:86740a56073b 12201 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
AnnaBridge 143:86740a56073b 12202 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
AnnaBridge 143:86740a56073b 12203
AnnaBridge 143:86740a56073b 12204 /* Register: SAADC_CH_CONFIG */
AnnaBridge 143:86740a56073b 12205 /* Description: Description cluster[0]: Input configuration for CH[0] */
AnnaBridge 143:86740a56073b 12206
AnnaBridge 143:86740a56073b 12207 /* Bit 24 : Enable burst mode */
AnnaBridge 143:86740a56073b 12208 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
AnnaBridge 143:86740a56073b 12209 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
AnnaBridge 143:86740a56073b 12210 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
AnnaBridge 143:86740a56073b 12211 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
AnnaBridge 143:86740a56073b 12212
AnnaBridge 143:86740a56073b 12213 /* Bit 20 : Enable differential mode */
AnnaBridge 143:86740a56073b 12214 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 12215 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 12216 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
AnnaBridge 143:86740a56073b 12217 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
AnnaBridge 143:86740a56073b 12218
AnnaBridge 143:86740a56073b 12219 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
AnnaBridge 143:86740a56073b 12220 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
AnnaBridge 143:86740a56073b 12221 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
AnnaBridge 143:86740a56073b 12222 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
AnnaBridge 143:86740a56073b 12223 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
AnnaBridge 143:86740a56073b 12224 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
AnnaBridge 143:86740a56073b 12225 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
AnnaBridge 143:86740a56073b 12226 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
AnnaBridge 143:86740a56073b 12227 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
AnnaBridge 143:86740a56073b 12228
AnnaBridge 143:86740a56073b 12229 /* Bit 12 : Reference control */
AnnaBridge 143:86740a56073b 12230 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
AnnaBridge 143:86740a56073b 12231 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
AnnaBridge 143:86740a56073b 12232 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
AnnaBridge 143:86740a56073b 12233 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
AnnaBridge 143:86740a56073b 12234
AnnaBridge 143:86740a56073b 12235 /* Bits 10..8 : Gain control */
AnnaBridge 143:86740a56073b 12236 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
AnnaBridge 143:86740a56073b 12237 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
AnnaBridge 143:86740a56073b 12238 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
AnnaBridge 143:86740a56073b 12239 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
AnnaBridge 143:86740a56073b 12240 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
AnnaBridge 143:86740a56073b 12241 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
AnnaBridge 143:86740a56073b 12242 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
AnnaBridge 143:86740a56073b 12243 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
AnnaBridge 143:86740a56073b 12244 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
AnnaBridge 143:86740a56073b 12245 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
AnnaBridge 143:86740a56073b 12246
AnnaBridge 143:86740a56073b 12247 /* Bits 5..4 : Negative channel resistor control */
AnnaBridge 143:86740a56073b 12248 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
AnnaBridge 143:86740a56073b 12249 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
AnnaBridge 143:86740a56073b 12250 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
AnnaBridge 143:86740a56073b 12251 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
AnnaBridge 143:86740a56073b 12252 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
AnnaBridge 143:86740a56073b 12253 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
AnnaBridge 143:86740a56073b 12254
AnnaBridge 143:86740a56073b 12255 /* Bits 1..0 : Positive channel resistor control */
AnnaBridge 143:86740a56073b 12256 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
AnnaBridge 143:86740a56073b 12257 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
AnnaBridge 143:86740a56073b 12258 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
AnnaBridge 143:86740a56073b 12259 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
AnnaBridge 143:86740a56073b 12260 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
AnnaBridge 143:86740a56073b 12261 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
AnnaBridge 143:86740a56073b 12262
AnnaBridge 143:86740a56073b 12263 /* Register: SAADC_CH_LIMIT */
AnnaBridge 143:86740a56073b 12264 /* Description: Description cluster[0]: High/low limits for event monitoring a channel */
AnnaBridge 143:86740a56073b 12265
AnnaBridge 143:86740a56073b 12266 /* Bits 31..16 : High level limit */
AnnaBridge 143:86740a56073b 12267 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
AnnaBridge 143:86740a56073b 12268 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
AnnaBridge 143:86740a56073b 12269
AnnaBridge 143:86740a56073b 12270 /* Bits 15..0 : Low level limit */
AnnaBridge 143:86740a56073b 12271 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
AnnaBridge 143:86740a56073b 12272 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
AnnaBridge 143:86740a56073b 12273
AnnaBridge 143:86740a56073b 12274 /* Register: SAADC_RESOLUTION */
AnnaBridge 143:86740a56073b 12275 /* Description: Resolution configuration */
AnnaBridge 143:86740a56073b 12276
AnnaBridge 143:86740a56073b 12277 /* Bits 2..0 : Set the resolution */
AnnaBridge 143:86740a56073b 12278 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
AnnaBridge 143:86740a56073b 12279 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
AnnaBridge 143:86740a56073b 12280 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
AnnaBridge 143:86740a56073b 12281 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
AnnaBridge 143:86740a56073b 12282 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
AnnaBridge 143:86740a56073b 12283 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
AnnaBridge 143:86740a56073b 12284
AnnaBridge 143:86740a56073b 12285 /* Register: SAADC_OVERSAMPLE */
AnnaBridge 143:86740a56073b 12286 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
AnnaBridge 143:86740a56073b 12287
AnnaBridge 143:86740a56073b 12288 /* Bits 3..0 : Oversample control */
AnnaBridge 143:86740a56073b 12289 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
AnnaBridge 143:86740a56073b 12290 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
AnnaBridge 143:86740a56073b 12291 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
AnnaBridge 143:86740a56073b 12292 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
AnnaBridge 143:86740a56073b 12293 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
AnnaBridge 143:86740a56073b 12294 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
AnnaBridge 143:86740a56073b 12295 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
AnnaBridge 143:86740a56073b 12296 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
AnnaBridge 143:86740a56073b 12297 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
AnnaBridge 143:86740a56073b 12298 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
AnnaBridge 143:86740a56073b 12299 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
AnnaBridge 143:86740a56073b 12300
AnnaBridge 143:86740a56073b 12301 /* Register: SAADC_SAMPLERATE */
AnnaBridge 143:86740a56073b 12302 /* Description: Controls normal or continuous sample rate */
AnnaBridge 143:86740a56073b 12303
AnnaBridge 143:86740a56073b 12304 /* Bit 12 : Select mode for sample rate control */
AnnaBridge 143:86740a56073b 12305 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 12306 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 12307 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
AnnaBridge 143:86740a56073b 12308 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
AnnaBridge 143:86740a56073b 12309
AnnaBridge 143:86740a56073b 12310 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
AnnaBridge 143:86740a56073b 12311 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
AnnaBridge 143:86740a56073b 12312 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
AnnaBridge 143:86740a56073b 12313
AnnaBridge 143:86740a56073b 12314 /* Register: SAADC_RESULT_PTR */
AnnaBridge 143:86740a56073b 12315 /* Description: Data pointer */
AnnaBridge 143:86740a56073b 12316
AnnaBridge 143:86740a56073b 12317 /* Bits 31..0 : Data pointer */
AnnaBridge 143:86740a56073b 12318 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 12319 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 12320
AnnaBridge 143:86740a56073b 12321 /* Register: SAADC_RESULT_MAXCNT */
AnnaBridge 143:86740a56073b 12322 /* Description: Maximum number of buffer words to transfer */
AnnaBridge 143:86740a56073b 12323
AnnaBridge 143:86740a56073b 12324 /* Bits 14..0 : Maximum number of buffer words to transfer */
AnnaBridge 143:86740a56073b 12325 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 12326 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 12327
AnnaBridge 143:86740a56073b 12328 /* Register: SAADC_RESULT_AMOUNT */
AnnaBridge 143:86740a56073b 12329 /* Description: Number of buffer words transferred since last START */
AnnaBridge 143:86740a56073b 12330
AnnaBridge 143:86740a56073b 12331 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
AnnaBridge 143:86740a56073b 12332 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 12333 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 12334
AnnaBridge 143:86740a56073b 12335
AnnaBridge 143:86740a56073b 12336 /* Peripheral: SPI */
AnnaBridge 143:86740a56073b 12337 /* Description: Serial Peripheral Interface 0 */
AnnaBridge 143:86740a56073b 12338
AnnaBridge 143:86740a56073b 12339 /* Register: SPI_INTENSET */
AnnaBridge 143:86740a56073b 12340 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 12341
AnnaBridge 143:86740a56073b 12342 /* Bit 2 : Write '1' to Enable interrupt for READY event */
AnnaBridge 143:86740a56073b 12343 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 12344 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 12345 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12346 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12347 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12348
AnnaBridge 143:86740a56073b 12349 /* Register: SPI_INTENCLR */
AnnaBridge 143:86740a56073b 12350 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 12351
AnnaBridge 143:86740a56073b 12352 /* Bit 2 : Write '1' to Disable interrupt for READY event */
AnnaBridge 143:86740a56073b 12353 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 12354 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 12355 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12356 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12357 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12358
AnnaBridge 143:86740a56073b 12359 /* Register: SPI_ENABLE */
AnnaBridge 143:86740a56073b 12360 /* Description: Enable SPI */
AnnaBridge 143:86740a56073b 12361
AnnaBridge 143:86740a56073b 12362 /* Bits 3..0 : Enable or disable SPI */
AnnaBridge 143:86740a56073b 12363 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 12364 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 12365 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
AnnaBridge 143:86740a56073b 12366 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
AnnaBridge 143:86740a56073b 12367
AnnaBridge 143:86740a56073b 12368 /* Register: SPI_PSEL_SCK */
AnnaBridge 143:86740a56073b 12369 /* Description: Pin select for SCK */
AnnaBridge 143:86740a56073b 12370
AnnaBridge 143:86740a56073b 12371 /* Bits 31..0 : Pin number configuration for SPI SCK signal */
AnnaBridge 143:86740a56073b 12372 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
AnnaBridge 143:86740a56073b 12373 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
AnnaBridge 143:86740a56073b 12374 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12375
AnnaBridge 143:86740a56073b 12376 /* Register: SPI_PSEL_MOSI */
AnnaBridge 143:86740a56073b 12377 /* Description: Pin select for MOSI */
AnnaBridge 143:86740a56073b 12378
AnnaBridge 143:86740a56073b 12379 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */
AnnaBridge 143:86740a56073b 12380 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
AnnaBridge 143:86740a56073b 12381 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
AnnaBridge 143:86740a56073b 12382 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12383
AnnaBridge 143:86740a56073b 12384 /* Register: SPI_PSEL_MISO */
AnnaBridge 143:86740a56073b 12385 /* Description: Pin select for MISO */
AnnaBridge 143:86740a56073b 12386
AnnaBridge 143:86740a56073b 12387 /* Bits 31..0 : Pin number configuration for SPI MISO signal */
AnnaBridge 143:86740a56073b 12388 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
AnnaBridge 143:86740a56073b 12389 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
AnnaBridge 143:86740a56073b 12390 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12391
AnnaBridge 143:86740a56073b 12392 /* Register: SPI_RXD */
AnnaBridge 143:86740a56073b 12393 /* Description: RXD register */
AnnaBridge 143:86740a56073b 12394
AnnaBridge 143:86740a56073b 12395 /* Bits 7..0 : RX data received. Double buffered */
AnnaBridge 143:86740a56073b 12396 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
AnnaBridge 143:86740a56073b 12397 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
AnnaBridge 143:86740a56073b 12398
AnnaBridge 143:86740a56073b 12399 /* Register: SPI_TXD */
AnnaBridge 143:86740a56073b 12400 /* Description: TXD register */
AnnaBridge 143:86740a56073b 12401
AnnaBridge 143:86740a56073b 12402 /* Bits 7..0 : TX data to send. Double buffered */
AnnaBridge 143:86740a56073b 12403 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
AnnaBridge 143:86740a56073b 12404 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
AnnaBridge 143:86740a56073b 12405
AnnaBridge 143:86740a56073b 12406 /* Register: SPI_FREQUENCY */
AnnaBridge 143:86740a56073b 12407 /* Description: SPI frequency */
AnnaBridge 143:86740a56073b 12408
AnnaBridge 143:86740a56073b 12409 /* Bits 31..0 : SPI master data rate */
AnnaBridge 143:86740a56073b 12410 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 12411 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 12412 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
AnnaBridge 143:86740a56073b 12413 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
AnnaBridge 143:86740a56073b 12414 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
AnnaBridge 143:86740a56073b 12415 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
AnnaBridge 143:86740a56073b 12416 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
AnnaBridge 143:86740a56073b 12417 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
AnnaBridge 143:86740a56073b 12418 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
AnnaBridge 143:86740a56073b 12419
AnnaBridge 143:86740a56073b 12420 /* Register: SPI_CONFIG */
AnnaBridge 143:86740a56073b 12421 /* Description: Configuration register */
AnnaBridge 143:86740a56073b 12422
AnnaBridge 143:86740a56073b 12423 /* Bit 2 : Serial clock (SCK) polarity */
AnnaBridge 143:86740a56073b 12424 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
AnnaBridge 143:86740a56073b 12425 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
AnnaBridge 143:86740a56073b 12426 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
AnnaBridge 143:86740a56073b 12427 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
AnnaBridge 143:86740a56073b 12428
AnnaBridge 143:86740a56073b 12429 /* Bit 1 : Serial clock (SCK) phase */
AnnaBridge 143:86740a56073b 12430 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
AnnaBridge 143:86740a56073b 12431 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
AnnaBridge 143:86740a56073b 12432 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
AnnaBridge 143:86740a56073b 12433 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
AnnaBridge 143:86740a56073b 12434
AnnaBridge 143:86740a56073b 12435 /* Bit 0 : Bit order */
AnnaBridge 143:86740a56073b 12436 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
AnnaBridge 143:86740a56073b 12437 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
AnnaBridge 143:86740a56073b 12438 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
AnnaBridge 143:86740a56073b 12439 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
AnnaBridge 143:86740a56073b 12440
AnnaBridge 143:86740a56073b 12441
AnnaBridge 143:86740a56073b 12442 /* Peripheral: SPIM */
AnnaBridge 143:86740a56073b 12443 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
AnnaBridge 143:86740a56073b 12444
AnnaBridge 143:86740a56073b 12445 /* Register: SPIM_SHORTS */
AnnaBridge 143:86740a56073b 12446 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 12447
AnnaBridge 143:86740a56073b 12448 /* Bit 17 : Shortcut between END event and START task */
AnnaBridge 143:86740a56073b 12449 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
AnnaBridge 143:86740a56073b 12450 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
AnnaBridge 143:86740a56073b 12451 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 12452 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 12453
AnnaBridge 143:86740a56073b 12454 /* Register: SPIM_INTENSET */
AnnaBridge 143:86740a56073b 12455 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 12456
AnnaBridge 143:86740a56073b 12457 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 12458 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 12459 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 12460 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12461 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12462 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12463
AnnaBridge 143:86740a56073b 12464 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 12465 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 12466 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 12467 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12468 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12469 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12470
AnnaBridge 143:86740a56073b 12471 /* Bit 6 : Write '1' to Enable interrupt for END event */
AnnaBridge 143:86740a56073b 12472 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 12473 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 12474 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12475 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12476 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12477
AnnaBridge 143:86740a56073b 12478 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 12479 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 12480 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 12481 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12482 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12483 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12484
AnnaBridge 143:86740a56073b 12485 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 12486 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 12487 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 12488 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12489 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12490 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12491
AnnaBridge 143:86740a56073b 12492 /* Register: SPIM_INTENCLR */
AnnaBridge 143:86740a56073b 12493 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 12494
AnnaBridge 143:86740a56073b 12495 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
AnnaBridge 143:86740a56073b 12496 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 12497 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 12498 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12499 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12500 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12501
AnnaBridge 143:86740a56073b 12502 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 12503 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 12504 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 12505 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12506 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12507 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12508
AnnaBridge 143:86740a56073b 12509 /* Bit 6 : Write '1' to Disable interrupt for END event */
AnnaBridge 143:86740a56073b 12510 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 12511 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 12512 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12513 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12514 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12515
AnnaBridge 143:86740a56073b 12516 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 12517 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 12518 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 12519 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12520 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12521 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12522
AnnaBridge 143:86740a56073b 12523 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 12524 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 12525 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 12526 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12527 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12528 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12529
AnnaBridge 143:86740a56073b 12530 /* Register: SPIM_ENABLE */
AnnaBridge 143:86740a56073b 12531 /* Description: Enable SPIM */
AnnaBridge 143:86740a56073b 12532
AnnaBridge 143:86740a56073b 12533 /* Bits 3..0 : Enable or disable SPIM */
AnnaBridge 143:86740a56073b 12534 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 12535 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 12536 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
AnnaBridge 143:86740a56073b 12537 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
AnnaBridge 143:86740a56073b 12538
AnnaBridge 143:86740a56073b 12539 /* Register: SPIM_PSEL_SCK */
AnnaBridge 143:86740a56073b 12540 /* Description: Pin select for SCK */
AnnaBridge 143:86740a56073b 12541
AnnaBridge 143:86740a56073b 12542 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 12543 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 12544 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 12545 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 12546 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12547
AnnaBridge 143:86740a56073b 12548 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 12549 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 12550 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 12551
AnnaBridge 143:86740a56073b 12552 /* Register: SPIM_PSEL_MOSI */
AnnaBridge 143:86740a56073b 12553 /* Description: Pin select for MOSI signal */
AnnaBridge 143:86740a56073b 12554
AnnaBridge 143:86740a56073b 12555 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 12556 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 12557 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 12558 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 12559 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12560
AnnaBridge 143:86740a56073b 12561 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 12562 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 12563 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 12564
AnnaBridge 143:86740a56073b 12565 /* Register: SPIM_PSEL_MISO */
AnnaBridge 143:86740a56073b 12566 /* Description: Pin select for MISO signal */
AnnaBridge 143:86740a56073b 12567
AnnaBridge 143:86740a56073b 12568 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 12569 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 12570 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 12571 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 12572 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12573
AnnaBridge 143:86740a56073b 12574 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 12575 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 12576 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 12577
AnnaBridge 143:86740a56073b 12578 /* Register: SPIM_FREQUENCY */
AnnaBridge 143:86740a56073b 12579 /* Description: SPI frequency */
AnnaBridge 143:86740a56073b 12580
AnnaBridge 143:86740a56073b 12581 /* Bits 31..0 : SPI master data rate */
AnnaBridge 143:86740a56073b 12582 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 12583 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 12584 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
AnnaBridge 143:86740a56073b 12585 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
AnnaBridge 143:86740a56073b 12586 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
AnnaBridge 143:86740a56073b 12587 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
AnnaBridge 143:86740a56073b 12588 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
AnnaBridge 143:86740a56073b 12589 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
AnnaBridge 143:86740a56073b 12590 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
AnnaBridge 143:86740a56073b 12591
AnnaBridge 143:86740a56073b 12592 /* Register: SPIM_RXD_PTR */
AnnaBridge 143:86740a56073b 12593 /* Description: Data pointer */
AnnaBridge 143:86740a56073b 12594
AnnaBridge 143:86740a56073b 12595 /* Bits 31..0 : Data pointer */
AnnaBridge 143:86740a56073b 12596 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 12597 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 12598
AnnaBridge 143:86740a56073b 12599 /* Register: SPIM_RXD_MAXCNT */
AnnaBridge 143:86740a56073b 12600 /* Description: Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 12601
AnnaBridge 143:86740a56073b 12602 /* Bits 7..0 : Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 12603 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 12604 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 12605
AnnaBridge 143:86740a56073b 12606 /* Register: SPIM_RXD_AMOUNT */
AnnaBridge 143:86740a56073b 12607 /* Description: Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 12608
AnnaBridge 143:86740a56073b 12609 /* Bits 7..0 : Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 12610 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 12611 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 12612
AnnaBridge 143:86740a56073b 12613 /* Register: SPIM_RXD_LIST */
AnnaBridge 143:86740a56073b 12614 /* Description: EasyDMA list type */
AnnaBridge 143:86740a56073b 12615
AnnaBridge 143:86740a56073b 12616 /* Bits 2..0 : List type */
AnnaBridge 143:86740a56073b 12617 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
AnnaBridge 143:86740a56073b 12618 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
AnnaBridge 143:86740a56073b 12619 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
AnnaBridge 143:86740a56073b 12620 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
AnnaBridge 143:86740a56073b 12621
AnnaBridge 143:86740a56073b 12622 /* Register: SPIM_TXD_PTR */
AnnaBridge 143:86740a56073b 12623 /* Description: Data pointer */
AnnaBridge 143:86740a56073b 12624
AnnaBridge 143:86740a56073b 12625 /* Bits 31..0 : Data pointer */
AnnaBridge 143:86740a56073b 12626 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 12627 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 12628
AnnaBridge 143:86740a56073b 12629 /* Register: SPIM_TXD_MAXCNT */
AnnaBridge 143:86740a56073b 12630 /* Description: Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 12631
AnnaBridge 143:86740a56073b 12632 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 12633 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 12634 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 12635
AnnaBridge 143:86740a56073b 12636 /* Register: SPIM_TXD_AMOUNT */
AnnaBridge 143:86740a56073b 12637 /* Description: Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 12638
AnnaBridge 143:86740a56073b 12639 /* Bits 7..0 : Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 12640 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 12641 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 12642
AnnaBridge 143:86740a56073b 12643 /* Register: SPIM_TXD_LIST */
AnnaBridge 143:86740a56073b 12644 /* Description: EasyDMA list type */
AnnaBridge 143:86740a56073b 12645
AnnaBridge 143:86740a56073b 12646 /* Bits 2..0 : List type */
AnnaBridge 143:86740a56073b 12647 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
AnnaBridge 143:86740a56073b 12648 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
AnnaBridge 143:86740a56073b 12649 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
AnnaBridge 143:86740a56073b 12650 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
AnnaBridge 143:86740a56073b 12651
AnnaBridge 143:86740a56073b 12652 /* Register: SPIM_CONFIG */
AnnaBridge 143:86740a56073b 12653 /* Description: Configuration register */
AnnaBridge 143:86740a56073b 12654
AnnaBridge 143:86740a56073b 12655 /* Bit 2 : Serial clock (SCK) polarity */
AnnaBridge 143:86740a56073b 12656 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
AnnaBridge 143:86740a56073b 12657 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
AnnaBridge 143:86740a56073b 12658 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
AnnaBridge 143:86740a56073b 12659 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
AnnaBridge 143:86740a56073b 12660
AnnaBridge 143:86740a56073b 12661 /* Bit 1 : Serial clock (SCK) phase */
AnnaBridge 143:86740a56073b 12662 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
AnnaBridge 143:86740a56073b 12663 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
AnnaBridge 143:86740a56073b 12664 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
AnnaBridge 143:86740a56073b 12665 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
AnnaBridge 143:86740a56073b 12666
AnnaBridge 143:86740a56073b 12667 /* Bit 0 : Bit order */
AnnaBridge 143:86740a56073b 12668 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
AnnaBridge 143:86740a56073b 12669 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
AnnaBridge 143:86740a56073b 12670 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
AnnaBridge 143:86740a56073b 12671 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
AnnaBridge 143:86740a56073b 12672
AnnaBridge 143:86740a56073b 12673 /* Register: SPIM_ORC */
AnnaBridge 143:86740a56073b 12674 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
AnnaBridge 143:86740a56073b 12675
AnnaBridge 143:86740a56073b 12676 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
AnnaBridge 143:86740a56073b 12677 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
AnnaBridge 143:86740a56073b 12678 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
AnnaBridge 143:86740a56073b 12679
AnnaBridge 143:86740a56073b 12680
AnnaBridge 143:86740a56073b 12681 /* Peripheral: SPIS */
AnnaBridge 143:86740a56073b 12682 /* Description: SPI Slave 0 */
AnnaBridge 143:86740a56073b 12683
AnnaBridge 143:86740a56073b 12684 /* Register: SPIS_SHORTS */
AnnaBridge 143:86740a56073b 12685 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 12686
AnnaBridge 143:86740a56073b 12687 /* Bit 2 : Shortcut between END event and ACQUIRE task */
AnnaBridge 143:86740a56073b 12688 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
AnnaBridge 143:86740a56073b 12689 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
AnnaBridge 143:86740a56073b 12690 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 12691 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 12692
AnnaBridge 143:86740a56073b 12693 /* Register: SPIS_INTENSET */
AnnaBridge 143:86740a56073b 12694 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 12695
AnnaBridge 143:86740a56073b 12696 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
AnnaBridge 143:86740a56073b 12697 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
AnnaBridge 143:86740a56073b 12698 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
AnnaBridge 143:86740a56073b 12699 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12700 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12701 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12702
AnnaBridge 143:86740a56073b 12703 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 12704 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 12705 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 12706 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12707 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12708 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12709
AnnaBridge 143:86740a56073b 12710 /* Bit 1 : Write '1' to Enable interrupt for END event */
AnnaBridge 143:86740a56073b 12711 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 12712 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 12713 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12714 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12715 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12716
AnnaBridge 143:86740a56073b 12717 /* Register: SPIS_INTENCLR */
AnnaBridge 143:86740a56073b 12718 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 12719
AnnaBridge 143:86740a56073b 12720 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
AnnaBridge 143:86740a56073b 12721 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
AnnaBridge 143:86740a56073b 12722 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
AnnaBridge 143:86740a56073b 12723 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12724 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12725 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12726
AnnaBridge 143:86740a56073b 12727 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 12728 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 12729 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 12730 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12731 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12732 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12733
AnnaBridge 143:86740a56073b 12734 /* Bit 1 : Write '1' to Disable interrupt for END event */
AnnaBridge 143:86740a56073b 12735 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 12736 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 12737 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12738 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12739 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12740
AnnaBridge 143:86740a56073b 12741 /* Register: SPIS_SEMSTAT */
AnnaBridge 143:86740a56073b 12742 /* Description: Semaphore status register */
AnnaBridge 143:86740a56073b 12743
AnnaBridge 143:86740a56073b 12744 /* Bits 1..0 : Semaphore status */
AnnaBridge 143:86740a56073b 12745 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
AnnaBridge 143:86740a56073b 12746 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
AnnaBridge 143:86740a56073b 12747 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
AnnaBridge 143:86740a56073b 12748 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
AnnaBridge 143:86740a56073b 12749 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
AnnaBridge 143:86740a56073b 12750 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
AnnaBridge 143:86740a56073b 12751
AnnaBridge 143:86740a56073b 12752 /* Register: SPIS_STATUS */
AnnaBridge 143:86740a56073b 12753 /* Description: Status from last transaction */
AnnaBridge 143:86740a56073b 12754
AnnaBridge 143:86740a56073b 12755 /* Bit 1 : RX buffer overflow detected, and prevented */
AnnaBridge 143:86740a56073b 12756 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
AnnaBridge 143:86740a56073b 12757 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
AnnaBridge 143:86740a56073b 12758 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 12759 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 12760 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
AnnaBridge 143:86740a56073b 12761
AnnaBridge 143:86740a56073b 12762 /* Bit 0 : TX buffer over-read detected, and prevented */
AnnaBridge 143:86740a56073b 12763 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
AnnaBridge 143:86740a56073b 12764 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
AnnaBridge 143:86740a56073b 12765 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 12766 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 12767 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
AnnaBridge 143:86740a56073b 12768
AnnaBridge 143:86740a56073b 12769 /* Register: SPIS_ENABLE */
AnnaBridge 143:86740a56073b 12770 /* Description: Enable SPI slave */
AnnaBridge 143:86740a56073b 12771
AnnaBridge 143:86740a56073b 12772 /* Bits 3..0 : Enable or disable SPI slave */
AnnaBridge 143:86740a56073b 12773 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 12774 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 12775 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
AnnaBridge 143:86740a56073b 12776 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
AnnaBridge 143:86740a56073b 12777
AnnaBridge 143:86740a56073b 12778 /* Register: SPIS_PSEL_SCK */
AnnaBridge 143:86740a56073b 12779 /* Description: Pin select for SCK */
AnnaBridge 143:86740a56073b 12780
AnnaBridge 143:86740a56073b 12781 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 12782 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 12783 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 12784 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 12785 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12786
AnnaBridge 143:86740a56073b 12787 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 12788 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 12789 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 12790
AnnaBridge 143:86740a56073b 12791 /* Register: SPIS_PSEL_MISO */
AnnaBridge 143:86740a56073b 12792 /* Description: Pin select for MISO signal */
AnnaBridge 143:86740a56073b 12793
AnnaBridge 143:86740a56073b 12794 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 12795 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 12796 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 12797 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 12798 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12799
AnnaBridge 143:86740a56073b 12800 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 12801 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 12802 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 12803
AnnaBridge 143:86740a56073b 12804 /* Register: SPIS_PSEL_MOSI */
AnnaBridge 143:86740a56073b 12805 /* Description: Pin select for MOSI signal */
AnnaBridge 143:86740a56073b 12806
AnnaBridge 143:86740a56073b 12807 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 12808 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 12809 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 12810 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 12811 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12812
AnnaBridge 143:86740a56073b 12813 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 12814 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 12815 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 12816
AnnaBridge 143:86740a56073b 12817 /* Register: SPIS_PSEL_CSN */
AnnaBridge 143:86740a56073b 12818 /* Description: Pin select for CSN signal */
AnnaBridge 143:86740a56073b 12819
AnnaBridge 143:86740a56073b 12820 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 12821 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 12822 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 12823 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 12824 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 12825
AnnaBridge 143:86740a56073b 12826 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 12827 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 12828 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 12829
AnnaBridge 143:86740a56073b 12830 /* Register: SPIS_RXD_PTR */
AnnaBridge 143:86740a56073b 12831 /* Description: RXD data pointer */
AnnaBridge 143:86740a56073b 12832
AnnaBridge 143:86740a56073b 12833 /* Bits 31..0 : RXD data pointer */
AnnaBridge 143:86740a56073b 12834 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 12835 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 12836
AnnaBridge 143:86740a56073b 12837 /* Register: SPIS_RXD_MAXCNT */
AnnaBridge 143:86740a56073b 12838 /* Description: Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 12839
AnnaBridge 143:86740a56073b 12840 /* Bits 7..0 : Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 12841 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 12842 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 12843
AnnaBridge 143:86740a56073b 12844 /* Register: SPIS_RXD_AMOUNT */
AnnaBridge 143:86740a56073b 12845 /* Description: Number of bytes received in last granted transaction */
AnnaBridge 143:86740a56073b 12846
AnnaBridge 143:86740a56073b 12847 /* Bits 7..0 : Number of bytes received in the last granted transaction */
AnnaBridge 143:86740a56073b 12848 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 12849 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 12850
AnnaBridge 143:86740a56073b 12851 /* Register: SPIS_TXD_PTR */
AnnaBridge 143:86740a56073b 12852 /* Description: TXD data pointer */
AnnaBridge 143:86740a56073b 12853
AnnaBridge 143:86740a56073b 12854 /* Bits 31..0 : TXD data pointer */
AnnaBridge 143:86740a56073b 12855 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 12856 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 12857
AnnaBridge 143:86740a56073b 12858 /* Register: SPIS_TXD_MAXCNT */
AnnaBridge 143:86740a56073b 12859 /* Description: Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 12860
AnnaBridge 143:86740a56073b 12861 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 12862 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 12863 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 12864
AnnaBridge 143:86740a56073b 12865 /* Register: SPIS_TXD_AMOUNT */
AnnaBridge 143:86740a56073b 12866 /* Description: Number of bytes transmitted in last granted transaction */
AnnaBridge 143:86740a56073b 12867
AnnaBridge 143:86740a56073b 12868 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */
AnnaBridge 143:86740a56073b 12869 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 12870 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 12871
AnnaBridge 143:86740a56073b 12872 /* Register: SPIS_CONFIG */
AnnaBridge 143:86740a56073b 12873 /* Description: Configuration register */
AnnaBridge 143:86740a56073b 12874
AnnaBridge 143:86740a56073b 12875 /* Bit 2 : Serial clock (SCK) polarity */
AnnaBridge 143:86740a56073b 12876 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
AnnaBridge 143:86740a56073b 12877 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
AnnaBridge 143:86740a56073b 12878 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
AnnaBridge 143:86740a56073b 12879 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
AnnaBridge 143:86740a56073b 12880
AnnaBridge 143:86740a56073b 12881 /* Bit 1 : Serial clock (SCK) phase */
AnnaBridge 143:86740a56073b 12882 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
AnnaBridge 143:86740a56073b 12883 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
AnnaBridge 143:86740a56073b 12884 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
AnnaBridge 143:86740a56073b 12885 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
AnnaBridge 143:86740a56073b 12886
AnnaBridge 143:86740a56073b 12887 /* Bit 0 : Bit order */
AnnaBridge 143:86740a56073b 12888 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
AnnaBridge 143:86740a56073b 12889 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
AnnaBridge 143:86740a56073b 12890 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
AnnaBridge 143:86740a56073b 12891 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
AnnaBridge 143:86740a56073b 12892
AnnaBridge 143:86740a56073b 12893 /* Register: SPIS_DEF */
AnnaBridge 143:86740a56073b 12894 /* Description: Default character. Character clocked out in case of an ignored transaction. */
AnnaBridge 143:86740a56073b 12895
AnnaBridge 143:86740a56073b 12896 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
AnnaBridge 143:86740a56073b 12897 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
AnnaBridge 143:86740a56073b 12898 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
AnnaBridge 143:86740a56073b 12899
AnnaBridge 143:86740a56073b 12900 /* Register: SPIS_ORC */
AnnaBridge 143:86740a56073b 12901 /* Description: Over-read character */
AnnaBridge 143:86740a56073b 12902
AnnaBridge 143:86740a56073b 12903 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
AnnaBridge 143:86740a56073b 12904 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
AnnaBridge 143:86740a56073b 12905 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
AnnaBridge 143:86740a56073b 12906
AnnaBridge 143:86740a56073b 12907
AnnaBridge 143:86740a56073b 12908 /* Peripheral: TEMP */
AnnaBridge 143:86740a56073b 12909 /* Description: Temperature Sensor */
AnnaBridge 143:86740a56073b 12910
AnnaBridge 143:86740a56073b 12911 /* Register: TEMP_INTENSET */
AnnaBridge 143:86740a56073b 12912 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 12913
AnnaBridge 143:86740a56073b 12914 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
AnnaBridge 143:86740a56073b 12915 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
AnnaBridge 143:86740a56073b 12916 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
AnnaBridge 143:86740a56073b 12917 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12918 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12919 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 12920
AnnaBridge 143:86740a56073b 12921 /* Register: TEMP_INTENCLR */
AnnaBridge 143:86740a56073b 12922 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 12923
AnnaBridge 143:86740a56073b 12924 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
AnnaBridge 143:86740a56073b 12925 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
AnnaBridge 143:86740a56073b 12926 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
AnnaBridge 143:86740a56073b 12927 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 12928 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 12929 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 12930
AnnaBridge 143:86740a56073b 12931 /* Register: TEMP_TEMP */
AnnaBridge 143:86740a56073b 12932 /* Description: Temperature in degC (0.25deg steps) */
AnnaBridge 143:86740a56073b 12933
AnnaBridge 143:86740a56073b 12934 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
AnnaBridge 143:86740a56073b 12935 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
AnnaBridge 143:86740a56073b 12936 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
AnnaBridge 143:86740a56073b 12937
AnnaBridge 143:86740a56073b 12938 /* Register: TEMP_A0 */
AnnaBridge 143:86740a56073b 12939 /* Description: Slope of 1st piece wise linear function */
AnnaBridge 143:86740a56073b 12940
AnnaBridge 143:86740a56073b 12941 /* Bits 11..0 : Slope of 1st piece wise linear function */
AnnaBridge 143:86740a56073b 12942 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
AnnaBridge 143:86740a56073b 12943 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
AnnaBridge 143:86740a56073b 12944
AnnaBridge 143:86740a56073b 12945 /* Register: TEMP_A1 */
AnnaBridge 143:86740a56073b 12946 /* Description: Slope of 2nd piece wise linear function */
AnnaBridge 143:86740a56073b 12947
AnnaBridge 143:86740a56073b 12948 /* Bits 11..0 : Slope of 2nd piece wise linear function */
AnnaBridge 143:86740a56073b 12949 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
AnnaBridge 143:86740a56073b 12950 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
AnnaBridge 143:86740a56073b 12951
AnnaBridge 143:86740a56073b 12952 /* Register: TEMP_A2 */
AnnaBridge 143:86740a56073b 12953 /* Description: Slope of 3rd piece wise linear function */
AnnaBridge 143:86740a56073b 12954
AnnaBridge 143:86740a56073b 12955 /* Bits 11..0 : Slope of 3rd piece wise linear function */
AnnaBridge 143:86740a56073b 12956 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
AnnaBridge 143:86740a56073b 12957 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
AnnaBridge 143:86740a56073b 12958
AnnaBridge 143:86740a56073b 12959 /* Register: TEMP_A3 */
AnnaBridge 143:86740a56073b 12960 /* Description: Slope of 4th piece wise linear function */
AnnaBridge 143:86740a56073b 12961
AnnaBridge 143:86740a56073b 12962 /* Bits 11..0 : Slope of 4th piece wise linear function */
AnnaBridge 143:86740a56073b 12963 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
AnnaBridge 143:86740a56073b 12964 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
AnnaBridge 143:86740a56073b 12965
AnnaBridge 143:86740a56073b 12966 /* Register: TEMP_A4 */
AnnaBridge 143:86740a56073b 12967 /* Description: Slope of 5th piece wise linear function */
AnnaBridge 143:86740a56073b 12968
AnnaBridge 143:86740a56073b 12969 /* Bits 11..0 : Slope of 5th piece wise linear function */
AnnaBridge 143:86740a56073b 12970 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
AnnaBridge 143:86740a56073b 12971 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
AnnaBridge 143:86740a56073b 12972
AnnaBridge 143:86740a56073b 12973 /* Register: TEMP_A5 */
AnnaBridge 143:86740a56073b 12974 /* Description: Slope of 6th piece wise linear function */
AnnaBridge 143:86740a56073b 12975
AnnaBridge 143:86740a56073b 12976 /* Bits 11..0 : Slope of 6th piece wise linear function */
AnnaBridge 143:86740a56073b 12977 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
AnnaBridge 143:86740a56073b 12978 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
AnnaBridge 143:86740a56073b 12979
AnnaBridge 143:86740a56073b 12980 /* Register: TEMP_B0 */
AnnaBridge 143:86740a56073b 12981 /* Description: y-intercept of 1st piece wise linear function */
AnnaBridge 143:86740a56073b 12982
AnnaBridge 143:86740a56073b 12983 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
AnnaBridge 143:86740a56073b 12984 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
AnnaBridge 143:86740a56073b 12985 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
AnnaBridge 143:86740a56073b 12986
AnnaBridge 143:86740a56073b 12987 /* Register: TEMP_B1 */
AnnaBridge 143:86740a56073b 12988 /* Description: y-intercept of 2nd piece wise linear function */
AnnaBridge 143:86740a56073b 12989
AnnaBridge 143:86740a56073b 12990 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
AnnaBridge 143:86740a56073b 12991 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
AnnaBridge 143:86740a56073b 12992 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
AnnaBridge 143:86740a56073b 12993
AnnaBridge 143:86740a56073b 12994 /* Register: TEMP_B2 */
AnnaBridge 143:86740a56073b 12995 /* Description: y-intercept of 3rd piece wise linear function */
AnnaBridge 143:86740a56073b 12996
AnnaBridge 143:86740a56073b 12997 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
AnnaBridge 143:86740a56073b 12998 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
AnnaBridge 143:86740a56073b 12999 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
AnnaBridge 143:86740a56073b 13000
AnnaBridge 143:86740a56073b 13001 /* Register: TEMP_B3 */
AnnaBridge 143:86740a56073b 13002 /* Description: y-intercept of 4th piece wise linear function */
AnnaBridge 143:86740a56073b 13003
AnnaBridge 143:86740a56073b 13004 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
AnnaBridge 143:86740a56073b 13005 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
AnnaBridge 143:86740a56073b 13006 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
AnnaBridge 143:86740a56073b 13007
AnnaBridge 143:86740a56073b 13008 /* Register: TEMP_B4 */
AnnaBridge 143:86740a56073b 13009 /* Description: y-intercept of 5th piece wise linear function */
AnnaBridge 143:86740a56073b 13010
AnnaBridge 143:86740a56073b 13011 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
AnnaBridge 143:86740a56073b 13012 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
AnnaBridge 143:86740a56073b 13013 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
AnnaBridge 143:86740a56073b 13014
AnnaBridge 143:86740a56073b 13015 /* Register: TEMP_B5 */
AnnaBridge 143:86740a56073b 13016 /* Description: y-intercept of 6th piece wise linear function */
AnnaBridge 143:86740a56073b 13017
AnnaBridge 143:86740a56073b 13018 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
AnnaBridge 143:86740a56073b 13019 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
AnnaBridge 143:86740a56073b 13020 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
AnnaBridge 143:86740a56073b 13021
AnnaBridge 143:86740a56073b 13022 /* Register: TEMP_T0 */
AnnaBridge 143:86740a56073b 13023 /* Description: End point of 1st piece wise linear function */
AnnaBridge 143:86740a56073b 13024
AnnaBridge 143:86740a56073b 13025 /* Bits 7..0 : End point of 1st piece wise linear function */
AnnaBridge 143:86740a56073b 13026 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
AnnaBridge 143:86740a56073b 13027 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
AnnaBridge 143:86740a56073b 13028
AnnaBridge 143:86740a56073b 13029 /* Register: TEMP_T1 */
AnnaBridge 143:86740a56073b 13030 /* Description: End point of 2nd piece wise linear function */
AnnaBridge 143:86740a56073b 13031
AnnaBridge 143:86740a56073b 13032 /* Bits 7..0 : End point of 2nd piece wise linear function */
AnnaBridge 143:86740a56073b 13033 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
AnnaBridge 143:86740a56073b 13034 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
AnnaBridge 143:86740a56073b 13035
AnnaBridge 143:86740a56073b 13036 /* Register: TEMP_T2 */
AnnaBridge 143:86740a56073b 13037 /* Description: End point of 3rd piece wise linear function */
AnnaBridge 143:86740a56073b 13038
AnnaBridge 143:86740a56073b 13039 /* Bits 7..0 : End point of 3rd piece wise linear function */
AnnaBridge 143:86740a56073b 13040 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
AnnaBridge 143:86740a56073b 13041 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
AnnaBridge 143:86740a56073b 13042
AnnaBridge 143:86740a56073b 13043 /* Register: TEMP_T3 */
AnnaBridge 143:86740a56073b 13044 /* Description: End point of 4th piece wise linear function */
AnnaBridge 143:86740a56073b 13045
AnnaBridge 143:86740a56073b 13046 /* Bits 7..0 : End point of 4th piece wise linear function */
AnnaBridge 143:86740a56073b 13047 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
AnnaBridge 143:86740a56073b 13048 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
AnnaBridge 143:86740a56073b 13049
AnnaBridge 143:86740a56073b 13050 /* Register: TEMP_T4 */
AnnaBridge 143:86740a56073b 13051 /* Description: End point of 5th piece wise linear function */
AnnaBridge 143:86740a56073b 13052
AnnaBridge 143:86740a56073b 13053 /* Bits 7..0 : End point of 5th piece wise linear function */
AnnaBridge 143:86740a56073b 13054 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
AnnaBridge 143:86740a56073b 13055 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
AnnaBridge 143:86740a56073b 13056
AnnaBridge 143:86740a56073b 13057
AnnaBridge 143:86740a56073b 13058 /* Peripheral: TIMER */
AnnaBridge 143:86740a56073b 13059 /* Description: Timer/Counter 0 */
AnnaBridge 143:86740a56073b 13060
AnnaBridge 143:86740a56073b 13061 /* Register: TIMER_SHORTS */
AnnaBridge 143:86740a56073b 13062 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 13063
AnnaBridge 143:86740a56073b 13064 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
AnnaBridge 143:86740a56073b 13065 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
AnnaBridge 143:86740a56073b 13066 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
AnnaBridge 143:86740a56073b 13067 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13068 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13069
AnnaBridge 143:86740a56073b 13070 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
AnnaBridge 143:86740a56073b 13071 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
AnnaBridge 143:86740a56073b 13072 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
AnnaBridge 143:86740a56073b 13073 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13074 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13075
AnnaBridge 143:86740a56073b 13076 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
AnnaBridge 143:86740a56073b 13077 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
AnnaBridge 143:86740a56073b 13078 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
AnnaBridge 143:86740a56073b 13079 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13080 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13081
AnnaBridge 143:86740a56073b 13082 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
AnnaBridge 143:86740a56073b 13083 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
AnnaBridge 143:86740a56073b 13084 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
AnnaBridge 143:86740a56073b 13085 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13086 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13087
AnnaBridge 143:86740a56073b 13088 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
AnnaBridge 143:86740a56073b 13089 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
AnnaBridge 143:86740a56073b 13090 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
AnnaBridge 143:86740a56073b 13091 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13092 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13093
AnnaBridge 143:86740a56073b 13094 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
AnnaBridge 143:86740a56073b 13095 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
AnnaBridge 143:86740a56073b 13096 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
AnnaBridge 143:86740a56073b 13097 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13098 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13099
AnnaBridge 143:86740a56073b 13100 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
AnnaBridge 143:86740a56073b 13101 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
AnnaBridge 143:86740a56073b 13102 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
AnnaBridge 143:86740a56073b 13103 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13104 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13105
AnnaBridge 143:86740a56073b 13106 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
AnnaBridge 143:86740a56073b 13107 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
AnnaBridge 143:86740a56073b 13108 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
AnnaBridge 143:86740a56073b 13109 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13110 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13111
AnnaBridge 143:86740a56073b 13112 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
AnnaBridge 143:86740a56073b 13113 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
AnnaBridge 143:86740a56073b 13114 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
AnnaBridge 143:86740a56073b 13115 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13116 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13117
AnnaBridge 143:86740a56073b 13118 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
AnnaBridge 143:86740a56073b 13119 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
AnnaBridge 143:86740a56073b 13120 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
AnnaBridge 143:86740a56073b 13121 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13122 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13123
AnnaBridge 143:86740a56073b 13124 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
AnnaBridge 143:86740a56073b 13125 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
AnnaBridge 143:86740a56073b 13126 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
AnnaBridge 143:86740a56073b 13127 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13128 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13129
AnnaBridge 143:86740a56073b 13130 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
AnnaBridge 143:86740a56073b 13131 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
AnnaBridge 143:86740a56073b 13132 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
AnnaBridge 143:86740a56073b 13133 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13134 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13135
AnnaBridge 143:86740a56073b 13136 /* Register: TIMER_INTENSET */
AnnaBridge 143:86740a56073b 13137 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 13138
AnnaBridge 143:86740a56073b 13139 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
AnnaBridge 143:86740a56073b 13140 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
AnnaBridge 143:86740a56073b 13141 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
AnnaBridge 143:86740a56073b 13142 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13143 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13144 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13145
AnnaBridge 143:86740a56073b 13146 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
AnnaBridge 143:86740a56073b 13147 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
AnnaBridge 143:86740a56073b 13148 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
AnnaBridge 143:86740a56073b 13149 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13150 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13151 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13152
AnnaBridge 143:86740a56073b 13153 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
AnnaBridge 143:86740a56073b 13154 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 13155 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 13156 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13157 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13158 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13159
AnnaBridge 143:86740a56073b 13160 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
AnnaBridge 143:86740a56073b 13161 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 13162 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 13163 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13164 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13165 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13166
AnnaBridge 143:86740a56073b 13167 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
AnnaBridge 143:86740a56073b 13168 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 13169 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 13170 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13171 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13172 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13173
AnnaBridge 143:86740a56073b 13174 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
AnnaBridge 143:86740a56073b 13175 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 13176 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 13177 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13178 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13179 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13180
AnnaBridge 143:86740a56073b 13181 /* Register: TIMER_INTENCLR */
AnnaBridge 143:86740a56073b 13182 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 13183
AnnaBridge 143:86740a56073b 13184 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
AnnaBridge 143:86740a56073b 13185 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
AnnaBridge 143:86740a56073b 13186 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
AnnaBridge 143:86740a56073b 13187 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13188 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13189 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13190
AnnaBridge 143:86740a56073b 13191 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
AnnaBridge 143:86740a56073b 13192 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
AnnaBridge 143:86740a56073b 13193 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
AnnaBridge 143:86740a56073b 13194 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13195 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13196 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13197
AnnaBridge 143:86740a56073b 13198 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
AnnaBridge 143:86740a56073b 13199 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 13200 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 13201 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13202 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13203 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13204
AnnaBridge 143:86740a56073b 13205 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
AnnaBridge 143:86740a56073b 13206 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 13207 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 13208 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13209 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13210 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13211
AnnaBridge 143:86740a56073b 13212 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
AnnaBridge 143:86740a56073b 13213 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 13214 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 13215 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13216 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13217 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13218
AnnaBridge 143:86740a56073b 13219 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
AnnaBridge 143:86740a56073b 13220 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 13221 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 13222 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13223 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13224 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13225
AnnaBridge 143:86740a56073b 13226 /* Register: TIMER_MODE */
AnnaBridge 143:86740a56073b 13227 /* Description: Timer mode selection */
AnnaBridge 143:86740a56073b 13228
AnnaBridge 143:86740a56073b 13229 /* Bits 1..0 : Timer mode */
AnnaBridge 143:86740a56073b 13230 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 13231 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 13232 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
AnnaBridge 143:86740a56073b 13233 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
AnnaBridge 143:86740a56073b 13234 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
AnnaBridge 143:86740a56073b 13235
AnnaBridge 143:86740a56073b 13236 /* Register: TIMER_BITMODE */
AnnaBridge 143:86740a56073b 13237 /* Description: Configure the number of bits used by the TIMER */
AnnaBridge 143:86740a56073b 13238
AnnaBridge 143:86740a56073b 13239 /* Bits 1..0 : Timer bit width */
AnnaBridge 143:86740a56073b 13240 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
AnnaBridge 143:86740a56073b 13241 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
AnnaBridge 143:86740a56073b 13242 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
AnnaBridge 143:86740a56073b 13243 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
AnnaBridge 143:86740a56073b 13244 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
AnnaBridge 143:86740a56073b 13245 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
AnnaBridge 143:86740a56073b 13246
AnnaBridge 143:86740a56073b 13247 /* Register: TIMER_PRESCALER */
AnnaBridge 143:86740a56073b 13248 /* Description: Timer prescaler register */
AnnaBridge 143:86740a56073b 13249
AnnaBridge 143:86740a56073b 13250 /* Bits 3..0 : Prescaler value */
AnnaBridge 143:86740a56073b 13251 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
AnnaBridge 143:86740a56073b 13252 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
AnnaBridge 143:86740a56073b 13253
AnnaBridge 143:86740a56073b 13254 /* Register: TIMER_CC */
AnnaBridge 143:86740a56073b 13255 /* Description: Description collection[0]: Capture/Compare register 0 */
AnnaBridge 143:86740a56073b 13256
AnnaBridge 143:86740a56073b 13257 /* Bits 31..0 : Capture/Compare value */
AnnaBridge 143:86740a56073b 13258 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
AnnaBridge 143:86740a56073b 13259 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
AnnaBridge 143:86740a56073b 13260
AnnaBridge 143:86740a56073b 13261
AnnaBridge 143:86740a56073b 13262 /* Peripheral: TWI */
AnnaBridge 143:86740a56073b 13263 /* Description: I2C compatible Two-Wire Interface 0 */
AnnaBridge 143:86740a56073b 13264
AnnaBridge 143:86740a56073b 13265 /* Register: TWI_SHORTS */
AnnaBridge 143:86740a56073b 13266 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 13267
AnnaBridge 143:86740a56073b 13268 /* Bit 1 : Shortcut between BB event and STOP task */
AnnaBridge 143:86740a56073b 13269 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
AnnaBridge 143:86740a56073b 13270 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
AnnaBridge 143:86740a56073b 13271 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13272 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13273
AnnaBridge 143:86740a56073b 13274 /* Bit 0 : Shortcut between BB event and SUSPEND task */
AnnaBridge 143:86740a56073b 13275 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
AnnaBridge 143:86740a56073b 13276 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
AnnaBridge 143:86740a56073b 13277 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13278 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13279
AnnaBridge 143:86740a56073b 13280 /* Register: TWI_INTENSET */
AnnaBridge 143:86740a56073b 13281 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 13282
AnnaBridge 143:86740a56073b 13283 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
AnnaBridge 143:86740a56073b 13284 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13285 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13286 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13287 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13288 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13289
AnnaBridge 143:86740a56073b 13290 /* Bit 14 : Write '1' to Enable interrupt for BB event */
AnnaBridge 143:86740a56073b 13291 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
AnnaBridge 143:86740a56073b 13292 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
AnnaBridge 143:86740a56073b 13293 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13294 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13295 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13296
AnnaBridge 143:86740a56073b 13297 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13298 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13299 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13300 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13301 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13302 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13303
AnnaBridge 143:86740a56073b 13304 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
AnnaBridge 143:86740a56073b 13305 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
AnnaBridge 143:86740a56073b 13306 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
AnnaBridge 143:86740a56073b 13307 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13308 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13309 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13310
AnnaBridge 143:86740a56073b 13311 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
AnnaBridge 143:86740a56073b 13312 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
AnnaBridge 143:86740a56073b 13313 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
AnnaBridge 143:86740a56073b 13314 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13315 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13316 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13317
AnnaBridge 143:86740a56073b 13318 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13319 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13320 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13321 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13322 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13323 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13324
AnnaBridge 143:86740a56073b 13325 /* Register: TWI_INTENCLR */
AnnaBridge 143:86740a56073b 13326 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 13327
AnnaBridge 143:86740a56073b 13328 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
AnnaBridge 143:86740a56073b 13329 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13330 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13331 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13332 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13333 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13334
AnnaBridge 143:86740a56073b 13335 /* Bit 14 : Write '1' to Disable interrupt for BB event */
AnnaBridge 143:86740a56073b 13336 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
AnnaBridge 143:86740a56073b 13337 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
AnnaBridge 143:86740a56073b 13338 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13339 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13340 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13341
AnnaBridge 143:86740a56073b 13342 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13343 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13344 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13345 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13346 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13347 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13348
AnnaBridge 143:86740a56073b 13349 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
AnnaBridge 143:86740a56073b 13350 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
AnnaBridge 143:86740a56073b 13351 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
AnnaBridge 143:86740a56073b 13352 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13353 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13354 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13355
AnnaBridge 143:86740a56073b 13356 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
AnnaBridge 143:86740a56073b 13357 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
AnnaBridge 143:86740a56073b 13358 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
AnnaBridge 143:86740a56073b 13359 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13360 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13361 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13362
AnnaBridge 143:86740a56073b 13363 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13364 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13365 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13366 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13367 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13368 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13369
AnnaBridge 143:86740a56073b 13370 /* Register: TWI_ERRORSRC */
AnnaBridge 143:86740a56073b 13371 /* Description: Error source */
AnnaBridge 143:86740a56073b 13372
AnnaBridge 143:86740a56073b 13373 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
AnnaBridge 143:86740a56073b 13374 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
AnnaBridge 143:86740a56073b 13375 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
AnnaBridge 143:86740a56073b 13376 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 13377 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 13378
AnnaBridge 143:86740a56073b 13379 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
AnnaBridge 143:86740a56073b 13380 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
AnnaBridge 143:86740a56073b 13381 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
AnnaBridge 143:86740a56073b 13382 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 13383 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 13384
AnnaBridge 143:86740a56073b 13385 /* Bit 0 : Overrun error */
AnnaBridge 143:86740a56073b 13386 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
AnnaBridge 143:86740a56073b 13387 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
AnnaBridge 143:86740a56073b 13388 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
AnnaBridge 143:86740a56073b 13389 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
AnnaBridge 143:86740a56073b 13390
AnnaBridge 143:86740a56073b 13391 /* Register: TWI_ENABLE */
AnnaBridge 143:86740a56073b 13392 /* Description: Enable TWI */
AnnaBridge 143:86740a56073b 13393
AnnaBridge 143:86740a56073b 13394 /* Bits 3..0 : Enable or disable TWI */
AnnaBridge 143:86740a56073b 13395 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 13396 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 13397 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
AnnaBridge 143:86740a56073b 13398 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
AnnaBridge 143:86740a56073b 13399
AnnaBridge 143:86740a56073b 13400 /* Register: TWI_PSELSCL */
AnnaBridge 143:86740a56073b 13401 /* Description: Pin select for SCL */
AnnaBridge 143:86740a56073b 13402
AnnaBridge 143:86740a56073b 13403 /* Bits 31..0 : Pin number configuration for TWI SCL signal */
AnnaBridge 143:86740a56073b 13404 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
AnnaBridge 143:86740a56073b 13405 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
AnnaBridge 143:86740a56073b 13406 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 13407
AnnaBridge 143:86740a56073b 13408 /* Register: TWI_PSELSDA */
AnnaBridge 143:86740a56073b 13409 /* Description: Pin select for SDA */
AnnaBridge 143:86740a56073b 13410
AnnaBridge 143:86740a56073b 13411 /* Bits 31..0 : Pin number configuration for TWI SDA signal */
AnnaBridge 143:86740a56073b 13412 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
AnnaBridge 143:86740a56073b 13413 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
AnnaBridge 143:86740a56073b 13414 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 13415
AnnaBridge 143:86740a56073b 13416 /* Register: TWI_RXD */
AnnaBridge 143:86740a56073b 13417 /* Description: RXD register */
AnnaBridge 143:86740a56073b 13418
AnnaBridge 143:86740a56073b 13419 /* Bits 7..0 : RXD register */
AnnaBridge 143:86740a56073b 13420 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
AnnaBridge 143:86740a56073b 13421 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
AnnaBridge 143:86740a56073b 13422
AnnaBridge 143:86740a56073b 13423 /* Register: TWI_TXD */
AnnaBridge 143:86740a56073b 13424 /* Description: TXD register */
AnnaBridge 143:86740a56073b 13425
AnnaBridge 143:86740a56073b 13426 /* Bits 7..0 : TXD register */
AnnaBridge 143:86740a56073b 13427 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
AnnaBridge 143:86740a56073b 13428 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
AnnaBridge 143:86740a56073b 13429
AnnaBridge 143:86740a56073b 13430 /* Register: TWI_FREQUENCY */
AnnaBridge 143:86740a56073b 13431 /* Description: TWI frequency */
AnnaBridge 143:86740a56073b 13432
AnnaBridge 143:86740a56073b 13433 /* Bits 31..0 : TWI master clock frequency */
AnnaBridge 143:86740a56073b 13434 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 13435 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 13436 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
AnnaBridge 143:86740a56073b 13437 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
AnnaBridge 143:86740a56073b 13438 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
AnnaBridge 143:86740a56073b 13439
AnnaBridge 143:86740a56073b 13440 /* Register: TWI_ADDRESS */
AnnaBridge 143:86740a56073b 13441 /* Description: Address used in the TWI transfer */
AnnaBridge 143:86740a56073b 13442
AnnaBridge 143:86740a56073b 13443 /* Bits 6..0 : Address used in the TWI transfer */
AnnaBridge 143:86740a56073b 13444 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 13445 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 13446
AnnaBridge 143:86740a56073b 13447
AnnaBridge 143:86740a56073b 13448 /* Peripheral: TWIM */
AnnaBridge 143:86740a56073b 13449 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
AnnaBridge 143:86740a56073b 13450
AnnaBridge 143:86740a56073b 13451 /* Register: TWIM_SHORTS */
AnnaBridge 143:86740a56073b 13452 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 13453
AnnaBridge 143:86740a56073b 13454 /* Bit 12 : Shortcut between LASTRX event and STOP task */
AnnaBridge 143:86740a56073b 13455 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
AnnaBridge 143:86740a56073b 13456 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
AnnaBridge 143:86740a56073b 13457 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13458 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13459
AnnaBridge 143:86740a56073b 13460 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */
AnnaBridge 143:86740a56073b 13461 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
AnnaBridge 143:86740a56073b 13462 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
AnnaBridge 143:86740a56073b 13463 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13464 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13465
AnnaBridge 143:86740a56073b 13466 /* Bit 9 : Shortcut between LASTTX event and STOP task */
AnnaBridge 143:86740a56073b 13467 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
AnnaBridge 143:86740a56073b 13468 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
AnnaBridge 143:86740a56073b 13469 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13470 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13471
AnnaBridge 143:86740a56073b 13472 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
AnnaBridge 143:86740a56073b 13473 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
AnnaBridge 143:86740a56073b 13474 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
AnnaBridge 143:86740a56073b 13475 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13476 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13477
AnnaBridge 143:86740a56073b 13478 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */
AnnaBridge 143:86740a56073b 13479 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
AnnaBridge 143:86740a56073b 13480 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
AnnaBridge 143:86740a56073b 13481 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13482 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13483
AnnaBridge 143:86740a56073b 13484 /* Register: TWIM_INTEN */
AnnaBridge 143:86740a56073b 13485 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 13486
AnnaBridge 143:86740a56073b 13487 /* Bit 24 : Enable or disable interrupt for LASTTX event */
AnnaBridge 143:86740a56073b 13488 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
AnnaBridge 143:86740a56073b 13489 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
AnnaBridge 143:86740a56073b 13490 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13491 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13492
AnnaBridge 143:86740a56073b 13493 /* Bit 23 : Enable or disable interrupt for LASTRX event */
AnnaBridge 143:86740a56073b 13494 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
AnnaBridge 143:86740a56073b 13495 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
AnnaBridge 143:86740a56073b 13496 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13497 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13498
AnnaBridge 143:86740a56073b 13499 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 13500 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13501 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13502 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13503 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13504
AnnaBridge 143:86740a56073b 13505 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 13506 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13507 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13508 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13509 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13510
AnnaBridge 143:86740a56073b 13511 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
AnnaBridge 143:86740a56073b 13512 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13513 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13514 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13515 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13516
AnnaBridge 143:86740a56073b 13517 /* Bit 9 : Enable or disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13518 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13519 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13520 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13521 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13522
AnnaBridge 143:86740a56073b 13523 /* Bit 1 : Enable or disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13524 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13525 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13526 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13527 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13528
AnnaBridge 143:86740a56073b 13529 /* Register: TWIM_INTENSET */
AnnaBridge 143:86740a56073b 13530 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 13531
AnnaBridge 143:86740a56073b 13532 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
AnnaBridge 143:86740a56073b 13533 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
AnnaBridge 143:86740a56073b 13534 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
AnnaBridge 143:86740a56073b 13535 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13536 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13537 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13538
AnnaBridge 143:86740a56073b 13539 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
AnnaBridge 143:86740a56073b 13540 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
AnnaBridge 143:86740a56073b 13541 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
AnnaBridge 143:86740a56073b 13542 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13543 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13544 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13545
AnnaBridge 143:86740a56073b 13546 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 13547 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13548 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13549 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13550 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13551 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13552
AnnaBridge 143:86740a56073b 13553 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 13554 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13555 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13556 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13557 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13558 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13559
AnnaBridge 143:86740a56073b 13560 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
AnnaBridge 143:86740a56073b 13561 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13562 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13563 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13564 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13565 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13566
AnnaBridge 143:86740a56073b 13567 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13568 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13569 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13570 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13571 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13572 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13573
AnnaBridge 143:86740a56073b 13574 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13575 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13576 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13577 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13578 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13579 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13580
AnnaBridge 143:86740a56073b 13581 /* Register: TWIM_INTENCLR */
AnnaBridge 143:86740a56073b 13582 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 13583
AnnaBridge 143:86740a56073b 13584 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
AnnaBridge 143:86740a56073b 13585 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
AnnaBridge 143:86740a56073b 13586 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
AnnaBridge 143:86740a56073b 13587 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13588 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13589 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13590
AnnaBridge 143:86740a56073b 13591 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
AnnaBridge 143:86740a56073b 13592 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
AnnaBridge 143:86740a56073b 13593 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
AnnaBridge 143:86740a56073b 13594 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13595 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13596 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13597
AnnaBridge 143:86740a56073b 13598 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 13599 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13600 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13601 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13602 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13603 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13604
AnnaBridge 143:86740a56073b 13605 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 13606 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13607 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13608 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13609 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13610 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13611
AnnaBridge 143:86740a56073b 13612 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
AnnaBridge 143:86740a56073b 13613 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13614 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
AnnaBridge 143:86740a56073b 13615 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13616 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13617 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13618
AnnaBridge 143:86740a56073b 13619 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13620 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13621 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13622 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13623 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13624 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13625
AnnaBridge 143:86740a56073b 13626 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13627 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13628 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13629 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13630 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13631 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13632
AnnaBridge 143:86740a56073b 13633 /* Register: TWIM_ERRORSRC */
AnnaBridge 143:86740a56073b 13634 /* Description: Error source */
AnnaBridge 143:86740a56073b 13635
AnnaBridge 143:86740a56073b 13636 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
AnnaBridge 143:86740a56073b 13637 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
AnnaBridge 143:86740a56073b 13638 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
AnnaBridge 143:86740a56073b 13639 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
AnnaBridge 143:86740a56073b 13640 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
AnnaBridge 143:86740a56073b 13641
AnnaBridge 143:86740a56073b 13642 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
AnnaBridge 143:86740a56073b 13643 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
AnnaBridge 143:86740a56073b 13644 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
AnnaBridge 143:86740a56073b 13645 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
AnnaBridge 143:86740a56073b 13646 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
AnnaBridge 143:86740a56073b 13647
AnnaBridge 143:86740a56073b 13648 /* Register: TWIM_ENABLE */
AnnaBridge 143:86740a56073b 13649 /* Description: Enable TWIM */
AnnaBridge 143:86740a56073b 13650
AnnaBridge 143:86740a56073b 13651 /* Bits 3..0 : Enable or disable TWIM */
AnnaBridge 143:86740a56073b 13652 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 13653 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 13654 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
AnnaBridge 143:86740a56073b 13655 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
AnnaBridge 143:86740a56073b 13656
AnnaBridge 143:86740a56073b 13657 /* Register: TWIM_PSEL_SCL */
AnnaBridge 143:86740a56073b 13658 /* Description: Pin select for SCL signal */
AnnaBridge 143:86740a56073b 13659
AnnaBridge 143:86740a56073b 13660 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 13661 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 13662 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 13663 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 13664 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 13665
AnnaBridge 143:86740a56073b 13666 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 13667 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 13668 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 13669
AnnaBridge 143:86740a56073b 13670 /* Register: TWIM_PSEL_SDA */
AnnaBridge 143:86740a56073b 13671 /* Description: Pin select for SDA signal */
AnnaBridge 143:86740a56073b 13672
AnnaBridge 143:86740a56073b 13673 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 13674 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 13675 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 13676 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 13677 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 13678
AnnaBridge 143:86740a56073b 13679 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 13680 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 13681 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 13682
AnnaBridge 143:86740a56073b 13683 /* Register: TWIM_FREQUENCY */
AnnaBridge 143:86740a56073b 13684 /* Description: TWI frequency */
AnnaBridge 143:86740a56073b 13685
AnnaBridge 143:86740a56073b 13686 /* Bits 31..0 : TWI master clock frequency */
AnnaBridge 143:86740a56073b 13687 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 13688 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 13689 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
AnnaBridge 143:86740a56073b 13690 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
AnnaBridge 143:86740a56073b 13691 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
AnnaBridge 143:86740a56073b 13692
AnnaBridge 143:86740a56073b 13693 /* Register: TWIM_RXD_PTR */
AnnaBridge 143:86740a56073b 13694 /* Description: Data pointer */
AnnaBridge 143:86740a56073b 13695
AnnaBridge 143:86740a56073b 13696 /* Bits 31..0 : Data pointer */
AnnaBridge 143:86740a56073b 13697 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 13698 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 13699
AnnaBridge 143:86740a56073b 13700 /* Register: TWIM_RXD_MAXCNT */
AnnaBridge 143:86740a56073b 13701 /* Description: Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 13702
AnnaBridge 143:86740a56073b 13703 /* Bits 7..0 : Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 13704 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 13705 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 13706
AnnaBridge 143:86740a56073b 13707 /* Register: TWIM_RXD_AMOUNT */
AnnaBridge 143:86740a56073b 13708 /* Description: Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 13709
AnnaBridge 143:86740a56073b 13710 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
AnnaBridge 143:86740a56073b 13711 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 13712 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 13713
AnnaBridge 143:86740a56073b 13714 /* Register: TWIM_RXD_LIST */
AnnaBridge 143:86740a56073b 13715 /* Description: EasyDMA list type */
AnnaBridge 143:86740a56073b 13716
AnnaBridge 143:86740a56073b 13717 /* Bits 2..0 : List type */
AnnaBridge 143:86740a56073b 13718 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
AnnaBridge 143:86740a56073b 13719 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
AnnaBridge 143:86740a56073b 13720 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
AnnaBridge 143:86740a56073b 13721 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
AnnaBridge 143:86740a56073b 13722
AnnaBridge 143:86740a56073b 13723 /* Register: TWIM_TXD_PTR */
AnnaBridge 143:86740a56073b 13724 /* Description: Data pointer */
AnnaBridge 143:86740a56073b 13725
AnnaBridge 143:86740a56073b 13726 /* Bits 31..0 : Data pointer */
AnnaBridge 143:86740a56073b 13727 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 13728 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 13729
AnnaBridge 143:86740a56073b 13730 /* Register: TWIM_TXD_MAXCNT */
AnnaBridge 143:86740a56073b 13731 /* Description: Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 13732
AnnaBridge 143:86740a56073b 13733 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 13734 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 13735 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 13736
AnnaBridge 143:86740a56073b 13737 /* Register: TWIM_TXD_AMOUNT */
AnnaBridge 143:86740a56073b 13738 /* Description: Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 13739
AnnaBridge 143:86740a56073b 13740 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
AnnaBridge 143:86740a56073b 13741 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 13742 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 13743
AnnaBridge 143:86740a56073b 13744 /* Register: TWIM_TXD_LIST */
AnnaBridge 143:86740a56073b 13745 /* Description: EasyDMA list type */
AnnaBridge 143:86740a56073b 13746
AnnaBridge 143:86740a56073b 13747 /* Bits 2..0 : List type */
AnnaBridge 143:86740a56073b 13748 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
AnnaBridge 143:86740a56073b 13749 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
AnnaBridge 143:86740a56073b 13750 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
AnnaBridge 143:86740a56073b 13751 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
AnnaBridge 143:86740a56073b 13752
AnnaBridge 143:86740a56073b 13753 /* Register: TWIM_ADDRESS */
AnnaBridge 143:86740a56073b 13754 /* Description: Address used in the TWI transfer */
AnnaBridge 143:86740a56073b 13755
AnnaBridge 143:86740a56073b 13756 /* Bits 6..0 : Address used in the TWI transfer */
AnnaBridge 143:86740a56073b 13757 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 13758 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 13759
AnnaBridge 143:86740a56073b 13760
AnnaBridge 143:86740a56073b 13761 /* Peripheral: TWIS */
AnnaBridge 143:86740a56073b 13762 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
AnnaBridge 143:86740a56073b 13763
AnnaBridge 143:86740a56073b 13764 /* Register: TWIS_SHORTS */
AnnaBridge 143:86740a56073b 13765 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 13766
AnnaBridge 143:86740a56073b 13767 /* Bit 14 : Shortcut between READ event and SUSPEND task */
AnnaBridge 143:86740a56073b 13768 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
AnnaBridge 143:86740a56073b 13769 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
AnnaBridge 143:86740a56073b 13770 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13771 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13772
AnnaBridge 143:86740a56073b 13773 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
AnnaBridge 143:86740a56073b 13774 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
AnnaBridge 143:86740a56073b 13775 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
AnnaBridge 143:86740a56073b 13776 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 13777 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 13778
AnnaBridge 143:86740a56073b 13779 /* Register: TWIS_INTEN */
AnnaBridge 143:86740a56073b 13780 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 13781
AnnaBridge 143:86740a56073b 13782 /* Bit 26 : Enable or disable interrupt for READ event */
AnnaBridge 143:86740a56073b 13783 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
AnnaBridge 143:86740a56073b 13784 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
AnnaBridge 143:86740a56073b 13785 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13786 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13787
AnnaBridge 143:86740a56073b 13788 /* Bit 25 : Enable or disable interrupt for WRITE event */
AnnaBridge 143:86740a56073b 13789 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
AnnaBridge 143:86740a56073b 13790 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
AnnaBridge 143:86740a56073b 13791 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13792 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13793
AnnaBridge 143:86740a56073b 13794 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 13795 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13796 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13797 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13798 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13799
AnnaBridge 143:86740a56073b 13800 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 13801 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13802 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13803 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13804 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13805
AnnaBridge 143:86740a56073b 13806 /* Bit 9 : Enable or disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13807 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13808 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13809 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13810 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13811
AnnaBridge 143:86740a56073b 13812 /* Bit 1 : Enable or disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13813 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13814 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13815 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13816 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13817
AnnaBridge 143:86740a56073b 13818 /* Register: TWIS_INTENSET */
AnnaBridge 143:86740a56073b 13819 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 13820
AnnaBridge 143:86740a56073b 13821 /* Bit 26 : Write '1' to Enable interrupt for READ event */
AnnaBridge 143:86740a56073b 13822 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
AnnaBridge 143:86740a56073b 13823 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
AnnaBridge 143:86740a56073b 13824 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13825 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13826 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13827
AnnaBridge 143:86740a56073b 13828 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
AnnaBridge 143:86740a56073b 13829 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
AnnaBridge 143:86740a56073b 13830 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
AnnaBridge 143:86740a56073b 13831 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13832 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13833 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13834
AnnaBridge 143:86740a56073b 13835 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 13836 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13837 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13838 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13839 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13840 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13841
AnnaBridge 143:86740a56073b 13842 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 13843 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13844 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13845 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13846 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13847 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13848
AnnaBridge 143:86740a56073b 13849 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13850 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13851 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13852 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13853 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13854 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13855
AnnaBridge 143:86740a56073b 13856 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13857 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13858 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13859 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13860 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13861 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 13862
AnnaBridge 143:86740a56073b 13863 /* Register: TWIS_INTENCLR */
AnnaBridge 143:86740a56073b 13864 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 13865
AnnaBridge 143:86740a56073b 13866 /* Bit 26 : Write '1' to Disable interrupt for READ event */
AnnaBridge 143:86740a56073b 13867 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
AnnaBridge 143:86740a56073b 13868 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
AnnaBridge 143:86740a56073b 13869 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13870 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13871 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13872
AnnaBridge 143:86740a56073b 13873 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
AnnaBridge 143:86740a56073b 13874 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
AnnaBridge 143:86740a56073b 13875 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
AnnaBridge 143:86740a56073b 13876 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13877 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13878 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13879
AnnaBridge 143:86740a56073b 13880 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 13881 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13882 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 13883 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13884 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13885 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13886
AnnaBridge 143:86740a56073b 13887 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 13888 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13889 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 13890 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13891 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13892 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13893
AnnaBridge 143:86740a56073b 13894 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 13895 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 13896 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 13897 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13898 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13899 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13900
AnnaBridge 143:86740a56073b 13901 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
AnnaBridge 143:86740a56073b 13902 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 13903 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 13904 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 13905 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 13906 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 13907
AnnaBridge 143:86740a56073b 13908 /* Register: TWIS_ERRORSRC */
AnnaBridge 143:86740a56073b 13909 /* Description: Error source */
AnnaBridge 143:86740a56073b 13910
AnnaBridge 143:86740a56073b 13911 /* Bit 3 : TX buffer over-read detected, and prevented */
AnnaBridge 143:86740a56073b 13912 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
AnnaBridge 143:86740a56073b 13913 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
AnnaBridge 143:86740a56073b 13914 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
AnnaBridge 143:86740a56073b 13915 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
AnnaBridge 143:86740a56073b 13916
AnnaBridge 143:86740a56073b 13917 /* Bit 2 : NACK sent after receiving a data byte */
AnnaBridge 143:86740a56073b 13918 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
AnnaBridge 143:86740a56073b 13919 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
AnnaBridge 143:86740a56073b 13920 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
AnnaBridge 143:86740a56073b 13921 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
AnnaBridge 143:86740a56073b 13922
AnnaBridge 143:86740a56073b 13923 /* Bit 0 : RX buffer overflow detected, and prevented */
AnnaBridge 143:86740a56073b 13924 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
AnnaBridge 143:86740a56073b 13925 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
AnnaBridge 143:86740a56073b 13926 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
AnnaBridge 143:86740a56073b 13927 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
AnnaBridge 143:86740a56073b 13928
AnnaBridge 143:86740a56073b 13929 /* Register: TWIS_MATCH */
AnnaBridge 143:86740a56073b 13930 /* Description: Status register indicating which address had a match */
AnnaBridge 143:86740a56073b 13931
AnnaBridge 143:86740a56073b 13932 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
AnnaBridge 143:86740a56073b 13933 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
AnnaBridge 143:86740a56073b 13934 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
AnnaBridge 143:86740a56073b 13935
AnnaBridge 143:86740a56073b 13936 /* Register: TWIS_ENABLE */
AnnaBridge 143:86740a56073b 13937 /* Description: Enable TWIS */
AnnaBridge 143:86740a56073b 13938
AnnaBridge 143:86740a56073b 13939 /* Bits 3..0 : Enable or disable TWIS */
AnnaBridge 143:86740a56073b 13940 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 13941 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 13942 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
AnnaBridge 143:86740a56073b 13943 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
AnnaBridge 143:86740a56073b 13944
AnnaBridge 143:86740a56073b 13945 /* Register: TWIS_PSEL_SCL */
AnnaBridge 143:86740a56073b 13946 /* Description: Pin select for SCL signal */
AnnaBridge 143:86740a56073b 13947
AnnaBridge 143:86740a56073b 13948 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 13949 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 13950 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 13951 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 13952 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 13953
AnnaBridge 143:86740a56073b 13954 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 13955 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 13956 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 13957
AnnaBridge 143:86740a56073b 13958 /* Register: TWIS_PSEL_SDA */
AnnaBridge 143:86740a56073b 13959 /* Description: Pin select for SDA signal */
AnnaBridge 143:86740a56073b 13960
AnnaBridge 143:86740a56073b 13961 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 13962 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 13963 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 13964 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 13965 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 13966
AnnaBridge 143:86740a56073b 13967 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 13968 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 13969 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 13970
AnnaBridge 143:86740a56073b 13971 /* Register: TWIS_RXD_PTR */
AnnaBridge 143:86740a56073b 13972 /* Description: RXD Data pointer */
AnnaBridge 143:86740a56073b 13973
AnnaBridge 143:86740a56073b 13974 /* Bits 31..0 : RXD Data pointer */
AnnaBridge 143:86740a56073b 13975 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 13976 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 13977
AnnaBridge 143:86740a56073b 13978 /* Register: TWIS_RXD_MAXCNT */
AnnaBridge 143:86740a56073b 13979 /* Description: Maximum number of bytes in RXD buffer */
AnnaBridge 143:86740a56073b 13980
AnnaBridge 143:86740a56073b 13981 /* Bits 7..0 : Maximum number of bytes in RXD buffer */
AnnaBridge 143:86740a56073b 13982 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 13983 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 13984
AnnaBridge 143:86740a56073b 13985 /* Register: TWIS_RXD_AMOUNT */
AnnaBridge 143:86740a56073b 13986 /* Description: Number of bytes transferred in the last RXD transaction */
AnnaBridge 143:86740a56073b 13987
AnnaBridge 143:86740a56073b 13988 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
AnnaBridge 143:86740a56073b 13989 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 13990 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 13991
AnnaBridge 143:86740a56073b 13992 /* Register: TWIS_TXD_PTR */
AnnaBridge 143:86740a56073b 13993 /* Description: TXD Data pointer */
AnnaBridge 143:86740a56073b 13994
AnnaBridge 143:86740a56073b 13995 /* Bits 31..0 : TXD Data pointer */
AnnaBridge 143:86740a56073b 13996 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 13997 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 13998
AnnaBridge 143:86740a56073b 13999 /* Register: TWIS_TXD_MAXCNT */
AnnaBridge 143:86740a56073b 14000 /* Description: Maximum number of bytes in TXD buffer */
AnnaBridge 143:86740a56073b 14001
AnnaBridge 143:86740a56073b 14002 /* Bits 7..0 : Maximum number of bytes in TXD buffer */
AnnaBridge 143:86740a56073b 14003 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 14004 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 14005
AnnaBridge 143:86740a56073b 14006 /* Register: TWIS_TXD_AMOUNT */
AnnaBridge 143:86740a56073b 14007 /* Description: Number of bytes transferred in the last TXD transaction */
AnnaBridge 143:86740a56073b 14008
AnnaBridge 143:86740a56073b 14009 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
AnnaBridge 143:86740a56073b 14010 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 14011 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 14012
AnnaBridge 143:86740a56073b 14013 /* Register: TWIS_ADDRESS */
AnnaBridge 143:86740a56073b 14014 /* Description: Description collection[0]: TWI slave address 0 */
AnnaBridge 143:86740a56073b 14015
AnnaBridge 143:86740a56073b 14016 /* Bits 6..0 : TWI slave address */
AnnaBridge 143:86740a56073b 14017 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 14018 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 14019
AnnaBridge 143:86740a56073b 14020 /* Register: TWIS_CONFIG */
AnnaBridge 143:86740a56073b 14021 /* Description: Configuration register for the address match mechanism */
AnnaBridge 143:86740a56073b 14022
AnnaBridge 143:86740a56073b 14023 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
AnnaBridge 143:86740a56073b 14024 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
AnnaBridge 143:86740a56073b 14025 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
AnnaBridge 143:86740a56073b 14026 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 14027 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 14028
AnnaBridge 143:86740a56073b 14029 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
AnnaBridge 143:86740a56073b 14030 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
AnnaBridge 143:86740a56073b 14031 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
AnnaBridge 143:86740a56073b 14032 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 14033 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 14034
AnnaBridge 143:86740a56073b 14035 /* Register: TWIS_ORC */
AnnaBridge 143:86740a56073b 14036 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
AnnaBridge 143:86740a56073b 14037
AnnaBridge 143:86740a56073b 14038 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
AnnaBridge 143:86740a56073b 14039 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
AnnaBridge 143:86740a56073b 14040 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
AnnaBridge 143:86740a56073b 14041
AnnaBridge 143:86740a56073b 14042
AnnaBridge 143:86740a56073b 14043 /* Peripheral: UART */
AnnaBridge 143:86740a56073b 14044 /* Description: Universal Asynchronous Receiver/Transmitter */
AnnaBridge 143:86740a56073b 14045
AnnaBridge 143:86740a56073b 14046 /* Register: UART_SHORTS */
AnnaBridge 143:86740a56073b 14047 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 14048
AnnaBridge 143:86740a56073b 14049 /* Bit 4 : Shortcut between NCTS event and STOPRX task */
AnnaBridge 143:86740a56073b 14050 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
AnnaBridge 143:86740a56073b 14051 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
AnnaBridge 143:86740a56073b 14052 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 14053 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 14054
AnnaBridge 143:86740a56073b 14055 /* Bit 3 : Shortcut between CTS event and STARTRX task */
AnnaBridge 143:86740a56073b 14056 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
AnnaBridge 143:86740a56073b 14057 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
AnnaBridge 143:86740a56073b 14058 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 14059 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 14060
AnnaBridge 143:86740a56073b 14061 /* Register: UART_INTENSET */
AnnaBridge 143:86740a56073b 14062 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 14063
AnnaBridge 143:86740a56073b 14064 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
AnnaBridge 143:86740a56073b 14065 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
AnnaBridge 143:86740a56073b 14066 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
AnnaBridge 143:86740a56073b 14067 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14068 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14069 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14070
AnnaBridge 143:86740a56073b 14071 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 14072 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 14073 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 14074 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14075 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14076 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14077
AnnaBridge 143:86740a56073b 14078 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
AnnaBridge 143:86740a56073b 14079 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
AnnaBridge 143:86740a56073b 14080 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
AnnaBridge 143:86740a56073b 14081 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14082 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14083 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14084
AnnaBridge 143:86740a56073b 14085 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
AnnaBridge 143:86740a56073b 14086 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
AnnaBridge 143:86740a56073b 14087 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
AnnaBridge 143:86740a56073b 14088 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14089 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14090 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14091
AnnaBridge 143:86740a56073b 14092 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
AnnaBridge 143:86740a56073b 14093 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
AnnaBridge 143:86740a56073b 14094 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
AnnaBridge 143:86740a56073b 14095 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14096 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14097 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14098
AnnaBridge 143:86740a56073b 14099 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
AnnaBridge 143:86740a56073b 14100 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
AnnaBridge 143:86740a56073b 14101 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
AnnaBridge 143:86740a56073b 14102 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14103 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14104 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14105
AnnaBridge 143:86740a56073b 14106 /* Register: UART_INTENCLR */
AnnaBridge 143:86740a56073b 14107 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 14108
AnnaBridge 143:86740a56073b 14109 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
AnnaBridge 143:86740a56073b 14110 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
AnnaBridge 143:86740a56073b 14111 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
AnnaBridge 143:86740a56073b 14112 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14113 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14114 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14115
AnnaBridge 143:86740a56073b 14116 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 14117 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 14118 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 14119 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14120 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14121 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14122
AnnaBridge 143:86740a56073b 14123 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
AnnaBridge 143:86740a56073b 14124 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
AnnaBridge 143:86740a56073b 14125 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
AnnaBridge 143:86740a56073b 14126 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14127 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14128 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14129
AnnaBridge 143:86740a56073b 14130 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
AnnaBridge 143:86740a56073b 14131 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
AnnaBridge 143:86740a56073b 14132 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
AnnaBridge 143:86740a56073b 14133 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14134 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14135 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14136
AnnaBridge 143:86740a56073b 14137 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
AnnaBridge 143:86740a56073b 14138 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
AnnaBridge 143:86740a56073b 14139 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
AnnaBridge 143:86740a56073b 14140 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14141 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14142 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14143
AnnaBridge 143:86740a56073b 14144 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
AnnaBridge 143:86740a56073b 14145 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
AnnaBridge 143:86740a56073b 14146 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
AnnaBridge 143:86740a56073b 14147 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14148 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14149 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14150
AnnaBridge 143:86740a56073b 14151 /* Register: UART_ERRORSRC */
AnnaBridge 143:86740a56073b 14152 /* Description: Error source */
AnnaBridge 143:86740a56073b 14153
AnnaBridge 143:86740a56073b 14154 /* Bit 3 : Break condition */
AnnaBridge 143:86740a56073b 14155 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
AnnaBridge 143:86740a56073b 14156 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
AnnaBridge 143:86740a56073b 14157 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14158 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14159
AnnaBridge 143:86740a56073b 14160 /* Bit 2 : Framing error occurred */
AnnaBridge 143:86740a56073b 14161 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
AnnaBridge 143:86740a56073b 14162 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
AnnaBridge 143:86740a56073b 14163 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14164 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14165
AnnaBridge 143:86740a56073b 14166 /* Bit 1 : Parity error */
AnnaBridge 143:86740a56073b 14167 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 14168 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 14169 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14170 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14171
AnnaBridge 143:86740a56073b 14172 /* Bit 0 : Overrun error */
AnnaBridge 143:86740a56073b 14173 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
AnnaBridge 143:86740a56073b 14174 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
AnnaBridge 143:86740a56073b 14175 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14176 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14177
AnnaBridge 143:86740a56073b 14178 /* Register: UART_ENABLE */
AnnaBridge 143:86740a56073b 14179 /* Description: Enable UART */
AnnaBridge 143:86740a56073b 14180
AnnaBridge 143:86740a56073b 14181 /* Bits 3..0 : Enable or disable UART */
AnnaBridge 143:86740a56073b 14182 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 14183 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 14184 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
AnnaBridge 143:86740a56073b 14185 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
AnnaBridge 143:86740a56073b 14186
AnnaBridge 143:86740a56073b 14187 /* Register: UART_PSELRTS */
AnnaBridge 143:86740a56073b 14188 /* Description: Pin select for RTS */
AnnaBridge 143:86740a56073b 14189
AnnaBridge 143:86740a56073b 14190 /* Bits 31..0 : Pin number configuration for UART RTS signal */
AnnaBridge 143:86740a56073b 14191 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
AnnaBridge 143:86740a56073b 14192 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
AnnaBridge 143:86740a56073b 14193 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14194
AnnaBridge 143:86740a56073b 14195 /* Register: UART_PSELTXD */
AnnaBridge 143:86740a56073b 14196 /* Description: Pin select for TXD */
AnnaBridge 143:86740a56073b 14197
AnnaBridge 143:86740a56073b 14198 /* Bits 31..0 : Pin number configuration for UART TXD signal */
AnnaBridge 143:86740a56073b 14199 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
AnnaBridge 143:86740a56073b 14200 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
AnnaBridge 143:86740a56073b 14201 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14202
AnnaBridge 143:86740a56073b 14203 /* Register: UART_PSELCTS */
AnnaBridge 143:86740a56073b 14204 /* Description: Pin select for CTS */
AnnaBridge 143:86740a56073b 14205
AnnaBridge 143:86740a56073b 14206 /* Bits 31..0 : Pin number configuration for UART CTS signal */
AnnaBridge 143:86740a56073b 14207 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
AnnaBridge 143:86740a56073b 14208 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
AnnaBridge 143:86740a56073b 14209 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14210
AnnaBridge 143:86740a56073b 14211 /* Register: UART_PSELRXD */
AnnaBridge 143:86740a56073b 14212 /* Description: Pin select for RXD */
AnnaBridge 143:86740a56073b 14213
AnnaBridge 143:86740a56073b 14214 /* Bits 31..0 : Pin number configuration for UART RXD signal */
AnnaBridge 143:86740a56073b 14215 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
AnnaBridge 143:86740a56073b 14216 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
AnnaBridge 143:86740a56073b 14217 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14218
AnnaBridge 143:86740a56073b 14219 /* Register: UART_RXD */
AnnaBridge 143:86740a56073b 14220 /* Description: RXD register */
AnnaBridge 143:86740a56073b 14221
AnnaBridge 143:86740a56073b 14222 /* Bits 7..0 : RX data received in previous transfers, double buffered */
AnnaBridge 143:86740a56073b 14223 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
AnnaBridge 143:86740a56073b 14224 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
AnnaBridge 143:86740a56073b 14225
AnnaBridge 143:86740a56073b 14226 /* Register: UART_TXD */
AnnaBridge 143:86740a56073b 14227 /* Description: TXD register */
AnnaBridge 143:86740a56073b 14228
AnnaBridge 143:86740a56073b 14229 /* Bits 7..0 : TX data to be transferred */
AnnaBridge 143:86740a56073b 14230 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
AnnaBridge 143:86740a56073b 14231 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
AnnaBridge 143:86740a56073b 14232
AnnaBridge 143:86740a56073b 14233 /* Register: UART_BAUDRATE */
AnnaBridge 143:86740a56073b 14234 /* Description: Baud rate */
AnnaBridge 143:86740a56073b 14235
AnnaBridge 143:86740a56073b 14236 /* Bits 31..0 : Baud-rate */
AnnaBridge 143:86740a56073b 14237 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
AnnaBridge 143:86740a56073b 14238 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
AnnaBridge 143:86740a56073b 14239 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
AnnaBridge 143:86740a56073b 14240 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
AnnaBridge 143:86740a56073b 14241 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
AnnaBridge 143:86740a56073b 14242 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
AnnaBridge 143:86740a56073b 14243 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
AnnaBridge 143:86740a56073b 14244 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
AnnaBridge 143:86740a56073b 14245 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
AnnaBridge 143:86740a56073b 14246 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
AnnaBridge 143:86740a56073b 14247 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
AnnaBridge 143:86740a56073b 14248 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
AnnaBridge 143:86740a56073b 14249 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
AnnaBridge 143:86740a56073b 14250 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
AnnaBridge 143:86740a56073b 14251 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
AnnaBridge 143:86740a56073b 14252 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
AnnaBridge 143:86740a56073b 14253 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
AnnaBridge 143:86740a56073b 14254 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
AnnaBridge 143:86740a56073b 14255
AnnaBridge 143:86740a56073b 14256 /* Register: UART_CONFIG */
AnnaBridge 143:86740a56073b 14257 /* Description: Configuration of parity and hardware flow control */
AnnaBridge 143:86740a56073b 14258
AnnaBridge 143:86740a56073b 14259 /* Bits 3..1 : Parity */
AnnaBridge 143:86740a56073b 14260 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 14261 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 14262 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
AnnaBridge 143:86740a56073b 14263 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
AnnaBridge 143:86740a56073b 14264
AnnaBridge 143:86740a56073b 14265 /* Bit 0 : Hardware flow control */
AnnaBridge 143:86740a56073b 14266 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
AnnaBridge 143:86740a56073b 14267 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
AnnaBridge 143:86740a56073b 14268 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 14269 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 14270
AnnaBridge 143:86740a56073b 14271
AnnaBridge 143:86740a56073b 14272 /* Peripheral: UARTE */
AnnaBridge 143:86740a56073b 14273 /* Description: UART with EasyDMA */
AnnaBridge 143:86740a56073b 14274
AnnaBridge 143:86740a56073b 14275 /* Register: UARTE_SHORTS */
AnnaBridge 143:86740a56073b 14276 /* Description: Shortcut register */
AnnaBridge 143:86740a56073b 14277
AnnaBridge 143:86740a56073b 14278 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */
AnnaBridge 143:86740a56073b 14279 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
AnnaBridge 143:86740a56073b 14280 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
AnnaBridge 143:86740a56073b 14281 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 14282 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 14283
AnnaBridge 143:86740a56073b 14284 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */
AnnaBridge 143:86740a56073b 14285 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
AnnaBridge 143:86740a56073b 14286 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
AnnaBridge 143:86740a56073b 14287 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
AnnaBridge 143:86740a56073b 14288 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
AnnaBridge 143:86740a56073b 14289
AnnaBridge 143:86740a56073b 14290 /* Register: UARTE_INTEN */
AnnaBridge 143:86740a56073b 14291 /* Description: Enable or disable interrupt */
AnnaBridge 143:86740a56073b 14292
AnnaBridge 143:86740a56073b 14293 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
AnnaBridge 143:86740a56073b 14294 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
AnnaBridge 143:86740a56073b 14295 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
AnnaBridge 143:86740a56073b 14296 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14297 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14298
AnnaBridge 143:86740a56073b 14299 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 14300 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 14301 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 14302 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14303 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14304
AnnaBridge 143:86740a56073b 14305 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 14306 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 14307 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 14308 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14309 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14310
AnnaBridge 143:86740a56073b 14311 /* Bit 17 : Enable or disable interrupt for RXTO event */
AnnaBridge 143:86740a56073b 14312 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
AnnaBridge 143:86740a56073b 14313 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
AnnaBridge 143:86740a56073b 14314 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14315 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14316
AnnaBridge 143:86740a56073b 14317 /* Bit 9 : Enable or disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 14318 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 14319 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 14320 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14321 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14322
AnnaBridge 143:86740a56073b 14323 /* Bit 8 : Enable or disable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 14324 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 14325 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 14326 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14327 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14328
AnnaBridge 143:86740a56073b 14329 /* Bit 4 : Enable or disable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 14330 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 14331 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 14332 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14333 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14334
AnnaBridge 143:86740a56073b 14335 /* Bit 1 : Enable or disable interrupt for NCTS event */
AnnaBridge 143:86740a56073b 14336 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
AnnaBridge 143:86740a56073b 14337 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
AnnaBridge 143:86740a56073b 14338 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14339 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14340
AnnaBridge 143:86740a56073b 14341 /* Bit 0 : Enable or disable interrupt for CTS event */
AnnaBridge 143:86740a56073b 14342 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
AnnaBridge 143:86740a56073b 14343 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
AnnaBridge 143:86740a56073b 14344 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14345 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14346
AnnaBridge 143:86740a56073b 14347 /* Register: UARTE_INTENSET */
AnnaBridge 143:86740a56073b 14348 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 14349
AnnaBridge 143:86740a56073b 14350 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
AnnaBridge 143:86740a56073b 14351 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
AnnaBridge 143:86740a56073b 14352 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
AnnaBridge 143:86740a56073b 14353 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14354 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14355 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14356
AnnaBridge 143:86740a56073b 14357 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 14358 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 14359 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 14360 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14361 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14362 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14363
AnnaBridge 143:86740a56073b 14364 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 14365 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 14366 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 14367 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14368 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14369 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14370
AnnaBridge 143:86740a56073b 14371 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
AnnaBridge 143:86740a56073b 14372 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
AnnaBridge 143:86740a56073b 14373 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
AnnaBridge 143:86740a56073b 14374 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14375 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14376 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14377
AnnaBridge 143:86740a56073b 14378 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 14379 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 14380 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 14381 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14382 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14383 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14384
AnnaBridge 143:86740a56073b 14385 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 14386 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 14387 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 14388 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14389 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14390 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14391
AnnaBridge 143:86740a56073b 14392 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 14393 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 14394 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 14395 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14396 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14397 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14398
AnnaBridge 143:86740a56073b 14399 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
AnnaBridge 143:86740a56073b 14400 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
AnnaBridge 143:86740a56073b 14401 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
AnnaBridge 143:86740a56073b 14402 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14403 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14404 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14405
AnnaBridge 143:86740a56073b 14406 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
AnnaBridge 143:86740a56073b 14407 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
AnnaBridge 143:86740a56073b 14408 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
AnnaBridge 143:86740a56073b 14409 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14410 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14411 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14412
AnnaBridge 143:86740a56073b 14413 /* Register: UARTE_INTENCLR */
AnnaBridge 143:86740a56073b 14414 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 14415
AnnaBridge 143:86740a56073b 14416 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
AnnaBridge 143:86740a56073b 14417 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
AnnaBridge 143:86740a56073b 14418 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
AnnaBridge 143:86740a56073b 14419 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14420 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14421 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14422
AnnaBridge 143:86740a56073b 14423 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
AnnaBridge 143:86740a56073b 14424 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
AnnaBridge 143:86740a56073b 14425 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
AnnaBridge 143:86740a56073b 14426 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14427 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14428 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14429
AnnaBridge 143:86740a56073b 14430 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
AnnaBridge 143:86740a56073b 14431 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
AnnaBridge 143:86740a56073b 14432 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
AnnaBridge 143:86740a56073b 14433 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14434 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14435 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14436
AnnaBridge 143:86740a56073b 14437 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
AnnaBridge 143:86740a56073b 14438 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
AnnaBridge 143:86740a56073b 14439 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
AnnaBridge 143:86740a56073b 14440 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14441 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14442 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14443
AnnaBridge 143:86740a56073b 14444 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
AnnaBridge 143:86740a56073b 14445 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 14446 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 14447 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14448 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14449 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14450
AnnaBridge 143:86740a56073b 14451 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
AnnaBridge 143:86740a56073b 14452 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 14453 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 14454 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14455 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14456 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14457
AnnaBridge 143:86740a56073b 14458 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
AnnaBridge 143:86740a56073b 14459 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 14460 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 14461 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14462 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14463 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14464
AnnaBridge 143:86740a56073b 14465 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
AnnaBridge 143:86740a56073b 14466 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
AnnaBridge 143:86740a56073b 14467 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
AnnaBridge 143:86740a56073b 14468 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14469 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14470 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14471
AnnaBridge 143:86740a56073b 14472 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
AnnaBridge 143:86740a56073b 14473 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
AnnaBridge 143:86740a56073b 14474 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
AnnaBridge 143:86740a56073b 14475 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14476 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14477 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14478
AnnaBridge 143:86740a56073b 14479 /* Register: UARTE_ERRORSRC */
AnnaBridge 143:86740a56073b 14480 /* Description: Error source */
AnnaBridge 143:86740a56073b 14481
AnnaBridge 143:86740a56073b 14482 /* Bit 3 : Break condition */
AnnaBridge 143:86740a56073b 14483 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
AnnaBridge 143:86740a56073b 14484 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
AnnaBridge 143:86740a56073b 14485 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14486 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14487
AnnaBridge 143:86740a56073b 14488 /* Bit 2 : Framing error occurred */
AnnaBridge 143:86740a56073b 14489 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
AnnaBridge 143:86740a56073b 14490 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
AnnaBridge 143:86740a56073b 14491 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14492 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14493
AnnaBridge 143:86740a56073b 14494 /* Bit 1 : Parity error */
AnnaBridge 143:86740a56073b 14495 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 14496 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 14497 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14498 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14499
AnnaBridge 143:86740a56073b 14500 /* Bit 0 : Overrun error */
AnnaBridge 143:86740a56073b 14501 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
AnnaBridge 143:86740a56073b 14502 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
AnnaBridge 143:86740a56073b 14503 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
AnnaBridge 143:86740a56073b 14504 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
AnnaBridge 143:86740a56073b 14505
AnnaBridge 143:86740a56073b 14506 /* Register: UARTE_ENABLE */
AnnaBridge 143:86740a56073b 14507 /* Description: Enable UART */
AnnaBridge 143:86740a56073b 14508
AnnaBridge 143:86740a56073b 14509 /* Bits 3..0 : Enable or disable UARTE */
AnnaBridge 143:86740a56073b 14510 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 14511 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 14512 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
AnnaBridge 143:86740a56073b 14513 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
AnnaBridge 143:86740a56073b 14514
AnnaBridge 143:86740a56073b 14515 /* Register: UARTE_PSEL_RTS */
AnnaBridge 143:86740a56073b 14516 /* Description: Pin select for RTS signal */
AnnaBridge 143:86740a56073b 14517
AnnaBridge 143:86740a56073b 14518 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 14519 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 14520 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 14521 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 14522 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14523
AnnaBridge 143:86740a56073b 14524 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 14525 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 14526 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 14527
AnnaBridge 143:86740a56073b 14528 /* Register: UARTE_PSEL_TXD */
AnnaBridge 143:86740a56073b 14529 /* Description: Pin select for TXD signal */
AnnaBridge 143:86740a56073b 14530
AnnaBridge 143:86740a56073b 14531 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 14532 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 14533 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 14534 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 14535 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14536
AnnaBridge 143:86740a56073b 14537 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 14538 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 14539 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 14540
AnnaBridge 143:86740a56073b 14541 /* Register: UARTE_PSEL_CTS */
AnnaBridge 143:86740a56073b 14542 /* Description: Pin select for CTS signal */
AnnaBridge 143:86740a56073b 14543
AnnaBridge 143:86740a56073b 14544 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 14545 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 14546 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 14547 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 14548 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14549
AnnaBridge 143:86740a56073b 14550 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 14551 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 14552 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 14553
AnnaBridge 143:86740a56073b 14554 /* Register: UARTE_PSEL_RXD */
AnnaBridge 143:86740a56073b 14555 /* Description: Pin select for RXD signal */
AnnaBridge 143:86740a56073b 14556
AnnaBridge 143:86740a56073b 14557 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 14558 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 14559 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 14560 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 14561 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14562
AnnaBridge 143:86740a56073b 14563 /* Bits 4..0 : Pin number */
AnnaBridge 143:86740a56073b 14564 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 14565 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 14566
AnnaBridge 143:86740a56073b 14567 /* Register: UARTE_BAUDRATE */
AnnaBridge 143:86740a56073b 14568 /* Description: Baud rate */
AnnaBridge 143:86740a56073b 14569
AnnaBridge 143:86740a56073b 14570 /* Bits 31..0 : Baud-rate */
AnnaBridge 143:86740a56073b 14571 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
AnnaBridge 143:86740a56073b 14572 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
AnnaBridge 143:86740a56073b 14573 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
AnnaBridge 143:86740a56073b 14574 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
AnnaBridge 143:86740a56073b 14575 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
AnnaBridge 143:86740a56073b 14576 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
AnnaBridge 143:86740a56073b 14577 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
AnnaBridge 143:86740a56073b 14578 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
AnnaBridge 143:86740a56073b 14579 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
AnnaBridge 143:86740a56073b 14580 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
AnnaBridge 143:86740a56073b 14581 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
AnnaBridge 143:86740a56073b 14582 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
AnnaBridge 143:86740a56073b 14583 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
AnnaBridge 143:86740a56073b 14584 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
AnnaBridge 143:86740a56073b 14585 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
AnnaBridge 143:86740a56073b 14586 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
AnnaBridge 143:86740a56073b 14587 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
AnnaBridge 143:86740a56073b 14588 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
AnnaBridge 143:86740a56073b 14589
AnnaBridge 143:86740a56073b 14590 /* Register: UARTE_RXD_PTR */
AnnaBridge 143:86740a56073b 14591 /* Description: Data pointer */
AnnaBridge 143:86740a56073b 14592
AnnaBridge 143:86740a56073b 14593 /* Bits 31..0 : Data pointer */
AnnaBridge 143:86740a56073b 14594 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 14595 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 14596
AnnaBridge 143:86740a56073b 14597 /* Register: UARTE_RXD_MAXCNT */
AnnaBridge 143:86740a56073b 14598 /* Description: Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 14599
AnnaBridge 143:86740a56073b 14600 /* Bits 7..0 : Maximum number of bytes in receive buffer */
AnnaBridge 143:86740a56073b 14601 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 14602 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 14603
AnnaBridge 143:86740a56073b 14604 /* Register: UARTE_RXD_AMOUNT */
AnnaBridge 143:86740a56073b 14605 /* Description: Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 14606
AnnaBridge 143:86740a56073b 14607 /* Bits 7..0 : Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 14608 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 14609 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 14610
AnnaBridge 143:86740a56073b 14611 /* Register: UARTE_TXD_PTR */
AnnaBridge 143:86740a56073b 14612 /* Description: Data pointer */
AnnaBridge 143:86740a56073b 14613
AnnaBridge 143:86740a56073b 14614 /* Bits 31..0 : Data pointer */
AnnaBridge 143:86740a56073b 14615 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 14616 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 14617
AnnaBridge 143:86740a56073b 14618 /* Register: UARTE_TXD_MAXCNT */
AnnaBridge 143:86740a56073b 14619 /* Description: Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 14620
AnnaBridge 143:86740a56073b 14621 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
AnnaBridge 143:86740a56073b 14622 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 14623 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 14624
AnnaBridge 143:86740a56073b 14625 /* Register: UARTE_TXD_AMOUNT */
AnnaBridge 143:86740a56073b 14626 /* Description: Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 14627
AnnaBridge 143:86740a56073b 14628 /* Bits 7..0 : Number of bytes transferred in the last transaction */
AnnaBridge 143:86740a56073b 14629 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 14630 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 14631
AnnaBridge 143:86740a56073b 14632 /* Register: UARTE_CONFIG */
AnnaBridge 143:86740a56073b 14633 /* Description: Configuration of parity and hardware flow control */
AnnaBridge 143:86740a56073b 14634
AnnaBridge 143:86740a56073b 14635 /* Bits 3..1 : Parity */
AnnaBridge 143:86740a56073b 14636 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 14637 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 14638 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
AnnaBridge 143:86740a56073b 14639 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
AnnaBridge 143:86740a56073b 14640
AnnaBridge 143:86740a56073b 14641 /* Bit 0 : Hardware flow control */
AnnaBridge 143:86740a56073b 14642 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
AnnaBridge 143:86740a56073b 14643 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
AnnaBridge 143:86740a56073b 14644 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
AnnaBridge 143:86740a56073b 14645 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
AnnaBridge 143:86740a56073b 14646
AnnaBridge 143:86740a56073b 14647
AnnaBridge 143:86740a56073b 14648 /* Peripheral: UICR */
AnnaBridge 143:86740a56073b 14649 /* Description: User Information Configuration Registers */
AnnaBridge 143:86740a56073b 14650
AnnaBridge 143:86740a56073b 14651 /* Register: UICR_NRFFW */
AnnaBridge 143:86740a56073b 14652 /* Description: Description collection[0]: Reserved for Nordic firmware design */
AnnaBridge 143:86740a56073b 14653
AnnaBridge 143:86740a56073b 14654 /* Bits 31..0 : Reserved for Nordic firmware design */
AnnaBridge 143:86740a56073b 14655 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
AnnaBridge 143:86740a56073b 14656 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
AnnaBridge 143:86740a56073b 14657
AnnaBridge 143:86740a56073b 14658 /* Register: UICR_NRFHW */
AnnaBridge 143:86740a56073b 14659 /* Description: Description collection[0]: Reserved for Nordic hardware design */
AnnaBridge 143:86740a56073b 14660
AnnaBridge 143:86740a56073b 14661 /* Bits 31..0 : Reserved for Nordic hardware design */
AnnaBridge 143:86740a56073b 14662 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
AnnaBridge 143:86740a56073b 14663 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
AnnaBridge 143:86740a56073b 14664
AnnaBridge 143:86740a56073b 14665 /* Register: UICR_CUSTOMER */
AnnaBridge 143:86740a56073b 14666 /* Description: Description collection[0]: Reserved for customer */
AnnaBridge 143:86740a56073b 14667
AnnaBridge 143:86740a56073b 14668 /* Bits 31..0 : Reserved for customer */
AnnaBridge 143:86740a56073b 14669 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
AnnaBridge 143:86740a56073b 14670 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
AnnaBridge 143:86740a56073b 14671
AnnaBridge 143:86740a56073b 14672 /* Register: UICR_PSELRESET */
AnnaBridge 143:86740a56073b 14673 /* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */
AnnaBridge 143:86740a56073b 14674
AnnaBridge 143:86740a56073b 14675 /* Bit 31 : Connection */
AnnaBridge 143:86740a56073b 14676 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
AnnaBridge 143:86740a56073b 14677 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
AnnaBridge 143:86740a56073b 14678 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
AnnaBridge 143:86740a56073b 14679 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
AnnaBridge 143:86740a56073b 14680
AnnaBridge 143:86740a56073b 14681 /* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
AnnaBridge 143:86740a56073b 14682 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
AnnaBridge 143:86740a56073b 14683 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
AnnaBridge 143:86740a56073b 14684
AnnaBridge 143:86740a56073b 14685 /* Register: UICR_APPROTECT */
AnnaBridge 143:86740a56073b 14686 /* Description: Access Port protection */
AnnaBridge 143:86740a56073b 14687
AnnaBridge 143:86740a56073b 14688 /* Bits 7..0 : Enable or disable Access Port protection. */
AnnaBridge 143:86740a56073b 14689 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
AnnaBridge 143:86740a56073b 14690 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
AnnaBridge 143:86740a56073b 14691 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14692 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
AnnaBridge 143:86740a56073b 14693
AnnaBridge 143:86740a56073b 14694 /* Register: UICR_NFCPINS */
AnnaBridge 143:86740a56073b 14695 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
AnnaBridge 143:86740a56073b 14696
AnnaBridge 143:86740a56073b 14697 /* Bit 0 : Setting of pins dedicated to NFC functionality */
AnnaBridge 143:86740a56073b 14698 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
AnnaBridge 143:86740a56073b 14699 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
AnnaBridge 143:86740a56073b 14700 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
AnnaBridge 143:86740a56073b 14701 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
AnnaBridge 143:86740a56073b 14702
AnnaBridge 143:86740a56073b 14703
AnnaBridge 143:86740a56073b 14704 /* Peripheral: WDT */
AnnaBridge 143:86740a56073b 14705 /* Description: Watchdog Timer */
AnnaBridge 143:86740a56073b 14706
AnnaBridge 143:86740a56073b 14707 /* Register: WDT_INTENSET */
AnnaBridge 143:86740a56073b 14708 /* Description: Enable interrupt */
AnnaBridge 143:86740a56073b 14709
AnnaBridge 143:86740a56073b 14710 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
AnnaBridge 143:86740a56073b 14711 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
AnnaBridge 143:86740a56073b 14712 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
AnnaBridge 143:86740a56073b 14713 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14714 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14715 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
AnnaBridge 143:86740a56073b 14716
AnnaBridge 143:86740a56073b 14717 /* Register: WDT_INTENCLR */
AnnaBridge 143:86740a56073b 14718 /* Description: Disable interrupt */
AnnaBridge 143:86740a56073b 14719
AnnaBridge 143:86740a56073b 14720 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
AnnaBridge 143:86740a56073b 14721 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
AnnaBridge 143:86740a56073b 14722 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
AnnaBridge 143:86740a56073b 14723 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
AnnaBridge 143:86740a56073b 14724 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
AnnaBridge 143:86740a56073b 14725 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
AnnaBridge 143:86740a56073b 14726
AnnaBridge 143:86740a56073b 14727 /* Register: WDT_RUNSTATUS */
AnnaBridge 143:86740a56073b 14728 /* Description: Run status */
AnnaBridge 143:86740a56073b 14729
AnnaBridge 143:86740a56073b 14730 /* Bit 0 : Indicates whether or not the watchdog is running */
AnnaBridge 143:86740a56073b 14731 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
AnnaBridge 143:86740a56073b 14732 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
AnnaBridge 143:86740a56073b 14733 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
AnnaBridge 143:86740a56073b 14734 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
AnnaBridge 143:86740a56073b 14735
AnnaBridge 143:86740a56073b 14736 /* Register: WDT_REQSTATUS */
AnnaBridge 143:86740a56073b 14737 /* Description: Request status */
AnnaBridge 143:86740a56073b 14738
AnnaBridge 143:86740a56073b 14739 /* Bit 7 : Request status for RR[7] register */
AnnaBridge 143:86740a56073b 14740 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
AnnaBridge 143:86740a56073b 14741 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
AnnaBridge 143:86740a56073b 14742 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14743 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14744
AnnaBridge 143:86740a56073b 14745 /* Bit 6 : Request status for RR[6] register */
AnnaBridge 143:86740a56073b 14746 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
AnnaBridge 143:86740a56073b 14747 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
AnnaBridge 143:86740a56073b 14748 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14749 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14750
AnnaBridge 143:86740a56073b 14751 /* Bit 5 : Request status for RR[5] register */
AnnaBridge 143:86740a56073b 14752 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
AnnaBridge 143:86740a56073b 14753 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
AnnaBridge 143:86740a56073b 14754 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14755 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14756
AnnaBridge 143:86740a56073b 14757 /* Bit 4 : Request status for RR[4] register */
AnnaBridge 143:86740a56073b 14758 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
AnnaBridge 143:86740a56073b 14759 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
AnnaBridge 143:86740a56073b 14760 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14761 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14762
AnnaBridge 143:86740a56073b 14763 /* Bit 3 : Request status for RR[3] register */
AnnaBridge 143:86740a56073b 14764 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
AnnaBridge 143:86740a56073b 14765 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
AnnaBridge 143:86740a56073b 14766 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14767 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14768
AnnaBridge 143:86740a56073b 14769 /* Bit 2 : Request status for RR[2] register */
AnnaBridge 143:86740a56073b 14770 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
AnnaBridge 143:86740a56073b 14771 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
AnnaBridge 143:86740a56073b 14772 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14773 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14774
AnnaBridge 143:86740a56073b 14775 /* Bit 1 : Request status for RR[1] register */
AnnaBridge 143:86740a56073b 14776 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
AnnaBridge 143:86740a56073b 14777 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
AnnaBridge 143:86740a56073b 14778 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14779 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14780
AnnaBridge 143:86740a56073b 14781 /* Bit 0 : Request status for RR[0] register */
AnnaBridge 143:86740a56073b 14782 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
AnnaBridge 143:86740a56073b 14783 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
AnnaBridge 143:86740a56073b 14784 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
AnnaBridge 143:86740a56073b 14785 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
AnnaBridge 143:86740a56073b 14786
AnnaBridge 143:86740a56073b 14787 /* Register: WDT_CRV */
AnnaBridge 143:86740a56073b 14788 /* Description: Counter reload value */
AnnaBridge 143:86740a56073b 14789
AnnaBridge 143:86740a56073b 14790 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
AnnaBridge 143:86740a56073b 14791 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
AnnaBridge 143:86740a56073b 14792 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
AnnaBridge 143:86740a56073b 14793
AnnaBridge 143:86740a56073b 14794 /* Register: WDT_RREN */
AnnaBridge 143:86740a56073b 14795 /* Description: Enable register for reload request registers */
AnnaBridge 143:86740a56073b 14796
AnnaBridge 143:86740a56073b 14797 /* Bit 7 : Enable or disable RR[7] register */
AnnaBridge 143:86740a56073b 14798 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
AnnaBridge 143:86740a56073b 14799 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
AnnaBridge 143:86740a56073b 14800 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
AnnaBridge 143:86740a56073b 14801 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
AnnaBridge 143:86740a56073b 14802
AnnaBridge 143:86740a56073b 14803 /* Bit 6 : Enable or disable RR[6] register */
AnnaBridge 143:86740a56073b 14804 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
AnnaBridge 143:86740a56073b 14805 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
AnnaBridge 143:86740a56073b 14806 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
AnnaBridge 143:86740a56073b 14807 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
AnnaBridge 143:86740a56073b 14808
AnnaBridge 143:86740a56073b 14809 /* Bit 5 : Enable or disable RR[5] register */
AnnaBridge 143:86740a56073b 14810 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
AnnaBridge 143:86740a56073b 14811 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
AnnaBridge 143:86740a56073b 14812 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
AnnaBridge 143:86740a56073b 14813 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
AnnaBridge 143:86740a56073b 14814
AnnaBridge 143:86740a56073b 14815 /* Bit 4 : Enable or disable RR[4] register */
AnnaBridge 143:86740a56073b 14816 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
AnnaBridge 143:86740a56073b 14817 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
AnnaBridge 143:86740a56073b 14818 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
AnnaBridge 143:86740a56073b 14819 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
AnnaBridge 143:86740a56073b 14820
AnnaBridge 143:86740a56073b 14821 /* Bit 3 : Enable or disable RR[3] register */
AnnaBridge 143:86740a56073b 14822 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
AnnaBridge 143:86740a56073b 14823 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
AnnaBridge 143:86740a56073b 14824 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
AnnaBridge 143:86740a56073b 14825 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
AnnaBridge 143:86740a56073b 14826
AnnaBridge 143:86740a56073b 14827 /* Bit 2 : Enable or disable RR[2] register */
AnnaBridge 143:86740a56073b 14828 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
AnnaBridge 143:86740a56073b 14829 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
AnnaBridge 143:86740a56073b 14830 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
AnnaBridge 143:86740a56073b 14831 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
AnnaBridge 143:86740a56073b 14832
AnnaBridge 143:86740a56073b 14833 /* Bit 1 : Enable or disable RR[1] register */
AnnaBridge 143:86740a56073b 14834 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
AnnaBridge 143:86740a56073b 14835 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
AnnaBridge 143:86740a56073b 14836 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
AnnaBridge 143:86740a56073b 14837 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
AnnaBridge 143:86740a56073b 14838
AnnaBridge 143:86740a56073b 14839 /* Bit 0 : Enable or disable RR[0] register */
AnnaBridge 143:86740a56073b 14840 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
AnnaBridge 143:86740a56073b 14841 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
AnnaBridge 143:86740a56073b 14842 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
AnnaBridge 143:86740a56073b 14843 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
AnnaBridge 143:86740a56073b 14844
AnnaBridge 143:86740a56073b 14845 /* Register: WDT_CONFIG */
AnnaBridge 143:86740a56073b 14846 /* Description: Configuration register */
AnnaBridge 143:86740a56073b 14847
AnnaBridge 143:86740a56073b 14848 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
AnnaBridge 143:86740a56073b 14849 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
AnnaBridge 143:86740a56073b 14850 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
AnnaBridge 143:86740a56073b 14851 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
AnnaBridge 143:86740a56073b 14852 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
AnnaBridge 143:86740a56073b 14853
AnnaBridge 143:86740a56073b 14854 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
AnnaBridge 143:86740a56073b 14855 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
AnnaBridge 143:86740a56073b 14856 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
AnnaBridge 143:86740a56073b 14857 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
AnnaBridge 143:86740a56073b 14858 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
AnnaBridge 143:86740a56073b 14859
AnnaBridge 143:86740a56073b 14860 /* Register: WDT_RR */
AnnaBridge 143:86740a56073b 14861 /* Description: Description collection[0]: Reload request 0 */
AnnaBridge 143:86740a56073b 14862
AnnaBridge 143:86740a56073b 14863 /* Bits 31..0 : Reload request register */
AnnaBridge 143:86740a56073b 14864 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
AnnaBridge 143:86740a56073b 14865 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
AnnaBridge 143:86740a56073b 14866 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
AnnaBridge 143:86740a56073b 14867
AnnaBridge 143:86740a56073b 14868
AnnaBridge 143:86740a56073b 14869 /*lint --flb "Leave library region" */
AnnaBridge 143:86740a56073b 14870 #endif