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TARGET_USENSE/TOOLCHAIN_IAR/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/*
AnnaBridge	145:64910690c574	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge	145:64910690c574	3	* All rights reserved.
AnnaBridge	145:64910690c574	4	*
AnnaBridge	145:64910690c574	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	6	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	7	*
AnnaBridge	145:64910690c574	8	* o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	145:64910690c574	9	* of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	145:64910690c574	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	145:64910690c574	13	* other materials provided with the distribution.
AnnaBridge	145:64910690c574	14	*
AnnaBridge	145:64910690c574	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge	145:64910690c574	16	* contributors may be used to endorse or promote products derived from this
AnnaBridge	145:64910690c574	17	* software without specific prior written permission.
AnnaBridge	145:64910690c574	18	*
AnnaBridge	145:64910690c574	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	145:64910690c574	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	145:64910690c574	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	145:64910690c574	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	145:64910690c574	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	145:64910690c574	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	145:64910690c574	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	145:64910690c574	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	145:64910690c574	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	29	*/
AnnaBridge	145:64910690c574	30
AnnaBridge	145:64910690c574	31	#ifndef _FSL_CLOCK_H_
AnnaBridge	145:64910690c574	32	#define _FSL_CLOCK_H_
AnnaBridge	145:64910690c574	33
AnnaBridge	145:64910690c574	34	#include "fsl_device_registers.h"
AnnaBridge	145:64910690c574	35	#include <stdint.h>
AnnaBridge	145:64910690c574	36	#include <stdbool.h>
AnnaBridge	145:64910690c574	37	#include <assert.h>
AnnaBridge	145:64910690c574	38
AnnaBridge	145:64910690c574	39	/! @addtogroup clock /
AnnaBridge	145:64910690c574	40	/! @{ /
AnnaBridge	145:64910690c574	41
AnnaBridge	145:64910690c574	42	/! @file /
AnnaBridge	145:64910690c574	43
AnnaBridge	145:64910690c574	44	/*******************************************************************************
AnnaBridge	145:64910690c574	45	* Definitions
AnnaBridge	145:64910690c574	46	******************************************************************************/
AnnaBridge	145:64910690c574	47
AnnaBridge	145:64910690c574	48	/! @name Driver version /
AnnaBridge	145:64910690c574	49	/@{/
AnnaBridge	145:64910690c574	50	/! @brief CLOCK driver version 2.2.0. /
AnnaBridge	145:64910690c574	51	#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
AnnaBridge	145:64910690c574	52	/@}/
AnnaBridge	145:64910690c574	53
AnnaBridge	145:64910690c574	54	/*! @brief External XTAL0 (OSC0) clock frequency.
AnnaBridge	145:64910690c574	55	*
AnnaBridge	145:64910690c574	56	* The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
AnnaBridge	145:64910690c574	57	* function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
AnnaBridge	145:64910690c574	58	* if XTAL0 is 8 MHz:
AnnaBridge	145:64910690c574	59	* @code
AnnaBridge	145:64910690c574	60	* CLOCK_InitOsc0(...); // Set up the OSC0
AnnaBridge	145:64910690c574	61	* CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
AnnaBridge	145:64910690c574	62	* @endcode
AnnaBridge	145:64910690c574	63	*
AnnaBridge	145:64910690c574	64	* This is important for the multicore platforms where only one core needs to set up the
AnnaBridge	145:64910690c574	65	* OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
AnnaBridge	145:64910690c574	66	* to get a valid clock frequency.
AnnaBridge	145:64910690c574	67	*/
AnnaBridge	145:64910690c574	68	extern uint32_t g_xtal0Freq;
AnnaBridge	145:64910690c574	69
AnnaBridge	145:64910690c574	70	/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
AnnaBridge	145:64910690c574	71	*
AnnaBridge	145:64910690c574	72	* The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
AnnaBridge	145:64910690c574	73	* function CLOCK_SetXtal32Freq to set the value in the clock driver.
AnnaBridge	145:64910690c574	74	*
AnnaBridge	145:64910690c574	75	* This is important for the multicore platforms where only one core needs to set up
AnnaBridge	145:64910690c574	76	* the clock. All other cores need to call the CLOCK_SetXtal32Freq
AnnaBridge	145:64910690c574	77	* to get a valid clock frequency.
AnnaBridge	145:64910690c574	78	*/
AnnaBridge	145:64910690c574	79	extern uint32_t g_xtal32Freq;
AnnaBridge	145:64910690c574	80
AnnaBridge	145:64910690c574	81	/! @brief IRC48M clock frequency in Hz. /
AnnaBridge	145:64910690c574	82	#define MCG_INTERNAL_IRC_48M 48000000U
AnnaBridge	145:64910690c574	83
AnnaBridge	145:64910690c574	84	#if (defined(OSC) && !(defined(OSC0)))
AnnaBridge	145:64910690c574	85	#define OSC0 OSC
AnnaBridge	145:64910690c574	86	#endif
AnnaBridge	145:64910690c574	87
AnnaBridge	145:64910690c574	88	/! @brief Clock ip name array for DMAMUX. /
AnnaBridge	145:64910690c574	89	#define DMAMUX_CLOCKS \
AnnaBridge	145:64910690c574	90	{ \
AnnaBridge	145:64910690c574	91	kCLOCK_Dmamux0 \
AnnaBridge	145:64910690c574	92	}
AnnaBridge	145:64910690c574	93
AnnaBridge	145:64910690c574	94	/! @brief Clock ip name array for RTC. /
AnnaBridge	145:64910690c574	95	#define RTC_CLOCKS \
AnnaBridge	145:64910690c574	96	{ \
AnnaBridge	145:64910690c574	97	kCLOCK_Rtc0 \
AnnaBridge	145:64910690c574	98	}
AnnaBridge	145:64910690c574	99
AnnaBridge	145:64910690c574	100	/! @brief Clock ip name array for PORT. /
AnnaBridge	145:64910690c574	101	#define PORT_CLOCKS \
AnnaBridge	145:64910690c574	102	{ \
AnnaBridge	145:64910690c574	103	kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
AnnaBridge	145:64910690c574	104	}
AnnaBridge	145:64910690c574	105
AnnaBridge	145:64910690c574	106	/! @brief Clock ip name array for EWM. /
AnnaBridge	145:64910690c574	107	#define EWM_CLOCKS \
AnnaBridge	145:64910690c574	108	{ \
AnnaBridge	145:64910690c574	109	kCLOCK_Ewm0 \
AnnaBridge	145:64910690c574	110	}
AnnaBridge	145:64910690c574	111
AnnaBridge	145:64910690c574	112	/! @brief Clock ip name array for PIT. /
AnnaBridge	145:64910690c574	113	#define PIT_CLOCKS \
AnnaBridge	145:64910690c574	114	{ \
AnnaBridge	145:64910690c574	115	kCLOCK_Pit0 \
AnnaBridge	145:64910690c574	116	}
AnnaBridge	145:64910690c574	117
AnnaBridge	145:64910690c574	118	/! @brief Clock ip name array for DSPI. /
AnnaBridge	145:64910690c574	119	#define DSPI_CLOCKS \
AnnaBridge	145:64910690c574	120	{ \
AnnaBridge	145:64910690c574	121	kCLOCK_Spi0, kCLOCK_Spi1 \
AnnaBridge	145:64910690c574	122	}
AnnaBridge	145:64910690c574	123
AnnaBridge	145:64910690c574	124	/! @brief Clock ip name array for EMVSIM. /
AnnaBridge	145:64910690c574	125	#define EMVSIM_CLOCKS \
AnnaBridge	145:64910690c574	126	{ \
AnnaBridge	145:64910690c574	127	kCLOCK_Emvsim0, kCLOCK_Emvsim1 \
AnnaBridge	145:64910690c574	128	}
AnnaBridge	145:64910690c574	129
AnnaBridge	145:64910690c574	130	/! @brief Clock ip name array for QSPI. /
AnnaBridge	145:64910690c574	131	#define QSPI_CLOCKS \
AnnaBridge	145:64910690c574	132	{ \
AnnaBridge	145:64910690c574	133	kCLOCK_Qspi0 \
AnnaBridge	145:64910690c574	134	}
AnnaBridge	145:64910690c574	135
AnnaBridge	145:64910690c574	136	/! @brief Clock ip name array for EDMA. /
AnnaBridge	145:64910690c574	137	#define EDMA_CLOCKS \
AnnaBridge	145:64910690c574	138	{ \
AnnaBridge	145:64910690c574	139	kCLOCK_Dma0 \
AnnaBridge	145:64910690c574	140	}
AnnaBridge	145:64910690c574	141
AnnaBridge	145:64910690c574	142	/! @brief Clock ip name array for LPUART. /
AnnaBridge	145:64910690c574	143	#define LPUART_CLOCKS \
AnnaBridge	145:64910690c574	144	{ \
AnnaBridge	145:64910690c574	145	kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2 \
AnnaBridge	145:64910690c574	146	}
AnnaBridge	145:64910690c574	147
AnnaBridge	145:64910690c574	148	/! @brief Clock ip name array for DAC. /
AnnaBridge	145:64910690c574	149	#define DAC_CLOCKS \
AnnaBridge	145:64910690c574	150	{ \
AnnaBridge	145:64910690c574	151	kCLOCK_Dac0 \
AnnaBridge	145:64910690c574	152	}
AnnaBridge	145:64910690c574	153
AnnaBridge	145:64910690c574	154	/! @brief Clock ip name array for LPTMR. /
AnnaBridge	145:64910690c574	155	#define LPTMR_CLOCKS \
AnnaBridge	145:64910690c574	156	{ \
AnnaBridge	145:64910690c574	157	kCLOCK_Lptmr0, kCLOCK_Lptmr1 \
AnnaBridge	145:64910690c574	158	}
AnnaBridge	145:64910690c574	159
AnnaBridge	145:64910690c574	160	/! @brief Clock ip name array for ADC16. /
AnnaBridge	145:64910690c574	161	#define ADC16_CLOCKS \
AnnaBridge	145:64910690c574	162	{ \
AnnaBridge	145:64910690c574	163	kCLOCK_Adc0 \
AnnaBridge	145:64910690c574	164	}
AnnaBridge	145:64910690c574	165
AnnaBridge	145:64910690c574	166	/! @brief Clock ip name array for TRNG. /
AnnaBridge	145:64910690c574	167	#define TRNG_CLOCKS \
AnnaBridge	145:64910690c574	168	{ \
AnnaBridge	145:64910690c574	169	kCLOCK_Trng0 \
AnnaBridge	145:64910690c574	170	}
AnnaBridge	145:64910690c574	171
AnnaBridge	145:64910690c574	172	/! @brief Clock ip name array for MPU. /
AnnaBridge	145:64910690c574	173	#define MPU_CLOCKS \
AnnaBridge	145:64910690c574	174	{ \
AnnaBridge	145:64910690c574	175	kCLOCK_Mpu0 \
AnnaBridge	145:64910690c574	176	}
AnnaBridge	145:64910690c574	177
AnnaBridge	145:64910690c574	178	/! @brief Clock ip name array for FLEXIO. /
AnnaBridge	145:64910690c574	179	#define FLEXIO_CLOCKS \
AnnaBridge	145:64910690c574	180	{ \
AnnaBridge	145:64910690c574	181	kCLOCK_Flexio0 \
AnnaBridge	145:64910690c574	182	}
AnnaBridge	145:64910690c574	183
AnnaBridge	145:64910690c574	184	/! @brief Clock ip name array for VREF. /
AnnaBridge	145:64910690c574	185	#define VREF_CLOCKS \
AnnaBridge	145:64910690c574	186	{ \
AnnaBridge	145:64910690c574	187	kCLOCK_Vref0 \
AnnaBridge	145:64910690c574	188	}
AnnaBridge	145:64910690c574	189
AnnaBridge	145:64910690c574	190	/! @brief Clock ip name array for TPM. /
AnnaBridge	145:64910690c574	191	#define TPM_CLOCKS \
AnnaBridge	145:64910690c574	192	{ \
AnnaBridge	145:64910690c574	193	kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
AnnaBridge	145:64910690c574	194	}
AnnaBridge	145:64910690c574	195
AnnaBridge	145:64910690c574	196	/! @brief Clock ip name array for TSI. /
AnnaBridge	145:64910690c574	197	#define TSI_CLOCKS \
AnnaBridge	145:64910690c574	198	{ \
AnnaBridge	145:64910690c574	199	kCLOCK_Tsi0 \
AnnaBridge	145:64910690c574	200	}
AnnaBridge	145:64910690c574	201
AnnaBridge	145:64910690c574	202	/! @brief Clock ip name array for LTC. /
AnnaBridge	145:64910690c574	203	#define LTC_CLOCKS \
AnnaBridge	145:64910690c574	204	{ \
AnnaBridge	145:64910690c574	205	kCLOCK_Ltc0 \
AnnaBridge	145:64910690c574	206	}
AnnaBridge	145:64910690c574	207
AnnaBridge	145:64910690c574	208	/! @brief Clock ip name array for CRC. /
AnnaBridge	145:64910690c574	209	#define CRC_CLOCKS \
AnnaBridge	145:64910690c574	210	{ \
AnnaBridge	145:64910690c574	211	kCLOCK_Crc0 \
AnnaBridge	145:64910690c574	212	}
AnnaBridge	145:64910690c574	213
AnnaBridge	145:64910690c574	214	/! @brief Clock ip name array for I2C. /
AnnaBridge	145:64910690c574	215	#define I2C_CLOCKS \
AnnaBridge	145:64910690c574	216	{ \
AnnaBridge	145:64910690c574	217	kCLOCK_I2c0, kCLOCK_I2c1 \
AnnaBridge	145:64910690c574	218	}
AnnaBridge	145:64910690c574	219
AnnaBridge	145:64910690c574	220	/! @brief Clock ip name array for CMP. /
AnnaBridge	145:64910690c574	221	#define CMP_CLOCKS \
AnnaBridge	145:64910690c574	222	{ \
AnnaBridge	145:64910690c574	223	kCLOCK_Cmp0 \
AnnaBridge	145:64910690c574	224	}
AnnaBridge	145:64910690c574	225
AnnaBridge	145:64910690c574	226	/! @brief Clock ip name array for INTMUX. /
AnnaBridge	145:64910690c574	227	#define INTMUX_CLOCKS \
AnnaBridge	145:64910690c574	228	{ \
AnnaBridge	145:64910690c574	229	kCLOCK_Intmux0 \
AnnaBridge	145:64910690c574	230	}
AnnaBridge	145:64910690c574	231
AnnaBridge	145:64910690c574	232	/*!
AnnaBridge	145:64910690c574	233	* @brief LPO clock frequency.
AnnaBridge	145:64910690c574	234	*/
AnnaBridge	145:64910690c574	235	#define LPO_CLK_FREQ 1000U
AnnaBridge	145:64910690c574	236
AnnaBridge	145:64910690c574	237	/! @brief Peripherals clock source definition. /
AnnaBridge	145:64910690c574	238	#define SYS_CLK kCLOCK_CoreSysClk
AnnaBridge	145:64910690c574	239	#define BUS_CLK kCLOCK_BusClk
AnnaBridge	145:64910690c574	240
AnnaBridge	145:64910690c574	241	#define I2C0_CLK_SRC BUS_CLK
AnnaBridge	145:64910690c574	242	#define I2C1_CLK_SRC BUS_CLK
AnnaBridge	145:64910690c574	243	#define DSPI0_CLK_SRC SYS_CLK
AnnaBridge	145:64910690c574	244	#define DSPI1_CLK_SRC SYS_CLK
AnnaBridge	145:64910690c574	245
AnnaBridge	145:64910690c574	246	/! @brief Clock name used to get clock frequency. /
AnnaBridge	145:64910690c574	247	typedef enum _clock_name
AnnaBridge	145:64910690c574	248	{
AnnaBridge	145:64910690c574	249
AnnaBridge	145:64910690c574	250	/* ----------------------------- System layer clock -------------------------------*/
AnnaBridge	145:64910690c574	251	kCLOCK_CoreSysClk, /!< Core/system clock /
AnnaBridge	145:64910690c574	252	kCLOCK_PlatClk, /!< Platform clock /
AnnaBridge	145:64910690c574	253	kCLOCK_BusClk, /!< Bus clock /
AnnaBridge	145:64910690c574	254	kCLOCK_FlashClk, /!< Flash clock /
AnnaBridge	145:64910690c574	255	kCLOCK_FastPeriphClk, /!< Fast peripheral clock /
AnnaBridge	145:64910690c574	256	kCLOCK_PllFllSelClk, /!< The clock after SIM[PLLFLLSEL] /
AnnaBridge	145:64910690c574	257	kCLOCK_QspiBusClk, /!< QSPI bus interface clock /
AnnaBridge	145:64910690c574	258
AnnaBridge	145:64910690c574	259	/* ---------------------------------- OSC clock -----------------------------------*/
AnnaBridge	145:64910690c574	260	kCLOCK_Er32kClk, /!< External reference 32K clock (ERCLK32K) /
AnnaBridge	145:64910690c574	261	kCLOCK_Osc0ErClk, /!< OSC0 external reference clock (OSC0ERCLK) /
AnnaBridge	145:64910690c574	262	kCLOCK_Osc1ErClk, /!< OSC1 external reference clock (OSC1ERCLK) /
AnnaBridge	145:64910690c574	263	kCLOCK_Osc0ErClkUndiv, /!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). /
AnnaBridge	145:64910690c574	264
AnnaBridge	145:64910690c574	265	/* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
AnnaBridge	145:64910690c574	266	kCLOCK_McgFixedFreqClk, /!< MCG fixed frequency clock (MCGFFCLK) /
AnnaBridge	145:64910690c574	267	kCLOCK_McgInternalRefClk, /!< MCG internal reference clock (MCGIRCLK) /
AnnaBridge	145:64910690c574	268	kCLOCK_McgFllClk, /!< MCGFLLCLK /
AnnaBridge	145:64910690c574	269	kCLOCK_McgPll0Clk, /!< MCGPLL0CLK /
AnnaBridge	145:64910690c574	270	kCLOCK_McgPll1Clk, /!< MCGPLL1CLK /
AnnaBridge	145:64910690c574	271	kCLOCK_McgExtPllClk, /!< EXT_PLLCLK /
AnnaBridge	145:64910690c574	272	kCLOCK_McgPeriphClk, /!< MCG peripheral clock (MCGPCLK) /
AnnaBridge	145:64910690c574	273	kCLOCK_McgIrc48MClk, /!< MCG IRC48M clock /
AnnaBridge	145:64910690c574	274
AnnaBridge	145:64910690c574	275	/* --------------------------------- Other clock ----------------------------------*/
AnnaBridge	145:64910690c574	276	kCLOCK_LpoClk, /!< LPO clock /
AnnaBridge	145:64910690c574	277
AnnaBridge	145:64910690c574	278	} clock_name_t;
AnnaBridge	145:64910690c574	279
AnnaBridge	145:64910690c574	280	/! @brief USB clock source definition. /
AnnaBridge	145:64910690c574	281	typedef enum _clock_usb_src
AnnaBridge	145:64910690c574	282	{
AnnaBridge	145:64910690c574	283	kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(1U), /!< Use PLL0. /
AnnaBridge	145:64910690c574	284	kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(3U), /!< Use IRC48M. /
AnnaBridge	145:64910690c574	285	kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /!< Use USB_CLKIN. /
AnnaBridge	145:64910690c574	286	} clock_usb_src_t;
AnnaBridge	145:64910690c574	287
AnnaBridge	145:64910690c574	288	/*------------------------------------------------------------------------------
AnnaBridge	145:64910690c574	289
AnnaBridge	145:64910690c574	290	clock_gate_t definition:
AnnaBridge	145:64910690c574	291
AnnaBridge	145:64910690c574	292	31 16 0
AnnaBridge	145:64910690c574	293	-----------------------------------------------------------------
AnnaBridge	145:64910690c574	294	\| SIM_SCGC register offset \| control bit offset in SCGC \|
AnnaBridge	145:64910690c574	295	-----------------------------------------------------------------
AnnaBridge	145:64910690c574	296
AnnaBridge	145:64910690c574	297	For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
AnnaBridge	145:64910690c574	298	SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
AnnaBridge	145:64910690c574	299
AnnaBridge	145:64910690c574	300	kClockGateSdhc0 = (0x1030 << 16) \| 17;
AnnaBridge	145:64910690c574	301
AnnaBridge	145:64910690c574	302	------------------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	303
AnnaBridge	145:64910690c574	304	#define CLK_GATE_REG_OFFSET_SHIFT 16U
AnnaBridge	145:64910690c574	305	#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
AnnaBridge	145:64910690c574	306	#define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge	145:64910690c574	307	#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
AnnaBridge	145:64910690c574	308
AnnaBridge	145:64910690c574	309	#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge	145:64910690c574	310	((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) \| \
AnnaBridge	145:64910690c574	311	(((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge	145:64910690c574	312
AnnaBridge	145:64910690c574	313	#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge	145:64910690c574	314	#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge	145:64910690c574	315
AnnaBridge	145:64910690c574	316	/! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. /
AnnaBridge	145:64910690c574	317	typedef enum _clock_ip_name
AnnaBridge	145:64910690c574	318	{
AnnaBridge	145:64910690c574	319	kCLOCK_IpInvalid = 0U,
AnnaBridge	145:64910690c574	320
AnnaBridge	145:64910690c574	321	kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
AnnaBridge	145:64910690c574	322	kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
AnnaBridge	145:64910690c574	323	kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
AnnaBridge	145:64910690c574	324	kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
AnnaBridge	145:64910690c574	325	kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge	145:64910690c574	326	kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
AnnaBridge	145:64910690c574	327
AnnaBridge	145:64910690c574	328	kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
AnnaBridge	145:64910690c574	329	kCLOCK_Secreg0 = CLK_GATE_DEFINE(0x1038U, 3U),
AnnaBridge	145:64910690c574	330	kCLOCK_Lptmr1 = CLK_GATE_DEFINE(0x1038U, 4U),
AnnaBridge	145:64910690c574	331	kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
AnnaBridge	145:64910690c574	332	kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
AnnaBridge	145:64910690c574	333	kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
AnnaBridge	145:64910690c574	334	kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
AnnaBridge	145:64910690c574	335	kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
AnnaBridge	145:64910690c574	336	kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
AnnaBridge	145:64910690c574	337	kCLOCK_Emvsim0 = CLK_GATE_DEFINE(0x1038U, 14U),
AnnaBridge	145:64910690c574	338	kCLOCK_Emvsim1 = CLK_GATE_DEFINE(0x1038U, 15U),
AnnaBridge	145:64910690c574	339	kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x1038U, 17U),
AnnaBridge	145:64910690c574	340	kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
AnnaBridge	145:64910690c574	341	kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x1038U, 21U),
AnnaBridge	145:64910690c574	342	kCLOCK_Lpuart2 = CLK_GATE_DEFINE(0x1038U, 22U),
AnnaBridge	145:64910690c574	343	kCLOCK_Qspi0 = CLK_GATE_DEFINE(0x1038U, 26U),
AnnaBridge	145:64910690c574	344	kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x1038U, 31U),
AnnaBridge	145:64910690c574	345
AnnaBridge	145:64910690c574	346	kCLOCK_Nvm0 = CLK_GATE_DEFINE(0x103CU, 0U),
AnnaBridge	145:64910690c574	347	kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
AnnaBridge	145:64910690c574	348	kCLOCK_Intmux0 = CLK_GATE_DEFINE(0x103CU, 4U),
AnnaBridge	145:64910690c574	349	kCLOCK_Trng0 = CLK_GATE_DEFINE(0x103CU, 5U),
AnnaBridge	145:64910690c574	350	kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
AnnaBridge	145:64910690c574	351	kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
AnnaBridge	145:64910690c574	352	kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
AnnaBridge	145:64910690c574	353	kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
AnnaBridge	145:64910690c574	354	kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U),
AnnaBridge	145:64910690c574	355	kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U),
AnnaBridge	145:64910690c574	356	kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U),
AnnaBridge	145:64910690c574	357	kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
AnnaBridge	145:64910690c574	358	kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
AnnaBridge	145:64910690c574	359	kCLOCK_Rtc_Rf0 = CLK_GATE_DEFINE(0x103CU, 30U),
AnnaBridge	145:64910690c574	360	kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
AnnaBridge	145:64910690c574	361
AnnaBridge	145:64910690c574	362	kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
AnnaBridge	145:64910690c574	363	kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
AnnaBridge	145:64910690c574	364	} clock_ip_name_t;
AnnaBridge	145:64910690c574	365
AnnaBridge	145:64910690c574	366	/!@brief SIM configuration structure for clock setting. /
AnnaBridge	145:64910690c574	367	typedef struct _sim_clock_config
AnnaBridge	145:64910690c574	368	{
AnnaBridge	145:64910690c574	369	uint8_t pllFllSel; /!< PLL/FLL/IRC48M selection. /
AnnaBridge	145:64910690c574	370	uint8_t pllFllDiv; /!< PLLFLLSEL clock divider divisor. /
AnnaBridge	145:64910690c574	371	uint8_t pllFllFrac; /!< PLLFLLSEL clock divider fraction. /
AnnaBridge	145:64910690c574	372	uint8_t er32kSrc; /!< ERCLK32K source selection. /
AnnaBridge	145:64910690c574	373	uint32_t clkdiv1; /!< SIM_CLKDIV1. /
AnnaBridge	145:64910690c574	374	} sim_clock_config_t;
AnnaBridge	145:64910690c574	375
AnnaBridge	145:64910690c574	376	/! @brief OSC work mode. /
AnnaBridge	145:64910690c574	377	typedef enum _osc_mode
AnnaBridge	145:64910690c574	378	{
AnnaBridge	145:64910690c574	379	kOSC_ModeExt = 0U, /!< Use an external clock. /
AnnaBridge	145:64910690c574	380	#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge	145:64910690c574	381	kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /!< Oscillator low power. /
AnnaBridge	145:64910690c574	382	#else
AnnaBridge	145:64910690c574	383	kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /!< Oscillator low power. /
AnnaBridge	145:64910690c574	384	#endif
AnnaBridge	145:64910690c574	385	kOSC_ModeOscHighGain = 0U
AnnaBridge	145:64910690c574	386	#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge	145:64910690c574	387	\|
AnnaBridge	145:64910690c574	388	MCG_C2_EREFS_MASK
AnnaBridge	145:64910690c574	389	#else
AnnaBridge	145:64910690c574	390	\|
AnnaBridge	145:64910690c574	391	MCG_C2_EREFS0_MASK
AnnaBridge	145:64910690c574	392	#endif
AnnaBridge	145:64910690c574	393	#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
AnnaBridge	145:64910690c574	394	\|
AnnaBridge	145:64910690c574	395	MCG_C2_HGO_MASK, /!< Oscillator high gain. /
AnnaBridge	145:64910690c574	396	#else
AnnaBridge	145:64910690c574	397	\|
AnnaBridge	145:64910690c574	398	MCG_C2_HGO0_MASK, /!< Oscillator high gain. /
AnnaBridge	145:64910690c574	399	#endif
AnnaBridge	145:64910690c574	400	} osc_mode_t;
AnnaBridge	145:64910690c574	401
AnnaBridge	145:64910690c574	402	/! @brief Oscillator capacitor load setting./
AnnaBridge	145:64910690c574	403	enum _osc_cap_load
AnnaBridge	145:64910690c574	404	{
AnnaBridge	145:64910690c574	405	kOSC_Cap2P = OSC_CR_SC2P_MASK, /!< 2 pF capacitor load /
AnnaBridge	145:64910690c574	406	kOSC_Cap4P = OSC_CR_SC4P_MASK, /!< 4 pF capacitor load /
AnnaBridge	145:64910690c574	407	kOSC_Cap8P = OSC_CR_SC8P_MASK, /!< 8 pF capacitor load /
AnnaBridge	145:64910690c574	408	kOSC_Cap16P = OSC_CR_SC16P_MASK /!< 16 pF capacitor load /
AnnaBridge	145:64910690c574	409	};
AnnaBridge	145:64910690c574	410
AnnaBridge	145:64910690c574	411	/! @brief OSCERCLK enable mode. /
AnnaBridge	145:64910690c574	412	enum _oscer_enable_mode
AnnaBridge	145:64910690c574	413	{
AnnaBridge	145:64910690c574	414	kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /!< Enable. /
AnnaBridge	145:64910690c574	415	kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /!< Enable in stop mode. /
AnnaBridge	145:64910690c574	416	};
AnnaBridge	145:64910690c574	417
AnnaBridge	145:64910690c574	418	/! @brief OSC configuration for OSCERCLK. /
AnnaBridge	145:64910690c574	419	typedef struct _oscer_config
AnnaBridge	145:64910690c574	420	{
AnnaBridge	145:64910690c574	421	uint8_t enableMode; /!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. /
AnnaBridge	145:64910690c574	422
AnnaBridge	145:64910690c574	423	uint8_t erclkDiv; /!< Divider for OSCERCLK./
AnnaBridge	145:64910690c574	424	} oscer_config_t;
AnnaBridge	145:64910690c574	425
AnnaBridge	145:64910690c574	426	/*!
AnnaBridge	145:64910690c574	427	* @brief OSC Initialization Configuration Structure
AnnaBridge	145:64910690c574	428	*
AnnaBridge	145:64910690c574	429	* Defines the configuration data structure to initialize the OSC.
AnnaBridge	145:64910690c574	430	* When porting to a new board, set the following members
AnnaBridge	145:64910690c574	431	* according to the board setting:
AnnaBridge	145:64910690c574	432	* 1. freq: The external frequency.
AnnaBridge	145:64910690c574	433	* 2. workMode: The OSC module mode.
AnnaBridge	145:64910690c574	434	*/
AnnaBridge	145:64910690c574	435	typedef struct _osc_config
AnnaBridge	145:64910690c574	436	{
AnnaBridge	145:64910690c574	437	uint32_t freq; /!< External clock frequency. /
AnnaBridge	145:64910690c574	438	uint8_t capLoad; /!< Capacitor load setting. /
AnnaBridge	145:64910690c574	439	osc_mode_t workMode; /!< OSC work mode setting. /
AnnaBridge	145:64910690c574	440	oscer_config_t oscerConfig; /!< Configuration for OSCERCLK. /
AnnaBridge	145:64910690c574	441	} osc_config_t;
AnnaBridge	145:64910690c574	442
AnnaBridge	145:64910690c574	443	/! @brief MCG FLL reference clock source select. /
AnnaBridge	145:64910690c574	444	typedef enum _mcg_fll_src
AnnaBridge	145:64910690c574	445	{
AnnaBridge	145:64910690c574	446	kMCG_FllSrcExternal, /!< External reference clock is selected /
AnnaBridge	145:64910690c574	447	kMCG_FllSrcInternal /!< The slow internal reference clock is selected /
AnnaBridge	145:64910690c574	448	} mcg_fll_src_t;
AnnaBridge	145:64910690c574	449
AnnaBridge	145:64910690c574	450	/! @brief MCG internal reference clock select /
AnnaBridge	145:64910690c574	451	typedef enum _mcg_irc_mode
AnnaBridge	145:64910690c574	452	{
AnnaBridge	145:64910690c574	453	kMCG_IrcSlow, /!< Slow internal reference clock selected /
AnnaBridge	145:64910690c574	454	kMCG_IrcFast /!< Fast internal reference clock selected /
AnnaBridge	145:64910690c574	455	} mcg_irc_mode_t;
AnnaBridge	145:64910690c574	456
AnnaBridge	145:64910690c574	457	/! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference /
AnnaBridge	145:64910690c574	458	typedef enum _mcg_dmx32
AnnaBridge	145:64910690c574	459	{
AnnaBridge	145:64910690c574	460	kMCG_Dmx32Default, /!< DCO has a default range of 25% /
AnnaBridge	145:64910690c574	461	kMCG_Dmx32Fine /!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference /
AnnaBridge	145:64910690c574	462	} mcg_dmx32_t;
AnnaBridge	145:64910690c574	463
AnnaBridge	145:64910690c574	464	/! @brief MCG DCO range select /
AnnaBridge	145:64910690c574	465	typedef enum _mcg_drs
AnnaBridge	145:64910690c574	466	{
AnnaBridge	145:64910690c574	467	kMCG_DrsLow, /!< Low frequency range /
AnnaBridge	145:64910690c574	468	kMCG_DrsMid, /!< Mid frequency range /
AnnaBridge	145:64910690c574	469	kMCG_DrsMidHigh, /!< Mid-High frequency range /
AnnaBridge	145:64910690c574	470	kMCG_DrsHigh /!< High frequency range /
AnnaBridge	145:64910690c574	471	} mcg_drs_t;
AnnaBridge	145:64910690c574	472
AnnaBridge	145:64910690c574	473	/! @brief MCG PLL reference clock select /
AnnaBridge	145:64910690c574	474	typedef enum _mcg_pll_ref_src
AnnaBridge	145:64910690c574	475	{
AnnaBridge	145:64910690c574	476	kMCG_PllRefOsc0, /!< Selects OSC0 as PLL reference clock /
AnnaBridge	145:64910690c574	477	kMCG_PllRefOsc1 /!< Selects OSC1 as PLL reference clock /
AnnaBridge	145:64910690c574	478	} mcg_pll_ref_src_t;
AnnaBridge	145:64910690c574	479
AnnaBridge	145:64910690c574	480	/! @brief MCGOUT clock source. /
AnnaBridge	145:64910690c574	481	typedef enum _mcg_clkout_src
AnnaBridge	145:64910690c574	482	{
AnnaBridge	145:64910690c574	483	kMCG_ClkOutSrcOut, /!< Output of the FLL is selected (reset default) /
AnnaBridge	145:64910690c574	484	kMCG_ClkOutSrcInternal, /!< Internal reference clock is selected /
AnnaBridge	145:64910690c574	485	kMCG_ClkOutSrcExternal, /!< External reference clock is selected /
AnnaBridge	145:64910690c574	486	} mcg_clkout_src_t;
AnnaBridge	145:64910690c574	487
AnnaBridge	145:64910690c574	488	/! @brief MCG Automatic Trim Machine Select /
AnnaBridge	145:64910690c574	489	typedef enum _mcg_atm_select
AnnaBridge	145:64910690c574	490	{
AnnaBridge	145:64910690c574	491	kMCG_AtmSel32k, /!< 32 kHz Internal Reference Clock selected /
AnnaBridge	145:64910690c574	492	kMCG_AtmSel4m /!< 4 MHz Internal Reference Clock selected /
AnnaBridge	145:64910690c574	493	} mcg_atm_select_t;
AnnaBridge	145:64910690c574	494
AnnaBridge	145:64910690c574	495	/! @brief MCG OSC Clock Select /
AnnaBridge	145:64910690c574	496	typedef enum _mcg_oscsel
AnnaBridge	145:64910690c574	497	{
AnnaBridge	145:64910690c574	498	kMCG_OscselOsc, /!< Selects System Oscillator (OSCCLK) /
AnnaBridge	145:64910690c574	499	kMCG_OscselRtc, /!< Selects 32 kHz RTC Oscillator /
AnnaBridge	145:64910690c574	500	kMCG_OscselIrc /!< Selects 48 MHz IRC Oscillator /
AnnaBridge	145:64910690c574	501	} mcg_oscsel_t;
AnnaBridge	145:64910690c574	502
AnnaBridge	145:64910690c574	503	/! @brief MCG PLLCS select /
AnnaBridge	145:64910690c574	504	typedef enum _mcg_pll_clk_select
AnnaBridge	145:64910690c574	505	{
AnnaBridge	145:64910690c574	506	kMCG_PllClkSelPll0, /!< PLL0 output clock is selected /
AnnaBridge	145:64910690c574	507	kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
AnnaBridge	145:64910690c574	508	} mcg_pll_clk_select_t;
AnnaBridge	145:64910690c574	509
AnnaBridge	145:64910690c574	510	/! @brief MCG clock monitor mode. /
AnnaBridge	145:64910690c574	511	typedef enum _mcg_monitor_mode
AnnaBridge	145:64910690c574	512	{
AnnaBridge	145:64910690c574	513	kMCG_MonitorNone, /!< Clock monitor is disabled. /
AnnaBridge	145:64910690c574	514	kMCG_MonitorInt, /!< Trigger interrupt when clock lost. /
AnnaBridge	145:64910690c574	515	kMCG_MonitorReset /!< System reset when clock lost. /
AnnaBridge	145:64910690c574	516	} mcg_monitor_mode_t;
AnnaBridge	145:64910690c574	517
AnnaBridge	145:64910690c574	518	/! @brief MCG status. /
AnnaBridge	145:64910690c574	519	enum _mcg_status
AnnaBridge	145:64910690c574	520	{
AnnaBridge	145:64910690c574	521	kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /!< Can't switch to target mode. /
AnnaBridge	145:64910690c574	522	kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
AnnaBridge	145:64910690c574	523	function. */
AnnaBridge	145:64910690c574	524	kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /!< Invalid bus clock for ATM. /
AnnaBridge	145:64910690c574	525	kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /!< Invalid desired frequency for ATM. /
AnnaBridge	145:64910690c574	526	kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /!< IRC is used when using ATM. /
AnnaBridge	145:64910690c574	527	kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /!< Hardware fail occurs during ATM. /
AnnaBridge	145:64910690c574	528	kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
AnnaBridge	145:64910690c574	529	it is in use. */
AnnaBridge	145:64910690c574	530	};
AnnaBridge	145:64910690c574	531
AnnaBridge	145:64910690c574	532	/! @brief MCG status flags. /
AnnaBridge	145:64910690c574	533	enum _mcg_status_flags_t
AnnaBridge	145:64910690c574	534	{
AnnaBridge	145:64910690c574	535	kMCG_Osc0LostFlag = (1U << 0U), /!< OSC0 lost. /
AnnaBridge	145:64910690c574	536	kMCG_Osc0InitFlag = (1U << 1U), /!< OSC0 crystal initialized. /
AnnaBridge	145:64910690c574	537	kMCG_RtcOscLostFlag = (1U << 4U), /!< RTC OSC lost. /
AnnaBridge	145:64910690c574	538	kMCG_Pll0LostFlag = (1U << 5U), /!< PLL0 lost. /
AnnaBridge	145:64910690c574	539	kMCG_Pll0LockFlag = (1U << 6U), /!< PLL0 locked. /
AnnaBridge	145:64910690c574	540	};
AnnaBridge	145:64910690c574	541
AnnaBridge	145:64910690c574	542	/! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. /
AnnaBridge	145:64910690c574	543	enum _mcg_irclk_enable_mode
AnnaBridge	145:64910690c574	544	{
AnnaBridge	145:64910690c574	545	kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /!< MCGIRCLK enable. /
AnnaBridge	145:64910690c574	546	kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /!< MCGIRCLK enable in stop mode. /
AnnaBridge	145:64910690c574	547	};
AnnaBridge	145:64910690c574	548
AnnaBridge	145:64910690c574	549	/! @brief MCG PLL clock enable mode definition. /
AnnaBridge	145:64910690c574	550	enum _mcg_pll_enable_mode
AnnaBridge	145:64910690c574	551	{
AnnaBridge	145:64910690c574	552	kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
AnnaBridge	145:64910690c574	553	MCG clock mode. Generally, the PLL
AnnaBridge	145:64910690c574	554	is disabled in FLL modes
AnnaBridge	145:64910690c574	555	(FEI/FBI/FEE/FBE). Setting the PLL clock
AnnaBridge	145:64910690c574	556	enable independent, enables the
AnnaBridge	145:64910690c574	557	PLL in the FLL modes. */
AnnaBridge	145:64910690c574	558	kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /!< MCGPLLCLK enable in STOP mode. /
AnnaBridge	145:64910690c574	559	};
AnnaBridge	145:64910690c574	560
AnnaBridge	145:64910690c574	561	/! @brief MCG mode definitions /
AnnaBridge	145:64910690c574	562	typedef enum _mcg_mode
AnnaBridge	145:64910690c574	563	{
AnnaBridge	145:64910690c574	564	kMCG_ModeFEI = 0U, /!< FEI - FLL Engaged Internal /
AnnaBridge	145:64910690c574	565	kMCG_ModeFBI, /!< FBI - FLL Bypassed Internal /
AnnaBridge	145:64910690c574	566	kMCG_ModeBLPI, /!< BLPI - Bypassed Low Power Internal /
AnnaBridge	145:64910690c574	567	kMCG_ModeFEE, /!< FEE - FLL Engaged External /
AnnaBridge	145:64910690c574	568	kMCG_ModeFBE, /!< FBE - FLL Bypassed External /
AnnaBridge	145:64910690c574	569	kMCG_ModeBLPE, /!< BLPE - Bypassed Low Power External /
AnnaBridge	145:64910690c574	570	kMCG_ModePBE, /!< PBE - PLL Bypassed External /
AnnaBridge	145:64910690c574	571	kMCG_ModePEE, /!< PEE - PLL Engaged External /
AnnaBridge	145:64910690c574	572	kMCG_ModeError /!< Unknown mode /
AnnaBridge	145:64910690c574	573	} mcg_mode_t;
AnnaBridge	145:64910690c574	574
AnnaBridge	145:64910690c574	575	/! @brief MCG PLL configuration. /
AnnaBridge	145:64910690c574	576	typedef struct _mcg_pll_config
AnnaBridge	145:64910690c574	577	{
AnnaBridge	145:64910690c574	578	uint8_t enableMode; /!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. /
AnnaBridge	145:64910690c574	579	uint8_t prdiv; /!< Reference divider PRDIV. /
AnnaBridge	145:64910690c574	580	uint8_t vdiv; /!< VCO divider VDIV. /
AnnaBridge	145:64910690c574	581	} mcg_pll_config_t;
AnnaBridge	145:64910690c574	582
AnnaBridge	145:64910690c574	583	/*! @brief MCG mode change configuration structure
AnnaBridge	145:64910690c574	584	*
AnnaBridge	145:64910690c574	585	* When porting to a new board, set the following members
AnnaBridge	145:64910690c574	586	* according to the board setting:
AnnaBridge	145:64910690c574	587	* 1. frdiv: If the FLL uses the external reference clock, set this
AnnaBridge	145:64910690c574	588	* value to ensure that the external reference clock divided by frdiv is
AnnaBridge	145:64910690c574	589	* in the 31.25 kHz to 39.0625 kHz range.
AnnaBridge	145:64910690c574	590	* 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
AnnaBridge	145:64910690c574	591	* PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
AnnaBridge	145:64910690c574	592	* FSL_FEATURE_MCG_PLL_REF_MAX range.
AnnaBridge	145:64910690c574	593	*/
AnnaBridge	145:64910690c574	594	typedef struct _mcg_config
AnnaBridge	145:64910690c574	595	{
AnnaBridge	145:64910690c574	596	mcg_mode_t mcgMode; /!< MCG mode. /
AnnaBridge	145:64910690c574	597
AnnaBridge	145:64910690c574	598	/* ----------------------- MCGIRCCLK settings ------------------------ */
AnnaBridge	145:64910690c574	599	uint8_t irclkEnableMode; /!< MCGIRCLK enable mode. /
AnnaBridge	145:64910690c574	600	mcg_irc_mode_t ircs; /!< Source, MCG_C2[IRCS]. /
AnnaBridge	145:64910690c574	601	uint8_t fcrdiv; /!< Divider, MCG_SC[FCRDIV]. /
AnnaBridge	145:64910690c574	602
AnnaBridge	145:64910690c574	603	/* ------------------------ MCG FLL settings ------------------------- */
AnnaBridge	145:64910690c574	604	uint8_t frdiv; /!< Divider MCG_C1[FRDIV]. /
AnnaBridge	145:64910690c574	605	mcg_drs_t drs; /!< DCO range MCG_C4[DRST_DRS]. /
AnnaBridge	145:64910690c574	606	mcg_dmx32_t dmx32; /!< MCG_C4[DMX32]. /
AnnaBridge	145:64910690c574	607	mcg_oscsel_t oscsel; /!< OSC select MCG_C7[OSCSEL]. /
AnnaBridge	145:64910690c574	608
AnnaBridge	145:64910690c574	609	/* ------------------------ MCG PLL settings ------------------------- */
AnnaBridge	145:64910690c574	610	mcg_pll_config_t pll0Config; /!< MCGPLL0CLK configuration. /
AnnaBridge	145:64910690c574	611
AnnaBridge	145:64910690c574	612	} mcg_config_t;
AnnaBridge	145:64910690c574	613
AnnaBridge	145:64910690c574	614	/*******************************************************************************
AnnaBridge	145:64910690c574	615	* API
AnnaBridge	145:64910690c574	616	******************************************************************************/
AnnaBridge	145:64910690c574	617
AnnaBridge	145:64910690c574	618	#if defined(__cplusplus)
AnnaBridge	145:64910690c574	619	extern "C" {
AnnaBridge	145:64910690c574	620	#endif /* __cplusplus */
AnnaBridge	145:64910690c574	621
AnnaBridge	145:64910690c574	622	/*!
AnnaBridge	145:64910690c574	623	* @brief Enable the clock for specific IP.
AnnaBridge	145:64910690c574	624	*
AnnaBridge	145:64910690c574	625	* @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge	145:64910690c574	626	*/
AnnaBridge	145:64910690c574	627	static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge	145:64910690c574	628	{
AnnaBridge	145:64910690c574	629	uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge	145:64910690c574	630	((volatile uint32_t )regAddr) \|= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge	145:64910690c574	631	}
AnnaBridge	145:64910690c574	632
AnnaBridge	145:64910690c574	633	/*!
AnnaBridge	145:64910690c574	634	* @brief Disable the clock for specific IP.
AnnaBridge	145:64910690c574	635	*
AnnaBridge	145:64910690c574	636	* @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge	145:64910690c574	637	*/
AnnaBridge	145:64910690c574	638	static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge	145:64910690c574	639	{
AnnaBridge	145:64910690c574	640	uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge	145:64910690c574	641	((volatile uint32_t )regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge	145:64910690c574	642	}
AnnaBridge	145:64910690c574	643
AnnaBridge	145:64910690c574	644	/*!
AnnaBridge	145:64910690c574	645	* @brief Set ERCLK32K source.
AnnaBridge	145:64910690c574	646	*
AnnaBridge	145:64910690c574	647	* @param src The value to set ERCLK32K clock source.
AnnaBridge	145:64910690c574	648	*/
AnnaBridge	145:64910690c574	649	static inline void CLOCK_SetEr32kClock(uint32_t src)
AnnaBridge	145:64910690c574	650	{
AnnaBridge	145:64910690c574	651	SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) \| SIM_SOPT1_OSC32KSEL(src));
AnnaBridge	145:64910690c574	652	}
AnnaBridge	145:64910690c574	653
AnnaBridge	145:64910690c574	654	/*!
AnnaBridge	145:64910690c574	655	* @brief Set EMVSIM clock source.
AnnaBridge	145:64910690c574	656	*
AnnaBridge	145:64910690c574	657	* @param src The value to set EMVSIM clock source.
AnnaBridge	145:64910690c574	658	*/
AnnaBridge	145:64910690c574	659	static inline void CLOCK_SetEmvsimClock(uint32_t src)
AnnaBridge	145:64910690c574	660	{
AnnaBridge	145:64910690c574	661	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_EMVSIMSRC_MASK) \| SIM_SOPT2_EMVSIMSRC(src));
AnnaBridge	145:64910690c574	662	}
AnnaBridge	145:64910690c574	663
AnnaBridge	145:64910690c574	664	/*!
AnnaBridge	145:64910690c574	665	* @brief Set LPUART clock source.
AnnaBridge	145:64910690c574	666	*
AnnaBridge	145:64910690c574	667	* @param src The value to set LPUART clock source.
AnnaBridge	145:64910690c574	668	*/
AnnaBridge	145:64910690c574	669	static inline void CLOCK_SetLpuartClock(uint32_t src)
AnnaBridge	145:64910690c574	670	{
AnnaBridge	145:64910690c574	671	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) \| SIM_SOPT2_LPUARTSRC(src));
AnnaBridge	145:64910690c574	672	}
AnnaBridge	145:64910690c574	673
AnnaBridge	145:64910690c574	674	/*!
AnnaBridge	145:64910690c574	675	* @brief Set TPM clock source.
AnnaBridge	145:64910690c574	676	*
AnnaBridge	145:64910690c574	677	* @param src The value to set TPM clock source.
AnnaBridge	145:64910690c574	678	*/
AnnaBridge	145:64910690c574	679	static inline void CLOCK_SetTpmClock(uint32_t src)
AnnaBridge	145:64910690c574	680	{
AnnaBridge	145:64910690c574	681	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) \| SIM_SOPT2_TPMSRC(src));
AnnaBridge	145:64910690c574	682	}
AnnaBridge	145:64910690c574	683
AnnaBridge	145:64910690c574	684	/*!
AnnaBridge	145:64910690c574	685	* @brief Set FLEXIO clock source.
AnnaBridge	145:64910690c574	686	*
AnnaBridge	145:64910690c574	687	* @param src The value to set FLEXIO clock source.
AnnaBridge	145:64910690c574	688	*/
AnnaBridge	145:64910690c574	689	static inline void CLOCK_SetFlexio0Clock(uint32_t src)
AnnaBridge	145:64910690c574	690	{
AnnaBridge	145:64910690c574	691	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) \| SIM_SOPT2_FLEXIOSRC(src));
AnnaBridge	145:64910690c574	692	}
AnnaBridge	145:64910690c574	693
AnnaBridge	145:64910690c574	694	/*!
AnnaBridge	145:64910690c574	695	* @brief Set PLLFLLSEL clock source.
AnnaBridge	145:64910690c574	696	*
AnnaBridge	145:64910690c574	697	* @param src The value to set PLLFLLSEL clock source.
AnnaBridge	145:64910690c574	698	*/
AnnaBridge	145:64910690c574	699	static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
AnnaBridge	145:64910690c574	700	{
AnnaBridge	145:64910690c574	701	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) \| SIM_SOPT2_PLLFLLSEL(src));
AnnaBridge	145:64910690c574	702	SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) \| SIM_CLKDIV3_PLLFLLFRAC(fracValue);
AnnaBridge	145:64910690c574	703	}
AnnaBridge	145:64910690c574	704
AnnaBridge	145:64910690c574	705	/*!
AnnaBridge	145:64910690c574	706	* @brief Set CLKOUT source.
AnnaBridge	145:64910690c574	707	*
AnnaBridge	145:64910690c574	708	* @param src The value to set CLKOUT source.
AnnaBridge	145:64910690c574	709	*/
AnnaBridge	145:64910690c574	710	static inline void CLOCK_SetClkOutClock(uint32_t src)
AnnaBridge	145:64910690c574	711	{
AnnaBridge	145:64910690c574	712	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUT_MASK) \| SIM_SOPT2_CLKOUT(src));
AnnaBridge	145:64910690c574	713	}
AnnaBridge	145:64910690c574	714
AnnaBridge	145:64910690c574	715	/*!
AnnaBridge	145:64910690c574	716	* @brief Set RTC_CLKOUT source.
AnnaBridge	145:64910690c574	717	*
AnnaBridge	145:64910690c574	718	* @param src The value to set RTC_CLKOUT source.
AnnaBridge	145:64910690c574	719	*/
AnnaBridge	145:64910690c574	720	static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
AnnaBridge	145:64910690c574	721	{
AnnaBridge	145:64910690c574	722	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTS_MASK) \| SIM_SOPT2_RTCCLKOUTS(src));
AnnaBridge	145:64910690c574	723	}
AnnaBridge	145:64910690c574	724
AnnaBridge	145:64910690c574	725	/*! @brief Enable USB FS clock.
AnnaBridge	145:64910690c574	726	*
AnnaBridge	145:64910690c574	727	* @param src USB FS clock source.
AnnaBridge	145:64910690c574	728	* @param freq The frequency specified by src.
AnnaBridge	145:64910690c574	729	* @retval true The clock is set successfully.
AnnaBridge	145:64910690c574	730	* @retval false The clock source is invalid to get proper USB FS clock.
AnnaBridge	145:64910690c574	731	*/
AnnaBridge	145:64910690c574	732	bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
AnnaBridge	145:64910690c574	733
AnnaBridge	145:64910690c574	734	/*! @brief Disable USB FS clock.
AnnaBridge	145:64910690c574	735	*
AnnaBridge	145:64910690c574	736	* Disable USB FS clock.
AnnaBridge	145:64910690c574	737	*/
AnnaBridge	145:64910690c574	738	static inline void CLOCK_DisableUsbfs0Clock(void)
AnnaBridge	145:64910690c574	739	{
AnnaBridge	145:64910690c574	740	CLOCK_DisableClock(kCLOCK_Usbfs0);
AnnaBridge	145:64910690c574	741	}
AnnaBridge	145:64910690c574	742
AnnaBridge	145:64910690c574	743	/*!
AnnaBridge	145:64910690c574	744	* @brief System clock divider
AnnaBridge	145:64910690c574	745	*
AnnaBridge	145:64910690c574	746	* Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV4], SIM_CLKDIV1[OUTDIV5].
AnnaBridge	145:64910690c574	747	*
AnnaBridge	145:64910690c574	748	* @param outdiv1 Clock 1 output divider value.
AnnaBridge	145:64910690c574	749	*
AnnaBridge	145:64910690c574	750	* @param outdiv2 Clock 2 output divider value.
AnnaBridge	145:64910690c574	751	*
AnnaBridge	145:64910690c574	752	* @param outdiv4 Clock 4 output divider value.
AnnaBridge	145:64910690c574	753	*
AnnaBridge	145:64910690c574	754	* @param outdiv5 Clock 5 output divider value.
AnnaBridge	145:64910690c574	755	*/
AnnaBridge	145:64910690c574	756	static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv4, uint32_t outdiv5)
AnnaBridge	145:64910690c574	757	{
AnnaBridge	145:64910690c574	758	SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) \| SIM_CLKDIV1_OUTDIV2(outdiv2) \| SIM_CLKDIV1_OUTDIV4(outdiv4) \|
AnnaBridge	145:64910690c574	759	SIM_CLKDIV1_OUTDIV5(outdiv5);
AnnaBridge	145:64910690c574	760	}
AnnaBridge	145:64910690c574	761
AnnaBridge	145:64910690c574	762	/*!
AnnaBridge	145:64910690c574	763	* @brief Gets the clock frequency for a specific clock name.
AnnaBridge	145:64910690c574	764	*
AnnaBridge	145:64910690c574	765	* This function checks the current clock configurations and then calculates
AnnaBridge	145:64910690c574	766	* the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge	145:64910690c574	767	* The MCG must be properly configured before using this function.
AnnaBridge	145:64910690c574	768	*
AnnaBridge	145:64910690c574	769	* @param clockName Clock names defined in clock_name_t
AnnaBridge	145:64910690c574	770	* @return Clock frequency value in Hertz
AnnaBridge	145:64910690c574	771	*/
AnnaBridge	145:64910690c574	772	uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge	145:64910690c574	773
AnnaBridge	145:64910690c574	774	/*!
AnnaBridge	145:64910690c574	775	* @brief Get the core clock or system clock frequency.
AnnaBridge	145:64910690c574	776	*
AnnaBridge	145:64910690c574	777	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	778	*/
AnnaBridge	145:64910690c574	779	uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge	145:64910690c574	780
AnnaBridge	145:64910690c574	781	/*!
AnnaBridge	145:64910690c574	782	* @brief Get the platform clock frequency.
AnnaBridge	145:64910690c574	783	*
AnnaBridge	145:64910690c574	784	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	785	*/
AnnaBridge	145:64910690c574	786	uint32_t CLOCK_GetPlatClkFreq(void);
AnnaBridge	145:64910690c574	787
AnnaBridge	145:64910690c574	788	/*!
AnnaBridge	145:64910690c574	789	* @brief Get the bus clock frequency.
AnnaBridge	145:64910690c574	790	*
AnnaBridge	145:64910690c574	791	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	792	*/
AnnaBridge	145:64910690c574	793	uint32_t CLOCK_GetBusClkFreq(void);
AnnaBridge	145:64910690c574	794
AnnaBridge	145:64910690c574	795	/*!
AnnaBridge	145:64910690c574	796	* @brief Get the flash clock frequency.
AnnaBridge	145:64910690c574	797	*
AnnaBridge	145:64910690c574	798	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	799	*/
AnnaBridge	145:64910690c574	800	uint32_t CLOCK_GetFlashClkFreq(void);
AnnaBridge	145:64910690c574	801
AnnaBridge	145:64910690c574	802	/*!
AnnaBridge	145:64910690c574	803	* @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
AnnaBridge	145:64910690c574	804	*
AnnaBridge	145:64910690c574	805	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	806	*/
AnnaBridge	145:64910690c574	807	uint32_t CLOCK_GetPllFllSelClkFreq(void);
AnnaBridge	145:64910690c574	808
AnnaBridge	145:64910690c574	809	/*!
AnnaBridge	145:64910690c574	810	* @brief Get the QSPI bus interface clock frequency.
AnnaBridge	145:64910690c574	811	*
AnnaBridge	145:64910690c574	812	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	813	*/
AnnaBridge	145:64910690c574	814	uint32_t CLOCK_GetQspiBusClkFreq(void);
AnnaBridge	145:64910690c574	815
AnnaBridge	145:64910690c574	816	/*!
AnnaBridge	145:64910690c574	817	* @brief Get the external reference 32K clock frequency (ERCLK32K).
AnnaBridge	145:64910690c574	818	*
AnnaBridge	145:64910690c574	819	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	820	*/
AnnaBridge	145:64910690c574	821	uint32_t CLOCK_GetEr32kClkFreq(void);
AnnaBridge	145:64910690c574	822
AnnaBridge	145:64910690c574	823	/*!
AnnaBridge	145:64910690c574	824	* @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
AnnaBridge	145:64910690c574	825	*
AnnaBridge	145:64910690c574	826	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	827	*/
AnnaBridge	145:64910690c574	828	uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
AnnaBridge	145:64910690c574	829
AnnaBridge	145:64910690c574	830	/*!
AnnaBridge	145:64910690c574	831	* @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
AnnaBridge	145:64910690c574	832	*
AnnaBridge	145:64910690c574	833	* @return Clock frequency in Hz.
AnnaBridge	145:64910690c574	834	*/
AnnaBridge	145:64910690c574	835	uint32_t CLOCK_GetOsc0ErClkFreq(void);
AnnaBridge	145:64910690c574	836
AnnaBridge	145:64910690c574	837	/*!
AnnaBridge	145:64910690c574	838	* @brief Set the clock configure in SIM module.
AnnaBridge	145:64910690c574	839	*
AnnaBridge	145:64910690c574	840	* This function sets system layer clock settings in SIM module.
AnnaBridge	145:64910690c574	841	*
AnnaBridge	145:64910690c574	842	* @param config Pointer to the configure structure.
AnnaBridge	145:64910690c574	843	*/
AnnaBridge	145:64910690c574	844	void CLOCK_SetSimConfig(sim_clock_config_t const *config);
AnnaBridge	145:64910690c574	845
AnnaBridge	145:64910690c574	846	/*!
AnnaBridge	145:64910690c574	847	* @brief Set the system clock dividers in SIM to safe value.
AnnaBridge	145:64910690c574	848	*
AnnaBridge	145:64910690c574	849	* The system level clocks (core clock, bus clock, flexbus clock and flash clock)
AnnaBridge	145:64910690c574	850	* must be in allowed ranges. During MCG clock mode switch, the MCG output clock
AnnaBridge	145:64910690c574	851	* changes then the system level clocks may be out of range. This function could
AnnaBridge	145:64910690c574	852	* be used before MCG mode change, to make sure system level clocks are in allowed
AnnaBridge	145:64910690c574	853	* range.
AnnaBridge	145:64910690c574	854	*
AnnaBridge	145:64910690c574	855	* @param config Pointer to the configure structure.
AnnaBridge	145:64910690c574	856	*/
AnnaBridge	145:64910690c574	857	static inline void CLOCK_SetSimSafeDivs(void)
AnnaBridge	145:64910690c574	858	{
AnnaBridge	145:64910690c574	859	SIM->CLKDIV1 = 0x15051000U;
AnnaBridge	145:64910690c574	860	}
AnnaBridge	145:64910690c574	861
AnnaBridge	145:64910690c574	862	/! @name MCG frequency functions. /
AnnaBridge	145:64910690c574	863	/@{/
AnnaBridge	145:64910690c574	864
AnnaBridge	145:64910690c574	865	/*!
AnnaBridge	145:64910690c574	866	* @brief Gets the MCG output clock (MCGOUTCLK) frequency.
AnnaBridge	145:64910690c574	867	*
AnnaBridge	145:64910690c574	868	* This function gets the MCG output clock frequency in Hz based on the current MCG
AnnaBridge	145:64910690c574	869	* register value.
AnnaBridge	145:64910690c574	870	*
AnnaBridge	145:64910690c574	871	* @return The frequency of MCGOUTCLK.
AnnaBridge	145:64910690c574	872	*/
AnnaBridge	145:64910690c574	873	uint32_t CLOCK_GetOutClkFreq(void);
AnnaBridge	145:64910690c574	874
AnnaBridge	145:64910690c574	875	/*!
AnnaBridge	145:64910690c574	876	* @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
AnnaBridge	145:64910690c574	877	*
AnnaBridge	145:64910690c574	878	* This function gets the MCG FLL clock frequency in Hz based on the current MCG
AnnaBridge	145:64910690c574	879	* register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
AnnaBridge	145:64910690c574	880	* disabled in low power state in other modes.
AnnaBridge	145:64910690c574	881	*
AnnaBridge	145:64910690c574	882	* @return The frequency of MCGFLLCLK.
AnnaBridge	145:64910690c574	883	*/
AnnaBridge	145:64910690c574	884	uint32_t CLOCK_GetFllFreq(void);
AnnaBridge	145:64910690c574	885
AnnaBridge	145:64910690c574	886	/*!
AnnaBridge	145:64910690c574	887	* @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
AnnaBridge	145:64910690c574	888	*
AnnaBridge	145:64910690c574	889	* This function gets the MCG internal reference clock frequency in Hz based
AnnaBridge	145:64910690c574	890	* on the current MCG register value.
AnnaBridge	145:64910690c574	891	*
AnnaBridge	145:64910690c574	892	* @return The frequency of MCGIRCLK.
AnnaBridge	145:64910690c574	893	*/
AnnaBridge	145:64910690c574	894	uint32_t CLOCK_GetInternalRefClkFreq(void);
AnnaBridge	145:64910690c574	895
AnnaBridge	145:64910690c574	896	/*!
AnnaBridge	145:64910690c574	897	* @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
AnnaBridge	145:64910690c574	898	*
AnnaBridge	145:64910690c574	899	* This function gets the MCG fixed frequency clock frequency in Hz based
AnnaBridge	145:64910690c574	900	* on the current MCG register value.
AnnaBridge	145:64910690c574	901	*
AnnaBridge	145:64910690c574	902	* @return The frequency of MCGFFCLK.
AnnaBridge	145:64910690c574	903	*/
AnnaBridge	145:64910690c574	904	uint32_t CLOCK_GetFixedFreqClkFreq(void);
AnnaBridge	145:64910690c574	905
AnnaBridge	145:64910690c574	906	/*!
AnnaBridge	145:64910690c574	907	* @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
AnnaBridge	145:64910690c574	908	*
AnnaBridge	145:64910690c574	909	* This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
AnnaBridge	145:64910690c574	910	* register value.
AnnaBridge	145:64910690c574	911	*
AnnaBridge	145:64910690c574	912	* @return The frequency of MCGPLL0CLK.
AnnaBridge	145:64910690c574	913	*/
AnnaBridge	145:64910690c574	914	uint32_t CLOCK_GetPll0Freq(void);
AnnaBridge	145:64910690c574	915
AnnaBridge	145:64910690c574	916	/@}/
AnnaBridge	145:64910690c574	917
AnnaBridge	145:64910690c574	918	/! @name MCG clock configuration. /
AnnaBridge	145:64910690c574	919	/@{/
AnnaBridge	145:64910690c574	920
AnnaBridge	145:64910690c574	921	/*!
AnnaBridge	145:64910690c574	922	* @brief Enables or disables the MCG low power.
AnnaBridge	145:64910690c574	923	*
AnnaBridge	145:64910690c574	924	* Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
AnnaBridge	145:64910690c574	925	* in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
AnnaBridge	145:64910690c574	926	* PBI modes, enabling low power sets the MCG to BLPI mode.
AnnaBridge	145:64910690c574	927	* When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
AnnaBridge	145:64910690c574	928	*
AnnaBridge	145:64910690c574	929	* @param enable True to enable MCG low power, false to disable MCG low power.
AnnaBridge	145:64910690c574	930	*/
AnnaBridge	145:64910690c574	931	static inline void CLOCK_SetLowPowerEnable(bool enable)
AnnaBridge	145:64910690c574	932	{
AnnaBridge	145:64910690c574	933	if (enable)
AnnaBridge	145:64910690c574	934	{
AnnaBridge	145:64910690c574	935	MCG->C2 \|= MCG_C2_LP_MASK;
AnnaBridge	145:64910690c574	936	}
AnnaBridge	145:64910690c574	937	else
AnnaBridge	145:64910690c574	938	{
AnnaBridge	145:64910690c574	939	MCG->C2 &= ~MCG_C2_LP_MASK;
AnnaBridge	145:64910690c574	940	}
AnnaBridge	145:64910690c574	941	}
AnnaBridge	145:64910690c574	942
AnnaBridge	145:64910690c574	943	/*!
AnnaBridge	145:64910690c574	944	* @brief Configures the Internal Reference clock (MCGIRCLK).
AnnaBridge	145:64910690c574	945	*
AnnaBridge	145:64910690c574	946	* This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
AnnaBridge	145:64910690c574	947	* source. If the fast IRC is used, this function sets the fast IRC divider.
AnnaBridge	145:64910690c574	948	* This function also sets whether the \c MCGIRCLK is enabled in stop mode.
AnnaBridge	145:64910690c574	949	* Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
AnnaBridge	145:64910690c574	950	* using the function in these modes it is not allowed.
AnnaBridge	145:64910690c574	951	*
AnnaBridge	145:64910690c574	952	* @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge	145:64910690c574	953	* @param ircs MCGIRCLK clock source, choose fast or slow.
AnnaBridge	145:64910690c574	954	* @param fcrdiv Fast IRC divider setting (\c FCRDIV).
AnnaBridge	145:64910690c574	955	* @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
AnnaBridge	145:64910690c574	956	* the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge	145:64910690c574	957	* @retval kStatus_Success MCGIRCLK configuration finished successfully.
AnnaBridge	145:64910690c574	958	*/
AnnaBridge	145:64910690c574	959	status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
AnnaBridge	145:64910690c574	960
AnnaBridge	145:64910690c574	961	/*!
AnnaBridge	145:64910690c574	962	* @brief Selects the MCG external reference clock.
AnnaBridge	145:64910690c574	963	*
AnnaBridge	145:64910690c574	964	* Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
AnnaBridge	145:64910690c574	965	* and waits for the clock source to be stable. Because the external reference
AnnaBridge	145:64910690c574	966	* clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
AnnaBridge	145:64910690c574	967	*
AnnaBridge	145:64910690c574	968	* @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
AnnaBridge	145:64910690c574	969	* @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
AnnaBridge	145:64910690c574	970	* the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge	145:64910690c574	971	* @retval kStatus_Success External reference clock set successfully.
AnnaBridge	145:64910690c574	972	*/
AnnaBridge	145:64910690c574	973	status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
AnnaBridge	145:64910690c574	974
AnnaBridge	145:64910690c574	975	/*!
AnnaBridge	145:64910690c574	976	* @brief Enables the PLL0 in FLL mode.
AnnaBridge	145:64910690c574	977	*
AnnaBridge	145:64910690c574	978	* This function sets us the PLL0 in FLL mode and reconfigures
AnnaBridge	145:64910690c574	979	* the PLL0. Ensure that the PLL reference
AnnaBridge	145:64910690c574	980	* clock is enabled before calling this function and that the PLL0 is not used as a clock source.
AnnaBridge	145:64910690c574	981	* The function CLOCK_CalcPllDiv gets the correct PLL
AnnaBridge	145:64910690c574	982	* divider values.
AnnaBridge	145:64910690c574	983	*
AnnaBridge	145:64910690c574	984	* @param config Pointer to the configuration structure.
AnnaBridge	145:64910690c574	985	*/
AnnaBridge	145:64910690c574	986	void CLOCK_EnablePll0(mcg_pll_config_t const *config);
AnnaBridge	145:64910690c574	987
AnnaBridge	145:64910690c574	988	/*!
AnnaBridge	145:64910690c574	989	* @brief Disables the PLL0 in FLL mode.
AnnaBridge	145:64910690c574	990	*
AnnaBridge	145:64910690c574	991	* This function disables the PLL0 in FLL mode. It should be used together with the
AnnaBridge	145:64910690c574	992	* @ref CLOCK_EnablePll0.
AnnaBridge	145:64910690c574	993	*/
AnnaBridge	145:64910690c574	994	static inline void CLOCK_DisablePll0(void)
AnnaBridge	145:64910690c574	995	{
AnnaBridge	145:64910690c574	996	MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK \| MCG_C5_PLLSTEN0_MASK);
AnnaBridge	145:64910690c574	997	}
AnnaBridge	145:64910690c574	998
AnnaBridge	145:64910690c574	999	/*!
AnnaBridge	145:64910690c574	1000	* @brief Calculates the PLL divider setting for a desired output frequency.
AnnaBridge	145:64910690c574	1001	*
AnnaBridge	145:64910690c574	1002	* This function calculates the correct reference clock divider (\c PRDIV) and
AnnaBridge	145:64910690c574	1003	* VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
AnnaBridge	145:64910690c574	1004	* closest frequency match with the corresponding \c PRDIV/VDIV
AnnaBridge	145:64910690c574	1005	* returned from parameters. If a desired frequency is not valid, this function
AnnaBridge	145:64910690c574	1006	* returns 0.
AnnaBridge	145:64910690c574	1007	*
AnnaBridge	145:64910690c574	1008	* @param refFreq PLL reference clock frequency.
AnnaBridge	145:64910690c574	1009	* @param desireFreq Desired PLL output frequency.
AnnaBridge	145:64910690c574	1010	* @param prdiv PRDIV value to generate desired PLL frequency.
AnnaBridge	145:64910690c574	1011	* @param vdiv VDIV value to generate desired PLL frequency.
AnnaBridge	145:64910690c574	1012	* @return Closest frequency match that the PLL was able generate.
AnnaBridge	145:64910690c574	1013	*/
AnnaBridge	145:64910690c574	1014	uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t prdiv, uint8_t vdiv);
AnnaBridge	145:64910690c574	1015
AnnaBridge	145:64910690c574	1016	/@}/
AnnaBridge	145:64910690c574	1017
AnnaBridge	145:64910690c574	1018	/! @name MCG clock lock monitor functions. /
AnnaBridge	145:64910690c574	1019	/@{/
AnnaBridge	145:64910690c574	1020
AnnaBridge	145:64910690c574	1021	/*!
AnnaBridge	145:64910690c574	1022	* @brief Sets the OSC0 clock monitor mode.
AnnaBridge	145:64910690c574	1023	*
AnnaBridge	145:64910690c574	1024	* This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	145:64910690c574	1025	*
AnnaBridge	145:64910690c574	1026	* @param mode Monitor mode to set.
AnnaBridge	145:64910690c574	1027	*/
AnnaBridge	145:64910690c574	1028	void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	145:64910690c574	1029
AnnaBridge	145:64910690c574	1030	/*!
AnnaBridge	145:64910690c574	1031	* @brief Sets the RTC OSC clock monitor mode.
AnnaBridge	145:64910690c574	1032	*
AnnaBridge	145:64910690c574	1033	* This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	145:64910690c574	1034	*
AnnaBridge	145:64910690c574	1035	* @param mode Monitor mode to set.
AnnaBridge	145:64910690c574	1036	*/
AnnaBridge	145:64910690c574	1037	void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	145:64910690c574	1038
AnnaBridge	145:64910690c574	1039	/*!
AnnaBridge	145:64910690c574	1040	* @brief Sets the PLL0 clock monitor mode.
AnnaBridge	145:64910690c574	1041	*
AnnaBridge	145:64910690c574	1042	* This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	145:64910690c574	1043	*
AnnaBridge	145:64910690c574	1044	* @param mode Monitor mode to set.
AnnaBridge	145:64910690c574	1045	*/
AnnaBridge	145:64910690c574	1046	void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	145:64910690c574	1047
AnnaBridge	145:64910690c574	1048	/*!
AnnaBridge	145:64910690c574	1049	* @brief Gets the MCG status flags.
AnnaBridge	145:64910690c574	1050	*
AnnaBridge	145:64910690c574	1051	* This function gets the MCG clock status flags. All status flags are
AnnaBridge	145:64910690c574	1052	* returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
AnnaBridge	145:64910690c574	1053	* check a specific flag, compare the return value with the flag.
AnnaBridge	145:64910690c574	1054	*
AnnaBridge	145:64910690c574	1055	* Example:
AnnaBridge	145:64910690c574	1056	* @code
AnnaBridge	145:64910690c574	1057	// To check the clock lost lock status of OSC0 and PLL0.
AnnaBridge	145:64910690c574	1058	uint32_t mcgFlags;
AnnaBridge	145:64910690c574	1059
AnnaBridge	145:64910690c574	1060	mcgFlags = CLOCK_GetStatusFlags();
AnnaBridge	145:64910690c574	1061
AnnaBridge	145:64910690c574	1062	if (mcgFlags & kMCG_Osc0LostFlag)
AnnaBridge	145:64910690c574	1063	{
AnnaBridge	145:64910690c574	1064	// OSC0 clock lock lost. Do something.
AnnaBridge	145:64910690c574	1065	}
AnnaBridge	145:64910690c574	1066	if (mcgFlags & kMCG_Pll0LostFlag)
AnnaBridge	145:64910690c574	1067	{
AnnaBridge	145:64910690c574	1068	// PLL0 clock lock lost. Do something.
AnnaBridge	145:64910690c574	1069	}
AnnaBridge	145:64910690c574	1070	@endcode
AnnaBridge	145:64910690c574	1071	*
AnnaBridge	145:64910690c574	1072	* @return Logical OR value of the @ref _mcg_status_flags_t.
AnnaBridge	145:64910690c574	1073	*/
AnnaBridge	145:64910690c574	1074	uint32_t CLOCK_GetStatusFlags(void);
AnnaBridge	145:64910690c574	1075
AnnaBridge	145:64910690c574	1076	/*!
AnnaBridge	145:64910690c574	1077	* @brief Clears the MCG status flags.
AnnaBridge	145:64910690c574	1078	*
AnnaBridge	145:64910690c574	1079	* This function clears the MCG clock lock lost status. The parameter is a logical
AnnaBridge	145:64910690c574	1080	* OR value of the flags to clear. See @ref _mcg_status_flags_t.
AnnaBridge	145:64910690c574	1081	*
AnnaBridge	145:64910690c574	1082	* Example:
AnnaBridge	145:64910690c574	1083	* @code
AnnaBridge	145:64910690c574	1084	// To clear the clock lost lock status flags of OSC0 and PLL0.
AnnaBridge	145:64910690c574	1085
AnnaBridge	145:64910690c574	1086	CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag \| kMCG_Pll0LostFlag);
AnnaBridge	145:64910690c574	1087	@endcode
AnnaBridge	145:64910690c574	1088	*
AnnaBridge	145:64910690c574	1089	* @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge	145:64910690c574	1090	* enumeration @ref _mcg_status_flags_t.
AnnaBridge	145:64910690c574	1091	*/
AnnaBridge	145:64910690c574	1092	void CLOCK_ClearStatusFlags(uint32_t mask);
AnnaBridge	145:64910690c574	1093
AnnaBridge	145:64910690c574	1094	/@}/
AnnaBridge	145:64910690c574	1095
AnnaBridge	145:64910690c574	1096	/*!
AnnaBridge	145:64910690c574	1097	* @name OSC configuration
AnnaBridge	145:64910690c574	1098	* @{
AnnaBridge	145:64910690c574	1099	*/
AnnaBridge	145:64910690c574	1100
AnnaBridge	145:64910690c574	1101	/*!
AnnaBridge	145:64910690c574	1102	* @brief Configures the OSC external reference clock (OSCERCLK).
AnnaBridge	145:64910690c574	1103	*
AnnaBridge	145:64910690c574	1104	* This function configures the OSC external reference clock (OSCERCLK).
AnnaBridge	145:64910690c574	1105	* This is an example to enable the OSCERCLK in normal and stop modes and also set
AnnaBridge	145:64910690c574	1106	* the output divider to 1:
AnnaBridge	145:64910690c574	1107	*
AnnaBridge	145:64910690c574	1108	@code
AnnaBridge	145:64910690c574	1109	oscer_config_t config =
AnnaBridge	145:64910690c574	1110	{
AnnaBridge	145:64910690c574	1111	.enableMode = kOSC_ErClkEnable \| kOSC_ErClkEnableInStop,
AnnaBridge	145:64910690c574	1112	.erclkDiv = 1U,
AnnaBridge	145:64910690c574	1113	};
AnnaBridge	145:64910690c574	1114
AnnaBridge	145:64910690c574	1115	OSC_SetExtRefClkConfig(OSC, &config);
AnnaBridge	145:64910690c574	1116	@endcode
AnnaBridge	145:64910690c574	1117	*
AnnaBridge	145:64910690c574	1118	* @param base OSC peripheral address.
AnnaBridge	145:64910690c574	1119	* @param config Pointer to the configuration structure.
AnnaBridge	145:64910690c574	1120	*/
AnnaBridge	145:64910690c574	1121	static inline void OSC_SetExtRefClkConfig(OSC_Type base, oscer_config_t const config)
AnnaBridge	145:64910690c574	1122	{
AnnaBridge	145:64910690c574	1123	uint8_t reg = base->CR;
AnnaBridge	145:64910690c574	1124
AnnaBridge	145:64910690c574	1125	reg &= ~(OSC_CR_ERCLKEN_MASK \| OSC_CR_EREFSTEN_MASK);
AnnaBridge	145:64910690c574	1126	reg \|= config->enableMode;
AnnaBridge	145:64910690c574	1127
AnnaBridge	145:64910690c574	1128	base->CR = reg;
AnnaBridge	145:64910690c574	1129
AnnaBridge	145:64910690c574	1130	base->DIV = OSC_DIV_ERPS(config->erclkDiv);
AnnaBridge	145:64910690c574	1131	}
AnnaBridge	145:64910690c574	1132
AnnaBridge	145:64910690c574	1133	/*!
AnnaBridge	145:64910690c574	1134	* @brief Sets the capacitor load configuration for the oscillator.
AnnaBridge	145:64910690c574	1135	*
AnnaBridge	145:64910690c574	1136	* This function sets the specified capacitors configuration for the oscillator.
AnnaBridge	145:64910690c574	1137	* This should be done in the early system level initialization function call
AnnaBridge	145:64910690c574	1138	* based on the system configuration.
AnnaBridge	145:64910690c574	1139	*
AnnaBridge	145:64910690c574	1140	* @param base OSC peripheral address.
AnnaBridge	145:64910690c574	1141	* @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
AnnaBridge	145:64910690c574	1142	*
AnnaBridge	145:64910690c574	1143	* Example:
AnnaBridge	145:64910690c574	1144	@code
AnnaBridge	145:64910690c574	1145	// To enable only 2 pF and 8 pF capacitor load, please use like this.
AnnaBridge	145:64910690c574	1146	OSC_SetCapLoad(OSC, kOSC_Cap2P \| kOSC_Cap8P);
AnnaBridge	145:64910690c574	1147	@endcode
AnnaBridge	145:64910690c574	1148	*/
AnnaBridge	145:64910690c574	1149	static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
AnnaBridge	145:64910690c574	1150	{
AnnaBridge	145:64910690c574	1151	uint8_t reg = base->CR;
AnnaBridge	145:64910690c574	1152
AnnaBridge	145:64910690c574	1153	reg &= ~(OSC_CR_SC2P_MASK \| OSC_CR_SC4P_MASK \| OSC_CR_SC8P_MASK \| OSC_CR_SC16P_MASK);
AnnaBridge	145:64910690c574	1154	reg \|= capLoad;
AnnaBridge	145:64910690c574	1155
AnnaBridge	145:64910690c574	1156	base->CR = reg;
AnnaBridge	145:64910690c574	1157	}
AnnaBridge	145:64910690c574	1158
AnnaBridge	145:64910690c574	1159	/*!
AnnaBridge	145:64910690c574	1160	* @brief Initializes the OSC0.
AnnaBridge	145:64910690c574	1161	*
AnnaBridge	145:64910690c574	1162	* This function initializes the OSC0 according to the board configuration.
AnnaBridge	145:64910690c574	1163	*
AnnaBridge	145:64910690c574	1164	* @param config Pointer to the OSC0 configuration structure.
AnnaBridge	145:64910690c574	1165	*/
AnnaBridge	145:64910690c574	1166	void CLOCK_InitOsc0(osc_config_t const *config);
AnnaBridge	145:64910690c574	1167
AnnaBridge	145:64910690c574	1168	/*!
AnnaBridge	145:64910690c574	1169	* @brief Deinitializes the OSC0.
AnnaBridge	145:64910690c574	1170	*
AnnaBridge	145:64910690c574	1171	* This function deinitializes the OSC0.
AnnaBridge	145:64910690c574	1172	*/
AnnaBridge	145:64910690c574	1173	void CLOCK_DeinitOsc0(void);
AnnaBridge	145:64910690c574	1174
AnnaBridge	145:64910690c574	1175	/* @} */
AnnaBridge	145:64910690c574	1176
AnnaBridge	145:64910690c574	1177	/*!
AnnaBridge	145:64910690c574	1178	* @name External clock frequency
AnnaBridge	145:64910690c574	1179	* @{
AnnaBridge	145:64910690c574	1180	*/
AnnaBridge	145:64910690c574	1181
AnnaBridge	145:64910690c574	1182	/*!
AnnaBridge	145:64910690c574	1183	* @brief Sets the XTAL0 frequency based on board settings.
AnnaBridge	145:64910690c574	1184	*
AnnaBridge	145:64910690c574	1185	* @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
AnnaBridge	145:64910690c574	1186	*/
AnnaBridge	145:64910690c574	1187	static inline void CLOCK_SetXtal0Freq(uint32_t freq)
AnnaBridge	145:64910690c574	1188	{
AnnaBridge	145:64910690c574	1189	g_xtal0Freq = freq;
AnnaBridge	145:64910690c574	1190	}
AnnaBridge	145:64910690c574	1191
AnnaBridge	145:64910690c574	1192	/*!
AnnaBridge	145:64910690c574	1193	* @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
AnnaBridge	145:64910690c574	1194	*
AnnaBridge	145:64910690c574	1195	* @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
AnnaBridge	145:64910690c574	1196	*/
AnnaBridge	145:64910690c574	1197	static inline void CLOCK_SetXtal32Freq(uint32_t freq)
AnnaBridge	145:64910690c574	1198	{
AnnaBridge	145:64910690c574	1199	g_xtal32Freq = freq;
AnnaBridge	145:64910690c574	1200	}
AnnaBridge	145:64910690c574	1201	/* @} */
AnnaBridge	145:64910690c574	1202
AnnaBridge	145:64910690c574	1203	/*!
AnnaBridge	145:64910690c574	1204	* @name MCG auto-trim machine.
AnnaBridge	145:64910690c574	1205	* @{
AnnaBridge	145:64910690c574	1206	*/
AnnaBridge	145:64910690c574	1207
AnnaBridge	145:64910690c574	1208	/*!
AnnaBridge	145:64910690c574	1209	* @brief Auto trims the internal reference clock.
AnnaBridge	145:64910690c574	1210	*
AnnaBridge	145:64910690c574	1211	* This function trims the internal reference clock by using the external clock. If
AnnaBridge	145:64910690c574	1212	* successful, it returns the kStatus_Success and the frequency after
AnnaBridge	145:64910690c574	1213	* trimming is received in the parameter @p actualFreq. If an error occurs,
AnnaBridge	145:64910690c574	1214	* the error code is returned.
AnnaBridge	145:64910690c574	1215	*
AnnaBridge	145:64910690c574	1216	* @param extFreq External clock frequency, which should be a bus clock.
AnnaBridge	145:64910690c574	1217	* @param desireFreq Frequency to trim to.
AnnaBridge	145:64910690c574	1218	* @param actualFreq Actual frequency after trimming.
AnnaBridge	145:64910690c574	1219	* @param atms Trim fast or slow internal reference clock.
AnnaBridge	145:64910690c574	1220	* @retval kStatus_Success ATM success.
AnnaBridge	145:64910690c574	1221	* @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
AnnaBridge	145:64910690c574	1222	* @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
AnnaBridge	145:64910690c574	1223	* @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
AnnaBridge	145:64910690c574	1224	* @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
AnnaBridge	145:64910690c574	1225	*/
AnnaBridge	145:64910690c574	1226	status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
AnnaBridge	145:64910690c574	1227	/* @} */
AnnaBridge	145:64910690c574	1228
AnnaBridge	145:64910690c574	1229	/! @name MCG mode functions. /
AnnaBridge	145:64910690c574	1230	/@{/
AnnaBridge	145:64910690c574	1231
AnnaBridge	145:64910690c574	1232	/*!
AnnaBridge	145:64910690c574	1233	* @brief Gets the current MCG mode.
AnnaBridge	145:64910690c574	1234	*
AnnaBridge	145:64910690c574	1235	* This function checks the MCG registers and determines the current MCG mode.
AnnaBridge	145:64910690c574	1236	*
AnnaBridge	145:64910690c574	1237	* @return Current MCG mode or error code; See @ref mcg_mode_t.
AnnaBridge	145:64910690c574	1238	*/
AnnaBridge	145:64910690c574	1239	mcg_mode_t CLOCK_GetMode(void);
AnnaBridge	145:64910690c574	1240
AnnaBridge	145:64910690c574	1241	/*!
AnnaBridge	145:64910690c574	1242	* @brief Sets the MCG to FEI mode.
AnnaBridge	145:64910690c574	1243	*
AnnaBridge	145:64910690c574	1244	* This function sets the MCG to FEI mode. If setting to FEI mode fails
AnnaBridge	145:64910690c574	1245	* from the current mode, this function returns an error.
AnnaBridge	145:64910690c574	1246	*
AnnaBridge	145:64910690c574	1247	* @param dmx32 DMX32 in FEI mode.
AnnaBridge	145:64910690c574	1248	* @param drs The DCO range selection.
AnnaBridge	145:64910690c574	1249	* @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
AnnaBridge	145:64910690c574	1250	* NULL does not cause a delay.
AnnaBridge	145:64910690c574	1251	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1252	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1253	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	145:64910690c574	1254	* to a frequency above 32768 Hz.
AnnaBridge	145:64910690c574	1255	*/
AnnaBridge	145:64910690c574	1256	status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	145:64910690c574	1257
AnnaBridge	145:64910690c574	1258	/*!
AnnaBridge	145:64910690c574	1259	* @brief Sets the MCG to FEE mode.
AnnaBridge	145:64910690c574	1260	*
AnnaBridge	145:64910690c574	1261	* This function sets the MCG to FEE mode. If setting to FEE mode fails
AnnaBridge	145:64910690c574	1262	* from the current mode, this function returns an error.
AnnaBridge	145:64910690c574	1263	*
AnnaBridge	145:64910690c574	1264	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	145:64910690c574	1265	* @param dmx32 DMX32 in FEE mode.
AnnaBridge	145:64910690c574	1266	* @param drs The DCO range selection.
AnnaBridge	145:64910690c574	1267	* @param fllStableDelay Delay function to make sure FLL is stable. Passing
AnnaBridge	145:64910690c574	1268	* NULL does not cause a delay.
AnnaBridge	145:64910690c574	1269	*
AnnaBridge	145:64910690c574	1270	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1271	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1272	*/
AnnaBridge	145:64910690c574	1273	status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	145:64910690c574	1274
AnnaBridge	145:64910690c574	1275	/*!
AnnaBridge	145:64910690c574	1276	* @brief Sets the MCG to FBI mode.
AnnaBridge	145:64910690c574	1277	*
AnnaBridge	145:64910690c574	1278	* This function sets the MCG to FBI mode. If setting to FBI mode fails
AnnaBridge	145:64910690c574	1279	* from the current mode, this function returns an error.
AnnaBridge	145:64910690c574	1280	*
AnnaBridge	145:64910690c574	1281	* @param dmx32 DMX32 in FBI mode.
AnnaBridge	145:64910690c574	1282	* @param drs The DCO range selection.
AnnaBridge	145:64910690c574	1283	* @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge	145:64910690c574	1284	* is not used in FBI mode, this parameter can be NULL. Passing
AnnaBridge	145:64910690c574	1285	* NULL does not cause a delay.
AnnaBridge	145:64910690c574	1286	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1287	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1288	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	145:64910690c574	1289	* to frequency above 32768 Hz.
AnnaBridge	145:64910690c574	1290	*/
AnnaBridge	145:64910690c574	1291	status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	145:64910690c574	1292
AnnaBridge	145:64910690c574	1293	/*!
AnnaBridge	145:64910690c574	1294	* @brief Sets the MCG to FBE mode.
AnnaBridge	145:64910690c574	1295	*
AnnaBridge	145:64910690c574	1296	* This function sets the MCG to FBE mode. If setting to FBE mode fails
AnnaBridge	145:64910690c574	1297	* from the current mode, this function returns an error.
AnnaBridge	145:64910690c574	1298	*
AnnaBridge	145:64910690c574	1299	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	145:64910690c574	1300	* @param dmx32 DMX32 in FBE mode.
AnnaBridge	145:64910690c574	1301	* @param drs The DCO range selection.
AnnaBridge	145:64910690c574	1302	* @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge	145:64910690c574	1303	* is not used in FBE mode, this parameter can be NULL. Passing NULL
AnnaBridge	145:64910690c574	1304	* does not cause a delay.
AnnaBridge	145:64910690c574	1305	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1306	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1307	*/
AnnaBridge	145:64910690c574	1308	status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	145:64910690c574	1309
AnnaBridge	145:64910690c574	1310	/*!
AnnaBridge	145:64910690c574	1311	* @brief Sets the MCG to BLPI mode.
AnnaBridge	145:64910690c574	1312	*
AnnaBridge	145:64910690c574	1313	* This function sets the MCG to BLPI mode. If setting to BLPI mode fails
AnnaBridge	145:64910690c574	1314	* from the current mode, this function returns an error.
AnnaBridge	145:64910690c574	1315	*
AnnaBridge	145:64910690c574	1316	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1317	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1318	*/
AnnaBridge	145:64910690c574	1319	status_t CLOCK_SetBlpiMode(void);
AnnaBridge	145:64910690c574	1320
AnnaBridge	145:64910690c574	1321	/*!
AnnaBridge	145:64910690c574	1322	* @brief Sets the MCG to BLPE mode.
AnnaBridge	145:64910690c574	1323	*
AnnaBridge	145:64910690c574	1324	* This function sets the MCG to BLPE mode. If setting to BLPE mode fails
AnnaBridge	145:64910690c574	1325	* from the current mode, this function returns an error.
AnnaBridge	145:64910690c574	1326	*
AnnaBridge	145:64910690c574	1327	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1328	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1329	*/
AnnaBridge	145:64910690c574	1330	status_t CLOCK_SetBlpeMode(void);
AnnaBridge	145:64910690c574	1331
AnnaBridge	145:64910690c574	1332	/*!
AnnaBridge	145:64910690c574	1333	* @brief Sets the MCG to PBE mode.
AnnaBridge	145:64910690c574	1334	*
AnnaBridge	145:64910690c574	1335	* This function sets the MCG to PBE mode. If setting to PBE mode fails
AnnaBridge	145:64910690c574	1336	* from the current mode, this function returns an error.
AnnaBridge	145:64910690c574	1337	*
AnnaBridge	145:64910690c574	1338	* @param pllcs The PLL selection, PLLCS.
AnnaBridge	145:64910690c574	1339	* @param config Pointer to the PLL configuration.
AnnaBridge	145:64910690c574	1340	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1341	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1342	*
AnnaBridge	145:64910690c574	1343	* @note
AnnaBridge	145:64910690c574	1344	* 1. The parameter \c pllcs selects the PLL. For platforms with
AnnaBridge	145:64910690c574	1345	* only one PLL, the parameter pllcs is kept for interface compatibility.
AnnaBridge	145:64910690c574	1346	* 2. The parameter \c config is the PLL configuration structure. On some
AnnaBridge	145:64910690c574	1347	* platforms, it is possible to choose the external PLL directly, which renders the
AnnaBridge	145:64910690c574	1348	* configuration structure not necessary. In this case, pass in NULL.
AnnaBridge	145:64910690c574	1349	* For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
AnnaBridge	145:64910690c574	1350	*/
AnnaBridge	145:64910690c574	1351	status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge	145:64910690c574	1352
AnnaBridge	145:64910690c574	1353	/*!
AnnaBridge	145:64910690c574	1354	* @brief Sets the MCG to PEE mode.
AnnaBridge	145:64910690c574	1355	*
AnnaBridge	145:64910690c574	1356	* This function sets the MCG to PEE mode.
AnnaBridge	145:64910690c574	1357	*
AnnaBridge	145:64910690c574	1358	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1359	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1360	*
AnnaBridge	145:64910690c574	1361	* @note This function only changes the CLKS to use the PLL/FLL output. If the
AnnaBridge	145:64910690c574	1362	* PRDIV/VDIV are different than in the PBE mode, set them up
AnnaBridge	145:64910690c574	1363	* in PBE mode and wait. When the clock is stable, switch to PEE mode.
AnnaBridge	145:64910690c574	1364	*/
AnnaBridge	145:64910690c574	1365	status_t CLOCK_SetPeeMode(void);
AnnaBridge	145:64910690c574	1366
AnnaBridge	145:64910690c574	1367	/*!
AnnaBridge	145:64910690c574	1368	* @brief Switches the MCG to FBE mode from the external mode.
AnnaBridge	145:64910690c574	1369	*
AnnaBridge	145:64910690c574	1370	* This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
AnnaBridge	145:64910690c574	1371	* The external clock is used as the system clock souce and PLL is disabled. However,
AnnaBridge	145:64910690c574	1372	* the FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge	145:64910690c574	1373	* during the mode switch. For example, to switch from PEE mode to FEI mode:
AnnaBridge	145:64910690c574	1374	*
AnnaBridge	145:64910690c574	1375	* @code
AnnaBridge	145:64910690c574	1376	* CLOCK_ExternalModeToFbeModeQuick();
AnnaBridge	145:64910690c574	1377	* CLOCK_SetFeiMode(...);
AnnaBridge	145:64910690c574	1378	* @endcode
AnnaBridge	145:64910690c574	1379	*
AnnaBridge	145:64910690c574	1380	* @retval kStatus_Success Switched successfully.
AnnaBridge	145:64910690c574	1381	* @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
AnnaBridge	145:64910690c574	1382	*/
AnnaBridge	145:64910690c574	1383	status_t CLOCK_ExternalModeToFbeModeQuick(void);
AnnaBridge	145:64910690c574	1384
AnnaBridge	145:64910690c574	1385	/*!
AnnaBridge	145:64910690c574	1386	* @brief Switches the MCG to FBI mode from internal modes.
AnnaBridge	145:64910690c574	1387	*
AnnaBridge	145:64910690c574	1388	* This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
AnnaBridge	145:64910690c574	1389	* The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
AnnaBridge	145:64910690c574	1390	* FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge	145:64910690c574	1391	* during the mode switch. For example, to switch from PEI mode to FEE mode:
AnnaBridge	145:64910690c574	1392	*
AnnaBridge	145:64910690c574	1393	* @code
AnnaBridge	145:64910690c574	1394	* CLOCK_InternalModeToFbiModeQuick();
AnnaBridge	145:64910690c574	1395	* CLOCK_SetFeeMode(...);
AnnaBridge	145:64910690c574	1396	* @endcode
AnnaBridge	145:64910690c574	1397	*
AnnaBridge	145:64910690c574	1398	* @retval kStatus_Success Switched successfully.
AnnaBridge	145:64910690c574	1399	* @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
AnnaBridge	145:64910690c574	1400	*/
AnnaBridge	145:64910690c574	1401	status_t CLOCK_InternalModeToFbiModeQuick(void);
AnnaBridge	145:64910690c574	1402
AnnaBridge	145:64910690c574	1403	/*!
AnnaBridge	145:64910690c574	1404	* @brief Sets the MCG to FEI mode during system boot up.
AnnaBridge	145:64910690c574	1405	*
AnnaBridge	145:64910690c574	1406	* This function sets the MCG to FEI mode from the reset mode. It can also be used to
AnnaBridge	145:64910690c574	1407	* set up MCG during system boot up.
AnnaBridge	145:64910690c574	1408	*
AnnaBridge	145:64910690c574	1409	* @param dmx32 DMX32 in FEI mode.
AnnaBridge	145:64910690c574	1410	* @param drs The DCO range selection.
AnnaBridge	145:64910690c574	1411	* @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge	145:64910690c574	1412	*
AnnaBridge	145:64910690c574	1413	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1414	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1415	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	145:64910690c574	1416	* to frequency above 32768 Hz.
AnnaBridge	145:64910690c574	1417	*/
AnnaBridge	145:64910690c574	1418	status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	145:64910690c574	1419
AnnaBridge	145:64910690c574	1420	/*!
AnnaBridge	145:64910690c574	1421	* @brief Sets the MCG to FEE mode during system bootup.
AnnaBridge	145:64910690c574	1422	*
AnnaBridge	145:64910690c574	1423	* This function sets MCG to FEE mode from the reset mode. It can also be used to
AnnaBridge	145:64910690c574	1424	* set up the MCG during system boot up.
AnnaBridge	145:64910690c574	1425	*
AnnaBridge	145:64910690c574	1426	* @param oscsel OSC clock select, OSCSEL.
AnnaBridge	145:64910690c574	1427	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	145:64910690c574	1428	* @param dmx32 DMX32 in FEE mode.
AnnaBridge	145:64910690c574	1429	* @param drs The DCO range selection.
AnnaBridge	145:64910690c574	1430	* @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge	145:64910690c574	1431	*
AnnaBridge	145:64910690c574	1432	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1433	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1434	*/
AnnaBridge	145:64910690c574	1435	status_t CLOCK_BootToFeeMode(
AnnaBridge	145:64910690c574	1436	mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	145:64910690c574	1437
AnnaBridge	145:64910690c574	1438	/*!
AnnaBridge	145:64910690c574	1439	* @brief Sets the MCG to BLPI mode during system boot up.
AnnaBridge	145:64910690c574	1440	*
AnnaBridge	145:64910690c574	1441	* This function sets the MCG to BLPI mode from the reset mode. It can also be used to
AnnaBridge	145:64910690c574	1442	* set up the MCG during sytem boot up.
AnnaBridge	145:64910690c574	1443	*
AnnaBridge	145:64910690c574	1444	* @param fcrdiv Fast IRC divider, FCRDIV.
AnnaBridge	145:64910690c574	1445	* @param ircs The internal reference clock to select, IRCS.
AnnaBridge	145:64910690c574	1446	* @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge	145:64910690c574	1447	*
AnnaBridge	145:64910690c574	1448	* @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
AnnaBridge	145:64910690c574	1449	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1450	*/
AnnaBridge	145:64910690c574	1451	status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
AnnaBridge	145:64910690c574	1452
AnnaBridge	145:64910690c574	1453	/*!
AnnaBridge	145:64910690c574	1454	* @brief Sets the MCG to BLPE mode during sytem boot up.
AnnaBridge	145:64910690c574	1455	*
AnnaBridge	145:64910690c574	1456	* This function sets the MCG to BLPE mode from the reset mode. It can also be used to
AnnaBridge	145:64910690c574	1457	* set up the MCG during sytem boot up.
AnnaBridge	145:64910690c574	1458	*
AnnaBridge	145:64910690c574	1459	* @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge	145:64910690c574	1460	*
AnnaBridge	145:64910690c574	1461	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1462	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1463	*/
AnnaBridge	145:64910690c574	1464	status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
AnnaBridge	145:64910690c574	1465
AnnaBridge	145:64910690c574	1466	/*!
AnnaBridge	145:64910690c574	1467	* @brief Sets the MCG to PEE mode during system boot up.
AnnaBridge	145:64910690c574	1468	*
AnnaBridge	145:64910690c574	1469	* This function sets the MCG to PEE mode from reset mode. It can also be used to
AnnaBridge	145:64910690c574	1470	* set up the MCG during system boot up.
AnnaBridge	145:64910690c574	1471	*
AnnaBridge	145:64910690c574	1472	* @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge	145:64910690c574	1473	* @param pllcs The PLL selection, PLLCS.
AnnaBridge	145:64910690c574	1474	* @param config Pointer to the PLL configuration.
AnnaBridge	145:64910690c574	1475	*
AnnaBridge	145:64910690c574	1476	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	145:64910690c574	1477	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	145:64910690c574	1478	*/
AnnaBridge	145:64910690c574	1479	status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge	145:64910690c574	1480
AnnaBridge	145:64910690c574	1481	/*!
AnnaBridge	145:64910690c574	1482	* @brief Sets the MCG to a target mode.
AnnaBridge	145:64910690c574	1483	*
AnnaBridge	145:64910690c574	1484	* This function sets MCG to a target mode defined by the configuration
AnnaBridge	145:64910690c574	1485	* structure. If switching to the target mode fails, this function
AnnaBridge	145:64910690c574	1486	* chooses the correct path.
AnnaBridge	145:64910690c574	1487	*
AnnaBridge	145:64910690c574	1488	* @param config Pointer to the target MCG mode configuration structure.
AnnaBridge	145:64910690c574	1489	* @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
AnnaBridge	145:64910690c574	1490	*
AnnaBridge	145:64910690c574	1491	* @note If the external clock is used in the target mode, ensure that it is
AnnaBridge	145:64910690c574	1492	* enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
AnnaBridge	145:64910690c574	1493	* function.
AnnaBridge	145:64910690c574	1494	*/
AnnaBridge	145:64910690c574	1495	status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
AnnaBridge	145:64910690c574	1496
AnnaBridge	145:64910690c574	1497	/@}/
AnnaBridge	145:64910690c574	1498
AnnaBridge	145:64910690c574	1499	#if defined(__cplusplus)
AnnaBridge	145:64910690c574	1500	}
AnnaBridge	145:64910690c574	1501	#endif /* __cplusplus */
AnnaBridge	145:64910690c574	1502
AnnaBridge	145:64910690c574	1503	/! @} /
AnnaBridge	145:64910690c574	1504
AnnaBridge	145:64910690c574	1505	#endif /* _FSL_CLOCK_H_ */