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TARGET_TY51822R3/TOOLCHAIN_GCC_ARM/nrf51_to_nrf52.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 148:fd96258d940d | 1 | /* |
| Kojto | 148:fd96258d940d | 2 | * Copyright (c) 2015 Nordic Semiconductor ASA |
| Kojto | 148:fd96258d940d | 3 | * All rights reserved. |
| Kojto | 148:fd96258d940d | 4 | * |
| Kojto | 148:fd96258d940d | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 148:fd96258d940d | 6 | * are permitted provided that the following conditions are met: |
| Kojto | 148:fd96258d940d | 7 | * |
| Kojto | 148:fd96258d940d | 8 | * 1. Redistributions of source code must retain the above copyright notice, this list |
| Kojto | 148:fd96258d940d | 9 | * of conditions and the following disclaimer. |
| Kojto | 148:fd96258d940d | 10 | * |
| Kojto | 148:fd96258d940d | 11 | * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA |
| Kojto | 148:fd96258d940d | 12 | * integrated circuit in a product or a software update for such product, must reproduce |
| Kojto | 148:fd96258d940d | 13 | * the above copyright notice, this list of conditions and the following disclaimer in |
| Kojto | 148:fd96258d940d | 14 | * the documentation and/or other materials provided with the distribution. |
| Kojto | 148:fd96258d940d | 15 | * |
| Kojto | 148:fd96258d940d | 16 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be |
| Kojto | 148:fd96258d940d | 17 | * used to endorse or promote products derived from this software without specific prior |
| Kojto | 148:fd96258d940d | 18 | * written permission. |
| Kojto | 148:fd96258d940d | 19 | * |
| Kojto | 148:fd96258d940d | 20 | * 4. This software, with or without modification, must only be used with a |
| Kojto | 148:fd96258d940d | 21 | * Nordic Semiconductor ASA integrated circuit. |
| Kojto | 148:fd96258d940d | 22 | * |
| Kojto | 148:fd96258d940d | 23 | * 5. Any software provided in binary or object form under this license must not be reverse |
| Kojto | 148:fd96258d940d | 24 | * engineered, decompiled, modified and/or disassembled. |
| Kojto | 148:fd96258d940d | 25 | * |
| Kojto | 148:fd96258d940d | 26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| Kojto | 148:fd96258d940d | 27 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| Kojto | 148:fd96258d940d | 28 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 148:fd96258d940d | 29 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| Kojto | 148:fd96258d940d | 30 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| Kojto | 148:fd96258d940d | 31 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| Kojto | 148:fd96258d940d | 32 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| Kojto | 148:fd96258d940d | 33 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| Kojto | 148:fd96258d940d | 34 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| Kojto | 148:fd96258d940d | 35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 148:fd96258d940d | 36 | * |
| Kojto | 148:fd96258d940d | 37 | */ |
| Kojto | 148:fd96258d940d | 38 | |
| Kojto | 148:fd96258d940d | 39 | |
| Kojto | 148:fd96258d940d | 40 | #ifndef NRF51_TO_NRF52_H |
| Kojto | 148:fd96258d940d | 41 | #define NRF51_TO_NRF52_H |
| Kojto | 148:fd96258d940d | 42 | |
| Kojto | 148:fd96258d940d | 43 | /*lint ++flb "Enter library region */ |
| Kojto | 148:fd96258d940d | 44 | |
| Kojto | 148:fd96258d940d | 45 | /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. |
| Kojto | 148:fd96258d940d | 46 | * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the |
| Kojto | 148:fd96258d940d | 47 | * functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros |
| Kojto | 148:fd96258d940d | 48 | * from the nrf51_deprecated.h file. */ |
| Kojto | 148:fd96258d940d | 49 | |
| Kojto | 148:fd96258d940d | 50 | |
| Kojto | 148:fd96258d940d | 51 | /* IRQ */ |
| Kojto | 148:fd96258d940d | 52 | /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ |
| Kojto | 148:fd96258d940d | 53 | #define UART0_IRQHandler UARTE0_UART0_IRQHandler |
| Kojto | 148:fd96258d940d | 54 | #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler |
| Kojto | 148:fd96258d940d | 55 | #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler |
| Kojto | 148:fd96258d940d | 56 | #define ADC_IRQHandler SAADC_IRQHandler |
| Kojto | 148:fd96258d940d | 57 | #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler |
| Kojto | 148:fd96258d940d | 58 | #define SWI0_IRQHandler SWI0_EGU0_IRQHandler |
| Kojto | 148:fd96258d940d | 59 | #define SWI1_IRQHandler SWI1_EGU1_IRQHandler |
| Kojto | 148:fd96258d940d | 60 | #define SWI2_IRQHandler SWI2_EGU2_IRQHandler |
| Kojto | 148:fd96258d940d | 61 | #define SWI3_IRQHandler SWI3_EGU3_IRQHandler |
| Kojto | 148:fd96258d940d | 62 | #define SWI4_IRQHandler SWI4_EGU4_IRQHandler |
| Kojto | 148:fd96258d940d | 63 | #define SWI5_IRQHandler SWI5_EGU5_IRQHandler |
| Kojto | 148:fd96258d940d | 64 | |
| Kojto | 148:fd96258d940d | 65 | #define UART0_IRQn UARTE0_UART0_IRQn |
| Kojto | 148:fd96258d940d | 66 | #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn |
| Kojto | 148:fd96258d940d | 67 | #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn |
| Kojto | 148:fd96258d940d | 68 | #define ADC_IRQn SAADC_IRQn |
| Kojto | 148:fd96258d940d | 69 | #define LPCOMP_IRQn COMP_LPCOMP_IRQn |
| Kojto | 148:fd96258d940d | 70 | #define SWI0_IRQn SWI0_EGU0_IRQn |
| Kojto | 148:fd96258d940d | 71 | #define SWI1_IRQn SWI1_EGU1_IRQn |
| Kojto | 148:fd96258d940d | 72 | #define SWI2_IRQn SWI2_EGU2_IRQn |
| Kojto | 148:fd96258d940d | 73 | #define SWI3_IRQn SWI3_EGU3_IRQn |
| Kojto | 148:fd96258d940d | 74 | #define SWI4_IRQn SWI4_EGU4_IRQn |
| Kojto | 148:fd96258d940d | 75 | #define SWI5_IRQn SWI5_EGU5_IRQn |
| Kojto | 148:fd96258d940d | 76 | |
| Kojto | 148:fd96258d940d | 77 | |
| Kojto | 148:fd96258d940d | 78 | /* UICR */ |
| Kojto | 148:fd96258d940d | 79 | /* Register RBPCONF was renamed to APPROTECT. */ |
| Kojto | 148:fd96258d940d | 80 | #define RBPCONF APPROTECT |
| Kojto | 148:fd96258d940d | 81 | |
| Kojto | 148:fd96258d940d | 82 | #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos |
| Kojto | 148:fd96258d940d | 83 | #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk |
| Kojto | 148:fd96258d940d | 84 | #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled |
| Kojto | 148:fd96258d940d | 85 | #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled |
| Kojto | 148:fd96258d940d | 86 | |
| Kojto | 148:fd96258d940d | 87 | |
| Kojto | 148:fd96258d940d | 88 | /* GPIO */ |
| Kojto | 148:fd96258d940d | 89 | /* GPIO port was renamed to P0. */ |
| Kojto | 148:fd96258d940d | 90 | #define NRF_GPIO NRF_P0 |
| Kojto | 148:fd96258d940d | 91 | #define NRF_GPIO_BASE NRF_P0_BASE |
| Kojto | 148:fd96258d940d | 92 | |
| Kojto | 148:fd96258d940d | 93 | |
| Kojto | 148:fd96258d940d | 94 | /* SPIS */ |
| Kojto | 148:fd96258d940d | 95 | /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ |
| Kojto | 148:fd96258d940d | 96 | #define PSELSCK PSEL.SCK |
| Kojto | 148:fd96258d940d | 97 | #define PSELMISO PSEL.MISO |
| Kojto | 148:fd96258d940d | 98 | #define PSELMOSI PSEL.MOSI |
| Kojto | 148:fd96258d940d | 99 | #define PSELCSN PSEL.CSN |
| Kojto | 148:fd96258d940d | 100 | |
| Kojto | 148:fd96258d940d | 101 | /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ |
| Kojto | 148:fd96258d940d | 102 | #define RXDPTR RXD.PTR |
| Kojto | 148:fd96258d940d | 103 | #define MAXRX RXD.MAXCNT |
| Kojto | 148:fd96258d940d | 104 | #define AMOUNTRX RXD.AMOUNT |
| Kojto | 148:fd96258d940d | 105 | |
| Kojto | 148:fd96258d940d | 106 | #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos |
| Kojto | 148:fd96258d940d | 107 | #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk |
| Kojto | 148:fd96258d940d | 108 | |
| Kojto | 148:fd96258d940d | 109 | #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos |
| Kojto | 148:fd96258d940d | 110 | #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk |
| Kojto | 148:fd96258d940d | 111 | |
| Kojto | 148:fd96258d940d | 112 | /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ |
| Kojto | 148:fd96258d940d | 113 | #define TXDPTR TXD.PTR |
| Kojto | 148:fd96258d940d | 114 | #define MAXTX TXD.MAXCNT |
| Kojto | 148:fd96258d940d | 115 | #define AMOUNTTX TXD.AMOUNT |
| Kojto | 148:fd96258d940d | 116 | |
| Kojto | 148:fd96258d940d | 117 | #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos |
| Kojto | 148:fd96258d940d | 118 | #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk |
| Kojto | 148:fd96258d940d | 119 | |
| Kojto | 148:fd96258d940d | 120 | #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos |
| Kojto | 148:fd96258d940d | 121 | #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk |
| Kojto | 148:fd96258d940d | 122 | |
| Kojto | 148:fd96258d940d | 123 | |
| Kojto | 148:fd96258d940d | 124 | /* MPU */ |
| Kojto | 148:fd96258d940d | 125 | /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ |
| Kojto | 148:fd96258d940d | 126 | #define NRF_MPU NRF_BPROT |
| Kojto | 148:fd96258d940d | 127 | |
| Kojto | 148:fd96258d940d | 128 | /* Register DISABLEINDEBUG macros were affected. */ |
| Kojto | 148:fd96258d940d | 129 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos |
| Kojto | 148:fd96258d940d | 130 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk |
| Kojto | 148:fd96258d940d | 131 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled |
| Kojto | 148:fd96258d940d | 132 | #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled |
| Kojto | 148:fd96258d940d | 133 | |
| Kojto | 148:fd96258d940d | 134 | /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ |
| Kojto | 148:fd96258d940d | 135 | #define PROTENSET0 CONFIG0 |
| Kojto | 148:fd96258d940d | 136 | #define PROTENSET1 CONFIG1 |
| Kojto | 148:fd96258d940d | 137 | |
| Kojto | 148:fd96258d940d | 138 | #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos |
| Kojto | 148:fd96258d940d | 139 | #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk |
| Kojto | 148:fd96258d940d | 140 | #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled |
| Kojto | 148:fd96258d940d | 141 | #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled |
| Kojto | 148:fd96258d940d | 142 | #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled |
| Kojto | 148:fd96258d940d | 143 | |
| Kojto | 148:fd96258d940d | 144 | #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos |
| Kojto | 148:fd96258d940d | 145 | #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk |
| Kojto | 148:fd96258d940d | 146 | #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled |
| Kojto | 148:fd96258d940d | 147 | #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled |
| Kojto | 148:fd96258d940d | 148 | #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled |
| Kojto | 148:fd96258d940d | 149 | |
| Kojto | 148:fd96258d940d | 150 | #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos |
| Kojto | 148:fd96258d940d | 151 | #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk |
| Kojto | 148:fd96258d940d | 152 | #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled |
| Kojto | 148:fd96258d940d | 153 | #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled |
| Kojto | 148:fd96258d940d | 154 | #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled |
| Kojto | 148:fd96258d940d | 155 | |
| Kojto | 148:fd96258d940d | 156 | #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos |
| Kojto | 148:fd96258d940d | 157 | #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk |
| Kojto | 148:fd96258d940d | 158 | #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled |
| Kojto | 148:fd96258d940d | 159 | #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled |
| Kojto | 148:fd96258d940d | 160 | #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled |
| Kojto | 148:fd96258d940d | 161 | |
| Kojto | 148:fd96258d940d | 162 | #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos |
| Kojto | 148:fd96258d940d | 163 | #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk |
| Kojto | 148:fd96258d940d | 164 | #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled |
| Kojto | 148:fd96258d940d | 165 | #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled |
| Kojto | 148:fd96258d940d | 166 | #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled |
| Kojto | 148:fd96258d940d | 167 | |
| Kojto | 148:fd96258d940d | 168 | #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos |
| Kojto | 148:fd96258d940d | 169 | #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk |
| Kojto | 148:fd96258d940d | 170 | #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled |
| Kojto | 148:fd96258d940d | 171 | #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled |
| Kojto | 148:fd96258d940d | 172 | #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled |
| Kojto | 148:fd96258d940d | 173 | |
| Kojto | 148:fd96258d940d | 174 | #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos |
| Kojto | 148:fd96258d940d | 175 | #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk |
| Kojto | 148:fd96258d940d | 176 | #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled |
| Kojto | 148:fd96258d940d | 177 | #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled |
| Kojto | 148:fd96258d940d | 178 | #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled |
| Kojto | 148:fd96258d940d | 179 | |
| Kojto | 148:fd96258d940d | 180 | #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos |
| Kojto | 148:fd96258d940d | 181 | #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk |
| Kojto | 148:fd96258d940d | 182 | #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled |
| Kojto | 148:fd96258d940d | 183 | #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled |
| Kojto | 148:fd96258d940d | 184 | #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled |
| Kojto | 148:fd96258d940d | 185 | |
| Kojto | 148:fd96258d940d | 186 | #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos |
| Kojto | 148:fd96258d940d | 187 | #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk |
| Kojto | 148:fd96258d940d | 188 | #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled |
| Kojto | 148:fd96258d940d | 189 | #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled |
| Kojto | 148:fd96258d940d | 190 | #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled |
| Kojto | 148:fd96258d940d | 191 | |
| Kojto | 148:fd96258d940d | 192 | #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos |
| Kojto | 148:fd96258d940d | 193 | #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk |
| Kojto | 148:fd96258d940d | 194 | #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled |
| Kojto | 148:fd96258d940d | 195 | #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled |
| Kojto | 148:fd96258d940d | 196 | #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled |
| Kojto | 148:fd96258d940d | 197 | |
| Kojto | 148:fd96258d940d | 198 | #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos |
| Kojto | 148:fd96258d940d | 199 | #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk |
| Kojto | 148:fd96258d940d | 200 | #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled |
| Kojto | 148:fd96258d940d | 201 | #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled |
| Kojto | 148:fd96258d940d | 202 | #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled |
| Kojto | 148:fd96258d940d | 203 | |
| Kojto | 148:fd96258d940d | 204 | #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos |
| Kojto | 148:fd96258d940d | 205 | #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk |
| Kojto | 148:fd96258d940d | 206 | #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled |
| Kojto | 148:fd96258d940d | 207 | #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled |
| Kojto | 148:fd96258d940d | 208 | #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled |
| Kojto | 148:fd96258d940d | 209 | |
| Kojto | 148:fd96258d940d | 210 | #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos |
| Kojto | 148:fd96258d940d | 211 | #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk |
| Kojto | 148:fd96258d940d | 212 | #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled |
| Kojto | 148:fd96258d940d | 213 | #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled |
| Kojto | 148:fd96258d940d | 214 | #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled |
| Kojto | 148:fd96258d940d | 215 | |
| Kojto | 148:fd96258d940d | 216 | #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos |
| Kojto | 148:fd96258d940d | 217 | #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk |
| Kojto | 148:fd96258d940d | 218 | #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled |
| Kojto | 148:fd96258d940d | 219 | #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled |
| Kojto | 148:fd96258d940d | 220 | #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled |
| Kojto | 148:fd96258d940d | 221 | |
| Kojto | 148:fd96258d940d | 222 | #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos |
| Kojto | 148:fd96258d940d | 223 | #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk |
| Kojto | 148:fd96258d940d | 224 | #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled |
| Kojto | 148:fd96258d940d | 225 | #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled |
| Kojto | 148:fd96258d940d | 226 | #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled |
| Kojto | 148:fd96258d940d | 227 | |
| Kojto | 148:fd96258d940d | 228 | #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos |
| Kojto | 148:fd96258d940d | 229 | #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk |
| Kojto | 148:fd96258d940d | 230 | #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled |
| Kojto | 148:fd96258d940d | 231 | #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled |
| Kojto | 148:fd96258d940d | 232 | #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled |
| Kojto | 148:fd96258d940d | 233 | |
| Kojto | 148:fd96258d940d | 234 | #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos |
| Kojto | 148:fd96258d940d | 235 | #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk |
| Kojto | 148:fd96258d940d | 236 | #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled |
| Kojto | 148:fd96258d940d | 237 | #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled |
| Kojto | 148:fd96258d940d | 238 | #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled |
| Kojto | 148:fd96258d940d | 239 | |
| Kojto | 148:fd96258d940d | 240 | #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos |
| Kojto | 148:fd96258d940d | 241 | #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk |
| Kojto | 148:fd96258d940d | 242 | #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled |
| Kojto | 148:fd96258d940d | 243 | #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled |
| Kojto | 148:fd96258d940d | 244 | #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled |
| Kojto | 148:fd96258d940d | 245 | |
| Kojto | 148:fd96258d940d | 246 | #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos |
| Kojto | 148:fd96258d940d | 247 | #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk |
| Kojto | 148:fd96258d940d | 248 | #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled |
| Kojto | 148:fd96258d940d | 249 | #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled |
| Kojto | 148:fd96258d940d | 250 | #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled |
| Kojto | 148:fd96258d940d | 251 | |
| Kojto | 148:fd96258d940d | 252 | #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos |
| Kojto | 148:fd96258d940d | 253 | #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk |
| Kojto | 148:fd96258d940d | 254 | #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled |
| Kojto | 148:fd96258d940d | 255 | #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled |
| Kojto | 148:fd96258d940d | 256 | #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled |
| Kojto | 148:fd96258d940d | 257 | |
| Kojto | 148:fd96258d940d | 258 | #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos |
| Kojto | 148:fd96258d940d | 259 | #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk |
| Kojto | 148:fd96258d940d | 260 | #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled |
| Kojto | 148:fd96258d940d | 261 | #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled |
| Kojto | 148:fd96258d940d | 262 | #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled |
| Kojto | 148:fd96258d940d | 263 | |
| Kojto | 148:fd96258d940d | 264 | #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos |
| Kojto | 148:fd96258d940d | 265 | #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk |
| Kojto | 148:fd96258d940d | 266 | #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled |
| Kojto | 148:fd96258d940d | 267 | #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled |
| Kojto | 148:fd96258d940d | 268 | #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled |
| Kojto | 148:fd96258d940d | 269 | |
| Kojto | 148:fd96258d940d | 270 | #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos |
| Kojto | 148:fd96258d940d | 271 | #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk |
| Kojto | 148:fd96258d940d | 272 | #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled |
| Kojto | 148:fd96258d940d | 273 | #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled |
| Kojto | 148:fd96258d940d | 274 | #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled |
| Kojto | 148:fd96258d940d | 275 | |
| Kojto | 148:fd96258d940d | 276 | #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos |
| Kojto | 148:fd96258d940d | 277 | #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk |
| Kojto | 148:fd96258d940d | 278 | #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled |
| Kojto | 148:fd96258d940d | 279 | #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled |
| Kojto | 148:fd96258d940d | 280 | #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled |
| Kojto | 148:fd96258d940d | 281 | |
| Kojto | 148:fd96258d940d | 282 | #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos |
| Kojto | 148:fd96258d940d | 283 | #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk |
| Kojto | 148:fd96258d940d | 284 | #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled |
| Kojto | 148:fd96258d940d | 285 | #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled |
| Kojto | 148:fd96258d940d | 286 | #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled |
| Kojto | 148:fd96258d940d | 287 | |
| Kojto | 148:fd96258d940d | 288 | #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos |
| Kojto | 148:fd96258d940d | 289 | #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk |
| Kojto | 148:fd96258d940d | 290 | #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled |
| Kojto | 148:fd96258d940d | 291 | #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled |
| Kojto | 148:fd96258d940d | 292 | #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled |
| Kojto | 148:fd96258d940d | 293 | |
| Kojto | 148:fd96258d940d | 294 | #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos |
| Kojto | 148:fd96258d940d | 295 | #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk |
| Kojto | 148:fd96258d940d | 296 | #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled |
| Kojto | 148:fd96258d940d | 297 | #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled |
| Kojto | 148:fd96258d940d | 298 | #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled |
| Kojto | 148:fd96258d940d | 299 | |
| Kojto | 148:fd96258d940d | 300 | #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos |
| Kojto | 148:fd96258d940d | 301 | #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk |
| Kojto | 148:fd96258d940d | 302 | #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled |
| Kojto | 148:fd96258d940d | 303 | #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled |
| Kojto | 148:fd96258d940d | 304 | #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled |
| Kojto | 148:fd96258d940d | 305 | |
| Kojto | 148:fd96258d940d | 306 | #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos |
| Kojto | 148:fd96258d940d | 307 | #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk |
| Kojto | 148:fd96258d940d | 308 | #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled |
| Kojto | 148:fd96258d940d | 309 | #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled |
| Kojto | 148:fd96258d940d | 310 | #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled |
| Kojto | 148:fd96258d940d | 311 | |
| Kojto | 148:fd96258d940d | 312 | #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos |
| Kojto | 148:fd96258d940d | 313 | #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk |
| Kojto | 148:fd96258d940d | 314 | #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled |
| Kojto | 148:fd96258d940d | 315 | #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled |
| Kojto | 148:fd96258d940d | 316 | #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled |
| Kojto | 148:fd96258d940d | 317 | |
| Kojto | 148:fd96258d940d | 318 | #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos |
| Kojto | 148:fd96258d940d | 319 | #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk |
| Kojto | 148:fd96258d940d | 320 | #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled |
| Kojto | 148:fd96258d940d | 321 | #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled |
| Kojto | 148:fd96258d940d | 322 | #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled |
| Kojto | 148:fd96258d940d | 323 | |
| Kojto | 148:fd96258d940d | 324 | #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos |
| Kojto | 148:fd96258d940d | 325 | #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk |
| Kojto | 148:fd96258d940d | 326 | #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled |
| Kojto | 148:fd96258d940d | 327 | #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled |
| Kojto | 148:fd96258d940d | 328 | #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled |
| Kojto | 148:fd96258d940d | 329 | |
| Kojto | 148:fd96258d940d | 330 | #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos |
| Kojto | 148:fd96258d940d | 331 | #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk |
| Kojto | 148:fd96258d940d | 332 | #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled |
| Kojto | 148:fd96258d940d | 333 | #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled |
| Kojto | 148:fd96258d940d | 334 | #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled |
| Kojto | 148:fd96258d940d | 335 | |
| Kojto | 148:fd96258d940d | 336 | #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos |
| Kojto | 148:fd96258d940d | 337 | #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk |
| Kojto | 148:fd96258d940d | 338 | #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled |
| Kojto | 148:fd96258d940d | 339 | #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled |
| Kojto | 148:fd96258d940d | 340 | #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled |
| Kojto | 148:fd96258d940d | 341 | |
| Kojto | 148:fd96258d940d | 342 | #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos |
| Kojto | 148:fd96258d940d | 343 | #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk |
| Kojto | 148:fd96258d940d | 344 | #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled |
| Kojto | 148:fd96258d940d | 345 | #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled |
| Kojto | 148:fd96258d940d | 346 | #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled |
| Kojto | 148:fd96258d940d | 347 | |
| Kojto | 148:fd96258d940d | 348 | #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos |
| Kojto | 148:fd96258d940d | 349 | #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk |
| Kojto | 148:fd96258d940d | 350 | #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled |
| Kojto | 148:fd96258d940d | 351 | #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled |
| Kojto | 148:fd96258d940d | 352 | #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled |
| Kojto | 148:fd96258d940d | 353 | |
| Kojto | 148:fd96258d940d | 354 | #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos |
| Kojto | 148:fd96258d940d | 355 | #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk |
| Kojto | 148:fd96258d940d | 356 | #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled |
| Kojto | 148:fd96258d940d | 357 | #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled |
| Kojto | 148:fd96258d940d | 358 | #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled |
| Kojto | 148:fd96258d940d | 359 | |
| Kojto | 148:fd96258d940d | 360 | #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos |
| Kojto | 148:fd96258d940d | 361 | #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk |
| Kojto | 148:fd96258d940d | 362 | #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled |
| Kojto | 148:fd96258d940d | 363 | #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled |
| Kojto | 148:fd96258d940d | 364 | #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled |
| Kojto | 148:fd96258d940d | 365 | |
| Kojto | 148:fd96258d940d | 366 | #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos |
| Kojto | 148:fd96258d940d | 367 | #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk |
| Kojto | 148:fd96258d940d | 368 | #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled |
| Kojto | 148:fd96258d940d | 369 | #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled |
| Kojto | 148:fd96258d940d | 370 | #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled |
| Kojto | 148:fd96258d940d | 371 | |
| Kojto | 148:fd96258d940d | 372 | #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos |
| Kojto | 148:fd96258d940d | 373 | #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk |
| Kojto | 148:fd96258d940d | 374 | #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled |
| Kojto | 148:fd96258d940d | 375 | #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled |
| Kojto | 148:fd96258d940d | 376 | #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled |
| Kojto | 148:fd96258d940d | 377 | |
| Kojto | 148:fd96258d940d | 378 | #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos |
| Kojto | 148:fd96258d940d | 379 | #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk |
| Kojto | 148:fd96258d940d | 380 | #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled |
| Kojto | 148:fd96258d940d | 381 | #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled |
| Kojto | 148:fd96258d940d | 382 | #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled |
| Kojto | 148:fd96258d940d | 383 | |
| Kojto | 148:fd96258d940d | 384 | #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos |
| Kojto | 148:fd96258d940d | 385 | #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk |
| Kojto | 148:fd96258d940d | 386 | #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled |
| Kojto | 148:fd96258d940d | 387 | #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled |
| Kojto | 148:fd96258d940d | 388 | #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled |
| Kojto | 148:fd96258d940d | 389 | |
| Kojto | 148:fd96258d940d | 390 | #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos |
| Kojto | 148:fd96258d940d | 391 | #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk |
| Kojto | 148:fd96258d940d | 392 | #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled |
| Kojto | 148:fd96258d940d | 393 | #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled |
| Kojto | 148:fd96258d940d | 394 | #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled |
| Kojto | 148:fd96258d940d | 395 | |
| Kojto | 148:fd96258d940d | 396 | #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos |
| Kojto | 148:fd96258d940d | 397 | #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk |
| Kojto | 148:fd96258d940d | 398 | #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled |
| Kojto | 148:fd96258d940d | 399 | #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled |
| Kojto | 148:fd96258d940d | 400 | #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled |
| Kojto | 148:fd96258d940d | 401 | |
| Kojto | 148:fd96258d940d | 402 | #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos |
| Kojto | 148:fd96258d940d | 403 | #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk |
| Kojto | 148:fd96258d940d | 404 | #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled |
| Kojto | 148:fd96258d940d | 405 | #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled |
| Kojto | 148:fd96258d940d | 406 | #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled |
| Kojto | 148:fd96258d940d | 407 | |
| Kojto | 148:fd96258d940d | 408 | #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos |
| Kojto | 148:fd96258d940d | 409 | #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk |
| Kojto | 148:fd96258d940d | 410 | #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled |
| Kojto | 148:fd96258d940d | 411 | #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled |
| Kojto | 148:fd96258d940d | 412 | #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled |
| Kojto | 148:fd96258d940d | 413 | |
| Kojto | 148:fd96258d940d | 414 | #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos |
| Kojto | 148:fd96258d940d | 415 | #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk |
| Kojto | 148:fd96258d940d | 416 | #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled |
| Kojto | 148:fd96258d940d | 417 | #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled |
| Kojto | 148:fd96258d940d | 418 | #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled |
| Kojto | 148:fd96258d940d | 419 | |
| Kojto | 148:fd96258d940d | 420 | #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos |
| Kojto | 148:fd96258d940d | 421 | #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk |
| Kojto | 148:fd96258d940d | 422 | #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled |
| Kojto | 148:fd96258d940d | 423 | #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled |
| Kojto | 148:fd96258d940d | 424 | #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled |
| Kojto | 148:fd96258d940d | 425 | |
| Kojto | 148:fd96258d940d | 426 | #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos |
| Kojto | 148:fd96258d940d | 427 | #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk |
| Kojto | 148:fd96258d940d | 428 | #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled |
| Kojto | 148:fd96258d940d | 429 | #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled |
| Kojto | 148:fd96258d940d | 430 | #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled |
| Kojto | 148:fd96258d940d | 431 | |
| Kojto | 148:fd96258d940d | 432 | #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos |
| Kojto | 148:fd96258d940d | 433 | #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk |
| Kojto | 148:fd96258d940d | 434 | #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled |
| Kojto | 148:fd96258d940d | 435 | #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled |
| Kojto | 148:fd96258d940d | 436 | #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled |
| Kojto | 148:fd96258d940d | 437 | |
| Kojto | 148:fd96258d940d | 438 | #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos |
| Kojto | 148:fd96258d940d | 439 | #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk |
| Kojto | 148:fd96258d940d | 440 | #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled |
| Kojto | 148:fd96258d940d | 441 | #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled |
| Kojto | 148:fd96258d940d | 442 | #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled |
| Kojto | 148:fd96258d940d | 443 | |
| Kojto | 148:fd96258d940d | 444 | #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos |
| Kojto | 148:fd96258d940d | 445 | #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk |
| Kojto | 148:fd96258d940d | 446 | #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled |
| Kojto | 148:fd96258d940d | 447 | #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled |
| Kojto | 148:fd96258d940d | 448 | #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled |
| Kojto | 148:fd96258d940d | 449 | |
| Kojto | 148:fd96258d940d | 450 | #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos |
| Kojto | 148:fd96258d940d | 451 | #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk |
| Kojto | 148:fd96258d940d | 452 | #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled |
| Kojto | 148:fd96258d940d | 453 | #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled |
| Kojto | 148:fd96258d940d | 454 | #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled |
| Kojto | 148:fd96258d940d | 455 | |
| Kojto | 148:fd96258d940d | 456 | #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos |
| Kojto | 148:fd96258d940d | 457 | #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk |
| Kojto | 148:fd96258d940d | 458 | #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled |
| Kojto | 148:fd96258d940d | 459 | #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled |
| Kojto | 148:fd96258d940d | 460 | #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled |
| Kojto | 148:fd96258d940d | 461 | |
| Kojto | 148:fd96258d940d | 462 | #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos |
| Kojto | 148:fd96258d940d | 463 | #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk |
| Kojto | 148:fd96258d940d | 464 | #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled |
| Kojto | 148:fd96258d940d | 465 | #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled |
| Kojto | 148:fd96258d940d | 466 | #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled |
| Kojto | 148:fd96258d940d | 467 | |
| Kojto | 148:fd96258d940d | 468 | #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos |
| Kojto | 148:fd96258d940d | 469 | #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk |
| Kojto | 148:fd96258d940d | 470 | #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled |
| Kojto | 148:fd96258d940d | 471 | #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled |
| Kojto | 148:fd96258d940d | 472 | #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled |
| Kojto | 148:fd96258d940d | 473 | |
| Kojto | 148:fd96258d940d | 474 | #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos |
| Kojto | 148:fd96258d940d | 475 | #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk |
| Kojto | 148:fd96258d940d | 476 | #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled |
| Kojto | 148:fd96258d940d | 477 | #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled |
| Kojto | 148:fd96258d940d | 478 | #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled |
| Kojto | 148:fd96258d940d | 479 | |
| Kojto | 148:fd96258d940d | 480 | #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos |
| Kojto | 148:fd96258d940d | 481 | #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk |
| Kojto | 148:fd96258d940d | 482 | #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled |
| Kojto | 148:fd96258d940d | 483 | #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled |
| Kojto | 148:fd96258d940d | 484 | #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled |
| Kojto | 148:fd96258d940d | 485 | |
| Kojto | 148:fd96258d940d | 486 | #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos |
| Kojto | 148:fd96258d940d | 487 | #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk |
| Kojto | 148:fd96258d940d | 488 | #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled |
| Kojto | 148:fd96258d940d | 489 | #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled |
| Kojto | 148:fd96258d940d | 490 | #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled |
| Kojto | 148:fd96258d940d | 491 | |
| Kojto | 148:fd96258d940d | 492 | #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos |
| Kojto | 148:fd96258d940d | 493 | #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk |
| Kojto | 148:fd96258d940d | 494 | #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled |
| Kojto | 148:fd96258d940d | 495 | #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled |
| Kojto | 148:fd96258d940d | 496 | #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled |
| Kojto | 148:fd96258d940d | 497 | |
| Kojto | 148:fd96258d940d | 498 | #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos |
| Kojto | 148:fd96258d940d | 499 | #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk |
| Kojto | 148:fd96258d940d | 500 | #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled |
| Kojto | 148:fd96258d940d | 501 | #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled |
| Kojto | 148:fd96258d940d | 502 | #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled |
| Kojto | 148:fd96258d940d | 503 | |
| Kojto | 148:fd96258d940d | 504 | #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos |
| Kojto | 148:fd96258d940d | 505 | #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk |
| Kojto | 148:fd96258d940d | 506 | #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled |
| Kojto | 148:fd96258d940d | 507 | #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled |
| Kojto | 148:fd96258d940d | 508 | #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled |
| Kojto | 148:fd96258d940d | 509 | |
| Kojto | 148:fd96258d940d | 510 | #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos |
| Kojto | 148:fd96258d940d | 511 | #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk |
| Kojto | 148:fd96258d940d | 512 | #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled |
| Kojto | 148:fd96258d940d | 513 | #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled |
| Kojto | 148:fd96258d940d | 514 | #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled |
| Kojto | 148:fd96258d940d | 515 | |
| Kojto | 148:fd96258d940d | 516 | #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos |
| Kojto | 148:fd96258d940d | 517 | #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk |
| Kojto | 148:fd96258d940d | 518 | #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled |
| Kojto | 148:fd96258d940d | 519 | #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled |
| Kojto | 148:fd96258d940d | 520 | #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled |
| Kojto | 148:fd96258d940d | 521 | |
| Kojto | 148:fd96258d940d | 522 | |
| Kojto | 148:fd96258d940d | 523 | /* From nrf51_deprecated.h */ |
| Kojto | 148:fd96258d940d | 524 | |
| Kojto | 148:fd96258d940d | 525 | /* NVMC */ |
| Kojto | 148:fd96258d940d | 526 | /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ |
| Kojto | 148:fd96258d940d | 527 | #define ERASEPROTECTEDPAGE ERASEPCR0 |
| Kojto | 148:fd96258d940d | 528 | |
| Kojto | 148:fd96258d940d | 529 | |
| Kojto | 148:fd96258d940d | 530 | /* IRQ */ |
| Kojto | 148:fd96258d940d | 531 | /* COMP module was eliminated. Adapted to nrf52 headers. */ |
| Kojto | 148:fd96258d940d | 532 | #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler |
| Kojto | 148:fd96258d940d | 533 | #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn |
| Kojto | 148:fd96258d940d | 534 | |
| Kojto | 148:fd96258d940d | 535 | |
| Kojto | 148:fd96258d940d | 536 | /* RADIO */ |
| Kojto | 148:fd96258d940d | 537 | /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ |
| Kojto | 148:fd96258d940d | 538 | #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos |
| Kojto | 148:fd96258d940d | 539 | #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk |
| Kojto | 148:fd96258d940d | 540 | #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include |
| Kojto | 148:fd96258d940d | 541 | #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip |
| Kojto | 148:fd96258d940d | 542 | |
| Kojto | 148:fd96258d940d | 543 | |
| Kojto | 148:fd96258d940d | 544 | /* FICR */ |
| Kojto | 148:fd96258d940d | 545 | /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ |
| Kojto | 148:fd96258d940d | 546 | #define DEVICEID0 DEVICEID[0] |
| Kojto | 148:fd96258d940d | 547 | #define DEVICEID1 DEVICEID[1] |
| Kojto | 148:fd96258d940d | 548 | |
| Kojto | 148:fd96258d940d | 549 | /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ |
| Kojto | 148:fd96258d940d | 550 | #define ER0 ER[0] |
| Kojto | 148:fd96258d940d | 551 | #define ER1 ER[1] |
| Kojto | 148:fd96258d940d | 552 | #define ER2 ER[2] |
| Kojto | 148:fd96258d940d | 553 | #define ER3 ER[3] |
| Kojto | 148:fd96258d940d | 554 | |
| Kojto | 148:fd96258d940d | 555 | /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ |
| Kojto | 148:fd96258d940d | 556 | #define IR0 IR[0] |
| Kojto | 148:fd96258d940d | 557 | #define IR1 IR[1] |
| Kojto | 148:fd96258d940d | 558 | #define IR2 IR[2] |
| Kojto | 148:fd96258d940d | 559 | #define IR3 IR[3] |
| Kojto | 148:fd96258d940d | 560 | |
| Kojto | 148:fd96258d940d | 561 | /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ |
| Kojto | 148:fd96258d940d | 562 | #define DEVICEADDR0 DEVICEADDR[0] |
| Kojto | 148:fd96258d940d | 563 | #define DEVICEADDR1 DEVICEADDR[1] |
| Kojto | 148:fd96258d940d | 564 | |
| Kojto | 148:fd96258d940d | 565 | |
| Kojto | 148:fd96258d940d | 566 | /* PPI */ |
| Kojto | 148:fd96258d940d | 567 | /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ |
| Kojto | 148:fd96258d940d | 568 | #define TASKS_CHG0EN TASKS_CHG[0].EN |
| Kojto | 148:fd96258d940d | 569 | #define TASKS_CHG0DIS TASKS_CHG[0].DIS |
| Kojto | 148:fd96258d940d | 570 | #define TASKS_CHG1EN TASKS_CHG[1].EN |
| Kojto | 148:fd96258d940d | 571 | #define TASKS_CHG1DIS TASKS_CHG[1].DIS |
| Kojto | 148:fd96258d940d | 572 | #define TASKS_CHG2EN TASKS_CHG[2].EN |
| Kojto | 148:fd96258d940d | 573 | #define TASKS_CHG2DIS TASKS_CHG[2].DIS |
| Kojto | 148:fd96258d940d | 574 | #define TASKS_CHG3EN TASKS_CHG[3].EN |
| Kojto | 148:fd96258d940d | 575 | #define TASKS_CHG3DIS TASKS_CHG[3].DIS |
| Kojto | 148:fd96258d940d | 576 | |
| Kojto | 148:fd96258d940d | 577 | /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ |
| Kojto | 148:fd96258d940d | 578 | #define CH0_EEP CH[0].EEP |
| Kojto | 148:fd96258d940d | 579 | #define CH0_TEP CH[0].TEP |
| Kojto | 148:fd96258d940d | 580 | #define CH1_EEP CH[1].EEP |
| Kojto | 148:fd96258d940d | 581 | #define CH1_TEP CH[1].TEP |
| Kojto | 148:fd96258d940d | 582 | #define CH2_EEP CH[2].EEP |
| Kojto | 148:fd96258d940d | 583 | #define CH2_TEP CH[2].TEP |
| Kojto | 148:fd96258d940d | 584 | #define CH3_EEP CH[3].EEP |
| Kojto | 148:fd96258d940d | 585 | #define CH3_TEP CH[3].TEP |
| Kojto | 148:fd96258d940d | 586 | #define CH4_EEP CH[4].EEP |
| Kojto | 148:fd96258d940d | 587 | #define CH4_TEP CH[4].TEP |
| Kojto | 148:fd96258d940d | 588 | #define CH5_EEP CH[5].EEP |
| Kojto | 148:fd96258d940d | 589 | #define CH5_TEP CH[5].TEP |
| Kojto | 148:fd96258d940d | 590 | #define CH6_EEP CH[6].EEP |
| Kojto | 148:fd96258d940d | 591 | #define CH6_TEP CH[6].TEP |
| Kojto | 148:fd96258d940d | 592 | #define CH7_EEP CH[7].EEP |
| Kojto | 148:fd96258d940d | 593 | #define CH7_TEP CH[7].TEP |
| Kojto | 148:fd96258d940d | 594 | #define CH8_EEP CH[8].EEP |
| Kojto | 148:fd96258d940d | 595 | #define CH8_TEP CH[8].TEP |
| Kojto | 148:fd96258d940d | 596 | #define CH9_EEP CH[9].EEP |
| Kojto | 148:fd96258d940d | 597 | #define CH9_TEP CH[9].TEP |
| Kojto | 148:fd96258d940d | 598 | #define CH10_EEP CH[10].EEP |
| Kojto | 148:fd96258d940d | 599 | #define CH10_TEP CH[10].TEP |
| Kojto | 148:fd96258d940d | 600 | #define CH11_EEP CH[11].EEP |
| Kojto | 148:fd96258d940d | 601 | #define CH11_TEP CH[11].TEP |
| Kojto | 148:fd96258d940d | 602 | #define CH12_EEP CH[12].EEP |
| Kojto | 148:fd96258d940d | 603 | #define CH12_TEP CH[12].TEP |
| Kojto | 148:fd96258d940d | 604 | #define CH13_EEP CH[13].EEP |
| Kojto | 148:fd96258d940d | 605 | #define CH13_TEP CH[13].TEP |
| Kojto | 148:fd96258d940d | 606 | #define CH14_EEP CH[14].EEP |
| Kojto | 148:fd96258d940d | 607 | #define CH14_TEP CH[14].TEP |
| Kojto | 148:fd96258d940d | 608 | #define CH15_EEP CH[15].EEP |
| Kojto | 148:fd96258d940d | 609 | #define CH15_TEP CH[15].TEP |
| Kojto | 148:fd96258d940d | 610 | |
| Kojto | 148:fd96258d940d | 611 | /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ |
| Kojto | 148:fd96258d940d | 612 | #define CHG0 CHG[0] |
| Kojto | 148:fd96258d940d | 613 | #define CHG1 CHG[1] |
| Kojto | 148:fd96258d940d | 614 | #define CHG2 CHG[2] |
| Kojto | 148:fd96258d940d | 615 | #define CHG3 CHG[3] |
| Kojto | 148:fd96258d940d | 616 | |
| Kojto | 148:fd96258d940d | 617 | /* All bitfield macros for the CHGx registers therefore changed name. */ |
| Kojto | 148:fd96258d940d | 618 | #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos |
| Kojto | 148:fd96258d940d | 619 | #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk |
| Kojto | 148:fd96258d940d | 620 | #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded |
| Kojto | 148:fd96258d940d | 621 | #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included |
| Kojto | 148:fd96258d940d | 622 | |
| Kojto | 148:fd96258d940d | 623 | #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos |
| Kojto | 148:fd96258d940d | 624 | #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk |
| Kojto | 148:fd96258d940d | 625 | #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded |
| Kojto | 148:fd96258d940d | 626 | #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included |
| Kojto | 148:fd96258d940d | 627 | |
| Kojto | 148:fd96258d940d | 628 | #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos |
| Kojto | 148:fd96258d940d | 629 | #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk |
| Kojto | 148:fd96258d940d | 630 | #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded |
| Kojto | 148:fd96258d940d | 631 | #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included |
| Kojto | 148:fd96258d940d | 632 | |
| Kojto | 148:fd96258d940d | 633 | #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos |
| Kojto | 148:fd96258d940d | 634 | #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk |
| Kojto | 148:fd96258d940d | 635 | #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded |
| Kojto | 148:fd96258d940d | 636 | #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included |
| Kojto | 148:fd96258d940d | 637 | |
| Kojto | 148:fd96258d940d | 638 | #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos |
| Kojto | 148:fd96258d940d | 639 | #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk |
| Kojto | 148:fd96258d940d | 640 | #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded |
| Kojto | 148:fd96258d940d | 641 | #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included |
| Kojto | 148:fd96258d940d | 642 | |
| Kojto | 148:fd96258d940d | 643 | #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos |
| Kojto | 148:fd96258d940d | 644 | #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk |
| Kojto | 148:fd96258d940d | 645 | #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded |
| Kojto | 148:fd96258d940d | 646 | #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included |
| Kojto | 148:fd96258d940d | 647 | |
| Kojto | 148:fd96258d940d | 648 | #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos |
| Kojto | 148:fd96258d940d | 649 | #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk |
| Kojto | 148:fd96258d940d | 650 | #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded |
| Kojto | 148:fd96258d940d | 651 | #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included |
| Kojto | 148:fd96258d940d | 652 | |
| Kojto | 148:fd96258d940d | 653 | #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos |
| Kojto | 148:fd96258d940d | 654 | #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk |
| Kojto | 148:fd96258d940d | 655 | #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded |
| Kojto | 148:fd96258d940d | 656 | #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included |
| Kojto | 148:fd96258d940d | 657 | |
| Kojto | 148:fd96258d940d | 658 | #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos |
| Kojto | 148:fd96258d940d | 659 | #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk |
| Kojto | 148:fd96258d940d | 660 | #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded |
| Kojto | 148:fd96258d940d | 661 | #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included |
| Kojto | 148:fd96258d940d | 662 | |
| Kojto | 148:fd96258d940d | 663 | #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos |
| Kojto | 148:fd96258d940d | 664 | #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk |
| Kojto | 148:fd96258d940d | 665 | #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded |
| Kojto | 148:fd96258d940d | 666 | #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included |
| Kojto | 148:fd96258d940d | 667 | |
| Kojto | 148:fd96258d940d | 668 | #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos |
| Kojto | 148:fd96258d940d | 669 | #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk |
| Kojto | 148:fd96258d940d | 670 | #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded |
| Kojto | 148:fd96258d940d | 671 | #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included |
| Kojto | 148:fd96258d940d | 672 | |
| Kojto | 148:fd96258d940d | 673 | #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos |
| Kojto | 148:fd96258d940d | 674 | #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk |
| Kojto | 148:fd96258d940d | 675 | #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded |
| Kojto | 148:fd96258d940d | 676 | #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included |
| Kojto | 148:fd96258d940d | 677 | |
| Kojto | 148:fd96258d940d | 678 | #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos |
| Kojto | 148:fd96258d940d | 679 | #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk |
| Kojto | 148:fd96258d940d | 680 | #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded |
| Kojto | 148:fd96258d940d | 681 | #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included |
| Kojto | 148:fd96258d940d | 682 | |
| Kojto | 148:fd96258d940d | 683 | #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos |
| Kojto | 148:fd96258d940d | 684 | #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk |
| Kojto | 148:fd96258d940d | 685 | #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded |
| Kojto | 148:fd96258d940d | 686 | #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included |
| Kojto | 148:fd96258d940d | 687 | |
| Kojto | 148:fd96258d940d | 688 | #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos |
| Kojto | 148:fd96258d940d | 689 | #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk |
| Kojto | 148:fd96258d940d | 690 | #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded |
| Kojto | 148:fd96258d940d | 691 | #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included |
| Kojto | 148:fd96258d940d | 692 | |
| Kojto | 148:fd96258d940d | 693 | #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos |
| Kojto | 148:fd96258d940d | 694 | #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk |
| Kojto | 148:fd96258d940d | 695 | #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded |
| Kojto | 148:fd96258d940d | 696 | #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included |
| Kojto | 148:fd96258d940d | 697 | |
| Kojto | 148:fd96258d940d | 698 | #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos |
| Kojto | 148:fd96258d940d | 699 | #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk |
| Kojto | 148:fd96258d940d | 700 | #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded |
| Kojto | 148:fd96258d940d | 701 | #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included |
| Kojto | 148:fd96258d940d | 702 | |
| Kojto | 148:fd96258d940d | 703 | #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos |
| Kojto | 148:fd96258d940d | 704 | #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk |
| Kojto | 148:fd96258d940d | 705 | #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded |
| Kojto | 148:fd96258d940d | 706 | #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included |
| Kojto | 148:fd96258d940d | 707 | |
| Kojto | 148:fd96258d940d | 708 | #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos |
| Kojto | 148:fd96258d940d | 709 | #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk |
| Kojto | 148:fd96258d940d | 710 | #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded |
| Kojto | 148:fd96258d940d | 711 | #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included |
| Kojto | 148:fd96258d940d | 712 | |
| Kojto | 148:fd96258d940d | 713 | #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos |
| Kojto | 148:fd96258d940d | 714 | #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk |
| Kojto | 148:fd96258d940d | 715 | #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded |
| Kojto | 148:fd96258d940d | 716 | #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included |
| Kojto | 148:fd96258d940d | 717 | |
| Kojto | 148:fd96258d940d | 718 | #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos |
| Kojto | 148:fd96258d940d | 719 | #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk |
| Kojto | 148:fd96258d940d | 720 | #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded |
| Kojto | 148:fd96258d940d | 721 | #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included |
| Kojto | 148:fd96258d940d | 722 | |
| Kojto | 148:fd96258d940d | 723 | #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos |
| Kojto | 148:fd96258d940d | 724 | #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk |
| Kojto | 148:fd96258d940d | 725 | #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded |
| Kojto | 148:fd96258d940d | 726 | #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included |
| Kojto | 148:fd96258d940d | 727 | |
| Kojto | 148:fd96258d940d | 728 | #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos |
| Kojto | 148:fd96258d940d | 729 | #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk |
| Kojto | 148:fd96258d940d | 730 | #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded |
| Kojto | 148:fd96258d940d | 731 | #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included |
| Kojto | 148:fd96258d940d | 732 | |
| Kojto | 148:fd96258d940d | 733 | #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos |
| Kojto | 148:fd96258d940d | 734 | #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk |
| Kojto | 148:fd96258d940d | 735 | #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded |
| Kojto | 148:fd96258d940d | 736 | #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included |
| Kojto | 148:fd96258d940d | 737 | |
| Kojto | 148:fd96258d940d | 738 | #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos |
| Kojto | 148:fd96258d940d | 739 | #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk |
| Kojto | 148:fd96258d940d | 740 | #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded |
| Kojto | 148:fd96258d940d | 741 | #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included |
| Kojto | 148:fd96258d940d | 742 | |
| Kojto | 148:fd96258d940d | 743 | #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos |
| Kojto | 148:fd96258d940d | 744 | #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk |
| Kojto | 148:fd96258d940d | 745 | #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded |
| Kojto | 148:fd96258d940d | 746 | #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included |
| Kojto | 148:fd96258d940d | 747 | |
| Kojto | 148:fd96258d940d | 748 | #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos |
| Kojto | 148:fd96258d940d | 749 | #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk |
| Kojto | 148:fd96258d940d | 750 | #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded |
| Kojto | 148:fd96258d940d | 751 | #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included |
| Kojto | 148:fd96258d940d | 752 | |
| Kojto | 148:fd96258d940d | 753 | #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos |
| Kojto | 148:fd96258d940d | 754 | #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk |
| Kojto | 148:fd96258d940d | 755 | #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded |
| Kojto | 148:fd96258d940d | 756 | #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included |
| Kojto | 148:fd96258d940d | 757 | |
| Kojto | 148:fd96258d940d | 758 | #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos |
| Kojto | 148:fd96258d940d | 759 | #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk |
| Kojto | 148:fd96258d940d | 760 | #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded |
| Kojto | 148:fd96258d940d | 761 | #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included |
| Kojto | 148:fd96258d940d | 762 | |
| Kojto | 148:fd96258d940d | 763 | #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos |
| Kojto | 148:fd96258d940d | 764 | #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk |
| Kojto | 148:fd96258d940d | 765 | #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded |
| Kojto | 148:fd96258d940d | 766 | #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included |
| Kojto | 148:fd96258d940d | 767 | |
| Kojto | 148:fd96258d940d | 768 | #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos |
| Kojto | 148:fd96258d940d | 769 | #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk |
| Kojto | 148:fd96258d940d | 770 | #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded |
| Kojto | 148:fd96258d940d | 771 | #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included |
| Kojto | 148:fd96258d940d | 772 | |
| Kojto | 148:fd96258d940d | 773 | #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos |
| Kojto | 148:fd96258d940d | 774 | #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk |
| Kojto | 148:fd96258d940d | 775 | #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded |
| Kojto | 148:fd96258d940d | 776 | #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included |
| Kojto | 148:fd96258d940d | 777 | |
| Kojto | 148:fd96258d940d | 778 | #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos |
| Kojto | 148:fd96258d940d | 779 | #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk |
| Kojto | 148:fd96258d940d | 780 | #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded |
| Kojto | 148:fd96258d940d | 781 | #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included |
| Kojto | 148:fd96258d940d | 782 | |
| Kojto | 148:fd96258d940d | 783 | #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos |
| Kojto | 148:fd96258d940d | 784 | #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk |
| Kojto | 148:fd96258d940d | 785 | #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded |
| Kojto | 148:fd96258d940d | 786 | #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included |
| Kojto | 148:fd96258d940d | 787 | |
| Kojto | 148:fd96258d940d | 788 | #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos |
| Kojto | 148:fd96258d940d | 789 | #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk |
| Kojto | 148:fd96258d940d | 790 | #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded |
| Kojto | 148:fd96258d940d | 791 | #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included |
| Kojto | 148:fd96258d940d | 792 | |
| Kojto | 148:fd96258d940d | 793 | #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos |
| Kojto | 148:fd96258d940d | 794 | #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk |
| Kojto | 148:fd96258d940d | 795 | #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded |
| Kojto | 148:fd96258d940d | 796 | #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included |
| Kojto | 148:fd96258d940d | 797 | |
| Kojto | 148:fd96258d940d | 798 | #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos |
| Kojto | 148:fd96258d940d | 799 | #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk |
| Kojto | 148:fd96258d940d | 800 | #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded |
| Kojto | 148:fd96258d940d | 801 | #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included |
| Kojto | 148:fd96258d940d | 802 | |
| Kojto | 148:fd96258d940d | 803 | #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos |
| Kojto | 148:fd96258d940d | 804 | #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk |
| Kojto | 148:fd96258d940d | 805 | #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded |
| Kojto | 148:fd96258d940d | 806 | #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included |
| Kojto | 148:fd96258d940d | 807 | |
| Kojto | 148:fd96258d940d | 808 | #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos |
| Kojto | 148:fd96258d940d | 809 | #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk |
| Kojto | 148:fd96258d940d | 810 | #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded |
| Kojto | 148:fd96258d940d | 811 | #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included |
| Kojto | 148:fd96258d940d | 812 | |
| Kojto | 148:fd96258d940d | 813 | #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos |
| Kojto | 148:fd96258d940d | 814 | #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk |
| Kojto | 148:fd96258d940d | 815 | #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded |
| Kojto | 148:fd96258d940d | 816 | #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included |
| Kojto | 148:fd96258d940d | 817 | |
| Kojto | 148:fd96258d940d | 818 | #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos |
| Kojto | 148:fd96258d940d | 819 | #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk |
| Kojto | 148:fd96258d940d | 820 | #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded |
| Kojto | 148:fd96258d940d | 821 | #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included |
| Kojto | 148:fd96258d940d | 822 | |
| Kojto | 148:fd96258d940d | 823 | #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos |
| Kojto | 148:fd96258d940d | 824 | #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk |
| Kojto | 148:fd96258d940d | 825 | #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded |
| Kojto | 148:fd96258d940d | 826 | #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included |
| Kojto | 148:fd96258d940d | 827 | |
| Kojto | 148:fd96258d940d | 828 | #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos |
| Kojto | 148:fd96258d940d | 829 | #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk |
| Kojto | 148:fd96258d940d | 830 | #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded |
| Kojto | 148:fd96258d940d | 831 | #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included |
| Kojto | 148:fd96258d940d | 832 | |
| Kojto | 148:fd96258d940d | 833 | #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos |
| Kojto | 148:fd96258d940d | 834 | #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk |
| Kojto | 148:fd96258d940d | 835 | #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded |
| Kojto | 148:fd96258d940d | 836 | #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included |
| Kojto | 148:fd96258d940d | 837 | |
| Kojto | 148:fd96258d940d | 838 | #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos |
| Kojto | 148:fd96258d940d | 839 | #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk |
| Kojto | 148:fd96258d940d | 840 | #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded |
| Kojto | 148:fd96258d940d | 841 | #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included |
| Kojto | 148:fd96258d940d | 842 | |
| Kojto | 148:fd96258d940d | 843 | #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos |
| Kojto | 148:fd96258d940d | 844 | #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk |
| Kojto | 148:fd96258d940d | 845 | #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded |
| Kojto | 148:fd96258d940d | 846 | #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included |
| Kojto | 148:fd96258d940d | 847 | |
| Kojto | 148:fd96258d940d | 848 | #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos |
| Kojto | 148:fd96258d940d | 849 | #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk |
| Kojto | 148:fd96258d940d | 850 | #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded |
| Kojto | 148:fd96258d940d | 851 | #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included |
| Kojto | 148:fd96258d940d | 852 | |
| Kojto | 148:fd96258d940d | 853 | #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos |
| Kojto | 148:fd96258d940d | 854 | #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk |
| Kojto | 148:fd96258d940d | 855 | #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded |
| Kojto | 148:fd96258d940d | 856 | #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included |
| Kojto | 148:fd96258d940d | 857 | |
| Kojto | 148:fd96258d940d | 858 | #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos |
| Kojto | 148:fd96258d940d | 859 | #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk |
| Kojto | 148:fd96258d940d | 860 | #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded |
| Kojto | 148:fd96258d940d | 861 | #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included |
| Kojto | 148:fd96258d940d | 862 | |
| Kojto | 148:fd96258d940d | 863 | #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos |
| Kojto | 148:fd96258d940d | 864 | #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk |
| Kojto | 148:fd96258d940d | 865 | #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded |
| Kojto | 148:fd96258d940d | 866 | #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included |
| Kojto | 148:fd96258d940d | 867 | |
| Kojto | 148:fd96258d940d | 868 | #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos |
| Kojto | 148:fd96258d940d | 869 | #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk |
| Kojto | 148:fd96258d940d | 870 | #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded |
| Kojto | 148:fd96258d940d | 871 | #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included |
| Kojto | 148:fd96258d940d | 872 | |
| Kojto | 148:fd96258d940d | 873 | #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos |
| Kojto | 148:fd96258d940d | 874 | #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk |
| Kojto | 148:fd96258d940d | 875 | #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded |
| Kojto | 148:fd96258d940d | 876 | #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included |
| Kojto | 148:fd96258d940d | 877 | |
| Kojto | 148:fd96258d940d | 878 | #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos |
| Kojto | 148:fd96258d940d | 879 | #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk |
| Kojto | 148:fd96258d940d | 880 | #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded |
| Kojto | 148:fd96258d940d | 881 | #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included |
| Kojto | 148:fd96258d940d | 882 | |
| Kojto | 148:fd96258d940d | 883 | #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos |
| Kojto | 148:fd96258d940d | 884 | #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk |
| Kojto | 148:fd96258d940d | 885 | #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded |
| Kojto | 148:fd96258d940d | 886 | #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included |
| Kojto | 148:fd96258d940d | 887 | |
| Kojto | 148:fd96258d940d | 888 | #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos |
| Kojto | 148:fd96258d940d | 889 | #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk |
| Kojto | 148:fd96258d940d | 890 | #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded |
| Kojto | 148:fd96258d940d | 891 | #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included |
| Kojto | 148:fd96258d940d | 892 | |
| Kojto | 148:fd96258d940d | 893 | #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos |
| Kojto | 148:fd96258d940d | 894 | #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk |
| Kojto | 148:fd96258d940d | 895 | #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded |
| Kojto | 148:fd96258d940d | 896 | #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included |
| Kojto | 148:fd96258d940d | 897 | |
| Kojto | 148:fd96258d940d | 898 | #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos |
| Kojto | 148:fd96258d940d | 899 | #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk |
| Kojto | 148:fd96258d940d | 900 | #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded |
| Kojto | 148:fd96258d940d | 901 | #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included |
| Kojto | 148:fd96258d940d | 902 | |
| Kojto | 148:fd96258d940d | 903 | #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos |
| Kojto | 148:fd96258d940d | 904 | #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk |
| Kojto | 148:fd96258d940d | 905 | #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded |
| Kojto | 148:fd96258d940d | 906 | #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included |
| Kojto | 148:fd96258d940d | 907 | |
| Kojto | 148:fd96258d940d | 908 | #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos |
| Kojto | 148:fd96258d940d | 909 | #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk |
| Kojto | 148:fd96258d940d | 910 | #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded |
| Kojto | 148:fd96258d940d | 911 | #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included |
| Kojto | 148:fd96258d940d | 912 | |
| Kojto | 148:fd96258d940d | 913 | #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos |
| Kojto | 148:fd96258d940d | 914 | #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk |
| Kojto | 148:fd96258d940d | 915 | #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded |
| Kojto | 148:fd96258d940d | 916 | #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included |
| Kojto | 148:fd96258d940d | 917 | |
| Kojto | 148:fd96258d940d | 918 | #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos |
| Kojto | 148:fd96258d940d | 919 | #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk |
| Kojto | 148:fd96258d940d | 920 | #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded |
| Kojto | 148:fd96258d940d | 921 | #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included |
| Kojto | 148:fd96258d940d | 922 | |
| Kojto | 148:fd96258d940d | 923 | #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos |
| Kojto | 148:fd96258d940d | 924 | #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk |
| Kojto | 148:fd96258d940d | 925 | #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded |
| Kojto | 148:fd96258d940d | 926 | #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included |
| Kojto | 148:fd96258d940d | 927 | |
| Kojto | 148:fd96258d940d | 928 | #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos |
| Kojto | 148:fd96258d940d | 929 | #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk |
| Kojto | 148:fd96258d940d | 930 | #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded |
| Kojto | 148:fd96258d940d | 931 | #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included |
| Kojto | 148:fd96258d940d | 932 | |
| Kojto | 148:fd96258d940d | 933 | #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos |
| Kojto | 148:fd96258d940d | 934 | #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk |
| Kojto | 148:fd96258d940d | 935 | #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded |
| Kojto | 148:fd96258d940d | 936 | #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included |
| Kojto | 148:fd96258d940d | 937 | |
| Kojto | 148:fd96258d940d | 938 | |
| Kojto | 148:fd96258d940d | 939 | |
| Kojto | 148:fd96258d940d | 940 | |
| Kojto | 148:fd96258d940d | 941 | /*lint --flb "Leave library region" */ |
| Kojto | 148:fd96258d940d | 942 | |
| Kojto | 148:fd96258d940d | 943 | #endif /* NRF51_TO_NRF52_H */ |
| Kojto | 148:fd96258d940d | 944 |
