mbed official
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_TB_SENSE_12/TOOLCHAIN_IAR/efr32mg12p_trng.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg12p_trng.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG12P_TRNG register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG12P_TRNG |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG12P_TRNG Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CONTROL; /**< Main Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 46 | __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IOM uint32_t KEY0; /**< Key Register 0 */ |
| Anna Bridge |
142:4eea097334d6 | 48 | __IOM uint32_t KEY1; /**< Key Register 1 */ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IOM uint32_t KEY2; /**< Key Register 2 */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IOM uint32_t KEY3; /**< Key Register 3 */ |
| Anna Bridge |
142:4eea097334d6 | 51 | __IOM uint32_t TESTDATA; /**< Test Data Register */ |
| Anna Bridge |
142:4eea097334d6 | 52 | |
| Anna Bridge |
142:4eea097334d6 | 53 | uint32_t RESERVED1[3]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IOM uint32_t STATUS; /**< Status Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ |
| Anna Bridge |
142:4eea097334d6 | 56 | uint32_t RESERVED2[50]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 57 | __IM uint32_t FIFO; /**< FIFO Data */ |
| Anna Bridge |
142:4eea097334d6 | 58 | } TRNG_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 59 | |
| Anna Bridge |
142:4eea097334d6 | 60 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 61 | * @defgroup EFR32MG12P_TRNG_BitFields |
| Anna Bridge |
142:4eea097334d6 | 62 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 63 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 64 | |
| Anna Bridge |
142:4eea097334d6 | 65 | /* Bit fields for TRNG CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 66 | #define _TRNG_CONTROL_RESETVALUE 0x00000000UL /**< Default value for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 67 | #define _TRNG_CONTROL_MASK 0x00003FFDUL /**< Mask for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 68 | #define TRNG_CONTROL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ |
| Anna Bridge |
142:4eea097334d6 | 69 | #define _TRNG_CONTROL_ENABLE_SHIFT 0 /**< Shift value for TRNG_ENABLE */ |
| Anna Bridge |
142:4eea097334d6 | 70 | #define _TRNG_CONTROL_ENABLE_MASK 0x1UL /**< Bit mask for TRNG_ENABLE */ |
| Anna Bridge |
142:4eea097334d6 | 71 | #define _TRNG_CONTROL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 72 | #define _TRNG_CONTROL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 73 | #define _TRNG_CONTROL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 74 | #define TRNG_CONTROL_ENABLE_DEFAULT (_TRNG_CONTROL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 75 | #define TRNG_CONTROL_ENABLE_DISABLED (_TRNG_CONTROL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define TRNG_CONTROL_ENABLE_ENABLED (_TRNG_CONTROL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define TRNG_CONTROL_TESTEN (0x1UL << 2) /**< Test Enable */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define _TRNG_CONTROL_TESTEN_SHIFT 2 /**< Shift value for TRNG_TESTEN */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define _TRNG_CONTROL_TESTEN_MASK 0x4UL /**< Bit mask for TRNG_TESTEN */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define _TRNG_CONTROL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define _TRNG_CONTROL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define _TRNG_CONTROL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define TRNG_CONTROL_TESTEN_DEFAULT (_TRNG_CONTROL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define TRNG_CONTROL_TESTEN_NOISE (_TRNG_CONTROL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define TRNG_CONTROL_TESTEN_TESTDATA (_TRNG_CONTROL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define TRNG_CONTROL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ |
| Anna Bridge |
142:4eea097334d6 | 87 | #define _TRNG_CONTROL_CONDBYPASS_SHIFT 3 /**< Shift value for TRNG_CONDBYPASS */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define _TRNG_CONTROL_CONDBYPASS_MASK 0x8UL /**< Bit mask for TRNG_CONDBYPASS */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define _TRNG_CONTROL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define _TRNG_CONTROL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define _TRNG_CONTROL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define TRNG_CONTROL_CONDBYPASS_DEFAULT (_TRNG_CONTROL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define TRNG_CONTROL_CONDBYPASS_NORMAL (_TRNG_CONTROL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define TRNG_CONTROL_CONDBYPASS_BYPASS (_TRNG_CONTROL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define TRNG_CONTROL_REPCOUNTIEN (0x1UL << 4) /**< Interrupt enable for Repetition Count Test failure */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define _TRNG_CONTROL_REPCOUNTIEN_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIEN */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _TRNG_CONTROL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIEN */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _TRNG_CONTROL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define TRNG_CONTROL_REPCOUNTIEN_DEFAULT (_TRNG_CONTROL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define TRNG_CONTROL_APT64IEN (0x1UL << 5) /**< Interrupt enable for Adaptive Proportion Test failure (64-sample window) */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define _TRNG_CONTROL_APT64IEN_SHIFT 5 /**< Shift value for TRNG_APT64IEN */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define _TRNG_CONTROL_APT64IEN_MASK 0x20UL /**< Bit mask for TRNG_APT64IEN */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define _TRNG_CONTROL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define TRNG_CONTROL_APT64IEN_DEFAULT (_TRNG_CONTROL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define TRNG_CONTROL_APT4096IEN (0x1UL << 6) /**< Interrupt enable for Adaptive Proportion Test failure (4096-sample window) */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define _TRNG_CONTROL_APT4096IEN_SHIFT 6 /**< Shift value for TRNG_APT4096IEN */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define _TRNG_CONTROL_APT4096IEN_MASK 0x40UL /**< Bit mask for TRNG_APT4096IEN */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _TRNG_CONTROL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define TRNG_CONTROL_APT4096IEN_DEFAULT (_TRNG_CONTROL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define TRNG_CONTROL_FULLIEN (0x1UL << 7) /**< Interrupt enable for FIFO full */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define _TRNG_CONTROL_FULLIEN_SHIFT 7 /**< Shift value for TRNG_FULLIEN */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _TRNG_CONTROL_FULLIEN_MASK 0x80UL /**< Bit mask for TRNG_FULLIEN */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define _TRNG_CONTROL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define TRNG_CONTROL_FULLIEN_DEFAULT (_TRNG_CONTROL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define TRNG_CONTROL_SOFTRESET (0x1UL << 8) /**< Software Reset */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define _TRNG_CONTROL_SOFTRESET_SHIFT 8 /**< Shift value for TRNG_SOFTRESET */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define _TRNG_CONTROL_SOFTRESET_MASK 0x100UL /**< Bit mask for TRNG_SOFTRESET */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define _TRNG_CONTROL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define _TRNG_CONTROL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define _TRNG_CONTROL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define TRNG_CONTROL_SOFTRESET_DEFAULT (_TRNG_CONTROL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define TRNG_CONTROL_SOFTRESET_NORMAL (_TRNG_CONTROL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define TRNG_CONTROL_SOFTRESET_RESET (_TRNG_CONTROL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define TRNG_CONTROL_PREIEN (0x1UL << 9) /**< Interrupt enable for AIS31 preliminary noise alarm */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define _TRNG_CONTROL_PREIEN_SHIFT 9 /**< Shift value for TRNG_PREIEN */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define _TRNG_CONTROL_PREIEN_MASK 0x200UL /**< Bit mask for TRNG_PREIEN */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define _TRNG_CONTROL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define TRNG_CONTROL_PREIEN_DEFAULT (_TRNG_CONTROL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define TRNG_CONTROL_ALMIEN (0x1UL << 10) /**< Interrupt enable for AIS31 noise alarm */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define _TRNG_CONTROL_ALMIEN_SHIFT 10 /**< Shift value for TRNG_ALMIEN */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define _TRNG_CONTROL_ALMIEN_MASK 0x400UL /**< Bit mask for TRNG_ALMIEN */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define _TRNG_CONTROL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define TRNG_CONTROL_ALMIEN_DEFAULT (_TRNG_CONTROL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define TRNG_CONTROL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define _TRNG_CONTROL_FORCERUN_SHIFT 11 /**< Shift value for TRNG_FORCERUN */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define _TRNG_CONTROL_FORCERUN_MASK 0x800UL /**< Bit mask for TRNG_FORCERUN */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define _TRNG_CONTROL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define _TRNG_CONTROL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define _TRNG_CONTROL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define TRNG_CONTROL_FORCERUN_DEFAULT (_TRNG_CONTROL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 141 | #define TRNG_CONTROL_FORCERUN_NORMAL (_TRNG_CONTROL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define TRNG_CONTROL_FORCERUN_RUN (_TRNG_CONTROL_FORCERUN_RUN << 11) /**< Shifted mode RUN for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define TRNG_CONTROL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define _TRNG_CONTROL_BYPNIST_SHIFT 12 /**< Shift value for TRNG_BYPNIST */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define _TRNG_CONTROL_BYPNIST_MASK 0x1000UL /**< Bit mask for TRNG_BYPNIST */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _TRNG_CONTROL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _TRNG_CONTROL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _TRNG_CONTROL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define TRNG_CONTROL_BYPNIST_DEFAULT (_TRNG_CONTROL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define TRNG_CONTROL_BYPNIST_NORMAL (_TRNG_CONTROL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define TRNG_CONTROL_BYPNIST_BYPASS (_TRNG_CONTROL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define TRNG_CONTROL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define _TRNG_CONTROL_BYPAIS31_SHIFT 13 /**< Shift value for TRNG_BYPAIS31 */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define _TRNG_CONTROL_BYPAIS31_MASK 0x2000UL /**< Bit mask for TRNG_BYPAIS31 */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define _TRNG_CONTROL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 156 | #define _TRNG_CONTROL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define _TRNG_CONTROL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define TRNG_CONTROL_BYPAIS31_DEFAULT (_TRNG_CONTROL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define TRNG_CONTROL_BYPAIS31_NORMAL (_TRNG_CONTROL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define TRNG_CONTROL_BYPAIS31_BYPASS (_TRNG_CONTROL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for TRNG_CONTROL */ |
| Anna Bridge |
142:4eea097334d6 | 161 | |
| Anna Bridge |
142:4eea097334d6 | 162 | /* Bit fields for TRNG FIFOLEVEL */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define _TRNG_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFOLEVEL */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define _TRNG_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFOLEVEL */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define _TRNG_FIFOLEVEL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define _TRNG_FIFOLEVEL_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 167 | #define _TRNG_FIFOLEVEL_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFOLEVEL */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define TRNG_FIFOLEVEL_VALUE_DEFAULT (_TRNG_FIFOLEVEL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFOLEVEL */ |
| Anna Bridge |
142:4eea097334d6 | 169 | |
| Anna Bridge |
142:4eea097334d6 | 170 | /* Bit fields for TRNG FIFODEPTH */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _TRNG_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for TRNG_FIFODEPTH */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define _TRNG_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFODEPTH */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define _TRNG_FIFODEPTH_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 174 | #define _TRNG_FIFODEPTH_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 175 | #define _TRNG_FIFODEPTH_VALUE_DEFAULT 0x00000040UL /**< Mode DEFAULT for TRNG_FIFODEPTH */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define TRNG_FIFODEPTH_VALUE_DEFAULT (_TRNG_FIFODEPTH_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFODEPTH */ |
| Anna Bridge |
142:4eea097334d6 | 177 | |
| Anna Bridge |
142:4eea097334d6 | 178 | /* Bit fields for TRNG KEY0 */ |
| Anna Bridge |
142:4eea097334d6 | 179 | #define _TRNG_KEY0_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY0 */ |
| Anna Bridge |
142:4eea097334d6 | 180 | #define _TRNG_KEY0_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY0 */ |
| Anna Bridge |
142:4eea097334d6 | 181 | #define _TRNG_KEY0_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 182 | #define _TRNG_KEY0_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 183 | #define _TRNG_KEY0_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY0 */ |
| Anna Bridge |
142:4eea097334d6 | 184 | #define TRNG_KEY0_VALUE_DEFAULT (_TRNG_KEY0_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY0 */ |
| Anna Bridge |
142:4eea097334d6 | 185 | |
| Anna Bridge |
142:4eea097334d6 | 186 | /* Bit fields for TRNG KEY1 */ |
| Anna Bridge |
142:4eea097334d6 | 187 | #define _TRNG_KEY1_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY1 */ |
| Anna Bridge |
142:4eea097334d6 | 188 | #define _TRNG_KEY1_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY1 */ |
| Anna Bridge |
142:4eea097334d6 | 189 | #define _TRNG_KEY1_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 190 | #define _TRNG_KEY1_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 191 | #define _TRNG_KEY1_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY1 */ |
| Anna Bridge |
142:4eea097334d6 | 192 | #define TRNG_KEY1_VALUE_DEFAULT (_TRNG_KEY1_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY1 */ |
| Anna Bridge |
142:4eea097334d6 | 193 | |
| Anna Bridge |
142:4eea097334d6 | 194 | /* Bit fields for TRNG KEY2 */ |
| Anna Bridge |
142:4eea097334d6 | 195 | #define _TRNG_KEY2_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY2 */ |
| Anna Bridge |
142:4eea097334d6 | 196 | #define _TRNG_KEY2_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY2 */ |
| Anna Bridge |
142:4eea097334d6 | 197 | #define _TRNG_KEY2_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 198 | #define _TRNG_KEY2_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 199 | #define _TRNG_KEY2_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY2 */ |
| Anna Bridge |
142:4eea097334d6 | 200 | #define TRNG_KEY2_VALUE_DEFAULT (_TRNG_KEY2_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY2 */ |
| Anna Bridge |
142:4eea097334d6 | 201 | |
| Anna Bridge |
142:4eea097334d6 | 202 | /* Bit fields for TRNG KEY3 */ |
| Anna Bridge |
142:4eea097334d6 | 203 | #define _TRNG_KEY3_RESETVALUE 0x00000000UL /**< Default value for TRNG_KEY3 */ |
| Anna Bridge |
142:4eea097334d6 | 204 | #define _TRNG_KEY3_MASK 0xFFFFFFFFUL /**< Mask for TRNG_KEY3 */ |
| Anna Bridge |
142:4eea097334d6 | 205 | #define _TRNG_KEY3_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 206 | #define _TRNG_KEY3_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 207 | #define _TRNG_KEY3_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_KEY3 */ |
| Anna Bridge |
142:4eea097334d6 | 208 | #define TRNG_KEY3_VALUE_DEFAULT (_TRNG_KEY3_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_KEY3 */ |
| Anna Bridge |
142:4eea097334d6 | 209 | |
| Anna Bridge |
142:4eea097334d6 | 210 | /* Bit fields for TRNG TESTDATA */ |
| Anna Bridge |
142:4eea097334d6 | 211 | #define _TRNG_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for TRNG_TESTDATA */ |
| Anna Bridge |
142:4eea097334d6 | 212 | #define _TRNG_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for TRNG_TESTDATA */ |
| Anna Bridge |
142:4eea097334d6 | 213 | #define _TRNG_TESTDATA_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 214 | #define _TRNG_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 215 | #define _TRNG_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_TESTDATA */ |
| Anna Bridge |
142:4eea097334d6 | 216 | #define TRNG_TESTDATA_VALUE_DEFAULT (_TRNG_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_TESTDATA */ |
| Anna Bridge |
142:4eea097334d6 | 217 | |
| Anna Bridge |
142:4eea097334d6 | 218 | /* Bit fields for TRNG STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 219 | #define _TRNG_STATUS_RESETVALUE 0x00000000UL /**< Default value for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 220 | #define _TRNG_STATUS_MASK 0x000003F1UL /**< Mask for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 221 | #define TRNG_STATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ |
| Anna Bridge |
142:4eea097334d6 | 222 | #define _TRNG_STATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for TRNG_TESTDATABUSY */ |
| Anna Bridge |
142:4eea097334d6 | 223 | #define _TRNG_STATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for TRNG_TESTDATABUSY */ |
| Anna Bridge |
142:4eea097334d6 | 224 | #define _TRNG_STATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 225 | #define _TRNG_STATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 226 | #define _TRNG_STATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 227 | #define TRNG_STATUS_TESTDATABUSY_DEFAULT (_TRNG_STATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 228 | #define TRNG_STATUS_TESTDATABUSY_IDLE (_TRNG_STATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 229 | #define TRNG_STATUS_TESTDATABUSY_BUSY (_TRNG_STATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 230 | #define TRNG_STATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ |
| Anna Bridge |
142:4eea097334d6 | 231 | #define _TRNG_STATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for TRNG_REPCOUNTIF */ |
| Anna Bridge |
142:4eea097334d6 | 232 | #define _TRNG_STATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for TRNG_REPCOUNTIF */ |
| Anna Bridge |
142:4eea097334d6 | 233 | #define _TRNG_STATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 234 | #define TRNG_STATUS_REPCOUNTIF_DEFAULT (_TRNG_STATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 235 | #define TRNG_STATUS_APT64IF (0x1UL << 5) /**< Adaptive Proportion test failure (64-sample window) interrupt status */ |
| Anna Bridge |
142:4eea097334d6 | 236 | #define _TRNG_STATUS_APT64IF_SHIFT 5 /**< Shift value for TRNG_APT64IF */ |
| Anna Bridge |
142:4eea097334d6 | 237 | #define _TRNG_STATUS_APT64IF_MASK 0x20UL /**< Bit mask for TRNG_APT64IF */ |
| Anna Bridge |
142:4eea097334d6 | 238 | #define _TRNG_STATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 239 | #define TRNG_STATUS_APT64IF_DEFAULT (_TRNG_STATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 240 | #define TRNG_STATUS_APT4096IF (0x1UL << 6) /**< Adaptive Proportion test failure (4096-sample window) interrupt status */ |
| Anna Bridge |
142:4eea097334d6 | 241 | #define _TRNG_STATUS_APT4096IF_SHIFT 6 /**< Shift value for TRNG_APT4096IF */ |
| Anna Bridge |
142:4eea097334d6 | 242 | #define _TRNG_STATUS_APT4096IF_MASK 0x40UL /**< Bit mask for TRNG_APT4096IF */ |
| Anna Bridge |
142:4eea097334d6 | 243 | #define _TRNG_STATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 244 | #define TRNG_STATUS_APT4096IF_DEFAULT (_TRNG_STATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 245 | #define TRNG_STATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ |
| Anna Bridge |
142:4eea097334d6 | 246 | #define _TRNG_STATUS_FULLIF_SHIFT 7 /**< Shift value for TRNG_FULLIF */ |
| Anna Bridge |
142:4eea097334d6 | 247 | #define _TRNG_STATUS_FULLIF_MASK 0x80UL /**< Bit mask for TRNG_FULLIF */ |
| Anna Bridge |
142:4eea097334d6 | 248 | #define _TRNG_STATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 249 | #define TRNG_STATUS_FULLIF_DEFAULT (_TRNG_STATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 250 | #define TRNG_STATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm interrupt status */ |
| Anna Bridge |
142:4eea097334d6 | 251 | #define _TRNG_STATUS_PREIF_SHIFT 8 /**< Shift value for TRNG_PREIF */ |
| Anna Bridge |
142:4eea097334d6 | 252 | #define _TRNG_STATUS_PREIF_MASK 0x100UL /**< Bit mask for TRNG_PREIF */ |
| Anna Bridge |
142:4eea097334d6 | 253 | #define _TRNG_STATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 254 | #define TRNG_STATUS_PREIF_DEFAULT (_TRNG_STATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 255 | #define TRNG_STATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ |
| Anna Bridge |
142:4eea097334d6 | 256 | #define _TRNG_STATUS_ALMIF_SHIFT 9 /**< Shift value for TRNG_ALMIF */ |
| Anna Bridge |
142:4eea097334d6 | 257 | #define _TRNG_STATUS_ALMIF_MASK 0x200UL /**< Bit mask for TRNG_ALMIF */ |
| Anna Bridge |
142:4eea097334d6 | 258 | #define _TRNG_STATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 259 | #define TRNG_STATUS_ALMIF_DEFAULT (_TRNG_STATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for TRNG_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 260 | |
| Anna Bridge |
142:4eea097334d6 | 261 | /* Bit fields for TRNG INITWAITVAL */ |
| Anna Bridge |
142:4eea097334d6 | 262 | #define _TRNG_INITWAITVAL_RESETVALUE 0x000000FFUL /**< Default value for TRNG_INITWAITVAL */ |
| Anna Bridge |
142:4eea097334d6 | 263 | #define _TRNG_INITWAITVAL_MASK 0x000000FFUL /**< Mask for TRNG_INITWAITVAL */ |
| Anna Bridge |
142:4eea097334d6 | 264 | #define _TRNG_INITWAITVAL_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 265 | #define _TRNG_INITWAITVAL_VALUE_MASK 0xFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 266 | #define _TRNG_INITWAITVAL_VALUE_DEFAULT 0x000000FFUL /**< Mode DEFAULT for TRNG_INITWAITVAL */ |
| Anna Bridge |
142:4eea097334d6 | 267 | #define TRNG_INITWAITVAL_VALUE_DEFAULT (_TRNG_INITWAITVAL_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_INITWAITVAL */ |
| Anna Bridge |
142:4eea097334d6 | 268 | |
| Anna Bridge |
142:4eea097334d6 | 269 | /* Bit fields for TRNG FIFO */ |
| Anna Bridge |
142:4eea097334d6 | 270 | #define _TRNG_FIFO_RESETVALUE 0x00000000UL /**< Default value for TRNG_FIFO */ |
| Anna Bridge |
142:4eea097334d6 | 271 | #define _TRNG_FIFO_MASK 0xFFFFFFFFUL /**< Mask for TRNG_FIFO */ |
| Anna Bridge |
142:4eea097334d6 | 272 | #define _TRNG_FIFO_VALUE_SHIFT 0 /**< Shift value for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 273 | #define _TRNG_FIFO_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for TRNG_VALUE */ |
| Anna Bridge |
142:4eea097334d6 | 274 | #define _TRNG_FIFO_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TRNG_FIFO */ |
| Anna Bridge |
142:4eea097334d6 | 275 | #define TRNG_FIFO_VALUE_DEFAULT (_TRNG_FIFO_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for TRNG_FIFO */ |
| Anna Bridge |
142:4eea097334d6 | 276 | |
| Anna Bridge |
142:4eea097334d6 | 277 | /** @} End of group EFR32MG12P_TRNG */ |
| Anna Bridge |
142:4eea097334d6 | 278 | /** @} End of group Parts */ |
| Anna Bridge |
142:4eea097334d6 | 279 |
