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TARGET_TB_SENSE_12/TOOLCHAIN_IAR/efr32mg12p_etm.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file efr32mg12p_etm.h
Anna Bridge 142:4eea097334d6 3 * @brief EFR32MG12P_ETM register and bit field definitions
Anna Bridge 142:4eea097334d6 4 * @version 5.1.2
Anna Bridge 142:4eea097334d6 5 ******************************************************************************
Anna Bridge 142:4eea097334d6 6 * @section License
Anna Bridge 142:4eea097334d6 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
Anna Bridge 142:4eea097334d6 8 ******************************************************************************
Anna Bridge 142:4eea097334d6 9 *
Anna Bridge 142:4eea097334d6 10 * Permission is granted to anyone to use this software for any purpose,
Anna Bridge 142:4eea097334d6 11 * including commercial applications, and to alter it and redistribute it
Anna Bridge 142:4eea097334d6 12 * freely, subject to the following restrictions:
Anna Bridge 142:4eea097334d6 13 *
Anna Bridge 142:4eea097334d6 14 * 1. The origin of this software must not be misrepresented; you must not
Anna Bridge 142:4eea097334d6 15 * claim that you wrote the original software.@n
Anna Bridge 142:4eea097334d6 16 * 2. Altered source versions must be plainly marked as such, and must not be
Anna Bridge 142:4eea097334d6 17 * misrepresented as being the original software.@n
Anna Bridge 142:4eea097334d6 18 * 3. This notice may not be removed or altered from any source distribution.
Anna Bridge 142:4eea097334d6 19 *
Anna Bridge 142:4eea097334d6 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Anna Bridge 142:4eea097334d6 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Anna Bridge 142:4eea097334d6 22 * providing the Software "AS IS", with no express or implied warranties of any
Anna Bridge 142:4eea097334d6 23 * kind, including, but not limited to, any implied warranties of
Anna Bridge 142:4eea097334d6 24 * merchantability or fitness for any particular purpose or warranties against
Anna Bridge 142:4eea097334d6 25 * infringement of any proprietary rights of a third party.
Anna Bridge 142:4eea097334d6 26 *
Anna Bridge 142:4eea097334d6 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
Anna Bridge 142:4eea097334d6 28 * incidental, or special damages, or any other relief, or for any claim by
Anna Bridge 142:4eea097334d6 29 * any third party, arising from your use of this Software.
Anna Bridge 142:4eea097334d6 30 *
Anna Bridge 142:4eea097334d6 31 *****************************************************************************/
Anna Bridge 142:4eea097334d6 32 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 33 * @addtogroup Parts
Anna Bridge 142:4eea097334d6 34 * @{
Anna Bridge 142:4eea097334d6 35 ******************************************************************************/
Anna Bridge 142:4eea097334d6 36 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 37 * @defgroup EFR32MG12P_ETM
Anna Bridge 142:4eea097334d6 38 * @{
Anna Bridge 142:4eea097334d6 39 * @brief EFR32MG12P_ETM Register Declaration
Anna Bridge 142:4eea097334d6 40 *****************************************************************************/
Anna Bridge 142:4eea097334d6 41 typedef struct
Anna Bridge 142:4eea097334d6 42 {
Anna Bridge 142:4eea097334d6 43 __IOM uint32_t ETMCR; /**< Main Control Register */
Anna Bridge 142:4eea097334d6 44 __IM uint32_t ETMCCR; /**< Configuration Code Register */
Anna Bridge 142:4eea097334d6 45 __IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
Anna Bridge 142:4eea097334d6 46 uint32_t RESERVED0[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 47 __IOM uint32_t ETMSR; /**< ETM Status Register */
Anna Bridge 142:4eea097334d6 48 __IM uint32_t ETMSCR; /**< ETM System Configuration Register */
Anna Bridge 142:4eea097334d6 49 uint32_t RESERVED1[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 50 __IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
Anna Bridge 142:4eea097334d6 51 __IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
Anna Bridge 142:4eea097334d6 52 uint32_t RESERVED2[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 53 __IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
Anna Bridge 142:4eea097334d6 54 uint32_t RESERVED3[68]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 55 __IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
Anna Bridge 142:4eea097334d6 56 uint32_t RESERVED4[39]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 57 __IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
Anna Bridge 142:4eea097334d6 58 __IM uint32_t ETMIDR; /**< ID Register */
Anna Bridge 142:4eea097334d6 59 __IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
Anna Bridge 142:4eea097334d6 60 uint32_t RESERVED5[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 61 __IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
Anna Bridge 142:4eea097334d6 62 uint32_t RESERVED6[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 63 __IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
Anna Bridge 142:4eea097334d6 64 uint32_t RESERVED7[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 65 __IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
Anna Bridge 142:4eea097334d6 66 uint32_t RESERVED8[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 67 __IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
Anna Bridge 142:4eea097334d6 68 uint32_t RESERVED9[66]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 69 __IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
Anna Bridge 142:4eea097334d6 70 uint32_t RESERVED10[754]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 71 __IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
Anna Bridge 142:4eea097334d6 72 uint32_t RESERVED11[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 73 __IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
Anna Bridge 142:4eea097334d6 74 uint32_t RESERVED12[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 75 __IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
Anna Bridge 142:4eea097334d6 76 uint32_t RESERVED13[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 77 __IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
Anna Bridge 142:4eea097334d6 78 uint32_t RESERVED14[1]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 79 __IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
Anna Bridge 142:4eea097334d6 80 uint32_t RESERVED15[39]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 81 __IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
Anna Bridge 142:4eea097334d6 82 __IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
Anna Bridge 142:4eea097334d6 83 uint32_t RESERVED16[2]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 84 __IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
Anna Bridge 142:4eea097334d6 85 __IM uint32_t ETMLSR; /**< Lock Status Register */
Anna Bridge 142:4eea097334d6 86 __IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
Anna Bridge 142:4eea097334d6 87 uint32_t RESERVED17[4]; /**< Reserved for future use **/
Anna Bridge 142:4eea097334d6 88 __IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
Anna Bridge 142:4eea097334d6 89 __IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
Anna Bridge 142:4eea097334d6 90 __OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
Anna Bridge 142:4eea097334d6 91 __OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
Anna Bridge 142:4eea097334d6 92 __OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
Anna Bridge 142:4eea097334d6 93 __IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
Anna Bridge 142:4eea097334d6 94 __IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
Anna Bridge 142:4eea097334d6 95 __IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
Anna Bridge 142:4eea097334d6 96 __IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
Anna Bridge 142:4eea097334d6 97 __IM uint32_t ETMCIDR0; /**< Component ID0 Register */
Anna Bridge 142:4eea097334d6 98 __IM uint32_t ETMCIDR1; /**< Component ID1 Register */
Anna Bridge 142:4eea097334d6 99 __IM uint32_t ETMCIDR2; /**< Component ID2 Register */
Anna Bridge 142:4eea097334d6 100 __IM uint32_t ETMCIDR3; /**< Component ID3 Register */
Anna Bridge 142:4eea097334d6 101 } ETM_TypeDef; /** @} */
Anna Bridge 142:4eea097334d6 102
Anna Bridge 142:4eea097334d6 103 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 104 * @defgroup EFR32MG12P_ETM_BitFields
Anna Bridge 142:4eea097334d6 105 * @{
Anna Bridge 142:4eea097334d6 106 *****************************************************************************/
Anna Bridge 142:4eea097334d6 107
Anna Bridge 142:4eea097334d6 108 /* Bit fields for ETM ETMCR */
Anna Bridge 142:4eea097334d6 109 #define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 110 #define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 111 #define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
Anna Bridge 142:4eea097334d6 112 #define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
Anna Bridge 142:4eea097334d6 113 #define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
Anna Bridge 142:4eea097334d6 114 #define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 115 #define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 116 #define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
Anna Bridge 142:4eea097334d6 117 #define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
Anna Bridge 142:4eea097334d6 118 #define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 119 #define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 120 #define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
Anna Bridge 142:4eea097334d6 121 #define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
Anna Bridge 142:4eea097334d6 122 #define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
Anna Bridge 142:4eea097334d6 123 #define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 124 #define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 125 #define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
Anna Bridge 142:4eea097334d6 126 #define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
Anna Bridge 142:4eea097334d6 127 #define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
Anna Bridge 142:4eea097334d6 128 #define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 129 #define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 130 #define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
Anna Bridge 142:4eea097334d6 131 #define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
Anna Bridge 142:4eea097334d6 132 #define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
Anna Bridge 142:4eea097334d6 133 #define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 134 #define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 135 #define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
Anna Bridge 142:4eea097334d6 136 #define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
Anna Bridge 142:4eea097334d6 137 #define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
Anna Bridge 142:4eea097334d6 138 #define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 139 #define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 140 #define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
Anna Bridge 142:4eea097334d6 141 #define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
Anna Bridge 142:4eea097334d6 142 #define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
Anna Bridge 142:4eea097334d6 143 #define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 144 #define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 145 #define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 146 #define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 147 #define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 148 #define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 149 #define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
Anna Bridge 142:4eea097334d6 150 #define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
Anna Bridge 142:4eea097334d6 151 #define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
Anna Bridge 142:4eea097334d6 152 #define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 153 #define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 154 #define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
Anna Bridge 142:4eea097334d6 155 #define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
Anna Bridge 142:4eea097334d6 156 #define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 157 #define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 158 #define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
Anna Bridge 142:4eea097334d6 159 #define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
Anna Bridge 142:4eea097334d6 160 #define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 161 #define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 162 #define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
Anna Bridge 142:4eea097334d6 163 #define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
Anna Bridge 142:4eea097334d6 164 #define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
Anna Bridge 142:4eea097334d6 165 #define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 166 #define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
Anna Bridge 142:4eea097334d6 167
Anna Bridge 142:4eea097334d6 168 /* Bit fields for ETM ETMCCR */
Anna Bridge 142:4eea097334d6 169 #define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 170 #define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 171 #define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
Anna Bridge 142:4eea097334d6 172 #define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
Anna Bridge 142:4eea097334d6 173 #define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 174 #define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 175 #define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
Anna Bridge 142:4eea097334d6 176 #define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
Anna Bridge 142:4eea097334d6 177 #define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 178 #define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 179 #define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
Anna Bridge 142:4eea097334d6 180 #define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
Anna Bridge 142:4eea097334d6 181 #define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 182 #define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 183 #define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
Anna Bridge 142:4eea097334d6 184 #define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
Anna Bridge 142:4eea097334d6 185 #define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 186 #define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 187 #define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
Anna Bridge 142:4eea097334d6 188 #define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
Anna Bridge 142:4eea097334d6 189 #define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
Anna Bridge 142:4eea097334d6 190 #define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 191 #define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 192 #define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
Anna Bridge 142:4eea097334d6 193 #define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
Anna Bridge 142:4eea097334d6 194 #define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 195 #define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 196 #define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 197 #define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 198 #define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 199 #define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 200 #define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 201 #define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 202 #define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
Anna Bridge 142:4eea097334d6 203 #define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
Anna Bridge 142:4eea097334d6 204 #define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 205 #define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 206 #define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
Anna Bridge 142:4eea097334d6 207 #define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
Anna Bridge 142:4eea097334d6 208 #define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
Anna Bridge 142:4eea097334d6 209 #define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 210 #define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 211 #define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
Anna Bridge 142:4eea097334d6 212 #define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
Anna Bridge 142:4eea097334d6 213 #define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 214 #define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 215 #define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
Anna Bridge 142:4eea097334d6 216 #define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
Anna Bridge 142:4eea097334d6 217 #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
Anna Bridge 142:4eea097334d6 218 #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 219 #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 220 #define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
Anna Bridge 142:4eea097334d6 221 #define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
Anna Bridge 142:4eea097334d6 222 #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
Anna Bridge 142:4eea097334d6 223 #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 224 #define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 225 #define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
Anna Bridge 142:4eea097334d6 226 #define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
Anna Bridge 142:4eea097334d6 227 #define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
Anna Bridge 142:4eea097334d6 228 #define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 229 #define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
Anna Bridge 142:4eea097334d6 230
Anna Bridge 142:4eea097334d6 231 /* Bit fields for ETM ETMTRIGGER */
Anna Bridge 142:4eea097334d6 232 #define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 233 #define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 234 #define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
Anna Bridge 142:4eea097334d6 235 #define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
Anna Bridge 142:4eea097334d6 236 #define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 237 #define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 238 #define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
Anna Bridge 142:4eea097334d6 239 #define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
Anna Bridge 142:4eea097334d6 240 #define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 241 #define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 242 #define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
Anna Bridge 142:4eea097334d6 243 #define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
Anna Bridge 142:4eea097334d6 244 #define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 245 #define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
Anna Bridge 142:4eea097334d6 246
Anna Bridge 142:4eea097334d6 247 /* Bit fields for ETM ETMSR */
Anna Bridge 142:4eea097334d6 248 #define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 249 #define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 250 #define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
Anna Bridge 142:4eea097334d6 251 #define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
Anna Bridge 142:4eea097334d6 252 #define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
Anna Bridge 142:4eea097334d6 253 #define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 254 #define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 255 #define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
Anna Bridge 142:4eea097334d6 256 #define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
Anna Bridge 142:4eea097334d6 257 #define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
Anna Bridge 142:4eea097334d6 258 #define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 259 #define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 260 #define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
Anna Bridge 142:4eea097334d6 261 #define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
Anna Bridge 142:4eea097334d6 262 #define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
Anna Bridge 142:4eea097334d6 263 #define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 264 #define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 265 #define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
Anna Bridge 142:4eea097334d6 266 #define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
Anna Bridge 142:4eea097334d6 267 #define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
Anna Bridge 142:4eea097334d6 268 #define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 269 #define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
Anna Bridge 142:4eea097334d6 270
Anna Bridge 142:4eea097334d6 271 /* Bit fields for ETM ETMSCR */
Anna Bridge 142:4eea097334d6 272 #define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 273 #define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 274 #define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
Anna Bridge 142:4eea097334d6 275 #define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
Anna Bridge 142:4eea097334d6 276 #define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 277 #define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 278 #define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
Anna Bridge 142:4eea097334d6 279 #define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
Anna Bridge 142:4eea097334d6 280 #define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
Anna Bridge 142:4eea097334d6 281 #define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 282 #define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 283 #define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
Anna Bridge 142:4eea097334d6 284 #define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
Anna Bridge 142:4eea097334d6 285 #define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
Anna Bridge 142:4eea097334d6 286 #define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 287 #define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 288 #define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
Anna Bridge 142:4eea097334d6 289 #define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
Anna Bridge 142:4eea097334d6 290 #define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
Anna Bridge 142:4eea097334d6 291 #define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 292 #define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 293 #define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
Anna Bridge 142:4eea097334d6 294 #define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
Anna Bridge 142:4eea097334d6 295 #define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
Anna Bridge 142:4eea097334d6 296 #define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 297 #define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 298 #define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
Anna Bridge 142:4eea097334d6 299 #define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
Anna Bridge 142:4eea097334d6 300 #define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 301 #define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 302 #define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
Anna Bridge 142:4eea097334d6 303 #define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
Anna Bridge 142:4eea097334d6 304 #define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
Anna Bridge 142:4eea097334d6 305 #define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 306 #define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
Anna Bridge 142:4eea097334d6 307
Anna Bridge 142:4eea097334d6 308 /* Bit fields for ETM ETMTEEVR */
Anna Bridge 142:4eea097334d6 309 #define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 310 #define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 311 #define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
Anna Bridge 142:4eea097334d6 312 #define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
Anna Bridge 142:4eea097334d6 313 #define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 314 #define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 315 #define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
Anna Bridge 142:4eea097334d6 316 #define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
Anna Bridge 142:4eea097334d6 317 #define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 318 #define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 319 #define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
Anna Bridge 142:4eea097334d6 320 #define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
Anna Bridge 142:4eea097334d6 321 #define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 322 #define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
Anna Bridge 142:4eea097334d6 323
Anna Bridge 142:4eea097334d6 324 /* Bit fields for ETM ETMTECR1 */
Anna Bridge 142:4eea097334d6 325 #define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 326 #define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 327 #define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
Anna Bridge 142:4eea097334d6 328 #define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
Anna Bridge 142:4eea097334d6 329 #define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 330 #define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 331 #define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
Anna Bridge 142:4eea097334d6 332 #define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
Anna Bridge 142:4eea097334d6 333 #define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 334 #define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 335 #define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
Anna Bridge 142:4eea097334d6 336 #define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
Anna Bridge 142:4eea097334d6 337 #define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
Anna Bridge 142:4eea097334d6 338 #define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 339 #define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 340 #define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 341 #define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 342 #define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 343 #define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 344 #define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
Anna Bridge 142:4eea097334d6 345 #define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
Anna Bridge 142:4eea097334d6 346 #define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
Anna Bridge 142:4eea097334d6 347 #define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 348 #define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 349 #define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 350 #define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 351 #define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 352 #define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
Anna Bridge 142:4eea097334d6 353
Anna Bridge 142:4eea097334d6 354 /* Bit fields for ETM ETMFFLR */
Anna Bridge 142:4eea097334d6 355 #define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
Anna Bridge 142:4eea097334d6 356 #define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
Anna Bridge 142:4eea097334d6 357 #define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
Anna Bridge 142:4eea097334d6 358 #define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
Anna Bridge 142:4eea097334d6 359 #define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
Anna Bridge 142:4eea097334d6 360 #define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
Anna Bridge 142:4eea097334d6 361
Anna Bridge 142:4eea097334d6 362 /* Bit fields for ETM ETMCNTRLDVR1 */
Anna Bridge 142:4eea097334d6 363 #define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
Anna Bridge 142:4eea097334d6 364 #define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
Anna Bridge 142:4eea097334d6 365 #define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
Anna Bridge 142:4eea097334d6 366 #define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
Anna Bridge 142:4eea097334d6 367 #define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
Anna Bridge 142:4eea097334d6 368 #define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
Anna Bridge 142:4eea097334d6 369
Anna Bridge 142:4eea097334d6 370 /* Bit fields for ETM ETMSYNCFR */
Anna Bridge 142:4eea097334d6 371 #define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
Anna Bridge 142:4eea097334d6 372 #define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
Anna Bridge 142:4eea097334d6 373 #define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
Anna Bridge 142:4eea097334d6 374 #define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
Anna Bridge 142:4eea097334d6 375 #define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
Anna Bridge 142:4eea097334d6 376 #define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
Anna Bridge 142:4eea097334d6 377
Anna Bridge 142:4eea097334d6 378 /* Bit fields for ETM ETMIDR */
Anna Bridge 142:4eea097334d6 379 #define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 380 #define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 381 #define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
Anna Bridge 142:4eea097334d6 382 #define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
Anna Bridge 142:4eea097334d6 383 #define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 384 #define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 385 #define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
Anna Bridge 142:4eea097334d6 386 #define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
Anna Bridge 142:4eea097334d6 387 #define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 388 #define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 389 #define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
Anna Bridge 142:4eea097334d6 390 #define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
Anna Bridge 142:4eea097334d6 391 #define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 392 #define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 393 #define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
Anna Bridge 142:4eea097334d6 394 #define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
Anna Bridge 142:4eea097334d6 395 #define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 396 #define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 397 #define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
Anna Bridge 142:4eea097334d6 398 #define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
Anna Bridge 142:4eea097334d6 399 #define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
Anna Bridge 142:4eea097334d6 400 #define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 401 #define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 402 #define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
Anna Bridge 142:4eea097334d6 403 #define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
Anna Bridge 142:4eea097334d6 404 #define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
Anna Bridge 142:4eea097334d6 405 #define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 406 #define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 407 #define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
Anna Bridge 142:4eea097334d6 408 #define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
Anna Bridge 142:4eea097334d6 409 #define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
Anna Bridge 142:4eea097334d6 410 #define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 411 #define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 412 #define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
Anna Bridge 142:4eea097334d6 413 #define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
Anna Bridge 142:4eea097334d6 414 #define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
Anna Bridge 142:4eea097334d6 415 #define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 416 #define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 417 #define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
Anna Bridge 142:4eea097334d6 418 #define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
Anna Bridge 142:4eea097334d6 419 #define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 420 #define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
Anna Bridge 142:4eea097334d6 421
Anna Bridge 142:4eea097334d6 422 /* Bit fields for ETM ETMCCER */
Anna Bridge 142:4eea097334d6 423 #define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 424 #define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 425 #define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
Anna Bridge 142:4eea097334d6 426 #define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
Anna Bridge 142:4eea097334d6 427 #define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 428 #define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 429 #define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
Anna Bridge 142:4eea097334d6 430 #define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
Anna Bridge 142:4eea097334d6 431 #define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 432 #define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 433 #define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
Anna Bridge 142:4eea097334d6 434 #define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
Anna Bridge 142:4eea097334d6 435 #define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
Anna Bridge 142:4eea097334d6 436 #define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 437 #define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 438 #define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
Anna Bridge 142:4eea097334d6 439 #define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
Anna Bridge 142:4eea097334d6 440 #define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
Anna Bridge 142:4eea097334d6 441 #define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 442 #define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 443 #define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
Anna Bridge 142:4eea097334d6 444 #define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
Anna Bridge 142:4eea097334d6 445 #define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 446 #define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 447 #define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
Anna Bridge 142:4eea097334d6 448 #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
Anna Bridge 142:4eea097334d6 449 #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 450 #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 451 #define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
Anna Bridge 142:4eea097334d6 452 #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
Anna Bridge 142:4eea097334d6 453 #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
Anna Bridge 142:4eea097334d6 454 #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 455 #define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 456 #define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
Anna Bridge 142:4eea097334d6 457 #define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
Anna Bridge 142:4eea097334d6 458 #define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
Anna Bridge 142:4eea097334d6 459 #define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 460 #define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 461 #define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
Anna Bridge 142:4eea097334d6 462 #define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
Anna Bridge 142:4eea097334d6 463 #define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
Anna Bridge 142:4eea097334d6 464 #define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 465 #define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 466 #define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
Anna Bridge 142:4eea097334d6 467 #define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
Anna Bridge 142:4eea097334d6 468 #define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
Anna Bridge 142:4eea097334d6 469 #define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 470 #define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 471 #define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
Anna Bridge 142:4eea097334d6 472 #define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
Anna Bridge 142:4eea097334d6 473 #define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
Anna Bridge 142:4eea097334d6 474 #define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 475 #define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 476 #define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
Anna Bridge 142:4eea097334d6 477 #define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
Anna Bridge 142:4eea097334d6 478 #define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
Anna Bridge 142:4eea097334d6 479 #define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 480 #define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
Anna Bridge 142:4eea097334d6 481
Anna Bridge 142:4eea097334d6 482 /* Bit fields for ETM ETMTESSEICR */
Anna Bridge 142:4eea097334d6 483 #define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
Anna Bridge 142:4eea097334d6 484 #define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
Anna Bridge 142:4eea097334d6 485 #define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
Anna Bridge 142:4eea097334d6 486 #define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
Anna Bridge 142:4eea097334d6 487 #define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
Anna Bridge 142:4eea097334d6 488 #define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
Anna Bridge 142:4eea097334d6 489 #define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
Anna Bridge 142:4eea097334d6 490 #define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
Anna Bridge 142:4eea097334d6 491 #define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
Anna Bridge 142:4eea097334d6 492 #define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
Anna Bridge 142:4eea097334d6 493
Anna Bridge 142:4eea097334d6 494 /* Bit fields for ETM ETMTSEVR */
Anna Bridge 142:4eea097334d6 495 #define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 496 #define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 497 #define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
Anna Bridge 142:4eea097334d6 498 #define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
Anna Bridge 142:4eea097334d6 499 #define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 500 #define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 501 #define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
Anna Bridge 142:4eea097334d6 502 #define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
Anna Bridge 142:4eea097334d6 503 #define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 504 #define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 505 #define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
Anna Bridge 142:4eea097334d6 506 #define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
Anna Bridge 142:4eea097334d6 507 #define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 508 #define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
Anna Bridge 142:4eea097334d6 509
Anna Bridge 142:4eea097334d6 510 /* Bit fields for ETM ETMTRACEIDR */
Anna Bridge 142:4eea097334d6 511 #define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
Anna Bridge 142:4eea097334d6 512 #define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
Anna Bridge 142:4eea097334d6 513 #define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
Anna Bridge 142:4eea097334d6 514 #define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
Anna Bridge 142:4eea097334d6 515 #define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
Anna Bridge 142:4eea097334d6 516 #define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
Anna Bridge 142:4eea097334d6 517
Anna Bridge 142:4eea097334d6 518 /* Bit fields for ETM ETMIDR2 */
Anna Bridge 142:4eea097334d6 519 #define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 520 #define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 521 #define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
Anna Bridge 142:4eea097334d6 522 #define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
Anna Bridge 142:4eea097334d6 523 #define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
Anna Bridge 142:4eea097334d6 524 #define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 525 #define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 526 #define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 527 #define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 528 #define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 529 #define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 530 #define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
Anna Bridge 142:4eea097334d6 531 #define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
Anna Bridge 142:4eea097334d6 532 #define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
Anna Bridge 142:4eea097334d6 533 #define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 534 #define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 535 #define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 536 #define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 537 #define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 538 #define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
Anna Bridge 142:4eea097334d6 539
Anna Bridge 142:4eea097334d6 540 /* Bit fields for ETM ETMPDSR */
Anna Bridge 142:4eea097334d6 541 #define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
Anna Bridge 142:4eea097334d6 542 #define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
Anna Bridge 142:4eea097334d6 543 #define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
Anna Bridge 142:4eea097334d6 544 #define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
Anna Bridge 142:4eea097334d6 545 #define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
Anna Bridge 142:4eea097334d6 546 #define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
Anna Bridge 142:4eea097334d6 547 #define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
Anna Bridge 142:4eea097334d6 548
Anna Bridge 142:4eea097334d6 549 /* Bit fields for ETM ETMISCIN */
Anna Bridge 142:4eea097334d6 550 #define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
Anna Bridge 142:4eea097334d6 551 #define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
Anna Bridge 142:4eea097334d6 552 #define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
Anna Bridge 142:4eea097334d6 553 #define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
Anna Bridge 142:4eea097334d6 554 #define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
Anna Bridge 142:4eea097334d6 555 #define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
Anna Bridge 142:4eea097334d6 556 #define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
Anna Bridge 142:4eea097334d6 557 #define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
Anna Bridge 142:4eea097334d6 558 #define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
Anna Bridge 142:4eea097334d6 559 #define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
Anna Bridge 142:4eea097334d6 560 #define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
Anna Bridge 142:4eea097334d6 561
Anna Bridge 142:4eea097334d6 562 /* Bit fields for ETM ITTRIGOUT */
Anna Bridge 142:4eea097334d6 563 #define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
Anna Bridge 142:4eea097334d6 564 #define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
Anna Bridge 142:4eea097334d6 565 #define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
Anna Bridge 142:4eea097334d6 566 #define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
Anna Bridge 142:4eea097334d6 567 #define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
Anna Bridge 142:4eea097334d6 568 #define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
Anna Bridge 142:4eea097334d6 569 #define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
Anna Bridge 142:4eea097334d6 570
Anna Bridge 142:4eea097334d6 571 /* Bit fields for ETM ETMITATBCTR2 */
Anna Bridge 142:4eea097334d6 572 #define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
Anna Bridge 142:4eea097334d6 573 #define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
Anna Bridge 142:4eea097334d6 574 #define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
Anna Bridge 142:4eea097334d6 575 #define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
Anna Bridge 142:4eea097334d6 576 #define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
Anna Bridge 142:4eea097334d6 577 #define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
Anna Bridge 142:4eea097334d6 578 #define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
Anna Bridge 142:4eea097334d6 579
Anna Bridge 142:4eea097334d6 580 /* Bit fields for ETM ETMITATBCTR0 */
Anna Bridge 142:4eea097334d6 581 #define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
Anna Bridge 142:4eea097334d6 582 #define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
Anna Bridge 142:4eea097334d6 583 #define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
Anna Bridge 142:4eea097334d6 584 #define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
Anna Bridge 142:4eea097334d6 585 #define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
Anna Bridge 142:4eea097334d6 586 #define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
Anna Bridge 142:4eea097334d6 587 #define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
Anna Bridge 142:4eea097334d6 588
Anna Bridge 142:4eea097334d6 589 /* Bit fields for ETM ETMITCTRL */
Anna Bridge 142:4eea097334d6 590 #define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
Anna Bridge 142:4eea097334d6 591 #define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
Anna Bridge 142:4eea097334d6 592 #define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
Anna Bridge 142:4eea097334d6 593 #define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
Anna Bridge 142:4eea097334d6 594 #define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
Anna Bridge 142:4eea097334d6 595 #define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
Anna Bridge 142:4eea097334d6 596 #define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
Anna Bridge 142:4eea097334d6 597
Anna Bridge 142:4eea097334d6 598 /* Bit fields for ETM ETMCLAIMSET */
Anna Bridge 142:4eea097334d6 599 #define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
Anna Bridge 142:4eea097334d6 600 #define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
Anna Bridge 142:4eea097334d6 601 #define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
Anna Bridge 142:4eea097334d6 602 #define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
Anna Bridge 142:4eea097334d6 603 #define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
Anna Bridge 142:4eea097334d6 604 #define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
Anna Bridge 142:4eea097334d6 605
Anna Bridge 142:4eea097334d6 606 /* Bit fields for ETM ETMCLAIMCLR */
Anna Bridge 142:4eea097334d6 607 #define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
Anna Bridge 142:4eea097334d6 608 #define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
Anna Bridge 142:4eea097334d6 609 #define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
Anna Bridge 142:4eea097334d6 610 #define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
Anna Bridge 142:4eea097334d6 611 #define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
Anna Bridge 142:4eea097334d6 612 #define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
Anna Bridge 142:4eea097334d6 613 #define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
Anna Bridge 142:4eea097334d6 614
Anna Bridge 142:4eea097334d6 615 /* Bit fields for ETM ETMLAR */
Anna Bridge 142:4eea097334d6 616 #define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
Anna Bridge 142:4eea097334d6 617 #define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
Anna Bridge 142:4eea097334d6 618 #define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
Anna Bridge 142:4eea097334d6 619 #define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
Anna Bridge 142:4eea097334d6 620 #define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
Anna Bridge 142:4eea097334d6 621 #define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
Anna Bridge 142:4eea097334d6 622 #define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
Anna Bridge 142:4eea097334d6 623
Anna Bridge 142:4eea097334d6 624 /* Bit fields for ETM ETMLSR */
Anna Bridge 142:4eea097334d6 625 #define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
Anna Bridge 142:4eea097334d6 626 #define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
Anna Bridge 142:4eea097334d6 627 #define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
Anna Bridge 142:4eea097334d6 628 #define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
Anna Bridge 142:4eea097334d6 629 #define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
Anna Bridge 142:4eea097334d6 630 #define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
Anna Bridge 142:4eea097334d6 631 #define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
Anna Bridge 142:4eea097334d6 632 #define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
Anna Bridge 142:4eea097334d6 633 #define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
Anna Bridge 142:4eea097334d6 634 #define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
Anna Bridge 142:4eea097334d6 635 #define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
Anna Bridge 142:4eea097334d6 636 #define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
Anna Bridge 142:4eea097334d6 637
Anna Bridge 142:4eea097334d6 638 /* Bit fields for ETM ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 639 #define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 640 #define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 641 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
Anna Bridge 142:4eea097334d6 642 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
Anna Bridge 142:4eea097334d6 643 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 644 #define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 645 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
Anna Bridge 142:4eea097334d6 646 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
Anna Bridge 142:4eea097334d6 647 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 648 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 649 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 650 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 651 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 652 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 653 #define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
Anna Bridge 142:4eea097334d6 654 #define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
Anna Bridge 142:4eea097334d6 655 #define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 656 #define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 657 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
Anna Bridge 142:4eea097334d6 658 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
Anna Bridge 142:4eea097334d6 659 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 660 #define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
Anna Bridge 142:4eea097334d6 661
Anna Bridge 142:4eea097334d6 662 /* Bit fields for ETM ETMDEVTYPE */
Anna Bridge 142:4eea097334d6 663 #define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
Anna Bridge 142:4eea097334d6 664 #define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
Anna Bridge 142:4eea097334d6 665 #define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
Anna Bridge 142:4eea097334d6 666 #define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
Anna Bridge 142:4eea097334d6 667 #define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
Anna Bridge 142:4eea097334d6 668 #define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
Anna Bridge 142:4eea097334d6 669 #define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
Anna Bridge 142:4eea097334d6 670 #define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
Anna Bridge 142:4eea097334d6 671 #define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
Anna Bridge 142:4eea097334d6 672 #define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
Anna Bridge 142:4eea097334d6 673
Anna Bridge 142:4eea097334d6 674 /* Bit fields for ETM ETMPIDR4 */
Anna Bridge 142:4eea097334d6 675 #define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
Anna Bridge 142:4eea097334d6 676 #define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
Anna Bridge 142:4eea097334d6 677 #define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
Anna Bridge 142:4eea097334d6 678 #define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
Anna Bridge 142:4eea097334d6 679 #define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
Anna Bridge 142:4eea097334d6 680 #define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
Anna Bridge 142:4eea097334d6 681 #define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
Anna Bridge 142:4eea097334d6 682 #define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
Anna Bridge 142:4eea097334d6 683 #define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
Anna Bridge 142:4eea097334d6 684 #define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
Anna Bridge 142:4eea097334d6 685
Anna Bridge 142:4eea097334d6 686 /* Bit fields for ETM ETMPIDR5 */
Anna Bridge 142:4eea097334d6 687 #define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
Anna Bridge 142:4eea097334d6 688 #define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
Anna Bridge 142:4eea097334d6 689
Anna Bridge 142:4eea097334d6 690 /* Bit fields for ETM ETMPIDR6 */
Anna Bridge 142:4eea097334d6 691 #define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
Anna Bridge 142:4eea097334d6 692 #define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
Anna Bridge 142:4eea097334d6 693
Anna Bridge 142:4eea097334d6 694 /* Bit fields for ETM ETMPIDR7 */
Anna Bridge 142:4eea097334d6 695 #define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
Anna Bridge 142:4eea097334d6 696 #define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
Anna Bridge 142:4eea097334d6 697
Anna Bridge 142:4eea097334d6 698 /* Bit fields for ETM ETMPIDR0 */
Anna Bridge 142:4eea097334d6 699 #define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */
Anna Bridge 142:4eea097334d6 700 #define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
Anna Bridge 142:4eea097334d6 701 #define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
Anna Bridge 142:4eea097334d6 702 #define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
Anna Bridge 142:4eea097334d6 703 #define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
Anna Bridge 142:4eea097334d6 704 #define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
Anna Bridge 142:4eea097334d6 705
Anna Bridge 142:4eea097334d6 706 /* Bit fields for ETM ETMPIDR1 */
Anna Bridge 142:4eea097334d6 707 #define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
Anna Bridge 142:4eea097334d6 708 #define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
Anna Bridge 142:4eea097334d6 709 #define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
Anna Bridge 142:4eea097334d6 710 #define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
Anna Bridge 142:4eea097334d6 711 #define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
Anna Bridge 142:4eea097334d6 712 #define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
Anna Bridge 142:4eea097334d6 713 #define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
Anna Bridge 142:4eea097334d6 714 #define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
Anna Bridge 142:4eea097334d6 715 #define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
Anna Bridge 142:4eea097334d6 716 #define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
Anna Bridge 142:4eea097334d6 717
Anna Bridge 142:4eea097334d6 718 /* Bit fields for ETM ETMPIDR2 */
Anna Bridge 142:4eea097334d6 719 #define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 720 #define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 721 #define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
Anna Bridge 142:4eea097334d6 722 #define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
Anna Bridge 142:4eea097334d6 723 #define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 724 #define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 725 #define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
Anna Bridge 142:4eea097334d6 726 #define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
Anna Bridge 142:4eea097334d6 727 #define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
Anna Bridge 142:4eea097334d6 728 #define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 729 #define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 730 #define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
Anna Bridge 142:4eea097334d6 731 #define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
Anna Bridge 142:4eea097334d6 732 #define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 733 #define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
Anna Bridge 142:4eea097334d6 734
Anna Bridge 142:4eea097334d6 735 /* Bit fields for ETM ETMPIDR3 */
Anna Bridge 142:4eea097334d6 736 #define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
Anna Bridge 142:4eea097334d6 737 #define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
Anna Bridge 142:4eea097334d6 738 #define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
Anna Bridge 142:4eea097334d6 739 #define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
Anna Bridge 142:4eea097334d6 740 #define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
Anna Bridge 142:4eea097334d6 741 #define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
Anna Bridge 142:4eea097334d6 742 #define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
Anna Bridge 142:4eea097334d6 743 #define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
Anna Bridge 142:4eea097334d6 744 #define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
Anna Bridge 142:4eea097334d6 745 #define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
Anna Bridge 142:4eea097334d6 746
Anna Bridge 142:4eea097334d6 747 /* Bit fields for ETM ETMCIDR0 */
Anna Bridge 142:4eea097334d6 748 #define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
Anna Bridge 142:4eea097334d6 749 #define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
Anna Bridge 142:4eea097334d6 750 #define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 751 #define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 752 #define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
Anna Bridge 142:4eea097334d6 753 #define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
Anna Bridge 142:4eea097334d6 754
Anna Bridge 142:4eea097334d6 755 /* Bit fields for ETM ETMCIDR1 */
Anna Bridge 142:4eea097334d6 756 #define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
Anna Bridge 142:4eea097334d6 757 #define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
Anna Bridge 142:4eea097334d6 758 #define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 759 #define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 760 #define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
Anna Bridge 142:4eea097334d6 761 #define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
Anna Bridge 142:4eea097334d6 762
Anna Bridge 142:4eea097334d6 763 /* Bit fields for ETM ETMCIDR2 */
Anna Bridge 142:4eea097334d6 764 #define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
Anna Bridge 142:4eea097334d6 765 #define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
Anna Bridge 142:4eea097334d6 766 #define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 767 #define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 768 #define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
Anna Bridge 142:4eea097334d6 769 #define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
Anna Bridge 142:4eea097334d6 770
Anna Bridge 142:4eea097334d6 771 /* Bit fields for ETM ETMCIDR3 */
Anna Bridge 142:4eea097334d6 772 #define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
Anna Bridge 142:4eea097334d6 773 #define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
Anna Bridge 142:4eea097334d6 774 #define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 775 #define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
Anna Bridge 142:4eea097334d6 776 #define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
Anna Bridge 142:4eea097334d6 777 #define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
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Anna Bridge 142:4eea097334d6 779 /** @} End of group EFR32MG12P_ETM */
Anna Bridge 142:4eea097334d6 780 /** @} End of group Parts */
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