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TARGET_STEVAL_3DP001V1/TOOLCHAIN_IAR/stm32f4xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32f4xx_ll_system.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @brief Header file of SYSTEM LL module.
AnnaBridge	145:64910690c574	6	@verbatim
AnnaBridge	145:64910690c574	7	==============================================================================
AnnaBridge	145:64910690c574	8	##### How to use this driver #####
AnnaBridge	145:64910690c574	9	==============================================================================
AnnaBridge	145:64910690c574	10	[..]
AnnaBridge	145:64910690c574	11	The LL SYSTEM driver contains a set of generic APIs that can be
AnnaBridge	145:64910690c574	12	used by user:
AnnaBridge	145:64910690c574	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
AnnaBridge	145:64910690c574	14	(+) Access to DBGCMU registers
AnnaBridge	145:64910690c574	15	(+) Access to SYSCFG registers
AnnaBridge	145:64910690c574	16
AnnaBridge	145:64910690c574	17	@endverbatim
AnnaBridge	145:64910690c574	18	******************************************************************************
AnnaBridge	145:64910690c574	19	* @attention
AnnaBridge	145:64910690c574	20	*
AnnaBridge	145:64910690c574	21	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	22	*
AnnaBridge	145:64910690c574	23	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	24	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	25	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	26	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	27	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	28	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	29	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	30	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	31	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	32	* without specific prior written permission.
AnnaBridge	145:64910690c574	33	*
AnnaBridge	145:64910690c574	34	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	35	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	36	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	37	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	38	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	39	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	40	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	41	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	42	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	43	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	44	*
AnnaBridge	145:64910690c574	45	******************************************************************************
AnnaBridge	145:64910690c574	46	*/
AnnaBridge	145:64910690c574	47
AnnaBridge	145:64910690c574	48	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	49	#ifndef __STM32F4xx_LL_SYSTEM_H
AnnaBridge	145:64910690c574	50	#define __STM32F4xx_LL_SYSTEM_H
AnnaBridge	145:64910690c574	51
AnnaBridge	145:64910690c574	52	#ifdef __cplusplus
AnnaBridge	145:64910690c574	53	extern "C" {
AnnaBridge	145:64910690c574	54	#endif
AnnaBridge	145:64910690c574	55
AnnaBridge	145:64910690c574	56	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	57	#include "stm32f4xx.h"
AnnaBridge	145:64910690c574	58
AnnaBridge	145:64910690c574	59	/** @addtogroup STM32F4xx_LL_Driver
AnnaBridge	145:64910690c574	60	* @{
AnnaBridge	145:64910690c574	61	*/
AnnaBridge	145:64910690c574	62
AnnaBridge	145:64910690c574	63	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
AnnaBridge	145:64910690c574	64
AnnaBridge	145:64910690c574	65	/** @defgroup SYSTEM_LL SYSTEM
AnnaBridge	145:64910690c574	66	* @{
AnnaBridge	145:64910690c574	67	*/
AnnaBridge	145:64910690c574	68
AnnaBridge	145:64910690c574	69	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	70	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	71
AnnaBridge	145:64910690c574	72	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	73	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
AnnaBridge	145:64910690c574	74	* @{
AnnaBridge	145:64910690c574	75	*/
AnnaBridge	145:64910690c574	76
AnnaBridge	145:64910690c574	77	/**
AnnaBridge	145:64910690c574	78	* @}
AnnaBridge	145:64910690c574	79	*/
AnnaBridge	145:64910690c574	80
AnnaBridge	145:64910690c574	81	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	82
AnnaBridge	145:64910690c574	83	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	84	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	85	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
AnnaBridge	145:64910690c574	86	* @{
AnnaBridge	145:64910690c574	87	*/
AnnaBridge	145:64910690c574	88
AnnaBridge	145:64910690c574	89	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
AnnaBridge	145:64910690c574	90	* @{
AnnaBridge	145:64910690c574	91	*/
AnnaBridge	145:64910690c574	92	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /!< Main Flash memory mapped at 0x00000000 /
AnnaBridge	145:64910690c574	93	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
AnnaBridge	145:64910690c574	94	#if defined(FSMC_Bank1)
AnnaBridge	163:e59c8e839560	95	#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
AnnaBridge	145:64910690c574	96	#endif /* FSMC_Bank1 */
AnnaBridge	145:64910690c574	97	#if defined(FMC_Bank1)
AnnaBridge	163:e59c8e839560	98	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 /
AnnaBridge	163:e59c8e839560	99	#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /!< FMC/SDRAM mapped at 0x00000000 /
AnnaBridge	145:64910690c574	100	#endif /* FMC_Bank1 */
AnnaBridge	145:64910690c574	101	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< SRAM1 mapped at 0x00000000 /
AnnaBridge	163:e59c8e839560	102
AnnaBridge	145:64910690c574	103	/**
AnnaBridge	145:64910690c574	104	* @}
AnnaBridge	145:64910690c574	105	*/
AnnaBridge	145:64910690c574	106
AnnaBridge	145:64910690c574	107	#if defined(SYSCFG_PMC_MII_RMII_SEL)
AnnaBridge	145:64910690c574	108	/** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
AnnaBridge	145:64910690c574	109	* @{
AnnaBridge	145:64910690c574	110	*/
AnnaBridge	145:64910690c574	111	#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /!< ETH Media MII interface /
AnnaBridge	145:64910690c574	112	#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /!< ETH Media RMII interface /
AnnaBridge	145:64910690c574	113
AnnaBridge	145:64910690c574	114	/**
AnnaBridge	145:64910690c574	115	* @}
AnnaBridge	145:64910690c574	116	*/
AnnaBridge	145:64910690c574	117	#endif /* SYSCFG_PMC_MII_RMII_SEL */
AnnaBridge	145:64910690c574	118
AnnaBridge	145:64910690c574	119
AnnaBridge	145:64910690c574	120
AnnaBridge	145:64910690c574	121	#if defined(SYSCFG_MEMRMP_UFB_MODE)
AnnaBridge	145:64910690c574	122	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
AnnaBridge	145:64910690c574	123	* @{
AnnaBridge	145:64910690c574	124	*/
AnnaBridge	145:64910690c574	125	#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
AnnaBridge	145:64910690c574	126	and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
AnnaBridge	145:64910690c574	127	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
AnnaBridge	145:64910690c574	128	and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
AnnaBridge	145:64910690c574	129	/**
AnnaBridge	145:64910690c574	130	* @}
AnnaBridge	145:64910690c574	131	*/
AnnaBridge	145:64910690c574	132	#endif /* SYSCFG_MEMRMP_UFB_MODE */
AnnaBridge	145:64910690c574	133	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
AnnaBridge	145:64910690c574	134	* @{
AnnaBridge	145:64910690c574	135	*/
AnnaBridge	145:64910690c574	136	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
AnnaBridge	145:64910690c574	137	#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /!< Enable Fast Mode Plus on FMPI2C_SCL pin /
AnnaBridge	145:64910690c574	138	#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /!< Enable Fast Mode Plus on FMPI2C_SDA pin/
AnnaBridge	145:64910690c574	139	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
AnnaBridge	145:64910690c574	140	/**
AnnaBridge	145:64910690c574	141	* @}
AnnaBridge	145:64910690c574	142	*/
AnnaBridge	145:64910690c574	143
AnnaBridge	145:64910690c574	144	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
AnnaBridge	145:64910690c574	145	* @{
AnnaBridge	145:64910690c574	146	*/
AnnaBridge	145:64910690c574	147	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /!< EXTI PORT A /
AnnaBridge	145:64910690c574	148	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /!< EXTI PORT B /
AnnaBridge	145:64910690c574	149	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /!< EXTI PORT C /
AnnaBridge	145:64910690c574	150	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /!< EXTI PORT D /
AnnaBridge	145:64910690c574	151	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /!< EXTI PORT E /
AnnaBridge	145:64910690c574	152	#if defined(GPIOF)
AnnaBridge	145:64910690c574	153	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /!< EXTI PORT F /
AnnaBridge	145:64910690c574	154	#endif /* GPIOF */
AnnaBridge	145:64910690c574	155	#if defined(GPIOG)
AnnaBridge	145:64910690c574	156	#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /!< EXTI PORT G /
AnnaBridge	145:64910690c574	157	#endif /* GPIOG */
AnnaBridge	145:64910690c574	158	#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /!< EXTI PORT H /
AnnaBridge	145:64910690c574	159	#if defined(GPIOI)
AnnaBridge	145:64910690c574	160	#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /!< EXTI PORT I /
AnnaBridge	145:64910690c574	161	#endif /* GPIOI */
AnnaBridge	145:64910690c574	162	#if defined(GPIOJ)
AnnaBridge	145:64910690c574	163	#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /!< EXTI PORT J /
AnnaBridge	145:64910690c574	164	#endif /* GPIOJ */
AnnaBridge	145:64910690c574	165	#if defined(GPIOK)
AnnaBridge	145:64910690c574	166	#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /!< EXTI PORT k /
AnnaBridge	145:64910690c574	167	#endif /* GPIOK */
AnnaBridge	145:64910690c574	168	/**
AnnaBridge	145:64910690c574	169	* @}
AnnaBridge	145:64910690c574	170	*/
AnnaBridge	145:64910690c574	171
AnnaBridge	145:64910690c574	172	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
AnnaBridge	145:64910690c574	173	* @{
AnnaBridge	145:64910690c574	174	*/
AnnaBridge	145:64910690c574	175	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 \| 0) /!< EXTI_POSITION_0 \| EXTICR[0] /
AnnaBridge	145:64910690c574	176	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 \| 0) /!< EXTI_POSITION_4 \| EXTICR[0] /
AnnaBridge	145:64910690c574	177	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 \| 0) /!< EXTI_POSITION_8 \| EXTICR[0] /
AnnaBridge	145:64910690c574	178	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 \| 0) /!< EXTI_POSITION_12 \| EXTICR[0] /
AnnaBridge	145:64910690c574	179	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 \| 1) /!< EXTI_POSITION_0 \| EXTICR[1] /
AnnaBridge	145:64910690c574	180	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 \| 1) /!< EXTI_POSITION_4 \| EXTICR[1] /
AnnaBridge	145:64910690c574	181	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 \| 1) /!< EXTI_POSITION_8 \| EXTICR[1] /
AnnaBridge	145:64910690c574	182	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 \| 1) /!< EXTI_POSITION_12 \| EXTICR[1] /
AnnaBridge	145:64910690c574	183	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 \| 2) /!< EXTI_POSITION_0 \| EXTICR[2] /
AnnaBridge	145:64910690c574	184	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 \| 2) /!< EXTI_POSITION_4 \| EXTICR[2] /
AnnaBridge	145:64910690c574	185	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 \| 2) /!< EXTI_POSITION_8 \| EXTICR[2] /
AnnaBridge	145:64910690c574	186	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 \| 2) /!< EXTI_POSITION_12 \| EXTICR[2] /
AnnaBridge	145:64910690c574	187	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 \| 3) /!< EXTI_POSITION_0 \| EXTICR[3] /
AnnaBridge	145:64910690c574	188	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 \| 3) /!< EXTI_POSITION_4 \| EXTICR[3] /
AnnaBridge	145:64910690c574	189	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 \| 3) /!< EXTI_POSITION_8 \| EXTICR[3] /
AnnaBridge	145:64910690c574	190	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 \| 3) /!< EXTI_POSITION_12 \| EXTICR[3] /
AnnaBridge	145:64910690c574	191	/**
AnnaBridge	145:64910690c574	192	* @}
AnnaBridge	145:64910690c574	193	*/
AnnaBridge	145:64910690c574	194
AnnaBridge	145:64910690c574	195	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
AnnaBridge	145:64910690c574	196	* @{
AnnaBridge	145:64910690c574	197	*/
AnnaBridge	145:64910690c574	198	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
AnnaBridge	145:64910690c574	199	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
AnnaBridge	145:64910690c574	200	with Break Input of TIM1/8 */
AnnaBridge	145:64910690c574	201	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
AnnaBridge	145:64910690c574	202	and also the PVDE and PLS bits of the Power Control Interface */
AnnaBridge	145:64910690c574	203	#endif /* SYSCFG_CFGR2_CLL */
AnnaBridge	145:64910690c574	204	/**
AnnaBridge	145:64910690c574	205	* @}
AnnaBridge	145:64910690c574	206	*/
AnnaBridge	145:64910690c574	207
AnnaBridge	145:64910690c574	208	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
AnnaBridge	145:64910690c574	209	/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
AnnaBridge	145:64910690c574	210	* @{
AnnaBridge	145:64910690c574	211	*/
AnnaBridge	145:64910690c574	212	#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
AnnaBridge	145:64910690c574	213	#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
AnnaBridge	145:64910690c574	214	/**
AnnaBridge	145:64910690c574	215	* @}
AnnaBridge	145:64910690c574	216	*/
AnnaBridge	145:64910690c574	217	/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
AnnaBridge	145:64910690c574	218	* @{
AnnaBridge	145:64910690c574	219	*/
AnnaBridge	145:64910690c574	220	#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
AnnaBridge	145:64910690c574	221	#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
AnnaBridge	145:64910690c574	222	/**
AnnaBridge	145:64910690c574	223	* @}
AnnaBridge	145:64910690c574	224	*/
AnnaBridge	145:64910690c574	225	/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL
AnnaBridge	145:64910690c574	226	* @{
AnnaBridge	145:64910690c574	227	*/
AnnaBridge	145:64910690c574	228	#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
AnnaBridge	145:64910690c574	229	#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
AnnaBridge	145:64910690c574	230
AnnaBridge	145:64910690c574	231	#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| 0x00000000)
AnnaBridge	145:64910690c574	232	#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D0SEL)
AnnaBridge	145:64910690c574	233	#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| 0x00000000)
AnnaBridge	145:64910690c574	234	#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D0SEL)
AnnaBridge	145:64910690c574	235	/**
AnnaBridge	145:64910690c574	236	* @}
AnnaBridge	145:64910690c574	237	*/
AnnaBridge	145:64910690c574	238	/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
AnnaBridge	145:64910690c574	239	* @{
AnnaBridge	145:64910690c574	240	*/
AnnaBridge	145:64910690c574	241	#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
AnnaBridge	145:64910690c574	242	#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
AnnaBridge	145:64910690c574	243
AnnaBridge	145:64910690c574	244	#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| 0x00000000)
AnnaBridge	145:64910690c574	245	#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM1D2SEL)
AnnaBridge	145:64910690c574	246	#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| 0x00000000)
AnnaBridge	145:64910690c574	247	#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) \| SYSCFG_MCHDLYCR_DFSDM2D2SEL)
AnnaBridge	145:64910690c574	248	/**
AnnaBridge	145:64910690c574	249	* @}
AnnaBridge	145:64910690c574	250	*/
AnnaBridge	145:64910690c574	251	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
AnnaBridge	145:64910690c574	252	* @{
AnnaBridge	145:64910690c574	253	*/
AnnaBridge	145:64910690c574	254	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
AnnaBridge	145:64910690c574	255	#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
AnnaBridge	145:64910690c574	256	/**
AnnaBridge	145:64910690c574	257	* @}
AnnaBridge	145:64910690c574	258	*/
AnnaBridge	145:64910690c574	259	/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
AnnaBridge	145:64910690c574	260	* @{
AnnaBridge	145:64910690c574	261	*/
AnnaBridge	145:64910690c574	262	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
AnnaBridge	145:64910690c574	263	#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
AnnaBridge	145:64910690c574	264	/**
AnnaBridge	145:64910690c574	265	* @}
AnnaBridge	145:64910690c574	266	*/
AnnaBridge	145:64910690c574	267	/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
AnnaBridge	145:64910690c574	268	* @{
AnnaBridge	145:64910690c574	269	*/
AnnaBridge	145:64910690c574	270	#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
AnnaBridge	145:64910690c574	271	#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
AnnaBridge	145:64910690c574	272	/**
AnnaBridge	145:64910690c574	273	* @}
AnnaBridge	145:64910690c574	274	*/
AnnaBridge	145:64910690c574	275	/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
AnnaBridge	145:64910690c574	276	* @{
AnnaBridge	145:64910690c574	277	*/
AnnaBridge	145:64910690c574	278	#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
AnnaBridge	145:64910690c574	279	#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
AnnaBridge	145:64910690c574	280	/**
AnnaBridge	145:64910690c574	281	* @}
AnnaBridge	145:64910690c574	282	*/
AnnaBridge	145:64910690c574	283
AnnaBridge	145:64910690c574	284	/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
AnnaBridge	145:64910690c574	285	* @{
AnnaBridge	145:64910690c574	286	*/
AnnaBridge	145:64910690c574	287	#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
AnnaBridge	145:64910690c574	288	#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
AnnaBridge	145:64910690c574	289	/**
AnnaBridge	145:64910690c574	290	* @}
AnnaBridge	145:64910690c574	291	*/
AnnaBridge	145:64910690c574	292	/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
AnnaBridge	145:64910690c574	293	* @{
AnnaBridge	145:64910690c574	294	*/
AnnaBridge	145:64910690c574	295	#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
AnnaBridge	145:64910690c574	296	#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
AnnaBridge	145:64910690c574	297	/**
AnnaBridge	145:64910690c574	298	* @}
AnnaBridge	145:64910690c574	299	*/
AnnaBridge	145:64910690c574	300	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
AnnaBridge	145:64910690c574	301	* @{
AnnaBridge	145:64910690c574	302	*/
AnnaBridge	145:64910690c574	303	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
AnnaBridge	145:64910690c574	304	#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
AnnaBridge	145:64910690c574	305	/**
AnnaBridge	145:64910690c574	306	* @}
AnnaBridge	145:64910690c574	307	*/
AnnaBridge	145:64910690c574	308	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
AnnaBridge	145:64910690c574	309	* @{
AnnaBridge	145:64910690c574	310	*/
AnnaBridge	145:64910690c574	311	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
AnnaBridge	145:64910690c574	312	#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
AnnaBridge	145:64910690c574	313	/**
AnnaBridge	145:64910690c574	314	* @}
AnnaBridge	145:64910690c574	315	*/
AnnaBridge	145:64910690c574	316	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
AnnaBridge	145:64910690c574	317	* @{
AnnaBridge	145:64910690c574	318	*/
AnnaBridge	145:64910690c574	319	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
AnnaBridge	145:64910690c574	320	#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
AnnaBridge	145:64910690c574	321	/**
AnnaBridge	145:64910690c574	322	* @}
AnnaBridge	145:64910690c574	323	*/
AnnaBridge	145:64910690c574	324	/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
AnnaBridge	145:64910690c574	325	* @{
AnnaBridge	145:64910690c574	326	*/
AnnaBridge	145:64910690c574	327	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
AnnaBridge	145:64910690c574	328	#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
AnnaBridge	145:64910690c574	329	/**
AnnaBridge	145:64910690c574	330	* @}
AnnaBridge	145:64910690c574	331	*/
AnnaBridge	145:64910690c574	332	/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
AnnaBridge	145:64910690c574	333	* @{
AnnaBridge	145:64910690c574	334	*/
AnnaBridge	145:64910690c574	335	#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
AnnaBridge	145:64910690c574	336	#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
AnnaBridge	145:64910690c574	337	/**
AnnaBridge	145:64910690c574	338	* @}
AnnaBridge	145:64910690c574	339	*/
AnnaBridge	145:64910690c574	340	/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
AnnaBridge	145:64910690c574	341	* @{
AnnaBridge	145:64910690c574	342	*/
AnnaBridge	145:64910690c574	343	#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
AnnaBridge	145:64910690c574	344	#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
AnnaBridge	145:64910690c574	345	/**
AnnaBridge	145:64910690c574	346	* @}
AnnaBridge	145:64910690c574	347	*/
AnnaBridge	145:64910690c574	348	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
AnnaBridge	145:64910690c574	349
AnnaBridge	145:64910690c574	350	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
AnnaBridge	145:64910690c574	351	* @{
AnnaBridge	145:64910690c574	352	*/
AnnaBridge	145:64910690c574	353	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
AnnaBridge	145:64910690c574	354	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
AnnaBridge	145:64910690c574	355	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
AnnaBridge	145:64910690c574	356	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
AnnaBridge	145:64910690c574	357	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
AnnaBridge	145:64910690c574	358	/**
AnnaBridge	145:64910690c574	359	* @}
AnnaBridge	145:64910690c574	360	*/
AnnaBridge	145:64910690c574	361
AnnaBridge	145:64910690c574	362	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
AnnaBridge	145:64910690c574	363	* @{
AnnaBridge	145:64910690c574	364	*/
AnnaBridge	145:64910690c574	365	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
AnnaBridge	145:64910690c574	366	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
AnnaBridge	145:64910690c574	367	#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
AnnaBridge	145:64910690c574	368	#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
AnnaBridge	145:64910690c574	369	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
AnnaBridge	145:64910690c574	370	#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
AnnaBridge	145:64910690c574	371	#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
AnnaBridge	145:64910690c574	372	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /!< TIM4 counter stopped when core is halted /
AnnaBridge	145:64910690c574	373	#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
AnnaBridge	145:64910690c574	374	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /!< TIM5 counter stopped when core is halted /
AnnaBridge	145:64910690c574	375	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
AnnaBridge	145:64910690c574	376	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
AnnaBridge	145:64910690c574	377	#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
AnnaBridge	145:64910690c574	378	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
AnnaBridge	145:64910690c574	379	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
AnnaBridge	145:64910690c574	380	#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
AnnaBridge	145:64910690c574	381	#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
AnnaBridge	145:64910690c574	382	#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /!< TIM12 counter stopped when core is halted /
AnnaBridge	145:64910690c574	383	#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
AnnaBridge	145:64910690c574	384	#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
AnnaBridge	145:64910690c574	385	#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /!< TIM13 counter stopped when core is halted /
AnnaBridge	145:64910690c574	386	#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
AnnaBridge	145:64910690c574	387	#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
AnnaBridge	145:64910690c574	388	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
AnnaBridge	145:64910690c574	389	#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
AnnaBridge	145:64910690c574	390	#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
AnnaBridge	145:64910690c574	391	#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /!< LPTIM counter stopped when core is halted /
AnnaBridge	145:64910690c574	392	#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
AnnaBridge	145:64910690c574	393	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC counter stopped when core is halted /
AnnaBridge	145:64910690c574	394	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
AnnaBridge	145:64910690c574	395	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
AnnaBridge	145:64910690c574	396	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	145:64910690c574	397	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /!< I2C2 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	145:64910690c574	398	#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
AnnaBridge	145:64910690c574	399	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /!< I2C3 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	145:64910690c574	400	#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
AnnaBridge	145:64910690c574	401	#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
AnnaBridge	145:64910690c574	402	#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /!< I2C4 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	145:64910690c574	403	#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
AnnaBridge	145:64910690c574	404	#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
AnnaBridge	145:64910690c574	405	#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /!< CAN1 debug stopped when Core is halted /
AnnaBridge	145:64910690c574	406	#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
AnnaBridge	145:64910690c574	407	#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
AnnaBridge	145:64910690c574	408	#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /!< CAN2 debug stopped when Core is halted /
AnnaBridge	145:64910690c574	409	#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
AnnaBridge	145:64910690c574	410	#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
AnnaBridge	145:64910690c574	411	#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /!< CAN3 debug stopped when Core is halted /
AnnaBridge	145:64910690c574	412	#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
AnnaBridge	145:64910690c574	413	/**
AnnaBridge	145:64910690c574	414	* @}
AnnaBridge	145:64910690c574	415	*/
AnnaBridge	145:64910690c574	416
AnnaBridge	145:64910690c574	417	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
AnnaBridge	145:64910690c574	418	* @{
AnnaBridge	145:64910690c574	419	*/
AnnaBridge	145:64910690c574	420	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
AnnaBridge	145:64910690c574	421	#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
AnnaBridge	145:64910690c574	422	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /!< TIM8 counter stopped when core is halted /
AnnaBridge	145:64910690c574	423	#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
AnnaBridge	145:64910690c574	424	#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /!< TIM9 counter stopped when core is halted /
AnnaBridge	145:64910690c574	425	#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
AnnaBridge	145:64910690c574	426	#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /!< TIM10 counter stopped when core is halted /
AnnaBridge	145:64910690c574	427	#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
AnnaBridge	145:64910690c574	428	#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /!< TIM11 counter stopped when core is halted /
AnnaBridge	145:64910690c574	429	/**
AnnaBridge	145:64910690c574	430	* @}
AnnaBridge	145:64910690c574	431	*/
AnnaBridge	145:64910690c574	432
AnnaBridge	145:64910690c574	433	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
AnnaBridge	145:64910690c574	434	* @{
AnnaBridge	145:64910690c574	435	*/
AnnaBridge	145:64910690c574	436	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
AnnaBridge	145:64910690c574	437	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
AnnaBridge	145:64910690c574	438	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
AnnaBridge	145:64910690c574	439	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
AnnaBridge	145:64910690c574	440	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
AnnaBridge	145:64910690c574	441	#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH five wait state /
AnnaBridge	145:64910690c574	442	#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH six wait state /
AnnaBridge	145:64910690c574	443	#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH seven wait states /
AnnaBridge	145:64910690c574	444	#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /!< FLASH eight wait states /
AnnaBridge	145:64910690c574	445	#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /!< FLASH nine wait states /
AnnaBridge	145:64910690c574	446	#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /!< FLASH ten wait states /
AnnaBridge	145:64910690c574	447	#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /!< FLASH eleven wait states /
AnnaBridge	145:64910690c574	448	#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /!< FLASH twelve wait states /
AnnaBridge	145:64910690c574	449	#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /!< FLASH thirteen wait states /
AnnaBridge	145:64910690c574	450	#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /!< FLASH fourteen wait states /
AnnaBridge	145:64910690c574	451	#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /!< FLASH fifteen wait states /
AnnaBridge	145:64910690c574	452	/**
AnnaBridge	145:64910690c574	453	* @}
AnnaBridge	145:64910690c574	454	*/
AnnaBridge	145:64910690c574	455
AnnaBridge	145:64910690c574	456	/**
AnnaBridge	145:64910690c574	457	* @}
AnnaBridge	145:64910690c574	458	*/
AnnaBridge	145:64910690c574	459
AnnaBridge	145:64910690c574	460	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	461
AnnaBridge	145:64910690c574	462	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	463	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
AnnaBridge	145:64910690c574	464	* @{
AnnaBridge	145:64910690c574	465	*/
AnnaBridge	145:64910690c574	466
AnnaBridge	145:64910690c574	467	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
AnnaBridge	145:64910690c574	468	* @{
AnnaBridge	145:64910690c574	469	*/
AnnaBridge	145:64910690c574	470	/**
AnnaBridge	145:64910690c574	471	* @brief Set memory mapping at address 0x00000000
AnnaBridge	145:64910690c574	472	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
AnnaBridge	145:64910690c574	473	* @param Memory This parameter can be one of the following values:
AnnaBridge	145:64910690c574	474	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	145:64910690c574	475	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	145:64910690c574	476	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	145:64910690c574	477	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
AnnaBridge	145:64910690c574	478	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
AnnaBridge	145:64910690c574	479	* @retval None
AnnaBridge	145:64910690c574	480	*/
AnnaBridge	145:64910690c574	481	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
AnnaBridge	145:64910690c574	482	{
AnnaBridge	145:64910690c574	483	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
AnnaBridge	145:64910690c574	484	}
AnnaBridge	145:64910690c574	485
AnnaBridge	145:64910690c574	486	/**
AnnaBridge	145:64910690c574	487	* @brief Get memory mapping at address 0x00000000
AnnaBridge	145:64910690c574	488	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
AnnaBridge	145:64910690c574	489	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	490	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	145:64910690c574	491	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	145:64910690c574	492	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	145:64910690c574	493	* @arg @ref LL_SYSCFG_REMAP_FSMC (*)
AnnaBridge	145:64910690c574	494	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
AnnaBridge	145:64910690c574	495	*/
AnnaBridge	145:64910690c574	496	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
AnnaBridge	145:64910690c574	497	{
AnnaBridge	145:64910690c574	498	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
AnnaBridge	145:64910690c574	499	}
AnnaBridge	145:64910690c574	500
AnnaBridge	145:64910690c574	501	#if defined(SYSCFG_MEMRMP_SWP_FMC)
AnnaBridge	145:64910690c574	502	/**
AnnaBridge	145:64910690c574	503	* @brief Enables the FMC Memory Mapping Swapping
AnnaBridge	145:64910690c574	504	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
AnnaBridge	145:64910690c574	505	* @note SDRAM is accessible at 0x60000000 and NOR/RAM
AnnaBridge	145:64910690c574	506	* is accessible at 0xC0000000
AnnaBridge	145:64910690c574	507	* @retval None
AnnaBridge	145:64910690c574	508	*/
AnnaBridge	145:64910690c574	509	__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
AnnaBridge	145:64910690c574	510	{
AnnaBridge	145:64910690c574	511	SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
AnnaBridge	145:64910690c574	512	}
AnnaBridge	145:64910690c574	513
AnnaBridge	145:64910690c574	514	/**
AnnaBridge	145:64910690c574	515	* @brief Disables the FMC Memory Mapping Swapping
AnnaBridge	145:64910690c574	516	* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
AnnaBridge	145:64910690c574	517	* @note SDRAM is accessible at 0xC0000000 (default mapping)
AnnaBridge	145:64910690c574	518	* and NOR/RAM is accessible at 0x60000000 (default mapping)
AnnaBridge	145:64910690c574	519	* @retval None
AnnaBridge	145:64910690c574	520	*/
AnnaBridge	145:64910690c574	521	__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
AnnaBridge	145:64910690c574	522	{
AnnaBridge	145:64910690c574	523	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
AnnaBridge	145:64910690c574	524	}
AnnaBridge	145:64910690c574	525
AnnaBridge	145:64910690c574	526	#endif /* SYSCFG_MEMRMP_SWP_FMC */
AnnaBridge	145:64910690c574	527	/**
AnnaBridge	145:64910690c574	528	* @brief Enables the Compensation cell Power Down
AnnaBridge	145:64910690c574	529	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
AnnaBridge	145:64910690c574	530	* @note The I/O compensation cell can be used only when the device supply
AnnaBridge	145:64910690c574	531	* voltage ranges from 2.4 to 3.6 V
AnnaBridge	145:64910690c574	532	* @retval None
AnnaBridge	145:64910690c574	533	*/
AnnaBridge	145:64910690c574	534	__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
AnnaBridge	145:64910690c574	535	{
AnnaBridge	145:64910690c574	536	SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
AnnaBridge	145:64910690c574	537	}
AnnaBridge	145:64910690c574	538
AnnaBridge	145:64910690c574	539	/**
AnnaBridge	145:64910690c574	540	* @brief Disables the Compensation cell Power Down
AnnaBridge	145:64910690c574	541	* @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
AnnaBridge	145:64910690c574	542	* @note The I/O compensation cell can be used only when the device supply
AnnaBridge	145:64910690c574	543	* voltage ranges from 2.4 to 3.6 V
AnnaBridge	145:64910690c574	544	* @retval None
AnnaBridge	145:64910690c574	545	*/
AnnaBridge	145:64910690c574	546	__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
AnnaBridge	145:64910690c574	547	{
AnnaBridge	145:64910690c574	548	CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
AnnaBridge	145:64910690c574	549	}
AnnaBridge	145:64910690c574	550
AnnaBridge	145:64910690c574	551	/**
AnnaBridge	145:64910690c574	552	* @brief Get Compensation Cell ready Flag
AnnaBridge	145:64910690c574	553	* @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
AnnaBridge	145:64910690c574	554	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	555	*/
AnnaBridge	145:64910690c574	556	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
AnnaBridge	145:64910690c574	557	{
AnnaBridge	145:64910690c574	558	return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
AnnaBridge	145:64910690c574	559	}
AnnaBridge	145:64910690c574	560
AnnaBridge	145:64910690c574	561	#if defined(SYSCFG_PMC_MII_RMII_SEL)
AnnaBridge	145:64910690c574	562	/**
AnnaBridge	145:64910690c574	563	* @brief Select Ethernet PHY interface
AnnaBridge	145:64910690c574	564	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
AnnaBridge	145:64910690c574	565	* @param Interface This parameter can be one of the following values:
AnnaBridge	145:64910690c574	566	* @arg @ref LL_SYSCFG_PMC_ETHMII
AnnaBridge	145:64910690c574	567	* @arg @ref LL_SYSCFG_PMC_ETHRMII
AnnaBridge	145:64910690c574	568	* @retval None
AnnaBridge	145:64910690c574	569	*/
AnnaBridge	145:64910690c574	570	__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
AnnaBridge	145:64910690c574	571	{
AnnaBridge	145:64910690c574	572	MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
AnnaBridge	145:64910690c574	573	}
AnnaBridge	145:64910690c574	574
AnnaBridge	145:64910690c574	575	/**
AnnaBridge	145:64910690c574	576	* @brief Get Ethernet PHY interface
AnnaBridge	145:64910690c574	577	* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
AnnaBridge	145:64910690c574	578	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	579	* @arg @ref LL_SYSCFG_PMC_ETHMII
AnnaBridge	145:64910690c574	580	* @arg @ref LL_SYSCFG_PMC_ETHRMII
AnnaBridge	145:64910690c574	581	* @retval None
AnnaBridge	145:64910690c574	582	*/
AnnaBridge	145:64910690c574	583	__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
AnnaBridge	145:64910690c574	584	{
AnnaBridge	145:64910690c574	585	return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
AnnaBridge	145:64910690c574	586	}
AnnaBridge	145:64910690c574	587	#endif /* SYSCFG_PMC_MII_RMII_SEL */
AnnaBridge	145:64910690c574	588
AnnaBridge	145:64910690c574	589
AnnaBridge	145:64910690c574	590
AnnaBridge	145:64910690c574	591	#if defined(SYSCFG_MEMRMP_UFB_MODE)
AnnaBridge	145:64910690c574	592	/**
AnnaBridge	145:64910690c574	593	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
AnnaBridge	145:64910690c574	594	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode
AnnaBridge	145:64910690c574	595	* @param Bank This parameter can be one of the following values:
AnnaBridge	145:64910690c574	596	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
AnnaBridge	145:64910690c574	597	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
AnnaBridge	145:64910690c574	598	* @retval None
AnnaBridge	145:64910690c574	599	*/
AnnaBridge	145:64910690c574	600	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
AnnaBridge	145:64910690c574	601	{
AnnaBridge	145:64910690c574	602	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
AnnaBridge	145:64910690c574	603	}
AnnaBridge	145:64910690c574	604
AnnaBridge	145:64910690c574	605	/**
AnnaBridge	145:64910690c574	606	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
AnnaBridge	145:64910690c574	607	* @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode
AnnaBridge	145:64910690c574	608	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	609	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
AnnaBridge	145:64910690c574	610	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
AnnaBridge	145:64910690c574	611	*/
AnnaBridge	145:64910690c574	612	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
AnnaBridge	145:64910690c574	613	{
AnnaBridge	145:64910690c574	614	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
AnnaBridge	145:64910690c574	615	}
AnnaBridge	145:64910690c574	616	#endif /* SYSCFG_MEMRMP_UFB_MODE */
AnnaBridge	145:64910690c574	617
AnnaBridge	145:64910690c574	618	#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
AnnaBridge	145:64910690c574	619	/**
AnnaBridge	145:64910690c574	620	* @brief Enable the I2C fast mode plus driving capability.
AnnaBridge	145:64910690c574	621	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	145:64910690c574	622	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus
AnnaBridge	145:64910690c574	623	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	624	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
AnnaBridge	145:64910690c574	625	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
AnnaBridge	145:64910690c574	626	* (*) value not defined in all devices
AnnaBridge	145:64910690c574	627	* @retval None
AnnaBridge	145:64910690c574	628	*/
AnnaBridge	145:64910690c574	629	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	145:64910690c574	630	{
AnnaBridge	145:64910690c574	631	SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
AnnaBridge	145:64910690c574	632	}
AnnaBridge	145:64910690c574	633
AnnaBridge	145:64910690c574	634	/**
AnnaBridge	145:64910690c574	635	* @brief Disable the I2C fast mode plus driving capability.
AnnaBridge	145:64910690c574	636	* @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	145:64910690c574	637	* SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	145:64910690c574	638	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	639	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
AnnaBridge	145:64910690c574	640	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
AnnaBridge	145:64910690c574	641	* (*) value not defined in all devices
AnnaBridge	145:64910690c574	642	* @retval None
AnnaBridge	145:64910690c574	643	*/
AnnaBridge	145:64910690c574	644	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	145:64910690c574	645	{
AnnaBridge	145:64910690c574	646	CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
AnnaBridge	145:64910690c574	647	}
AnnaBridge	145:64910690c574	648	#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
AnnaBridge	145:64910690c574	649
AnnaBridge	145:64910690c574	650	/**
AnnaBridge	145:64910690c574	651	* @brief Configure source input for the EXTI external interrupt.
AnnaBridge	145:64910690c574	652	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	145:64910690c574	653	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	145:64910690c574	654	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	145:64910690c574	655	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
AnnaBridge	145:64910690c574	656	* @param Port This parameter can be one of the following values:
AnnaBridge	145:64910690c574	657	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	145:64910690c574	658	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	145:64910690c574	659	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	145:64910690c574	660	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	145:64910690c574	661	* @arg @ref LL_SYSCFG_EXTI_PORTE
AnnaBridge	145:64910690c574	662	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
AnnaBridge	145:64910690c574	663	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
AnnaBridge	145:64910690c574	664	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	145:64910690c574	665	*
AnnaBridge	145:64910690c574	666	* (*) value not defined in all devices
AnnaBridge	145:64910690c574	667	* @param Line This parameter can be one of the following values:
AnnaBridge	145:64910690c574	668	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	145:64910690c574	669	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	145:64910690c574	670	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	145:64910690c574	671	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	145:64910690c574	672	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	145:64910690c574	673	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	145:64910690c574	674	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	145:64910690c574	675	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	145:64910690c574	676	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	145:64910690c574	677	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	145:64910690c574	678	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	145:64910690c574	679	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	145:64910690c574	680	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	145:64910690c574	681	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	145:64910690c574	682	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	145:64910690c574	683	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	145:64910690c574	684	* @retval None
AnnaBridge	145:64910690c574	685	*/
AnnaBridge	145:64910690c574	686	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
AnnaBridge	145:64910690c574	687	{
AnnaBridge	145:64910690c574	688	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
AnnaBridge	145:64910690c574	689	}
AnnaBridge	145:64910690c574	690
AnnaBridge	145:64910690c574	691	/**
AnnaBridge	145:64910690c574	692	* @brief Get the configured defined for specific EXTI Line
AnnaBridge	145:64910690c574	693	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	145:64910690c574	694	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	145:64910690c574	695	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	145:64910690c574	696	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
AnnaBridge	145:64910690c574	697	* @param Line This parameter can be one of the following values:
AnnaBridge	145:64910690c574	698	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	145:64910690c574	699	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	145:64910690c574	700	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	145:64910690c574	701	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	145:64910690c574	702	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	145:64910690c574	703	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	145:64910690c574	704	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	145:64910690c574	705	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	145:64910690c574	706	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	145:64910690c574	707	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	145:64910690c574	708	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	145:64910690c574	709	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	145:64910690c574	710	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	145:64910690c574	711	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	145:64910690c574	712	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	145:64910690c574	713	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	145:64910690c574	714	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	715	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	145:64910690c574	716	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	145:64910690c574	717	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	145:64910690c574	718	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	145:64910690c574	719	* @arg @ref LL_SYSCFG_EXTI_PORTE
AnnaBridge	145:64910690c574	720	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
AnnaBridge	145:64910690c574	721	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
AnnaBridge	145:64910690c574	722	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	145:64910690c574	723	* (*) value not defined in all devices
AnnaBridge	145:64910690c574	724	*/
AnnaBridge	145:64910690c574	725	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
AnnaBridge	145:64910690c574	726	{
AnnaBridge	145:64910690c574	727	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
AnnaBridge	145:64910690c574	728	}
AnnaBridge	145:64910690c574	729
AnnaBridge	145:64910690c574	730	#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
AnnaBridge	145:64910690c574	731	/**
AnnaBridge	145:64910690c574	732	* @brief Set connections to TIM1/8 break inputs
AnnaBridge	145:64910690c574	733	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
AnnaBridge	145:64910690c574	734	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
AnnaBridge	145:64910690c574	735	* @param Break This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	736	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
AnnaBridge	145:64910690c574	737	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
AnnaBridge	145:64910690c574	738	* @retval None
AnnaBridge	145:64910690c574	739	*/
AnnaBridge	145:64910690c574	740	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
AnnaBridge	145:64910690c574	741	{
AnnaBridge	145:64910690c574	742	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
AnnaBridge	145:64910690c574	743	}
AnnaBridge	145:64910690c574	744
AnnaBridge	145:64910690c574	745	/**
AnnaBridge	145:64910690c574	746	* @brief Get connections to TIM1/8 Break inputs
AnnaBridge	145:64910690c574	747	* @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
AnnaBridge	145:64910690c574	748	* SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
AnnaBridge	145:64910690c574	749	* @retval Returned value can be can be a combination of the following values:
AnnaBridge	145:64910690c574	750	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
AnnaBridge	145:64910690c574	751	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
AnnaBridge	145:64910690c574	752	*/
AnnaBridge	145:64910690c574	753	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
AnnaBridge	145:64910690c574	754	{
AnnaBridge	145:64910690c574	755	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
AnnaBridge	145:64910690c574	756	}
AnnaBridge	145:64910690c574	757	#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
AnnaBridge	145:64910690c574	758	#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
AnnaBridge	145:64910690c574	759	/**
AnnaBridge	145:64910690c574	760	* @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
AnnaBridge	145:64910690c574	761	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
AnnaBridge	145:64910690c574	762	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	763	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
AnnaBridge	145:64910690c574	764	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
AnnaBridge	145:64910690c574	765	* @retval None
AnnaBridge	145:64910690c574	766	*/
AnnaBridge	145:64910690c574	767	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
AnnaBridge	145:64910690c574	768	{
AnnaBridge	145:64910690c574	769	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
AnnaBridge	145:64910690c574	770	}
AnnaBridge	145:64910690c574	771	/**
AnnaBridge	145:64910690c574	772	* @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
AnnaBridge	145:64910690c574	773	* @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
AnnaBridge	145:64910690c574	774	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	775	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
AnnaBridge	145:64910690c574	776	* @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
AnnaBridge	145:64910690c574	777	* @retval None
AnnaBridge	145:64910690c574	778	*/
AnnaBridge	145:64910690c574	779	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
AnnaBridge	145:64910690c574	780	{
AnnaBridge	145:64910690c574	781	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
AnnaBridge	145:64910690c574	782	}
AnnaBridge	145:64910690c574	783	/**
AnnaBridge	145:64910690c574	784	* @brief Enables the DFSDM1 or DFSDM2 Delay clock
AnnaBridge	145:64910690c574	785	* @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock
AnnaBridge	145:64910690c574	786	* @param MCHDLY This paramater can be one of the following values
AnnaBridge	145:64910690c574	787	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
AnnaBridge	145:64910690c574	788	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
AnnaBridge	145:64910690c574	789	* @retval None
AnnaBridge	145:64910690c574	790	*/
AnnaBridge	145:64910690c574	791	__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
AnnaBridge	145:64910690c574	792	{
AnnaBridge	145:64910690c574	793	SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
AnnaBridge	145:64910690c574	794	}
AnnaBridge	145:64910690c574	795
AnnaBridge	145:64910690c574	796	/**
AnnaBridge	145:64910690c574	797	* @brief Disables the DFSDM1 or the DFSDM2 Delay clock
AnnaBridge	145:64910690c574	798	* @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock
AnnaBridge	145:64910690c574	799	* @param MCHDLY This paramater can be one of the following values
AnnaBridge	145:64910690c574	800	* @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
AnnaBridge	145:64910690c574	801	* @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
AnnaBridge	145:64910690c574	802	* @retval None
AnnaBridge	145:64910690c574	803	*/
AnnaBridge	145:64910690c574	804	__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
AnnaBridge	145:64910690c574	805	{
AnnaBridge	145:64910690c574	806	CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
AnnaBridge	145:64910690c574	807	}
AnnaBridge	145:64910690c574	808
AnnaBridge	145:64910690c574	809	/**
AnnaBridge	145:64910690c574	810	* @brief Select the source for DFSDM1 or DFSDM2 DatIn0
AnnaBridge	145:64910690c574	811	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
AnnaBridge	145:64910690c574	812	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	813	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
AnnaBridge	145:64910690c574	814	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
AnnaBridge	145:64910690c574	815	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
AnnaBridge	145:64910690c574	816	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
AnnaBridge	145:64910690c574	817	* @retval None
AnnaBridge	145:64910690c574	818	*/
AnnaBridge	145:64910690c574	819	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
AnnaBridge	145:64910690c574	820	{
AnnaBridge	145:64910690c574	821	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
AnnaBridge	145:64910690c574	822	}
AnnaBridge	145:64910690c574	823	/**
AnnaBridge	145:64910690c574	824	* @brief Get the source for DFSDM1 or DFSDM2 DatIn0.
AnnaBridge	145:64910690c574	825	* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source
AnnaBridge	145:64910690c574	826	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	827	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0
AnnaBridge	145:64910690c574	828	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0
AnnaBridge	145:64910690c574	829	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	830	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
AnnaBridge	145:64910690c574	831	* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
AnnaBridge	145:64910690c574	832	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
AnnaBridge	145:64910690c574	833	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
AnnaBridge	145:64910690c574	834	* @retval None
AnnaBridge	145:64910690c574	835	*/
AnnaBridge	145:64910690c574	836	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
AnnaBridge	145:64910690c574	837	{
AnnaBridge	145:64910690c574	838	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
AnnaBridge	145:64910690c574	839	}
AnnaBridge	145:64910690c574	840	/**
AnnaBridge	145:64910690c574	841	* @brief Select the source for DFSDM1 or DFSDM2 DatIn2
AnnaBridge	145:64910690c574	842	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
AnnaBridge	145:64910690c574	843	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	844	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
AnnaBridge	145:64910690c574	845	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
AnnaBridge	145:64910690c574	846	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
AnnaBridge	145:64910690c574	847	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
AnnaBridge	145:64910690c574	848	* @retval None
AnnaBridge	145:64910690c574	849	*/
AnnaBridge	145:64910690c574	850	__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
AnnaBridge	145:64910690c574	851	{
AnnaBridge	145:64910690c574	852	MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
AnnaBridge	145:64910690c574	853	}
AnnaBridge	145:64910690c574	854	/**
AnnaBridge	145:64910690c574	855	* @brief Get the source for DFSDM1 or DFSDM2 DatIn2.
AnnaBridge	145:64910690c574	856	* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source
AnnaBridge	145:64910690c574	857	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	858	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2
AnnaBridge	145:64910690c574	859	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2
AnnaBridge	145:64910690c574	860	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	861	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
AnnaBridge	145:64910690c574	862	* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
AnnaBridge	145:64910690c574	863	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
AnnaBridge	145:64910690c574	864	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
AnnaBridge	145:64910690c574	865	* @retval None
AnnaBridge	145:64910690c574	866	*/
AnnaBridge	145:64910690c574	867	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
AnnaBridge	145:64910690c574	868	{
AnnaBridge	145:64910690c574	869	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
AnnaBridge	145:64910690c574	870	}
AnnaBridge	145:64910690c574	871
AnnaBridge	145:64910690c574	872	/**
AnnaBridge	145:64910690c574	873	* @brief Select the distribution of the bitsream lock gated by TIM4 OC2
AnnaBridge	145:64910690c574	874	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
AnnaBridge	145:64910690c574	875	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	876	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
AnnaBridge	145:64910690c574	877	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
AnnaBridge	145:64910690c574	878	* @retval None
AnnaBridge	145:64910690c574	879	*/
AnnaBridge	145:64910690c574	880	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
AnnaBridge	145:64910690c574	881	{
AnnaBridge	145:64910690c574	882	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
AnnaBridge	145:64910690c574	883	}
AnnaBridge	145:64910690c574	884	/**
AnnaBridge	145:64910690c574	885	* @brief Get the distribution of the bitsream lock gated by TIM4 OC2
AnnaBridge	145:64910690c574	886	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
AnnaBridge	145:64910690c574	887	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	888	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
AnnaBridge	145:64910690c574	889	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
AnnaBridge	145:64910690c574	890	* @retval None
AnnaBridge	145:64910690c574	891	*/
AnnaBridge	145:64910690c574	892	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
AnnaBridge	145:64910690c574	893	{
AnnaBridge	145:64910690c574	894	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
AnnaBridge	145:64910690c574	895	}
AnnaBridge	145:64910690c574	896
AnnaBridge	145:64910690c574	897	/**
AnnaBridge	145:64910690c574	898	* @brief Select the distribution of the bitsream lock gated by TIM4 OC1
AnnaBridge	145:64910690c574	899	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
AnnaBridge	145:64910690c574	900	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	901	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
AnnaBridge	145:64910690c574	902	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
AnnaBridge	145:64910690c574	903	* @retval None
AnnaBridge	145:64910690c574	904	*/
AnnaBridge	145:64910690c574	905	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
AnnaBridge	145:64910690c574	906	{
AnnaBridge	145:64910690c574	907	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
AnnaBridge	145:64910690c574	908	}
AnnaBridge	145:64910690c574	909	/**
AnnaBridge	145:64910690c574	910	* @brief Get the distribution of the bitsream lock gated by TIM4 OC1
AnnaBridge	145:64910690c574	911	* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
AnnaBridge	145:64910690c574	912	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	913	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
AnnaBridge	145:64910690c574	914	* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
AnnaBridge	145:64910690c574	915	* @retval None
AnnaBridge	145:64910690c574	916	*/
AnnaBridge	145:64910690c574	917	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
AnnaBridge	145:64910690c574	918	{
AnnaBridge	145:64910690c574	919	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
AnnaBridge	145:64910690c574	920	}
AnnaBridge	145:64910690c574	921
AnnaBridge	145:64910690c574	922	/**
AnnaBridge	145:64910690c574	923	* @brief Select the DFSDM1 Clock In
AnnaBridge	145:64910690c574	924	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
AnnaBridge	145:64910690c574	925	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	926	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
AnnaBridge	145:64910690c574	927	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
AnnaBridge	145:64910690c574	928	* @retval None
AnnaBridge	145:64910690c574	929	*/
AnnaBridge	145:64910690c574	930	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
AnnaBridge	145:64910690c574	931	{
AnnaBridge	145:64910690c574	932	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
AnnaBridge	145:64910690c574	933	}
AnnaBridge	145:64910690c574	934	/**
AnnaBridge	145:64910690c574	935	* @brief GET the DFSDM1 Clock In
AnnaBridge	145:64910690c574	936	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection
AnnaBridge	145:64910690c574	937	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	938	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
AnnaBridge	145:64910690c574	939	* @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
AnnaBridge	145:64910690c574	940	* @retval None
AnnaBridge	145:64910690c574	941	*/
AnnaBridge	145:64910690c574	942	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
AnnaBridge	145:64910690c574	943	{
AnnaBridge	145:64910690c574	944	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
AnnaBridge	145:64910690c574	945	}
AnnaBridge	145:64910690c574	946
AnnaBridge	145:64910690c574	947	/**
AnnaBridge	145:64910690c574	948	* @brief Select the DFSDM1 Clock Out
AnnaBridge	145:64910690c574	949	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
AnnaBridge	145:64910690c574	950	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	951	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
AnnaBridge	145:64910690c574	952	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
AnnaBridge	145:64910690c574	953	* @retval None
AnnaBridge	145:64910690c574	954	*/
AnnaBridge	145:64910690c574	955	__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
AnnaBridge	145:64910690c574	956	{
AnnaBridge	145:64910690c574	957	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
AnnaBridge	145:64910690c574	958	}
AnnaBridge	145:64910690c574	959	/**
AnnaBridge	145:64910690c574	960	* @brief GET the DFSDM1 Clock Out
AnnaBridge	145:64910690c574	961	* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
AnnaBridge	145:64910690c574	962	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	963	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
AnnaBridge	145:64910690c574	964	* @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
AnnaBridge	145:64910690c574	965	* @retval None
AnnaBridge	145:64910690c574	966	*/
AnnaBridge	145:64910690c574	967	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
AnnaBridge	145:64910690c574	968	{
AnnaBridge	145:64910690c574	969	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
AnnaBridge	145:64910690c574	970	}
AnnaBridge	145:64910690c574	971
AnnaBridge	145:64910690c574	972	/**
AnnaBridge	145:64910690c574	973	* @brief Enables the DFSDM2 Delay clock
AnnaBridge	145:64910690c574	974	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock
AnnaBridge	145:64910690c574	975	* @retval None
AnnaBridge	145:64910690c574	976	*/
AnnaBridge	145:64910690c574	977	__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
AnnaBridge	145:64910690c574	978	{
AnnaBridge	145:64910690c574	979	SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
AnnaBridge	145:64910690c574	980	}
AnnaBridge	145:64910690c574	981
AnnaBridge	145:64910690c574	982	/**
AnnaBridge	145:64910690c574	983	* @brief Disables the DFSDM2 Delay clock
AnnaBridge	145:64910690c574	984	* @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock
AnnaBridge	145:64910690c574	985	* @retval None
AnnaBridge	145:64910690c574	986	*/
AnnaBridge	145:64910690c574	987	__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
AnnaBridge	145:64910690c574	988	{
AnnaBridge	145:64910690c574	989	CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
AnnaBridge	145:64910690c574	990	}
AnnaBridge	145:64910690c574	991	/**
AnnaBridge	145:64910690c574	992	* @brief Select the source for DFSDM2 DatIn0
AnnaBridge	145:64910690c574	993	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
AnnaBridge	145:64910690c574	994	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	995	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
AnnaBridge	145:64910690c574	996	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
AnnaBridge	145:64910690c574	997	* @retval None
AnnaBridge	145:64910690c574	998	*/
AnnaBridge	145:64910690c574	999	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
AnnaBridge	145:64910690c574	1000	{
AnnaBridge	145:64910690c574	1001	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
AnnaBridge	145:64910690c574	1002	}
AnnaBridge	145:64910690c574	1003	/**
AnnaBridge	145:64910690c574	1004	* @brief Get the source for DFSDM2 DatIn0.
AnnaBridge	145:64910690c574	1005	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source
AnnaBridge	145:64910690c574	1006	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1007	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
AnnaBridge	145:64910690c574	1008	* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
AnnaBridge	145:64910690c574	1009	* @retval None
AnnaBridge	145:64910690c574	1010	*/
AnnaBridge	145:64910690c574	1011	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
AnnaBridge	145:64910690c574	1012	{
AnnaBridge	145:64910690c574	1013	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
AnnaBridge	145:64910690c574	1014	}
AnnaBridge	145:64910690c574	1015
AnnaBridge	145:64910690c574	1016	/**
AnnaBridge	145:64910690c574	1017	* @brief Select the source for DFSDM2 DatIn2
AnnaBridge	145:64910690c574	1018	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
AnnaBridge	145:64910690c574	1019	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1020	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
AnnaBridge	145:64910690c574	1021	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
AnnaBridge	145:64910690c574	1022	* @retval None
AnnaBridge	145:64910690c574	1023	*/
AnnaBridge	145:64910690c574	1024	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
AnnaBridge	145:64910690c574	1025	{
AnnaBridge	145:64910690c574	1026	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
AnnaBridge	145:64910690c574	1027	}
AnnaBridge	145:64910690c574	1028	/**
AnnaBridge	145:64910690c574	1029	* @brief Get the source for DFSDM2 DatIn2.
AnnaBridge	145:64910690c574	1030	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source
AnnaBridge	145:64910690c574	1031	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1032	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
AnnaBridge	145:64910690c574	1033	* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
AnnaBridge	145:64910690c574	1034	* @retval None
AnnaBridge	145:64910690c574	1035	*/
AnnaBridge	145:64910690c574	1036	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
AnnaBridge	145:64910690c574	1037	{
AnnaBridge	145:64910690c574	1038	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
AnnaBridge	145:64910690c574	1039	}
AnnaBridge	145:64910690c574	1040
AnnaBridge	145:64910690c574	1041	/**
AnnaBridge	145:64910690c574	1042	* @brief Select the source for DFSDM2 DatIn4
AnnaBridge	145:64910690c574	1043	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
AnnaBridge	145:64910690c574	1044	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1045	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
AnnaBridge	145:64910690c574	1046	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
AnnaBridge	145:64910690c574	1047	* @retval None
AnnaBridge	145:64910690c574	1048	*/
AnnaBridge	145:64910690c574	1049	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
AnnaBridge	145:64910690c574	1050	{
AnnaBridge	145:64910690c574	1051	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
AnnaBridge	145:64910690c574	1052	}
AnnaBridge	145:64910690c574	1053	/**
AnnaBridge	145:64910690c574	1054	* @brief Get the source for DFSDM2 DatIn4.
AnnaBridge	145:64910690c574	1055	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source
AnnaBridge	145:64910690c574	1056	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1057	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
AnnaBridge	145:64910690c574	1058	* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
AnnaBridge	145:64910690c574	1059	* @retval None
AnnaBridge	145:64910690c574	1060	*/
AnnaBridge	145:64910690c574	1061	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
AnnaBridge	145:64910690c574	1062	{
AnnaBridge	145:64910690c574	1063	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
AnnaBridge	145:64910690c574	1064	}
AnnaBridge	145:64910690c574	1065
AnnaBridge	145:64910690c574	1066	/**
AnnaBridge	145:64910690c574	1067	* @brief Select the source for DFSDM2 DatIn6
AnnaBridge	145:64910690c574	1068	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
AnnaBridge	145:64910690c574	1069	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1070	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
AnnaBridge	145:64910690c574	1071	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
AnnaBridge	145:64910690c574	1072	* @retval None
AnnaBridge	145:64910690c574	1073	*/
AnnaBridge	145:64910690c574	1074	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
AnnaBridge	145:64910690c574	1075	{
AnnaBridge	145:64910690c574	1076	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
AnnaBridge	145:64910690c574	1077	}
AnnaBridge	145:64910690c574	1078	/**
AnnaBridge	145:64910690c574	1079	* @brief Get the source for DFSDM2 DatIn6.
AnnaBridge	145:64910690c574	1080	* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source
AnnaBridge	145:64910690c574	1081	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1082	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
AnnaBridge	145:64910690c574	1083	* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
AnnaBridge	145:64910690c574	1084	* @retval None
AnnaBridge	145:64910690c574	1085	*/
AnnaBridge	145:64910690c574	1086	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
AnnaBridge	145:64910690c574	1087	{
AnnaBridge	145:64910690c574	1088	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
AnnaBridge	145:64910690c574	1089	}
AnnaBridge	145:64910690c574	1090
AnnaBridge	145:64910690c574	1091	/**
AnnaBridge	145:64910690c574	1092	* @brief Select the distribution of the bitsream lock gated by TIM3 OC4
AnnaBridge	145:64910690c574	1093	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
AnnaBridge	145:64910690c574	1094	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1095	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
AnnaBridge	145:64910690c574	1096	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
AnnaBridge	145:64910690c574	1097	* @retval None
AnnaBridge	145:64910690c574	1098	*/
AnnaBridge	145:64910690c574	1099	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
AnnaBridge	145:64910690c574	1100	{
AnnaBridge	145:64910690c574	1101	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
AnnaBridge	145:64910690c574	1102	}
AnnaBridge	145:64910690c574	1103	/**
AnnaBridge	145:64910690c574	1104	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
AnnaBridge	145:64910690c574	1105	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
AnnaBridge	145:64910690c574	1106	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1107	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
AnnaBridge	145:64910690c574	1108	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
AnnaBridge	145:64910690c574	1109	* @retval None
AnnaBridge	145:64910690c574	1110	*/
AnnaBridge	145:64910690c574	1111	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
AnnaBridge	145:64910690c574	1112	{
AnnaBridge	145:64910690c574	1113	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
AnnaBridge	145:64910690c574	1114	}
AnnaBridge	145:64910690c574	1115
AnnaBridge	145:64910690c574	1116	/**
AnnaBridge	145:64910690c574	1117	* @brief Select the distribution of the bitsream lock gated by TIM3 OC3
AnnaBridge	145:64910690c574	1118	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
AnnaBridge	145:64910690c574	1119	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1120	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
AnnaBridge	145:64910690c574	1121	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
AnnaBridge	145:64910690c574	1122	* @retval None
AnnaBridge	145:64910690c574	1123	*/
AnnaBridge	145:64910690c574	1124	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
AnnaBridge	145:64910690c574	1125	{
AnnaBridge	145:64910690c574	1126	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
AnnaBridge	145:64910690c574	1127	}
AnnaBridge	145:64910690c574	1128	/**
AnnaBridge	145:64910690c574	1129	* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
AnnaBridge	145:64910690c574	1130	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
AnnaBridge	145:64910690c574	1131	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1132	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
AnnaBridge	145:64910690c574	1133	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
AnnaBridge	145:64910690c574	1134	* @retval None
AnnaBridge	145:64910690c574	1135	*/
AnnaBridge	145:64910690c574	1136	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
AnnaBridge	145:64910690c574	1137	{
AnnaBridge	145:64910690c574	1138	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
AnnaBridge	145:64910690c574	1139	}
AnnaBridge	145:64910690c574	1140
AnnaBridge	145:64910690c574	1141	/**
AnnaBridge	145:64910690c574	1142	* @brief Select the distribution of the bitsream lock gated by TIM3 OC2
AnnaBridge	145:64910690c574	1143	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
AnnaBridge	145:64910690c574	1144	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1145	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
AnnaBridge	145:64910690c574	1146	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
AnnaBridge	145:64910690c574	1147	* @retval None
AnnaBridge	145:64910690c574	1148	*/
AnnaBridge	145:64910690c574	1149	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
AnnaBridge	145:64910690c574	1150	{
AnnaBridge	145:64910690c574	1151	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
AnnaBridge	145:64910690c574	1152	}
AnnaBridge	145:64910690c574	1153	/**
AnnaBridge	145:64910690c574	1154	* @brief Get the distribution of the bitsream lock gated by TIM3 OC2
AnnaBridge	145:64910690c574	1155	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
AnnaBridge	145:64910690c574	1156	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1157	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
AnnaBridge	145:64910690c574	1158	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
AnnaBridge	145:64910690c574	1159	* @retval None
AnnaBridge	145:64910690c574	1160	*/
AnnaBridge	145:64910690c574	1161	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
AnnaBridge	145:64910690c574	1162	{
AnnaBridge	145:64910690c574	1163	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
AnnaBridge	145:64910690c574	1164	}
AnnaBridge	145:64910690c574	1165
AnnaBridge	145:64910690c574	1166	/**
AnnaBridge	145:64910690c574	1167	* @brief Select the distribution of the bitsream lock gated by TIM3 OC1
AnnaBridge	145:64910690c574	1168	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
AnnaBridge	145:64910690c574	1169	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1170	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
AnnaBridge	145:64910690c574	1171	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
AnnaBridge	145:64910690c574	1172	* @retval None
AnnaBridge	145:64910690c574	1173	*/
AnnaBridge	145:64910690c574	1174	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
AnnaBridge	145:64910690c574	1175	{
AnnaBridge	145:64910690c574	1176	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
AnnaBridge	145:64910690c574	1177	}
AnnaBridge	145:64910690c574	1178	/**
AnnaBridge	145:64910690c574	1179	* @brief Get the distribution of the bitsream lock gated by TIM3 OC1
AnnaBridge	145:64910690c574	1180	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
AnnaBridge	145:64910690c574	1181	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1182	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
AnnaBridge	145:64910690c574	1183	* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
AnnaBridge	145:64910690c574	1184	* @retval None
AnnaBridge	145:64910690c574	1185	*/
AnnaBridge	145:64910690c574	1186	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
AnnaBridge	145:64910690c574	1187	{
AnnaBridge	145:64910690c574	1188	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
AnnaBridge	145:64910690c574	1189	}
AnnaBridge	145:64910690c574	1190
AnnaBridge	145:64910690c574	1191	/**
AnnaBridge	145:64910690c574	1192	* @brief Select the DFSDM2 Clock In
AnnaBridge	145:64910690c574	1193	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
AnnaBridge	145:64910690c574	1194	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1195	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
AnnaBridge	145:64910690c574	1196	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
AnnaBridge	145:64910690c574	1197	* @retval None
AnnaBridge	145:64910690c574	1198	*/
AnnaBridge	145:64910690c574	1199	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
AnnaBridge	145:64910690c574	1200	{
AnnaBridge	145:64910690c574	1201	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
AnnaBridge	145:64910690c574	1202	}
AnnaBridge	145:64910690c574	1203	/**
AnnaBridge	145:64910690c574	1204	* @brief GET the DFSDM2 Clock In
AnnaBridge	145:64910690c574	1205	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection
AnnaBridge	145:64910690c574	1206	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1207	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
AnnaBridge	145:64910690c574	1208	* @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
AnnaBridge	145:64910690c574	1209	* @retval None
AnnaBridge	145:64910690c574	1210	*/
AnnaBridge	145:64910690c574	1211	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
AnnaBridge	145:64910690c574	1212	{
AnnaBridge	145:64910690c574	1213	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
AnnaBridge	145:64910690c574	1214	}
AnnaBridge	145:64910690c574	1215
AnnaBridge	145:64910690c574	1216	/**
AnnaBridge	145:64910690c574	1217	* @brief Select the DFSDM2 Clock Out
AnnaBridge	145:64910690c574	1218	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
AnnaBridge	145:64910690c574	1219	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1220	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
AnnaBridge	145:64910690c574	1221	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
AnnaBridge	145:64910690c574	1222	* @retval None
AnnaBridge	145:64910690c574	1223	*/
AnnaBridge	145:64910690c574	1224	__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
AnnaBridge	145:64910690c574	1225	{
AnnaBridge	145:64910690c574	1226	MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
AnnaBridge	145:64910690c574	1227	}
AnnaBridge	145:64910690c574	1228	/**
AnnaBridge	145:64910690c574	1229	* @brief GET the DFSDM2 Clock Out
AnnaBridge	145:64910690c574	1230	* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
AnnaBridge	145:64910690c574	1231	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1232	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
AnnaBridge	145:64910690c574	1233	* @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
AnnaBridge	145:64910690c574	1234	* @retval None
AnnaBridge	145:64910690c574	1235	*/
AnnaBridge	145:64910690c574	1236	__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
AnnaBridge	145:64910690c574	1237	{
AnnaBridge	145:64910690c574	1238	return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
AnnaBridge	145:64910690c574	1239	}
AnnaBridge	145:64910690c574	1240
AnnaBridge	145:64910690c574	1241	#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
AnnaBridge	145:64910690c574	1242	/**
AnnaBridge	145:64910690c574	1243	* @}
AnnaBridge	145:64910690c574	1244	*/
AnnaBridge	145:64910690c574	1245
AnnaBridge	145:64910690c574	1246
AnnaBridge	145:64910690c574	1247	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
AnnaBridge	145:64910690c574	1248	* @{
AnnaBridge	145:64910690c574	1249	*/
AnnaBridge	145:64910690c574	1250
AnnaBridge	145:64910690c574	1251	/**
AnnaBridge	145:64910690c574	1252	* @brief Return the device identifier
AnnaBridge	145:64910690c574	1253	* @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
AnnaBridge	145:64910690c574	1254	* @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
AnnaBridge	145:64910690c574	1255	* @note For STM32F401xx devices, the device ID is 0x423
AnnaBridge	145:64910690c574	1256	* @note For STM32F401xx devices, the device ID is 0x433
AnnaBridge	145:64910690c574	1257	* @note For STM32F411xx devices, the device ID is 0x431
AnnaBridge	145:64910690c574	1258	* @note For STM32F410xx devices, the device ID is 0x458
AnnaBridge	145:64910690c574	1259	* @note For STM32F412xx devices, the device ID is 0x441
AnnaBridge	145:64910690c574	1260	* @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
AnnaBridge	145:64910690c574	1261	* @note For STM32F446xx devices, the device ID is 0x421
AnnaBridge	145:64910690c574	1262	* @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
AnnaBridge	145:64910690c574	1263	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
AnnaBridge	145:64910690c574	1264	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
AnnaBridge	145:64910690c574	1265	*/
AnnaBridge	145:64910690c574	1266	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
AnnaBridge	145:64910690c574	1267	{
AnnaBridge	145:64910690c574	1268	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
AnnaBridge	145:64910690c574	1269	}
AnnaBridge	145:64910690c574	1270
AnnaBridge	145:64910690c574	1271	/**
AnnaBridge	145:64910690c574	1272	* @brief Return the device revision identifier
AnnaBridge	145:64910690c574	1273	* @note This field indicates the revision of the device.
AnnaBridge	145:64910690c574	1274	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
AnnaBridge	145:64910690c574	1275	For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
AnnaBridge	145:64910690c574	1276	For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
AnnaBridge	145:64910690c574	1277	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
AnnaBridge	145:64910690c574	1278	For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
AnnaBridge	145:64910690c574	1279	For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
AnnaBridge	145:64910690c574	1280	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
AnnaBridge	145:64910690c574	1281	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1282	*/
AnnaBridge	145:64910690c574	1283	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
AnnaBridge	145:64910690c574	1284	{
AnnaBridge	145:64910690c574	1285	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
AnnaBridge	145:64910690c574	1286	}
AnnaBridge	145:64910690c574	1287
AnnaBridge	145:64910690c574	1288	/**
AnnaBridge	145:64910690c574	1289	* @brief Enable the Debug Module during SLEEP mode
AnnaBridge	145:64910690c574	1290	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
AnnaBridge	145:64910690c574	1291	* @retval None
AnnaBridge	145:64910690c574	1292	*/
AnnaBridge	145:64910690c574	1293	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
AnnaBridge	145:64910690c574	1294	{
AnnaBridge	145:64910690c574	1295	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
AnnaBridge	145:64910690c574	1296	}
AnnaBridge	145:64910690c574	1297
AnnaBridge	145:64910690c574	1298	/**
AnnaBridge	145:64910690c574	1299	* @brief Disable the Debug Module during SLEEP mode
AnnaBridge	145:64910690c574	1300	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
AnnaBridge	145:64910690c574	1301	* @retval None
AnnaBridge	145:64910690c574	1302	*/
AnnaBridge	145:64910690c574	1303	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
AnnaBridge	145:64910690c574	1304	{
AnnaBridge	145:64910690c574	1305	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
AnnaBridge	145:64910690c574	1306	}
AnnaBridge	145:64910690c574	1307
AnnaBridge	145:64910690c574	1308	/**
AnnaBridge	145:64910690c574	1309	* @brief Enable the Debug Module during STOP mode
AnnaBridge	145:64910690c574	1310	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
AnnaBridge	145:64910690c574	1311	* @retval None
AnnaBridge	145:64910690c574	1312	*/
AnnaBridge	145:64910690c574	1313	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
AnnaBridge	145:64910690c574	1314	{
AnnaBridge	145:64910690c574	1315	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	145:64910690c574	1316	}
AnnaBridge	145:64910690c574	1317
AnnaBridge	145:64910690c574	1318	/**
AnnaBridge	145:64910690c574	1319	* @brief Disable the Debug Module during STOP mode
AnnaBridge	145:64910690c574	1320	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
AnnaBridge	145:64910690c574	1321	* @retval None
AnnaBridge	145:64910690c574	1322	*/
AnnaBridge	145:64910690c574	1323	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
AnnaBridge	145:64910690c574	1324	{
AnnaBridge	145:64910690c574	1325	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	145:64910690c574	1326	}
AnnaBridge	145:64910690c574	1327
AnnaBridge	145:64910690c574	1328	/**
AnnaBridge	145:64910690c574	1329	* @brief Enable the Debug Module during STANDBY mode
AnnaBridge	145:64910690c574	1330	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
AnnaBridge	145:64910690c574	1331	* @retval None
AnnaBridge	145:64910690c574	1332	*/
AnnaBridge	145:64910690c574	1333	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
AnnaBridge	145:64910690c574	1334	{
AnnaBridge	145:64910690c574	1335	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	145:64910690c574	1336	}
AnnaBridge	145:64910690c574	1337
AnnaBridge	145:64910690c574	1338	/**
AnnaBridge	145:64910690c574	1339	* @brief Disable the Debug Module during STANDBY mode
AnnaBridge	145:64910690c574	1340	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
AnnaBridge	145:64910690c574	1341	* @retval None
AnnaBridge	145:64910690c574	1342	*/
AnnaBridge	145:64910690c574	1343	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
AnnaBridge	145:64910690c574	1344	{
AnnaBridge	145:64910690c574	1345	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	145:64910690c574	1346	}
AnnaBridge	145:64910690c574	1347
AnnaBridge	145:64910690c574	1348	/**
AnnaBridge	145:64910690c574	1349	* @brief Set Trace pin assignment control
AnnaBridge	145:64910690c574	1350	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
AnnaBridge	145:64910690c574	1351	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
AnnaBridge	145:64910690c574	1352	* @param PinAssignment This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1353	* @arg @ref LL_DBGMCU_TRACE_NONE
AnnaBridge	145:64910690c574	1354	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
AnnaBridge	145:64910690c574	1355	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
AnnaBridge	145:64910690c574	1356	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
AnnaBridge	145:64910690c574	1357	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
AnnaBridge	145:64910690c574	1358	* @retval None
AnnaBridge	145:64910690c574	1359	*/
AnnaBridge	145:64910690c574	1360	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
AnnaBridge	145:64910690c574	1361	{
AnnaBridge	145:64910690c574	1362	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
AnnaBridge	145:64910690c574	1363	}
AnnaBridge	145:64910690c574	1364
AnnaBridge	145:64910690c574	1365	/**
AnnaBridge	145:64910690c574	1366	* @brief Get Trace pin assignment control
AnnaBridge	145:64910690c574	1367	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
AnnaBridge	145:64910690c574	1368	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
AnnaBridge	145:64910690c574	1369	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1370	* @arg @ref LL_DBGMCU_TRACE_NONE
AnnaBridge	145:64910690c574	1371	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
AnnaBridge	145:64910690c574	1372	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
AnnaBridge	145:64910690c574	1373	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
AnnaBridge	145:64910690c574	1374	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
AnnaBridge	145:64910690c574	1375	*/
AnnaBridge	145:64910690c574	1376	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
AnnaBridge	145:64910690c574	1377	{
AnnaBridge	145:64910690c574	1378	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
AnnaBridge	145:64910690c574	1379	}
AnnaBridge	145:64910690c574	1380
AnnaBridge	145:64910690c574	1381	/**
AnnaBridge	145:64910690c574	1382	* @brief Freeze APB1 peripherals (group1 peripherals)
AnnaBridge	145:64910690c574	1383	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1384	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1385	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1386	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1387	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1388	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1389	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1390	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1391	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1392	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1393	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1394	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1395	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1396	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1397	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1398	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1399	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1400	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1401	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1402	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
AnnaBridge	145:64910690c574	1403	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1404	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
AnnaBridge	145:64910690c574	1405	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
AnnaBridge	145:64910690c574	1406	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
AnnaBridge	145:64910690c574	1407	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
AnnaBridge	145:64910690c574	1408	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
AnnaBridge	145:64910690c574	1409	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
AnnaBridge	145:64910690c574	1410	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
AnnaBridge	145:64910690c574	1411	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
AnnaBridge	145:64910690c574	1412	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
AnnaBridge	145:64910690c574	1413	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
AnnaBridge	145:64910690c574	1414	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
AnnaBridge	145:64910690c574	1415	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	145:64910690c574	1416	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	145:64910690c574	1417	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	145:64910690c574	1418	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
AnnaBridge	145:64910690c574	1419	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
AnnaBridge	145:64910690c574	1420	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
AnnaBridge	145:64910690c574	1421	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
AnnaBridge	145:64910690c574	1422	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
AnnaBridge	145:64910690c574	1423	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
AnnaBridge	145:64910690c574	1424	*
AnnaBridge	145:64910690c574	1425	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1426	* @retval None
AnnaBridge	145:64910690c574	1427	*/
AnnaBridge	145:64910690c574	1428	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	145:64910690c574	1429	{
AnnaBridge	145:64910690c574	1430	SET_BIT(DBGMCU->APB1FZ, Periphs);
AnnaBridge	145:64910690c574	1431	}
AnnaBridge	145:64910690c574	1432
AnnaBridge	145:64910690c574	1433	/**
AnnaBridge	145:64910690c574	1434	* @brief Unfreeze APB1 peripherals (group1 peripherals)
AnnaBridge	145:64910690c574	1435	* @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1436	* DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1437	* DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1438	* DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1439	* DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1440	* DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1441	* DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1442	* DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1443	* DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1444	* DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1445	* DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1446	* DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1447	* DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1448	* DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1449	* DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1450	* DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1451	* DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1452	* DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1453	* DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1454	* DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
AnnaBridge	145:64910690c574	1455	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1456	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
AnnaBridge	145:64910690c574	1457	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
AnnaBridge	145:64910690c574	1458	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
AnnaBridge	145:64910690c574	1459	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
AnnaBridge	145:64910690c574	1460	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
AnnaBridge	145:64910690c574	1461	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
AnnaBridge	145:64910690c574	1462	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
AnnaBridge	145:64910690c574	1463	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
AnnaBridge	145:64910690c574	1464	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
AnnaBridge	145:64910690c574	1465	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
AnnaBridge	145:64910690c574	1466	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
AnnaBridge	145:64910690c574	1467	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	145:64910690c574	1468	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	145:64910690c574	1469	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	145:64910690c574	1470	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
AnnaBridge	145:64910690c574	1471	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
AnnaBridge	145:64910690c574	1472	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
AnnaBridge	145:64910690c574	1473	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
AnnaBridge	145:64910690c574	1474	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
AnnaBridge	145:64910690c574	1475	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
AnnaBridge	145:64910690c574	1476	*
AnnaBridge	145:64910690c574	1477	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1478	* @retval None
AnnaBridge	145:64910690c574	1479	*/
AnnaBridge	145:64910690c574	1480	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	145:64910690c574	1481	{
AnnaBridge	145:64910690c574	1482	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
AnnaBridge	145:64910690c574	1483	}
AnnaBridge	145:64910690c574	1484
AnnaBridge	145:64910690c574	1485	/**
AnnaBridge	145:64910690c574	1486	* @brief Freeze APB2 peripherals
AnnaBridge	145:64910690c574	1487	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1488	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1489	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1490	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	145:64910690c574	1491	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
AnnaBridge	145:64910690c574	1492	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1493	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
AnnaBridge	145:64910690c574	1494	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
AnnaBridge	145:64910690c574	1495	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
AnnaBridge	145:64910690c574	1496	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
AnnaBridge	145:64910690c574	1497	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
AnnaBridge	145:64910690c574	1498	*
AnnaBridge	145:64910690c574	1499	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1500	* @retval None
AnnaBridge	145:64910690c574	1501	*/
AnnaBridge	145:64910690c574	1502	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	145:64910690c574	1503	{
AnnaBridge	145:64910690c574	1504	SET_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	145:64910690c574	1505	}
AnnaBridge	145:64910690c574	1506
AnnaBridge	145:64910690c574	1507	/**
AnnaBridge	145:64910690c574	1508	* @brief Unfreeze APB2 peripherals
AnnaBridge	145:64910690c574	1509	* @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1510	* DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1511	* DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1512	* DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
AnnaBridge	145:64910690c574	1513	* DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
AnnaBridge	145:64910690c574	1514	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1515	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
AnnaBridge	145:64910690c574	1516	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
AnnaBridge	145:64910690c574	1517	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
AnnaBridge	145:64910690c574	1518	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
AnnaBridge	145:64910690c574	1519	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
AnnaBridge	145:64910690c574	1520	*
AnnaBridge	145:64910690c574	1521	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1522	* @retval None
AnnaBridge	145:64910690c574	1523	*/
AnnaBridge	145:64910690c574	1524	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	145:64910690c574	1525	{
AnnaBridge	145:64910690c574	1526	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	145:64910690c574	1527	}
AnnaBridge	145:64910690c574	1528	/**
AnnaBridge	145:64910690c574	1529	* @}
AnnaBridge	145:64910690c574	1530	*/
AnnaBridge	145:64910690c574	1531
AnnaBridge	145:64910690c574	1532	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
AnnaBridge	145:64910690c574	1533	* @{
AnnaBridge	145:64910690c574	1534	*/
AnnaBridge	145:64910690c574	1535
AnnaBridge	145:64910690c574	1536	/**
AnnaBridge	145:64910690c574	1537	* @brief Set FLASH Latency
AnnaBridge	145:64910690c574	1538	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
AnnaBridge	145:64910690c574	1539	* @param Latency This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1540	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	145:64910690c574	1541	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	145:64910690c574	1542	* @arg @ref LL_FLASH_LATENCY_2
AnnaBridge	145:64910690c574	1543	* @arg @ref LL_FLASH_LATENCY_3
AnnaBridge	145:64910690c574	1544	* @arg @ref LL_FLASH_LATENCY_4
AnnaBridge	145:64910690c574	1545	* @arg @ref LL_FLASH_LATENCY_5
AnnaBridge	145:64910690c574	1546	* @arg @ref LL_FLASH_LATENCY_6
AnnaBridge	145:64910690c574	1547	* @arg @ref LL_FLASH_LATENCY_7
AnnaBridge	145:64910690c574	1548	* @arg @ref LL_FLASH_LATENCY_8
AnnaBridge	145:64910690c574	1549	* @arg @ref LL_FLASH_LATENCY_9
AnnaBridge	145:64910690c574	1550	* @arg @ref LL_FLASH_LATENCY_10
AnnaBridge	145:64910690c574	1551	* @arg @ref LL_FLASH_LATENCY_11
AnnaBridge	145:64910690c574	1552	* @arg @ref LL_FLASH_LATENCY_12
AnnaBridge	145:64910690c574	1553	* @arg @ref LL_FLASH_LATENCY_13
AnnaBridge	145:64910690c574	1554	* @arg @ref LL_FLASH_LATENCY_14
AnnaBridge	145:64910690c574	1555	* @arg @ref LL_FLASH_LATENCY_15
AnnaBridge	145:64910690c574	1556	* @retval None
AnnaBridge	145:64910690c574	1557	*/
AnnaBridge	145:64910690c574	1558	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
AnnaBridge	145:64910690c574	1559	{
AnnaBridge	145:64910690c574	1560	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
AnnaBridge	145:64910690c574	1561	}
AnnaBridge	145:64910690c574	1562
AnnaBridge	145:64910690c574	1563	/**
AnnaBridge	145:64910690c574	1564	* @brief Get FLASH Latency
AnnaBridge	145:64910690c574	1565	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
AnnaBridge	145:64910690c574	1566	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1567	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	145:64910690c574	1568	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	145:64910690c574	1569	* @arg @ref LL_FLASH_LATENCY_2
AnnaBridge	145:64910690c574	1570	* @arg @ref LL_FLASH_LATENCY_3
AnnaBridge	145:64910690c574	1571	* @arg @ref LL_FLASH_LATENCY_4
AnnaBridge	145:64910690c574	1572	* @arg @ref LL_FLASH_LATENCY_5
AnnaBridge	145:64910690c574	1573	* @arg @ref LL_FLASH_LATENCY_6
AnnaBridge	145:64910690c574	1574	* @arg @ref LL_FLASH_LATENCY_7
AnnaBridge	145:64910690c574	1575	* @arg @ref LL_FLASH_LATENCY_8
AnnaBridge	145:64910690c574	1576	* @arg @ref LL_FLASH_LATENCY_9
AnnaBridge	145:64910690c574	1577	* @arg @ref LL_FLASH_LATENCY_10
AnnaBridge	145:64910690c574	1578	* @arg @ref LL_FLASH_LATENCY_11
AnnaBridge	145:64910690c574	1579	* @arg @ref LL_FLASH_LATENCY_12
AnnaBridge	145:64910690c574	1580	* @arg @ref LL_FLASH_LATENCY_13
AnnaBridge	145:64910690c574	1581	* @arg @ref LL_FLASH_LATENCY_14
AnnaBridge	145:64910690c574	1582	* @arg @ref LL_FLASH_LATENCY_15
AnnaBridge	145:64910690c574	1583	*/
AnnaBridge	145:64910690c574	1584	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
AnnaBridge	145:64910690c574	1585	{
AnnaBridge	145:64910690c574	1586	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
AnnaBridge	145:64910690c574	1587	}
AnnaBridge	145:64910690c574	1588
AnnaBridge	145:64910690c574	1589	/**
AnnaBridge	145:64910690c574	1590	* @brief Enable Prefetch
AnnaBridge	145:64910690c574	1591	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
AnnaBridge	145:64910690c574	1592	* @retval None
AnnaBridge	145:64910690c574	1593	*/
AnnaBridge	145:64910690c574	1594	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
AnnaBridge	145:64910690c574	1595	{
AnnaBridge	145:64910690c574	1596	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
AnnaBridge	145:64910690c574	1597	}
AnnaBridge	145:64910690c574	1598
AnnaBridge	145:64910690c574	1599	/**
AnnaBridge	145:64910690c574	1600	* @brief Disable Prefetch
AnnaBridge	145:64910690c574	1601	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
AnnaBridge	145:64910690c574	1602	* @retval None
AnnaBridge	145:64910690c574	1603	*/
AnnaBridge	145:64910690c574	1604	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
AnnaBridge	145:64910690c574	1605	{
AnnaBridge	145:64910690c574	1606	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
AnnaBridge	145:64910690c574	1607	}
AnnaBridge	145:64910690c574	1608
AnnaBridge	145:64910690c574	1609	/**
AnnaBridge	145:64910690c574	1610	* @brief Check if Prefetch buffer is enabled
AnnaBridge	145:64910690c574	1611	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
AnnaBridge	145:64910690c574	1612	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1613	*/
AnnaBridge	145:64910690c574	1614	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
AnnaBridge	145:64910690c574	1615	{
AnnaBridge	145:64910690c574	1616	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
AnnaBridge	145:64910690c574	1617	}
AnnaBridge	145:64910690c574	1618
AnnaBridge	145:64910690c574	1619	/**
AnnaBridge	145:64910690c574	1620	* @brief Enable Instruction cache
AnnaBridge	145:64910690c574	1621	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
AnnaBridge	145:64910690c574	1622	* @retval None
AnnaBridge	145:64910690c574	1623	*/
AnnaBridge	145:64910690c574	1624	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
AnnaBridge	145:64910690c574	1625	{
AnnaBridge	145:64910690c574	1626	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
AnnaBridge	145:64910690c574	1627	}
AnnaBridge	145:64910690c574	1628
AnnaBridge	145:64910690c574	1629	/**
AnnaBridge	145:64910690c574	1630	* @brief Disable Instruction cache
AnnaBridge	145:64910690c574	1631	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
AnnaBridge	145:64910690c574	1632	* @retval None
AnnaBridge	145:64910690c574	1633	*/
AnnaBridge	145:64910690c574	1634	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
AnnaBridge	145:64910690c574	1635	{
AnnaBridge	145:64910690c574	1636	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
AnnaBridge	145:64910690c574	1637	}
AnnaBridge	145:64910690c574	1638
AnnaBridge	145:64910690c574	1639	/**
AnnaBridge	145:64910690c574	1640	* @brief Enable Data cache
AnnaBridge	145:64910690c574	1641	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
AnnaBridge	145:64910690c574	1642	* @retval None
AnnaBridge	145:64910690c574	1643	*/
AnnaBridge	145:64910690c574	1644	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
AnnaBridge	145:64910690c574	1645	{
AnnaBridge	145:64910690c574	1646	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
AnnaBridge	145:64910690c574	1647	}
AnnaBridge	145:64910690c574	1648
AnnaBridge	145:64910690c574	1649	/**
AnnaBridge	145:64910690c574	1650	* @brief Disable Data cache
AnnaBridge	145:64910690c574	1651	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
AnnaBridge	145:64910690c574	1652	* @retval None
AnnaBridge	145:64910690c574	1653	*/
AnnaBridge	145:64910690c574	1654	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
AnnaBridge	145:64910690c574	1655	{
AnnaBridge	145:64910690c574	1656	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
AnnaBridge	145:64910690c574	1657	}
AnnaBridge	145:64910690c574	1658
AnnaBridge	145:64910690c574	1659	/**
AnnaBridge	145:64910690c574	1660	* @brief Enable Instruction cache reset
AnnaBridge	145:64910690c574	1661	* @note bit can be written only when the instruction cache is disabled
AnnaBridge	145:64910690c574	1662	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
AnnaBridge	145:64910690c574	1663	* @retval None
AnnaBridge	145:64910690c574	1664	*/
AnnaBridge	145:64910690c574	1665	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
AnnaBridge	145:64910690c574	1666	{
AnnaBridge	145:64910690c574	1667	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
AnnaBridge	145:64910690c574	1668	}
AnnaBridge	145:64910690c574	1669
AnnaBridge	145:64910690c574	1670	/**
AnnaBridge	145:64910690c574	1671	* @brief Disable Instruction cache reset
AnnaBridge	145:64910690c574	1672	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
AnnaBridge	145:64910690c574	1673	* @retval None
AnnaBridge	145:64910690c574	1674	*/
AnnaBridge	145:64910690c574	1675	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
AnnaBridge	145:64910690c574	1676	{
AnnaBridge	145:64910690c574	1677	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
AnnaBridge	145:64910690c574	1678	}
AnnaBridge	145:64910690c574	1679
AnnaBridge	145:64910690c574	1680	/**
AnnaBridge	145:64910690c574	1681	* @brief Enable Data cache reset
AnnaBridge	145:64910690c574	1682	* @note bit can be written only when the data cache is disabled
AnnaBridge	145:64910690c574	1683	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
AnnaBridge	145:64910690c574	1684	* @retval None
AnnaBridge	145:64910690c574	1685	*/
AnnaBridge	145:64910690c574	1686	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
AnnaBridge	145:64910690c574	1687	{
AnnaBridge	145:64910690c574	1688	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
AnnaBridge	145:64910690c574	1689	}
AnnaBridge	145:64910690c574	1690
AnnaBridge	145:64910690c574	1691	/**
AnnaBridge	145:64910690c574	1692	* @brief Disable Data cache reset
AnnaBridge	145:64910690c574	1693	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
AnnaBridge	145:64910690c574	1694	* @retval None
AnnaBridge	145:64910690c574	1695	*/
AnnaBridge	145:64910690c574	1696	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
AnnaBridge	145:64910690c574	1697	{
AnnaBridge	145:64910690c574	1698	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
AnnaBridge	145:64910690c574	1699	}
AnnaBridge	145:64910690c574	1700
AnnaBridge	145:64910690c574	1701
AnnaBridge	145:64910690c574	1702	/**
AnnaBridge	145:64910690c574	1703	* @}
AnnaBridge	145:64910690c574	1704	*/
AnnaBridge	145:64910690c574	1705
AnnaBridge	145:64910690c574	1706	/**
AnnaBridge	145:64910690c574	1707	* @}
AnnaBridge	145:64910690c574	1708	*/
AnnaBridge	145:64910690c574	1709
AnnaBridge	145:64910690c574	1710	/**
AnnaBridge	145:64910690c574	1711	* @}
AnnaBridge	145:64910690c574	1712	*/
AnnaBridge	145:64910690c574	1713
AnnaBridge	145:64910690c574	1714	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
AnnaBridge	145:64910690c574	1715
AnnaBridge	145:64910690c574	1716	/**
AnnaBridge	145:64910690c574	1717	* @}
AnnaBridge	145:64910690c574	1718	*/
AnnaBridge	145:64910690c574	1719
AnnaBridge	145:64910690c574	1720	#ifdef __cplusplus
AnnaBridge	145:64910690c574	1721	}
AnnaBridge	145:64910690c574	1722	#endif
AnnaBridge	145:64910690c574	1723
AnnaBridge	145:64910690c574	1724	#endif /* __STM32F4xx_LL_SYSTEM_H */
AnnaBridge	145:64910690c574	1725
AnnaBridge	145:64910690c574	1726	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/