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TARGET_STEVAL_3DP001V1/TOOLCHAIN_IAR/stm32f4xx_ll_pwr.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 145:64910690c574 | 1 | /** |
| AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
| AnnaBridge | 145:64910690c574 | 3 | * @file stm32f4xx_ll_pwr.h |
| AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
| AnnaBridge | 145:64910690c574 | 5 | * @brief Header file of PWR LL module. |
| AnnaBridge | 145:64910690c574 | 6 | ****************************************************************************** |
| AnnaBridge | 145:64910690c574 | 7 | * @attention |
| AnnaBridge | 145:64910690c574 | 8 | * |
| AnnaBridge | 145:64910690c574 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 145:64910690c574 | 10 | * |
| AnnaBridge | 145:64910690c574 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 145:64910690c574 | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 145:64910690c574 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 145:64910690c574 | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 145:64910690c574 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 145:64910690c574 | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 145:64910690c574 | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 145:64910690c574 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 145:64910690c574 | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 145:64910690c574 | 20 | * without specific prior written permission. |
| AnnaBridge | 145:64910690c574 | 21 | * |
| AnnaBridge | 145:64910690c574 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 145:64910690c574 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 145:64910690c574 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 145:64910690c574 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 145:64910690c574 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 145:64910690c574 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 145:64910690c574 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 145:64910690c574 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 145:64910690c574 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 145:64910690c574 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 145:64910690c574 | 32 | * |
| AnnaBridge | 145:64910690c574 | 33 | ****************************************************************************** |
| AnnaBridge | 145:64910690c574 | 34 | */ |
| AnnaBridge | 145:64910690c574 | 35 | |
| AnnaBridge | 145:64910690c574 | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 37 | #ifndef __STM32F4xx_LL_PWR_H |
| AnnaBridge | 145:64910690c574 | 38 | #define __STM32F4xx_LL_PWR_H |
| AnnaBridge | 145:64910690c574 | 39 | |
| AnnaBridge | 145:64910690c574 | 40 | #ifdef __cplusplus |
| AnnaBridge | 145:64910690c574 | 41 | extern "C" { |
| AnnaBridge | 145:64910690c574 | 42 | #endif |
| AnnaBridge | 145:64910690c574 | 43 | |
| AnnaBridge | 145:64910690c574 | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 45 | #include "stm32f4xx.h" |
| AnnaBridge | 145:64910690c574 | 46 | |
| AnnaBridge | 145:64910690c574 | 47 | /** @addtogroup STM32F4xx_LL_Driver |
| AnnaBridge | 145:64910690c574 | 48 | * @{ |
| AnnaBridge | 145:64910690c574 | 49 | */ |
| AnnaBridge | 145:64910690c574 | 50 | |
| AnnaBridge | 145:64910690c574 | 51 | #if defined(PWR) |
| AnnaBridge | 145:64910690c574 | 52 | |
| AnnaBridge | 145:64910690c574 | 53 | /** @defgroup PWR_LL PWR |
| AnnaBridge | 145:64910690c574 | 54 | * @{ |
| AnnaBridge | 145:64910690c574 | 55 | */ |
| AnnaBridge | 145:64910690c574 | 56 | |
| AnnaBridge | 145:64910690c574 | 57 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 58 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 59 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 60 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 61 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 62 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 63 | /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants |
| AnnaBridge | 145:64910690c574 | 64 | * @{ |
| AnnaBridge | 145:64910690c574 | 65 | */ |
| AnnaBridge | 145:64910690c574 | 66 | |
| AnnaBridge | 145:64910690c574 | 67 | /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines |
| AnnaBridge | 145:64910690c574 | 68 | * @brief Flags defines which can be used with LL_PWR_WriteReg function |
| AnnaBridge | 145:64910690c574 | 69 | * @{ |
| AnnaBridge | 145:64910690c574 | 70 | */ |
| AnnaBridge | 145:64910690c574 | 71 | #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ |
| AnnaBridge | 145:64910690c574 | 72 | #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ |
| AnnaBridge | 145:64910690c574 | 73 | /** |
| AnnaBridge | 145:64910690c574 | 74 | * @} |
| AnnaBridge | 145:64910690c574 | 75 | */ |
| AnnaBridge | 145:64910690c574 | 76 | |
| AnnaBridge | 145:64910690c574 | 77 | /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 145:64910690c574 | 78 | * @brief Flags defines which can be used with LL_PWR_ReadReg function |
| AnnaBridge | 145:64910690c574 | 79 | * @{ |
| AnnaBridge | 145:64910690c574 | 80 | */ |
| AnnaBridge | 145:64910690c574 | 81 | #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ |
| AnnaBridge | 145:64910690c574 | 82 | #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ |
| AnnaBridge | 145:64910690c574 | 83 | #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ |
| AnnaBridge | 145:64910690c574 | 84 | #define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */ |
| AnnaBridge | 145:64910690c574 | 85 | #if defined(PWR_CSR_EWUP) |
| AnnaBridge | 145:64910690c574 | 86 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */ |
| AnnaBridge | 145:64910690c574 | 87 | #elif defined(PWR_CSR_EWUP1) |
| AnnaBridge | 145:64910690c574 | 88 | #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ |
| AnnaBridge | 145:64910690c574 | 89 | #endif /* PWR_CSR_EWUP */ |
| AnnaBridge | 145:64910690c574 | 90 | #if defined(PWR_CSR_EWUP2) |
| AnnaBridge | 145:64910690c574 | 91 | #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ |
| AnnaBridge | 145:64910690c574 | 92 | #endif /* PWR_CSR_EWUP2 */ |
| AnnaBridge | 145:64910690c574 | 93 | #if defined(PWR_CSR_EWUP3) |
| AnnaBridge | 145:64910690c574 | 94 | #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ |
| AnnaBridge | 145:64910690c574 | 95 | #endif /* PWR_CSR_EWUP3 */ |
| AnnaBridge | 145:64910690c574 | 96 | /** |
| AnnaBridge | 145:64910690c574 | 97 | * @} |
| AnnaBridge | 145:64910690c574 | 98 | */ |
| AnnaBridge | 145:64910690c574 | 99 | |
| AnnaBridge | 145:64910690c574 | 100 | /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage |
| AnnaBridge | 145:64910690c574 | 101 | * @{ |
| AnnaBridge | 145:64910690c574 | 102 | */ |
| AnnaBridge | 145:64910690c574 | 103 | #if defined(PWR_CR_VOS_0) |
| AnnaBridge | 145:64910690c574 | 104 | #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0) |
| AnnaBridge | 145:64910690c574 | 105 | #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) |
| AnnaBridge | 145:64910690c574 | 106 | #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */ |
| AnnaBridge | 145:64910690c574 | 107 | #else |
| AnnaBridge | 145:64910690c574 | 108 | #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS) |
| AnnaBridge | 145:64910690c574 | 109 | #define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U |
| AnnaBridge | 145:64910690c574 | 110 | #endif /* PWR_CR_VOS_0 */ |
| AnnaBridge | 145:64910690c574 | 111 | /** |
| AnnaBridge | 145:64910690c574 | 112 | * @} |
| AnnaBridge | 145:64910690c574 | 113 | */ |
| AnnaBridge | 145:64910690c574 | 114 | |
| AnnaBridge | 145:64910690c574 | 115 | /** @defgroup PWR_LL_EC_MODE_PWR Mode Power |
| AnnaBridge | 145:64910690c574 | 116 | * @{ |
| AnnaBridge | 145:64910690c574 | 117 | */ |
| AnnaBridge | 145:64910690c574 | 118 | #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ |
| AnnaBridge | 145:64910690c574 | 119 | #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ |
| AnnaBridge | 145:64910690c574 | 120 | #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) |
| AnnaBridge | 145:64910690c574 | 121 | #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */ |
| AnnaBridge | 145:64910690c574 | 122 | #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */ |
| AnnaBridge | 145:64910690c574 | 123 | #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ |
| AnnaBridge | 145:64910690c574 | 124 | #if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) |
| AnnaBridge | 145:64910690c574 | 125 | #define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */ |
| AnnaBridge | 145:64910690c574 | 126 | #define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */ |
| AnnaBridge | 145:64910690c574 | 127 | #endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */ |
| AnnaBridge | 145:64910690c574 | 128 | #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ |
| AnnaBridge | 145:64910690c574 | 129 | /** |
| AnnaBridge | 145:64910690c574 | 130 | * @} |
| AnnaBridge | 145:64910690c574 | 131 | */ |
| AnnaBridge | 145:64910690c574 | 132 | |
| AnnaBridge | 145:64910690c574 | 133 | /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode |
| AnnaBridge | 145:64910690c574 | 134 | * @{ |
| AnnaBridge | 145:64910690c574 | 135 | */ |
| AnnaBridge | 145:64910690c574 | 136 | #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ |
| AnnaBridge | 145:64910690c574 | 137 | #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ |
| AnnaBridge | 145:64910690c574 | 138 | /** |
| AnnaBridge | 145:64910690c574 | 139 | * @} |
| AnnaBridge | 145:64910690c574 | 140 | */ |
| AnnaBridge | 145:64910690c574 | 141 | |
| AnnaBridge | 145:64910690c574 | 142 | /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level |
| AnnaBridge | 145:64910690c574 | 143 | * @{ |
| AnnaBridge | 145:64910690c574 | 144 | */ |
| AnnaBridge | 145:64910690c574 | 145 | #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ |
| AnnaBridge | 145:64910690c574 | 146 | #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ |
| AnnaBridge | 145:64910690c574 | 147 | #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ |
| AnnaBridge | 145:64910690c574 | 148 | #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ |
| AnnaBridge | 145:64910690c574 | 149 | #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ |
| AnnaBridge | 145:64910690c574 | 150 | #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ |
| AnnaBridge | 145:64910690c574 | 151 | #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ |
| AnnaBridge | 145:64910690c574 | 152 | #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ |
| AnnaBridge | 145:64910690c574 | 153 | /** |
| AnnaBridge | 145:64910690c574 | 154 | * @} |
| AnnaBridge | 145:64910690c574 | 155 | */ |
| AnnaBridge | 145:64910690c574 | 156 | /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins |
| AnnaBridge | 145:64910690c574 | 157 | * @{ |
| AnnaBridge | 145:64910690c574 | 158 | */ |
| AnnaBridge | 145:64910690c574 | 159 | #if defined(PWR_CSR_EWUP) |
| AnnaBridge | 145:64910690c574 | 160 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */ |
| AnnaBridge | 145:64910690c574 | 161 | #endif /* PWR_CSR_EWUP */ |
| AnnaBridge | 145:64910690c574 | 162 | #if defined(PWR_CSR_EWUP1) |
| AnnaBridge | 145:64910690c574 | 163 | #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ |
| AnnaBridge | 145:64910690c574 | 164 | #endif /* PWR_CSR_EWUP1 */ |
| AnnaBridge | 145:64910690c574 | 165 | #if defined(PWR_CSR_EWUP2) |
| AnnaBridge | 145:64910690c574 | 166 | #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */ |
| AnnaBridge | 145:64910690c574 | 167 | #endif /* PWR_CSR_EWUP2 */ |
| AnnaBridge | 145:64910690c574 | 168 | #if defined(PWR_CSR_EWUP3) |
| AnnaBridge | 145:64910690c574 | 169 | #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */ |
| AnnaBridge | 145:64910690c574 | 170 | #endif /* PWR_CSR_EWUP3 */ |
| AnnaBridge | 145:64910690c574 | 171 | /** |
| AnnaBridge | 145:64910690c574 | 172 | * @} |
| AnnaBridge | 145:64910690c574 | 173 | */ |
| AnnaBridge | 145:64910690c574 | 174 | |
| AnnaBridge | 145:64910690c574 | 175 | /** |
| AnnaBridge | 145:64910690c574 | 176 | * @} |
| AnnaBridge | 145:64910690c574 | 177 | */ |
| AnnaBridge | 145:64910690c574 | 178 | |
| AnnaBridge | 145:64910690c574 | 179 | |
| AnnaBridge | 145:64910690c574 | 180 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 181 | /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros |
| AnnaBridge | 145:64910690c574 | 182 | * @{ |
| AnnaBridge | 145:64910690c574 | 183 | */ |
| AnnaBridge | 145:64910690c574 | 184 | |
| AnnaBridge | 145:64910690c574 | 185 | /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros |
| AnnaBridge | 145:64910690c574 | 186 | * @{ |
| AnnaBridge | 145:64910690c574 | 187 | */ |
| AnnaBridge | 145:64910690c574 | 188 | |
| AnnaBridge | 145:64910690c574 | 189 | /** |
| AnnaBridge | 145:64910690c574 | 190 | * @brief Write a value in PWR register |
| AnnaBridge | 145:64910690c574 | 191 | * @param __REG__ Register to be written |
| AnnaBridge | 145:64910690c574 | 192 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 145:64910690c574 | 193 | * @retval None |
| AnnaBridge | 145:64910690c574 | 194 | */ |
| AnnaBridge | 145:64910690c574 | 195 | #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) |
| AnnaBridge | 145:64910690c574 | 196 | |
| AnnaBridge | 145:64910690c574 | 197 | /** |
| AnnaBridge | 145:64910690c574 | 198 | * @brief Read a value in PWR register |
| AnnaBridge | 145:64910690c574 | 199 | * @param __REG__ Register to be read |
| AnnaBridge | 145:64910690c574 | 200 | * @retval Register value |
| AnnaBridge | 145:64910690c574 | 201 | */ |
| AnnaBridge | 145:64910690c574 | 202 | #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) |
| AnnaBridge | 145:64910690c574 | 203 | /** |
| AnnaBridge | 145:64910690c574 | 204 | * @} |
| AnnaBridge | 145:64910690c574 | 205 | */ |
| AnnaBridge | 145:64910690c574 | 206 | |
| AnnaBridge | 145:64910690c574 | 207 | /** |
| AnnaBridge | 145:64910690c574 | 208 | * @} |
| AnnaBridge | 145:64910690c574 | 209 | */ |
| AnnaBridge | 145:64910690c574 | 210 | |
| AnnaBridge | 145:64910690c574 | 211 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 212 | /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions |
| AnnaBridge | 145:64910690c574 | 213 | * @{ |
| AnnaBridge | 145:64910690c574 | 214 | */ |
| AnnaBridge | 145:64910690c574 | 215 | |
| AnnaBridge | 145:64910690c574 | 216 | /** @defgroup PWR_LL_EF_Configuration Configuration |
| AnnaBridge | 145:64910690c574 | 217 | * @{ |
| AnnaBridge | 145:64910690c574 | 218 | */ |
| AnnaBridge | 145:64910690c574 | 219 | #if defined(PWR_CR_FISSR) |
| AnnaBridge | 145:64910690c574 | 220 | /** |
| AnnaBridge | 145:64910690c574 | 221 | * @brief Enable FLASH interface STOP while system Run is ON |
| AnnaBridge | 145:64910690c574 | 222 | * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP |
| AnnaBridge | 145:64910690c574 | 223 | * @note This mode is enabled only with STOP low power mode. |
| AnnaBridge | 145:64910690c574 | 224 | * @retval None |
| AnnaBridge | 145:64910690c574 | 225 | */ |
| AnnaBridge | 145:64910690c574 | 226 | __STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void) |
| AnnaBridge | 145:64910690c574 | 227 | { |
| AnnaBridge | 145:64910690c574 | 228 | SET_BIT(PWR->CR, PWR_CR_FISSR); |
| AnnaBridge | 145:64910690c574 | 229 | } |
| AnnaBridge | 145:64910690c574 | 230 | |
| AnnaBridge | 145:64910690c574 | 231 | /** |
| AnnaBridge | 145:64910690c574 | 232 | * @brief Disable FLASH Interface STOP while system Run is ON |
| AnnaBridge | 145:64910690c574 | 233 | * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP |
| AnnaBridge | 145:64910690c574 | 234 | * @retval None |
| AnnaBridge | 145:64910690c574 | 235 | */ |
| AnnaBridge | 145:64910690c574 | 236 | __STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void) |
| AnnaBridge | 145:64910690c574 | 237 | { |
| AnnaBridge | 145:64910690c574 | 238 | CLEAR_BIT(PWR->CR, PWR_CR_FISSR); |
| AnnaBridge | 145:64910690c574 | 239 | } |
| AnnaBridge | 145:64910690c574 | 240 | |
| AnnaBridge | 145:64910690c574 | 241 | /** |
| AnnaBridge | 145:64910690c574 | 242 | * @brief Check if FLASH Interface STOP while system Run feature is enabled |
| AnnaBridge | 145:64910690c574 | 243 | * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP |
| AnnaBridge | 145:64910690c574 | 244 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 245 | */ |
| AnnaBridge | 145:64910690c574 | 246 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void) |
| AnnaBridge | 145:64910690c574 | 247 | { |
| AnnaBridge | 145:64910690c574 | 248 | return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR)); |
| AnnaBridge | 145:64910690c574 | 249 | } |
| AnnaBridge | 145:64910690c574 | 250 | #endif /* PWR_CR_FISSR */ |
| AnnaBridge | 145:64910690c574 | 251 | |
| AnnaBridge | 145:64910690c574 | 252 | #if defined(PWR_CR_FMSSR) |
| AnnaBridge | 145:64910690c574 | 253 | /** |
| AnnaBridge | 145:64910690c574 | 254 | * @brief Enable FLASH Memory STOP while system Run is ON |
| AnnaBridge | 145:64910690c574 | 255 | * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP |
| AnnaBridge | 145:64910690c574 | 256 | * @note This mode is enabled only with STOP low power mode. |
| AnnaBridge | 145:64910690c574 | 257 | * @retval None |
| AnnaBridge | 145:64910690c574 | 258 | */ |
| AnnaBridge | 145:64910690c574 | 259 | __STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void) |
| AnnaBridge | 145:64910690c574 | 260 | { |
| AnnaBridge | 145:64910690c574 | 261 | SET_BIT(PWR->CR, PWR_CR_FMSSR); |
| AnnaBridge | 145:64910690c574 | 262 | } |
| AnnaBridge | 145:64910690c574 | 263 | |
| AnnaBridge | 145:64910690c574 | 264 | /** |
| AnnaBridge | 145:64910690c574 | 265 | * @brief Disable FLASH Memory STOP while system Run is ON |
| AnnaBridge | 145:64910690c574 | 266 | * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP |
| AnnaBridge | 145:64910690c574 | 267 | * @retval None |
| AnnaBridge | 145:64910690c574 | 268 | */ |
| AnnaBridge | 145:64910690c574 | 269 | __STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void) |
| AnnaBridge | 145:64910690c574 | 270 | { |
| AnnaBridge | 145:64910690c574 | 271 | CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); |
| AnnaBridge | 145:64910690c574 | 272 | } |
| AnnaBridge | 145:64910690c574 | 273 | |
| AnnaBridge | 145:64910690c574 | 274 | /** |
| AnnaBridge | 145:64910690c574 | 275 | * @brief Check if FLASH Memory STOP while system Run feature is enabled |
| AnnaBridge | 145:64910690c574 | 276 | * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP |
| AnnaBridge | 145:64910690c574 | 277 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 278 | */ |
| AnnaBridge | 145:64910690c574 | 279 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void) |
| AnnaBridge | 145:64910690c574 | 280 | { |
| AnnaBridge | 145:64910690c574 | 281 | return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR)); |
| AnnaBridge | 145:64910690c574 | 282 | } |
| AnnaBridge | 145:64910690c574 | 283 | #endif /* PWR_CR_FMSSR */ |
| AnnaBridge | 145:64910690c574 | 284 | #if defined(PWR_CR_UDEN) |
| AnnaBridge | 145:64910690c574 | 285 | /** |
| AnnaBridge | 145:64910690c574 | 286 | * @brief Enable Under Drive Mode |
| AnnaBridge | 145:64910690c574 | 287 | * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode |
| AnnaBridge | 145:64910690c574 | 288 | * @note This mode is enabled only with STOP low power mode. |
| AnnaBridge | 145:64910690c574 | 289 | * In this mode, the 1.2V domain is preserved in reduced leakage mode. This |
| AnnaBridge | 145:64910690c574 | 290 | * mode is only available when the main Regulator or the low power Regulator |
| AnnaBridge | 145:64910690c574 | 291 | * is in low voltage mode. |
| AnnaBridge | 145:64910690c574 | 292 | * @note If the Under-drive mode was enabled, it is automatically disabled after |
| AnnaBridge | 145:64910690c574 | 293 | * exiting Stop mode. |
| AnnaBridge | 145:64910690c574 | 294 | * When the voltage Regulator operates in Under-drive mode, an additional |
| AnnaBridge | 145:64910690c574 | 295 | * startup delay is induced when waking up from Stop mode. |
| AnnaBridge | 145:64910690c574 | 296 | * @retval None |
| AnnaBridge | 145:64910690c574 | 297 | */ |
| AnnaBridge | 145:64910690c574 | 298 | __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) |
| AnnaBridge | 145:64910690c574 | 299 | { |
| AnnaBridge | 145:64910690c574 | 300 | SET_BIT(PWR->CR, PWR_CR_UDEN); |
| AnnaBridge | 145:64910690c574 | 301 | } |
| AnnaBridge | 145:64910690c574 | 302 | |
| AnnaBridge | 145:64910690c574 | 303 | /** |
| AnnaBridge | 145:64910690c574 | 304 | * @brief Disable Under Drive Mode |
| AnnaBridge | 145:64910690c574 | 305 | * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode |
| AnnaBridge | 145:64910690c574 | 306 | * @retval None |
| AnnaBridge | 145:64910690c574 | 307 | */ |
| AnnaBridge | 145:64910690c574 | 308 | __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) |
| AnnaBridge | 145:64910690c574 | 309 | { |
| AnnaBridge | 145:64910690c574 | 310 | CLEAR_BIT(PWR->CR, PWR_CR_UDEN); |
| AnnaBridge | 145:64910690c574 | 311 | } |
| AnnaBridge | 145:64910690c574 | 312 | |
| AnnaBridge | 145:64910690c574 | 313 | /** |
| AnnaBridge | 145:64910690c574 | 314 | * @brief Check if Under Drive Mode is enabled |
| AnnaBridge | 145:64910690c574 | 315 | * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode |
| AnnaBridge | 145:64910690c574 | 316 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 317 | */ |
| AnnaBridge | 145:64910690c574 | 318 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) |
| AnnaBridge | 145:64910690c574 | 319 | { |
| AnnaBridge | 145:64910690c574 | 320 | return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN)); |
| AnnaBridge | 145:64910690c574 | 321 | } |
| AnnaBridge | 145:64910690c574 | 322 | #endif /* PWR_CR_UDEN */ |
| AnnaBridge | 145:64910690c574 | 323 | |
| AnnaBridge | 145:64910690c574 | 324 | #if defined(PWR_CR_ODSWEN) |
| AnnaBridge | 145:64910690c574 | 325 | /** |
| AnnaBridge | 145:64910690c574 | 326 | * @brief Enable Over drive switching |
| AnnaBridge | 145:64910690c574 | 327 | * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching |
| AnnaBridge | 145:64910690c574 | 328 | * @retval None |
| AnnaBridge | 145:64910690c574 | 329 | */ |
| AnnaBridge | 145:64910690c574 | 330 | __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) |
| AnnaBridge | 145:64910690c574 | 331 | { |
| AnnaBridge | 145:64910690c574 | 332 | SET_BIT(PWR->CR, PWR_CR_ODSWEN); |
| AnnaBridge | 145:64910690c574 | 333 | } |
| AnnaBridge | 145:64910690c574 | 334 | |
| AnnaBridge | 145:64910690c574 | 335 | /** |
| AnnaBridge | 145:64910690c574 | 336 | * @brief Disable Over drive switching |
| AnnaBridge | 145:64910690c574 | 337 | * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching |
| AnnaBridge | 145:64910690c574 | 338 | * @retval None |
| AnnaBridge | 145:64910690c574 | 339 | */ |
| AnnaBridge | 145:64910690c574 | 340 | __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) |
| AnnaBridge | 145:64910690c574 | 341 | { |
| AnnaBridge | 145:64910690c574 | 342 | CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN); |
| AnnaBridge | 145:64910690c574 | 343 | } |
| AnnaBridge | 145:64910690c574 | 344 | |
| AnnaBridge | 145:64910690c574 | 345 | /** |
| AnnaBridge | 145:64910690c574 | 346 | * @brief Check if Over drive switching is enabled |
| AnnaBridge | 145:64910690c574 | 347 | * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching |
| AnnaBridge | 145:64910690c574 | 348 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 349 | */ |
| AnnaBridge | 145:64910690c574 | 350 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) |
| AnnaBridge | 145:64910690c574 | 351 | { |
| AnnaBridge | 145:64910690c574 | 352 | return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN)); |
| AnnaBridge | 145:64910690c574 | 353 | } |
| AnnaBridge | 145:64910690c574 | 354 | #endif /* PWR_CR_ODSWEN */ |
| AnnaBridge | 145:64910690c574 | 355 | #if defined(PWR_CR_ODEN) |
| AnnaBridge | 145:64910690c574 | 356 | /** |
| AnnaBridge | 145:64910690c574 | 357 | * @brief Enable Over drive Mode |
| AnnaBridge | 145:64910690c574 | 358 | * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode |
| AnnaBridge | 145:64910690c574 | 359 | * @retval None |
| AnnaBridge | 145:64910690c574 | 360 | */ |
| AnnaBridge | 145:64910690c574 | 361 | __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) |
| AnnaBridge | 145:64910690c574 | 362 | { |
| AnnaBridge | 145:64910690c574 | 363 | SET_BIT(PWR->CR, PWR_CR_ODEN); |
| AnnaBridge | 145:64910690c574 | 364 | } |
| AnnaBridge | 145:64910690c574 | 365 | |
| AnnaBridge | 145:64910690c574 | 366 | /** |
| AnnaBridge | 145:64910690c574 | 367 | * @brief Disable Over drive Mode |
| AnnaBridge | 145:64910690c574 | 368 | * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode |
| AnnaBridge | 145:64910690c574 | 369 | * @retval None |
| AnnaBridge | 145:64910690c574 | 370 | */ |
| AnnaBridge | 145:64910690c574 | 371 | __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) |
| AnnaBridge | 145:64910690c574 | 372 | { |
| AnnaBridge | 145:64910690c574 | 373 | CLEAR_BIT(PWR->CR, PWR_CR_ODEN); |
| AnnaBridge | 145:64910690c574 | 374 | } |
| AnnaBridge | 145:64910690c574 | 375 | |
| AnnaBridge | 145:64910690c574 | 376 | /** |
| AnnaBridge | 145:64910690c574 | 377 | * @brief Check if Over drive switching is enabled |
| AnnaBridge | 145:64910690c574 | 378 | * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode |
| AnnaBridge | 145:64910690c574 | 379 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 380 | */ |
| AnnaBridge | 145:64910690c574 | 381 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) |
| AnnaBridge | 145:64910690c574 | 382 | { |
| AnnaBridge | 145:64910690c574 | 383 | return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN)); |
| AnnaBridge | 145:64910690c574 | 384 | } |
| AnnaBridge | 145:64910690c574 | 385 | #endif /* PWR_CR_ODEN */ |
| AnnaBridge | 145:64910690c574 | 386 | #if defined(PWR_CR_MRUDS) |
| AnnaBridge | 145:64910690c574 | 387 | /** |
| AnnaBridge | 145:64910690c574 | 388 | * @brief Enable Main Regulator in deepsleep under-drive Mode |
| AnnaBridge | 145:64910690c574 | 389 | * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode |
| AnnaBridge | 145:64910690c574 | 390 | * @retval None |
| AnnaBridge | 145:64910690c574 | 391 | */ |
| AnnaBridge | 145:64910690c574 | 392 | __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void) |
| AnnaBridge | 145:64910690c574 | 393 | { |
| AnnaBridge | 145:64910690c574 | 394 | SET_BIT(PWR->CR, PWR_CR_MRUDS); |
| AnnaBridge | 145:64910690c574 | 395 | } |
| AnnaBridge | 145:64910690c574 | 396 | |
| AnnaBridge | 145:64910690c574 | 397 | /** |
| AnnaBridge | 145:64910690c574 | 398 | * @brief Disable Main Regulator in deepsleep under-drive Mode |
| AnnaBridge | 145:64910690c574 | 399 | * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode |
| AnnaBridge | 145:64910690c574 | 400 | * @retval None |
| AnnaBridge | 145:64910690c574 | 401 | */ |
| AnnaBridge | 145:64910690c574 | 402 | __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void) |
| AnnaBridge | 145:64910690c574 | 403 | { |
| AnnaBridge | 145:64910690c574 | 404 | CLEAR_BIT(PWR->CR, PWR_CR_MRUDS); |
| AnnaBridge | 145:64910690c574 | 405 | } |
| AnnaBridge | 145:64910690c574 | 406 | |
| AnnaBridge | 145:64910690c574 | 407 | /** |
| AnnaBridge | 145:64910690c574 | 408 | * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled |
| AnnaBridge | 145:64910690c574 | 409 | * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode |
| AnnaBridge | 145:64910690c574 | 410 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 411 | */ |
| AnnaBridge | 145:64910690c574 | 412 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void) |
| AnnaBridge | 145:64910690c574 | 413 | { |
| AnnaBridge | 145:64910690c574 | 414 | return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS)); |
| AnnaBridge | 145:64910690c574 | 415 | } |
| AnnaBridge | 145:64910690c574 | 416 | #endif /* PWR_CR_MRUDS */ |
| AnnaBridge | 145:64910690c574 | 417 | |
| AnnaBridge | 145:64910690c574 | 418 | #if defined(PWR_CR_LPUDS) |
| AnnaBridge | 145:64910690c574 | 419 | /** |
| AnnaBridge | 145:64910690c574 | 420 | * @brief Enable Low Power Regulator in deepsleep under-drive Mode |
| AnnaBridge | 145:64910690c574 | 421 | * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode |
| AnnaBridge | 145:64910690c574 | 422 | * @retval None |
| AnnaBridge | 145:64910690c574 | 423 | */ |
| AnnaBridge | 145:64910690c574 | 424 | __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void) |
| AnnaBridge | 145:64910690c574 | 425 | { |
| AnnaBridge | 145:64910690c574 | 426 | SET_BIT(PWR->CR, PWR_CR_LPUDS); |
| AnnaBridge | 145:64910690c574 | 427 | } |
| AnnaBridge | 145:64910690c574 | 428 | |
| AnnaBridge | 145:64910690c574 | 429 | /** |
| AnnaBridge | 145:64910690c574 | 430 | * @brief Disable Low Power Regulator in deepsleep under-drive Mode |
| AnnaBridge | 145:64910690c574 | 431 | * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode |
| AnnaBridge | 145:64910690c574 | 432 | * @retval None |
| AnnaBridge | 145:64910690c574 | 433 | */ |
| AnnaBridge | 145:64910690c574 | 434 | __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void) |
| AnnaBridge | 145:64910690c574 | 435 | { |
| AnnaBridge | 145:64910690c574 | 436 | CLEAR_BIT(PWR->CR, PWR_CR_LPUDS); |
| AnnaBridge | 145:64910690c574 | 437 | } |
| AnnaBridge | 145:64910690c574 | 438 | |
| AnnaBridge | 145:64910690c574 | 439 | /** |
| AnnaBridge | 145:64910690c574 | 440 | * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled |
| AnnaBridge | 145:64910690c574 | 441 | * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode |
| AnnaBridge | 145:64910690c574 | 442 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 443 | */ |
| AnnaBridge | 145:64910690c574 | 444 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void) |
| AnnaBridge | 145:64910690c574 | 445 | { |
| AnnaBridge | 145:64910690c574 | 446 | return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS)); |
| AnnaBridge | 145:64910690c574 | 447 | } |
| AnnaBridge | 145:64910690c574 | 448 | #endif /* PWR_CR_LPUDS */ |
| AnnaBridge | 145:64910690c574 | 449 | |
| AnnaBridge | 145:64910690c574 | 450 | #if defined(PWR_CR_MRLVDS) |
| AnnaBridge | 145:64910690c574 | 451 | /** |
| AnnaBridge | 145:64910690c574 | 452 | * @brief Enable Main Regulator low voltage Mode |
| AnnaBridge | 145:64910690c574 | 453 | * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode |
| AnnaBridge | 145:64910690c574 | 454 | * @retval None |
| AnnaBridge | 145:64910690c574 | 455 | */ |
| AnnaBridge | 145:64910690c574 | 456 | __STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void) |
| AnnaBridge | 145:64910690c574 | 457 | { |
| AnnaBridge | 145:64910690c574 | 458 | SET_BIT(PWR->CR, PWR_CR_MRLVDS); |
| AnnaBridge | 145:64910690c574 | 459 | } |
| AnnaBridge | 145:64910690c574 | 460 | |
| AnnaBridge | 145:64910690c574 | 461 | /** |
| AnnaBridge | 145:64910690c574 | 462 | * @brief Disable Main Regulator low voltage Mode |
| AnnaBridge | 145:64910690c574 | 463 | * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode |
| AnnaBridge | 145:64910690c574 | 464 | * @retval None |
| AnnaBridge | 145:64910690c574 | 465 | */ |
| AnnaBridge | 145:64910690c574 | 466 | __STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void) |
| AnnaBridge | 145:64910690c574 | 467 | { |
| AnnaBridge | 145:64910690c574 | 468 | CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS); |
| AnnaBridge | 145:64910690c574 | 469 | } |
| AnnaBridge | 145:64910690c574 | 470 | |
| AnnaBridge | 145:64910690c574 | 471 | /** |
| AnnaBridge | 145:64910690c574 | 472 | * @brief Check if Main Regulator low voltage Mode is enabled |
| AnnaBridge | 145:64910690c574 | 473 | * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode |
| AnnaBridge | 145:64910690c574 | 474 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 475 | */ |
| AnnaBridge | 145:64910690c574 | 476 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void) |
| AnnaBridge | 145:64910690c574 | 477 | { |
| AnnaBridge | 145:64910690c574 | 478 | return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS)); |
| AnnaBridge | 145:64910690c574 | 479 | } |
| AnnaBridge | 145:64910690c574 | 480 | #endif /* PWR_CR_MRLVDS */ |
| AnnaBridge | 145:64910690c574 | 481 | |
| AnnaBridge | 145:64910690c574 | 482 | #if defined(PWR_CR_LPLVDS) |
| AnnaBridge | 145:64910690c574 | 483 | /** |
| AnnaBridge | 145:64910690c574 | 484 | * @brief Enable Low Power Regulator low voltage Mode |
| AnnaBridge | 145:64910690c574 | 485 | * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode |
| AnnaBridge | 145:64910690c574 | 486 | * @retval None |
| AnnaBridge | 145:64910690c574 | 487 | */ |
| AnnaBridge | 145:64910690c574 | 488 | __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void) |
| AnnaBridge | 145:64910690c574 | 489 | { |
| AnnaBridge | 145:64910690c574 | 490 | SET_BIT(PWR->CR, PWR_CR_LPLVDS); |
| AnnaBridge | 145:64910690c574 | 491 | } |
| AnnaBridge | 145:64910690c574 | 492 | |
| AnnaBridge | 145:64910690c574 | 493 | /** |
| AnnaBridge | 145:64910690c574 | 494 | * @brief Disable Low Power Regulator low voltage Mode |
| AnnaBridge | 145:64910690c574 | 495 | * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode |
| AnnaBridge | 145:64910690c574 | 496 | * @retval None |
| AnnaBridge | 145:64910690c574 | 497 | */ |
| AnnaBridge | 145:64910690c574 | 498 | __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void) |
| AnnaBridge | 145:64910690c574 | 499 | { |
| AnnaBridge | 145:64910690c574 | 500 | CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS); |
| AnnaBridge | 145:64910690c574 | 501 | } |
| AnnaBridge | 145:64910690c574 | 502 | |
| AnnaBridge | 145:64910690c574 | 503 | /** |
| AnnaBridge | 145:64910690c574 | 504 | * @brief Check if Low Power Regulator low voltage Mode is enabled |
| AnnaBridge | 145:64910690c574 | 505 | * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode |
| AnnaBridge | 145:64910690c574 | 506 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 507 | */ |
| AnnaBridge | 145:64910690c574 | 508 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void) |
| AnnaBridge | 145:64910690c574 | 509 | { |
| AnnaBridge | 145:64910690c574 | 510 | return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS)); |
| AnnaBridge | 145:64910690c574 | 511 | } |
| AnnaBridge | 145:64910690c574 | 512 | #endif /* PWR_CR_LPLVDS */ |
| AnnaBridge | 145:64910690c574 | 513 | /** |
| AnnaBridge | 145:64910690c574 | 514 | * @brief Set the main internal Regulator output voltage |
| AnnaBridge | 145:64910690c574 | 515 | * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling |
| AnnaBridge | 145:64910690c574 | 516 | * @param VoltageScaling This parameter can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 517 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) |
| AnnaBridge | 145:64910690c574 | 518 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 145:64910690c574 | 519 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 |
| AnnaBridge | 145:64910690c574 | 520 | * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices |
| AnnaBridge | 145:64910690c574 | 521 | * @retval None |
| AnnaBridge | 145:64910690c574 | 522 | */ |
| AnnaBridge | 145:64910690c574 | 523 | __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) |
| AnnaBridge | 145:64910690c574 | 524 | { |
| AnnaBridge | 145:64910690c574 | 525 | MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); |
| AnnaBridge | 145:64910690c574 | 526 | } |
| AnnaBridge | 145:64910690c574 | 527 | |
| AnnaBridge | 145:64910690c574 | 528 | /** |
| AnnaBridge | 145:64910690c574 | 529 | * @brief Get the main internal Regulator output voltage |
| AnnaBridge | 145:64910690c574 | 530 | * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling |
| AnnaBridge | 145:64910690c574 | 531 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 532 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) |
| AnnaBridge | 145:64910690c574 | 533 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 |
| AnnaBridge | 145:64910690c574 | 534 | * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 |
| AnnaBridge | 145:64910690c574 | 535 | * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices |
| AnnaBridge | 145:64910690c574 | 536 | */ |
| AnnaBridge | 145:64910690c574 | 537 | __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) |
| AnnaBridge | 145:64910690c574 | 538 | { |
| AnnaBridge | 145:64910690c574 | 539 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); |
| AnnaBridge | 145:64910690c574 | 540 | } |
| AnnaBridge | 145:64910690c574 | 541 | /** |
| AnnaBridge | 145:64910690c574 | 542 | * @brief Enable the Flash Power Down in Stop Mode |
| AnnaBridge | 145:64910690c574 | 543 | * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown |
| AnnaBridge | 145:64910690c574 | 544 | * @retval None |
| AnnaBridge | 145:64910690c574 | 545 | */ |
| AnnaBridge | 145:64910690c574 | 546 | __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) |
| AnnaBridge | 145:64910690c574 | 547 | { |
| AnnaBridge | 145:64910690c574 | 548 | SET_BIT(PWR->CR, PWR_CR_FPDS); |
| AnnaBridge | 145:64910690c574 | 549 | } |
| AnnaBridge | 145:64910690c574 | 550 | |
| AnnaBridge | 145:64910690c574 | 551 | /** |
| AnnaBridge | 145:64910690c574 | 552 | * @brief Disable the Flash Power Down in Stop Mode |
| AnnaBridge | 145:64910690c574 | 553 | * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown |
| AnnaBridge | 145:64910690c574 | 554 | * @retval None |
| AnnaBridge | 145:64910690c574 | 555 | */ |
| AnnaBridge | 145:64910690c574 | 556 | __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) |
| AnnaBridge | 145:64910690c574 | 557 | { |
| AnnaBridge | 145:64910690c574 | 558 | CLEAR_BIT(PWR->CR, PWR_CR_FPDS); |
| AnnaBridge | 145:64910690c574 | 559 | } |
| AnnaBridge | 145:64910690c574 | 560 | |
| AnnaBridge | 145:64910690c574 | 561 | /** |
| AnnaBridge | 145:64910690c574 | 562 | * @brief Check if the Flash Power Down in Stop Mode is enabled |
| AnnaBridge | 145:64910690c574 | 563 | * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown |
| AnnaBridge | 145:64910690c574 | 564 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 565 | */ |
| AnnaBridge | 145:64910690c574 | 566 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) |
| AnnaBridge | 145:64910690c574 | 567 | { |
| AnnaBridge | 145:64910690c574 | 568 | return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS)); |
| AnnaBridge | 145:64910690c574 | 569 | } |
| AnnaBridge | 145:64910690c574 | 570 | |
| AnnaBridge | 145:64910690c574 | 571 | /** |
| AnnaBridge | 145:64910690c574 | 572 | * @brief Enable access to the backup domain |
| AnnaBridge | 145:64910690c574 | 573 | * @rmtoll CR DBP LL_PWR_EnableBkUpAccess |
| AnnaBridge | 145:64910690c574 | 574 | * @retval None |
| AnnaBridge | 145:64910690c574 | 575 | */ |
| AnnaBridge | 145:64910690c574 | 576 | __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) |
| AnnaBridge | 145:64910690c574 | 577 | { |
| AnnaBridge | 145:64910690c574 | 578 | SET_BIT(PWR->CR, PWR_CR_DBP); |
| AnnaBridge | 145:64910690c574 | 579 | } |
| AnnaBridge | 145:64910690c574 | 580 | |
| AnnaBridge | 145:64910690c574 | 581 | /** |
| AnnaBridge | 145:64910690c574 | 582 | * @brief Disable access to the backup domain |
| AnnaBridge | 145:64910690c574 | 583 | * @rmtoll CR DBP LL_PWR_DisableBkUpAccess |
| AnnaBridge | 145:64910690c574 | 584 | * @retval None |
| AnnaBridge | 145:64910690c574 | 585 | */ |
| AnnaBridge | 145:64910690c574 | 586 | __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) |
| AnnaBridge | 145:64910690c574 | 587 | { |
| AnnaBridge | 145:64910690c574 | 588 | CLEAR_BIT(PWR->CR, PWR_CR_DBP); |
| AnnaBridge | 145:64910690c574 | 589 | } |
| AnnaBridge | 145:64910690c574 | 590 | |
| AnnaBridge | 145:64910690c574 | 591 | /** |
| AnnaBridge | 145:64910690c574 | 592 | * @brief Check if the backup domain is enabled |
| AnnaBridge | 145:64910690c574 | 593 | * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess |
| AnnaBridge | 145:64910690c574 | 594 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 595 | */ |
| AnnaBridge | 145:64910690c574 | 596 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) |
| AnnaBridge | 145:64910690c574 | 597 | { |
| AnnaBridge | 145:64910690c574 | 598 | return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); |
| AnnaBridge | 145:64910690c574 | 599 | } |
| AnnaBridge | 145:64910690c574 | 600 | /** |
| AnnaBridge | 145:64910690c574 | 601 | * @brief Enable the backup Regulator |
| AnnaBridge | 145:64910690c574 | 602 | * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator |
| AnnaBridge | 145:64910690c574 | 603 | * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. |
| AnnaBridge | 145:64910690c574 | 604 | * The LL_PWR_EnableBkUpAccess() must be called before using this API. |
| AnnaBridge | 145:64910690c574 | 605 | * @retval None |
| AnnaBridge | 145:64910690c574 | 606 | */ |
| AnnaBridge | 145:64910690c574 | 607 | __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) |
| AnnaBridge | 145:64910690c574 | 608 | { |
| AnnaBridge | 145:64910690c574 | 609 | SET_BIT(PWR->CSR, PWR_CSR_BRE); |
| AnnaBridge | 145:64910690c574 | 610 | } |
| AnnaBridge | 145:64910690c574 | 611 | |
| AnnaBridge | 145:64910690c574 | 612 | /** |
| AnnaBridge | 145:64910690c574 | 613 | * @brief Disable the backup Regulator |
| AnnaBridge | 145:64910690c574 | 614 | * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator |
| AnnaBridge | 145:64910690c574 | 615 | * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. |
| AnnaBridge | 145:64910690c574 | 616 | * The LL_PWR_EnableBkUpAccess() must be called before using this API. |
| AnnaBridge | 145:64910690c574 | 617 | * @retval None |
| AnnaBridge | 145:64910690c574 | 618 | */ |
| AnnaBridge | 145:64910690c574 | 619 | __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) |
| AnnaBridge | 145:64910690c574 | 620 | { |
| AnnaBridge | 145:64910690c574 | 621 | CLEAR_BIT(PWR->CSR, PWR_CSR_BRE); |
| AnnaBridge | 145:64910690c574 | 622 | } |
| AnnaBridge | 145:64910690c574 | 623 | |
| AnnaBridge | 145:64910690c574 | 624 | /** |
| AnnaBridge | 145:64910690c574 | 625 | * @brief Check if the backup Regulator is enabled |
| AnnaBridge | 145:64910690c574 | 626 | * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator |
| AnnaBridge | 145:64910690c574 | 627 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 628 | */ |
| AnnaBridge | 145:64910690c574 | 629 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) |
| AnnaBridge | 145:64910690c574 | 630 | { |
| AnnaBridge | 145:64910690c574 | 631 | return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE)); |
| AnnaBridge | 145:64910690c574 | 632 | } |
| AnnaBridge | 145:64910690c574 | 633 | |
| AnnaBridge | 145:64910690c574 | 634 | /** |
| AnnaBridge | 145:64910690c574 | 635 | * @brief Set voltage Regulator mode during deep sleep mode |
| AnnaBridge | 145:64910690c574 | 636 | * @rmtoll CR LPDS LL_PWR_SetRegulModeDS |
| AnnaBridge | 145:64910690c574 | 637 | * @param RegulMode This parameter can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 638 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
| AnnaBridge | 145:64910690c574 | 639 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
| AnnaBridge | 145:64910690c574 | 640 | * @retval None |
| AnnaBridge | 145:64910690c574 | 641 | */ |
| AnnaBridge | 145:64910690c574 | 642 | __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) |
| AnnaBridge | 145:64910690c574 | 643 | { |
| AnnaBridge | 145:64910690c574 | 644 | MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); |
| AnnaBridge | 145:64910690c574 | 645 | } |
| AnnaBridge | 145:64910690c574 | 646 | |
| AnnaBridge | 145:64910690c574 | 647 | /** |
| AnnaBridge | 145:64910690c574 | 648 | * @brief Get voltage Regulator mode during deep sleep mode |
| AnnaBridge | 145:64910690c574 | 649 | * @rmtoll CR LPDS LL_PWR_GetRegulModeDS |
| AnnaBridge | 145:64910690c574 | 650 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 651 | * @arg @ref LL_PWR_REGU_DSMODE_MAIN |
| AnnaBridge | 145:64910690c574 | 652 | * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER |
| AnnaBridge | 145:64910690c574 | 653 | */ |
| AnnaBridge | 145:64910690c574 | 654 | __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) |
| AnnaBridge | 145:64910690c574 | 655 | { |
| AnnaBridge | 145:64910690c574 | 656 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); |
| AnnaBridge | 145:64910690c574 | 657 | } |
| AnnaBridge | 145:64910690c574 | 658 | |
| AnnaBridge | 145:64910690c574 | 659 | /** |
| AnnaBridge | 145:64910690c574 | 660 | * @brief Set Power Down mode when CPU enters deepsleep |
| AnnaBridge | 145:64910690c574 | 661 | * @rmtoll CR PDDS LL_PWR_SetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 662 | * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 663 | * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 664 | * @rmtoll CR FPDS LL_PWR_SetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 665 | * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 666 | * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 667 | * @rmtoll CR FPDS LL_PWR_SetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 668 | * @rmtoll CR LPDS LL_PWR_SetPowerMode |
| AnnaBridge | 145:64910690c574 | 669 | * @param PDMode This parameter can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 670 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
| AnnaBridge | 145:64910690c574 | 671 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
| AnnaBridge | 145:64910690c574 | 672 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) |
| AnnaBridge | 145:64910690c574 | 673 | * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) |
| AnnaBridge | 145:64910690c574 | 674 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) |
| AnnaBridge | 145:64910690c574 | 675 | * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) |
| AnnaBridge | 145:64910690c574 | 676 | * |
| AnnaBridge | 145:64910690c574 | 677 | * (*) not available on all devices |
| AnnaBridge | 145:64910690c574 | 678 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 145:64910690c574 | 679 | * @retval None |
| AnnaBridge | 145:64910690c574 | 680 | */ |
| AnnaBridge | 145:64910690c574 | 681 | __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) |
| AnnaBridge | 145:64910690c574 | 682 | { |
| AnnaBridge | 145:64910690c574 | 683 | #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) |
| AnnaBridge | 145:64910690c574 | 684 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode); |
| AnnaBridge | 145:64910690c574 | 685 | #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) |
| AnnaBridge | 145:64910690c574 | 686 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode); |
| AnnaBridge | 145:64910690c574 | 687 | #else |
| AnnaBridge | 145:64910690c574 | 688 | MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); |
| AnnaBridge | 145:64910690c574 | 689 | #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ |
| AnnaBridge | 145:64910690c574 | 690 | } |
| AnnaBridge | 145:64910690c574 | 691 | |
| AnnaBridge | 145:64910690c574 | 692 | /** |
| AnnaBridge | 145:64910690c574 | 693 | * @brief Get Power Down mode when CPU enters deepsleep |
| AnnaBridge | 145:64910690c574 | 694 | * @rmtoll CR PDDS LL_PWR_GetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 695 | * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 696 | * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 697 | * @rmtoll CR FPDS LL_PWR_GetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 698 | * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 699 | * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 700 | * @rmtoll CR FPDS LL_PWR_GetPowerMode\n |
| AnnaBridge | 145:64910690c574 | 701 | * @rmtoll CR LPDS LL_PWR_GetPowerMode |
| AnnaBridge | 145:64910690c574 | 702 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 703 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU |
| AnnaBridge | 145:64910690c574 | 704 | * @arg @ref LL_PWR_MODE_STOP_LPREGU |
| AnnaBridge | 145:64910690c574 | 705 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) |
| AnnaBridge | 145:64910690c574 | 706 | * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) |
| AnnaBridge | 145:64910690c574 | 707 | * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) |
| AnnaBridge | 145:64910690c574 | 708 | * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) |
| AnnaBridge | 145:64910690c574 | 709 | * |
| AnnaBridge | 145:64910690c574 | 710 | * (*) not available on all devices |
| AnnaBridge | 145:64910690c574 | 711 | * @arg @ref LL_PWR_MODE_STANDBY |
| AnnaBridge | 145:64910690c574 | 712 | */ |
| AnnaBridge | 145:64910690c574 | 713 | __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) |
| AnnaBridge | 145:64910690c574 | 714 | { |
| AnnaBridge | 145:64910690c574 | 715 | #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) |
| AnnaBridge | 145:64910690c574 | 716 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS))); |
| AnnaBridge | 145:64910690c574 | 717 | #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) |
| AnnaBridge | 145:64910690c574 | 718 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS))); |
| AnnaBridge | 145:64910690c574 | 719 | #else |
| AnnaBridge | 145:64910690c574 | 720 | return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); |
| AnnaBridge | 145:64910690c574 | 721 | #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ |
| AnnaBridge | 145:64910690c574 | 722 | } |
| AnnaBridge | 145:64910690c574 | 723 | |
| AnnaBridge | 145:64910690c574 | 724 | /** |
| AnnaBridge | 145:64910690c574 | 725 | * @brief Configure the voltage threshold detected by the Power Voltage Detector |
| AnnaBridge | 145:64910690c574 | 726 | * @rmtoll CR PLS LL_PWR_SetPVDLevel |
| AnnaBridge | 145:64910690c574 | 727 | * @param PVDLevel This parameter can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 728 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 145:64910690c574 | 729 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 145:64910690c574 | 730 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 145:64910690c574 | 731 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 145:64910690c574 | 732 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 145:64910690c574 | 733 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 145:64910690c574 | 734 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 145:64910690c574 | 735 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 145:64910690c574 | 736 | * @retval None |
| AnnaBridge | 145:64910690c574 | 737 | */ |
| AnnaBridge | 145:64910690c574 | 738 | __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) |
| AnnaBridge | 145:64910690c574 | 739 | { |
| AnnaBridge | 145:64910690c574 | 740 | MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); |
| AnnaBridge | 145:64910690c574 | 741 | } |
| AnnaBridge | 145:64910690c574 | 742 | |
| AnnaBridge | 145:64910690c574 | 743 | /** |
| AnnaBridge | 145:64910690c574 | 744 | * @brief Get the voltage threshold detection |
| AnnaBridge | 145:64910690c574 | 745 | * @rmtoll CR PLS LL_PWR_GetPVDLevel |
| AnnaBridge | 145:64910690c574 | 746 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 747 | * @arg @ref LL_PWR_PVDLEVEL_0 |
| AnnaBridge | 145:64910690c574 | 748 | * @arg @ref LL_PWR_PVDLEVEL_1 |
| AnnaBridge | 145:64910690c574 | 749 | * @arg @ref LL_PWR_PVDLEVEL_2 |
| AnnaBridge | 145:64910690c574 | 750 | * @arg @ref LL_PWR_PVDLEVEL_3 |
| AnnaBridge | 145:64910690c574 | 751 | * @arg @ref LL_PWR_PVDLEVEL_4 |
| AnnaBridge | 145:64910690c574 | 752 | * @arg @ref LL_PWR_PVDLEVEL_5 |
| AnnaBridge | 145:64910690c574 | 753 | * @arg @ref LL_PWR_PVDLEVEL_6 |
| AnnaBridge | 145:64910690c574 | 754 | * @arg @ref LL_PWR_PVDLEVEL_7 |
| AnnaBridge | 145:64910690c574 | 755 | */ |
| AnnaBridge | 145:64910690c574 | 756 | __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) |
| AnnaBridge | 145:64910690c574 | 757 | { |
| AnnaBridge | 145:64910690c574 | 758 | return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); |
| AnnaBridge | 145:64910690c574 | 759 | } |
| AnnaBridge | 145:64910690c574 | 760 | |
| AnnaBridge | 145:64910690c574 | 761 | /** |
| AnnaBridge | 145:64910690c574 | 762 | * @brief Enable Power Voltage Detector |
| AnnaBridge | 145:64910690c574 | 763 | * @rmtoll CR PVDE LL_PWR_EnablePVD |
| AnnaBridge | 145:64910690c574 | 764 | * @retval None |
| AnnaBridge | 145:64910690c574 | 765 | */ |
| AnnaBridge | 145:64910690c574 | 766 | __STATIC_INLINE void LL_PWR_EnablePVD(void) |
| AnnaBridge | 145:64910690c574 | 767 | { |
| AnnaBridge | 145:64910690c574 | 768 | SET_BIT(PWR->CR, PWR_CR_PVDE); |
| AnnaBridge | 145:64910690c574 | 769 | } |
| AnnaBridge | 145:64910690c574 | 770 | |
| AnnaBridge | 145:64910690c574 | 771 | /** |
| AnnaBridge | 145:64910690c574 | 772 | * @brief Disable Power Voltage Detector |
| AnnaBridge | 145:64910690c574 | 773 | * @rmtoll CR PVDE LL_PWR_DisablePVD |
| AnnaBridge | 145:64910690c574 | 774 | * @retval None |
| AnnaBridge | 145:64910690c574 | 775 | */ |
| AnnaBridge | 145:64910690c574 | 776 | __STATIC_INLINE void LL_PWR_DisablePVD(void) |
| AnnaBridge | 145:64910690c574 | 777 | { |
| AnnaBridge | 145:64910690c574 | 778 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); |
| AnnaBridge | 145:64910690c574 | 779 | } |
| AnnaBridge | 145:64910690c574 | 780 | |
| AnnaBridge | 145:64910690c574 | 781 | /** |
| AnnaBridge | 145:64910690c574 | 782 | * @brief Check if Power Voltage Detector is enabled |
| AnnaBridge | 145:64910690c574 | 783 | * @rmtoll CR PVDE LL_PWR_IsEnabledPVD |
| AnnaBridge | 145:64910690c574 | 784 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 785 | */ |
| AnnaBridge | 145:64910690c574 | 786 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) |
| AnnaBridge | 145:64910690c574 | 787 | { |
| AnnaBridge | 145:64910690c574 | 788 | return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); |
| AnnaBridge | 145:64910690c574 | 789 | } |
| AnnaBridge | 145:64910690c574 | 790 | |
| AnnaBridge | 145:64910690c574 | 791 | /** |
| AnnaBridge | 145:64910690c574 | 792 | * @brief Enable the WakeUp PINx functionality |
| AnnaBridge | 145:64910690c574 | 793 | * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 794 | * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 795 | * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 796 | * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin |
| AnnaBridge | 145:64910690c574 | 797 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 798 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 145:64910690c574 | 799 | * @arg @ref LL_PWR_WAKEUP_PIN2 (*) |
| AnnaBridge | 145:64910690c574 | 800 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 145:64910690c574 | 801 | * |
| AnnaBridge | 145:64910690c574 | 802 | * (*) not available on all devices |
| AnnaBridge | 145:64910690c574 | 803 | * @retval None |
| AnnaBridge | 145:64910690c574 | 804 | */ |
| AnnaBridge | 145:64910690c574 | 805 | __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 145:64910690c574 | 806 | { |
| AnnaBridge | 145:64910690c574 | 807 | SET_BIT(PWR->CSR, WakeUpPin); |
| AnnaBridge | 145:64910690c574 | 808 | } |
| AnnaBridge | 145:64910690c574 | 809 | |
| AnnaBridge | 145:64910690c574 | 810 | /** |
| AnnaBridge | 145:64910690c574 | 811 | * @brief Disable the WakeUp PINx functionality |
| AnnaBridge | 145:64910690c574 | 812 | * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 813 | * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 814 | * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 815 | * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin |
| AnnaBridge | 145:64910690c574 | 816 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 817 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 145:64910690c574 | 818 | * @arg @ref LL_PWR_WAKEUP_PIN2 (*) |
| AnnaBridge | 145:64910690c574 | 819 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 145:64910690c574 | 820 | * |
| AnnaBridge | 145:64910690c574 | 821 | * (*) not available on all devices |
| AnnaBridge | 145:64910690c574 | 822 | * @retval None |
| AnnaBridge | 145:64910690c574 | 823 | */ |
| AnnaBridge | 145:64910690c574 | 824 | __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 145:64910690c574 | 825 | { |
| AnnaBridge | 145:64910690c574 | 826 | CLEAR_BIT(PWR->CSR, WakeUpPin); |
| AnnaBridge | 145:64910690c574 | 827 | } |
| AnnaBridge | 145:64910690c574 | 828 | |
| AnnaBridge | 145:64910690c574 | 829 | /** |
| AnnaBridge | 145:64910690c574 | 830 | * @brief Check if the WakeUp PINx functionality is enabled |
| AnnaBridge | 145:64910690c574 | 831 | * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 832 | * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 833 | * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n |
| AnnaBridge | 145:64910690c574 | 834 | * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin |
| AnnaBridge | 145:64910690c574 | 835 | * @param WakeUpPin This parameter can be one of the following values: |
| AnnaBridge | 145:64910690c574 | 836 | * @arg @ref LL_PWR_WAKEUP_PIN1 |
| AnnaBridge | 145:64910690c574 | 837 | * @arg @ref LL_PWR_WAKEUP_PIN2 (*) |
| AnnaBridge | 145:64910690c574 | 838 | * @arg @ref LL_PWR_WAKEUP_PIN3 (*) |
| AnnaBridge | 145:64910690c574 | 839 | * |
| AnnaBridge | 145:64910690c574 | 840 | * (*) not available on all devices |
| AnnaBridge | 145:64910690c574 | 841 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 842 | */ |
| AnnaBridge | 145:64910690c574 | 843 | __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) |
| AnnaBridge | 145:64910690c574 | 844 | { |
| AnnaBridge | 145:64910690c574 | 845 | return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); |
| AnnaBridge | 145:64910690c574 | 846 | } |
| AnnaBridge | 145:64910690c574 | 847 | |
| AnnaBridge | 145:64910690c574 | 848 | |
| AnnaBridge | 145:64910690c574 | 849 | /** |
| AnnaBridge | 145:64910690c574 | 850 | * @} |
| AnnaBridge | 145:64910690c574 | 851 | */ |
| AnnaBridge | 145:64910690c574 | 852 | |
| AnnaBridge | 145:64910690c574 | 853 | /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management |
| AnnaBridge | 145:64910690c574 | 854 | * @{ |
| AnnaBridge | 145:64910690c574 | 855 | */ |
| AnnaBridge | 145:64910690c574 | 856 | |
| AnnaBridge | 145:64910690c574 | 857 | /** |
| AnnaBridge | 145:64910690c574 | 858 | * @brief Get Wake-up Flag |
| AnnaBridge | 145:64910690c574 | 859 | * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU |
| AnnaBridge | 145:64910690c574 | 860 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 861 | */ |
| AnnaBridge | 145:64910690c574 | 862 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) |
| AnnaBridge | 145:64910690c574 | 863 | { |
| AnnaBridge | 145:64910690c574 | 864 | return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); |
| AnnaBridge | 145:64910690c574 | 865 | } |
| AnnaBridge | 145:64910690c574 | 866 | |
| AnnaBridge | 145:64910690c574 | 867 | /** |
| AnnaBridge | 145:64910690c574 | 868 | * @brief Get Standby Flag |
| AnnaBridge | 145:64910690c574 | 869 | * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB |
| AnnaBridge | 145:64910690c574 | 870 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 871 | */ |
| AnnaBridge | 145:64910690c574 | 872 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) |
| AnnaBridge | 145:64910690c574 | 873 | { |
| AnnaBridge | 145:64910690c574 | 874 | return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); |
| AnnaBridge | 145:64910690c574 | 875 | } |
| AnnaBridge | 145:64910690c574 | 876 | |
| AnnaBridge | 145:64910690c574 | 877 | /** |
| AnnaBridge | 145:64910690c574 | 878 | * @brief Get Backup Regulator ready Flag |
| AnnaBridge | 145:64910690c574 | 879 | * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR |
| AnnaBridge | 145:64910690c574 | 880 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 881 | */ |
| AnnaBridge | 145:64910690c574 | 882 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) |
| AnnaBridge | 145:64910690c574 | 883 | { |
| AnnaBridge | 145:64910690c574 | 884 | return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR)); |
| AnnaBridge | 145:64910690c574 | 885 | } |
| AnnaBridge | 145:64910690c574 | 886 | /** |
| AnnaBridge | 145:64910690c574 | 887 | * @brief Indicate whether VDD voltage is below the selected PVD threshold |
| AnnaBridge | 145:64910690c574 | 888 | * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO |
| AnnaBridge | 145:64910690c574 | 889 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 890 | */ |
| AnnaBridge | 145:64910690c574 | 891 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) |
| AnnaBridge | 145:64910690c574 | 892 | { |
| AnnaBridge | 145:64910690c574 | 893 | return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); |
| AnnaBridge | 145:64910690c574 | 894 | } |
| AnnaBridge | 145:64910690c574 | 895 | |
| AnnaBridge | 145:64910690c574 | 896 | /** |
| AnnaBridge | 145:64910690c574 | 897 | * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level |
| AnnaBridge | 145:64910690c574 | 898 | * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS |
| AnnaBridge | 145:64910690c574 | 899 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 900 | */ |
| AnnaBridge | 145:64910690c574 | 901 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) |
| AnnaBridge | 145:64910690c574 | 902 | { |
| AnnaBridge | 145:64910690c574 | 903 | return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS)); |
| AnnaBridge | 145:64910690c574 | 904 | } |
| AnnaBridge | 145:64910690c574 | 905 | #if defined(PWR_CR_ODEN) |
| AnnaBridge | 145:64910690c574 | 906 | /** |
| AnnaBridge | 145:64910690c574 | 907 | * @brief Indicate whether the Over-Drive mode is ready or not |
| AnnaBridge | 145:64910690c574 | 908 | * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD |
| AnnaBridge | 145:64910690c574 | 909 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 910 | */ |
| AnnaBridge | 145:64910690c574 | 911 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void) |
| AnnaBridge | 145:64910690c574 | 912 | { |
| AnnaBridge | 145:64910690c574 | 913 | return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY)); |
| AnnaBridge | 145:64910690c574 | 914 | } |
| AnnaBridge | 145:64910690c574 | 915 | #endif /* PWR_CR_ODEN */ |
| AnnaBridge | 145:64910690c574 | 916 | |
| AnnaBridge | 145:64910690c574 | 917 | #if defined(PWR_CR_ODSWEN) |
| AnnaBridge | 145:64910690c574 | 918 | /** |
| AnnaBridge | 145:64910690c574 | 919 | * @brief Indicate whether the Over-Drive mode switching is ready or not |
| AnnaBridge | 145:64910690c574 | 920 | * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW |
| AnnaBridge | 145:64910690c574 | 921 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 922 | */ |
| AnnaBridge | 145:64910690c574 | 923 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void) |
| AnnaBridge | 145:64910690c574 | 924 | { |
| AnnaBridge | 145:64910690c574 | 925 | return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY)); |
| AnnaBridge | 145:64910690c574 | 926 | } |
| AnnaBridge | 145:64910690c574 | 927 | #endif /* PWR_CR_ODSWEN */ |
| AnnaBridge | 145:64910690c574 | 928 | |
| AnnaBridge | 145:64910690c574 | 929 | #if defined(PWR_CR_UDEN) |
| AnnaBridge | 145:64910690c574 | 930 | /** |
| AnnaBridge | 145:64910690c574 | 931 | * @brief Indicate whether the Under-Drive mode is ready or not |
| AnnaBridge | 145:64910690c574 | 932 | * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD |
| AnnaBridge | 145:64910690c574 | 933 | * @retval State of bit (1 or 0). |
| AnnaBridge | 145:64910690c574 | 934 | */ |
| AnnaBridge | 145:64910690c574 | 935 | __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void) |
| AnnaBridge | 145:64910690c574 | 936 | { |
| AnnaBridge | 145:64910690c574 | 937 | return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY)); |
| AnnaBridge | 145:64910690c574 | 938 | } |
| AnnaBridge | 145:64910690c574 | 939 | #endif /* PWR_CR_UDEN */ |
| AnnaBridge | 145:64910690c574 | 940 | /** |
| AnnaBridge | 145:64910690c574 | 941 | * @brief Clear Standby Flag |
| AnnaBridge | 145:64910690c574 | 942 | * @rmtoll CR CSBF LL_PWR_ClearFlag_SB |
| AnnaBridge | 145:64910690c574 | 943 | * @retval None |
| AnnaBridge | 145:64910690c574 | 944 | */ |
| AnnaBridge | 145:64910690c574 | 945 | __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) |
| AnnaBridge | 145:64910690c574 | 946 | { |
| AnnaBridge | 145:64910690c574 | 947 | SET_BIT(PWR->CR, PWR_CR_CSBF); |
| AnnaBridge | 145:64910690c574 | 948 | } |
| AnnaBridge | 145:64910690c574 | 949 | |
| AnnaBridge | 145:64910690c574 | 950 | /** |
| AnnaBridge | 145:64910690c574 | 951 | * @brief Clear Wake-up Flags |
| AnnaBridge | 145:64910690c574 | 952 | * @rmtoll CR CWUF LL_PWR_ClearFlag_WU |
| AnnaBridge | 145:64910690c574 | 953 | * @retval None |
| AnnaBridge | 145:64910690c574 | 954 | */ |
| AnnaBridge | 145:64910690c574 | 955 | __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) |
| AnnaBridge | 145:64910690c574 | 956 | { |
| AnnaBridge | 145:64910690c574 | 957 | SET_BIT(PWR->CR, PWR_CR_CWUF); |
| AnnaBridge | 145:64910690c574 | 958 | } |
| AnnaBridge | 145:64910690c574 | 959 | #if defined(PWR_CSR_UDRDY) |
| AnnaBridge | 145:64910690c574 | 960 | /** |
| AnnaBridge | 145:64910690c574 | 961 | * @brief Clear Under-Drive ready Flag |
| AnnaBridge | 145:64910690c574 | 962 | * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD |
| AnnaBridge | 145:64910690c574 | 963 | * @retval None |
| AnnaBridge | 145:64910690c574 | 964 | */ |
| AnnaBridge | 145:64910690c574 | 965 | __STATIC_INLINE void LL_PWR_ClearFlag_UD(void) |
| AnnaBridge | 145:64910690c574 | 966 | { |
| AnnaBridge | 145:64910690c574 | 967 | WRITE_REG(PWR->CSR, PWR_CSR_UDRDY); |
| AnnaBridge | 145:64910690c574 | 968 | } |
| AnnaBridge | 145:64910690c574 | 969 | #endif /* PWR_CSR_UDRDY */ |
| AnnaBridge | 145:64910690c574 | 970 | |
| AnnaBridge | 145:64910690c574 | 971 | /** |
| AnnaBridge | 145:64910690c574 | 972 | * @} |
| AnnaBridge | 145:64910690c574 | 973 | */ |
| AnnaBridge | 145:64910690c574 | 974 | |
| AnnaBridge | 145:64910690c574 | 975 | #if defined(USE_FULL_LL_DRIVER) |
| AnnaBridge | 145:64910690c574 | 976 | /** @defgroup PWR_LL_EF_Init De-initialization function |
| AnnaBridge | 145:64910690c574 | 977 | * @{ |
| AnnaBridge | 145:64910690c574 | 978 | */ |
| AnnaBridge | 145:64910690c574 | 979 | ErrorStatus LL_PWR_DeInit(void); |
| AnnaBridge | 145:64910690c574 | 980 | /** |
| AnnaBridge | 145:64910690c574 | 981 | * @} |
| AnnaBridge | 145:64910690c574 | 982 | */ |
| AnnaBridge | 145:64910690c574 | 983 | #endif /* USE_FULL_LL_DRIVER */ |
| AnnaBridge | 145:64910690c574 | 984 | |
| AnnaBridge | 145:64910690c574 | 985 | /** |
| AnnaBridge | 145:64910690c574 | 986 | * @} |
| AnnaBridge | 145:64910690c574 | 987 | */ |
| AnnaBridge | 145:64910690c574 | 988 | |
| AnnaBridge | 145:64910690c574 | 989 | /** |
| AnnaBridge | 145:64910690c574 | 990 | * @} |
| AnnaBridge | 145:64910690c574 | 991 | */ |
| AnnaBridge | 145:64910690c574 | 992 | |
| AnnaBridge | 145:64910690c574 | 993 | #endif /* defined(PWR) */ |
| AnnaBridge | 145:64910690c574 | 994 | |
| AnnaBridge | 145:64910690c574 | 995 | /** |
| AnnaBridge | 145:64910690c574 | 996 | * @} |
| AnnaBridge | 145:64910690c574 | 997 | */ |
| AnnaBridge | 145:64910690c574 | 998 | |
| AnnaBridge | 145:64910690c574 | 999 | #ifdef __cplusplus |
| AnnaBridge | 145:64910690c574 | 1000 | } |
| AnnaBridge | 145:64910690c574 | 1001 | #endif |
| AnnaBridge | 145:64910690c574 | 1002 | |
| AnnaBridge | 145:64910690c574 | 1003 | #endif /* __STM32F4xx_LL_PWR_H */ |
| AnnaBridge | 145:64910690c574 | 1004 | |
| AnnaBridge | 145:64910690c574 | 1005 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
