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TARGET_STEVAL_3DP001V1/TOOLCHAIN_IAR/stm32f4xx_ll_bus.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32f4xx_ll_bus.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @brief Header file of BUS LL module.
AnnaBridge	145:64910690c574	6
AnnaBridge	145:64910690c574	7	@verbatim
AnnaBridge	145:64910690c574	8	##### RCC Limitations #####
AnnaBridge	145:64910690c574	9	==============================================================================
AnnaBridge	145:64910690c574	10	[..]
AnnaBridge	145:64910690c574	11	A delay between an RCC peripheral clock enable and the effective peripheral
AnnaBridge	145:64910690c574	12	enabling should be taken into account in order to manage the peripheral read/write
AnnaBridge	145:64910690c574	13	from/to registers.
AnnaBridge	145:64910690c574	14	(+) This delay depends on the peripheral mapping.
AnnaBridge	145:64910690c574	15	(++) AHB & APB peripherals, 1 dummy read is necessary
AnnaBridge	145:64910690c574	16
AnnaBridge	145:64910690c574	17	[..]
AnnaBridge	145:64910690c574	18	Workarounds:
AnnaBridge	145:64910690c574	19	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
AnnaBridge	145:64910690c574	20	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
AnnaBridge	145:64910690c574	21
AnnaBridge	145:64910690c574	22	@endverbatim
AnnaBridge	145:64910690c574	23	******************************************************************************
AnnaBridge	145:64910690c574	24	* @attention
AnnaBridge	145:64910690c574	25	*
AnnaBridge	145:64910690c574	26	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	27	*
AnnaBridge	145:64910690c574	28	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	29	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	30	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	31	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	32	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	33	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	34	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	35	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	36	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	37	* without specific prior written permission.
AnnaBridge	145:64910690c574	38	*
AnnaBridge	145:64910690c574	39	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	40	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	41	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	42	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	43	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	44	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	45	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	46	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	47	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	48	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	49	*
AnnaBridge	145:64910690c574	50	******************************************************************************
AnnaBridge	145:64910690c574	51	*/
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	54	#ifndef __STM32F4xx_LL_BUS_H
AnnaBridge	145:64910690c574	55	#define __STM32F4xx_LL_BUS_H
AnnaBridge	145:64910690c574	56
AnnaBridge	145:64910690c574	57	#ifdef __cplusplus
AnnaBridge	145:64910690c574	58	extern "C" {
AnnaBridge	145:64910690c574	59	#endif
AnnaBridge	145:64910690c574	60
AnnaBridge	145:64910690c574	61	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	62	#include "stm32f4xx.h"
AnnaBridge	145:64910690c574	63
AnnaBridge	145:64910690c574	64	/** @addtogroup STM32F4xx_LL_Driver
AnnaBridge	145:64910690c574	65	* @{
AnnaBridge	145:64910690c574	66	*/
AnnaBridge	145:64910690c574	67
AnnaBridge	145:64910690c574	68	#if defined(RCC)
AnnaBridge	145:64910690c574	69
AnnaBridge	145:64910690c574	70	/** @defgroup BUS_LL BUS
AnnaBridge	145:64910690c574	71	* @{
AnnaBridge	145:64910690c574	72	*/
AnnaBridge	145:64910690c574	73
AnnaBridge	145:64910690c574	74	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	75	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	76	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	77	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	78	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	79	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	80	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
AnnaBridge	145:64910690c574	81	* @{
AnnaBridge	145:64910690c574	82	*/
AnnaBridge	145:64910690c574	83
AnnaBridge	145:64910690c574	84	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
AnnaBridge	145:64910690c574	85	* @{
AnnaBridge	145:64910690c574	86	*/
AnnaBridge	145:64910690c574	87	#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	88	#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
AnnaBridge	145:64910690c574	89	#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
AnnaBridge	145:64910690c574	90	#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
AnnaBridge	145:64910690c574	91	#if defined(GPIOD)
AnnaBridge	145:64910690c574	92	#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
AnnaBridge	145:64910690c574	93	#endif /* GPIOD */
AnnaBridge	145:64910690c574	94	#if defined(GPIOE)
AnnaBridge	145:64910690c574	95	#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
AnnaBridge	145:64910690c574	96	#endif /* GPIOE */
AnnaBridge	145:64910690c574	97	#if defined(GPIOF)
AnnaBridge	145:64910690c574	98	#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
AnnaBridge	145:64910690c574	99	#endif /* GPIOF */
AnnaBridge	145:64910690c574	100	#if defined(GPIOG)
AnnaBridge	145:64910690c574	101	#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
AnnaBridge	145:64910690c574	102	#endif /* GPIOG */
AnnaBridge	145:64910690c574	103	#if defined(GPIOH)
AnnaBridge	145:64910690c574	104	#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
AnnaBridge	145:64910690c574	105	#endif /* GPIOH */
AnnaBridge	145:64910690c574	106	#if defined(GPIOI)
AnnaBridge	145:64910690c574	107	#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
AnnaBridge	145:64910690c574	108	#endif /* GPIOI */
AnnaBridge	145:64910690c574	109	#if defined(GPIOJ)
AnnaBridge	145:64910690c574	110	#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
AnnaBridge	145:64910690c574	111	#endif /* GPIOJ */
AnnaBridge	145:64910690c574	112	#if defined(GPIOK)
AnnaBridge	145:64910690c574	113	#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
AnnaBridge	145:64910690c574	114	#endif /* GPIOK */
AnnaBridge	145:64910690c574	115	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
AnnaBridge	145:64910690c574	116	#if defined(RCC_AHB1ENR_BKPSRAMEN)
AnnaBridge	145:64910690c574	117	#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
AnnaBridge	145:64910690c574	118	#endif /* RCC_AHB1ENR_BKPSRAMEN */
AnnaBridge	145:64910690c574	119	#if defined(RCC_AHB1ENR_CCMDATARAMEN)
AnnaBridge	145:64910690c574	120	#define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
AnnaBridge	145:64910690c574	121	#endif /* RCC_AHB1ENR_CCMDATARAMEN */
AnnaBridge	145:64910690c574	122	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
AnnaBridge	145:64910690c574	123	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
AnnaBridge	145:64910690c574	124	#if defined(RCC_AHB1ENR_RNGEN)
AnnaBridge	145:64910690c574	125	#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN
AnnaBridge	145:64910690c574	126	#endif /* RCC_AHB1ENR_RNGEN */
AnnaBridge	145:64910690c574	127	#if defined(DMA2D)
AnnaBridge	145:64910690c574	128	#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
AnnaBridge	145:64910690c574	129	#endif /* DMA2D */
AnnaBridge	145:64910690c574	130	#if defined(ETH)
AnnaBridge	145:64910690c574	131	#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
AnnaBridge	145:64910690c574	132	#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
AnnaBridge	145:64910690c574	133	#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
AnnaBridge	145:64910690c574	134	#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
AnnaBridge	145:64910690c574	135	#endif /* ETH */
AnnaBridge	145:64910690c574	136	#if defined(USB_OTG_HS)
AnnaBridge	145:64910690c574	137	#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
AnnaBridge	145:64910690c574	138	#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
AnnaBridge	145:64910690c574	139	#endif /* USB_OTG_HS */
AnnaBridge	145:64910690c574	140	#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
AnnaBridge	145:64910690c574	141	#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
AnnaBridge	145:64910690c574	142	#if defined(RCC_AHB1LPENR_SRAM2LPEN)
AnnaBridge	145:64910690c574	143	#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
AnnaBridge	145:64910690c574	144	#endif /* RCC_AHB1LPENR_SRAM2LPEN */
AnnaBridge	145:64910690c574	145	#if defined(RCC_AHB1LPENR_SRAM3LPEN)
AnnaBridge	145:64910690c574	146	#define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
AnnaBridge	145:64910690c574	147	#endif /* RCC_AHB1LPENR_SRAM3LPEN */
AnnaBridge	145:64910690c574	148	/**
AnnaBridge	145:64910690c574	149	* @}
AnnaBridge	145:64910690c574	150	*/
AnnaBridge	145:64910690c574	151
AnnaBridge	145:64910690c574	152	#if defined(RCC_AHB2_SUPPORT)
AnnaBridge	145:64910690c574	153	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
AnnaBridge	145:64910690c574	154	* @{
AnnaBridge	145:64910690c574	155	*/
AnnaBridge	145:64910690c574	156	#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	157	#if defined(DCMI)
AnnaBridge	145:64910690c574	158	#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
AnnaBridge	145:64910690c574	159	#endif /* DCMI */
AnnaBridge	145:64910690c574	160	#if defined(CRYP)
AnnaBridge	145:64910690c574	161	#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
AnnaBridge	145:64910690c574	162	#endif /* CRYP */
AnnaBridge	145:64910690c574	163	#if defined(AES)
AnnaBridge	145:64910690c574	164	#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
AnnaBridge	145:64910690c574	165	#endif /* AES */
AnnaBridge	145:64910690c574	166	#if defined(HASH)
AnnaBridge	145:64910690c574	167	#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
AnnaBridge	145:64910690c574	168	#endif /* HASH */
AnnaBridge	145:64910690c574	169	#if defined(RCC_AHB2ENR_RNGEN)
AnnaBridge	145:64910690c574	170	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
AnnaBridge	145:64910690c574	171	#endif /* RCC_AHB2ENR_RNGEN */
AnnaBridge	145:64910690c574	172	#if defined(USB_OTG_FS)
AnnaBridge	145:64910690c574	173	#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
AnnaBridge	145:64910690c574	174	#endif /* USB_OTG_FS */
AnnaBridge	145:64910690c574	175	/**
AnnaBridge	145:64910690c574	176	* @}
AnnaBridge	145:64910690c574	177	*/
AnnaBridge	145:64910690c574	178	#endif /* RCC_AHB2_SUPPORT */
AnnaBridge	145:64910690c574	179
AnnaBridge	145:64910690c574	180	#if defined(RCC_AHB3_SUPPORT)
AnnaBridge	145:64910690c574	181	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
AnnaBridge	145:64910690c574	182	* @{
AnnaBridge	145:64910690c574	183	*/
AnnaBridge	145:64910690c574	184	#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	185	#if defined(FSMC_Bank1)
AnnaBridge	145:64910690c574	186	#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
AnnaBridge	145:64910690c574	187	#endif /* FSMC_Bank1 */
AnnaBridge	145:64910690c574	188	#if defined(FMC_Bank1)
AnnaBridge	145:64910690c574	189	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
AnnaBridge	145:64910690c574	190	#endif /* FMC_Bank1 */
AnnaBridge	145:64910690c574	191	#if defined(QUADSPI)
AnnaBridge	145:64910690c574	192	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
AnnaBridge	145:64910690c574	193	#endif /* QUADSPI */
AnnaBridge	145:64910690c574	194	/**
AnnaBridge	145:64910690c574	195	* @}
AnnaBridge	145:64910690c574	196	*/
AnnaBridge	145:64910690c574	197	#endif /* RCC_AHB3_SUPPORT */
AnnaBridge	145:64910690c574	198
AnnaBridge	145:64910690c574	199	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
AnnaBridge	145:64910690c574	200	* @{
AnnaBridge	145:64910690c574	201	*/
AnnaBridge	145:64910690c574	202	#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	203	#if defined(TIM2)
AnnaBridge	145:64910690c574	204	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
AnnaBridge	145:64910690c574	205	#endif /* TIM2 */
AnnaBridge	145:64910690c574	206	#if defined(TIM3)
AnnaBridge	145:64910690c574	207	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
AnnaBridge	145:64910690c574	208	#endif /* TIM3 */
AnnaBridge	145:64910690c574	209	#if defined(TIM4)
AnnaBridge	145:64910690c574	210	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
AnnaBridge	145:64910690c574	211	#endif /* TIM4 */
AnnaBridge	145:64910690c574	212	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
AnnaBridge	145:64910690c574	213	#if defined(TIM6)
AnnaBridge	145:64910690c574	214	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
AnnaBridge	145:64910690c574	215	#endif /* TIM6 */
AnnaBridge	145:64910690c574	216	#if defined(TIM7)
AnnaBridge	145:64910690c574	217	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
AnnaBridge	145:64910690c574	218	#endif /* TIM7 */
AnnaBridge	145:64910690c574	219	#if defined(TIM12)
AnnaBridge	145:64910690c574	220	#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
AnnaBridge	145:64910690c574	221	#endif /* TIM12 */
AnnaBridge	145:64910690c574	222	#if defined(TIM13)
AnnaBridge	145:64910690c574	223	#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
AnnaBridge	145:64910690c574	224	#endif /* TIM13 */
AnnaBridge	145:64910690c574	225	#if defined(TIM14)
AnnaBridge	145:64910690c574	226	#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
AnnaBridge	145:64910690c574	227	#endif /* TIM14 */
AnnaBridge	145:64910690c574	228	#if defined(LPTIM1)
AnnaBridge	145:64910690c574	229	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
AnnaBridge	145:64910690c574	230	#endif /* LPTIM1 */
AnnaBridge	145:64910690c574	231	#if defined(RCC_APB1ENR_RTCAPBEN)
AnnaBridge	145:64910690c574	232	#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN
AnnaBridge	145:64910690c574	233	#endif /* RCC_APB1ENR_RTCAPBEN */
AnnaBridge	145:64910690c574	234	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
AnnaBridge	145:64910690c574	235	#if defined(SPI2)
AnnaBridge	145:64910690c574	236	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
AnnaBridge	145:64910690c574	237	#endif /* SPI2 */
AnnaBridge	145:64910690c574	238	#if defined(SPI3)
AnnaBridge	145:64910690c574	239	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
AnnaBridge	145:64910690c574	240	#endif /* SPI3 */
AnnaBridge	145:64910690c574	241	#if defined(SPDIFRX)
AnnaBridge	145:64910690c574	242	#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
AnnaBridge	145:64910690c574	243	#endif /* SPDIFRX */
AnnaBridge	145:64910690c574	244	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
AnnaBridge	145:64910690c574	245	#if defined(USART3)
AnnaBridge	145:64910690c574	246	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
AnnaBridge	145:64910690c574	247	#endif /* USART3 */
AnnaBridge	145:64910690c574	248	#if defined(UART4)
AnnaBridge	145:64910690c574	249	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
AnnaBridge	145:64910690c574	250	#endif /* UART4 */
AnnaBridge	145:64910690c574	251	#if defined(UART5)
AnnaBridge	145:64910690c574	252	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
AnnaBridge	145:64910690c574	253	#endif /* UART5 */
AnnaBridge	145:64910690c574	254	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
AnnaBridge	145:64910690c574	255	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
AnnaBridge	145:64910690c574	256	#if defined(I2C3)
AnnaBridge	145:64910690c574	257	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
AnnaBridge	145:64910690c574	258	#endif /* I2C3 */
AnnaBridge	145:64910690c574	259	#if defined(FMPI2C1)
AnnaBridge	145:64910690c574	260	#define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN
AnnaBridge	145:64910690c574	261	#endif /* FMPI2C1 */
AnnaBridge	145:64910690c574	262	#if defined(CAN1)
AnnaBridge	145:64910690c574	263	#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
AnnaBridge	145:64910690c574	264	#endif /* CAN1 */
AnnaBridge	145:64910690c574	265	#if defined(CAN2)
AnnaBridge	145:64910690c574	266	#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
AnnaBridge	145:64910690c574	267	#endif /* CAN2 */
AnnaBridge	145:64910690c574	268	#if defined(CAN3)
AnnaBridge	145:64910690c574	269	#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
AnnaBridge	145:64910690c574	270	#endif /* CAN3 */
AnnaBridge	145:64910690c574	271	#if defined(CEC)
AnnaBridge	145:64910690c574	272	#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
AnnaBridge	145:64910690c574	273	#endif /* CEC */
AnnaBridge	145:64910690c574	274	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
AnnaBridge	145:64910690c574	275	#if defined(DAC1)
AnnaBridge	145:64910690c574	276	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
AnnaBridge	145:64910690c574	277	#endif /* DAC1 */
AnnaBridge	145:64910690c574	278	#if defined(UART7)
AnnaBridge	145:64910690c574	279	#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
AnnaBridge	145:64910690c574	280	#endif /* UART7 */
AnnaBridge	145:64910690c574	281	#if defined(UART8)
AnnaBridge	145:64910690c574	282	#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
AnnaBridge	145:64910690c574	283	#endif /* UART8 */
AnnaBridge	145:64910690c574	284	/**
AnnaBridge	145:64910690c574	285	* @}
AnnaBridge	145:64910690c574	286	*/
AnnaBridge	145:64910690c574	287
AnnaBridge	145:64910690c574	288	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
AnnaBridge	145:64910690c574	289	* @{
AnnaBridge	145:64910690c574	290	*/
AnnaBridge	145:64910690c574	291	#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	292	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
AnnaBridge	145:64910690c574	293	#if defined(TIM8)
AnnaBridge	145:64910690c574	294	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
AnnaBridge	145:64910690c574	295	#endif /* TIM8 */
AnnaBridge	145:64910690c574	296	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
AnnaBridge	145:64910690c574	297	#if defined(USART6)
AnnaBridge	145:64910690c574	298	#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
AnnaBridge	145:64910690c574	299	#endif /* USART6 */
AnnaBridge	145:64910690c574	300	#if defined(UART9)
AnnaBridge	145:64910690c574	301	#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
AnnaBridge	145:64910690c574	302	#endif /* UART9 */
AnnaBridge	145:64910690c574	303	#if defined(UART10)
AnnaBridge	145:64910690c574	304	#define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN
AnnaBridge	145:64910690c574	305	#endif /* UART10 */
AnnaBridge	145:64910690c574	306	#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
AnnaBridge	145:64910690c574	307	#if defined(ADC2)
AnnaBridge	145:64910690c574	308	#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
AnnaBridge	145:64910690c574	309	#endif /* ADC2 */
AnnaBridge	145:64910690c574	310	#if defined(ADC3)
AnnaBridge	145:64910690c574	311	#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
AnnaBridge	145:64910690c574	312	#endif /* ADC3 */
AnnaBridge	145:64910690c574	313	#if defined(SDIO)
AnnaBridge	145:64910690c574	314	#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
AnnaBridge	145:64910690c574	315	#endif /* SDIO */
AnnaBridge	145:64910690c574	316	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
AnnaBridge	145:64910690c574	317	#if defined(SPI4)
AnnaBridge	145:64910690c574	318	#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
AnnaBridge	145:64910690c574	319	#endif /* SPI4 */
AnnaBridge	145:64910690c574	320	#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
AnnaBridge	145:64910690c574	321	#if defined(RCC_APB2ENR_EXTITEN)
AnnaBridge	145:64910690c574	322	#define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN
AnnaBridge	145:64910690c574	323	#endif /* RCC_APB2ENR_EXTITEN */
AnnaBridge	145:64910690c574	324	#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
AnnaBridge	145:64910690c574	325	#if defined(TIM10)
AnnaBridge	145:64910690c574	326	#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
AnnaBridge	145:64910690c574	327	#endif /* TIM10 */
AnnaBridge	145:64910690c574	328	#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
AnnaBridge	145:64910690c574	329	#if defined(SPI5)
AnnaBridge	145:64910690c574	330	#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
AnnaBridge	145:64910690c574	331	#endif /* SPI5 */
AnnaBridge	145:64910690c574	332	#if defined(SPI6)
AnnaBridge	145:64910690c574	333	#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
AnnaBridge	145:64910690c574	334	#endif /* SPI6 */
AnnaBridge	145:64910690c574	335	#if defined(SAI1)
AnnaBridge	145:64910690c574	336	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
AnnaBridge	145:64910690c574	337	#endif /* SAI1 */
AnnaBridge	145:64910690c574	338	#if defined(SAI2)
AnnaBridge	145:64910690c574	339	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
AnnaBridge	145:64910690c574	340	#endif /* SAI2 */
AnnaBridge	145:64910690c574	341	#if defined(LTDC)
AnnaBridge	145:64910690c574	342	#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
AnnaBridge	145:64910690c574	343	#endif /* LTDC */
AnnaBridge	145:64910690c574	344	#if defined(DSI)
AnnaBridge	145:64910690c574	345	#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
AnnaBridge	145:64910690c574	346	#endif /* DSI */
AnnaBridge	145:64910690c574	347	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	348	#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
AnnaBridge	145:64910690c574	349	#endif /* DFSDM1_Channel0 */
AnnaBridge	145:64910690c574	350	#if defined(DFSDM2_Channel0)
AnnaBridge	145:64910690c574	351	#define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN
AnnaBridge	145:64910690c574	352	#endif /* DFSDM2_Channel0 */
AnnaBridge	145:64910690c574	353	#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
AnnaBridge	145:64910690c574	354	/**
AnnaBridge	145:64910690c574	355	* @}
AnnaBridge	145:64910690c574	356	*/
AnnaBridge	145:64910690c574	357
AnnaBridge	145:64910690c574	358	/**
AnnaBridge	145:64910690c574	359	* @}
AnnaBridge	145:64910690c574	360	*/
AnnaBridge	145:64910690c574	361
AnnaBridge	145:64910690c574	362	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	363	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	364	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
AnnaBridge	145:64910690c574	365	* @{
AnnaBridge	145:64910690c574	366	*/
AnnaBridge	145:64910690c574	367
AnnaBridge	145:64910690c574	368	/** @defgroup BUS_LL_EF_AHB1 AHB1
AnnaBridge	145:64910690c574	369	* @{
AnnaBridge	145:64910690c574	370	*/
AnnaBridge	145:64910690c574	371
AnnaBridge	145:64910690c574	372	/**
AnnaBridge	145:64910690c574	373	* @brief Enable AHB1 peripherals clock.
AnnaBridge	145:64910690c574	374	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	375	* AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	376	* AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	377	* AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	378	* AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	379	* AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	380	* AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	381	* AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	382	* AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	383	* AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	384	* AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	385	* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	386	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	387	* AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	388	* AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	389	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	390	* AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	391	* AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	392	* AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	393	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	394	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	395	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	396	* AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	397	* AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
AnnaBridge	145:64910690c574	398	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	399	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	400	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	401	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	402	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	403	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	404	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	405	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	406	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
AnnaBridge	145:64910690c574	407	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	408	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
AnnaBridge	145:64910690c574	409	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
AnnaBridge	145:64910690c574	410	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	411	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
AnnaBridge	145:64910690c574	412	* @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
AnnaBridge	145:64910690c574	413	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	414	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	145:64910690c574	415	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	416	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	145:64910690c574	417	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
AnnaBridge	145:64910690c574	418	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
AnnaBridge	145:64910690c574	419	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
AnnaBridge	145:64910690c574	420	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
AnnaBridge	145:64910690c574	421	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
AnnaBridge	145:64910690c574	422	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
AnnaBridge	145:64910690c574	423	*
AnnaBridge	145:64910690c574	424	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	425	* @retval None
AnnaBridge	145:64910690c574	426	*/
AnnaBridge	145:64910690c574	427	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	428	{
AnnaBridge	145:64910690c574	429	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	430	SET_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	145:64910690c574	431	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	432	tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	145:64910690c574	433	(void)tmpreg;
AnnaBridge	145:64910690c574	434	}
AnnaBridge	145:64910690c574	435
AnnaBridge	145:64910690c574	436	/**
AnnaBridge	145:64910690c574	437	* @brief Check if AHB1 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	438	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	439	* AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	440	* AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	441	* AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	442	* AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	443	* AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	444	* AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	445	* AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	446	* AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	447	* AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	448	* AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	449	* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	450	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	451	* AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	452	* AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	453	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	454	* AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	455	* AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	456	* AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	457	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	458	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	459	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	460	* AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	461	* AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	462	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	463	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	464	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	465	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	466	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	467	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	468	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	469	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	470	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
AnnaBridge	145:64910690c574	471	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	472	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
AnnaBridge	145:64910690c574	473	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
AnnaBridge	145:64910690c574	474	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	475	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
AnnaBridge	145:64910690c574	476	* @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
AnnaBridge	145:64910690c574	477	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	478	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	145:64910690c574	479	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	480	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	145:64910690c574	481	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
AnnaBridge	145:64910690c574	482	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
AnnaBridge	145:64910690c574	483	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
AnnaBridge	145:64910690c574	484	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
AnnaBridge	145:64910690c574	485	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
AnnaBridge	145:64910690c574	486	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
AnnaBridge	145:64910690c574	487	*
AnnaBridge	145:64910690c574	488	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	489	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	490	*/
AnnaBridge	145:64910690c574	491	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	492	{
AnnaBridge	145:64910690c574	493	return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	494	}
AnnaBridge	145:64910690c574	495
AnnaBridge	145:64910690c574	496	/**
AnnaBridge	145:64910690c574	497	* @brief Disable AHB1 peripherals clock.
AnnaBridge	145:64910690c574	498	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	499	* AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	500	* AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	501	* AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	502	* AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	503	* AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	504	* AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	505	* AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	506	* AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	507	* AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	508	* AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	509	* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	510	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	511	* AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	512	* AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	513	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	514	* AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	515	* AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	516	* AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	517	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	518	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	519	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	520	* AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	521	* AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
AnnaBridge	145:64910690c574	522	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	523	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	524	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	525	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	526	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	527	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	528	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	529	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	530	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
AnnaBridge	145:64910690c574	531	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	532	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
AnnaBridge	145:64910690c574	533	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
AnnaBridge	145:64910690c574	534	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	535	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
AnnaBridge	145:64910690c574	536	* @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
AnnaBridge	145:64910690c574	537	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	538	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	145:64910690c574	539	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	540	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	145:64910690c574	541	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
AnnaBridge	145:64910690c574	542	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
AnnaBridge	145:64910690c574	543	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
AnnaBridge	145:64910690c574	544	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
AnnaBridge	145:64910690c574	545	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
AnnaBridge	145:64910690c574	546	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
AnnaBridge	145:64910690c574	547	*
AnnaBridge	145:64910690c574	548	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	549	* @retval None
AnnaBridge	145:64910690c574	550	*/
AnnaBridge	145:64910690c574	551	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	552	{
AnnaBridge	145:64910690c574	553	CLEAR_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	145:64910690c574	554	}
AnnaBridge	145:64910690c574	555
AnnaBridge	145:64910690c574	556	/**
AnnaBridge	145:64910690c574	557	* @brief Force AHB1 peripherals reset.
AnnaBridge	145:64910690c574	558	* @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	559	* AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	560	* AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	561	* AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	562	* AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	563	* AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	564	* AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	565	* AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	566	* AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	567	* AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	568	* AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	569	* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	570	* AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	571	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	572	* AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	573	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	574	* AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	575	* AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
AnnaBridge	145:64910690c574	576	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	577	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	578	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	579	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	580	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	581	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	582	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	583	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	584	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	585	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
AnnaBridge	145:64910690c574	586	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	587	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
AnnaBridge	145:64910690c574	588	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
AnnaBridge	145:64910690c574	589	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	590	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	591	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	145:64910690c574	592	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	593	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	145:64910690c574	594	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
AnnaBridge	145:64910690c574	595	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
AnnaBridge	145:64910690c574	596	*
AnnaBridge	145:64910690c574	597	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	598	* @retval None
AnnaBridge	145:64910690c574	599	*/
AnnaBridge	145:64910690c574	600	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	601	{
AnnaBridge	145:64910690c574	602	SET_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	145:64910690c574	603	}
AnnaBridge	145:64910690c574	604
AnnaBridge	145:64910690c574	605	/**
AnnaBridge	145:64910690c574	606	* @brief Release AHB1 peripherals reset.
AnnaBridge	145:64910690c574	607	* @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	608	* AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	609	* AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	610	* AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	611	* AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	612	* AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	613	* AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	614	* AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	615	* AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	616	* AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	617	* AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	618	* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	619	* AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	620	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	621	* AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	622	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	623	* AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	624	* AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	625	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	626	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	627	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	628	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	629	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	630	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	631	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	632	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	633	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	634	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
AnnaBridge	145:64910690c574	635	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	636	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
AnnaBridge	145:64910690c574	637	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
AnnaBridge	145:64910690c574	638	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	639	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	640	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	145:64910690c574	641	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	642	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	145:64910690c574	643	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
AnnaBridge	145:64910690c574	644	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
AnnaBridge	145:64910690c574	645	*
AnnaBridge	145:64910690c574	646	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	647	* @retval None
AnnaBridge	145:64910690c574	648	*/
AnnaBridge	145:64910690c574	649	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	650	{
AnnaBridge	145:64910690c574	651	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	145:64910690c574	652	}
AnnaBridge	145:64910690c574	653
AnnaBridge	145:64910690c574	654	/**
AnnaBridge	145:64910690c574	655	* @brief Enable AHB1 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	656	* @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	657	* AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	658	* AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	659	* AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	660	* AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	661	* AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	662	* AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	663	* AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	664	* AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	665	* AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	666	* AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	667	* AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	668	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	669	* AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	670	* AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	671	* AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	672	* AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	673	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	674	* AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	675	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	676	* AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	677	* AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	678	* AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	679	* AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	680	* AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	681	* AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	682	* AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	683	* AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
AnnaBridge	145:64910690c574	684	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	685	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	686	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	687	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	688	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	689	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	690	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	691	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	692	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
AnnaBridge	145:64910690c574	693	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	694	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
AnnaBridge	145:64910690c574	695	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
AnnaBridge	145:64910690c574	696	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	697	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
AnnaBridge	145:64910690c574	698	* @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
AnnaBridge	145:64910690c574	699	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
AnnaBridge	145:64910690c574	700	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
AnnaBridge	145:64910690c574	701	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
AnnaBridge	145:64910690c574	702	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	703	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	145:64910690c574	704	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	705	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	145:64910690c574	706	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
AnnaBridge	145:64910690c574	707	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
AnnaBridge	145:64910690c574	708	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
AnnaBridge	145:64910690c574	709	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
AnnaBridge	145:64910690c574	710	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
AnnaBridge	145:64910690c574	711	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
AnnaBridge	145:64910690c574	712	*
AnnaBridge	145:64910690c574	713	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	714	* @retval None
AnnaBridge	145:64910690c574	715	*/
AnnaBridge	145:64910690c574	716	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	717	{
AnnaBridge	145:64910690c574	718	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	719	SET_BIT(RCC->AHB1LPENR, Periphs);
AnnaBridge	145:64910690c574	720	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	721	tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
AnnaBridge	145:64910690c574	722	(void)tmpreg;
AnnaBridge	145:64910690c574	723	}
AnnaBridge	145:64910690c574	724
AnnaBridge	145:64910690c574	725	/**
AnnaBridge	145:64910690c574	726	* @brief Disable AHB1 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	727	* @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	728	* AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	729	* AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	730	* AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	731	* AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	732	* AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	733	* AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	734	* AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	735	* AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	736	* AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	737	* AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	738	* AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	739	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	740	* AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	741	* AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	742	* AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	743	* AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	744	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	745	* AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	746	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	747	* AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	748	* AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	749	* AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	750	* AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	751	* AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	752	* AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	753	* AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	754	* AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
AnnaBridge	145:64910690c574	755	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	756	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	757	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	758	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	759	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	760	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	761	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	762	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	763	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
AnnaBridge	145:64910690c574	764	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	765	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
AnnaBridge	145:64910690c574	766	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
AnnaBridge	145:64910690c574	767	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	768	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
AnnaBridge	145:64910690c574	769	* @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
AnnaBridge	145:64910690c574	770	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
AnnaBridge	145:64910690c574	771	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
AnnaBridge	145:64910690c574	772	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
AnnaBridge	145:64910690c574	773	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	774	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	145:64910690c574	775	* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	776	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	145:64910690c574	777	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
AnnaBridge	145:64910690c574	778	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
AnnaBridge	145:64910690c574	779	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
AnnaBridge	145:64910690c574	780	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
AnnaBridge	145:64910690c574	781	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
AnnaBridge	145:64910690c574	782	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
AnnaBridge	145:64910690c574	783	*
AnnaBridge	145:64910690c574	784	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	785	* @retval None
AnnaBridge	145:64910690c574	786	*/
AnnaBridge	145:64910690c574	787	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	788	{
AnnaBridge	145:64910690c574	789	CLEAR_BIT(RCC->AHB1LPENR, Periphs);
AnnaBridge	145:64910690c574	790	}
AnnaBridge	145:64910690c574	791
AnnaBridge	145:64910690c574	792	/**
AnnaBridge	145:64910690c574	793	* @}
AnnaBridge	145:64910690c574	794	*/
AnnaBridge	145:64910690c574	795
AnnaBridge	145:64910690c574	796	#if defined(RCC_AHB2_SUPPORT)
AnnaBridge	145:64910690c574	797	/** @defgroup BUS_LL_EF_AHB2 AHB2
AnnaBridge	145:64910690c574	798	* @{
AnnaBridge	145:64910690c574	799	*/
AnnaBridge	145:64910690c574	800
AnnaBridge	145:64910690c574	801	/**
AnnaBridge	145:64910690c574	802	* @brief Enable AHB2 peripherals clock.
AnnaBridge	145:64910690c574	803	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	804	* AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	805	* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	806	* AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	807	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	808	* AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
AnnaBridge	145:64910690c574	809	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	810	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	811	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	145:64910690c574	812	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	813	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	814	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	815	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	816	*
AnnaBridge	145:64910690c574	817	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	818	* @retval None
AnnaBridge	145:64910690c574	819	*/
AnnaBridge	145:64910690c574	820	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	821	{
AnnaBridge	145:64910690c574	822	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	823	SET_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	145:64910690c574	824	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	825	tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	145:64910690c574	826	(void)tmpreg;
AnnaBridge	145:64910690c574	827	}
AnnaBridge	145:64910690c574	828
AnnaBridge	145:64910690c574	829	/**
AnnaBridge	145:64910690c574	830	* @brief Check if AHB2 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	831	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	832	* AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	833	* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	834	* AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	835	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	836	* AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	837	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	838	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	839	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	145:64910690c574	840	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	841	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	842	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	843	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	844	*
AnnaBridge	145:64910690c574	845	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	846	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	847	*/
AnnaBridge	145:64910690c574	848	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	849	{
AnnaBridge	145:64910690c574	850	return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	851	}
AnnaBridge	145:64910690c574	852
AnnaBridge	145:64910690c574	853	/**
AnnaBridge	145:64910690c574	854	* @brief Disable AHB2 peripherals clock.
AnnaBridge	145:64910690c574	855	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	856	* AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	857	* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	858	* AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	859	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	860	* AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
AnnaBridge	145:64910690c574	861	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	862	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	863	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	145:64910690c574	864	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	865	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	866	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	867	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	868	*
AnnaBridge	145:64910690c574	869	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	870	* @retval None
AnnaBridge	145:64910690c574	871	*/
AnnaBridge	145:64910690c574	872	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	873	{
AnnaBridge	145:64910690c574	874	CLEAR_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	145:64910690c574	875	}
AnnaBridge	145:64910690c574	876
AnnaBridge	145:64910690c574	877	/**
AnnaBridge	145:64910690c574	878	* @brief Force AHB2 peripherals reset.
AnnaBridge	145:64910690c574	879	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	880	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	881	* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	882	* AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	883	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	884	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
AnnaBridge	145:64910690c574	885	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	886	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	887	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	888	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	145:64910690c574	889	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	890	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	891	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	892	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	893	*
AnnaBridge	145:64910690c574	894	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	895	* @retval None
AnnaBridge	145:64910690c574	896	*/
AnnaBridge	145:64910690c574	897	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	898	{
AnnaBridge	145:64910690c574	899	SET_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	145:64910690c574	900	}
AnnaBridge	145:64910690c574	901
AnnaBridge	145:64910690c574	902	/**
AnnaBridge	145:64910690c574	903	* @brief Release AHB2 peripherals reset.
AnnaBridge	145:64910690c574	904	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	905	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	906	* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	907	* AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	908	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	909	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	910	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	911	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	912	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	913	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	145:64910690c574	914	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	915	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	916	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	917	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	918	*
AnnaBridge	145:64910690c574	919	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	920	* @retval None
AnnaBridge	145:64910690c574	921	*/
AnnaBridge	145:64910690c574	922	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	923	{
AnnaBridge	145:64910690c574	924	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	145:64910690c574	925	}
AnnaBridge	145:64910690c574	926
AnnaBridge	145:64910690c574	927	/**
AnnaBridge	145:64910690c574	928	* @brief Enable AHB2 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	929	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	930	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	931	* AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	932	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	933	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	934	* AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
AnnaBridge	145:64910690c574	935	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	936	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	937	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	145:64910690c574	938	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	939	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	940	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	941	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	942	*
AnnaBridge	145:64910690c574	943	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	944	* @retval None
AnnaBridge	145:64910690c574	945	*/
AnnaBridge	145:64910690c574	946	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	947	{
AnnaBridge	145:64910690c574	948	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	949	SET_BIT(RCC->AHB2LPENR, Periphs);
AnnaBridge	145:64910690c574	950	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	951	tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
AnnaBridge	145:64910690c574	952	(void)tmpreg;
AnnaBridge	145:64910690c574	953	}
AnnaBridge	145:64910690c574	954
AnnaBridge	145:64910690c574	955	/**
AnnaBridge	145:64910690c574	956	* @brief Disable AHB2 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	957	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	958	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	959	* AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	960	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	961	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	962	* AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
AnnaBridge	145:64910690c574	963	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	964	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	965	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	145:64910690c574	966	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	967	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	968	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
AnnaBridge	145:64910690c574	969	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	970	*
AnnaBridge	145:64910690c574	971	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	972	* @retval None
AnnaBridge	145:64910690c574	973	*/
AnnaBridge	145:64910690c574	974	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	975	{
AnnaBridge	145:64910690c574	976	CLEAR_BIT(RCC->AHB2LPENR, Periphs);
AnnaBridge	145:64910690c574	977	}
AnnaBridge	145:64910690c574	978
AnnaBridge	145:64910690c574	979	/**
AnnaBridge	145:64910690c574	980	* @}
AnnaBridge	145:64910690c574	981	*/
AnnaBridge	145:64910690c574	982	#endif /* RCC_AHB2_SUPPORT */
AnnaBridge	145:64910690c574	983
AnnaBridge	145:64910690c574	984	#if defined(RCC_AHB3_SUPPORT)
AnnaBridge	145:64910690c574	985	/** @defgroup BUS_LL_EF_AHB3 AHB3
AnnaBridge	145:64910690c574	986	* @{
AnnaBridge	145:64910690c574	987	*/
AnnaBridge	145:64910690c574	988
AnnaBridge	145:64910690c574	989	/**
AnnaBridge	145:64910690c574	990	* @brief Enable AHB3 peripherals clock.
AnnaBridge	145:64910690c574	991	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	992	* AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	993	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
AnnaBridge	145:64910690c574	994	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	995	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	145:64910690c574	996	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
AnnaBridge	145:64910690c574	997	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	145:64910690c574	998	*
AnnaBridge	145:64910690c574	999	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1000	* @retval None
AnnaBridge	145:64910690c574	1001	*/
AnnaBridge	145:64910690c574	1002	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1003	{
AnnaBridge	145:64910690c574	1004	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1005	SET_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	145:64910690c574	1006	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1007	tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	145:64910690c574	1008	(void)tmpreg;
AnnaBridge	145:64910690c574	1009	}
AnnaBridge	145:64910690c574	1010
AnnaBridge	145:64910690c574	1011	/**
AnnaBridge	145:64910690c574	1012	* @brief Check if AHB3 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	1013	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1014	* AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1015	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	1016	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1017	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	145:64910690c574	1018	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
AnnaBridge	145:64910690c574	1019	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	145:64910690c574	1020	*
AnnaBridge	145:64910690c574	1021	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1022	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	1023	*/
AnnaBridge	145:64910690c574	1024	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1025	{
AnnaBridge	145:64910690c574	1026	return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	1027	}
AnnaBridge	145:64910690c574	1028
AnnaBridge	145:64910690c574	1029	/**
AnnaBridge	145:64910690c574	1030	* @brief Disable AHB3 peripherals clock.
AnnaBridge	145:64910690c574	1031	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1032	* AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1033	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
AnnaBridge	145:64910690c574	1034	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1035	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	145:64910690c574	1036	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
AnnaBridge	145:64910690c574	1037	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	145:64910690c574	1038	*
AnnaBridge	145:64910690c574	1039	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1040	* @retval None
AnnaBridge	145:64910690c574	1041	*/
AnnaBridge	145:64910690c574	1042	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1043	{
AnnaBridge	145:64910690c574	1044	CLEAR_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	145:64910690c574	1045	}
AnnaBridge	145:64910690c574	1046
AnnaBridge	145:64910690c574	1047	/**
AnnaBridge	145:64910690c574	1048	* @brief Force AHB3 peripherals reset.
AnnaBridge	145:64910690c574	1049	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1050	* AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1051	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
AnnaBridge	145:64910690c574	1052	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1053	* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1054	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	145:64910690c574	1055	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
AnnaBridge	145:64910690c574	1056	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	145:64910690c574	1057	*
AnnaBridge	145:64910690c574	1058	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1059	* @retval None
AnnaBridge	145:64910690c574	1060	*/
AnnaBridge	145:64910690c574	1061	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1062	{
AnnaBridge	145:64910690c574	1063	SET_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	145:64910690c574	1064	}
AnnaBridge	145:64910690c574	1065
AnnaBridge	145:64910690c574	1066	/**
AnnaBridge	145:64910690c574	1067	* @brief Release AHB3 peripherals reset.
AnnaBridge	145:64910690c574	1068	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1069	* AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1070	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	1071	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1072	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1073	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	145:64910690c574	1074	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
AnnaBridge	145:64910690c574	1075	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	145:64910690c574	1076	*
AnnaBridge	145:64910690c574	1077	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1078	* @retval None
AnnaBridge	145:64910690c574	1079	*/
AnnaBridge	145:64910690c574	1080	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1081	{
AnnaBridge	145:64910690c574	1082	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	145:64910690c574	1083	}
AnnaBridge	145:64910690c574	1084
AnnaBridge	145:64910690c574	1085	/**
AnnaBridge	145:64910690c574	1086	* @brief Enable AHB3 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	1087	* @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1088	* AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1089	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
AnnaBridge	145:64910690c574	1090	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1091	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	145:64910690c574	1092	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
AnnaBridge	145:64910690c574	1093	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	145:64910690c574	1094	*
AnnaBridge	145:64910690c574	1095	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1096	* @retval None
AnnaBridge	145:64910690c574	1097	*/
AnnaBridge	145:64910690c574	1098	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	1099	{
AnnaBridge	145:64910690c574	1100	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1101	SET_BIT(RCC->AHB3LPENR, Periphs);
AnnaBridge	145:64910690c574	1102	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1103	tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
AnnaBridge	145:64910690c574	1104	(void)tmpreg;
AnnaBridge	145:64910690c574	1105	}
AnnaBridge	145:64910690c574	1106
AnnaBridge	145:64910690c574	1107	/**
AnnaBridge	145:64910690c574	1108	* @brief Disable AHB3 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	1109	* @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1110	* AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1111	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
AnnaBridge	145:64910690c574	1112	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1113	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	145:64910690c574	1114	* @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
AnnaBridge	145:64910690c574	1115	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	145:64910690c574	1116	*
AnnaBridge	145:64910690c574	1117	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1118	* @retval None
AnnaBridge	145:64910690c574	1119	*/
AnnaBridge	145:64910690c574	1120	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	1121	{
AnnaBridge	145:64910690c574	1122	CLEAR_BIT(RCC->AHB3LPENR, Periphs);
AnnaBridge	145:64910690c574	1123	}
AnnaBridge	145:64910690c574	1124
AnnaBridge	145:64910690c574	1125	/**
AnnaBridge	145:64910690c574	1126	* @}
AnnaBridge	145:64910690c574	1127	*/
AnnaBridge	145:64910690c574	1128	#endif /* RCC_AHB3_SUPPORT */
AnnaBridge	145:64910690c574	1129
AnnaBridge	145:64910690c574	1130	/** @defgroup BUS_LL_EF_APB1 APB1
AnnaBridge	145:64910690c574	1131	* @{
AnnaBridge	145:64910690c574	1132	*/
AnnaBridge	145:64910690c574	1133
AnnaBridge	145:64910690c574	1134	/**
AnnaBridge	145:64910690c574	1135	* @brief Enable APB1 peripherals clock.
AnnaBridge	145:64910690c574	1136	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1137	* APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1138	* APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1139	* APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1140	* APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1141	* APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1142	* APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1143	* APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1144	* APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1145	* APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1146	* APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1147	* APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1148	* APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1149	* APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1150	* APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1151	* APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1152	* APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1153	* APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1154	* APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1155	* APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1156	* APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1157	* APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1158	* APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1159	* APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1160	* APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1161	* APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1162	* APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1163	* APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1164	* APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1165	* APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1166	* APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock
AnnaBridge	145:64910690c574	1167	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1168	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
AnnaBridge	145:64910690c574	1169	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1170	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1171	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	145:64910690c574	1172	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge	145:64910690c574	1173	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge	145:64910690c574	1174	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
AnnaBridge	145:64910690c574	1175	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
AnnaBridge	145:64910690c574	1176	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
AnnaBridge	145:64910690c574	1177	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
AnnaBridge	145:64910690c574	1178	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1179	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1180	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
AnnaBridge	145:64910690c574	1181	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
AnnaBridge	145:64910690c574	1182	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1183	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1184	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1185	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1186	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1187	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	145:64910690c574	1188	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge	145:64910690c574	1189	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
AnnaBridge	145:64910690c574	1190	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
AnnaBridge	145:64910690c574	1191	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1192	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
AnnaBridge	145:64910690c574	1193	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
AnnaBridge	145:64910690c574	1194	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1195	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge	145:64910690c574	1196	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
AnnaBridge	145:64910690c574	1197	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
AnnaBridge	145:64910690c574	1198	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1199	*
AnnaBridge	145:64910690c574	1200	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1201	* @retval None
AnnaBridge	145:64910690c574	1202	*/
AnnaBridge	145:64910690c574	1203	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1204	{
AnnaBridge	145:64910690c574	1205	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1206	SET_BIT(RCC->APB1ENR, Periphs);
AnnaBridge	145:64910690c574	1207	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1208	tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
AnnaBridge	145:64910690c574	1209	(void)tmpreg;
AnnaBridge	145:64910690c574	1210	}
AnnaBridge	145:64910690c574	1211
AnnaBridge	145:64910690c574	1212	/**
AnnaBridge	145:64910690c574	1213	* @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	1214	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1215	* APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1216	* APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1217	* APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1218	* APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1219	* APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1220	* APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1221	* APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1222	* APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1223	* APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1224	* APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1225	* APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1226	* APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1227	* APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1228	* APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1229	* APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1230	* APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1231	* APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1232	* APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1233	* APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1234	* APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1235	* APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1236	* APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1237	* APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1238	* APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1239	* APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1240	* APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1241	* APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1242	* APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1243	* APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1244	* APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	1245	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1246	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
AnnaBridge	145:64910690c574	1247	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1248	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1249	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	145:64910690c574	1250	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge	145:64910690c574	1251	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge	145:64910690c574	1252	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
AnnaBridge	145:64910690c574	1253	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
AnnaBridge	145:64910690c574	1254	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
AnnaBridge	145:64910690c574	1255	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
AnnaBridge	145:64910690c574	1256	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1257	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1258	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
AnnaBridge	145:64910690c574	1259	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
AnnaBridge	145:64910690c574	1260	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1261	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1262	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1263	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1264	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1265	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	145:64910690c574	1266	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge	145:64910690c574	1267	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
AnnaBridge	145:64910690c574	1268	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
AnnaBridge	145:64910690c574	1269	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1270	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
AnnaBridge	145:64910690c574	1271	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
AnnaBridge	145:64910690c574	1272	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1273	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge	145:64910690c574	1274	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
AnnaBridge	145:64910690c574	1275	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
AnnaBridge	145:64910690c574	1276	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1277	*
AnnaBridge	145:64910690c574	1278	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1279	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	1280	*/
AnnaBridge	145:64910690c574	1281	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1282	{
AnnaBridge	145:64910690c574	1283	return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	1284	}
AnnaBridge	145:64910690c574	1285
AnnaBridge	145:64910690c574	1286	/**
AnnaBridge	145:64910690c574	1287	* @brief Disable APB1 peripherals clock.
AnnaBridge	145:64910690c574	1288	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1289	* APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1290	* APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1291	* APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1292	* APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1293	* APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1294	* APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1295	* APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1296	* APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1297	* APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1298	* APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1299	* APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1300	* APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1301	* APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1302	* APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1303	* APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1304	* APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1305	* APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1306	* APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1307	* APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1308	* APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1309	* APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1310	* APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1311	* APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1312	* APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1313	* APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1314	* APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1315	* APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1316	* APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1317	* APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1318	* APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock
AnnaBridge	145:64910690c574	1319	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1320	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
AnnaBridge	145:64910690c574	1321	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1322	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1323	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	145:64910690c574	1324	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge	145:64910690c574	1325	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge	145:64910690c574	1326	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
AnnaBridge	145:64910690c574	1327	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
AnnaBridge	145:64910690c574	1328	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
AnnaBridge	145:64910690c574	1329	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
AnnaBridge	145:64910690c574	1330	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1331	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1332	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
AnnaBridge	145:64910690c574	1333	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
AnnaBridge	145:64910690c574	1334	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1335	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1336	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1337	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1338	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1339	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	145:64910690c574	1340	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge	145:64910690c574	1341	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
AnnaBridge	145:64910690c574	1342	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
AnnaBridge	145:64910690c574	1343	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1344	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
AnnaBridge	145:64910690c574	1345	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
AnnaBridge	145:64910690c574	1346	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1347	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge	145:64910690c574	1348	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
AnnaBridge	145:64910690c574	1349	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
AnnaBridge	145:64910690c574	1350	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1351	*
AnnaBridge	145:64910690c574	1352	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1353	* @retval None
AnnaBridge	145:64910690c574	1354	*/
AnnaBridge	145:64910690c574	1355	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1356	{
AnnaBridge	145:64910690c574	1357	CLEAR_BIT(RCC->APB1ENR, Periphs);
AnnaBridge	145:64910690c574	1358	}
AnnaBridge	145:64910690c574	1359
AnnaBridge	145:64910690c574	1360	/**
AnnaBridge	145:64910690c574	1361	* @brief Force APB1 peripherals reset.
AnnaBridge	145:64910690c574	1362	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1363	* APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1364	* APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1365	* APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1366	* APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1367	* APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1368	* APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1369	* APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1370	* APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1371	* APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1372	* APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1373	* APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1374	* APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1375	* APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1376	* APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1377	* APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1378	* APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1379	* APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1380	* APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1381	* APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1382	* APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1383	* APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1384	* APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1385	* APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1386	* APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1387	* APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1388	* APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1389	* APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1390	* APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1391	* APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
AnnaBridge	145:64910690c574	1392	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1393	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
AnnaBridge	145:64910690c574	1394	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1395	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1396	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	145:64910690c574	1397	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge	145:64910690c574	1398	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge	145:64910690c574	1399	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
AnnaBridge	145:64910690c574	1400	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
AnnaBridge	145:64910690c574	1401	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
AnnaBridge	145:64910690c574	1402	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
AnnaBridge	145:64910690c574	1403	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1404	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1405	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
AnnaBridge	145:64910690c574	1406	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
AnnaBridge	145:64910690c574	1407	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1408	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1409	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1410	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1411	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1412	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	145:64910690c574	1413	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge	145:64910690c574	1414	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
AnnaBridge	145:64910690c574	1415	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
AnnaBridge	145:64910690c574	1416	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1417	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
AnnaBridge	145:64910690c574	1418	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
AnnaBridge	145:64910690c574	1419	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1420	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge	145:64910690c574	1421	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
AnnaBridge	145:64910690c574	1422	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
AnnaBridge	145:64910690c574	1423	*
AnnaBridge	145:64910690c574	1424	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1425	* @retval None
AnnaBridge	145:64910690c574	1426	*/
AnnaBridge	145:64910690c574	1427	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1428	{
AnnaBridge	145:64910690c574	1429	SET_BIT(RCC->APB1RSTR, Periphs);
AnnaBridge	145:64910690c574	1430	}
AnnaBridge	145:64910690c574	1431
AnnaBridge	145:64910690c574	1432	/**
AnnaBridge	145:64910690c574	1433	* @brief Release APB1 peripherals reset.
AnnaBridge	145:64910690c574	1434	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1435	* APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1436	* APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1437	* APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1438	* APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1439	* APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1440	* APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1441	* APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1442	* APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1443	* APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1444	* APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1445	* APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1446	* APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1447	* APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1448	* APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1449	* APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1450	* APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1451	* APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1452	* APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1453	* APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1454	* APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1455	* APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1456	* APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1457	* APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1458	* APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1459	* APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1460	* APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1461	* APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1462	* APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1463	* APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	1464	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1465	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
AnnaBridge	145:64910690c574	1466	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1467	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1468	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	145:64910690c574	1469	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge	145:64910690c574	1470	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge	145:64910690c574	1471	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
AnnaBridge	145:64910690c574	1472	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
AnnaBridge	145:64910690c574	1473	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
AnnaBridge	145:64910690c574	1474	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
AnnaBridge	145:64910690c574	1475	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1476	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1477	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
AnnaBridge	145:64910690c574	1478	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
AnnaBridge	145:64910690c574	1479	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1480	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1481	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1482	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1483	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1484	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	145:64910690c574	1485	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge	145:64910690c574	1486	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
AnnaBridge	145:64910690c574	1487	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
AnnaBridge	145:64910690c574	1488	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1489	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
AnnaBridge	145:64910690c574	1490	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
AnnaBridge	145:64910690c574	1491	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1492	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge	145:64910690c574	1493	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
AnnaBridge	145:64910690c574	1494	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
AnnaBridge	145:64910690c574	1495	*
AnnaBridge	145:64910690c574	1496	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1497	* @retval None
AnnaBridge	145:64910690c574	1498	*/
AnnaBridge	145:64910690c574	1499	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1500	{
AnnaBridge	145:64910690c574	1501	CLEAR_BIT(RCC->APB1RSTR, Periphs);
AnnaBridge	145:64910690c574	1502	}
AnnaBridge	145:64910690c574	1503
AnnaBridge	145:64910690c574	1504	/**
AnnaBridge	145:64910690c574	1505	* @brief Enable APB1 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	1506	* @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1507	* APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1508	* APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1509	* APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1510	* APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1511	* APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1512	* APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1513	* APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1514	* APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1515	* APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1516	* APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1517	* APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1518	* APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1519	* APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1520	* APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1521	* APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1522	* APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1523	* APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1524	* APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1525	* APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1526	* APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1527	* APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1528	* APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1529	* APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1530	* APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1531	* APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1532	* APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1533	* APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1534	* APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1535	* APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1536	* APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower
AnnaBridge	145:64910690c574	1537	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1538	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
AnnaBridge	145:64910690c574	1539	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1540	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1541	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	145:64910690c574	1542	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge	145:64910690c574	1543	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge	145:64910690c574	1544	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
AnnaBridge	145:64910690c574	1545	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
AnnaBridge	145:64910690c574	1546	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
AnnaBridge	145:64910690c574	1547	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
AnnaBridge	145:64910690c574	1548	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1549	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1550	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
AnnaBridge	145:64910690c574	1551	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
AnnaBridge	145:64910690c574	1552	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1553	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1554	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1555	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1556	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1557	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	145:64910690c574	1558	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge	145:64910690c574	1559	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
AnnaBridge	145:64910690c574	1560	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
AnnaBridge	145:64910690c574	1561	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1562	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
AnnaBridge	145:64910690c574	1563	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
AnnaBridge	145:64910690c574	1564	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1565	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge	145:64910690c574	1566	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
AnnaBridge	145:64910690c574	1567	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
AnnaBridge	145:64910690c574	1568	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1569	*
AnnaBridge	145:64910690c574	1570	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1571	* @retval None
AnnaBridge	145:64910690c574	1572	*/
AnnaBridge	145:64910690c574	1573	__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	1574	{
AnnaBridge	145:64910690c574	1575	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1576	SET_BIT(RCC->APB1LPENR, Periphs);
AnnaBridge	145:64910690c574	1577	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1578	tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
AnnaBridge	145:64910690c574	1579	(void)tmpreg;
AnnaBridge	145:64910690c574	1580	}
AnnaBridge	145:64910690c574	1581
AnnaBridge	145:64910690c574	1582	/**
AnnaBridge	145:64910690c574	1583	* @brief Disable APB1 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	1584	* @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1585	* APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1586	* APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1587	* APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1588	* APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1589	* APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1590	* APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1591	* APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1592	* APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1593	* APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1594	* APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1595	* APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1596	* APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1597	* APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1598	* APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1599	* APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1600	* APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1601	* APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1602	* APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1603	* APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1604	* APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1605	* APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1606	* APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1607	* APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1608	* APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1609	* APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1610	* APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1611	* APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1612	* APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1613	* APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	1614	* APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower
AnnaBridge	145:64910690c574	1615	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1616	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
AnnaBridge	145:64910690c574	1617	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1618	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1619	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	145:64910690c574	1620	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
AnnaBridge	145:64910690c574	1621	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
AnnaBridge	145:64910690c574	1622	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
AnnaBridge	145:64910690c574	1623	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
AnnaBridge	145:64910690c574	1624	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
AnnaBridge	145:64910690c574	1625	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
AnnaBridge	145:64910690c574	1626	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1627	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1628	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
AnnaBridge	145:64910690c574	1629	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
AnnaBridge	145:64910690c574	1630	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1631	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1632	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1633	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1634	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1635	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	145:64910690c574	1636	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
AnnaBridge	145:64910690c574	1637	* @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
AnnaBridge	145:64910690c574	1638	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
AnnaBridge	145:64910690c574	1639	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1640	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
AnnaBridge	145:64910690c574	1641	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
AnnaBridge	145:64910690c574	1642	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1643	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
AnnaBridge	145:64910690c574	1644	* @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
AnnaBridge	145:64910690c574	1645	* @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
AnnaBridge	145:64910690c574	1646	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1647	*
AnnaBridge	145:64910690c574	1648	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1649	* @retval None
AnnaBridge	145:64910690c574	1650	*/
AnnaBridge	145:64910690c574	1651	__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	1652	{
AnnaBridge	145:64910690c574	1653	CLEAR_BIT(RCC->APB1LPENR, Periphs);
AnnaBridge	145:64910690c574	1654	}
AnnaBridge	145:64910690c574	1655
AnnaBridge	145:64910690c574	1656	/**
AnnaBridge	145:64910690c574	1657	* @}
AnnaBridge	145:64910690c574	1658	*/
AnnaBridge	145:64910690c574	1659
AnnaBridge	145:64910690c574	1660	/** @defgroup BUS_LL_EF_APB2 APB2
AnnaBridge	145:64910690c574	1661	* @{
AnnaBridge	145:64910690c574	1662	*/
AnnaBridge	145:64910690c574	1663
AnnaBridge	145:64910690c574	1664	/**
AnnaBridge	145:64910690c574	1665	* @brief Enable APB2 peripherals clock.
AnnaBridge	145:64910690c574	1666	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1667	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1668	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1669	* APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1670	* APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1671	* APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1672	* APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1673	* APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1674	* APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1675	* APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1676	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1677	* APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1678	* APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1679	* APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1680	* APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1681	* APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1682	* APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1683	* APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1684	* APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1685	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1686	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1687	* APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1688	* APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1689	* APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1690	* APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock
AnnaBridge	145:64910690c574	1691	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1692	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1693	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1694	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1695	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
AnnaBridge	145:64910690c574	1696	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
AnnaBridge	145:64910690c574	1697	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
AnnaBridge	145:64910690c574	1698	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge	145:64910690c574	1699	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
AnnaBridge	145:64910690c574	1700	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
AnnaBridge	145:64910690c574	1701	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
AnnaBridge	145:64910690c574	1702	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1703	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
AnnaBridge	145:64910690c574	1704	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1705	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
AnnaBridge	145:64910690c574	1706	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
AnnaBridge	145:64910690c574	1707	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
AnnaBridge	145:64910690c574	1708	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
AnnaBridge	145:64910690c574	1709	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
AnnaBridge	145:64910690c574	1710	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
AnnaBridge	145:64910690c574	1711	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
AnnaBridge	145:64910690c574	1712	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1713	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	145:64910690c574	1714	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1715	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	145:64910690c574	1716	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
AnnaBridge	145:64910690c574	1717
AnnaBridge	145:64910690c574	1718	*
AnnaBridge	145:64910690c574	1719	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1720	* @retval None
AnnaBridge	145:64910690c574	1721	*/
AnnaBridge	145:64910690c574	1722	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1723	{
AnnaBridge	145:64910690c574	1724	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1725	SET_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	145:64910690c574	1726	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1727	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	145:64910690c574	1728	(void)tmpreg;
AnnaBridge	145:64910690c574	1729	}
AnnaBridge	145:64910690c574	1730
AnnaBridge	145:64910690c574	1731	/**
AnnaBridge	145:64910690c574	1732	* @brief Check if APB2 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	1733	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1734	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1735	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1736	* APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1737	* APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1738	* APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1739	* APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1740	* APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1741	* APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1742	* APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1743	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1744	* APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1745	* APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1746	* APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1747	* APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1748	* APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1749	* APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1750	* APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1751	* APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1752	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1753	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1754	* APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1755	* APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1756	* APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1757	* APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	1758	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1759	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1760	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1761	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1762	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
AnnaBridge	145:64910690c574	1763	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
AnnaBridge	145:64910690c574	1764	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
AnnaBridge	145:64910690c574	1765	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge	145:64910690c574	1766	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
AnnaBridge	145:64910690c574	1767	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
AnnaBridge	145:64910690c574	1768	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
AnnaBridge	145:64910690c574	1769	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1770	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
AnnaBridge	145:64910690c574	1771	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1772	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
AnnaBridge	145:64910690c574	1773	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
AnnaBridge	145:64910690c574	1774	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
AnnaBridge	145:64910690c574	1775	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
AnnaBridge	145:64910690c574	1776	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
AnnaBridge	145:64910690c574	1777	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
AnnaBridge	145:64910690c574	1778	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
AnnaBridge	145:64910690c574	1779	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1780	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	145:64910690c574	1781	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1782	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	145:64910690c574	1783	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
AnnaBridge	145:64910690c574	1784	*
AnnaBridge	145:64910690c574	1785	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1786	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	1787	*/
AnnaBridge	145:64910690c574	1788	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1789	{
AnnaBridge	145:64910690c574	1790	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	1791	}
AnnaBridge	145:64910690c574	1792
AnnaBridge	145:64910690c574	1793	/**
AnnaBridge	145:64910690c574	1794	* @brief Disable APB2 peripherals clock.
AnnaBridge	145:64910690c574	1795	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1796	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1797	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1798	* APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1799	* APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1800	* APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1801	* APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1802	* APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1803	* APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1804	* APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1805	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1806	* APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1807	* APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1808	* APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1809	* APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1810	* APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1811	* APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1812	* APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1813	* APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1814	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1815	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1816	* APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1817	* APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1818	* APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1819	* APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock
AnnaBridge	145:64910690c574	1820	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1821	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1822	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1823	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1824	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
AnnaBridge	145:64910690c574	1825	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
AnnaBridge	145:64910690c574	1826	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
AnnaBridge	145:64910690c574	1827	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge	145:64910690c574	1828	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
AnnaBridge	145:64910690c574	1829	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
AnnaBridge	145:64910690c574	1830	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
AnnaBridge	145:64910690c574	1831	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1832	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
AnnaBridge	145:64910690c574	1833	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1834	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
AnnaBridge	145:64910690c574	1835	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
AnnaBridge	145:64910690c574	1836	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
AnnaBridge	145:64910690c574	1837	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
AnnaBridge	145:64910690c574	1838	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
AnnaBridge	145:64910690c574	1839	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
AnnaBridge	145:64910690c574	1840	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
AnnaBridge	145:64910690c574	1841	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1842	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	145:64910690c574	1843	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1844	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	145:64910690c574	1845	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
AnnaBridge	145:64910690c574	1846	*
AnnaBridge	145:64910690c574	1847	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1848	* @retval None
AnnaBridge	145:64910690c574	1849	*/
AnnaBridge	145:64910690c574	1850	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1851	{
AnnaBridge	145:64910690c574	1852	CLEAR_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	145:64910690c574	1853	}
AnnaBridge	145:64910690c574	1854
AnnaBridge	145:64910690c574	1855	/**
AnnaBridge	145:64910690c574	1856	* @brief Force APB2 peripherals reset.
AnnaBridge	145:64910690c574	1857	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1858	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1859	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1860	* APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1861	* APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1862	* APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1863	* APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1864	* APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1865	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1866	* APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1867	* APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1868	* APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1869	* APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1870	* APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1871	* APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1872	* APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1873	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1874	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1875	* APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1876	* APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1877	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1878	* APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset
AnnaBridge	145:64910690c574	1879	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1880	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1881	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1882	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1883	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1884	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
AnnaBridge	145:64910690c574	1885	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
AnnaBridge	145:64910690c574	1886	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
AnnaBridge	145:64910690c574	1887	* @arg @ref LL_APB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	1888	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
AnnaBridge	145:64910690c574	1889	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1890	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
AnnaBridge	145:64910690c574	1891	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1892	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
AnnaBridge	145:64910690c574	1893	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
AnnaBridge	145:64910690c574	1894	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
AnnaBridge	145:64910690c574	1895	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
AnnaBridge	145:64910690c574	1896	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
AnnaBridge	145:64910690c574	1897	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
AnnaBridge	145:64910690c574	1898	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1899	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	145:64910690c574	1900	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1901	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	145:64910690c574	1902	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
AnnaBridge	145:64910690c574	1903	*
AnnaBridge	145:64910690c574	1904	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1905	* @retval None
AnnaBridge	145:64910690c574	1906	*/
AnnaBridge	145:64910690c574	1907	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1908	{
AnnaBridge	145:64910690c574	1909	SET_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	145:64910690c574	1910	}
AnnaBridge	145:64910690c574	1911
AnnaBridge	145:64910690c574	1912	/**
AnnaBridge	145:64910690c574	1913	* @brief Release APB2 peripherals reset.
AnnaBridge	145:64910690c574	1914	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1915	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1916	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1917	* APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1918	* APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1919	* APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1920	* APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1921	* APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1922	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1923	* APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1924	* APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1925	* APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1926	* APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1927	* APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1928	* APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1929	* APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1930	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1931	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1932	* APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1933	* APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1934	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1935	* APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	1936	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1937	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1938	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1939	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1940	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1941	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
AnnaBridge	145:64910690c574	1942	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
AnnaBridge	145:64910690c574	1943	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
AnnaBridge	145:64910690c574	1944	* @arg @ref LL_APB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	1945	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
AnnaBridge	145:64910690c574	1946	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1947	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
AnnaBridge	145:64910690c574	1948	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1949	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
AnnaBridge	145:64910690c574	1950	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
AnnaBridge	145:64910690c574	1951	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
AnnaBridge	145:64910690c574	1952	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
AnnaBridge	145:64910690c574	1953	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
AnnaBridge	145:64910690c574	1954	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
AnnaBridge	145:64910690c574	1955	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
AnnaBridge	145:64910690c574	1956	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1957	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	145:64910690c574	1958	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1959	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	145:64910690c574	1960	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
AnnaBridge	145:64910690c574	1961	*
AnnaBridge	145:64910690c574	1962	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1963	* @retval None
AnnaBridge	145:64910690c574	1964	*/
AnnaBridge	145:64910690c574	1965	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1966	{
AnnaBridge	145:64910690c574	1967	CLEAR_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	145:64910690c574	1968	}
AnnaBridge	145:64910690c574	1969
AnnaBridge	145:64910690c574	1970	/**
AnnaBridge	145:64910690c574	1971	* @brief Enable APB2 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	1972	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1973	* APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1974	* APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1975	* APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1976	* APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1977	* APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1978	* APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1979	* APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1980	* APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1981	* APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1982	* APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1983	* APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1984	* APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1985	* APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1986	* APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1987	* APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1988	* APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1989	* APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1990	* APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1991	* APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1992	* APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1993	* APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1994	* APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1995	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1996	* APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
AnnaBridge	145:64910690c574	1997	* APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower
AnnaBridge	145:64910690c574	1998	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1999	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	2000	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	2001	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	2002	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
AnnaBridge	145:64910690c574	2003	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
AnnaBridge	145:64910690c574	2004	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
AnnaBridge	145:64910690c574	2005	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge	145:64910690c574	2006	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
AnnaBridge	145:64910690c574	2007	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
AnnaBridge	145:64910690c574	2008	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
AnnaBridge	145:64910690c574	2009	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	2010	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
AnnaBridge	145:64910690c574	2011	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	2012	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
AnnaBridge	145:64910690c574	2013	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
AnnaBridge	145:64910690c574	2014	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
AnnaBridge	145:64910690c574	2015	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
AnnaBridge	145:64910690c574	2016	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
AnnaBridge	145:64910690c574	2017	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
AnnaBridge	145:64910690c574	2018	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
AnnaBridge	145:64910690c574	2019	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	2020	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	145:64910690c574	2021	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	2022	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	145:64910690c574	2023	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
AnnaBridge	145:64910690c574	2024	*
AnnaBridge	145:64910690c574	2025	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2026	* @retval None
AnnaBridge	145:64910690c574	2027	*/
AnnaBridge	145:64910690c574	2028	__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	2029	{
AnnaBridge	145:64910690c574	2030	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	2031	SET_BIT(RCC->APB2LPENR, Periphs);
AnnaBridge	145:64910690c574	2032	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	2033	tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
AnnaBridge	145:64910690c574	2034	(void)tmpreg;
AnnaBridge	145:64910690c574	2035	}
AnnaBridge	145:64910690c574	2036
AnnaBridge	145:64910690c574	2037	/**
AnnaBridge	145:64910690c574	2038	* @brief Disable APB2 peripheral clocks in low-power mode
AnnaBridge	145:64910690c574	2039	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2040	* APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2041	* APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2042	* APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2043	* APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2044	* APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2045	* APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2046	* APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2047	* APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2048	* APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2049	* APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2050	* APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2051	* APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2052	* APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2053	* APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2054	* APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2055	* APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2056	* APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2057	* APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2058	* APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2059	* APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2060	* APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2061	* APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2062	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2063	* APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
AnnaBridge	145:64910690c574	2064	* APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower
AnnaBridge	145:64910690c574	2065	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	2066	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	2067	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	2068	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	2069	* @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
AnnaBridge	145:64910690c574	2070	* @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
AnnaBridge	145:64910690c574	2071	* @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
AnnaBridge	145:64910690c574	2072	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
AnnaBridge	145:64910690c574	2073	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
AnnaBridge	145:64910690c574	2074	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
AnnaBridge	145:64910690c574	2075	* @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
AnnaBridge	145:64910690c574	2076	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	2077	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
AnnaBridge	145:64910690c574	2078	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	2079	* @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
AnnaBridge	145:64910690c574	2080	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
AnnaBridge	145:64910690c574	2081	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
AnnaBridge	145:64910690c574	2082	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
AnnaBridge	145:64910690c574	2083	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
AnnaBridge	145:64910690c574	2084	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
AnnaBridge	145:64910690c574	2085	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
AnnaBridge	145:64910690c574	2086	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	2087	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	145:64910690c574	2088	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	2089	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	145:64910690c574	2090	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
AnnaBridge	145:64910690c574	2091	*
AnnaBridge	145:64910690c574	2092	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	2093	* @retval None
AnnaBridge	145:64910690c574	2094	*/
AnnaBridge	145:64910690c574	2095	__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
AnnaBridge	145:64910690c574	2096	{
AnnaBridge	145:64910690c574	2097	CLEAR_BIT(RCC->APB2LPENR, Periphs);
AnnaBridge	145:64910690c574	2098	}
AnnaBridge	145:64910690c574	2099
AnnaBridge	145:64910690c574	2100	/**
AnnaBridge	145:64910690c574	2101	* @}
AnnaBridge	145:64910690c574	2102	*/
AnnaBridge	145:64910690c574	2103
AnnaBridge	145:64910690c574	2104	/**
AnnaBridge	145:64910690c574	2105	* @}
AnnaBridge	145:64910690c574	2106	*/
AnnaBridge	145:64910690c574	2107
AnnaBridge	145:64910690c574	2108	/**
AnnaBridge	145:64910690c574	2109	* @}
AnnaBridge	145:64910690c574	2110	*/
AnnaBridge	145:64910690c574	2111
AnnaBridge	145:64910690c574	2112	#endif /* defined(RCC) */
AnnaBridge	145:64910690c574	2113
AnnaBridge	145:64910690c574	2114	/**
AnnaBridge	145:64910690c574	2115	* @}
AnnaBridge	145:64910690c574	2116	*/
AnnaBridge	145:64910690c574	2117
AnnaBridge	145:64910690c574	2118	#ifdef __cplusplus
AnnaBridge	145:64910690c574	2119	}
AnnaBridge	145:64910690c574	2120	#endif
AnnaBridge	145:64910690c574	2121
AnnaBridge	145:64910690c574	2122	#endif /* __STM32F4xx_LL_BUS_H */
AnnaBridge	145:64910690c574	2123
AnnaBridge	145:64910690c574	2124	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/