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TARGET_SDT32620B/TOOLCHAIN_IAR/tmr_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21839 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_TMR_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_TMR_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t ctrl; /* 0x0000 Timer Control Register */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t count32; /* 0x0004 Timer [32 bit] Current Count Value */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t term_cnt32; /* 0x0008 Timer [32 bit] Terminal Count Setting */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t pwm_cap32; /* 0x000C Timer [32 bit] PWM Compare Setting or Capture/Measure Value */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t count16_0; /* 0x0010 Timer [16 bit] Current Count Value, 16-bit Timer 0 */
AnnaBridge 167:84c0a372a020 76 __IO uint32_t term_cnt16_0; /* 0x0014 Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */
AnnaBridge 167:84c0a372a020 77 __IO uint32_t count16_1; /* 0x0018 Timer [16 bit] Current Count Value, 16-bit Timer 1 */
AnnaBridge 167:84c0a372a020 78 __IO uint32_t term_cnt16_1; /* 0x001C Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */
AnnaBridge 167:84c0a372a020 79 __IO uint32_t intfl; /* 0x0020 Timer Interrupt Flags */
AnnaBridge 167:84c0a372a020 80 __IO uint32_t inten; /* 0x0024 Timer Interrupt Enable/Disable Settings */
AnnaBridge 167:84c0a372a020 81 } mxc_tmr_regs_t;
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83
AnnaBridge 167:84c0a372a020 84 /*
AnnaBridge 167:84c0a372a020 85 Register offsets for module TMR.
AnnaBridge 167:84c0a372a020 86 */
AnnaBridge 167:84c0a372a020 87
AnnaBridge 167:84c0a372a020 88 #define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 89 #define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 90 #define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 91 #define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 92 #define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 93 #define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL)
AnnaBridge 167:84c0a372a020 94 #define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL)
AnnaBridge 167:84c0a372a020 95 #define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL)
AnnaBridge 167:84c0a372a020 96 #define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL)
AnnaBridge 167:84c0a372a020 97 #define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL)
AnnaBridge 167:84c0a372a020 98
AnnaBridge 167:84c0a372a020 99
AnnaBridge 167:84c0a372a020 100 /*
AnnaBridge 167:84c0a372a020 101 Field positions and masks for module TMR.
AnnaBridge 167:84c0a372a020 102 */
AnnaBridge 167:84c0a372a020 103
AnnaBridge 167:84c0a372a020 104 #define MXC_F_TMR_CTRL_MODE_POS 0
AnnaBridge 167:84c0a372a020 105 #define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 106 #define MXC_F_TMR_CTRL_TMR2X16_POS 3
AnnaBridge 167:84c0a372a020 107 #define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
AnnaBridge 167:84c0a372a020 108 #define MXC_F_TMR_CTRL_PRESCALE_POS 4
AnnaBridge 167:84c0a372a020 109 #define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 110 #define MXC_F_TMR_CTRL_POLARITY_POS 8
AnnaBridge 167:84c0a372a020 111 #define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
AnnaBridge 167:84c0a372a020 112 #define MXC_F_TMR_CTRL_ENABLE0_POS 12
AnnaBridge 167:84c0a372a020 113 #define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
AnnaBridge 167:84c0a372a020 114 #define MXC_F_TMR_CTRL_ENABLE1_POS 13
AnnaBridge 167:84c0a372a020 115 #define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
AnnaBridge 167:84c0a372a020 116
AnnaBridge 167:84c0a372a020 117 #define MXC_F_TMR_COUNT16_0_VALUE_POS 0
AnnaBridge 167:84c0a372a020 118 #define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
AnnaBridge 167:84c0a372a020 119
AnnaBridge 167:84c0a372a020 120 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0
AnnaBridge 167:84c0a372a020 121 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
AnnaBridge 167:84c0a372a020 122
AnnaBridge 167:84c0a372a020 123 #define MXC_F_TMR_COUNT16_1_VALUE_POS 0
AnnaBridge 167:84c0a372a020 124 #define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
AnnaBridge 167:84c0a372a020 125
AnnaBridge 167:84c0a372a020 126 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0
AnnaBridge 167:84c0a372a020 127 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
AnnaBridge 167:84c0a372a020 128
AnnaBridge 167:84c0a372a020 129 #define MXC_F_TMR_INTFL_TIMER0_POS 0
AnnaBridge 167:84c0a372a020 130 #define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
AnnaBridge 167:84c0a372a020 131 #define MXC_F_TMR_INTFL_TIMER1_POS 1
AnnaBridge 167:84c0a372a020 132 #define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
AnnaBridge 167:84c0a372a020 133
AnnaBridge 167:84c0a372a020 134 #define MXC_F_TMR_INTEN_TIMER0_POS 0
AnnaBridge 167:84c0a372a020 135 #define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
AnnaBridge 167:84c0a372a020 136 #define MXC_F_TMR_INTEN_TIMER1_POS 1
AnnaBridge 167:84c0a372a020 137 #define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
AnnaBridge 167:84c0a372a020 138
AnnaBridge 167:84c0a372a020 139
AnnaBridge 167:84c0a372a020 140
AnnaBridge 167:84c0a372a020 141 /*
AnnaBridge 167:84c0a372a020 142 Field values and shifted values for module TMR.
AnnaBridge 167:84c0a372a020 143 */
AnnaBridge 167:84c0a372a020 144
AnnaBridge 167:84c0a372a020 145 #define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 146 #define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 147 #define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 148 #define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 149 #define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL))
AnnaBridge 167:84c0a372a020 150 #define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL))
AnnaBridge 167:84c0a372a020 151 #define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL))
AnnaBridge 167:84c0a372a020 152 #define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL))
AnnaBridge 167:84c0a372a020 153
AnnaBridge 167:84c0a372a020 154 #define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 155 #define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 156 #define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 157 #define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 158 #define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 159 #define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 160 #define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 161 #define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS))
AnnaBridge 167:84c0a372a020 162
AnnaBridge 167:84c0a372a020 163 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 164 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 165 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 166 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 167 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL))
AnnaBridge 167:84c0a372a020 168 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL))
AnnaBridge 167:84c0a372a020 169 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL))
AnnaBridge 167:84c0a372a020 170 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL))
AnnaBridge 167:84c0a372a020 171 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL))
AnnaBridge 167:84c0a372a020 172 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL))
AnnaBridge 167:84c0a372a020 173 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL))
AnnaBridge 167:84c0a372a020 174 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL))
AnnaBridge 167:84c0a372a020 175 #define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL))
AnnaBridge 167:84c0a372a020 176
AnnaBridge 167:84c0a372a020 177 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 178 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 179 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 180 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 181 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 182 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 183 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 184 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 185 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 186 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 187 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 188 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 189 #define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS))
AnnaBridge 167:84c0a372a020 190
AnnaBridge 167:84c0a372a020 191
AnnaBridge 167:84c0a372a020 192 /*
AnnaBridge 167:84c0a372a020 193 * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module
AnnaBridge 167:84c0a372a020 194 * is in dual 16-bit timer mode.
AnnaBridge 167:84c0a372a020 195 */
AnnaBridge 167:84c0a372a020 196
AnnaBridge 167:84c0a372a020 197 #define MXC_F_TMR_CTRL_MODE_16_0_POS 0
AnnaBridge 167:84c0a372a020 198 #define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS))
AnnaBridge 167:84c0a372a020 199
AnnaBridge 167:84c0a372a020 200 #define MXC_F_TMR_CTRL_MODE_16_1_POS 1
AnnaBridge 167:84c0a372a020 201 #define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS))
AnnaBridge 167:84c0a372a020 202
AnnaBridge 167:84c0a372a020 203
AnnaBridge 167:84c0a372a020 204 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 205 }
AnnaBridge 167:84c0a372a020 206 #endif
AnnaBridge 167:84c0a372a020 207
AnnaBridge 167:84c0a372a020 208 #endif /* _MXC_TMR_REGS_H_ */
AnnaBridge 167:84c0a372a020 209