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TARGET_SDT32620B/TOOLCHAIN_IAR/ioman_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 167:84c0a372a020 | 1 | /******************************************************************************* |
| AnnaBridge | 167:84c0a372a020 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| AnnaBridge | 167:84c0a372a020 | 3 | * |
| AnnaBridge | 167:84c0a372a020 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| AnnaBridge | 167:84c0a372a020 | 5 | * copy of this software and associated documentation files (the "Software"), |
| AnnaBridge | 167:84c0a372a020 | 6 | * to deal in the Software without restriction, including without limitation |
| AnnaBridge | 167:84c0a372a020 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| AnnaBridge | 167:84c0a372a020 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| AnnaBridge | 167:84c0a372a020 | 9 | * Software is furnished to do so, subject to the following conditions: |
| AnnaBridge | 167:84c0a372a020 | 10 | * |
| AnnaBridge | 167:84c0a372a020 | 11 | * The above copyright notice and this permission notice shall be included |
| AnnaBridge | 167:84c0a372a020 | 12 | * in all copies or substantial portions of the Software. |
| AnnaBridge | 167:84c0a372a020 | 13 | * |
| AnnaBridge | 167:84c0a372a020 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| AnnaBridge | 167:84c0a372a020 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| AnnaBridge | 167:84c0a372a020 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| AnnaBridge | 167:84c0a372a020 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| AnnaBridge | 167:84c0a372a020 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| AnnaBridge | 167:84c0a372a020 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| AnnaBridge | 167:84c0a372a020 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| AnnaBridge | 167:84c0a372a020 | 21 | * |
| AnnaBridge | 167:84c0a372a020 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| AnnaBridge | 167:84c0a372a020 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| AnnaBridge | 167:84c0a372a020 | 24 | * Products, Inc. Branding Policy. |
| AnnaBridge | 167:84c0a372a020 | 25 | * |
| AnnaBridge | 167:84c0a372a020 | 26 | * The mere transfer of this software does not imply any licenses |
| AnnaBridge | 167:84c0a372a020 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| AnnaBridge | 167:84c0a372a020 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| AnnaBridge | 167:84c0a372a020 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| AnnaBridge | 167:84c0a372a020 | 30 | * ownership rights. |
| AnnaBridge | 167:84c0a372a020 | 31 | * |
| AnnaBridge | 167:84c0a372a020 | 32 | * $Date: 2016-06-03 16:02:37 -0500 (Fri, 03 Jun 2016) $ |
| AnnaBridge | 167:84c0a372a020 | 33 | * $Revision: 23203 $ |
| AnnaBridge | 167:84c0a372a020 | 34 | * |
| AnnaBridge | 167:84c0a372a020 | 35 | ******************************************************************************/ |
| AnnaBridge | 167:84c0a372a020 | 36 | |
| AnnaBridge | 167:84c0a372a020 | 37 | #ifndef _MXC_IOMAN_REGS_H_ |
| AnnaBridge | 167:84c0a372a020 | 38 | #define _MXC_IOMAN_REGS_H_ |
| AnnaBridge | 167:84c0a372a020 | 39 | |
| AnnaBridge | 167:84c0a372a020 | 40 | #ifdef __cplusplus |
| AnnaBridge | 167:84c0a372a020 | 41 | extern "C" { |
| AnnaBridge | 167:84c0a372a020 | 42 | #endif |
| AnnaBridge | 167:84c0a372a020 | 43 | |
| AnnaBridge | 167:84c0a372a020 | 44 | #include <stdint.h> |
| AnnaBridge | 167:84c0a372a020 | 45 | |
| AnnaBridge | 167:84c0a372a020 | 46 | /* |
| AnnaBridge | 167:84c0a372a020 | 47 | If types are not defined elsewhere (CMSIS) define them here |
| AnnaBridge | 167:84c0a372a020 | 48 | */ |
| AnnaBridge | 167:84c0a372a020 | 49 | #ifndef __IO |
| AnnaBridge | 167:84c0a372a020 | 50 | #define __IO volatile |
| AnnaBridge | 167:84c0a372a020 | 51 | #endif |
| AnnaBridge | 167:84c0a372a020 | 52 | #ifndef __I |
| AnnaBridge | 167:84c0a372a020 | 53 | #define __I volatile const |
| AnnaBridge | 167:84c0a372a020 | 54 | #endif |
| AnnaBridge | 167:84c0a372a020 | 55 | #ifndef __O |
| AnnaBridge | 167:84c0a372a020 | 56 | #define __O volatile |
| AnnaBridge | 167:84c0a372a020 | 57 | #endif |
| AnnaBridge | 167:84c0a372a020 | 58 | #ifndef __RO |
| AnnaBridge | 167:84c0a372a020 | 59 | #define __RO volatile const |
| AnnaBridge | 167:84c0a372a020 | 60 | #endif |
| AnnaBridge | 167:84c0a372a020 | 61 | |
| AnnaBridge | 167:84c0a372a020 | 62 | /** |
| AnnaBridge | 167:84c0a372a020 | 63 | * @brief Pin mapping define values common to all modules |
| AnnaBridge | 167:84c0a372a020 | 64 | */ |
| AnnaBridge | 167:84c0a372a020 | 65 | typedef enum { |
| AnnaBridge | 167:84c0a372a020 | 66 | /** Pin Mapping 'A' */ |
| AnnaBridge | 167:84c0a372a020 | 67 | MXC_E_IOMAN_MAPPING_A = 0, |
| AnnaBridge | 167:84c0a372a020 | 68 | /** Pin Mapping 'B' */ |
| AnnaBridge | 167:84c0a372a020 | 69 | MXC_E_IOMAN_MAPPING_B |
| AnnaBridge | 167:84c0a372a020 | 70 | } ioman_mapping_t; |
| AnnaBridge | 167:84c0a372a020 | 71 | |
| AnnaBridge | 167:84c0a372a020 | 72 | /* |
| AnnaBridge | 167:84c0a372a020 | 73 | Bitfield structs for registers in this module |
| AnnaBridge | 167:84c0a372a020 | 74 | */ |
| AnnaBridge | 167:84c0a372a020 | 75 | |
| AnnaBridge | 167:84c0a372a020 | 76 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 77 | uint32_t wud_req_p0 : 8; |
| AnnaBridge | 167:84c0a372a020 | 78 | uint32_t wud_req_p1 : 8; |
| AnnaBridge | 167:84c0a372a020 | 79 | uint32_t wud_req_p2 : 8; |
| AnnaBridge | 167:84c0a372a020 | 80 | uint32_t wud_req_p3 : 8; |
| AnnaBridge | 167:84c0a372a020 | 81 | } mxc_ioman_wud_req0_t; |
| AnnaBridge | 167:84c0a372a020 | 82 | |
| AnnaBridge | 167:84c0a372a020 | 83 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 84 | uint32_t wud_req_p4 : 8; |
| AnnaBridge | 167:84c0a372a020 | 85 | uint32_t wud_req_p5 : 8; |
| AnnaBridge | 167:84c0a372a020 | 86 | uint32_t wud_req_p6 : 8; |
| AnnaBridge | 167:84c0a372a020 | 87 | uint32_t wud_req_p7 : 8; |
| AnnaBridge | 167:84c0a372a020 | 88 | } mxc_ioman_wud_req1_t; |
| AnnaBridge | 167:84c0a372a020 | 89 | |
| AnnaBridge | 167:84c0a372a020 | 90 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 91 | uint32_t wud_ack_p0 : 8; |
| AnnaBridge | 167:84c0a372a020 | 92 | uint32_t wud_ack_p1 : 8; |
| AnnaBridge | 167:84c0a372a020 | 93 | uint32_t wud_ack_p2 : 8; |
| AnnaBridge | 167:84c0a372a020 | 94 | uint32_t wud_ack_p3 : 8; |
| AnnaBridge | 167:84c0a372a020 | 95 | } mxc_ioman_wud_ack0_t; |
| AnnaBridge | 167:84c0a372a020 | 96 | |
| AnnaBridge | 167:84c0a372a020 | 97 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 98 | uint32_t wud_ack_p4 : 8; |
| AnnaBridge | 167:84c0a372a020 | 99 | uint32_t wud_ack_p5 : 8; |
| AnnaBridge | 167:84c0a372a020 | 100 | uint32_t wud_ack_p6 : 8; |
| AnnaBridge | 167:84c0a372a020 | 101 | uint32_t wud_ack_p7 : 8; |
| AnnaBridge | 167:84c0a372a020 | 102 | } mxc_ioman_wud_ack1_t; |
| AnnaBridge | 167:84c0a372a020 | 103 | |
| AnnaBridge | 167:84c0a372a020 | 104 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 105 | uint32_t ali_req_p0 : 8; |
| AnnaBridge | 167:84c0a372a020 | 106 | uint32_t ali_req_p1 : 8; |
| AnnaBridge | 167:84c0a372a020 | 107 | uint32_t ali_req_p2 : 8; |
| AnnaBridge | 167:84c0a372a020 | 108 | uint32_t ali_req_p3 : 8; |
| AnnaBridge | 167:84c0a372a020 | 109 | } mxc_ioman_ali_req0_t; |
| AnnaBridge | 167:84c0a372a020 | 110 | |
| AnnaBridge | 167:84c0a372a020 | 111 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 112 | uint32_t ali_req_p4 : 8; |
| AnnaBridge | 167:84c0a372a020 | 113 | uint32_t ali_req_p5 : 8; |
| AnnaBridge | 167:84c0a372a020 | 114 | uint32_t ali_req_p6 : 8; |
| AnnaBridge | 167:84c0a372a020 | 115 | uint32_t ali_req_p7 : 8; |
| AnnaBridge | 167:84c0a372a020 | 116 | } mxc_ioman_ali_req1_t; |
| AnnaBridge | 167:84c0a372a020 | 117 | |
| AnnaBridge | 167:84c0a372a020 | 118 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 119 | uint32_t ali_ack_p0 : 8; |
| AnnaBridge | 167:84c0a372a020 | 120 | uint32_t ali_ack_p1 : 8; |
| AnnaBridge | 167:84c0a372a020 | 121 | uint32_t ali_ack_p2 : 8; |
| AnnaBridge | 167:84c0a372a020 | 122 | uint32_t ali_ack_p3 : 8; |
| AnnaBridge | 167:84c0a372a020 | 123 | } mxc_ioman_ali_ack0_t; |
| AnnaBridge | 167:84c0a372a020 | 124 | |
| AnnaBridge | 167:84c0a372a020 | 125 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 126 | uint32_t ali_ack_p4 : 8; |
| AnnaBridge | 167:84c0a372a020 | 127 | uint32_t ali_ack_p5 : 8; |
| AnnaBridge | 167:84c0a372a020 | 128 | uint32_t ali_ack_p6 : 8; |
| AnnaBridge | 167:84c0a372a020 | 129 | uint32_t ali_ack_p7 : 8; |
| AnnaBridge | 167:84c0a372a020 | 130 | } mxc_ioman_ali_ack1_t; |
| AnnaBridge | 167:84c0a372a020 | 131 | |
| AnnaBridge | 167:84c0a372a020 | 132 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 133 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 134 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 135 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 136 | uint32_t ss0_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 137 | uint32_t ss1_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 138 | uint32_t ss2_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 139 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 140 | uint32_t quad_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 141 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 142 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 143 | uint32_t : 15; |
| AnnaBridge | 167:84c0a372a020 | 144 | } mxc_ioman_spix_req_t; |
| AnnaBridge | 167:84c0a372a020 | 145 | |
| AnnaBridge | 167:84c0a372a020 | 146 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 147 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 148 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 149 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 150 | uint32_t ss0_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 151 | uint32_t ss1_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 152 | uint32_t ss2_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 153 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 154 | uint32_t quad_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 155 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 156 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 157 | uint32_t : 15; |
| AnnaBridge | 167:84c0a372a020 | 158 | } mxc_ioman_spix_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 159 | |
| AnnaBridge | 167:84c0a372a020 | 160 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 161 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 162 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 163 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 164 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 165 | uint32_t io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 166 | uint32_t cts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 167 | uint32_t rts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 168 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 169 | } mxc_ioman_uart0_req_t; |
| AnnaBridge | 167:84c0a372a020 | 170 | |
| AnnaBridge | 167:84c0a372a020 | 171 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 172 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 173 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 174 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 175 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 176 | uint32_t io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 177 | uint32_t cts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 178 | uint32_t rts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 179 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 180 | } mxc_ioman_uart0_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 181 | |
| AnnaBridge | 167:84c0a372a020 | 182 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 183 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 184 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 185 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 186 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 187 | uint32_t io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 188 | uint32_t cts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 189 | uint32_t rts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 190 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 191 | } mxc_ioman_uart1_req_t; |
| AnnaBridge | 167:84c0a372a020 | 192 | |
| AnnaBridge | 167:84c0a372a020 | 193 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 194 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 195 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 196 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 197 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 198 | uint32_t io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 199 | uint32_t cts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 200 | uint32_t rts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 201 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 202 | } mxc_ioman_uart1_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 203 | |
| AnnaBridge | 167:84c0a372a020 | 204 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 205 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 206 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 207 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 208 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 209 | uint32_t io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 210 | uint32_t cts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 211 | uint32_t rts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 212 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 213 | } mxc_ioman_uart2_req_t; |
| AnnaBridge | 167:84c0a372a020 | 214 | |
| AnnaBridge | 167:84c0a372a020 | 215 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 216 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 217 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 218 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 219 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 220 | uint32_t io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 221 | uint32_t cts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 222 | uint32_t rts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 223 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 224 | } mxc_ioman_uart2_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 225 | |
| AnnaBridge | 167:84c0a372a020 | 226 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 227 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 228 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 229 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 230 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 231 | uint32_t io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 232 | uint32_t cts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 233 | uint32_t rts_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 234 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 235 | } mxc_ioman_uart3_req_t; |
| AnnaBridge | 167:84c0a372a020 | 236 | |
| AnnaBridge | 167:84c0a372a020 | 237 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 238 | uint32_t io_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 239 | uint32_t cts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 240 | uint32_t rts_map : 1; |
| AnnaBridge | 167:84c0a372a020 | 241 | uint32_t : 1; |
| AnnaBridge | 167:84c0a372a020 | 242 | uint32_t io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 243 | uint32_t cts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 244 | uint32_t rts_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 245 | uint32_t : 25; |
| AnnaBridge | 167:84c0a372a020 | 246 | } mxc_ioman_uart3_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 247 | |
| AnnaBridge | 167:84c0a372a020 | 248 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 249 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 250 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 251 | uint32_t push_pull : 1; |
| AnnaBridge | 167:84c0a372a020 | 252 | uint32_t : 26; |
| AnnaBridge | 167:84c0a372a020 | 253 | } mxc_ioman_i2cm0_req_t; |
| AnnaBridge | 167:84c0a372a020 | 254 | |
| AnnaBridge | 167:84c0a372a020 | 255 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 256 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 257 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 258 | uint32_t : 27; |
| AnnaBridge | 167:84c0a372a020 | 259 | } mxc_ioman_i2cm0_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 260 | |
| AnnaBridge | 167:84c0a372a020 | 261 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 262 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 263 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 264 | uint32_t push_pull : 1; |
| AnnaBridge | 167:84c0a372a020 | 265 | uint32_t : 26; |
| AnnaBridge | 167:84c0a372a020 | 266 | } mxc_ioman_i2cm1_req_t; |
| AnnaBridge | 167:84c0a372a020 | 267 | |
| AnnaBridge | 167:84c0a372a020 | 268 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 269 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 270 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 271 | uint32_t : 27; |
| AnnaBridge | 167:84c0a372a020 | 272 | } mxc_ioman_i2cm1_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 273 | |
| AnnaBridge | 167:84c0a372a020 | 274 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 275 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 276 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 277 | uint32_t push_pull : 1; |
| AnnaBridge | 167:84c0a372a020 | 278 | uint32_t : 26; |
| AnnaBridge | 167:84c0a372a020 | 279 | } mxc_ioman_i2cm2_req_t; |
| AnnaBridge | 167:84c0a372a020 | 280 | |
| AnnaBridge | 167:84c0a372a020 | 281 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 282 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 283 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 284 | uint32_t : 27; |
| AnnaBridge | 167:84c0a372a020 | 285 | } mxc_ioman_i2cm2_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 286 | |
| AnnaBridge | 167:84c0a372a020 | 287 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 288 | uint32_t mapping_req : 2; |
| AnnaBridge | 167:84c0a372a020 | 289 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 290 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 291 | uint32_t : 27; |
| AnnaBridge | 167:84c0a372a020 | 292 | } mxc_ioman_i2cs_req_t; |
| AnnaBridge | 167:84c0a372a020 | 293 | |
| AnnaBridge | 167:84c0a372a020 | 294 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 295 | uint32_t mapping_ack : 2; |
| AnnaBridge | 167:84c0a372a020 | 296 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 297 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 298 | uint32_t : 27; |
| AnnaBridge | 167:84c0a372a020 | 299 | } mxc_ioman_i2cs_acl_t; |
| AnnaBridge | 167:84c0a372a020 | 300 | |
| AnnaBridge | 167:84c0a372a020 | 301 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 302 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 303 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 304 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 305 | uint32_t ss0_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 306 | uint32_t ss1_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 307 | uint32_t ss2_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 308 | uint32_t ss3_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 309 | uint32_t ss4_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 310 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 311 | uint32_t quad_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 312 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 313 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 314 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 315 | } mxc_ioman_spim0_req_t; |
| AnnaBridge | 167:84c0a372a020 | 316 | |
| AnnaBridge | 167:84c0a372a020 | 317 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 318 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 319 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 320 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 321 | uint32_t ss0_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 322 | uint32_t ss1_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 323 | uint32_t ss2_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 324 | uint32_t ss3_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 325 | uint32_t ss4_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 326 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 327 | uint32_t quad_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 328 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 329 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 330 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 331 | } mxc_ioman_spim0_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 332 | |
| AnnaBridge | 167:84c0a372a020 | 333 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 334 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 335 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 336 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 337 | uint32_t ss0_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 338 | uint32_t ss1_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 339 | uint32_t ss2_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 340 | uint32_t : 9; |
| AnnaBridge | 167:84c0a372a020 | 341 | uint32_t quad_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 342 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 343 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 344 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 345 | } mxc_ioman_spim1_req_t; |
| AnnaBridge | 167:84c0a372a020 | 346 | |
| AnnaBridge | 167:84c0a372a020 | 347 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 348 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 349 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 350 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 351 | uint32_t ss0_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 352 | uint32_t ss1_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 353 | uint32_t ss2_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 354 | uint32_t : 9; |
| AnnaBridge | 167:84c0a372a020 | 355 | uint32_t quad_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 356 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 357 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 358 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 359 | } mxc_ioman_spim1_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 360 | |
| AnnaBridge | 167:84c0a372a020 | 361 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 362 | uint32_t mapping_req : 2; |
| AnnaBridge | 167:84c0a372a020 | 363 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 364 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 365 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 366 | uint32_t ss0_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 367 | uint32_t ss1_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 368 | uint32_t ss2_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 369 | uint32_t : 5; |
| AnnaBridge | 167:84c0a372a020 | 370 | uint32_t sr0_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 371 | uint32_t sr1_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 372 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 373 | uint32_t quad_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 374 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 375 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 376 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 377 | } mxc_ioman_spim2_req_t; |
| AnnaBridge | 167:84c0a372a020 | 378 | |
| AnnaBridge | 167:84c0a372a020 | 379 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 380 | uint32_t mapping_ack : 2; |
| AnnaBridge | 167:84c0a372a020 | 381 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 382 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 383 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 384 | uint32_t ss0_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 385 | uint32_t ss1_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 386 | uint32_t ss2_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 387 | uint32_t : 5; |
| AnnaBridge | 167:84c0a372a020 | 388 | uint32_t sr0_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 389 | uint32_t sr1_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 390 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 391 | uint32_t quad_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 392 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 393 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 394 | uint32_t : 7; |
| AnnaBridge | 167:84c0a372a020 | 395 | } mxc_ioman_spim2_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 396 | |
| AnnaBridge | 167:84c0a372a020 | 397 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 398 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 399 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 400 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 401 | uint32_t quad_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 402 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 403 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 404 | uint32_t : 19; |
| AnnaBridge | 167:84c0a372a020 | 405 | } mxc_ioman_spib_req_t; |
| AnnaBridge | 167:84c0a372a020 | 406 | |
| AnnaBridge | 167:84c0a372a020 | 407 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 408 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 409 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 410 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 411 | uint32_t quad_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 412 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 413 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 414 | uint32_t : 19; |
| AnnaBridge | 167:84c0a372a020 | 415 | } mxc_ioman_spib_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 416 | |
| AnnaBridge | 167:84c0a372a020 | 417 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 418 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 419 | uint32_t mapping_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 420 | uint32_t epu_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 421 | uint32_t : 26; |
| AnnaBridge | 167:84c0a372a020 | 422 | } mxc_ioman_owm_req_t; |
| AnnaBridge | 167:84c0a372a020 | 423 | |
| AnnaBridge | 167:84c0a372a020 | 424 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 425 | uint32_t : 4; |
| AnnaBridge | 167:84c0a372a020 | 426 | uint32_t mapping_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 427 | uint32_t epu_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 428 | uint32_t : 26; |
| AnnaBridge | 167:84c0a372a020 | 429 | } mxc_ioman_owm_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 430 | |
| AnnaBridge | 167:84c0a372a020 | 431 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 432 | uint32_t mapping_req : 2; |
| AnnaBridge | 167:84c0a372a020 | 433 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 434 | uint32_t core_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 435 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 436 | uint32_t quad_io_req : 1; |
| AnnaBridge | 167:84c0a372a020 | 437 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 438 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 439 | uint32_t : 19; |
| AnnaBridge | 167:84c0a372a020 | 440 | } mxc_ioman_spis_req_t; |
| AnnaBridge | 167:84c0a372a020 | 441 | |
| AnnaBridge | 167:84c0a372a020 | 442 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 443 | uint32_t mapping_ack : 2; |
| AnnaBridge | 167:84c0a372a020 | 444 | uint32_t : 2; |
| AnnaBridge | 167:84c0a372a020 | 445 | uint32_t core_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 446 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 447 | uint32_t quad_io_ack : 1; |
| AnnaBridge | 167:84c0a372a020 | 448 | uint32_t : 3; |
| AnnaBridge | 167:84c0a372a020 | 449 | uint32_t fast_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 450 | uint32_t : 19; |
| AnnaBridge | 167:84c0a372a020 | 451 | } mxc_ioman_spis_ack_t; |
| AnnaBridge | 167:84c0a372a020 | 452 | |
| AnnaBridge | 167:84c0a372a020 | 453 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 454 | uint32_t slow_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 455 | uint32_t alt_rcvr_mode : 1; |
| AnnaBridge | 167:84c0a372a020 | 456 | uint32_t : 30; |
| AnnaBridge | 167:84c0a372a020 | 457 | } mxc_ioman_pad_mode_t; |
| AnnaBridge | 167:84c0a372a020 | 458 | |
| AnnaBridge | 167:84c0a372a020 | 459 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 460 | uint32_t wud_req_p8 : 2; |
| AnnaBridge | 167:84c0a372a020 | 461 | uint32_t : 30; |
| AnnaBridge | 167:84c0a372a020 | 462 | } mxc_ioman_wud_req2_t; |
| AnnaBridge | 167:84c0a372a020 | 463 | |
| AnnaBridge | 167:84c0a372a020 | 464 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 465 | uint32_t wud_ack_p8 : 2; |
| AnnaBridge | 167:84c0a372a020 | 466 | uint32_t : 30; |
| AnnaBridge | 167:84c0a372a020 | 467 | } mxc_ioman_wud_ack2_t; |
| AnnaBridge | 167:84c0a372a020 | 468 | |
| AnnaBridge | 167:84c0a372a020 | 469 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 470 | uint32_t ali_req_p8 : 2; |
| AnnaBridge | 167:84c0a372a020 | 471 | uint32_t : 30; |
| AnnaBridge | 167:84c0a372a020 | 472 | } mxc_ioman_ali_req2_t; |
| AnnaBridge | 167:84c0a372a020 | 473 | |
| AnnaBridge | 167:84c0a372a020 | 474 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 475 | uint32_t ali_ack_p8 : 2; |
| AnnaBridge | 167:84c0a372a020 | 476 | uint32_t : 30; |
| AnnaBridge | 167:84c0a372a020 | 477 | } mxc_ioman_ali_ack2_t; |
| AnnaBridge | 167:84c0a372a020 | 478 | |
| AnnaBridge | 167:84c0a372a020 | 479 | |
| AnnaBridge | 167:84c0a372a020 | 480 | /* |
| AnnaBridge | 167:84c0a372a020 | 481 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| AnnaBridge | 167:84c0a372a020 | 482 | access to each register in module. |
| AnnaBridge | 167:84c0a372a020 | 483 | */ |
| AnnaBridge | 167:84c0a372a020 | 484 | |
| AnnaBridge | 167:84c0a372a020 | 485 | /* Offset Register Description |
| AnnaBridge | 167:84c0a372a020 | 486 | ============= ============================================================================ */ |
| AnnaBridge | 167:84c0a372a020 | 487 | typedef struct { |
| AnnaBridge | 167:84c0a372a020 | 488 | __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 167:84c0a372a020 | 489 | __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 167:84c0a372a020 | 490 | __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 167:84c0a372a020 | 491 | __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 167:84c0a372a020 | 492 | __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 167:84c0a372a020 | 493 | __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 167:84c0a372a020 | 494 | __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 167:84c0a372a020 | 495 | __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 167:84c0a372a020 | 496 | __IO uint32_t ali_connect0; /* 0x0020 Analog I/O Connection Control Register 0 */ |
| AnnaBridge | 167:84c0a372a020 | 497 | __IO uint32_t ali_connect1; /* 0x0024 Analog I/O Connection Control Register 1 */ |
| AnnaBridge | 167:84c0a372a020 | 498 | __IO uint32_t spix_req; /* 0x0028 SPIX I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 499 | __IO uint32_t spix_ack; /* 0x002C SPIX I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 500 | __IO uint32_t uart0_req; /* 0x0030 UART0 I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 501 | __IO uint32_t uart0_ack; /* 0x0034 UART0 I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 502 | __IO uint32_t uart1_req; /* 0x0038 UART1 I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 503 | __IO uint32_t uart1_ack; /* 0x003C UART1 I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 504 | __IO uint32_t uart2_req; /* 0x0040 UART2 I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 505 | __IO uint32_t uart2_ack; /* 0x0044 UART2 I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 506 | __IO uint32_t uart3_req; /* 0x0048 UART3 I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 507 | __IO uint32_t uart3_ack; /* 0x004C UART3 I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 508 | __IO uint32_t i2cm0_req; /* 0x0050 I2C Master 0 I/O Request */ |
| AnnaBridge | 167:84c0a372a020 | 509 | __IO uint32_t i2cm0_ack; /* 0x0054 I2C Master 0 I/O Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 510 | __IO uint32_t i2cm1_req; /* 0x0058 I2C Master 1 I/O Request */ |
| AnnaBridge | 167:84c0a372a020 | 511 | __IO uint32_t i2cm1_ack; /* 0x005C I2C Master 1 I/O Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 512 | __IO uint32_t i2cm2_req; /* 0x0060 I2C Master 2 I/O Request */ |
| AnnaBridge | 167:84c0a372a020 | 513 | __IO uint32_t i2cm2_ack; /* 0x0064 I2C Master 2 I/O Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 514 | __IO uint32_t i2cs_req; /* 0x0068 I2C Slave I/O Request */ |
| AnnaBridge | 167:84c0a372a020 | 515 | __IO uint32_t i2cs_ack; /* 0x006C I2C Slave I/O Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 516 | __IO uint32_t spim0_req; /* 0x0070 SPI Master 0 I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 517 | __IO uint32_t spim0_ack; /* 0x0074 SPI Master 0 I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 518 | __IO uint32_t spim1_req; /* 0x0078 SPI Master 1 I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 519 | __IO uint32_t spim1_ack; /* 0x007C SPI Master 1 I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 520 | __IO uint32_t spim2_req; /* 0x0080 SPI Master 2 I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 521 | __IO uint32_t spim2_ack; /* 0x0084 SPI Master 2 I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 522 | __IO uint32_t spib_req; /* 0x0088 SPI Bridge I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 523 | __IO uint32_t spib_ack; /* 0x008C SPI Bridge I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 524 | __IO uint32_t owm_req; /* 0x0090 1-Wire Master I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 525 | __IO uint32_t owm_ack; /* 0x0094 1-Wire Master I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 526 | __IO uint32_t spis_req; /* 0x0098 SPI Slave I/O Mode Request */ |
| AnnaBridge | 167:84c0a372a020 | 527 | __IO uint32_t spis_ack; /* 0x009C SPI Slave I/O Mode Acknowledge */ |
| AnnaBridge | 167:84c0a372a020 | 528 | __RO uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */ |
| AnnaBridge | 167:84c0a372a020 | 529 | __IO uint32_t use_vddioh_0; /* 0x0100 Enable VDDIOH Register 0 */ |
| AnnaBridge | 167:84c0a372a020 | 530 | __IO uint32_t use_vddioh_1; /* 0x0104 Enable VDDIOH Register 1 */ |
| AnnaBridge | 167:84c0a372a020 | 531 | __IO uint32_t use_vddioh_2; /* 0x0108 Enable VDDIOH Register 2 */ |
| AnnaBridge | 167:84c0a372a020 | 532 | __RO uint32_t rsv10C; /* 0x010C */ |
| AnnaBridge | 167:84c0a372a020 | 533 | __IO uint32_t pad_mode; /* 0x0110 Pad Mode Control Register */ |
| AnnaBridge | 167:84c0a372a020 | 534 | __RO uint32_t rsv114[27]; /* 0x0114-0x017C */ |
| AnnaBridge | 167:84c0a372a020 | 535 | __IO uint32_t wud_req2; /* 0x0180 Wakeup Detect Mode Request Register 2 (P8) */ |
| AnnaBridge | 167:84c0a372a020 | 536 | __RO uint32_t rsv184; /* 0x0184 */ |
| AnnaBridge | 167:84c0a372a020 | 537 | __IO uint32_t wud_ack2; /* 0x0188 Wakeup Detect Mode Acknowledge Register 2 (P8) */ |
| AnnaBridge | 167:84c0a372a020 | 538 | __RO uint32_t rsv18C; /* 0x018C */ |
| AnnaBridge | 167:84c0a372a020 | 539 | __IO uint32_t ali_req2; /* 0x0190 Analog Input Request Register 2 (P8) */ |
| AnnaBridge | 167:84c0a372a020 | 540 | __RO uint32_t rsv194; /* 0x0194 */ |
| AnnaBridge | 167:84c0a372a020 | 541 | __IO uint32_t ali_ack2; /* 0x0198 Analog Input Acknowledge Register 2 (P8) */ |
| AnnaBridge | 167:84c0a372a020 | 542 | __RO uint32_t rsv19C; /* 0x019C */ |
| AnnaBridge | 167:84c0a372a020 | 543 | __IO uint32_t ali_connect2; /* 0x01A0 Analog I/O Connection Control Register 2 */ |
| AnnaBridge | 167:84c0a372a020 | 544 | } mxc_ioman_regs_t; |
| AnnaBridge | 167:84c0a372a020 | 545 | |
| AnnaBridge | 167:84c0a372a020 | 546 | |
| AnnaBridge | 167:84c0a372a020 | 547 | /* |
| AnnaBridge | 167:84c0a372a020 | 548 | Register offsets for module IOMAN. |
| AnnaBridge | 167:84c0a372a020 | 549 | */ |
| AnnaBridge | 167:84c0a372a020 | 550 | |
| AnnaBridge | 167:84c0a372a020 | 551 | #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) |
| AnnaBridge | 167:84c0a372a020 | 552 | #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) |
| AnnaBridge | 167:84c0a372a020 | 553 | #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) |
| AnnaBridge | 167:84c0a372a020 | 554 | #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) |
| AnnaBridge | 167:84c0a372a020 | 555 | #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) |
| AnnaBridge | 167:84c0a372a020 | 556 | #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) |
| AnnaBridge | 167:84c0a372a020 | 557 | #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) |
| AnnaBridge | 167:84c0a372a020 | 558 | #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) |
| AnnaBridge | 167:84c0a372a020 | 559 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) |
| AnnaBridge | 167:84c0a372a020 | 560 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) |
| AnnaBridge | 167:84c0a372a020 | 561 | #define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) |
| AnnaBridge | 167:84c0a372a020 | 562 | #define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) |
| AnnaBridge | 167:84c0a372a020 | 563 | #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) |
| AnnaBridge | 167:84c0a372a020 | 564 | #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) |
| AnnaBridge | 167:84c0a372a020 | 565 | #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) |
| AnnaBridge | 167:84c0a372a020 | 566 | #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) |
| AnnaBridge | 167:84c0a372a020 | 567 | #define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) |
| AnnaBridge | 167:84c0a372a020 | 568 | #define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) |
| AnnaBridge | 167:84c0a372a020 | 569 | #define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL) |
| AnnaBridge | 167:84c0a372a020 | 570 | #define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL) |
| AnnaBridge | 167:84c0a372a020 | 571 | #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) |
| AnnaBridge | 167:84c0a372a020 | 572 | #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) |
| AnnaBridge | 167:84c0a372a020 | 573 | #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) |
| AnnaBridge | 167:84c0a372a020 | 574 | #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) |
| AnnaBridge | 167:84c0a372a020 | 575 | #define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL) |
| AnnaBridge | 167:84c0a372a020 | 576 | #define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL) |
| AnnaBridge | 167:84c0a372a020 | 577 | #define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) |
| AnnaBridge | 167:84c0a372a020 | 578 | #define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) |
| AnnaBridge | 167:84c0a372a020 | 579 | #define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) |
| AnnaBridge | 167:84c0a372a020 | 580 | #define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) |
| AnnaBridge | 167:84c0a372a020 | 581 | #define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) |
| AnnaBridge | 167:84c0a372a020 | 582 | #define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) |
| AnnaBridge | 167:84c0a372a020 | 583 | #define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) |
| AnnaBridge | 167:84c0a372a020 | 584 | #define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) |
| AnnaBridge | 167:84c0a372a020 | 585 | #define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL) |
| AnnaBridge | 167:84c0a372a020 | 586 | #define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL) |
| AnnaBridge | 167:84c0a372a020 | 587 | #define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) |
| AnnaBridge | 167:84c0a372a020 | 588 | #define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) |
| AnnaBridge | 167:84c0a372a020 | 589 | #define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) |
| AnnaBridge | 167:84c0a372a020 | 590 | #define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) |
| AnnaBridge | 167:84c0a372a020 | 591 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) |
| AnnaBridge | 167:84c0a372a020 | 592 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) |
| AnnaBridge | 167:84c0a372a020 | 593 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_2 ((uint32_t)0x00000108UL) |
| AnnaBridge | 167:84c0a372a020 | 594 | #define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) |
| AnnaBridge | 167:84c0a372a020 | 595 | #define MXC_R_IOMAN_OFFS_WUD_REQ2 ((uint32_t)0x00000180UL) |
| AnnaBridge | 167:84c0a372a020 | 596 | #define MXC_R_IOMAN_OFFS_WUD_ACK2 ((uint32_t)0x00000188UL) |
| AnnaBridge | 167:84c0a372a020 | 597 | #define MXC_R_IOMAN_OFFS_ALI_REQ2 ((uint32_t)0x00000190UL) |
| AnnaBridge | 167:84c0a372a020 | 598 | #define MXC_R_IOMAN_OFFS_ALI_ACK2 ((uint32_t)0x00000198UL) |
| AnnaBridge | 167:84c0a372a020 | 599 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT2 ((uint32_t)0x000001A0UL) |
| AnnaBridge | 167:84c0a372a020 | 600 | |
| AnnaBridge | 167:84c0a372a020 | 601 | |
| AnnaBridge | 167:84c0a372a020 | 602 | /* |
| AnnaBridge | 167:84c0a372a020 | 603 | Field positions and masks for module IOMAN. |
| AnnaBridge | 167:84c0a372a020 | 604 | */ |
| AnnaBridge | 167:84c0a372a020 | 605 | |
| AnnaBridge | 167:84c0a372a020 | 606 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 607 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 608 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 609 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 610 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 611 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 612 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 613 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 614 | |
| AnnaBridge | 167:84c0a372a020 | 615 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 616 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 617 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 618 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 619 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 620 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 621 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 622 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 623 | |
| AnnaBridge | 167:84c0a372a020 | 624 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 625 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 626 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 627 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 628 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 629 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 630 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 631 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 632 | |
| AnnaBridge | 167:84c0a372a020 | 633 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 634 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 635 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 636 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 637 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 638 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 639 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 640 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 641 | |
| AnnaBridge | 167:84c0a372a020 | 642 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 643 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 644 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 645 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 646 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 647 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 648 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 649 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 650 | |
| AnnaBridge | 167:84c0a372a020 | 651 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 652 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 653 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 654 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 655 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 656 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 657 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 658 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 659 | |
| AnnaBridge | 167:84c0a372a020 | 660 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 661 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS)) |
| AnnaBridge | 167:84c0a372a020 | 662 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 663 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS)) |
| AnnaBridge | 167:84c0a372a020 | 664 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 665 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS)) |
| AnnaBridge | 167:84c0a372a020 | 666 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 667 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS)) |
| AnnaBridge | 167:84c0a372a020 | 668 | |
| AnnaBridge | 167:84c0a372a020 | 669 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 670 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS)) |
| AnnaBridge | 167:84c0a372a020 | 671 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 672 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS)) |
| AnnaBridge | 167:84c0a372a020 | 673 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 674 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS)) |
| AnnaBridge | 167:84c0a372a020 | 675 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 676 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS)) |
| AnnaBridge | 167:84c0a372a020 | 677 | |
| AnnaBridge | 167:84c0a372a020 | 678 | #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 679 | #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 680 | #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 681 | #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 682 | #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 683 | #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 684 | #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 685 | #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 686 | #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 687 | #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 688 | #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 689 | #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 690 | |
| AnnaBridge | 167:84c0a372a020 | 691 | #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 692 | #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 693 | #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 694 | #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 695 | #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 696 | #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 697 | #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 698 | #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 699 | #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 700 | #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 701 | #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 702 | #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 703 | |
| AnnaBridge | 167:84c0a372a020 | 704 | #define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 705 | #define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 706 | #define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 707 | #define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 708 | #define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 709 | #define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 710 | #define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 711 | #define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 712 | #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 713 | #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 714 | #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 715 | #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 716 | |
| AnnaBridge | 167:84c0a372a020 | 717 | #define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 718 | #define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 719 | #define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 720 | #define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 721 | #define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 722 | #define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 723 | #define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 724 | #define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 725 | #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 726 | #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 727 | #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 728 | #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 729 | |
| AnnaBridge | 167:84c0a372a020 | 730 | #define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 731 | #define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 732 | #define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 733 | #define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 734 | #define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 735 | #define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 736 | #define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 737 | #define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 738 | #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 739 | #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 740 | #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 741 | #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 742 | |
| AnnaBridge | 167:84c0a372a020 | 743 | #define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 744 | #define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 745 | #define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 746 | #define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 747 | #define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 748 | #define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 749 | #define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 750 | #define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 751 | #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 752 | #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 753 | #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 754 | #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 755 | |
| AnnaBridge | 167:84c0a372a020 | 756 | #define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 757 | #define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 758 | #define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 759 | #define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 760 | #define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 761 | #define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 762 | #define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 763 | #define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 764 | #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 765 | #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 766 | #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 767 | #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 768 | |
| AnnaBridge | 167:84c0a372a020 | 769 | #define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 770 | #define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 771 | #define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 772 | #define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 773 | #define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 774 | #define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 775 | #define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 776 | #define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 777 | #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 778 | #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 779 | #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 780 | #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 781 | |
| AnnaBridge | 167:84c0a372a020 | 782 | #define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 783 | #define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 784 | #define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 785 | #define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 786 | #define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 787 | #define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 788 | #define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 789 | #define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 790 | #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 791 | #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 792 | #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 793 | #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 794 | |
| AnnaBridge | 167:84c0a372a020 | 795 | #define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 796 | #define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 797 | #define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 798 | #define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 799 | #define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 167:84c0a372a020 | 800 | #define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 801 | #define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 802 | #define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 803 | #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 804 | #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 805 | #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 167:84c0a372a020 | 806 | #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 807 | |
| AnnaBridge | 167:84c0a372a020 | 808 | #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 809 | #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 810 | |
| AnnaBridge | 167:84c0a372a020 | 811 | #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 812 | #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 813 | |
| AnnaBridge | 167:84c0a372a020 | 814 | #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 815 | #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS)) |
| AnnaBridge | 167:84c0a372a020 | 816 | #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 817 | #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 818 | |
| AnnaBridge | 167:84c0a372a020 | 819 | #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 820 | #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS)) |
| AnnaBridge | 167:84c0a372a020 | 821 | #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 822 | #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 823 | |
| AnnaBridge | 167:84c0a372a020 | 824 | #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 825 | #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS)) |
| AnnaBridge | 167:84c0a372a020 | 826 | #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 827 | #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 828 | |
| AnnaBridge | 167:84c0a372a020 | 829 | #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 830 | #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS)) |
| AnnaBridge | 167:84c0a372a020 | 831 | #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 832 | #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 833 | |
| AnnaBridge | 167:84c0a372a020 | 834 | #define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 835 | #define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS)) |
| AnnaBridge | 167:84c0a372a020 | 836 | #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 837 | #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 838 | |
| AnnaBridge | 167:84c0a372a020 | 839 | #define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 840 | #define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS)) |
| AnnaBridge | 167:84c0a372a020 | 841 | #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 842 | #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 843 | |
| AnnaBridge | 167:84c0a372a020 | 844 | #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 845 | #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 846 | #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 847 | #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 848 | #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 849 | #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 850 | #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 851 | #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 852 | #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11 |
| AnnaBridge | 167:84c0a372a020 | 853 | #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 854 | #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 855 | #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 856 | #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 857 | #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 858 | #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 859 | #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 860 | |
| AnnaBridge | 167:84c0a372a020 | 861 | #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 862 | #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 863 | #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 864 | #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 865 | #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 866 | #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 867 | #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 868 | #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 869 | #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11 |
| AnnaBridge | 167:84c0a372a020 | 870 | #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 871 | #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 872 | #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 873 | #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 874 | #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 875 | #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 876 | #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 877 | |
| AnnaBridge | 167:84c0a372a020 | 878 | #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 879 | #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 880 | #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 881 | #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 882 | #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 883 | #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 884 | #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 885 | #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 886 | #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 887 | #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 888 | #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 889 | #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 890 | |
| AnnaBridge | 167:84c0a372a020 | 891 | #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 892 | #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 893 | #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 894 | #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 895 | #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 896 | #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 897 | #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 898 | #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 899 | #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 900 | #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 901 | #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 902 | #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 903 | |
| AnnaBridge | 167:84c0a372a020 | 904 | #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 905 | #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 906 | #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 907 | #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 908 | #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 909 | #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 910 | #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 911 | #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 912 | #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 913 | #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 914 | #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 915 | #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 916 | #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17 |
| AnnaBridge | 167:84c0a372a020 | 917 | #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 918 | #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 919 | #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 920 | #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 921 | #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 922 | |
| AnnaBridge | 167:84c0a372a020 | 923 | #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 924 | #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 925 | #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 926 | #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 927 | #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 928 | #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 929 | #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 167:84c0a372a020 | 930 | #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 931 | #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 167:84c0a372a020 | 932 | #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 933 | #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS 16 |
| AnnaBridge | 167:84c0a372a020 | 934 | #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 935 | #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK_POS 17 |
| AnnaBridge | 167:84c0a372a020 | 936 | #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 937 | #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20 |
| AnnaBridge | 167:84c0a372a020 | 938 | #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 939 | #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24 |
| AnnaBridge | 167:84c0a372a020 | 940 | #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 941 | |
| AnnaBridge | 167:84c0a372a020 | 942 | #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 943 | #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 944 | #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 945 | #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 946 | #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 947 | #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 948 | |
| AnnaBridge | 167:84c0a372a020 | 949 | #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 950 | #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 951 | #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 952 | #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 953 | #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 954 | #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 955 | |
| AnnaBridge | 167:84c0a372a020 | 956 | #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 957 | #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 958 | #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 959 | #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 960 | |
| AnnaBridge | 167:84c0a372a020 | 961 | #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 962 | #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 963 | #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5 |
| AnnaBridge | 167:84c0a372a020 | 964 | #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 965 | |
| AnnaBridge | 167:84c0a372a020 | 966 | #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 967 | #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 968 | #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 969 | #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 970 | #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 971 | #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 972 | #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 973 | #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 974 | |
| AnnaBridge | 167:84c0a372a020 | 975 | #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 976 | #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 977 | #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 167:84c0a372a020 | 978 | #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 979 | #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8 |
| AnnaBridge | 167:84c0a372a020 | 980 | #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 981 | #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12 |
| AnnaBridge | 167:84c0a372a020 | 982 | #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 983 | |
| AnnaBridge | 167:84c0a372a020 | 984 | #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 985 | #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 986 | #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1 |
| AnnaBridge | 167:84c0a372a020 | 987 | #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS)) |
| AnnaBridge | 167:84c0a372a020 | 988 | |
| AnnaBridge | 167:84c0a372a020 | 989 | #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 990 | #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS)) |
| AnnaBridge | 167:84c0a372a020 | 991 | |
| AnnaBridge | 167:84c0a372a020 | 992 | #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 993 | #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS)) |
| AnnaBridge | 167:84c0a372a020 | 994 | |
| AnnaBridge | 167:84c0a372a020 | 995 | #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 996 | #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS)) |
| AnnaBridge | 167:84c0a372a020 | 997 | |
| AnnaBridge | 167:84c0a372a020 | 998 | #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS 0 |
| AnnaBridge | 167:84c0a372a020 | 999 | #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1000 | |
| AnnaBridge | 167:84c0a372a020 | 1001 | /* |
| AnnaBridge | 167:84c0a372a020 | 1002 | Generic field positions and masks for module IOMAN. |
| AnnaBridge | 167:84c0a372a020 | 1003 | */ |
| AnnaBridge | 167:84c0a372a020 | 1004 | #define MXC_F_IOMAN_UART_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1005 | #define MXC_F_IOMAN_UART_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1006 | #define MXC_F_IOMAN_UART_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1007 | #define MXC_F_IOMAN_UART_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1008 | #define MXC_F_IOMAN_UART_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1009 | #define MXC_F_IOMAN_UART_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1010 | |
| AnnaBridge | 167:84c0a372a020 | 1011 | #define MXC_F_IOMAN_UART_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1012 | #define MXC_F_IOMAN_UART_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1013 | #define MXC_F_IOMAN_UART_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1014 | #define MXC_F_IOMAN_UART_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1015 | #define MXC_F_IOMAN_UART_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1016 | #define MXC_F_IOMAN_UART_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1017 | |
| AnnaBridge | 167:84c0a372a020 | 1018 | #define MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1019 | #define MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1020 | |
| AnnaBridge | 167:84c0a372a020 | 1021 | #define MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1022 | #define MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1023 | #define MXC_F_IOMAN_SPIM_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1024 | #define MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1025 | #define MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1026 | #define MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1027 | #define MXC_F_IOMAN_SPIM_ACK_SR0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1028 | #define MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1029 | #define MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 167:84c0a372a020 | 1030 | |
| AnnaBridge | 167:84c0a372a020 | 1031 | |
| AnnaBridge | 167:84c0a372a020 | 1032 | |
| AnnaBridge | 167:84c0a372a020 | 1033 | |
| AnnaBridge | 167:84c0a372a020 | 1034 | |
| AnnaBridge | 167:84c0a372a020 | 1035 | #ifdef __cplusplus |
| AnnaBridge | 167:84c0a372a020 | 1036 | } |
| AnnaBridge | 167:84c0a372a020 | 1037 | #endif |
| AnnaBridge | 167:84c0a372a020 | 1038 | |
| AnnaBridge | 167:84c0a372a020 | 1039 | #endif /* _MXC_IOMAN_REGS_H_ */ |
| AnnaBridge | 167:84c0a372a020 | 1040 |
