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TARGET_SDT32620B/TOOLCHAIN_IAR/flc_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21839 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_FLC_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_FLC_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
AnnaBridge 167:84c0a372a020 64 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
AnnaBridge 167:84c0a372a020 65 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
AnnaBridge 167:84c0a372a020 66
AnnaBridge 167:84c0a372a020 67 /*
AnnaBridge 167:84c0a372a020 68 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 69 access to each register in module.
AnnaBridge 167:84c0a372a020 70 */
AnnaBridge 167:84c0a372a020 71
AnnaBridge 167:84c0a372a020 72 /* Offset Register Description
AnnaBridge 167:84c0a372a020 73 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 74 typedef struct {
AnnaBridge 167:84c0a372a020 75 __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
AnnaBridge 167:84c0a372a020 76 __IO uint32_t fckdiv; /* 0x0004 Flash Clock Pulse Divisor */
AnnaBridge 167:84c0a372a020 77 __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
AnnaBridge 167:84c0a372a020 78 __RO uint32_t rsv00C[6]; /* 0x000C-0x0020 */
AnnaBridge 167:84c0a372a020 79 __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
AnnaBridge 167:84c0a372a020 80 __RO uint32_t rsv028[2]; /* 0x0028-0x002C */
AnnaBridge 167:84c0a372a020 81 __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
AnnaBridge 167:84c0a372a020 82 __RO uint32_t rsv034[7]; /* 0x0034-0x004C */
AnnaBridge 167:84c0a372a020 83 __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
AnnaBridge 167:84c0a372a020 84 __IO uint32_t tacc; /* 0x0054 Flash Read Cycle Config */
AnnaBridge 167:84c0a372a020 85 __IO uint32_t tprog; /* 0x0058 Flash Write Cycle Config */
AnnaBridge 167:84c0a372a020 86 __RO uint32_t rsv05C[9]; /* 0x005C-0x007C */
AnnaBridge 167:84c0a372a020 87 __IO uint32_t status; /* 0x0080 Security Status Flags */
AnnaBridge 167:84c0a372a020 88 __RO uint32_t rsv084; /* 0x0084 */
AnnaBridge 167:84c0a372a020 89 __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
AnnaBridge 167:84c0a372a020 90 __RO uint32_t rsv08C[4]; /* 0x008C-0x0098 */
AnnaBridge 167:84c0a372a020 91 __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
AnnaBridge 167:84c0a372a020 92 __RO uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */
AnnaBridge 167:84c0a372a020 93 __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
AnnaBridge 167:84c0a372a020 94 __RO uint32_t rsv104[15]; /* 0x0104-0x013C */
AnnaBridge 167:84c0a372a020 95 __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
AnnaBridge 167:84c0a372a020 96 __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
AnnaBridge 167:84c0a372a020 97 __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
AnnaBridge 167:84c0a372a020 98 __RO uint32_t rsv14C[9]; /* 0x014C-0x016C */
AnnaBridge 167:84c0a372a020 99 __IO uint32_t bl_ctrl; /* 0x0170 Bootloader Control Register */
AnnaBridge 167:84c0a372a020 100 __IO uint32_t twk; /* 0x0174 PDM33 Register */
AnnaBridge 167:84c0a372a020 101 __RO uint32_t rsv178; /* 0x0178 */
AnnaBridge 167:84c0a372a020 102 __IO uint32_t slm; /* 0x017C Sleep Mode Register */
AnnaBridge 167:84c0a372a020 103 __RO uint32_t rsv180[32]; /* 0x0180-0x01FC */
AnnaBridge 167:84c0a372a020 104 __IO uint32_t disable_xr0; /* 0x0200 Disable Flash Page Exec/Read Register 0 */
AnnaBridge 167:84c0a372a020 105 __IO uint32_t disable_xr1; /* 0x0204 Disable Flash Page Exec/Read Register 1 */
AnnaBridge 167:84c0a372a020 106 __IO uint32_t disable_xr2; /* 0x0208 Disable Flash Page Exec/Read Register 2 */
AnnaBridge 167:84c0a372a020 107 __IO uint32_t disable_xr3; /* 0x020C Disable Flash Page Exec/Read Register 3 */
AnnaBridge 167:84c0a372a020 108 __IO uint32_t disable_xr4; /* 0x0210 Disable Flash Page Exec/Read Register 4 */
AnnaBridge 167:84c0a372a020 109 __IO uint32_t disable_xr5; /* 0x0214 Disable Flash Page Exec/Read Register 5 */
AnnaBridge 167:84c0a372a020 110 __IO uint32_t disable_xr6; /* 0x0218 Disable Flash Page Exec/Read Register 6 */
AnnaBridge 167:84c0a372a020 111 __IO uint32_t disable_xr7; /* 0x021C Disable Flash Page Exec/Read Register 7 */
AnnaBridge 167:84c0a372a020 112 __RO uint32_t rsv220[56]; /* 0x0220-0x02FC */
AnnaBridge 167:84c0a372a020 113 __IO uint32_t disable_we0; /* 0x0300 Disable Flash Page Write/Erase Register 0 */
AnnaBridge 167:84c0a372a020 114 __IO uint32_t disable_we1; /* 0x0304 Disable Flash Page Write/Erase Register 1 */
AnnaBridge 167:84c0a372a020 115 __IO uint32_t disable_we2; /* 0x0308 Disable Flash Page Write/Erase Register 2 */
AnnaBridge 167:84c0a372a020 116 __IO uint32_t disable_we3; /* 0x030C Disable Flash Page Write/Erase Register 3 */
AnnaBridge 167:84c0a372a020 117 __IO uint32_t disable_we4; /* 0x0310 Disable Flash Page Write/Erase Register 4 */
AnnaBridge 167:84c0a372a020 118 __IO uint32_t disable_we5; /* 0x0314 Disable Flash Page Write/Erase Register 5 */
AnnaBridge 167:84c0a372a020 119 __IO uint32_t disable_we6; /* 0x0318 Disable Flash Page Write/Erase Register 6 */
AnnaBridge 167:84c0a372a020 120 __IO uint32_t disable_we7; /* 0x031C Disable Flash Page Write/Erase Register 7 */
AnnaBridge 167:84c0a372a020 121 } mxc_flc_regs_t;
AnnaBridge 167:84c0a372a020 122
AnnaBridge 167:84c0a372a020 123
AnnaBridge 167:84c0a372a020 124 /*
AnnaBridge 167:84c0a372a020 125 Register offsets for module FLC.
AnnaBridge 167:84c0a372a020 126 */
AnnaBridge 167:84c0a372a020 127
AnnaBridge 167:84c0a372a020 128 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 129 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 130 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 131 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
AnnaBridge 167:84c0a372a020 132 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
AnnaBridge 167:84c0a372a020 133 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
AnnaBridge 167:84c0a372a020 134 #define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL)
AnnaBridge 167:84c0a372a020 135 #define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL)
AnnaBridge 167:84c0a372a020 136 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
AnnaBridge 167:84c0a372a020 137 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
AnnaBridge 167:84c0a372a020 138 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
AnnaBridge 167:84c0a372a020 139 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
AnnaBridge 167:84c0a372a020 140 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
AnnaBridge 167:84c0a372a020 141 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
AnnaBridge 167:84c0a372a020 142 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
AnnaBridge 167:84c0a372a020 143 #define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL)
AnnaBridge 167:84c0a372a020 144 #define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL)
AnnaBridge 167:84c0a372a020 145 #define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL)
AnnaBridge 167:84c0a372a020 146 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL)
AnnaBridge 167:84c0a372a020 147 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL)
AnnaBridge 167:84c0a372a020 148 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL)
AnnaBridge 167:84c0a372a020 149 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL)
AnnaBridge 167:84c0a372a020 150 #define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL)
AnnaBridge 167:84c0a372a020 151 #define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL)
AnnaBridge 167:84c0a372a020 152 #define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL)
AnnaBridge 167:84c0a372a020 153 #define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL)
AnnaBridge 167:84c0a372a020 154 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL)
AnnaBridge 167:84c0a372a020 155 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL)
AnnaBridge 167:84c0a372a020 156 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL)
AnnaBridge 167:84c0a372a020 157 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL)
AnnaBridge 167:84c0a372a020 158 #define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL)
AnnaBridge 167:84c0a372a020 159 #define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL)
AnnaBridge 167:84c0a372a020 160 #define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL)
AnnaBridge 167:84c0a372a020 161 #define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL)
AnnaBridge 167:84c0a372a020 162
AnnaBridge 167:84c0a372a020 163
AnnaBridge 167:84c0a372a020 164 /*
AnnaBridge 167:84c0a372a020 165 Field positions and masks for module FLC.
AnnaBridge 167:84c0a372a020 166 */
AnnaBridge 167:84c0a372a020 167
AnnaBridge 167:84c0a372a020 168 #define MXC_F_FLC_FADDR_FADDR_POS 0
AnnaBridge 167:84c0a372a020 169 #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
AnnaBridge 167:84c0a372a020 170
AnnaBridge 167:84c0a372a020 171 #define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
AnnaBridge 167:84c0a372a020 172 #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
AnnaBridge 167:84c0a372a020 173 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16
AnnaBridge 167:84c0a372a020 174 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS))
AnnaBridge 167:84c0a372a020 175
AnnaBridge 167:84c0a372a020 176 #define MXC_F_FLC_CTRL_WRITE_POS 0
AnnaBridge 167:84c0a372a020 177 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
AnnaBridge 167:84c0a372a020 178 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
AnnaBridge 167:84c0a372a020 179 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
AnnaBridge 167:84c0a372a020 180 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
AnnaBridge 167:84c0a372a020 181 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
AnnaBridge 167:84c0a372a020 182 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
AnnaBridge 167:84c0a372a020 183 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
AnnaBridge 167:84c0a372a020 184 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
AnnaBridge 167:84c0a372a020 185 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
AnnaBridge 167:84c0a372a020 186 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
AnnaBridge 167:84c0a372a020 187 #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
AnnaBridge 167:84c0a372a020 188 #define MXC_F_FLC_CTRL_PENDING_POS 24
AnnaBridge 167:84c0a372a020 189 #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
AnnaBridge 167:84c0a372a020 190 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
AnnaBridge 167:84c0a372a020 191 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
AnnaBridge 167:84c0a372a020 192 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
AnnaBridge 167:84c0a372a020 193 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
AnnaBridge 167:84c0a372a020 194 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
AnnaBridge 167:84c0a372a020 195 #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
AnnaBridge 167:84c0a372a020 196
AnnaBridge 167:84c0a372a020 197 #define MXC_F_FLC_INTR_FINISHED_IF_POS 0
AnnaBridge 167:84c0a372a020 198 #define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS))
AnnaBridge 167:84c0a372a020 199 #define MXC_F_FLC_INTR_FAILED_IF_POS 1
AnnaBridge 167:84c0a372a020 200 #define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS))
AnnaBridge 167:84c0a372a020 201 #define MXC_F_FLC_INTR_FINISHED_IE_POS 8
AnnaBridge 167:84c0a372a020 202 #define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS))
AnnaBridge 167:84c0a372a020 203 #define MXC_F_FLC_INTR_FAILED_IE_POS 9
AnnaBridge 167:84c0a372a020 204 #define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS))
AnnaBridge 167:84c0a372a020 205 #define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16
AnnaBridge 167:84c0a372a020 206 #define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS))
AnnaBridge 167:84c0a372a020 207
AnnaBridge 167:84c0a372a020 208 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
AnnaBridge 167:84c0a372a020 209 #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
AnnaBridge 167:84c0a372a020 210 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
AnnaBridge 167:84c0a372a020 211 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
AnnaBridge 167:84c0a372a020 212 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12
AnnaBridge 167:84c0a372a020 213 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS))
AnnaBridge 167:84c0a372a020 214 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16
AnnaBridge 167:84c0a372a020 215 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS))
AnnaBridge 167:84c0a372a020 216 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20
AnnaBridge 167:84c0a372a020 217 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS))
AnnaBridge 167:84c0a372a020 218 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24
AnnaBridge 167:84c0a372a020 219 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS))
AnnaBridge 167:84c0a372a020 220 #define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28
AnnaBridge 167:84c0a372a020 221 #define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS))
AnnaBridge 167:84c0a372a020 222 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29
AnnaBridge 167:84c0a372a020 223 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS))
AnnaBridge 167:84c0a372a020 224
AnnaBridge 167:84c0a372a020 225 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0
AnnaBridge 167:84c0a372a020 226 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS))
AnnaBridge 167:84c0a372a020 227 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1
AnnaBridge 167:84c0a372a020 228 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS))
AnnaBridge 167:84c0a372a020 229 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
AnnaBridge 167:84c0a372a020 230 #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
AnnaBridge 167:84c0a372a020 231 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29
AnnaBridge 167:84c0a372a020 232 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS))
AnnaBridge 167:84c0a372a020 233 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30
AnnaBridge 167:84c0a372a020 234 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS))
AnnaBridge 167:84c0a372a020 235
AnnaBridge 167:84c0a372a020 236 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
AnnaBridge 167:84c0a372a020 237 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
AnnaBridge 167:84c0a372a020 238 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
AnnaBridge 167:84c0a372a020 239 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
AnnaBridge 167:84c0a372a020 240 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16
AnnaBridge 167:84c0a372a020 241 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS))
AnnaBridge 167:84c0a372a020 242 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24
AnnaBridge 167:84c0a372a020 243 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS))
AnnaBridge 167:84c0a372a020 244 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28
AnnaBridge 167:84c0a372a020 245 #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
AnnaBridge 167:84c0a372a020 246
AnnaBridge 167:84c0a372a020 247 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
AnnaBridge 167:84c0a372a020 248 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
AnnaBridge 167:84c0a372a020 249 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
AnnaBridge 167:84c0a372a020 250 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
AnnaBridge 167:84c0a372a020 251 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
AnnaBridge 167:84c0a372a020 252 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
AnnaBridge 167:84c0a372a020 253 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
AnnaBridge 167:84c0a372a020 254 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
AnnaBridge 167:84c0a372a020 255
AnnaBridge 167:84c0a372a020 256 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
AnnaBridge 167:84c0a372a020 257 #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
AnnaBridge 167:84c0a372a020 258 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1
AnnaBridge 167:84c0a372a020 259 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS))
AnnaBridge 167:84c0a372a020 260 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3
AnnaBridge 167:84c0a372a020 261 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS))
AnnaBridge 167:84c0a372a020 262 #define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4
AnnaBridge 167:84c0a372a020 263 #define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS))
AnnaBridge 167:84c0a372a020 264 #define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5
AnnaBridge 167:84c0a372a020 265 #define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS))
AnnaBridge 167:84c0a372a020 266 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6
AnnaBridge 167:84c0a372a020 267 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS))
AnnaBridge 167:84c0a372a020 268 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
AnnaBridge 167:84c0a372a020 269 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
AnnaBridge 167:84c0a372a020 270
AnnaBridge 167:84c0a372a020 271 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
AnnaBridge 167:84c0a372a020 272 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
AnnaBridge 167:84c0a372a020 273 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
AnnaBridge 167:84c0a372a020 274 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
AnnaBridge 167:84c0a372a020 275 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
AnnaBridge 167:84c0a372a020 276 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
AnnaBridge 167:84c0a372a020 277 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
AnnaBridge 167:84c0a372a020 278 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
AnnaBridge 167:84c0a372a020 279 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4
AnnaBridge 167:84c0a372a020 280 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS))
AnnaBridge 167:84c0a372a020 281 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5
AnnaBridge 167:84c0a372a020 282 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS))
AnnaBridge 167:84c0a372a020 283
AnnaBridge 167:84c0a372a020 284 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
AnnaBridge 167:84c0a372a020 285 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
AnnaBridge 167:84c0a372a020 286 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
AnnaBridge 167:84c0a372a020 287 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
AnnaBridge 167:84c0a372a020 288 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
AnnaBridge 167:84c0a372a020 289 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
AnnaBridge 167:84c0a372a020 290 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
AnnaBridge 167:84c0a372a020 291 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
AnnaBridge 167:84c0a372a020 292 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4
AnnaBridge 167:84c0a372a020 293 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS))
AnnaBridge 167:84c0a372a020 294 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5
AnnaBridge 167:84c0a372a020 295 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS))
AnnaBridge 167:84c0a372a020 296
AnnaBridge 167:84c0a372a020 297
AnnaBridge 167:84c0a372a020 298
AnnaBridge 167:84c0a372a020 299 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 300 }
AnnaBridge 167:84c0a372a020 301 #endif
AnnaBridge 167:84c0a372a020 302
AnnaBridge 167:84c0a372a020 303 #endif /* _MXC_FLC_REGS_H_ */
AnnaBridge 167:84c0a372a020 304