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TARGET_SDT32620B/TOOLCHAIN_IAR/adc_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-18 09:21:00 -0500 (Fri, 18 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21976 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_ADC_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_ADC_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t ctrl; /* 0x0000 ADC Control */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t status; /* 0x0004 ADC Status */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t data; /* 0x0008 ADC Output Data */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t intr; /* 0x000C ADC Interrupt Control Register */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t limit[4]; /* 0x0010-0x001C ADC Limit 0..3 */
AnnaBridge 167:84c0a372a020 76 __IO uint32_t afe_ctrl; /* 0x0020 AFE Control Register */
AnnaBridge 167:84c0a372a020 77 __IO uint32_t ro_cal0; /* 0x0024 RO Trim Calibration Register 0 */
AnnaBridge 167:84c0a372a020 78 __IO uint32_t ro_cal1; /* 0x0028 RO Trim Calibration Register 1 */
AnnaBridge 167:84c0a372a020 79 __IO uint32_t ro_cal2; /* 0x002C RO Trim Calibration Register 2 */
AnnaBridge 167:84c0a372a020 80 } mxc_adc_regs_t;
AnnaBridge 167:84c0a372a020 81
AnnaBridge 167:84c0a372a020 82
AnnaBridge 167:84c0a372a020 83 /*
AnnaBridge 167:84c0a372a020 84 Register offsets for module ADC.
AnnaBridge 167:84c0a372a020 85 */
AnnaBridge 167:84c0a372a020 86
AnnaBridge 167:84c0a372a020 87 #define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 88 #define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 89 #define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 90 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 91 #define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 92 #define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL)
AnnaBridge 167:84c0a372a020 93 #define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL)
AnnaBridge 167:84c0a372a020 94 #define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL)
AnnaBridge 167:84c0a372a020 95 #define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL)
AnnaBridge 167:84c0a372a020 96 #define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL)
AnnaBridge 167:84c0a372a020 97 #define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL)
AnnaBridge 167:84c0a372a020 98 #define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL)
AnnaBridge 167:84c0a372a020 99
AnnaBridge 167:84c0a372a020 100
AnnaBridge 167:84c0a372a020 101 /*
AnnaBridge 167:84c0a372a020 102 Field positions and masks for module ADC.
AnnaBridge 167:84c0a372a020 103 */
AnnaBridge 167:84c0a372a020 104
AnnaBridge 167:84c0a372a020 105 #define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0
AnnaBridge 167:84c0a372a020 106 #define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS))
AnnaBridge 167:84c0a372a020 107 #define MXC_F_ADC_CTRL_ADC_PU_POS 1
AnnaBridge 167:84c0a372a020 108 #define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS))
AnnaBridge 167:84c0a372a020 109 #define MXC_F_ADC_CTRL_BUF_PU_POS 2
AnnaBridge 167:84c0a372a020 110 #define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS))
AnnaBridge 167:84c0a372a020 111 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3
AnnaBridge 167:84c0a372a020 112 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS))
AnnaBridge 167:84c0a372a020 113 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4
AnnaBridge 167:84c0a372a020 114 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS))
AnnaBridge 167:84c0a372a020 115 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5
AnnaBridge 167:84c0a372a020 116 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS))
AnnaBridge 167:84c0a372a020 117 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6
AnnaBridge 167:84c0a372a020 118 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS))
AnnaBridge 167:84c0a372a020 119 #define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7
AnnaBridge 167:84c0a372a020 120 #define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS))
AnnaBridge 167:84c0a372a020 121 #define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8
AnnaBridge 167:84c0a372a020 122 #define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS))
AnnaBridge 167:84c0a372a020 123 #define MXC_F_ADC_CTRL_ADC_SCALE_POS 9
AnnaBridge 167:84c0a372a020 124 #define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS))
AnnaBridge 167:84c0a372a020 125 #define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10
AnnaBridge 167:84c0a372a020 126 #define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS))
AnnaBridge 167:84c0a372a020 127 #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11
AnnaBridge 167:84c0a372a020 128 #define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS))
AnnaBridge 167:84c0a372a020 129 #define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12
AnnaBridge 167:84c0a372a020 130 #define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS))
AnnaBridge 167:84c0a372a020 131
AnnaBridge 167:84c0a372a020 132 #if (MXC_ADC_REV == 0)
AnnaBridge 167:84c0a372a020 133 #define MXC_F_ADC_CTRL_ADC_XREF_POS 16
AnnaBridge 167:84c0a372a020 134 #define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS))
AnnaBridge 167:84c0a372a020 135 #endif
AnnaBridge 167:84c0a372a020 136
AnnaBridge 167:84c0a372a020 137 #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17
AnnaBridge 167:84c0a372a020 138 #define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS))
AnnaBridge 167:84c0a372a020 139 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24
AnnaBridge 167:84c0a372a020 140 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS))
AnnaBridge 167:84c0a372a020 141
AnnaBridge 167:84c0a372a020 142 #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0
AnnaBridge 167:84c0a372a020 143 #define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS))
AnnaBridge 167:84c0a372a020 144 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1
AnnaBridge 167:84c0a372a020 145 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS))
AnnaBridge 167:84c0a372a020 146 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2
AnnaBridge 167:84c0a372a020 147 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS))
AnnaBridge 167:84c0a372a020 148 #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3
AnnaBridge 167:84c0a372a020 149 #define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS))
AnnaBridge 167:84c0a372a020 150
AnnaBridge 167:84c0a372a020 151 #define MXC_F_ADC_DATA_ADC_DATA_POS 0
AnnaBridge 167:84c0a372a020 152 #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS))
AnnaBridge 167:84c0a372a020 153
AnnaBridge 167:84c0a372a020 154 #define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0
AnnaBridge 167:84c0a372a020 155 #define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS))
AnnaBridge 167:84c0a372a020 156 #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1
AnnaBridge 167:84c0a372a020 157 #define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS))
AnnaBridge 167:84c0a372a020 158 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2
AnnaBridge 167:84c0a372a020 159 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS))
AnnaBridge 167:84c0a372a020 160 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3
AnnaBridge 167:84c0a372a020 161 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS))
AnnaBridge 167:84c0a372a020 162 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4
AnnaBridge 167:84c0a372a020 163 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS))
AnnaBridge 167:84c0a372a020 164 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5
AnnaBridge 167:84c0a372a020 165 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS))
AnnaBridge 167:84c0a372a020 166 #define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16
AnnaBridge 167:84c0a372a020 167 #define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS))
AnnaBridge 167:84c0a372a020 168 #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17
AnnaBridge 167:84c0a372a020 169 #define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS))
AnnaBridge 167:84c0a372a020 170 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18
AnnaBridge 167:84c0a372a020 171 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS))
AnnaBridge 167:84c0a372a020 172 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19
AnnaBridge 167:84c0a372a020 173 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS))
AnnaBridge 167:84c0a372a020 174 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20
AnnaBridge 167:84c0a372a020 175 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS))
AnnaBridge 167:84c0a372a020 176 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21
AnnaBridge 167:84c0a372a020 177 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS))
AnnaBridge 167:84c0a372a020 178 #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22
AnnaBridge 167:84c0a372a020 179 #define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS))
AnnaBridge 167:84c0a372a020 180
AnnaBridge 167:84c0a372a020 181 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0
AnnaBridge 167:84c0a372a020 182 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS))
AnnaBridge 167:84c0a372a020 183 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12
AnnaBridge 167:84c0a372a020 184 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS))
AnnaBridge 167:84c0a372a020 185 #define MXC_F_ADC_LIMIT0_CH_SEL_POS 24
AnnaBridge 167:84c0a372a020 186 #define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS))
AnnaBridge 167:84c0a372a020 187 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28
AnnaBridge 167:84c0a372a020 188 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 189 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29
AnnaBridge 167:84c0a372a020 190 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 191
AnnaBridge 167:84c0a372a020 192 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0
AnnaBridge 167:84c0a372a020 193 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS))
AnnaBridge 167:84c0a372a020 194 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12
AnnaBridge 167:84c0a372a020 195 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS))
AnnaBridge 167:84c0a372a020 196 #define MXC_F_ADC_LIMIT1_CH_SEL_POS 24
AnnaBridge 167:84c0a372a020 197 #define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS))
AnnaBridge 167:84c0a372a020 198 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28
AnnaBridge 167:84c0a372a020 199 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 200 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29
AnnaBridge 167:84c0a372a020 201 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 202
AnnaBridge 167:84c0a372a020 203 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0
AnnaBridge 167:84c0a372a020 204 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS))
AnnaBridge 167:84c0a372a020 205 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12
AnnaBridge 167:84c0a372a020 206 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS))
AnnaBridge 167:84c0a372a020 207 #define MXC_F_ADC_LIMIT2_CH_SEL_POS 24
AnnaBridge 167:84c0a372a020 208 #define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS))
AnnaBridge 167:84c0a372a020 209 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28
AnnaBridge 167:84c0a372a020 210 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 211 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29
AnnaBridge 167:84c0a372a020 212 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 213
AnnaBridge 167:84c0a372a020 214 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0
AnnaBridge 167:84c0a372a020 215 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS))
AnnaBridge 167:84c0a372a020 216 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12
AnnaBridge 167:84c0a372a020 217 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS))
AnnaBridge 167:84c0a372a020 218 #define MXC_F_ADC_LIMIT3_CH_SEL_POS 24
AnnaBridge 167:84c0a372a020 219 #define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS))
AnnaBridge 167:84c0a372a020 220 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28
AnnaBridge 167:84c0a372a020 221 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 222 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29
AnnaBridge 167:84c0a372a020 223 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS))
AnnaBridge 167:84c0a372a020 224
AnnaBridge 167:84c0a372a020 225 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8
AnnaBridge 167:84c0a372a020 226 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS))
AnnaBridge 167:84c0a372a020 227 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9
AnnaBridge 167:84c0a372a020 228 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS))
AnnaBridge 167:84c0a372a020 229
AnnaBridge 167:84c0a372a020 230 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
AnnaBridge 167:84c0a372a020 231 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
AnnaBridge 167:84c0a372a020 232 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
AnnaBridge 167:84c0a372a020 233 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
AnnaBridge 167:84c0a372a020 234 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
AnnaBridge 167:84c0a372a020 235 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
AnnaBridge 167:84c0a372a020 236 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4
AnnaBridge 167:84c0a372a020 237 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS))
AnnaBridge 167:84c0a372a020 238 #define MXC_F_ADC_RO_CAL0_DUMMY_POS 5
AnnaBridge 167:84c0a372a020 239 #define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS))
AnnaBridge 167:84c0a372a020 240 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
AnnaBridge 167:84c0a372a020 241 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
AnnaBridge 167:84c0a372a020 242 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
AnnaBridge 167:84c0a372a020 243 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
AnnaBridge 167:84c0a372a020 244
AnnaBridge 167:84c0a372a020 245 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
AnnaBridge 167:84c0a372a020 246 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
AnnaBridge 167:84c0a372a020 247 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
AnnaBridge 167:84c0a372a020 248 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
AnnaBridge 167:84c0a372a020 249 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
AnnaBridge 167:84c0a372a020 250 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
AnnaBridge 167:84c0a372a020 251
AnnaBridge 167:84c0a372a020 252 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0
AnnaBridge 167:84c0a372a020 253 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS))
AnnaBridge 167:84c0a372a020 254
AnnaBridge 167:84c0a372a020 255 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL))
AnnaBridge 167:84c0a372a020 256 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL))
AnnaBridge 167:84c0a372a020 257 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL))
AnnaBridge 167:84c0a372a020 258 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL))
AnnaBridge 167:84c0a372a020 259 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL))
AnnaBridge 167:84c0a372a020 260 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL))
AnnaBridge 167:84c0a372a020 261 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL))
AnnaBridge 167:84c0a372a020 262 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL))
AnnaBridge 167:84c0a372a020 263 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL))
AnnaBridge 167:84c0a372a020 264 #define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL))
AnnaBridge 167:84c0a372a020 265 #define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL))
AnnaBridge 167:84c0a372a020 266
AnnaBridge 167:84c0a372a020 267 #if(MXC_ADC_REV > 0)
AnnaBridge 167:84c0a372a020 268 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL))
AnnaBridge 167:84c0a372a020 269 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL))
AnnaBridge 167:84c0a372a020 270 #endif
AnnaBridge 167:84c0a372a020 271
AnnaBridge 167:84c0a372a020 272 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 273 }
AnnaBridge 167:84c0a372a020 274 #endif
AnnaBridge 167:84c0a372a020 275
AnnaBridge 167:84c0a372a020 276 #endif /* _MXC_ADC_REGS_H_ */
AnnaBridge 167:84c0a372a020 277