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TARGET_SAKURAIO_EVB_01/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_tim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 163:e59c8e839560 1 /**
AnnaBridge 163:e59c8e839560 2 ******************************************************************************
AnnaBridge 163:e59c8e839560 3 * @file stm32f4xx_hal_tim.h
AnnaBridge 163:e59c8e839560 4 * @author MCD Application Team
AnnaBridge 163:e59c8e839560 5 * @brief Header file of TIM HAL module.
AnnaBridge 163:e59c8e839560 6 ******************************************************************************
AnnaBridge 163:e59c8e839560 7 * @attention
AnnaBridge 163:e59c8e839560 8 *
AnnaBridge 163:e59c8e839560 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 163:e59c8e839560 10 *
AnnaBridge 163:e59c8e839560 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 163:e59c8e839560 12 * are permitted provided that the following conditions are met:
AnnaBridge 163:e59c8e839560 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 163:e59c8e839560 14 * this list of conditions and the following disclaimer.
AnnaBridge 163:e59c8e839560 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 163:e59c8e839560 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 163:e59c8e839560 17 * and/or other materials provided with the distribution.
AnnaBridge 163:e59c8e839560 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 163:e59c8e839560 19 * may be used to endorse or promote products derived from this software
AnnaBridge 163:e59c8e839560 20 * without specific prior written permission.
AnnaBridge 163:e59c8e839560 21 *
AnnaBridge 163:e59c8e839560 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 163:e59c8e839560 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 163:e59c8e839560 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 163:e59c8e839560 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 163:e59c8e839560 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 163:e59c8e839560 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 163:e59c8e839560 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 163:e59c8e839560 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 163:e59c8e839560 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 163:e59c8e839560 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 163:e59c8e839560 32 *
AnnaBridge 163:e59c8e839560 33 ******************************************************************************
AnnaBridge 163:e59c8e839560 34 */
AnnaBridge 163:e59c8e839560 35
AnnaBridge 163:e59c8e839560 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 163:e59c8e839560 37 #ifndef __STM32F4xx_HAL_TIM_H
AnnaBridge 163:e59c8e839560 38 #define __STM32F4xx_HAL_TIM_H
AnnaBridge 163:e59c8e839560 39
AnnaBridge 163:e59c8e839560 40 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 41 extern "C" {
AnnaBridge 163:e59c8e839560 42 #endif
AnnaBridge 163:e59c8e839560 43
AnnaBridge 163:e59c8e839560 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 45 #include "stm32f4xx_hal_def.h"
AnnaBridge 163:e59c8e839560 46
AnnaBridge 163:e59c8e839560 47 /** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge 163:e59c8e839560 48 * @{
AnnaBridge 163:e59c8e839560 49 */
AnnaBridge 163:e59c8e839560 50
AnnaBridge 163:e59c8e839560 51 /** @addtogroup TIM
AnnaBridge 163:e59c8e839560 52 * @{
AnnaBridge 163:e59c8e839560 53 */
AnnaBridge 163:e59c8e839560 54
AnnaBridge 163:e59c8e839560 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 56 /** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge 163:e59c8e839560 57 * @{
AnnaBridge 163:e59c8e839560 58 */
AnnaBridge 163:e59c8e839560 59
AnnaBridge 163:e59c8e839560 60 /**
AnnaBridge 163:e59c8e839560 61 * @brief TIM Time base Configuration Structure definition
AnnaBridge 163:e59c8e839560 62 */
AnnaBridge 163:e59c8e839560 63 typedef struct
AnnaBridge 163:e59c8e839560 64 {
AnnaBridge 163:e59c8e839560 65 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge 163:e59c8e839560 66 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
AnnaBridge 163:e59c8e839560 67
AnnaBridge 163:e59c8e839560 68 uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge 163:e59c8e839560 69 This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge 163:e59c8e839560 70
AnnaBridge 163:e59c8e839560 71 uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge 163:e59c8e839560 72 Auto-Reload Register at the next update event.
AnnaBridge 163:e59c8e839560 73 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
AnnaBridge 163:e59c8e839560 74
AnnaBridge 163:e59c8e839560 75 uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge 163:e59c8e839560 76 This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge 163:e59c8e839560 77
AnnaBridge 163:e59c8e839560 78 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge 163:e59c8e839560 79 reaches zero, an update event is generated and counting restarts
AnnaBridge 163:e59c8e839560 80 from the RCR value (N).
AnnaBridge 163:e59c8e839560 81 This means in PWM mode that (N+1) corresponds to:
AnnaBridge 163:e59c8e839560 82 - the number of PWM periods in edge-aligned mode
AnnaBridge 163:e59c8e839560 83 - the number of half PWM period in center-aligned mode
AnnaBridge 163:e59c8e839560 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge 163:e59c8e839560 85 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 163:e59c8e839560 86 } TIM_Base_InitTypeDef;
AnnaBridge 163:e59c8e839560 87
AnnaBridge 163:e59c8e839560 88 /**
AnnaBridge 163:e59c8e839560 89 * @brief TIM Output Compare Configuration Structure definition
AnnaBridge 163:e59c8e839560 90 */
AnnaBridge 163:e59c8e839560 91
AnnaBridge 163:e59c8e839560 92 typedef struct
AnnaBridge 163:e59c8e839560 93 {
AnnaBridge 163:e59c8e839560 94 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 163:e59c8e839560 95 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 163:e59c8e839560 96
AnnaBridge 163:e59c8e839560 97 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 163:e59c8e839560 98 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
AnnaBridge 163:e59c8e839560 99
AnnaBridge 163:e59c8e839560 100 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 163:e59c8e839560 101 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 163:e59c8e839560 102
AnnaBridge 163:e59c8e839560 103 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 163:e59c8e839560 104 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 163:e59c8e839560 105 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 163:e59c8e839560 106
AnnaBridge 163:e59c8e839560 107 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge 163:e59c8e839560 108 This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge 163:e59c8e839560 109 @note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge 163:e59c8e839560 110
AnnaBridge 163:e59c8e839560 111
AnnaBridge 163:e59c8e839560 112 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 163:e59c8e839560 113 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 163:e59c8e839560 114 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 163:e59c8e839560 115
AnnaBridge 163:e59c8e839560 116 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 163:e59c8e839560 117 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 163:e59c8e839560 118 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 163:e59c8e839560 119 } TIM_OC_InitTypeDef;
AnnaBridge 163:e59c8e839560 120
AnnaBridge 163:e59c8e839560 121 /**
AnnaBridge 163:e59c8e839560 122 * @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge 163:e59c8e839560 123 */
AnnaBridge 163:e59c8e839560 124 typedef struct
AnnaBridge 163:e59c8e839560 125 {
AnnaBridge 163:e59c8e839560 126 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 163:e59c8e839560 127 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 163:e59c8e839560 128
AnnaBridge 163:e59c8e839560 129 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 163:e59c8e839560 130 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
AnnaBridge 163:e59c8e839560 131
AnnaBridge 163:e59c8e839560 132 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 163:e59c8e839560 133 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 163:e59c8e839560 134
AnnaBridge 163:e59c8e839560 135 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 163:e59c8e839560 136 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 163:e59c8e839560 137 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 163:e59c8e839560 138
AnnaBridge 163:e59c8e839560 139 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 163:e59c8e839560 140 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 163:e59c8e839560 141 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 163:e59c8e839560 142
AnnaBridge 163:e59c8e839560 143 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 163:e59c8e839560 144 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 163:e59c8e839560 145 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 163:e59c8e839560 146
AnnaBridge 163:e59c8e839560 147 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 163:e59c8e839560 148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 163:e59c8e839560 149
AnnaBridge 163:e59c8e839560 150 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 163:e59c8e839560 151 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 163:e59c8e839560 152
AnnaBridge 163:e59c8e839560 153 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 163:e59c8e839560 154 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 163:e59c8e839560 155 } TIM_OnePulse_InitTypeDef;
AnnaBridge 163:e59c8e839560 156
AnnaBridge 163:e59c8e839560 157
AnnaBridge 163:e59c8e839560 158 /**
AnnaBridge 163:e59c8e839560 159 * @brief TIM Input Capture Configuration Structure definition
AnnaBridge 163:e59c8e839560 160 */
AnnaBridge 163:e59c8e839560 161
AnnaBridge 163:e59c8e839560 162 typedef struct
AnnaBridge 163:e59c8e839560 163 {
AnnaBridge 163:e59c8e839560 164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 163:e59c8e839560 165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 163:e59c8e839560 166
AnnaBridge 163:e59c8e839560 167 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 163:e59c8e839560 168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 163:e59c8e839560 169
AnnaBridge 163:e59c8e839560 170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 163:e59c8e839560 171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 163:e59c8e839560 172
AnnaBridge 163:e59c8e839560 173 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 163:e59c8e839560 174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 163:e59c8e839560 175 } TIM_IC_InitTypeDef;
AnnaBridge 163:e59c8e839560 176
AnnaBridge 163:e59c8e839560 177 /**
AnnaBridge 163:e59c8e839560 178 * @brief TIM Encoder Configuration Structure definition
AnnaBridge 163:e59c8e839560 179 */
AnnaBridge 163:e59c8e839560 180
AnnaBridge 163:e59c8e839560 181 typedef struct
AnnaBridge 163:e59c8e839560 182 {
AnnaBridge 163:e59c8e839560 183 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge 163:e59c8e839560 184 This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge 163:e59c8e839560 185
AnnaBridge 163:e59c8e839560 186 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 163:e59c8e839560 187 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 163:e59c8e839560 188
AnnaBridge 163:e59c8e839560 189 uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge 163:e59c8e839560 190 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 163:e59c8e839560 191
AnnaBridge 163:e59c8e839560 192 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 163:e59c8e839560 193 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 163:e59c8e839560 194
AnnaBridge 163:e59c8e839560 195 uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge 163:e59c8e839560 196 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 163:e59c8e839560 197
AnnaBridge 163:e59c8e839560 198 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 163:e59c8e839560 199 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 163:e59c8e839560 200
AnnaBridge 163:e59c8e839560 201 uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge 163:e59c8e839560 202 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 163:e59c8e839560 203
AnnaBridge 163:e59c8e839560 204 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 163:e59c8e839560 205 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 163:e59c8e839560 206
AnnaBridge 163:e59c8e839560 207 uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge 163:e59c8e839560 208 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 163:e59c8e839560 209 } TIM_Encoder_InitTypeDef;
AnnaBridge 163:e59c8e839560 210
AnnaBridge 163:e59c8e839560 211 /**
AnnaBridge 163:e59c8e839560 212 * @brief Clock Configuration Handle Structure definition
AnnaBridge 163:e59c8e839560 213 */
AnnaBridge 163:e59c8e839560 214 typedef struct
AnnaBridge 163:e59c8e839560 215 {
AnnaBridge 163:e59c8e839560 216 uint32_t ClockSource; /*!< TIM clock sources.
AnnaBridge 163:e59c8e839560 217 This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge 163:e59c8e839560 218 uint32_t ClockPolarity; /*!< TIM clock polarity.
AnnaBridge 163:e59c8e839560 219 This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge 163:e59c8e839560 220 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
AnnaBridge 163:e59c8e839560 221 This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge 163:e59c8e839560 222 uint32_t ClockFilter; /*!< TIM clock filter.
AnnaBridge 163:e59c8e839560 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 163:e59c8e839560 224 }TIM_ClockConfigTypeDef;
AnnaBridge 163:e59c8e839560 225
AnnaBridge 163:e59c8e839560 226 /**
AnnaBridge 163:e59c8e839560 227 * @brief Clear Input Configuration Handle Structure definition
AnnaBridge 163:e59c8e839560 228 */
AnnaBridge 163:e59c8e839560 229 typedef struct
AnnaBridge 163:e59c8e839560 230 {
AnnaBridge 163:e59c8e839560 231 uint32_t ClearInputState; /*!< TIM clear Input state.
AnnaBridge 163:e59c8e839560 232 This parameter can be ENABLE or DISABLE */
AnnaBridge 163:e59c8e839560 233 uint32_t ClearInputSource; /*!< TIM clear Input sources.
AnnaBridge 163:e59c8e839560 234 This parameter can be a value of @ref TIM_ClearInput_Source */
AnnaBridge 163:e59c8e839560 235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
AnnaBridge 163:e59c8e839560 236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge 163:e59c8e839560 237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
AnnaBridge 163:e59c8e839560 238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
AnnaBridge 163:e59c8e839560 239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
AnnaBridge 163:e59c8e839560 240 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 163:e59c8e839560 241 }TIM_ClearInputConfigTypeDef;
AnnaBridge 163:e59c8e839560 242
AnnaBridge 163:e59c8e839560 243 /**
AnnaBridge 163:e59c8e839560 244 * @brief TIM Slave configuration Structure definition
AnnaBridge 163:e59c8e839560 245 */
AnnaBridge 163:e59c8e839560 246 typedef struct {
AnnaBridge 163:e59c8e839560 247 uint32_t SlaveMode; /*!< Slave mode selection
AnnaBridge 163:e59c8e839560 248 This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge 163:e59c8e839560 249 uint32_t InputTrigger; /*!< Input Trigger source
AnnaBridge 163:e59c8e839560 250 This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge 163:e59c8e839560 251 uint32_t TriggerPolarity; /*!< Input Trigger polarity
AnnaBridge 163:e59c8e839560 252 This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge 163:e59c8e839560 253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
AnnaBridge 163:e59c8e839560 254 This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge 163:e59c8e839560 255 uint32_t TriggerFilter; /*!< Input trigger filter
AnnaBridge 163:e59c8e839560 256 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 163:e59c8e839560 257
AnnaBridge 163:e59c8e839560 258 }TIM_SlaveConfigTypeDef;
AnnaBridge 163:e59c8e839560 259
AnnaBridge 163:e59c8e839560 260 /**
AnnaBridge 163:e59c8e839560 261 * @brief HAL State structures definition
AnnaBridge 163:e59c8e839560 262 */
AnnaBridge 163:e59c8e839560 263 typedef enum
AnnaBridge 163:e59c8e839560 264 {
AnnaBridge 163:e59c8e839560 265 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
AnnaBridge 163:e59c8e839560 266 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 163:e59c8e839560 267 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
AnnaBridge 163:e59c8e839560 268 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
AnnaBridge 163:e59c8e839560 269 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
AnnaBridge 163:e59c8e839560 270 }HAL_TIM_StateTypeDef;
AnnaBridge 163:e59c8e839560 271
AnnaBridge 163:e59c8e839560 272 /**
AnnaBridge 163:e59c8e839560 273 * @brief HAL Active channel structures definition
AnnaBridge 163:e59c8e839560 274 */
AnnaBridge 163:e59c8e839560 275 typedef enum
AnnaBridge 163:e59c8e839560 276 {
AnnaBridge 163:e59c8e839560 277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
AnnaBridge 163:e59c8e839560 278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
AnnaBridge 163:e59c8e839560 279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
AnnaBridge 163:e59c8e839560 280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
AnnaBridge 163:e59c8e839560 281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
AnnaBridge 163:e59c8e839560 282 }HAL_TIM_ActiveChannel;
AnnaBridge 163:e59c8e839560 283
AnnaBridge 163:e59c8e839560 284 /**
AnnaBridge 163:e59c8e839560 285 * @brief TIM Time Base Handle Structure definition
AnnaBridge 163:e59c8e839560 286 */
AnnaBridge 163:e59c8e839560 287 typedef struct
AnnaBridge 163:e59c8e839560 288 {
AnnaBridge 163:e59c8e839560 289 TIM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 163:e59c8e839560 290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
AnnaBridge 163:e59c8e839560 291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
AnnaBridge 163:e59c8e839560 292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
AnnaBridge 163:e59c8e839560 293 This array is accessed by a @ref DMA_Handle_index */
AnnaBridge 163:e59c8e839560 294 HAL_LockTypeDef Lock; /*!< Locking object */
AnnaBridge 163:e59c8e839560 295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
AnnaBridge 163:e59c8e839560 296 }TIM_HandleTypeDef;
AnnaBridge 163:e59c8e839560 297 /**
AnnaBridge 163:e59c8e839560 298 * @}
AnnaBridge 163:e59c8e839560 299 */
AnnaBridge 163:e59c8e839560 300
AnnaBridge 163:e59c8e839560 301 /* Exported constants --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 302 /** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge 163:e59c8e839560 303 * @{
AnnaBridge 163:e59c8e839560 304 */
AnnaBridge 163:e59c8e839560 305
AnnaBridge 163:e59c8e839560 306 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
AnnaBridge 163:e59c8e839560 307 * @{
AnnaBridge 163:e59c8e839560 308 */
AnnaBridge 163:e59c8e839560 309 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
AnnaBridge 163:e59c8e839560 310 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
AnnaBridge 163:e59c8e839560 311 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
AnnaBridge 163:e59c8e839560 312 /**
AnnaBridge 163:e59c8e839560 313 * @}
AnnaBridge 163:e59c8e839560 314 */
AnnaBridge 163:e59c8e839560 315
AnnaBridge 163:e59c8e839560 316 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
AnnaBridge 163:e59c8e839560 317 * @{
AnnaBridge 163:e59c8e839560 318 */
AnnaBridge 163:e59c8e839560 319 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
AnnaBridge 163:e59c8e839560 320 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
AnnaBridge 163:e59c8e839560 321 /**
AnnaBridge 163:e59c8e839560 322 * @}
AnnaBridge 163:e59c8e839560 323 */
AnnaBridge 163:e59c8e839560 324
AnnaBridge 163:e59c8e839560 325 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
AnnaBridge 163:e59c8e839560 326 * @{
AnnaBridge 163:e59c8e839560 327 */
AnnaBridge 163:e59c8e839560 328 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
AnnaBridge 163:e59c8e839560 329 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
AnnaBridge 163:e59c8e839560 330 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
AnnaBridge 163:e59c8e839560 331 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
AnnaBridge 163:e59c8e839560 332 /**
AnnaBridge 163:e59c8e839560 333 * @}
AnnaBridge 163:e59c8e839560 334 */
AnnaBridge 163:e59c8e839560 335
AnnaBridge 163:e59c8e839560 336 /** @defgroup TIM_Counter_Mode TIM Counter Mode
AnnaBridge 163:e59c8e839560 337 * @{
AnnaBridge 163:e59c8e839560 338 */
AnnaBridge 163:e59c8e839560 339 #define TIM_COUNTERMODE_UP 0x00000000U
AnnaBridge 163:e59c8e839560 340 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
AnnaBridge 163:e59c8e839560 341 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
AnnaBridge 163:e59c8e839560 342 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
AnnaBridge 163:e59c8e839560 343 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
AnnaBridge 163:e59c8e839560 344 /**
AnnaBridge 163:e59c8e839560 345 * @}
AnnaBridge 163:e59c8e839560 346 */
AnnaBridge 163:e59c8e839560 347
AnnaBridge 163:e59c8e839560 348 /** @defgroup TIM_ClockDivision TIM Clock Division
AnnaBridge 163:e59c8e839560 349 * @{
AnnaBridge 163:e59c8e839560 350 */
AnnaBridge 163:e59c8e839560 351 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
AnnaBridge 163:e59c8e839560 352 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
AnnaBridge 163:e59c8e839560 353 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
AnnaBridge 163:e59c8e839560 354 /**
AnnaBridge 163:e59c8e839560 355 * @}
AnnaBridge 163:e59c8e839560 356 */
AnnaBridge 163:e59c8e839560 357
AnnaBridge 163:e59c8e839560 358 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
AnnaBridge 163:e59c8e839560 359 * @{
AnnaBridge 163:e59c8e839560 360 */
AnnaBridge 163:e59c8e839560 361 #define TIM_OCMODE_TIMING 0x00000000U
AnnaBridge 163:e59c8e839560 362 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
AnnaBridge 163:e59c8e839560 363 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
AnnaBridge 163:e59c8e839560 364 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
AnnaBridge 163:e59c8e839560 365 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 366 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
AnnaBridge 163:e59c8e839560 367 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 368 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
AnnaBridge 163:e59c8e839560 369
AnnaBridge 163:e59c8e839560 370 /**
AnnaBridge 163:e59c8e839560 371 * @}
AnnaBridge 163:e59c8e839560 372 */
AnnaBridge 163:e59c8e839560 373
AnnaBridge 163:e59c8e839560 374 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
AnnaBridge 163:e59c8e839560 375 * @{
AnnaBridge 163:e59c8e839560 376 */
AnnaBridge 163:e59c8e839560 377 #define TIM_OCFAST_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 378 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
AnnaBridge 163:e59c8e839560 379 /**
AnnaBridge 163:e59c8e839560 380 * @}
AnnaBridge 163:e59c8e839560 381 */
AnnaBridge 163:e59c8e839560 382
AnnaBridge 163:e59c8e839560 383 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
AnnaBridge 163:e59c8e839560 384 * @{
AnnaBridge 163:e59c8e839560 385 */
AnnaBridge 163:e59c8e839560 386 #define TIM_OCPOLARITY_HIGH 0x00000000U
AnnaBridge 163:e59c8e839560 387 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
AnnaBridge 163:e59c8e839560 388 /**
AnnaBridge 163:e59c8e839560 389 * @}
AnnaBridge 163:e59c8e839560 390 */
AnnaBridge 163:e59c8e839560 391
AnnaBridge 163:e59c8e839560 392 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
AnnaBridge 163:e59c8e839560 393 * @{
AnnaBridge 163:e59c8e839560 394 */
AnnaBridge 163:e59c8e839560 395 #define TIM_OCNPOLARITY_HIGH 0x00000000U
AnnaBridge 163:e59c8e839560 396 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
AnnaBridge 163:e59c8e839560 397 /**
AnnaBridge 163:e59c8e839560 398 * @}
AnnaBridge 163:e59c8e839560 399 */
AnnaBridge 163:e59c8e839560 400
AnnaBridge 163:e59c8e839560 401 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
AnnaBridge 163:e59c8e839560 402 * @{
AnnaBridge 163:e59c8e839560 403 */
AnnaBridge 163:e59c8e839560 404 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge 163:e59c8e839560 405 #define TIM_OCIDLESTATE_RESET 0x00000000U
AnnaBridge 163:e59c8e839560 406 /**
AnnaBridge 163:e59c8e839560 407 * @}
AnnaBridge 163:e59c8e839560 408 */
AnnaBridge 163:e59c8e839560 409
AnnaBridge 163:e59c8e839560 410 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
AnnaBridge 163:e59c8e839560 411 * @{
AnnaBridge 163:e59c8e839560 412 */
AnnaBridge 163:e59c8e839560 413 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
AnnaBridge 163:e59c8e839560 414 #define TIM_OCNIDLESTATE_RESET 0x00000000U
AnnaBridge 163:e59c8e839560 415 /**
AnnaBridge 163:e59c8e839560 416 * @}
AnnaBridge 163:e59c8e839560 417 */
AnnaBridge 163:e59c8e839560 418
AnnaBridge 163:e59c8e839560 419 /** @defgroup TIM_Channel TIM Channel
AnnaBridge 163:e59c8e839560 420 * @{
AnnaBridge 163:e59c8e839560 421 */
AnnaBridge 163:e59c8e839560 422 #define TIM_CHANNEL_1 0x00000000U
AnnaBridge 163:e59c8e839560 423 #define TIM_CHANNEL_2 0x00000004U
AnnaBridge 163:e59c8e839560 424 #define TIM_CHANNEL_3 0x00000008U
AnnaBridge 163:e59c8e839560 425 #define TIM_CHANNEL_4 0x0000000CU
AnnaBridge 163:e59c8e839560 426 #define TIM_CHANNEL_ALL 0x00000018U
AnnaBridge 163:e59c8e839560 427
AnnaBridge 163:e59c8e839560 428 /**
AnnaBridge 163:e59c8e839560 429 * @}
AnnaBridge 163:e59c8e839560 430 */
AnnaBridge 163:e59c8e839560 431
AnnaBridge 163:e59c8e839560 432 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
AnnaBridge 163:e59c8e839560 433 * @{
AnnaBridge 163:e59c8e839560 434 */
AnnaBridge 163:e59c8e839560 435 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
AnnaBridge 163:e59c8e839560 436 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
AnnaBridge 163:e59c8e839560 437 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
AnnaBridge 163:e59c8e839560 438 /**
AnnaBridge 163:e59c8e839560 439 * @}
AnnaBridge 163:e59c8e839560 440 */
AnnaBridge 163:e59c8e839560 441
AnnaBridge 163:e59c8e839560 442 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
AnnaBridge 163:e59c8e839560 443 * @{
AnnaBridge 163:e59c8e839560 444 */
AnnaBridge 163:e59c8e839560 445 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 163:e59c8e839560 446 connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge 163:e59c8e839560 447 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 163:e59c8e839560 448 connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge 163:e59c8e839560 449 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
AnnaBridge 163:e59c8e839560 450
AnnaBridge 163:e59c8e839560 451 /**
AnnaBridge 163:e59c8e839560 452 * @}
AnnaBridge 163:e59c8e839560 453 */
AnnaBridge 163:e59c8e839560 454
AnnaBridge 163:e59c8e839560 455 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
AnnaBridge 163:e59c8e839560 456 * @{
AnnaBridge 163:e59c8e839560 457 */
AnnaBridge 163:e59c8e839560 458 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
AnnaBridge 163:e59c8e839560 459 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
AnnaBridge 163:e59c8e839560 460 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
AnnaBridge 163:e59c8e839560 461 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
AnnaBridge 163:e59c8e839560 462 /**
AnnaBridge 163:e59c8e839560 463 * @}
AnnaBridge 163:e59c8e839560 464 */
AnnaBridge 163:e59c8e839560 465
AnnaBridge 163:e59c8e839560 466 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
AnnaBridge 163:e59c8e839560 467 * @{
AnnaBridge 163:e59c8e839560 468 */
AnnaBridge 163:e59c8e839560 469 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge 163:e59c8e839560 470 #define TIM_OPMODE_REPETITIVE 0x00000000U
AnnaBridge 163:e59c8e839560 471 /**
AnnaBridge 163:e59c8e839560 472 * @}
AnnaBridge 163:e59c8e839560 473 */
AnnaBridge 163:e59c8e839560 474
AnnaBridge 163:e59c8e839560 475 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
AnnaBridge 163:e59c8e839560 476 * @{
AnnaBridge 163:e59c8e839560 477 */
AnnaBridge 163:e59c8e839560 478 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
AnnaBridge 163:e59c8e839560 479 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
AnnaBridge 163:e59c8e839560 480 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
AnnaBridge 163:e59c8e839560 481
AnnaBridge 163:e59c8e839560 482 /**
AnnaBridge 163:e59c8e839560 483 * @}
AnnaBridge 163:e59c8e839560 484 */
AnnaBridge 163:e59c8e839560 485
AnnaBridge 163:e59c8e839560 486 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
AnnaBridge 163:e59c8e839560 487 * @{
AnnaBridge 163:e59c8e839560 488 */
AnnaBridge 163:e59c8e839560 489 #define TIM_IT_UPDATE (TIM_DIER_UIE)
AnnaBridge 163:e59c8e839560 490 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
AnnaBridge 163:e59c8e839560 491 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
AnnaBridge 163:e59c8e839560 492 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
AnnaBridge 163:e59c8e839560 493 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
AnnaBridge 163:e59c8e839560 494 #define TIM_IT_COM (TIM_DIER_COMIE)
AnnaBridge 163:e59c8e839560 495 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
AnnaBridge 163:e59c8e839560 496 #define TIM_IT_BREAK (TIM_DIER_BIE)
AnnaBridge 163:e59c8e839560 497 /**
AnnaBridge 163:e59c8e839560 498 * @}
AnnaBridge 163:e59c8e839560 499 */
AnnaBridge 163:e59c8e839560 500
AnnaBridge 163:e59c8e839560 501 /** @defgroup TIM_Commutation_Source TIM Commutation Source
AnnaBridge 163:e59c8e839560 502 * @{
AnnaBridge 163:e59c8e839560 503 */
AnnaBridge 163:e59c8e839560 504 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
AnnaBridge 163:e59c8e839560 505 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
AnnaBridge 163:e59c8e839560 506 /**
AnnaBridge 163:e59c8e839560 507 * @}
AnnaBridge 163:e59c8e839560 508 */
AnnaBridge 163:e59c8e839560 509
AnnaBridge 163:e59c8e839560 510 /** @defgroup TIM_DMA_sources TIM DMA sources
AnnaBridge 163:e59c8e839560 511 * @{
AnnaBridge 163:e59c8e839560 512 */
AnnaBridge 163:e59c8e839560 513 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
AnnaBridge 163:e59c8e839560 514 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
AnnaBridge 163:e59c8e839560 515 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
AnnaBridge 163:e59c8e839560 516 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
AnnaBridge 163:e59c8e839560 517 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
AnnaBridge 163:e59c8e839560 518 #define TIM_DMA_COM (TIM_DIER_COMDE)
AnnaBridge 163:e59c8e839560 519 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
AnnaBridge 163:e59c8e839560 520 /**
AnnaBridge 163:e59c8e839560 521 * @}
AnnaBridge 163:e59c8e839560 522 */
AnnaBridge 163:e59c8e839560 523
AnnaBridge 163:e59c8e839560 524 /** @defgroup TIM_Event_Source TIM Event Source
AnnaBridge 163:e59c8e839560 525 * @{
AnnaBridge 163:e59c8e839560 526 */
AnnaBridge 163:e59c8e839560 527 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
AnnaBridge 163:e59c8e839560 528 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
AnnaBridge 163:e59c8e839560 529 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
AnnaBridge 163:e59c8e839560 530 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
AnnaBridge 163:e59c8e839560 531 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
AnnaBridge 163:e59c8e839560 532 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
AnnaBridge 163:e59c8e839560 533 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
AnnaBridge 163:e59c8e839560 534 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
AnnaBridge 163:e59c8e839560 535
AnnaBridge 163:e59c8e839560 536 /**
AnnaBridge 163:e59c8e839560 537 * @}
AnnaBridge 163:e59c8e839560 538 */
AnnaBridge 163:e59c8e839560 539
AnnaBridge 163:e59c8e839560 540 /** @defgroup TIM_Flag_definition TIM Flag definition
AnnaBridge 163:e59c8e839560 541 * @{
AnnaBridge 163:e59c8e839560 542 */
AnnaBridge 163:e59c8e839560 543 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
AnnaBridge 163:e59c8e839560 544 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
AnnaBridge 163:e59c8e839560 545 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
AnnaBridge 163:e59c8e839560 546 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
AnnaBridge 163:e59c8e839560 547 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
AnnaBridge 163:e59c8e839560 548 #define TIM_FLAG_COM (TIM_SR_COMIF)
AnnaBridge 163:e59c8e839560 549 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
AnnaBridge 163:e59c8e839560 550 #define TIM_FLAG_BREAK (TIM_SR_BIF)
AnnaBridge 163:e59c8e839560 551 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
AnnaBridge 163:e59c8e839560 552 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
AnnaBridge 163:e59c8e839560 553 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
AnnaBridge 163:e59c8e839560 554 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
AnnaBridge 163:e59c8e839560 555 /**
AnnaBridge 163:e59c8e839560 556 * @}
AnnaBridge 163:e59c8e839560 557 */
AnnaBridge 163:e59c8e839560 558
AnnaBridge 163:e59c8e839560 559 /** @defgroup TIM_Clock_Source TIM Clock Source
AnnaBridge 163:e59c8e839560 560 * @{
AnnaBridge 163:e59c8e839560 561 */
AnnaBridge 163:e59c8e839560 562 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
AnnaBridge 163:e59c8e839560 563 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge 163:e59c8e839560 564 #define TIM_CLOCKSOURCE_ITR0 0x00000000U
AnnaBridge 163:e59c8e839560 565 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
AnnaBridge 163:e59c8e839560 566 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
AnnaBridge 163:e59c8e839560 567 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
AnnaBridge 163:e59c8e839560 568 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
AnnaBridge 163:e59c8e839560 569 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
AnnaBridge 163:e59c8e839560 570 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
AnnaBridge 163:e59c8e839560 571 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
AnnaBridge 163:e59c8e839560 572 /**
AnnaBridge 163:e59c8e839560 573 * @}
AnnaBridge 163:e59c8e839560 574 */
AnnaBridge 163:e59c8e839560 575
AnnaBridge 163:e59c8e839560 576 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
AnnaBridge 163:e59c8e839560 577 * @{
AnnaBridge 163:e59c8e839560 578 */
AnnaBridge 163:e59c8e839560 579 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 163:e59c8e839560 580 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 163:e59c8e839560 581 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
AnnaBridge 163:e59c8e839560 582 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
AnnaBridge 163:e59c8e839560 583 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
AnnaBridge 163:e59c8e839560 584 /**
AnnaBridge 163:e59c8e839560 585 * @}
AnnaBridge 163:e59c8e839560 586 */
AnnaBridge 163:e59c8e839560 587
AnnaBridge 163:e59c8e839560 588 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
AnnaBridge 163:e59c8e839560 589 * @{
AnnaBridge 163:e59c8e839560 590 */
AnnaBridge 163:e59c8e839560 591 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 163:e59c8e839560 592 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
AnnaBridge 163:e59c8e839560 593 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
AnnaBridge 163:e59c8e839560 594 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
AnnaBridge 163:e59c8e839560 595 /**
AnnaBridge 163:e59c8e839560 596 * @}
AnnaBridge 163:e59c8e839560 597 */
AnnaBridge 163:e59c8e839560 598
AnnaBridge 163:e59c8e839560 599 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
AnnaBridge 163:e59c8e839560 600 * @{
AnnaBridge 163:e59c8e839560 601 */
AnnaBridge 163:e59c8e839560 602 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
AnnaBridge 163:e59c8e839560 603 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
AnnaBridge 163:e59c8e839560 604 /**
AnnaBridge 163:e59c8e839560 605 * @}
AnnaBridge 163:e59c8e839560 606 */
AnnaBridge 163:e59c8e839560 607
AnnaBridge 163:e59c8e839560 608 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
AnnaBridge 163:e59c8e839560 609 * @{
AnnaBridge 163:e59c8e839560 610 */
AnnaBridge 163:e59c8e839560 611 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
AnnaBridge 163:e59c8e839560 612 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
AnnaBridge 163:e59c8e839560 613 /**
AnnaBridge 163:e59c8e839560 614 * @}
AnnaBridge 163:e59c8e839560 615 */
AnnaBridge 163:e59c8e839560 616
AnnaBridge 163:e59c8e839560 617 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
AnnaBridge 163:e59c8e839560 618 * @{
AnnaBridge 163:e59c8e839560 619 */
AnnaBridge 163:e59c8e839560 620 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 163:e59c8e839560 621 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
AnnaBridge 163:e59c8e839560 622 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
AnnaBridge 163:e59c8e839560 623 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
AnnaBridge 163:e59c8e839560 624 /**
AnnaBridge 163:e59c8e839560 625 * @}
AnnaBridge 163:e59c8e839560 626 */
AnnaBridge 163:e59c8e839560 627
AnnaBridge 163:e59c8e839560 628 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
AnnaBridge 163:e59c8e839560 629 * @{
AnnaBridge 163:e59c8e839560 630 */
AnnaBridge 163:e59c8e839560 631 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge 163:e59c8e839560 632 #define TIM_OSSR_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 633 /**
AnnaBridge 163:e59c8e839560 634 * @}
AnnaBridge 163:e59c8e839560 635 */
AnnaBridge 163:e59c8e839560 636
AnnaBridge 163:e59c8e839560 637 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
AnnaBridge 163:e59c8e839560 638 * @{
AnnaBridge 163:e59c8e839560 639 */
AnnaBridge 163:e59c8e839560 640 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge 163:e59c8e839560 641 #define TIM_OSSI_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 642 /**
AnnaBridge 163:e59c8e839560 643 * @}
AnnaBridge 163:e59c8e839560 644 */
AnnaBridge 163:e59c8e839560 645
AnnaBridge 163:e59c8e839560 646 /** @defgroup TIM_Lock_level TIM Lock level
AnnaBridge 163:e59c8e839560 647 * @{
AnnaBridge 163:e59c8e839560 648 */
AnnaBridge 163:e59c8e839560 649 #define TIM_LOCKLEVEL_OFF 0x00000000U
AnnaBridge 163:e59c8e839560 650 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
AnnaBridge 163:e59c8e839560 651 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
AnnaBridge 163:e59c8e839560 652 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
AnnaBridge 163:e59c8e839560 653 /**
AnnaBridge 163:e59c8e839560 654 * @}
AnnaBridge 163:e59c8e839560 655 */
AnnaBridge 163:e59c8e839560 656 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
AnnaBridge 163:e59c8e839560 657 * @{
AnnaBridge 163:e59c8e839560 658 */
AnnaBridge 163:e59c8e839560 659 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
AnnaBridge 163:e59c8e839560 660 #define TIM_BREAK_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 661 /**
AnnaBridge 163:e59c8e839560 662 * @}
AnnaBridge 163:e59c8e839560 663 */
AnnaBridge 163:e59c8e839560 664
AnnaBridge 163:e59c8e839560 665 /** @defgroup TIM_Break_Polarity TIM Break Polarity
AnnaBridge 163:e59c8e839560 666 * @{
AnnaBridge 163:e59c8e839560 667 */
AnnaBridge 163:e59c8e839560 668 #define TIM_BREAKPOLARITY_LOW 0x00000000U
AnnaBridge 163:e59c8e839560 669 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
AnnaBridge 163:e59c8e839560 670 /**
AnnaBridge 163:e59c8e839560 671 * @}
AnnaBridge 163:e59c8e839560 672 */
AnnaBridge 163:e59c8e839560 673
AnnaBridge 163:e59c8e839560 674 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
AnnaBridge 163:e59c8e839560 675 * @{
AnnaBridge 163:e59c8e839560 676 */
AnnaBridge 163:e59c8e839560 677 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge 163:e59c8e839560 678 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 679 /**
AnnaBridge 163:e59c8e839560 680 * @}
AnnaBridge 163:e59c8e839560 681 */
AnnaBridge 163:e59c8e839560 682
AnnaBridge 163:e59c8e839560 683 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge 163:e59c8e839560 684 * @{
AnnaBridge 163:e59c8e839560 685 */
AnnaBridge 163:e59c8e839560 686 #define TIM_TRGO_RESET 0x00000000U
AnnaBridge 163:e59c8e839560 687 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge 163:e59c8e839560 688 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge 163:e59c8e839560 689 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 163:e59c8e839560 690 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge 163:e59c8e839560 691 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
AnnaBridge 163:e59c8e839560 692 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
AnnaBridge 163:e59c8e839560 693 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 163:e59c8e839560 694 /**
AnnaBridge 163:e59c8e839560 695 * @}
AnnaBridge 163:e59c8e839560 696 */
AnnaBridge 163:e59c8e839560 697
AnnaBridge 163:e59c8e839560 698 /** @defgroup TIM_Slave_Mode TIM Slave Mode
AnnaBridge 163:e59c8e839560 699 * @{
AnnaBridge 163:e59c8e839560 700 */
AnnaBridge 163:e59c8e839560 701 #define TIM_SLAVEMODE_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 702 #define TIM_SLAVEMODE_RESET 0x00000004U
AnnaBridge 163:e59c8e839560 703 #define TIM_SLAVEMODE_GATED 0x00000005U
AnnaBridge 163:e59c8e839560 704 #define TIM_SLAVEMODE_TRIGGER 0x00000006U
AnnaBridge 163:e59c8e839560 705 #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
AnnaBridge 163:e59c8e839560 706 /**
AnnaBridge 163:e59c8e839560 707 * @}
AnnaBridge 163:e59c8e839560 708 */
AnnaBridge 163:e59c8e839560 709
AnnaBridge 163:e59c8e839560 710 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
AnnaBridge 163:e59c8e839560 711 * @{
AnnaBridge 163:e59c8e839560 712 */
AnnaBridge 163:e59c8e839560 713 #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
AnnaBridge 163:e59c8e839560 714 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 715 /**
AnnaBridge 163:e59c8e839560 716 * @}
AnnaBridge 163:e59c8e839560 717 */
AnnaBridge 163:e59c8e839560 718
AnnaBridge 163:e59c8e839560 719 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
AnnaBridge 163:e59c8e839560 720 * @{
AnnaBridge 163:e59c8e839560 721 */
AnnaBridge 163:e59c8e839560 722 #define TIM_TS_ITR0 0x00000000U
AnnaBridge 163:e59c8e839560 723 #define TIM_TS_ITR1 0x00000010U
AnnaBridge 163:e59c8e839560 724 #define TIM_TS_ITR2 0x00000020U
AnnaBridge 163:e59c8e839560 725 #define TIM_TS_ITR3 0x00000030U
AnnaBridge 163:e59c8e839560 726 #define TIM_TS_TI1F_ED 0x00000040U
AnnaBridge 163:e59c8e839560 727 #define TIM_TS_TI1FP1 0x00000050U
AnnaBridge 163:e59c8e839560 728 #define TIM_TS_TI2FP2 0x00000060U
AnnaBridge 163:e59c8e839560 729 #define TIM_TS_ETRF 0x00000070U
AnnaBridge 163:e59c8e839560 730 #define TIM_TS_NONE 0x0000FFFFU
AnnaBridge 163:e59c8e839560 731 /**
AnnaBridge 163:e59c8e839560 732 * @}
AnnaBridge 163:e59c8e839560 733 */
AnnaBridge 163:e59c8e839560 734
AnnaBridge 163:e59c8e839560 735 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
AnnaBridge 163:e59c8e839560 736 * @{
AnnaBridge 163:e59c8e839560 737 */
AnnaBridge 163:e59c8e839560 738 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 163:e59c8e839560 739 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 163:e59c8e839560 740 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 163:e59c8e839560 741 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 163:e59c8e839560 742 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 163:e59c8e839560 743 /**
AnnaBridge 163:e59c8e839560 744 * @}
AnnaBridge 163:e59c8e839560 745 */
AnnaBridge 163:e59c8e839560 746
AnnaBridge 163:e59c8e839560 747 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
AnnaBridge 163:e59c8e839560 748 * @{
AnnaBridge 163:e59c8e839560 749 */
AnnaBridge 163:e59c8e839560 750 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 163:e59c8e839560 751 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
AnnaBridge 163:e59c8e839560 752 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
AnnaBridge 163:e59c8e839560 753 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
AnnaBridge 163:e59c8e839560 754 /**
AnnaBridge 163:e59c8e839560 755 * @}
AnnaBridge 163:e59c8e839560 756 */
AnnaBridge 163:e59c8e839560 757
AnnaBridge 163:e59c8e839560 758
AnnaBridge 163:e59c8e839560 759 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
AnnaBridge 163:e59c8e839560 760 * @{
AnnaBridge 163:e59c8e839560 761 */
AnnaBridge 163:e59c8e839560 762 #define TIM_TI1SELECTION_CH1 0x00000000U
AnnaBridge 163:e59c8e839560 763 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
AnnaBridge 163:e59c8e839560 764 /**
AnnaBridge 163:e59c8e839560 765 * @}
AnnaBridge 163:e59c8e839560 766 */
AnnaBridge 163:e59c8e839560 767
AnnaBridge 163:e59c8e839560 768 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
AnnaBridge 163:e59c8e839560 769 * @{
AnnaBridge 163:e59c8e839560 770 */
AnnaBridge 163:e59c8e839560 771 #define TIM_DMABASE_CR1 0x00000000U
AnnaBridge 163:e59c8e839560 772 #define TIM_DMABASE_CR2 0x00000001U
AnnaBridge 163:e59c8e839560 773 #define TIM_DMABASE_SMCR 0x00000002U
AnnaBridge 163:e59c8e839560 774 #define TIM_DMABASE_DIER 0x00000003U
AnnaBridge 163:e59c8e839560 775 #define TIM_DMABASE_SR 0x00000004U
AnnaBridge 163:e59c8e839560 776 #define TIM_DMABASE_EGR 0x00000005U
AnnaBridge 163:e59c8e839560 777 #define TIM_DMABASE_CCMR1 0x00000006U
AnnaBridge 163:e59c8e839560 778 #define TIM_DMABASE_CCMR2 0x00000007U
AnnaBridge 163:e59c8e839560 779 #define TIM_DMABASE_CCER 0x00000008U
AnnaBridge 163:e59c8e839560 780 #define TIM_DMABASE_CNT 0x00000009U
AnnaBridge 163:e59c8e839560 781 #define TIM_DMABASE_PSC 0x0000000AU
AnnaBridge 163:e59c8e839560 782 #define TIM_DMABASE_ARR 0x0000000BU
AnnaBridge 163:e59c8e839560 783 #define TIM_DMABASE_RCR 0x0000000CU
AnnaBridge 163:e59c8e839560 784 #define TIM_DMABASE_CCR1 0x0000000DU
AnnaBridge 163:e59c8e839560 785 #define TIM_DMABASE_CCR2 0x0000000EU
AnnaBridge 163:e59c8e839560 786 #define TIM_DMABASE_CCR3 0x0000000FU
AnnaBridge 163:e59c8e839560 787 #define TIM_DMABASE_CCR4 0x00000010U
AnnaBridge 163:e59c8e839560 788 #define TIM_DMABASE_BDTR 0x00000011U
AnnaBridge 163:e59c8e839560 789 #define TIM_DMABASE_DCR 0x00000012U
AnnaBridge 163:e59c8e839560 790 #define TIM_DMABASE_OR 0x00000013U
AnnaBridge 163:e59c8e839560 791 /**
AnnaBridge 163:e59c8e839560 792 * @}
AnnaBridge 163:e59c8e839560 793 */
AnnaBridge 163:e59c8e839560 794
AnnaBridge 163:e59c8e839560 795 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
AnnaBridge 163:e59c8e839560 796 * @{
AnnaBridge 163:e59c8e839560 797 */
AnnaBridge 163:e59c8e839560 798 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
AnnaBridge 163:e59c8e839560 799 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
AnnaBridge 163:e59c8e839560 800 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
AnnaBridge 163:e59c8e839560 801 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
AnnaBridge 163:e59c8e839560 802 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
AnnaBridge 163:e59c8e839560 803 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
AnnaBridge 163:e59c8e839560 804 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
AnnaBridge 163:e59c8e839560 805 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
AnnaBridge 163:e59c8e839560 806 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
AnnaBridge 163:e59c8e839560 807 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
AnnaBridge 163:e59c8e839560 808 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
AnnaBridge 163:e59c8e839560 809 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
AnnaBridge 163:e59c8e839560 810 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
AnnaBridge 163:e59c8e839560 811 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
AnnaBridge 163:e59c8e839560 812 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
AnnaBridge 163:e59c8e839560 813 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
AnnaBridge 163:e59c8e839560 814 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
AnnaBridge 163:e59c8e839560 815 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
AnnaBridge 163:e59c8e839560 816 /**
AnnaBridge 163:e59c8e839560 817 * @}
AnnaBridge 163:e59c8e839560 818 */
AnnaBridge 163:e59c8e839560 819
AnnaBridge 163:e59c8e839560 820 /** @defgroup DMA_Handle_index DMA Handle index
AnnaBridge 163:e59c8e839560 821 * @{
AnnaBridge 163:e59c8e839560 822 */
AnnaBridge 163:e59c8e839560 823 #define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */
AnnaBridge 163:e59c8e839560 824 #define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
AnnaBridge 163:e59c8e839560 825 #define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
AnnaBridge 163:e59c8e839560 826 #define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
AnnaBridge 163:e59c8e839560 827 #define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
AnnaBridge 163:e59c8e839560 828 #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
AnnaBridge 163:e59c8e839560 829 #define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
AnnaBridge 163:e59c8e839560 830 /**
AnnaBridge 163:e59c8e839560 831 * @}
AnnaBridge 163:e59c8e839560 832 */
AnnaBridge 163:e59c8e839560 833
AnnaBridge 163:e59c8e839560 834 /** @defgroup Channel_CC_State Channel CC State
AnnaBridge 163:e59c8e839560 835 * @{
AnnaBridge 163:e59c8e839560 836 */
AnnaBridge 163:e59c8e839560 837 #define TIM_CCx_ENABLE 0x00000001U
AnnaBridge 163:e59c8e839560 838 #define TIM_CCx_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 839 #define TIM_CCxN_ENABLE 0x00000004U
AnnaBridge 163:e59c8e839560 840 #define TIM_CCxN_DISABLE 0x00000000U
AnnaBridge 163:e59c8e839560 841 /**
AnnaBridge 163:e59c8e839560 842 * @}
AnnaBridge 163:e59c8e839560 843 */
AnnaBridge 163:e59c8e839560 844
AnnaBridge 163:e59c8e839560 845 /**
AnnaBridge 163:e59c8e839560 846 * @}
AnnaBridge 163:e59c8e839560 847 */
AnnaBridge 163:e59c8e839560 848
AnnaBridge 163:e59c8e839560 849 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 850 /** @defgroup TIM_Exported_Macros TIM Exported Macros
AnnaBridge 163:e59c8e839560 851 * @{
AnnaBridge 163:e59c8e839560 852 */
AnnaBridge 163:e59c8e839560 853 /** @brief Reset TIM handle state
AnnaBridge 163:e59c8e839560 854 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 855 * @retval None
AnnaBridge 163:e59c8e839560 856 */
AnnaBridge 163:e59c8e839560 857 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge 163:e59c8e839560 858
AnnaBridge 163:e59c8e839560 859 /**
AnnaBridge 163:e59c8e839560 860 * @brief Enable the TIM peripheral.
AnnaBridge 163:e59c8e839560 861 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 862 * @retval None
AnnaBridge 163:e59c8e839560 863 */
AnnaBridge 163:e59c8e839560 864 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
AnnaBridge 163:e59c8e839560 865
AnnaBridge 163:e59c8e839560 866 /**
AnnaBridge 163:e59c8e839560 867 * @brief Enable the TIM main Output.
AnnaBridge 163:e59c8e839560 868 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 869 * @retval None
AnnaBridge 163:e59c8e839560 870 */
AnnaBridge 163:e59c8e839560 871 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
AnnaBridge 163:e59c8e839560 872
AnnaBridge 163:e59c8e839560 873
AnnaBridge 163:e59c8e839560 874 /**
AnnaBridge 163:e59c8e839560 875 * @brief Disable the TIM peripheral.
AnnaBridge 163:e59c8e839560 876 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 877 * @retval None
AnnaBridge 163:e59c8e839560 878 */
AnnaBridge 163:e59c8e839560 879 #define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge 163:e59c8e839560 880 do { \
AnnaBridge 163:e59c8e839560 881 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
AnnaBridge 163:e59c8e839560 882 { \
AnnaBridge 163:e59c8e839560 883 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
AnnaBridge 163:e59c8e839560 884 { \
AnnaBridge 163:e59c8e839560 885 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge 163:e59c8e839560 886 } \
AnnaBridge 163:e59c8e839560 887 } \
AnnaBridge 163:e59c8e839560 888 } while(0U)
AnnaBridge 163:e59c8e839560 889
AnnaBridge 163:e59c8e839560 890 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge 163:e59c8e839560 891 channels have been disabled */
AnnaBridge 163:e59c8e839560 892 /**
AnnaBridge 163:e59c8e839560 893 * @brief Disable the TIM main Output.
AnnaBridge 163:e59c8e839560 894 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 895 * @retval None
AnnaBridge 163:e59c8e839560 896 */
AnnaBridge 163:e59c8e839560 897 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
AnnaBridge 163:e59c8e839560 898 do { \
AnnaBridge 163:e59c8e839560 899 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
AnnaBridge 163:e59c8e839560 900 { \
AnnaBridge 163:e59c8e839560 901 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
AnnaBridge 163:e59c8e839560 902 { \
AnnaBridge 163:e59c8e839560 903 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
AnnaBridge 163:e59c8e839560 904 } \
AnnaBridge 163:e59c8e839560 905 } \
AnnaBridge 163:e59c8e839560 906 } while(0U)
AnnaBridge 163:e59c8e839560 907
AnnaBridge 163:e59c8e839560 908 /**
AnnaBridge 163:e59c8e839560 909 * @brief Disable the TIM main Output.
AnnaBridge 163:e59c8e839560 910 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 911 * @retval None
AnnaBridge 163:e59c8e839560 912 * @note The Main Output Enable of a timer instance is disabled unconditionally
AnnaBridge 163:e59c8e839560 913 */
AnnaBridge 163:e59c8e839560 914 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
AnnaBridge 163:e59c8e839560 915
AnnaBridge 163:e59c8e839560 916 /** @brief Enable the specified TIM interrupt.
AnnaBridge 163:e59c8e839560 917 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 163:e59c8e839560 918 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
AnnaBridge 163:e59c8e839560 919 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 920 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 163:e59c8e839560 921 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 163:e59c8e839560 922 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 163:e59c8e839560 923 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 163:e59c8e839560 924 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 163:e59c8e839560 925 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 163:e59c8e839560 926 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 163:e59c8e839560 927 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 163:e59c8e839560 928 * @retval None
AnnaBridge 163:e59c8e839560 929 */
AnnaBridge 163:e59c8e839560 930 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
AnnaBridge 163:e59c8e839560 931
AnnaBridge 163:e59c8e839560 932
AnnaBridge 163:e59c8e839560 933 /** @brief Disable the specified TIM interrupt.
AnnaBridge 163:e59c8e839560 934 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 163:e59c8e839560 935 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
AnnaBridge 163:e59c8e839560 936 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 937 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 163:e59c8e839560 938 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 163:e59c8e839560 939 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 163:e59c8e839560 940 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 163:e59c8e839560 941 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 163:e59c8e839560 942 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 163:e59c8e839560 943 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 163:e59c8e839560 944 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 163:e59c8e839560 945 * @retval None
AnnaBridge 163:e59c8e839560 946 */
AnnaBridge 163:e59c8e839560 947 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge 163:e59c8e839560 948
AnnaBridge 163:e59c8e839560 949 /** @brief Enable the specified DMA request.
AnnaBridge 163:e59c8e839560 950 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 163:e59c8e839560 951 * @param __DMA__ specifies the TIM DMA request to enable.
AnnaBridge 163:e59c8e839560 952 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 953 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 163:e59c8e839560 954 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 163:e59c8e839560 955 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 163:e59c8e839560 956 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 163:e59c8e839560 957 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 163:e59c8e839560 958 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 163:e59c8e839560 959 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 163:e59c8e839560 960 * @retval None
AnnaBridge 163:e59c8e839560 961 */
AnnaBridge 163:e59c8e839560 962 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
AnnaBridge 163:e59c8e839560 963
AnnaBridge 163:e59c8e839560 964 /** @brief Disable the specified DMA request.
AnnaBridge 163:e59c8e839560 965 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 163:e59c8e839560 966 * @param __DMA__ specifies the TIM DMA request to disable.
AnnaBridge 163:e59c8e839560 967 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 968 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 163:e59c8e839560 969 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 163:e59c8e839560 970 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 163:e59c8e839560 971 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 163:e59c8e839560 972 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 163:e59c8e839560 973 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 163:e59c8e839560 974 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 163:e59c8e839560 975 * @retval None
AnnaBridge 163:e59c8e839560 976 */
AnnaBridge 163:e59c8e839560 977 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge 163:e59c8e839560 978
AnnaBridge 163:e59c8e839560 979 /** @brief Check whether the specified TIM interrupt flag is set or not.
AnnaBridge 163:e59c8e839560 980 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 163:e59c8e839560 981 * @param __FLAG__ specifies the TIM interrupt flag to check.
AnnaBridge 163:e59c8e839560 982 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 983 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 163:e59c8e839560 984 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 163:e59c8e839560 985 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 163:e59c8e839560 986 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 163:e59c8e839560 987 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 163:e59c8e839560 988 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge 163:e59c8e839560 989 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge 163:e59c8e839560 990 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 163:e59c8e839560 991 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 163:e59c8e839560 992 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 163:e59c8e839560 993 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge 163:e59c8e839560 994 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge 163:e59c8e839560 995 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 163:e59c8e839560 996 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 163:e59c8e839560 997 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 163:e59c8e839560 998 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 163:e59c8e839560 999 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 163:e59c8e839560 1000 */
AnnaBridge 163:e59c8e839560 1001 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge 163:e59c8e839560 1002
AnnaBridge 163:e59c8e839560 1003 /** @brief Clear the specified TIM interrupt flag.
AnnaBridge 163:e59c8e839560 1004 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 163:e59c8e839560 1005 * @param __FLAG__ specifies the TIM interrupt flag to clear.
AnnaBridge 163:e59c8e839560 1006 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1007 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 163:e59c8e839560 1008 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 163:e59c8e839560 1009 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 163:e59c8e839560 1010 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 163:e59c8e839560 1011 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 163:e59c8e839560 1012 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge 163:e59c8e839560 1013 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge 163:e59c8e839560 1014 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 163:e59c8e839560 1015 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 163:e59c8e839560 1016 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 163:e59c8e839560 1017 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge 163:e59c8e839560 1018 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge 163:e59c8e839560 1019 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 163:e59c8e839560 1020 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 163:e59c8e839560 1021 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 163:e59c8e839560 1022 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 163:e59c8e839560 1023 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 163:e59c8e839560 1024 */
AnnaBridge 163:e59c8e839560 1025 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge 163:e59c8e839560 1026
AnnaBridge 163:e59c8e839560 1027 /**
AnnaBridge 163:e59c8e839560 1028 * @brief Check whether the specified TIM interrupt source is enabled or not.
AnnaBridge 163:e59c8e839560 1029 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 1030 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
AnnaBridge 163:e59c8e839560 1031 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1032 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 163:e59c8e839560 1033 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 163:e59c8e839560 1034 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 163:e59c8e839560 1035 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 163:e59c8e839560 1036 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 163:e59c8e839560 1037 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 163:e59c8e839560 1038 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 163:e59c8e839560 1039 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 163:e59c8e839560 1040 * @retval The state of TIM_IT (SET or RESET).
AnnaBridge 163:e59c8e839560 1041 */
AnnaBridge 163:e59c8e839560 1042 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 163:e59c8e839560 1043
AnnaBridge 163:e59c8e839560 1044 /** @brief Clear the TIM interrupt pending bits.
AnnaBridge 163:e59c8e839560 1045 * @param __HANDLE__ TIM handle
AnnaBridge 163:e59c8e839560 1046 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 163:e59c8e839560 1047 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1048 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 163:e59c8e839560 1049 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 163:e59c8e839560 1050 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 163:e59c8e839560 1051 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 163:e59c8e839560 1052 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 163:e59c8e839560 1053 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 163:e59c8e839560 1054 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 163:e59c8e839560 1055 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 163:e59c8e839560 1056 * @retval None
AnnaBridge 163:e59c8e839560 1057 */
AnnaBridge 163:e59c8e839560 1058 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge 163:e59c8e839560 1059
AnnaBridge 163:e59c8e839560 1060 /**
AnnaBridge 163:e59c8e839560 1061 * @brief Indicates whether or not the TIM Counter is used as downcounter.
AnnaBridge 163:e59c8e839560 1062 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1063 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
AnnaBridge 163:e59c8e839560 1064 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
AnnaBridge 163:e59c8e839560 1065 mode.
AnnaBridge 163:e59c8e839560 1066 */
AnnaBridge 163:e59c8e839560 1067 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge 163:e59c8e839560 1068
AnnaBridge 163:e59c8e839560 1069 /**
AnnaBridge 163:e59c8e839560 1070 * @brief Set the TIM Prescaler on runtime.
AnnaBridge 163:e59c8e839560 1071 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1072 * @param __PRESC__ specifies the Prescaler new value.
AnnaBridge 163:e59c8e839560 1073 * @retval None
AnnaBridge 163:e59c8e839560 1074 */
AnnaBridge 163:e59c8e839560 1075 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge 163:e59c8e839560 1076
AnnaBridge 163:e59c8e839560 1077 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 163:e59c8e839560 1078 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
AnnaBridge 163:e59c8e839560 1079 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
AnnaBridge 163:e59c8e839560 1080 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
AnnaBridge 163:e59c8e839560 1081 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
AnnaBridge 163:e59c8e839560 1082
AnnaBridge 163:e59c8e839560 1083 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 1084 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
AnnaBridge 163:e59c8e839560 1085 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
AnnaBridge 163:e59c8e839560 1086 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
AnnaBridge 163:e59c8e839560 1087 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
AnnaBridge 163:e59c8e839560 1088
AnnaBridge 163:e59c8e839560 1089 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 163:e59c8e839560 1090 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
AnnaBridge 163:e59c8e839560 1091 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
AnnaBridge 163:e59c8e839560 1092 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
AnnaBridge 163:e59c8e839560 1093 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
AnnaBridge 163:e59c8e839560 1094
AnnaBridge 163:e59c8e839560 1095 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 1096 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
AnnaBridge 163:e59c8e839560 1097 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
AnnaBridge 163:e59c8e839560 1098 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
AnnaBridge 163:e59c8e839560 1099 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
AnnaBridge 163:e59c8e839560 1100
AnnaBridge 163:e59c8e839560 1101 /**
AnnaBridge 163:e59c8e839560 1102 * @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge 163:e59c8e839560 1103 * calling another time ConfigChannel function.
AnnaBridge 163:e59c8e839560 1104 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1105 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 1106 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 1108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 1109 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 1110 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 1111 * @param __COMPARE__ specifies the Capture Compare register new value.
AnnaBridge 163:e59c8e839560 1112 * @retval None
AnnaBridge 163:e59c8e839560 1113 */
AnnaBridge 163:e59c8e839560 1114 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge 163:e59c8e839560 1115 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
AnnaBridge 163:e59c8e839560 1116
AnnaBridge 163:e59c8e839560 1117 /**
AnnaBridge 163:e59c8e839560 1118 * @brief Gets the TIM Capture Compare Register value on runtime.
AnnaBridge 163:e59c8e839560 1119 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1120 * @param __CHANNEL__ TIM Channel associated with the capture compare register
AnnaBridge 163:e59c8e839560 1121 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1122 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge 163:e59c8e839560 1123 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge 163:e59c8e839560 1124 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge 163:e59c8e839560 1125 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge 163:e59c8e839560 1126 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
AnnaBridge 163:e59c8e839560 1127 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
AnnaBridge 163:e59c8e839560 1128 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
AnnaBridge 163:e59c8e839560 1129 */
AnnaBridge 163:e59c8e839560 1130 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 1131 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
AnnaBridge 163:e59c8e839560 1132
AnnaBridge 163:e59c8e839560 1133 /**
AnnaBridge 163:e59c8e839560 1134 * @brief Sets the TIM Counter Register value on runtime.
AnnaBridge 163:e59c8e839560 1135 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1136 * @param __COUNTER__ specifies the Counter register new value.
AnnaBridge 163:e59c8e839560 1137 * @retval None
AnnaBridge 163:e59c8e839560 1138 */
AnnaBridge 163:e59c8e839560 1139 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge 163:e59c8e839560 1140
AnnaBridge 163:e59c8e839560 1141 /**
AnnaBridge 163:e59c8e839560 1142 * @brief Gets the TIM Counter Register value on runtime.
AnnaBridge 163:e59c8e839560 1143 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1144 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
AnnaBridge 163:e59c8e839560 1145 */
AnnaBridge 163:e59c8e839560 1146 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
AnnaBridge 163:e59c8e839560 1147
AnnaBridge 163:e59c8e839560 1148 /**
AnnaBridge 163:e59c8e839560 1149 * @brief Sets the TIM Autoreload Register value on runtime without calling
AnnaBridge 163:e59c8e839560 1150 * another time any Init function.
AnnaBridge 163:e59c8e839560 1151 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1152 * @param __AUTORELOAD__ specifies the Counter register new value.
AnnaBridge 163:e59c8e839560 1153 * @retval None
AnnaBridge 163:e59c8e839560 1154 */
AnnaBridge 163:e59c8e839560 1155 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge 163:e59c8e839560 1156 do{ \
AnnaBridge 163:e59c8e839560 1157 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge 163:e59c8e839560 1158 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge 163:e59c8e839560 1159 } while(0U)
AnnaBridge 163:e59c8e839560 1160 /**
AnnaBridge 163:e59c8e839560 1161 * @brief Gets the TIM Autoreload Register value on runtime.
AnnaBridge 163:e59c8e839560 1162 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1163 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
AnnaBridge 163:e59c8e839560 1164 */
AnnaBridge 163:e59c8e839560 1165 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
AnnaBridge 163:e59c8e839560 1166
AnnaBridge 163:e59c8e839560 1167 /**
AnnaBridge 163:e59c8e839560 1168 * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function.
AnnaBridge 163:e59c8e839560 1169 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1170 * @param __CKD__ specifies the clock division value.
AnnaBridge 163:e59c8e839560 1171 * This parameter can be one of the following value:
AnnaBridge 163:e59c8e839560 1172 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge 163:e59c8e839560 1173 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge 163:e59c8e839560 1174 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge 163:e59c8e839560 1175 * @retval None
AnnaBridge 163:e59c8e839560 1176 */
AnnaBridge 163:e59c8e839560 1177 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge 163:e59c8e839560 1178 do{ \
AnnaBridge 163:e59c8e839560 1179 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
AnnaBridge 163:e59c8e839560 1180 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
AnnaBridge 163:e59c8e839560 1181 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge 163:e59c8e839560 1182 } while(0U)
AnnaBridge 163:e59c8e839560 1183 /**
AnnaBridge 163:e59c8e839560 1184 * @brief Gets the TIM Clock Division value on runtime.
AnnaBridge 163:e59c8e839560 1185 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1186 * @retval The clock division can be one of the following values:
AnnaBridge 163:e59c8e839560 1187 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge 163:e59c8e839560 1188 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge 163:e59c8e839560 1189 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge 163:e59c8e839560 1190 */
AnnaBridge 163:e59c8e839560 1191 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge 163:e59c8e839560 1192
AnnaBridge 163:e59c8e839560 1193 /**
AnnaBridge 163:e59c8e839560 1194 * @brief Sets the TIM Input Capture prescaler on runtime without calling
AnnaBridge 163:e59c8e839560 1195 * another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge 163:e59c8e839560 1196 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1197 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 1198 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1199 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 1200 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 1201 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 1202 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 1203 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
AnnaBridge 163:e59c8e839560 1204 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1205 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 163:e59c8e839560 1206 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 163:e59c8e839560 1207 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 163:e59c8e839560 1208 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 163:e59c8e839560 1209 * @retval None
AnnaBridge 163:e59c8e839560 1210 */
AnnaBridge 163:e59c8e839560 1211 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 163:e59c8e839560 1212 do{ \
AnnaBridge 163:e59c8e839560 1213 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 163:e59c8e839560 1214 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge 163:e59c8e839560 1215 } while(0U)
AnnaBridge 163:e59c8e839560 1216
AnnaBridge 163:e59c8e839560 1217 /**
AnnaBridge 163:e59c8e839560 1218 * @brief Get the TIM Input Capture prescaler on runtime.
AnnaBridge 163:e59c8e839560 1219 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1220 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 1221 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1222 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge 163:e59c8e839560 1223 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge 163:e59c8e839560 1224 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge 163:e59c8e839560 1225 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge 163:e59c8e839560 1226 * @retval The input capture prescaler can be one of the following values:
AnnaBridge 163:e59c8e839560 1227 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 163:e59c8e839560 1228 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 163:e59c8e839560 1229 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 163:e59c8e839560 1230 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 163:e59c8e839560 1231 */
AnnaBridge 163:e59c8e839560 1232 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge 163:e59c8e839560 1233 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge 163:e59c8e839560 1234 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
AnnaBridge 163:e59c8e839560 1235 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge 163:e59c8e839560 1236 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
AnnaBridge 163:e59c8e839560 1237
AnnaBridge 163:e59c8e839560 1238 /**
AnnaBridge 163:e59c8e839560 1239 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 163:e59c8e839560 1240 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1241 * @note When the USR bit of the TIMx_CR1 register is set, only counter
AnnaBridge 163:e59c8e839560 1242 * overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge 163:e59c8e839560 1243 * enabled)
AnnaBridge 163:e59c8e839560 1244 * @retval None
AnnaBridge 163:e59c8e839560 1245 */
AnnaBridge 163:e59c8e839560 1246 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge 163:e59c8e839560 1247 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
AnnaBridge 163:e59c8e839560 1248
AnnaBridge 163:e59c8e839560 1249 /**
AnnaBridge 163:e59c8e839560 1250 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 163:e59c8e839560 1251 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1252 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
AnnaBridge 163:e59c8e839560 1253 * following events generate an update interrupt or DMA request (if
AnnaBridge 163:e59c8e839560 1254 * enabled):
AnnaBridge 163:e59c8e839560 1255 * _ Counter overflow/underflow
AnnaBridge 163:e59c8e839560 1256 * _ Setting the UG bit
AnnaBridge 163:e59c8e839560 1257 * _ Update generation through the slave mode controller
AnnaBridge 163:e59c8e839560 1258 * @retval None
AnnaBridge 163:e59c8e839560 1259 */
AnnaBridge 163:e59c8e839560 1260 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge 163:e59c8e839560 1261 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
AnnaBridge 163:e59c8e839560 1262
AnnaBridge 163:e59c8e839560 1263 /**
AnnaBridge 163:e59c8e839560 1264 * @brief Sets the TIM Capture x input polarity on runtime.
AnnaBridge 163:e59c8e839560 1265 * @param __HANDLE__ TIM handle.
AnnaBridge 163:e59c8e839560 1266 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 163:e59c8e839560 1267 * This parameter can be one of the following values:
AnnaBridge 163:e59c8e839560 1268 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 163:e59c8e839560 1269 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 163:e59c8e839560 1270 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 163:e59c8e839560 1271 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 163:e59c8e839560 1272 * @param __POLARITY__ Polarity for TIx source
AnnaBridge 163:e59c8e839560 1273 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge 163:e59c8e839560 1274 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge 163:e59c8e839560 1275 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge 163:e59c8e839560 1276 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
AnnaBridge 163:e59c8e839560 1277 * @retval None
AnnaBridge 163:e59c8e839560 1278 */
AnnaBridge 163:e59c8e839560 1279 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 163:e59c8e839560 1280 do{ \
AnnaBridge 163:e59c8e839560 1281 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 163:e59c8e839560 1282 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge 163:e59c8e839560 1283 }while(0U)
AnnaBridge 163:e59c8e839560 1284 /**
AnnaBridge 163:e59c8e839560 1285 * @}
AnnaBridge 163:e59c8e839560 1286 */
AnnaBridge 163:e59c8e839560 1287
AnnaBridge 163:e59c8e839560 1288 /* Include TIM HAL Extension module */
AnnaBridge 163:e59c8e839560 1289 #include "stm32f4xx_hal_tim_ex.h"
AnnaBridge 163:e59c8e839560 1290
AnnaBridge 163:e59c8e839560 1291 /* Exported functions --------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1292 /** @addtogroup TIM_Exported_Functions
AnnaBridge 163:e59c8e839560 1293 * @{
AnnaBridge 163:e59c8e839560 1294 */
AnnaBridge 163:e59c8e839560 1295
AnnaBridge 163:e59c8e839560 1296 /** @addtogroup TIM_Exported_Functions_Group1
AnnaBridge 163:e59c8e839560 1297 * @{
AnnaBridge 163:e59c8e839560 1298 */
AnnaBridge 163:e59c8e839560 1299
AnnaBridge 163:e59c8e839560 1300 /* Time Base functions ********************************************************/
AnnaBridge 163:e59c8e839560 1301 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1302 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1303 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1304 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1305 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1306 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1307 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1308 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1309 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1310 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1311 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1312 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
AnnaBridge 163:e59c8e839560 1313 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1314 /**
AnnaBridge 163:e59c8e839560 1315 * @}
AnnaBridge 163:e59c8e839560 1316 */
AnnaBridge 163:e59c8e839560 1317
AnnaBridge 163:e59c8e839560 1318 /** @addtogroup TIM_Exported_Functions_Group2
AnnaBridge 163:e59c8e839560 1319 * @{
AnnaBridge 163:e59c8e839560 1320 */
AnnaBridge 163:e59c8e839560 1321 /* Timer Output Compare functions **********************************************/
AnnaBridge 163:e59c8e839560 1322 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1323 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1324 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1325 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1326 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1327 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1328 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1329 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1330 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1331 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1332 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1333 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 163:e59c8e839560 1334 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1335
AnnaBridge 163:e59c8e839560 1336 /**
AnnaBridge 163:e59c8e839560 1337 * @}
AnnaBridge 163:e59c8e839560 1338 */
AnnaBridge 163:e59c8e839560 1339
AnnaBridge 163:e59c8e839560 1340 /** @addtogroup TIM_Exported_Functions_Group3
AnnaBridge 163:e59c8e839560 1341 * @{
AnnaBridge 163:e59c8e839560 1342 */
AnnaBridge 163:e59c8e839560 1343 /* Timer PWM functions *********************************************************/
AnnaBridge 163:e59c8e839560 1344 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1345 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1346 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1347 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1348 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1349 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1350 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1351 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1352 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1353 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1354 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1355 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 163:e59c8e839560 1356 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1357
AnnaBridge 163:e59c8e839560 1358 /**
AnnaBridge 163:e59c8e839560 1359 * @}
AnnaBridge 163:e59c8e839560 1360 */
AnnaBridge 163:e59c8e839560 1361
AnnaBridge 163:e59c8e839560 1362 /** @addtogroup TIM_Exported_Functions_Group4
AnnaBridge 163:e59c8e839560 1363 * @{
AnnaBridge 163:e59c8e839560 1364 */
AnnaBridge 163:e59c8e839560 1365 /* Timer Input Capture functions ***********************************************/
AnnaBridge 163:e59c8e839560 1366 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1367 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1368 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1369 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1370 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1371 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1372 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1373 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1374 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1375 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1376 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1377 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 163:e59c8e839560 1378 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1379
AnnaBridge 163:e59c8e839560 1380 /**
AnnaBridge 163:e59c8e839560 1381 * @}
AnnaBridge 163:e59c8e839560 1382 */
AnnaBridge 163:e59c8e839560 1383
AnnaBridge 163:e59c8e839560 1384 /** @addtogroup TIM_Exported_Functions_Group5
AnnaBridge 163:e59c8e839560 1385 * @{
AnnaBridge 163:e59c8e839560 1386 */
AnnaBridge 163:e59c8e839560 1387 /* Timer One Pulse functions ***************************************************/
AnnaBridge 163:e59c8e839560 1388 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge 163:e59c8e839560 1389 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1390 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1391 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1392 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1393 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1394 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1395
AnnaBridge 163:e59c8e839560 1396 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1397 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1398 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 163:e59c8e839560 1399
AnnaBridge 163:e59c8e839560 1400 /**
AnnaBridge 163:e59c8e839560 1401 * @}
AnnaBridge 163:e59c8e839560 1402 */
AnnaBridge 163:e59c8e839560 1403
AnnaBridge 163:e59c8e839560 1404 /** @addtogroup TIM_Exported_Functions_Group6
AnnaBridge 163:e59c8e839560 1405 * @{
AnnaBridge 163:e59c8e839560 1406 */
AnnaBridge 163:e59c8e839560 1407 /* Timer Encoder functions *****************************************************/
AnnaBridge 163:e59c8e839560 1408 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
AnnaBridge 163:e59c8e839560 1409 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1410 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1411 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1412 /* Blocking mode: Polling */
AnnaBridge 163:e59c8e839560 1413 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1414 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1415 /* Non-Blocking mode: Interrupt */
AnnaBridge 163:e59c8e839560 1416 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1417 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1418 /* Non-Blocking mode: DMA */
AnnaBridge 163:e59c8e839560 1419 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge 163:e59c8e839560 1420 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1421
AnnaBridge 163:e59c8e839560 1422 /**
AnnaBridge 163:e59c8e839560 1423 * @}
AnnaBridge 163:e59c8e839560 1424 */
AnnaBridge 163:e59c8e839560 1425
AnnaBridge 163:e59c8e839560 1426 /** @addtogroup TIM_Exported_Functions_Group7
AnnaBridge 163:e59c8e839560 1427 * @{
AnnaBridge 163:e59c8e839560 1428 */
AnnaBridge 163:e59c8e839560 1429 /* Interrupt Handler functions **********************************************/
AnnaBridge 163:e59c8e839560 1430 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1431
AnnaBridge 163:e59c8e839560 1432 /**
AnnaBridge 163:e59c8e839560 1433 * @}
AnnaBridge 163:e59c8e839560 1434 */
AnnaBridge 163:e59c8e839560 1435
AnnaBridge 163:e59c8e839560 1436 /** @addtogroup TIM_Exported_Functions_Group8
AnnaBridge 163:e59c8e839560 1437 * @{
AnnaBridge 163:e59c8e839560 1438 */
AnnaBridge 163:e59c8e839560 1439 /* Control functions *********************************************************/
AnnaBridge 163:e59c8e839560 1440 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1441 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1442 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1443 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge 163:e59c8e839560 1444 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1445 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
AnnaBridge 163:e59c8e839560 1446 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge 163:e59c8e839560 1447 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 163:e59c8e839560 1448 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 163:e59c8e839560 1449 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 163:e59c8e839560 1450 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 163:e59c8e839560 1451 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 163:e59c8e839560 1452 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 163:e59c8e839560 1453 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 163:e59c8e839560 1454 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 163:e59c8e839560 1455 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge 163:e59c8e839560 1456 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 163:e59c8e839560 1457
AnnaBridge 163:e59c8e839560 1458 /**
AnnaBridge 163:e59c8e839560 1459 * @}
AnnaBridge 163:e59c8e839560 1460 */
AnnaBridge 163:e59c8e839560 1461
AnnaBridge 163:e59c8e839560 1462 /** @addtogroup TIM_Exported_Functions_Group9
AnnaBridge 163:e59c8e839560 1463 * @{
AnnaBridge 163:e59c8e839560 1464 */
AnnaBridge 163:e59c8e839560 1465 /* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge 163:e59c8e839560 1466 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1467 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1468 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1469 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1470 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1471 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1472
AnnaBridge 163:e59c8e839560 1473 /**
AnnaBridge 163:e59c8e839560 1474 * @}
AnnaBridge 163:e59c8e839560 1475 */
AnnaBridge 163:e59c8e839560 1476
AnnaBridge 163:e59c8e839560 1477 /** @addtogroup TIM_Exported_Functions_Group10
AnnaBridge 163:e59c8e839560 1478 * @{
AnnaBridge 163:e59c8e839560 1479 */
AnnaBridge 163:e59c8e839560 1480 /* Peripheral State functions **************************************************/
AnnaBridge 163:e59c8e839560 1481 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1482 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1483 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1484 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1485 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1486 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 163:e59c8e839560 1487
AnnaBridge 163:e59c8e839560 1488 /**
AnnaBridge 163:e59c8e839560 1489 * @}
AnnaBridge 163:e59c8e839560 1490 */
AnnaBridge 163:e59c8e839560 1491
AnnaBridge 163:e59c8e839560 1492 /**
AnnaBridge 163:e59c8e839560 1493 * @}
AnnaBridge 163:e59c8e839560 1494 */
AnnaBridge 163:e59c8e839560 1495
AnnaBridge 163:e59c8e839560 1496 /* Private macros ------------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1497 /** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge 163:e59c8e839560 1498 * @{
AnnaBridge 163:e59c8e839560 1499 */
AnnaBridge 163:e59c8e839560 1500
AnnaBridge 163:e59c8e839560 1501 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
AnnaBridge 163:e59c8e839560 1502 * @{
AnnaBridge 163:e59c8e839560 1503 */
AnnaBridge 163:e59c8e839560 1504 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
AnnaBridge 163:e59c8e839560 1505 ((MODE) == TIM_COUNTERMODE_DOWN) || \
AnnaBridge 163:e59c8e839560 1506 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
AnnaBridge 163:e59c8e839560 1507 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
AnnaBridge 163:e59c8e839560 1508 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge 163:e59c8e839560 1509
AnnaBridge 163:e59c8e839560 1510 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
AnnaBridge 163:e59c8e839560 1511 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
AnnaBridge 163:e59c8e839560 1512 ((DIV) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge 163:e59c8e839560 1513
AnnaBridge 163:e59c8e839560 1514 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
AnnaBridge 163:e59c8e839560 1515 ((MODE) == TIM_OCMODE_PWM2))
AnnaBridge 163:e59c8e839560 1516
AnnaBridge 163:e59c8e839560 1517 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
AnnaBridge 163:e59c8e839560 1518 ((MODE) == TIM_OCMODE_ACTIVE) || \
AnnaBridge 163:e59c8e839560 1519 ((MODE) == TIM_OCMODE_INACTIVE) || \
AnnaBridge 163:e59c8e839560 1520 ((MODE) == TIM_OCMODE_TOGGLE) || \
AnnaBridge 163:e59c8e839560 1521 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
AnnaBridge 163:e59c8e839560 1522 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
AnnaBridge 163:e59c8e839560 1523
AnnaBridge 163:e59c8e839560 1524 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
AnnaBridge 163:e59c8e839560 1525 ((STATE) == TIM_OCFAST_ENABLE))
AnnaBridge 163:e59c8e839560 1526
AnnaBridge 163:e59c8e839560 1527 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
AnnaBridge 163:e59c8e839560 1528 ((POLARITY) == TIM_OCPOLARITY_LOW))
AnnaBridge 163:e59c8e839560 1529
AnnaBridge 163:e59c8e839560 1530 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
AnnaBridge 163:e59c8e839560 1531 ((POLARITY) == TIM_OCNPOLARITY_LOW))
AnnaBridge 163:e59c8e839560 1532
AnnaBridge 163:e59c8e839560 1533 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
AnnaBridge 163:e59c8e839560 1534 ((STATE) == TIM_OCIDLESTATE_RESET))
AnnaBridge 163:e59c8e839560 1535
AnnaBridge 163:e59c8e839560 1536 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
AnnaBridge 163:e59c8e839560 1537 ((STATE) == TIM_OCNIDLESTATE_RESET))
AnnaBridge 163:e59c8e839560 1538
AnnaBridge 163:e59c8e839560 1539 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 1540 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 163:e59c8e839560 1541 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 163:e59c8e839560 1542 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 163:e59c8e839560 1543 ((CHANNEL) == TIM_CHANNEL_ALL))
AnnaBridge 163:e59c8e839560 1544
AnnaBridge 163:e59c8e839560 1545 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 1546 ((CHANNEL) == TIM_CHANNEL_2))
AnnaBridge 163:e59c8e839560 1547
AnnaBridge 163:e59c8e839560 1548 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 163:e59c8e839560 1549 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 163:e59c8e839560 1550 ((CHANNEL) == TIM_CHANNEL_3))
AnnaBridge 163:e59c8e839560 1551
AnnaBridge 163:e59c8e839560 1552 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
AnnaBridge 163:e59c8e839560 1553 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
AnnaBridge 163:e59c8e839560 1554 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge 163:e59c8e839560 1555
AnnaBridge 163:e59c8e839560 1556 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
AnnaBridge 163:e59c8e839560 1557 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
AnnaBridge 163:e59c8e839560 1558 ((SELECTION) == TIM_ICSELECTION_TRC))
AnnaBridge 163:e59c8e839560 1559
AnnaBridge 163:e59c8e839560 1560 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
AnnaBridge 163:e59c8e839560 1561 ((PRESCALER) == TIM_ICPSC_DIV2) || \
AnnaBridge 163:e59c8e839560 1562 ((PRESCALER) == TIM_ICPSC_DIV4) || \
AnnaBridge 163:e59c8e839560 1563 ((PRESCALER) == TIM_ICPSC_DIV8))
AnnaBridge 163:e59c8e839560 1564
AnnaBridge 163:e59c8e839560 1565 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
AnnaBridge 163:e59c8e839560 1566 ((MODE) == TIM_OPMODE_REPETITIVE))
AnnaBridge 163:e59c8e839560 1567
AnnaBridge 163:e59c8e839560 1568 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 163:e59c8e839560 1569
AnnaBridge 163:e59c8e839560 1570 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
AnnaBridge 163:e59c8e839560 1571 ((MODE) == TIM_ENCODERMODE_TI2) || \
AnnaBridge 163:e59c8e839560 1572 ((MODE) == TIM_ENCODERMODE_TI12))
AnnaBridge 163:e59c8e839560 1573
AnnaBridge 163:e59c8e839560 1574 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 163:e59c8e839560 1575
AnnaBridge 163:e59c8e839560 1576 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
AnnaBridge 163:e59c8e839560 1577 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
AnnaBridge 163:e59c8e839560 1578 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
AnnaBridge 163:e59c8e839560 1579 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
AnnaBridge 163:e59c8e839560 1580 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
AnnaBridge 163:e59c8e839560 1581 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
AnnaBridge 163:e59c8e839560 1582 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
AnnaBridge 163:e59c8e839560 1583 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
AnnaBridge 163:e59c8e839560 1584 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
AnnaBridge 163:e59c8e839560 1585 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge 163:e59c8e839560 1586
AnnaBridge 163:e59c8e839560 1587 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
AnnaBridge 163:e59c8e839560 1588 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
AnnaBridge 163:e59c8e839560 1589 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
AnnaBridge 163:e59c8e839560 1590 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
AnnaBridge 163:e59c8e839560 1591 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge 163:e59c8e839560 1592
AnnaBridge 163:e59c8e839560 1593 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
AnnaBridge 163:e59c8e839560 1594 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
AnnaBridge 163:e59c8e839560 1595 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
AnnaBridge 163:e59c8e839560 1596 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge 163:e59c8e839560 1597
AnnaBridge 163:e59c8e839560 1598 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
AnnaBridge 163:e59c8e839560 1599
AnnaBridge 163:e59c8e839560 1600 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
AnnaBridge 163:e59c8e839560 1601 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
AnnaBridge 163:e59c8e839560 1602
AnnaBridge 163:e59c8e839560 1603 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
AnnaBridge 163:e59c8e839560 1604 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge 163:e59c8e839560 1605
AnnaBridge 163:e59c8e839560 1606 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
AnnaBridge 163:e59c8e839560 1607 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
AnnaBridge 163:e59c8e839560 1608 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
AnnaBridge 163:e59c8e839560 1609 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge 163:e59c8e839560 1610
AnnaBridge 163:e59c8e839560 1611 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
AnnaBridge 163:e59c8e839560 1612
AnnaBridge 163:e59c8e839560 1613 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
AnnaBridge 163:e59c8e839560 1614 ((STATE) == TIM_OSSR_DISABLE))
AnnaBridge 163:e59c8e839560 1615
AnnaBridge 163:e59c8e839560 1616 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
AnnaBridge 163:e59c8e839560 1617 ((STATE) == TIM_OSSI_DISABLE))
AnnaBridge 163:e59c8e839560 1618
AnnaBridge 163:e59c8e839560 1619 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
AnnaBridge 163:e59c8e839560 1620 ((LEVEL) == TIM_LOCKLEVEL_1) || \
AnnaBridge 163:e59c8e839560 1621 ((LEVEL) == TIM_LOCKLEVEL_2) || \
AnnaBridge 163:e59c8e839560 1622 ((LEVEL) == TIM_LOCKLEVEL_3))
AnnaBridge 163:e59c8e839560 1623
AnnaBridge 163:e59c8e839560 1624 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
AnnaBridge 163:e59c8e839560 1625 ((STATE) == TIM_BREAK_DISABLE))
AnnaBridge 163:e59c8e839560 1626
AnnaBridge 163:e59c8e839560 1627 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
AnnaBridge 163:e59c8e839560 1628 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
AnnaBridge 163:e59c8e839560 1629
AnnaBridge 163:e59c8e839560 1630 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
AnnaBridge 163:e59c8e839560 1631 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
AnnaBridge 163:e59c8e839560 1632
AnnaBridge 163:e59c8e839560 1633 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
AnnaBridge 163:e59c8e839560 1634 ((SOURCE) == TIM_TRGO_ENABLE) || \
AnnaBridge 163:e59c8e839560 1635 ((SOURCE) == TIM_TRGO_UPDATE) || \
AnnaBridge 163:e59c8e839560 1636 ((SOURCE) == TIM_TRGO_OC1) || \
AnnaBridge 163:e59c8e839560 1637 ((SOURCE) == TIM_TRGO_OC1REF) || \
AnnaBridge 163:e59c8e839560 1638 ((SOURCE) == TIM_TRGO_OC2REF) || \
AnnaBridge 163:e59c8e839560 1639 ((SOURCE) == TIM_TRGO_OC3REF) || \
AnnaBridge 163:e59c8e839560 1640 ((SOURCE) == TIM_TRGO_OC4REF))
AnnaBridge 163:e59c8e839560 1641
AnnaBridge 163:e59c8e839560 1642 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
AnnaBridge 163:e59c8e839560 1643 ((MODE) == TIM_SLAVEMODE_GATED) || \
AnnaBridge 163:e59c8e839560 1644 ((MODE) == TIM_SLAVEMODE_RESET) || \
AnnaBridge 163:e59c8e839560 1645 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 163:e59c8e839560 1646 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
AnnaBridge 163:e59c8e839560 1647
AnnaBridge 163:e59c8e839560 1648 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
AnnaBridge 163:e59c8e839560 1649 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge 163:e59c8e839560 1650
AnnaBridge 163:e59c8e839560 1651 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
AnnaBridge 163:e59c8e839560 1652 ((SELECTION) == TIM_TS_ITR1) || \
AnnaBridge 163:e59c8e839560 1653 ((SELECTION) == TIM_TS_ITR2) || \
AnnaBridge 163:e59c8e839560 1654 ((SELECTION) == TIM_TS_ITR3) || \
AnnaBridge 163:e59c8e839560 1655 ((SELECTION) == TIM_TS_TI1F_ED) || \
AnnaBridge 163:e59c8e839560 1656 ((SELECTION) == TIM_TS_TI1FP1) || \
AnnaBridge 163:e59c8e839560 1657 ((SELECTION) == TIM_TS_TI2FP2) || \
AnnaBridge 163:e59c8e839560 1658 ((SELECTION) == TIM_TS_ETRF))
AnnaBridge 163:e59c8e839560 1659
AnnaBridge 163:e59c8e839560 1660 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
AnnaBridge 163:e59c8e839560 1661 ((SELECTION) == TIM_TS_ITR1) || \
AnnaBridge 163:e59c8e839560 1662 ((SELECTION) == TIM_TS_ITR2) || \
AnnaBridge 163:e59c8e839560 1663 ((SELECTION) == TIM_TS_ITR3) || \
AnnaBridge 163:e59c8e839560 1664 ((SELECTION) == TIM_TS_NONE))
AnnaBridge 163:e59c8e839560 1665
AnnaBridge 163:e59c8e839560 1666 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
AnnaBridge 163:e59c8e839560 1667 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
AnnaBridge 163:e59c8e839560 1668 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
AnnaBridge 163:e59c8e839560 1669 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
AnnaBridge 163:e59c8e839560 1670 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge 163:e59c8e839560 1671
AnnaBridge 163:e59c8e839560 1672 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
AnnaBridge 163:e59c8e839560 1673 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
AnnaBridge 163:e59c8e839560 1674 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
AnnaBridge 163:e59c8e839560 1675 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge 163:e59c8e839560 1676
AnnaBridge 163:e59c8e839560 1677 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
AnnaBridge 163:e59c8e839560 1678
AnnaBridge 163:e59c8e839560 1679 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
AnnaBridge 163:e59c8e839560 1680 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge 163:e59c8e839560 1681
AnnaBridge 163:e59c8e839560 1682 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
AnnaBridge 163:e59c8e839560 1683 ((BASE) == TIM_DMABASE_CR2) || \
AnnaBridge 163:e59c8e839560 1684 ((BASE) == TIM_DMABASE_SMCR) || \
AnnaBridge 163:e59c8e839560 1685 ((BASE) == TIM_DMABASE_DIER) || \
AnnaBridge 163:e59c8e839560 1686 ((BASE) == TIM_DMABASE_SR) || \
AnnaBridge 163:e59c8e839560 1687 ((BASE) == TIM_DMABASE_EGR) || \
AnnaBridge 163:e59c8e839560 1688 ((BASE) == TIM_DMABASE_CCMR1) || \
AnnaBridge 163:e59c8e839560 1689 ((BASE) == TIM_DMABASE_CCMR2) || \
AnnaBridge 163:e59c8e839560 1690 ((BASE) == TIM_DMABASE_CCER) || \
AnnaBridge 163:e59c8e839560 1691 ((BASE) == TIM_DMABASE_CNT) || \
AnnaBridge 163:e59c8e839560 1692 ((BASE) == TIM_DMABASE_PSC) || \
AnnaBridge 163:e59c8e839560 1693 ((BASE) == TIM_DMABASE_ARR) || \
AnnaBridge 163:e59c8e839560 1694 ((BASE) == TIM_DMABASE_RCR) || \
AnnaBridge 163:e59c8e839560 1695 ((BASE) == TIM_DMABASE_CCR1) || \
AnnaBridge 163:e59c8e839560 1696 ((BASE) == TIM_DMABASE_CCR2) || \
AnnaBridge 163:e59c8e839560 1697 ((BASE) == TIM_DMABASE_CCR3) || \
AnnaBridge 163:e59c8e839560 1698 ((BASE) == TIM_DMABASE_CCR4) || \
AnnaBridge 163:e59c8e839560 1699 ((BASE) == TIM_DMABASE_BDTR) || \
AnnaBridge 163:e59c8e839560 1700 ((BASE) == TIM_DMABASE_DCR) || \
AnnaBridge 163:e59c8e839560 1701 ((BASE) == TIM_DMABASE_OR))
AnnaBridge 163:e59c8e839560 1702
AnnaBridge 163:e59c8e839560 1703 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
AnnaBridge 163:e59c8e839560 1704 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1705 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1706 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1707 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1708 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1709 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1710 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1711 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1712 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1713 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1714 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1715 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1716 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1717 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1718 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1719 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
AnnaBridge 163:e59c8e839560 1720 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
AnnaBridge 163:e59c8e839560 1721
AnnaBridge 163:e59c8e839560 1722 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
AnnaBridge 163:e59c8e839560 1723 /**
AnnaBridge 163:e59c8e839560 1724 * @}
AnnaBridge 163:e59c8e839560 1725 */
AnnaBridge 163:e59c8e839560 1726
AnnaBridge 163:e59c8e839560 1727 /** @defgroup TIM_Mask_Definitions TIM Mask Definition
AnnaBridge 163:e59c8e839560 1728 * @{
AnnaBridge 163:e59c8e839560 1729 */
AnnaBridge 163:e59c8e839560 1730 /* The counter of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge 163:e59c8e839560 1731 channels have been disabled */
AnnaBridge 163:e59c8e839560 1732 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
AnnaBridge 163:e59c8e839560 1733 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
AnnaBridge 163:e59c8e839560 1734 /**
AnnaBridge 163:e59c8e839560 1735 * @}
AnnaBridge 163:e59c8e839560 1736 */
AnnaBridge 163:e59c8e839560 1737
AnnaBridge 163:e59c8e839560 1738 /**
AnnaBridge 163:e59c8e839560 1739 * @}
AnnaBridge 163:e59c8e839560 1740 */
AnnaBridge 163:e59c8e839560 1741
AnnaBridge 163:e59c8e839560 1742 /* Private functions ---------------------------------------------------------*/
AnnaBridge 163:e59c8e839560 1743 /** @defgroup TIM_Private_Functions TIM Private Functions
AnnaBridge 163:e59c8e839560 1744 * @{
AnnaBridge 163:e59c8e839560 1745 */
AnnaBridge 163:e59c8e839560 1746 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
AnnaBridge 163:e59c8e839560 1747 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
AnnaBridge 163:e59c8e839560 1748 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
AnnaBridge 163:e59c8e839560 1749 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 163:e59c8e839560 1750 void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge 163:e59c8e839560 1751 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 163:e59c8e839560 1752 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
AnnaBridge 163:e59c8e839560 1753 /**
AnnaBridge 163:e59c8e839560 1754 * @}
AnnaBridge 163:e59c8e839560 1755 */
AnnaBridge 163:e59c8e839560 1756
AnnaBridge 163:e59c8e839560 1757 /**
AnnaBridge 163:e59c8e839560 1758 * @}
AnnaBridge 163:e59c8e839560 1759 */
AnnaBridge 163:e59c8e839560 1760
AnnaBridge 163:e59c8e839560 1761 /**
AnnaBridge 163:e59c8e839560 1762 * @}
AnnaBridge 163:e59c8e839560 1763 */
AnnaBridge 163:e59c8e839560 1764
AnnaBridge 163:e59c8e839560 1765 #ifdef __cplusplus
AnnaBridge 163:e59c8e839560 1766 }
AnnaBridge 163:e59c8e839560 1767 #endif
AnnaBridge 163:e59c8e839560 1768
AnnaBridge 163:e59c8e839560 1769 #endif /* __STM32F4xx_HAL_TIM_H */
AnnaBridge 163:e59c8e839560 1770
AnnaBridge 163:e59c8e839560 1771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/