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TARGET_SAKURAIO_EVB_01/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 169:a7c7b631e539 1 /**
Anna Bridge 169:a7c7b631e539 2 ******************************************************************************
Anna Bridge 169:a7c7b631e539 3 * @file stm32f4xx_hal_rcc.h
Anna Bridge 169:a7c7b631e539 4 * @author MCD Application Team
Anna Bridge 169:a7c7b631e539 5 * @brief Header file of RCC HAL module.
Anna Bridge 169:a7c7b631e539 6 ******************************************************************************
Anna Bridge 169:a7c7b631e539 7 * @attention
Anna Bridge 169:a7c7b631e539 8 *
Anna Bridge 169:a7c7b631e539 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Anna Bridge 169:a7c7b631e539 10 *
Anna Bridge 169:a7c7b631e539 11 * Redistribution and use in source and binary forms, with or without modification,
Anna Bridge 169:a7c7b631e539 12 * are permitted provided that the following conditions are met:
Anna Bridge 169:a7c7b631e539 13 * 1. Redistributions of source code must retain the above copyright notice,
Anna Bridge 169:a7c7b631e539 14 * this list of conditions and the following disclaimer.
Anna Bridge 169:a7c7b631e539 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
Anna Bridge 169:a7c7b631e539 16 * this list of conditions and the following disclaimer in the documentation
Anna Bridge 169:a7c7b631e539 17 * and/or other materials provided with the distribution.
Anna Bridge 169:a7c7b631e539 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Anna Bridge 169:a7c7b631e539 19 * may be used to endorse or promote products derived from this software
Anna Bridge 169:a7c7b631e539 20 * without specific prior written permission.
Anna Bridge 169:a7c7b631e539 21 *
Anna Bridge 169:a7c7b631e539 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Anna Bridge 169:a7c7b631e539 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Anna Bridge 169:a7c7b631e539 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Anna Bridge 169:a7c7b631e539 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Anna Bridge 169:a7c7b631e539 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Anna Bridge 169:a7c7b631e539 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Anna Bridge 169:a7c7b631e539 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Anna Bridge 169:a7c7b631e539 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Anna Bridge 169:a7c7b631e539 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Anna Bridge 169:a7c7b631e539 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Anna Bridge 169:a7c7b631e539 32 *
Anna Bridge 169:a7c7b631e539 33 ******************************************************************************
Anna Bridge 169:a7c7b631e539 34 */
Anna Bridge 169:a7c7b631e539 35
Anna Bridge 169:a7c7b631e539 36 /* Define to prevent recursive inclusion -------------------------------------*/
Anna Bridge 169:a7c7b631e539 37 #ifndef __STM32F4xx_HAL_RCC_H
Anna Bridge 169:a7c7b631e539 38 #define __STM32F4xx_HAL_RCC_H
Anna Bridge 169:a7c7b631e539 39
Anna Bridge 169:a7c7b631e539 40 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 41 extern "C" {
Anna Bridge 169:a7c7b631e539 42 #endif
Anna Bridge 169:a7c7b631e539 43
Anna Bridge 169:a7c7b631e539 44 /* Includes ------------------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 45 #include "stm32f4xx_hal_def.h"
Anna Bridge 169:a7c7b631e539 46
Anna Bridge 169:a7c7b631e539 47 /* Include RCC HAL Extended module */
Anna Bridge 169:a7c7b631e539 48 /* (include on top of file since RCC structures are defined in extended file) */
Anna Bridge 169:a7c7b631e539 49 #include "stm32f4xx_hal_rcc_ex.h"
Anna Bridge 169:a7c7b631e539 50
Anna Bridge 169:a7c7b631e539 51 /** @addtogroup STM32F4xx_HAL_Driver
Anna Bridge 169:a7c7b631e539 52 * @{
Anna Bridge 169:a7c7b631e539 53 */
Anna Bridge 169:a7c7b631e539 54
Anna Bridge 169:a7c7b631e539 55 /** @addtogroup RCC
Anna Bridge 169:a7c7b631e539 56 * @{
Anna Bridge 169:a7c7b631e539 57 */
Anna Bridge 169:a7c7b631e539 58
Anna Bridge 169:a7c7b631e539 59 /* Exported types ------------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 60 /** @defgroup RCC_Exported_Types RCC Exported Types
Anna Bridge 169:a7c7b631e539 61 * @{
Anna Bridge 169:a7c7b631e539 62 */
Anna Bridge 169:a7c7b631e539 63
Anna Bridge 169:a7c7b631e539 64 /**
Anna Bridge 169:a7c7b631e539 65 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Anna Bridge 169:a7c7b631e539 66 */
Anna Bridge 169:a7c7b631e539 67 typedef struct
Anna Bridge 169:a7c7b631e539 68 {
Anna Bridge 169:a7c7b631e539 69 uint32_t OscillatorType; /*!< The oscillators to be configured.
Anna Bridge 169:a7c7b631e539 70 This parameter can be a value of @ref RCC_Oscillator_Type */
Anna Bridge 169:a7c7b631e539 71
Anna Bridge 169:a7c7b631e539 72 uint32_t HSEState; /*!< The new state of the HSE.
Anna Bridge 169:a7c7b631e539 73 This parameter can be a value of @ref RCC_HSE_Config */
Anna Bridge 169:a7c7b631e539 74
Anna Bridge 169:a7c7b631e539 75 uint32_t LSEState; /*!< The new state of the LSE.
Anna Bridge 169:a7c7b631e539 76 This parameter can be a value of @ref RCC_LSE_Config */
Anna Bridge 169:a7c7b631e539 77
Anna Bridge 169:a7c7b631e539 78 uint32_t HSIState; /*!< The new state of the HSI.
Anna Bridge 169:a7c7b631e539 79 This parameter can be a value of @ref RCC_HSI_Config */
Anna Bridge 169:a7c7b631e539 80
Anna Bridge 169:a7c7b631e539 81 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Anna Bridge 169:a7c7b631e539 82 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Anna Bridge 169:a7c7b631e539 83
Anna Bridge 169:a7c7b631e539 84 uint32_t LSIState; /*!< The new state of the LSI.
Anna Bridge 169:a7c7b631e539 85 This parameter can be a value of @ref RCC_LSI_Config */
Anna Bridge 169:a7c7b631e539 86
Anna Bridge 169:a7c7b631e539 87 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Anna Bridge 169:a7c7b631e539 88 }RCC_OscInitTypeDef;
Anna Bridge 169:a7c7b631e539 89
Anna Bridge 169:a7c7b631e539 90 /**
Anna Bridge 169:a7c7b631e539 91 * @brief RCC System, AHB and APB busses clock configuration structure definition
Anna Bridge 169:a7c7b631e539 92 */
Anna Bridge 169:a7c7b631e539 93 typedef struct
Anna Bridge 169:a7c7b631e539 94 {
Anna Bridge 169:a7c7b631e539 95 uint32_t ClockType; /*!< The clock to be configured.
Anna Bridge 169:a7c7b631e539 96 This parameter can be a value of @ref RCC_System_Clock_Type */
Anna Bridge 169:a7c7b631e539 97
Anna Bridge 169:a7c7b631e539 98 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Anna Bridge 169:a7c7b631e539 99 This parameter can be a value of @ref RCC_System_Clock_Source */
Anna Bridge 169:a7c7b631e539 100
Anna Bridge 169:a7c7b631e539 101 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Anna Bridge 169:a7c7b631e539 102 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Anna Bridge 169:a7c7b631e539 103
Anna Bridge 169:a7c7b631e539 104 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Anna Bridge 169:a7c7b631e539 105 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Anna Bridge 169:a7c7b631e539 106
Anna Bridge 169:a7c7b631e539 107 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Anna Bridge 169:a7c7b631e539 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Anna Bridge 169:a7c7b631e539 109
Anna Bridge 169:a7c7b631e539 110 }RCC_ClkInitTypeDef;
Anna Bridge 169:a7c7b631e539 111
Anna Bridge 169:a7c7b631e539 112 /**
Anna Bridge 169:a7c7b631e539 113 * @}
Anna Bridge 169:a7c7b631e539 114 */
Anna Bridge 169:a7c7b631e539 115
Anna Bridge 169:a7c7b631e539 116 /* Exported constants --------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 117 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Anna Bridge 169:a7c7b631e539 118 * @{
Anna Bridge 169:a7c7b631e539 119 */
Anna Bridge 169:a7c7b631e539 120
Anna Bridge 169:a7c7b631e539 121 /** @defgroup RCC_Oscillator_Type Oscillator Type
Anna Bridge 169:a7c7b631e539 122 * @{
Anna Bridge 169:a7c7b631e539 123 */
Anna Bridge 169:a7c7b631e539 124 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
Anna Bridge 169:a7c7b631e539 125 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
Anna Bridge 169:a7c7b631e539 126 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
Anna Bridge 169:a7c7b631e539 127 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
Anna Bridge 169:a7c7b631e539 128 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
Anna Bridge 169:a7c7b631e539 129 /**
Anna Bridge 169:a7c7b631e539 130 * @}
Anna Bridge 169:a7c7b631e539 131 */
Anna Bridge 169:a7c7b631e539 132
Anna Bridge 169:a7c7b631e539 133 /** @defgroup RCC_HSE_Config HSE Config
Anna Bridge 169:a7c7b631e539 134 * @{
Anna Bridge 169:a7c7b631e539 135 */
Anna Bridge 169:a7c7b631e539 136 #define RCC_HSE_OFF 0x00000000U
Anna Bridge 169:a7c7b631e539 137 #define RCC_HSE_ON RCC_CR_HSEON
Anna Bridge 169:a7c7b631e539 138 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
Anna Bridge 169:a7c7b631e539 139 /**
Anna Bridge 169:a7c7b631e539 140 * @}
Anna Bridge 169:a7c7b631e539 141 */
Anna Bridge 169:a7c7b631e539 142
Anna Bridge 169:a7c7b631e539 143 /** @defgroup RCC_LSE_Config LSE Config
Anna Bridge 169:a7c7b631e539 144 * @{
Anna Bridge 169:a7c7b631e539 145 */
Anna Bridge 169:a7c7b631e539 146 #define RCC_LSE_OFF 0x00000000U
Anna Bridge 169:a7c7b631e539 147 #define RCC_LSE_ON RCC_BDCR_LSEON
Anna Bridge 169:a7c7b631e539 148 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
Anna Bridge 169:a7c7b631e539 149 /**
Anna Bridge 169:a7c7b631e539 150 * @}
Anna Bridge 169:a7c7b631e539 151 */
Anna Bridge 169:a7c7b631e539 152
Anna Bridge 169:a7c7b631e539 153 /** @defgroup RCC_HSI_Config HSI Config
Anna Bridge 169:a7c7b631e539 154 * @{
Anna Bridge 169:a7c7b631e539 155 */
Anna Bridge 169:a7c7b631e539 156 #define RCC_HSI_OFF ((uint8_t)0x00)
Anna Bridge 169:a7c7b631e539 157 #define RCC_HSI_ON ((uint8_t)0x01)
Anna Bridge 169:a7c7b631e539 158
Anna Bridge 169:a7c7b631e539 159 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
Anna Bridge 169:a7c7b631e539 160 /**
Anna Bridge 169:a7c7b631e539 161 * @}
Anna Bridge 169:a7c7b631e539 162 */
Anna Bridge 169:a7c7b631e539 163
Anna Bridge 169:a7c7b631e539 164 /** @defgroup RCC_LSI_Config LSI Config
Anna Bridge 169:a7c7b631e539 165 * @{
Anna Bridge 169:a7c7b631e539 166 */
Anna Bridge 169:a7c7b631e539 167 #define RCC_LSI_OFF ((uint8_t)0x00)
Anna Bridge 169:a7c7b631e539 168 #define RCC_LSI_ON ((uint8_t)0x01)
Anna Bridge 169:a7c7b631e539 169 /**
Anna Bridge 169:a7c7b631e539 170 * @}
Anna Bridge 169:a7c7b631e539 171 */
Anna Bridge 169:a7c7b631e539 172
Anna Bridge 169:a7c7b631e539 173 /** @defgroup RCC_PLL_Config PLL Config
Anna Bridge 169:a7c7b631e539 174 * @{
Anna Bridge 169:a7c7b631e539 175 */
Anna Bridge 169:a7c7b631e539 176 #define RCC_PLL_NONE ((uint8_t)0x00)
Anna Bridge 169:a7c7b631e539 177 #define RCC_PLL_OFF ((uint8_t)0x01)
Anna Bridge 169:a7c7b631e539 178 #define RCC_PLL_ON ((uint8_t)0x02)
Anna Bridge 169:a7c7b631e539 179 /**
Anna Bridge 169:a7c7b631e539 180 * @}
Anna Bridge 169:a7c7b631e539 181 */
Anna Bridge 169:a7c7b631e539 182
Anna Bridge 169:a7c7b631e539 183 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Anna Bridge 169:a7c7b631e539 184 * @{
Anna Bridge 169:a7c7b631e539 185 */
Anna Bridge 169:a7c7b631e539 186 #define RCC_PLLP_DIV2 0x00000002U
Anna Bridge 169:a7c7b631e539 187 #define RCC_PLLP_DIV4 0x00000004U
Anna Bridge 169:a7c7b631e539 188 #define RCC_PLLP_DIV6 0x00000006U
Anna Bridge 169:a7c7b631e539 189 #define RCC_PLLP_DIV8 0x00000008U
Anna Bridge 169:a7c7b631e539 190 /**
Anna Bridge 169:a7c7b631e539 191 * @}
Anna Bridge 169:a7c7b631e539 192 */
Anna Bridge 169:a7c7b631e539 193
Anna Bridge 169:a7c7b631e539 194 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Anna Bridge 169:a7c7b631e539 195 * @{
Anna Bridge 169:a7c7b631e539 196 */
Anna Bridge 169:a7c7b631e539 197 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Anna Bridge 169:a7c7b631e539 198 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Anna Bridge 169:a7c7b631e539 199 /**
Anna Bridge 169:a7c7b631e539 200 * @}
Anna Bridge 169:a7c7b631e539 201 */
Anna Bridge 169:a7c7b631e539 202
Anna Bridge 169:a7c7b631e539 203 /** @defgroup RCC_System_Clock_Type System Clock Type
Anna Bridge 169:a7c7b631e539 204 * @{
Anna Bridge 169:a7c7b631e539 205 */
Anna Bridge 169:a7c7b631e539 206 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
Anna Bridge 169:a7c7b631e539 207 #define RCC_CLOCKTYPE_HCLK 0x00000002U
Anna Bridge 169:a7c7b631e539 208 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
Anna Bridge 169:a7c7b631e539 209 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
Anna Bridge 169:a7c7b631e539 210 /**
Anna Bridge 169:a7c7b631e539 211 * @}
Anna Bridge 169:a7c7b631e539 212 */
Anna Bridge 169:a7c7b631e539 213
Anna Bridge 169:a7c7b631e539 214 /** @defgroup RCC_System_Clock_Source System Clock Source
Anna Bridge 169:a7c7b631e539 215 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
Anna Bridge 169:a7c7b631e539 216 * STM32F446xx devices.
Anna Bridge 169:a7c7b631e539 217 * @{
Anna Bridge 169:a7c7b631e539 218 */
Anna Bridge 169:a7c7b631e539 219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Anna Bridge 169:a7c7b631e539 220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Anna Bridge 169:a7c7b631e539 221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Anna Bridge 169:a7c7b631e539 222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
Anna Bridge 169:a7c7b631e539 223 /**
Anna Bridge 169:a7c7b631e539 224 * @}
Anna Bridge 169:a7c7b631e539 225 */
Anna Bridge 169:a7c7b631e539 226
Anna Bridge 169:a7c7b631e539 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Anna Bridge 169:a7c7b631e539 228 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
Anna Bridge 169:a7c7b631e539 229 * STM32F446xx devices.
Anna Bridge 169:a7c7b631e539 230 * @{
Anna Bridge 169:a7c7b631e539 231 */
Anna Bridge 169:a7c7b631e539 232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Anna Bridge 169:a7c7b631e539 233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Anna Bridge 169:a7c7b631e539 234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Anna Bridge 169:a7c7b631e539 235 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
Anna Bridge 169:a7c7b631e539 236 /**
Anna Bridge 169:a7c7b631e539 237 * @}
Anna Bridge 169:a7c7b631e539 238 */
Anna Bridge 169:a7c7b631e539 239
Anna Bridge 169:a7c7b631e539 240 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Anna Bridge 169:a7c7b631e539 241 * @{
Anna Bridge 169:a7c7b631e539 242 */
Anna Bridge 169:a7c7b631e539 243 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Anna Bridge 169:a7c7b631e539 244 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Anna Bridge 169:a7c7b631e539 245 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Anna Bridge 169:a7c7b631e539 246 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Anna Bridge 169:a7c7b631e539 247 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Anna Bridge 169:a7c7b631e539 248 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Anna Bridge 169:a7c7b631e539 249 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Anna Bridge 169:a7c7b631e539 250 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Anna Bridge 169:a7c7b631e539 251 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Anna Bridge 169:a7c7b631e539 252 /**
Anna Bridge 169:a7c7b631e539 253 * @}
Anna Bridge 169:a7c7b631e539 254 */
Anna Bridge 169:a7c7b631e539 255
Anna Bridge 169:a7c7b631e539 256 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
Anna Bridge 169:a7c7b631e539 257 * @{
Anna Bridge 169:a7c7b631e539 258 */
Anna Bridge 169:a7c7b631e539 259 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Anna Bridge 169:a7c7b631e539 260 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Anna Bridge 169:a7c7b631e539 261 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Anna Bridge 169:a7c7b631e539 262 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Anna Bridge 169:a7c7b631e539 263 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Anna Bridge 169:a7c7b631e539 264 /**
Anna Bridge 169:a7c7b631e539 265 * @}
Anna Bridge 169:a7c7b631e539 266 */
Anna Bridge 169:a7c7b631e539 267
Anna Bridge 169:a7c7b631e539 268 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Anna Bridge 169:a7c7b631e539 269 * @{
Anna Bridge 169:a7c7b631e539 270 */
Anna Bridge 169:a7c7b631e539 271 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
Anna Bridge 169:a7c7b631e539 272 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
Anna Bridge 169:a7c7b631e539 273 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
Anna Bridge 169:a7c7b631e539 274 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
Anna Bridge 169:a7c7b631e539 275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
Anna Bridge 169:a7c7b631e539 276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
Anna Bridge 169:a7c7b631e539 277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
Anna Bridge 169:a7c7b631e539 278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
Anna Bridge 169:a7c7b631e539 279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
Anna Bridge 169:a7c7b631e539 280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
Anna Bridge 169:a7c7b631e539 281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
Anna Bridge 169:a7c7b631e539 282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
Anna Bridge 169:a7c7b631e539 283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
Anna Bridge 169:a7c7b631e539 284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
Anna Bridge 169:a7c7b631e539 285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
Anna Bridge 169:a7c7b631e539 286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
Anna Bridge 169:a7c7b631e539 287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
Anna Bridge 169:a7c7b631e539 288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
Anna Bridge 169:a7c7b631e539 289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
Anna Bridge 169:a7c7b631e539 290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
Anna Bridge 169:a7c7b631e539 291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
Anna Bridge 169:a7c7b631e539 292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
Anna Bridge 169:a7c7b631e539 293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
Anna Bridge 169:a7c7b631e539 294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
Anna Bridge 169:a7c7b631e539 295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
Anna Bridge 169:a7c7b631e539 296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
Anna Bridge 169:a7c7b631e539 297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
Anna Bridge 169:a7c7b631e539 298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
Anna Bridge 169:a7c7b631e539 299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
Anna Bridge 169:a7c7b631e539 300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
Anna Bridge 169:a7c7b631e539 301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
Anna Bridge 169:a7c7b631e539 302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
Anna Bridge 169:a7c7b631e539 303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
Anna Bridge 169:a7c7b631e539 304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
Anna Bridge 169:a7c7b631e539 305 /**
Anna Bridge 169:a7c7b631e539 306 * @}
Anna Bridge 169:a7c7b631e539 307 */
Anna Bridge 169:a7c7b631e539 308
Anna Bridge 169:a7c7b631e539 309 /** @defgroup RCC_MCO_Index MCO Index
Anna Bridge 169:a7c7b631e539 310 * @{
Anna Bridge 169:a7c7b631e539 311 */
Anna Bridge 169:a7c7b631e539 312 #define RCC_MCO1 0x00000000U
Anna Bridge 169:a7c7b631e539 313 #define RCC_MCO2 0x00000001U
Anna Bridge 169:a7c7b631e539 314 /**
Anna Bridge 169:a7c7b631e539 315 * @}
Anna Bridge 169:a7c7b631e539 316 */
Anna Bridge 169:a7c7b631e539 317
Anna Bridge 169:a7c7b631e539 318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Anna Bridge 169:a7c7b631e539 319 * @{
Anna Bridge 169:a7c7b631e539 320 */
Anna Bridge 169:a7c7b631e539 321 #define RCC_MCO1SOURCE_HSI 0x00000000U
Anna Bridge 169:a7c7b631e539 322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Anna Bridge 169:a7c7b631e539 323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Anna Bridge 169:a7c7b631e539 324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Anna Bridge 169:a7c7b631e539 325 /**
Anna Bridge 169:a7c7b631e539 326 * @}
Anna Bridge 169:a7c7b631e539 327 */
Anna Bridge 169:a7c7b631e539 328
Anna Bridge 169:a7c7b631e539 329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
Anna Bridge 169:a7c7b631e539 330 * @{
Anna Bridge 169:a7c7b631e539 331 */
Anna Bridge 169:a7c7b631e539 332 #define RCC_MCODIV_1 0x00000000U
Anna Bridge 169:a7c7b631e539 333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Anna Bridge 169:a7c7b631e539 334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
Anna Bridge 169:a7c7b631e539 335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
Anna Bridge 169:a7c7b631e539 336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Anna Bridge 169:a7c7b631e539 337 /**
Anna Bridge 169:a7c7b631e539 338 * @}
Anna Bridge 169:a7c7b631e539 339 */
Anna Bridge 169:a7c7b631e539 340
Anna Bridge 169:a7c7b631e539 341 /** @defgroup RCC_Interrupt Interrupts
Anna Bridge 169:a7c7b631e539 342 * @{
Anna Bridge 169:a7c7b631e539 343 */
Anna Bridge 169:a7c7b631e539 344 #define RCC_IT_LSIRDY ((uint8_t)0x01)
Anna Bridge 169:a7c7b631e539 345 #define RCC_IT_LSERDY ((uint8_t)0x02)
Anna Bridge 169:a7c7b631e539 346 #define RCC_IT_HSIRDY ((uint8_t)0x04)
Anna Bridge 169:a7c7b631e539 347 #define RCC_IT_HSERDY ((uint8_t)0x08)
Anna Bridge 169:a7c7b631e539 348 #define RCC_IT_PLLRDY ((uint8_t)0x10)
Anna Bridge 169:a7c7b631e539 349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Anna Bridge 169:a7c7b631e539 350 #define RCC_IT_CSS ((uint8_t)0x80)
Anna Bridge 169:a7c7b631e539 351 /**
Anna Bridge 169:a7c7b631e539 352 * @}
Anna Bridge 169:a7c7b631e539 353 */
Anna Bridge 169:a7c7b631e539 354
Anna Bridge 169:a7c7b631e539 355 /** @defgroup RCC_Flag Flags
Anna Bridge 169:a7c7b631e539 356 * Elements values convention: 0XXYYYYYb
Anna Bridge 169:a7c7b631e539 357 * - YYYYY : Flag position in the register
Anna Bridge 169:a7c7b631e539 358 * - 0XX : Register index
Anna Bridge 169:a7c7b631e539 359 * - 01: CR register
Anna Bridge 169:a7c7b631e539 360 * - 10: BDCR register
Anna Bridge 169:a7c7b631e539 361 * - 11: CSR register
Anna Bridge 169:a7c7b631e539 362 * @{
Anna Bridge 169:a7c7b631e539 363 */
Anna Bridge 169:a7c7b631e539 364 /* Flags in the CR register */
Anna Bridge 169:a7c7b631e539 365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Anna Bridge 169:a7c7b631e539 366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
Anna Bridge 169:a7c7b631e539 367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Anna Bridge 169:a7c7b631e539 368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Anna Bridge 169:a7c7b631e539 369
Anna Bridge 169:a7c7b631e539 370 /* Flags in the BDCR register */
Anna Bridge 169:a7c7b631e539 371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
Anna Bridge 169:a7c7b631e539 372
Anna Bridge 169:a7c7b631e539 373 /* Flags in the CSR register */
Anna Bridge 169:a7c7b631e539 374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Anna Bridge 169:a7c7b631e539 375 #define RCC_FLAG_BORRST ((uint8_t)0x79)
Anna Bridge 169:a7c7b631e539 376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
Anna Bridge 169:a7c7b631e539 377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
Anna Bridge 169:a7c7b631e539 378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Anna Bridge 169:a7c7b631e539 379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Anna Bridge 169:a7c7b631e539 380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Anna Bridge 169:a7c7b631e539 381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Anna Bridge 169:a7c7b631e539 382 /**
Anna Bridge 169:a7c7b631e539 383 * @}
Anna Bridge 169:a7c7b631e539 384 */
Anna Bridge 169:a7c7b631e539 385
Anna Bridge 169:a7c7b631e539 386 /**
Anna Bridge 169:a7c7b631e539 387 * @}
Anna Bridge 169:a7c7b631e539 388 */
Anna Bridge 169:a7c7b631e539 389
Anna Bridge 169:a7c7b631e539 390 /* Exported macro ------------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 391 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Anna Bridge 169:a7c7b631e539 392 * @{
Anna Bridge 169:a7c7b631e539 393 */
Anna Bridge 169:a7c7b631e539 394
Anna Bridge 169:a7c7b631e539 395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Anna Bridge 169:a7c7b631e539 396 * @brief Enable or disable the AHB1 peripheral clock.
Anna Bridge 169:a7c7b631e539 397 * @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge 169:a7c7b631e539 398 * is disabled and the application software has to enable this clock before
Anna Bridge 169:a7c7b631e539 399 * using it.
Anna Bridge 169:a7c7b631e539 400 * @{
Anna Bridge 169:a7c7b631e539 401 */
Anna Bridge 169:a7c7b631e539 402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 403 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Anna Bridge 169:a7c7b631e539 405 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Anna Bridge 169:a7c7b631e539 407 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 408 } while(0U)
Anna Bridge 169:a7c7b631e539 409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 410 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Anna Bridge 169:a7c7b631e539 412 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Anna Bridge 169:a7c7b631e539 414 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 415 } while(0U)
Anna Bridge 169:a7c7b631e539 416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 417 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Anna Bridge 169:a7c7b631e539 419 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Anna Bridge 169:a7c7b631e539 421 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 422 } while(0U)
Anna Bridge 169:a7c7b631e539 423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 424 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Anna Bridge 169:a7c7b631e539 426 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Anna Bridge 169:a7c7b631e539 428 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 429 } while(0U)
Anna Bridge 169:a7c7b631e539 430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 431 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Anna Bridge 169:a7c7b631e539 433 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Anna Bridge 169:a7c7b631e539 435 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 436 } while(0U)
Anna Bridge 169:a7c7b631e539 437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 438 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Anna Bridge 169:a7c7b631e539 440 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Anna Bridge 169:a7c7b631e539 442 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 443 } while(0U)
Anna Bridge 169:a7c7b631e539 444
Anna Bridge 169:a7c7b631e539 445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Anna Bridge 169:a7c7b631e539 446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Anna Bridge 169:a7c7b631e539 447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Anna Bridge 169:a7c7b631e539 448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Anna Bridge 169:a7c7b631e539 449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Anna Bridge 169:a7c7b631e539 450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Anna Bridge 169:a7c7b631e539 451 /**
Anna Bridge 169:a7c7b631e539 452 * @}
Anna Bridge 169:a7c7b631e539 453 */
Anna Bridge 169:a7c7b631e539 454
Anna Bridge 169:a7c7b631e539 455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Anna Bridge 169:a7c7b631e539 456 * @brief Get the enable or disable status of the AHB1 peripheral clock.
Anna Bridge 169:a7c7b631e539 457 * @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge 169:a7c7b631e539 458 * is disabled and the application software has to enable this clock before
Anna Bridge 169:a7c7b631e539 459 * using it.
Anna Bridge 169:a7c7b631e539 460 * @{
Anna Bridge 169:a7c7b631e539 461 */
Anna Bridge 169:a7c7b631e539 462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
Anna Bridge 169:a7c7b631e539 463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
Anna Bridge 169:a7c7b631e539 464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
Anna Bridge 169:a7c7b631e539 465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
Anna Bridge 169:a7c7b631e539 466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
Anna Bridge 169:a7c7b631e539 467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
Anna Bridge 169:a7c7b631e539 468
Anna Bridge 169:a7c7b631e539 469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
Anna Bridge 169:a7c7b631e539 470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
Anna Bridge 169:a7c7b631e539 471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
Anna Bridge 169:a7c7b631e539 472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
Anna Bridge 169:a7c7b631e539 473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
Anna Bridge 169:a7c7b631e539 474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
Anna Bridge 169:a7c7b631e539 475 /**
Anna Bridge 169:a7c7b631e539 476 * @}
Anna Bridge 169:a7c7b631e539 477 */
Anna Bridge 169:a7c7b631e539 478
Anna Bridge 169:a7c7b631e539 479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Anna Bridge 169:a7c7b631e539 480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Anna Bridge 169:a7c7b631e539 481 * @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge 169:a7c7b631e539 482 * is disabled and the application software has to enable this clock before
Anna Bridge 169:a7c7b631e539 483 * using it.
Anna Bridge 169:a7c7b631e539 484 * @{
Anna Bridge 169:a7c7b631e539 485 */
Anna Bridge 169:a7c7b631e539 486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 487 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Anna Bridge 169:a7c7b631e539 489 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Anna Bridge 169:a7c7b631e539 491 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 492 } while(0U)
Anna Bridge 169:a7c7b631e539 493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 494 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Anna Bridge 169:a7c7b631e539 496 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Anna Bridge 169:a7c7b631e539 498 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 499 } while(0U)
Anna Bridge 169:a7c7b631e539 500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 501 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Anna Bridge 169:a7c7b631e539 503 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Anna Bridge 169:a7c7b631e539 505 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 506 } while(0U)
Anna Bridge 169:a7c7b631e539 507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 508 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 509 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Anna Bridge 169:a7c7b631e539 510 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 511 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Anna Bridge 169:a7c7b631e539 512 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 513 } while(0U)
Anna Bridge 169:a7c7b631e539 514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 515 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 516 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Anna Bridge 169:a7c7b631e539 517 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 518 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Anna Bridge 169:a7c7b631e539 519 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 520 } while(0U)
Anna Bridge 169:a7c7b631e539 521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 522 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 523 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Anna Bridge 169:a7c7b631e539 524 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 525 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Anna Bridge 169:a7c7b631e539 526 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 527 } while(0U)
Anna Bridge 169:a7c7b631e539 528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 529 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 530 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Anna Bridge 169:a7c7b631e539 531 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 532 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Anna Bridge 169:a7c7b631e539 533 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 534 } while(0U)
Anna Bridge 169:a7c7b631e539 535
Anna Bridge 169:a7c7b631e539 536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Anna Bridge 169:a7c7b631e539 537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Anna Bridge 169:a7c7b631e539 538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Anna Bridge 169:a7c7b631e539 539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Anna Bridge 169:a7c7b631e539 540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Anna Bridge 169:a7c7b631e539 541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Anna Bridge 169:a7c7b631e539 542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Anna Bridge 169:a7c7b631e539 543 /**
Anna Bridge 169:a7c7b631e539 544 * @}
Anna Bridge 169:a7c7b631e539 545 */
Anna Bridge 169:a7c7b631e539 546
Anna Bridge 169:a7c7b631e539 547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Anna Bridge 169:a7c7b631e539 548 * @brief Get the enable or disable status of the APB1 peripheral clock.
Anna Bridge 169:a7c7b631e539 549 * @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge 169:a7c7b631e539 550 * is disabled and the application software has to enable this clock before
Anna Bridge 169:a7c7b631e539 551 * using it.
Anna Bridge 169:a7c7b631e539 552 * @{
Anna Bridge 169:a7c7b631e539 553 */
Anna Bridge 169:a7c7b631e539 554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Anna Bridge 169:a7c7b631e539 555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Anna Bridge 169:a7c7b631e539 556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Anna Bridge 169:a7c7b631e539 557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Anna Bridge 169:a7c7b631e539 558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Anna Bridge 169:a7c7b631e539 559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Anna Bridge 169:a7c7b631e539 560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Anna Bridge 169:a7c7b631e539 561
Anna Bridge 169:a7c7b631e539 562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Anna Bridge 169:a7c7b631e539 563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Anna Bridge 169:a7c7b631e539 564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Anna Bridge 169:a7c7b631e539 565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Anna Bridge 169:a7c7b631e539 566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Anna Bridge 169:a7c7b631e539 567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Anna Bridge 169:a7c7b631e539 568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Anna Bridge 169:a7c7b631e539 569 /**
Anna Bridge 169:a7c7b631e539 570 * @}
Anna Bridge 169:a7c7b631e539 571 */
Anna Bridge 169:a7c7b631e539 572
Anna Bridge 169:a7c7b631e539 573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Anna Bridge 169:a7c7b631e539 574 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Anna Bridge 169:a7c7b631e539 575 * @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge 169:a7c7b631e539 576 * is disabled and the application software has to enable this clock before
Anna Bridge 169:a7c7b631e539 577 * using it.
Anna Bridge 169:a7c7b631e539 578 * @{
Anna Bridge 169:a7c7b631e539 579 */
Anna Bridge 169:a7c7b631e539 580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 581 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Anna Bridge 169:a7c7b631e539 583 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Anna Bridge 169:a7c7b631e539 585 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 586 } while(0U)
Anna Bridge 169:a7c7b631e539 587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 588 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 589 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Anna Bridge 169:a7c7b631e539 590 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 591 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Anna Bridge 169:a7c7b631e539 592 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 593 } while(0U)
Anna Bridge 169:a7c7b631e539 594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 595 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 596 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Anna Bridge 169:a7c7b631e539 597 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 598 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Anna Bridge 169:a7c7b631e539 599 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 600 } while(0U)
Anna Bridge 169:a7c7b631e539 601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 602 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 603 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Anna Bridge 169:a7c7b631e539 604 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 605 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Anna Bridge 169:a7c7b631e539 606 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 607 } while(0U)
Anna Bridge 169:a7c7b631e539 608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 609 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 610 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Anna Bridge 169:a7c7b631e539 611 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 612 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Anna Bridge 169:a7c7b631e539 613 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 614 } while(0U)
Anna Bridge 169:a7c7b631e539 615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 616 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 617 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Anna Bridge 169:a7c7b631e539 618 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 619 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Anna Bridge 169:a7c7b631e539 620 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 621 } while(0U)
Anna Bridge 169:a7c7b631e539 622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 623 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 624 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Anna Bridge 169:a7c7b631e539 625 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 626 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Anna Bridge 169:a7c7b631e539 627 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 628 } while(0U)
Anna Bridge 169:a7c7b631e539 629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Anna Bridge 169:a7c7b631e539 630 __IO uint32_t tmpreg = 0x00U; \
Anna Bridge 169:a7c7b631e539 631 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Anna Bridge 169:a7c7b631e539 632 /* Delay after an RCC peripheral clock enabling */ \
Anna Bridge 169:a7c7b631e539 633 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Anna Bridge 169:a7c7b631e539 634 UNUSED(tmpreg); \
Anna Bridge 169:a7c7b631e539 635 } while(0U)
Anna Bridge 169:a7c7b631e539 636
Anna Bridge 169:a7c7b631e539 637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Anna Bridge 169:a7c7b631e539 638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Anna Bridge 169:a7c7b631e539 639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Anna Bridge 169:a7c7b631e539 640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Anna Bridge 169:a7c7b631e539 641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Anna Bridge 169:a7c7b631e539 642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Anna Bridge 169:a7c7b631e539 643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Anna Bridge 169:a7c7b631e539 644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Anna Bridge 169:a7c7b631e539 645 /**
Anna Bridge 169:a7c7b631e539 646 * @}
Anna Bridge 169:a7c7b631e539 647 */
Anna Bridge 169:a7c7b631e539 648
Anna Bridge 169:a7c7b631e539 649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Anna Bridge 169:a7c7b631e539 650 * @brief Get the enable or disable status of the APB2 peripheral clock.
Anna Bridge 169:a7c7b631e539 651 * @note After reset, the peripheral clock (used for registers read/write access)
Anna Bridge 169:a7c7b631e539 652 * is disabled and the application software has to enable this clock before
Anna Bridge 169:a7c7b631e539 653 * using it.
Anna Bridge 169:a7c7b631e539 654 * @{
Anna Bridge 169:a7c7b631e539 655 */
Anna Bridge 169:a7c7b631e539 656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Anna Bridge 169:a7c7b631e539 657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Anna Bridge 169:a7c7b631e539 658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Anna Bridge 169:a7c7b631e539 659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Anna Bridge 169:a7c7b631e539 660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Anna Bridge 169:a7c7b631e539 661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Anna Bridge 169:a7c7b631e539 662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Anna Bridge 169:a7c7b631e539 663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Anna Bridge 169:a7c7b631e539 664
Anna Bridge 169:a7c7b631e539 665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Anna Bridge 169:a7c7b631e539 666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Anna Bridge 169:a7c7b631e539 667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Anna Bridge 169:a7c7b631e539 668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Anna Bridge 169:a7c7b631e539 669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Anna Bridge 169:a7c7b631e539 670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Anna Bridge 169:a7c7b631e539 671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Anna Bridge 169:a7c7b631e539 672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Anna Bridge 169:a7c7b631e539 673 /**
Anna Bridge 169:a7c7b631e539 674 * @}
Anna Bridge 169:a7c7b631e539 675 */
Anna Bridge 169:a7c7b631e539 676
Anna Bridge 169:a7c7b631e539 677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Anna Bridge 169:a7c7b631e539 678 * @brief Force or release AHB1 peripheral reset.
Anna Bridge 169:a7c7b631e539 679 * @{
Anna Bridge 169:a7c7b631e539 680 */
Anna Bridge 169:a7c7b631e539 681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Anna Bridge 169:a7c7b631e539 682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Anna Bridge 169:a7c7b631e539 683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Anna Bridge 169:a7c7b631e539 684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Anna Bridge 169:a7c7b631e539 685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Anna Bridge 169:a7c7b631e539 686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Anna Bridge 169:a7c7b631e539 687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Anna Bridge 169:a7c7b631e539 688
Anna Bridge 169:a7c7b631e539 689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
Anna Bridge 169:a7c7b631e539 690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Anna Bridge 169:a7c7b631e539 691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Anna Bridge 169:a7c7b631e539 692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Anna Bridge 169:a7c7b631e539 693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Anna Bridge 169:a7c7b631e539 694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Anna Bridge 169:a7c7b631e539 695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Anna Bridge 169:a7c7b631e539 696 /**
Anna Bridge 169:a7c7b631e539 697 * @}
Anna Bridge 169:a7c7b631e539 698 */
Anna Bridge 169:a7c7b631e539 699
Anna Bridge 169:a7c7b631e539 700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Anna Bridge 169:a7c7b631e539 701 * @brief Force or release APB1 peripheral reset.
Anna Bridge 169:a7c7b631e539 702 * @{
Anna Bridge 169:a7c7b631e539 703 */
Anna Bridge 169:a7c7b631e539 704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Anna Bridge 169:a7c7b631e539 705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Anna Bridge 169:a7c7b631e539 706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Anna Bridge 169:a7c7b631e539 707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Anna Bridge 169:a7c7b631e539 708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Anna Bridge 169:a7c7b631e539 709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Anna Bridge 169:a7c7b631e539 710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Anna Bridge 169:a7c7b631e539 711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Anna Bridge 169:a7c7b631e539 712
Anna Bridge 169:a7c7b631e539 713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
Anna Bridge 169:a7c7b631e539 714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Anna Bridge 169:a7c7b631e539 715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Anna Bridge 169:a7c7b631e539 716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Anna Bridge 169:a7c7b631e539 717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Anna Bridge 169:a7c7b631e539 718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Anna Bridge 169:a7c7b631e539 719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Anna Bridge 169:a7c7b631e539 720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Anna Bridge 169:a7c7b631e539 721 /**
Anna Bridge 169:a7c7b631e539 722 * @}
Anna Bridge 169:a7c7b631e539 723 */
Anna Bridge 169:a7c7b631e539 724
Anna Bridge 169:a7c7b631e539 725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Anna Bridge 169:a7c7b631e539 726 * @brief Force or release APB2 peripheral reset.
Anna Bridge 169:a7c7b631e539 727 * @{
Anna Bridge 169:a7c7b631e539 728 */
Anna Bridge 169:a7c7b631e539 729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Anna Bridge 169:a7c7b631e539 730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Anna Bridge 169:a7c7b631e539 731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Anna Bridge 169:a7c7b631e539 732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Anna Bridge 169:a7c7b631e539 733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Anna Bridge 169:a7c7b631e539 734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Anna Bridge 169:a7c7b631e539 735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Anna Bridge 169:a7c7b631e539 736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Anna Bridge 169:a7c7b631e539 737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Anna Bridge 169:a7c7b631e539 738
Anna Bridge 169:a7c7b631e539 739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
Anna Bridge 169:a7c7b631e539 740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Anna Bridge 169:a7c7b631e539 741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Anna Bridge 169:a7c7b631e539 742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Anna Bridge 169:a7c7b631e539 743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Anna Bridge 169:a7c7b631e539 744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Anna Bridge 169:a7c7b631e539 745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Anna Bridge 169:a7c7b631e539 746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Anna Bridge 169:a7c7b631e539 747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Anna Bridge 169:a7c7b631e539 748 /**
Anna Bridge 169:a7c7b631e539 749 * @}
Anna Bridge 169:a7c7b631e539 750 */
Anna Bridge 169:a7c7b631e539 751
Anna Bridge 169:a7c7b631e539 752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Anna Bridge 169:a7c7b631e539 753 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Anna Bridge 169:a7c7b631e539 754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Anna Bridge 169:a7c7b631e539 755 * power consumption.
Anna Bridge 169:a7c7b631e539 756 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Anna Bridge 169:a7c7b631e539 757 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Anna Bridge 169:a7c7b631e539 758 * @{
Anna Bridge 169:a7c7b631e539 759 */
Anna Bridge 169:a7c7b631e539 760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Anna Bridge 169:a7c7b631e539 761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Anna Bridge 169:a7c7b631e539 762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Anna Bridge 169:a7c7b631e539 763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Anna Bridge 169:a7c7b631e539 764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Anna Bridge 169:a7c7b631e539 765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
Anna Bridge 169:a7c7b631e539 766
Anna Bridge 169:a7c7b631e539 767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Anna Bridge 169:a7c7b631e539 768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Anna Bridge 169:a7c7b631e539 769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Anna Bridge 169:a7c7b631e539 770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Anna Bridge 169:a7c7b631e539 771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Anna Bridge 169:a7c7b631e539 772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Anna Bridge 169:a7c7b631e539 773 /**
Anna Bridge 169:a7c7b631e539 774 * @}
Anna Bridge 169:a7c7b631e539 775 */
Anna Bridge 169:a7c7b631e539 776
Anna Bridge 169:a7c7b631e539 777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Anna Bridge 169:a7c7b631e539 778 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Anna Bridge 169:a7c7b631e539 779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Anna Bridge 169:a7c7b631e539 780 * power consumption.
Anna Bridge 169:a7c7b631e539 781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Anna Bridge 169:a7c7b631e539 782 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Anna Bridge 169:a7c7b631e539 783 * @{
Anna Bridge 169:a7c7b631e539 784 */
Anna Bridge 169:a7c7b631e539 785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Anna Bridge 169:a7c7b631e539 786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Anna Bridge 169:a7c7b631e539 787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Anna Bridge 169:a7c7b631e539 788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Anna Bridge 169:a7c7b631e539 789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Anna Bridge 169:a7c7b631e539 790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Anna Bridge 169:a7c7b631e539 791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
Anna Bridge 169:a7c7b631e539 792
Anna Bridge 169:a7c7b631e539 793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Anna Bridge 169:a7c7b631e539 794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Anna Bridge 169:a7c7b631e539 795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Anna Bridge 169:a7c7b631e539 796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Anna Bridge 169:a7c7b631e539 797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Anna Bridge 169:a7c7b631e539 798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Anna Bridge 169:a7c7b631e539 799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Anna Bridge 169:a7c7b631e539 800 /**
Anna Bridge 169:a7c7b631e539 801 * @}
Anna Bridge 169:a7c7b631e539 802 */
Anna Bridge 169:a7c7b631e539 803
Anna Bridge 169:a7c7b631e539 804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Anna Bridge 169:a7c7b631e539 805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Anna Bridge 169:a7c7b631e539 806 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Anna Bridge 169:a7c7b631e539 807 * power consumption.
Anna Bridge 169:a7c7b631e539 808 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Anna Bridge 169:a7c7b631e539 809 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Anna Bridge 169:a7c7b631e539 810 * @{
Anna Bridge 169:a7c7b631e539 811 */
Anna Bridge 169:a7c7b631e539 812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Anna Bridge 169:a7c7b631e539 813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Anna Bridge 169:a7c7b631e539 814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Anna Bridge 169:a7c7b631e539 815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Anna Bridge 169:a7c7b631e539 816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Anna Bridge 169:a7c7b631e539 817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Anna Bridge 169:a7c7b631e539 818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Anna Bridge 169:a7c7b631e539 819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
Anna Bridge 169:a7c7b631e539 820
Anna Bridge 169:a7c7b631e539 821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Anna Bridge 169:a7c7b631e539 822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Anna Bridge 169:a7c7b631e539 823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Anna Bridge 169:a7c7b631e539 824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Anna Bridge 169:a7c7b631e539 825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Anna Bridge 169:a7c7b631e539 826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Anna Bridge 169:a7c7b631e539 827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Anna Bridge 169:a7c7b631e539 828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Anna Bridge 169:a7c7b631e539 829 /**
Anna Bridge 169:a7c7b631e539 830 * @}
Anna Bridge 169:a7c7b631e539 831 */
Anna Bridge 169:a7c7b631e539 832
Anna Bridge 169:a7c7b631e539 833 /** @defgroup RCC_HSI_Configuration HSI Configuration
Anna Bridge 169:a7c7b631e539 834 * @{
Anna Bridge 169:a7c7b631e539 835 */
Anna Bridge 169:a7c7b631e539 836
Anna Bridge 169:a7c7b631e539 837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Anna Bridge 169:a7c7b631e539 838 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Anna Bridge 169:a7c7b631e539 839 * It is used (enabled by hardware) as system clock source after startup
Anna Bridge 169:a7c7b631e539 840 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
Anna Bridge 169:a7c7b631e539 841 * of the HSE used directly or indirectly as system clock (if the Clock
Anna Bridge 169:a7c7b631e539 842 * Security System CSS is enabled).
Anna Bridge 169:a7c7b631e539 843 * @note HSI can not be stopped if it is used as system clock source. In this case,
Anna Bridge 169:a7c7b631e539 844 * you have to select another source of the system clock then stop the HSI.
Anna Bridge 169:a7c7b631e539 845 * @note After enabling the HSI, the application software should wait on HSIRDY
Anna Bridge 169:a7c7b631e539 846 * flag to be set indicating that HSI clock is stable and can be used as
Anna Bridge 169:a7c7b631e539 847 * system clock source.
Anna Bridge 169:a7c7b631e539 848 * This parameter can be: ENABLE or DISABLE.
Anna Bridge 169:a7c7b631e539 849 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Anna Bridge 169:a7c7b631e539 850 * clock cycles.
Anna Bridge 169:a7c7b631e539 851 */
Anna Bridge 169:a7c7b631e539 852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Anna Bridge 169:a7c7b631e539 853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
Anna Bridge 169:a7c7b631e539 854
Anna Bridge 169:a7c7b631e539 855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Anna Bridge 169:a7c7b631e539 856 * @note The calibration is used to compensate for the variations in voltage
Anna Bridge 169:a7c7b631e539 857 * and temperature that influence the frequency of the internal HSI RC.
Anna Bridge 169:a7c7b631e539 858 * @param __HSICalibrationValue__ specifies the calibration trimming value.
Anna Bridge 169:a7c7b631e539 859 * (default is RCC_HSICALIBRATION_DEFAULT).
Anna Bridge 169:a7c7b631e539 860 * This parameter must be a number between 0 and 0x1F.
Anna Bridge 169:a7c7b631e539 861 */
Anna Bridge 169:a7c7b631e539 862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
Anna Bridge 169:a7c7b631e539 863 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
Anna Bridge 169:a7c7b631e539 864 /**
Anna Bridge 169:a7c7b631e539 865 * @}
Anna Bridge 169:a7c7b631e539 866 */
Anna Bridge 169:a7c7b631e539 867
Anna Bridge 169:a7c7b631e539 868 /** @defgroup RCC_LSI_Configuration LSI Configuration
Anna Bridge 169:a7c7b631e539 869 * @{
Anna Bridge 169:a7c7b631e539 870 */
Anna Bridge 169:a7c7b631e539 871
Anna Bridge 169:a7c7b631e539 872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Anna Bridge 169:a7c7b631e539 873 * @note After enabling the LSI, the application software should wait on
Anna Bridge 169:a7c7b631e539 874 * LSIRDY flag to be set indicating that LSI clock is stable and can
Anna Bridge 169:a7c7b631e539 875 * be used to clock the IWDG and/or the RTC.
Anna Bridge 169:a7c7b631e539 876 * @note LSI can not be disabled if the IWDG is running.
Anna Bridge 169:a7c7b631e539 877 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Anna Bridge 169:a7c7b631e539 878 * clock cycles.
Anna Bridge 169:a7c7b631e539 879 */
Anna Bridge 169:a7c7b631e539 880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Anna Bridge 169:a7c7b631e539 881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Anna Bridge 169:a7c7b631e539 882 /**
Anna Bridge 169:a7c7b631e539 883 * @}
Anna Bridge 169:a7c7b631e539 884 */
Anna Bridge 169:a7c7b631e539 885
Anna Bridge 169:a7c7b631e539 886 /** @defgroup RCC_HSE_Configuration HSE Configuration
Anna Bridge 169:a7c7b631e539 887 * @{
Anna Bridge 169:a7c7b631e539 888 */
Anna Bridge 169:a7c7b631e539 889
Anna Bridge 169:a7c7b631e539 890 /**
Anna Bridge 169:a7c7b631e539 891 * @brief Macro to configure the External High Speed oscillator (HSE).
Anna Bridge 169:a7c7b631e539 892 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Anna Bridge 169:a7c7b631e539 893 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Anna Bridge 169:a7c7b631e539 894 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Anna Bridge 169:a7c7b631e539 895 * software should wait on HSERDY flag to be set indicating that HSE clock
Anna Bridge 169:a7c7b631e539 896 * is stable and can be used to clock the PLL and/or system clock.
Anna Bridge 169:a7c7b631e539 897 * @note HSE state can not be changed if it is used directly or through the
Anna Bridge 169:a7c7b631e539 898 * PLL as system clock. In this case, you have to select another source
Anna Bridge 169:a7c7b631e539 899 * of the system clock then change the HSE state (ex. disable it).
Anna Bridge 169:a7c7b631e539 900 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Anna Bridge 169:a7c7b631e539 901 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Anna Bridge 169:a7c7b631e539 902 * was previously enabled you have to enable it again after calling this
Anna Bridge 169:a7c7b631e539 903 * function.
Anna Bridge 169:a7c7b631e539 904 * @param __STATE__ specifies the new state of the HSE.
Anna Bridge 169:a7c7b631e539 905 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 906 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Anna Bridge 169:a7c7b631e539 907 * 6 HSE oscillator clock cycles.
Anna Bridge 169:a7c7b631e539 908 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
Anna Bridge 169:a7c7b631e539 909 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Anna Bridge 169:a7c7b631e539 910 */
Anna Bridge 169:a7c7b631e539 911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
Anna Bridge 169:a7c7b631e539 912 do { \
Anna Bridge 169:a7c7b631e539 913 if ((__STATE__) == RCC_HSE_ON) \
Anna Bridge 169:a7c7b631e539 914 { \
Anna Bridge 169:a7c7b631e539 915 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Anna Bridge 169:a7c7b631e539 916 } \
Anna Bridge 169:a7c7b631e539 917 else if ((__STATE__) == RCC_HSE_BYPASS) \
Anna Bridge 169:a7c7b631e539 918 { \
Anna Bridge 169:a7c7b631e539 919 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Anna Bridge 169:a7c7b631e539 920 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Anna Bridge 169:a7c7b631e539 921 } \
Anna Bridge 169:a7c7b631e539 922 else \
Anna Bridge 169:a7c7b631e539 923 { \
Anna Bridge 169:a7c7b631e539 924 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Anna Bridge 169:a7c7b631e539 925 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Anna Bridge 169:a7c7b631e539 926 } \
Anna Bridge 169:a7c7b631e539 927 } while(0U)
Anna Bridge 169:a7c7b631e539 928 /**
Anna Bridge 169:a7c7b631e539 929 * @}
Anna Bridge 169:a7c7b631e539 930 */
Anna Bridge 169:a7c7b631e539 931
Anna Bridge 169:a7c7b631e539 932 /** @defgroup RCC_LSE_Configuration LSE Configuration
Anna Bridge 169:a7c7b631e539 933 * @{
Anna Bridge 169:a7c7b631e539 934 */
Anna Bridge 169:a7c7b631e539 935
Anna Bridge 169:a7c7b631e539 936 /**
Anna Bridge 169:a7c7b631e539 937 * @brief Macro to configure the External Low Speed oscillator (LSE).
Anna Bridge 169:a7c7b631e539 938 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Anna Bridge 169:a7c7b631e539 939 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Anna Bridge 169:a7c7b631e539 940 * @note As the LSE is in the Backup domain and write access is denied to
Anna Bridge 169:a7c7b631e539 941 * this domain after reset, you have to enable write access using
Anna Bridge 169:a7c7b631e539 942 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Anna Bridge 169:a7c7b631e539 943 * (to be done once after reset).
Anna Bridge 169:a7c7b631e539 944 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Anna Bridge 169:a7c7b631e539 945 * software should wait on LSERDY flag to be set indicating that LSE clock
Anna Bridge 169:a7c7b631e539 946 * is stable and can be used to clock the RTC.
Anna Bridge 169:a7c7b631e539 947 * @param __STATE__ specifies the new state of the LSE.
Anna Bridge 169:a7c7b631e539 948 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 949 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Anna Bridge 169:a7c7b631e539 950 * 6 LSE oscillator clock cycles.
Anna Bridge 169:a7c7b631e539 951 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
Anna Bridge 169:a7c7b631e539 952 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Anna Bridge 169:a7c7b631e539 953 */
Anna Bridge 169:a7c7b631e539 954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Anna Bridge 169:a7c7b631e539 955 do { \
Anna Bridge 169:a7c7b631e539 956 if((__STATE__) == RCC_LSE_ON) \
Anna Bridge 169:a7c7b631e539 957 { \
Anna Bridge 169:a7c7b631e539 958 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Anna Bridge 169:a7c7b631e539 959 } \
Anna Bridge 169:a7c7b631e539 960 else if((__STATE__) == RCC_LSE_BYPASS) \
Anna Bridge 169:a7c7b631e539 961 { \
Anna Bridge 169:a7c7b631e539 962 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Anna Bridge 169:a7c7b631e539 963 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Anna Bridge 169:a7c7b631e539 964 } \
Anna Bridge 169:a7c7b631e539 965 else \
Anna Bridge 169:a7c7b631e539 966 { \
Anna Bridge 169:a7c7b631e539 967 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Anna Bridge 169:a7c7b631e539 968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Anna Bridge 169:a7c7b631e539 969 } \
Anna Bridge 169:a7c7b631e539 970 } while(0U)
Anna Bridge 169:a7c7b631e539 971 /**
Anna Bridge 169:a7c7b631e539 972 * @}
Anna Bridge 169:a7c7b631e539 973 */
Anna Bridge 169:a7c7b631e539 974
Anna Bridge 169:a7c7b631e539 975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Anna Bridge 169:a7c7b631e539 976 * @{
Anna Bridge 169:a7c7b631e539 977 */
Anna Bridge 169:a7c7b631e539 978
Anna Bridge 169:a7c7b631e539 979 /** @brief Macros to enable or disable the RTC clock.
Anna Bridge 169:a7c7b631e539 980 * @note These macros must be used only after the RTC clock source was selected.
Anna Bridge 169:a7c7b631e539 981 */
Anna Bridge 169:a7c7b631e539 982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Anna Bridge 169:a7c7b631e539 983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Anna Bridge 169:a7c7b631e539 984
Anna Bridge 169:a7c7b631e539 985 /** @brief Macros to configure the RTC clock (RTCCLK).
Anna Bridge 169:a7c7b631e539 986 * @note As the RTC clock configuration bits are in the Backup domain and write
Anna Bridge 169:a7c7b631e539 987 * access is denied to this domain after reset, you have to enable write
Anna Bridge 169:a7c7b631e539 988 * access using the Power Backup Access macro before to configure
Anna Bridge 169:a7c7b631e539 989 * the RTC clock source (to be done once after reset).
Anna Bridge 169:a7c7b631e539 990 * @note Once the RTC clock is configured it can't be changed unless the
Anna Bridge 169:a7c7b631e539 991 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Anna Bridge 169:a7c7b631e539 992 * a Power On Reset (POR).
Anna Bridge 169:a7c7b631e539 993 * @param __RTCCLKSource__ specifies the RTC clock source.
Anna Bridge 169:a7c7b631e539 994 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 995 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
Anna Bridge 169:a7c7b631e539 996 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Anna Bridge 169:a7c7b631e539 997 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Anna Bridge 169:a7c7b631e539 998 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
Anna Bridge 169:a7c7b631e539 999 * as RTC clock, where x:[2,31]
Anna Bridge 169:a7c7b631e539 1000 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Anna Bridge 169:a7c7b631e539 1001 * work in STOP and STANDBY modes, and can be used as wake-up source.
Anna Bridge 169:a7c7b631e539 1002 * However, when the HSE clock is used as RTC clock source, the RTC
Anna Bridge 169:a7c7b631e539 1003 * cannot be used in STOP and STANDBY modes.
Anna Bridge 169:a7c7b631e539 1004 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Anna Bridge 169:a7c7b631e539 1005 * RTC clock source).
Anna Bridge 169:a7c7b631e539 1006 */
Anna Bridge 169:a7c7b631e539 1007 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Anna Bridge 169:a7c7b631e539 1008 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Anna Bridge 169:a7c7b631e539 1009
Anna Bridge 169:a7c7b631e539 1010 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Anna Bridge 169:a7c7b631e539 1011 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
Anna Bridge 169:a7c7b631e539 1012 } while(0U)
Anna Bridge 169:a7c7b631e539 1013
Anna Bridge 169:a7c7b631e539 1014 /** @brief Macro to get the RTC clock source.
Anna Bridge 169:a7c7b631e539 1015 * @retval The clock source can be one of the following values:
Anna Bridge 169:a7c7b631e539 1016 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Anna Bridge 169:a7c7b631e539 1017 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Anna Bridge 169:a7c7b631e539 1018 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Anna Bridge 169:a7c7b631e539 1019 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
Anna Bridge 169:a7c7b631e539 1020 */
Anna Bridge 169:a7c7b631e539 1021 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Anna Bridge 169:a7c7b631e539 1022
Anna Bridge 169:a7c7b631e539 1023 /**
Anna Bridge 169:a7c7b631e539 1024 * @brief Get the RTC and HSE clock divider (RTCPRE).
Anna Bridge 169:a7c7b631e539 1025 * @retval Returned value can be one of the following values:
Anna Bridge 169:a7c7b631e539 1026 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
Anna Bridge 169:a7c7b631e539 1027 * as RTC clock, where x:[2,31]
Anna Bridge 169:a7c7b631e539 1028 */
Anna Bridge 169:a7c7b631e539 1029 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
Anna Bridge 169:a7c7b631e539 1030
Anna Bridge 169:a7c7b631e539 1031 /** @brief Macros to force or release the Backup domain reset.
Anna Bridge 169:a7c7b631e539 1032 * @note This function resets the RTC peripheral (including the backup registers)
Anna Bridge 169:a7c7b631e539 1033 * and the RTC clock source selection in RCC_CSR register.
Anna Bridge 169:a7c7b631e539 1034 * @note The BKPSRAM is not affected by this reset.
Anna Bridge 169:a7c7b631e539 1035 */
Anna Bridge 169:a7c7b631e539 1036 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Anna Bridge 169:a7c7b631e539 1037 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Anna Bridge 169:a7c7b631e539 1038 /**
Anna Bridge 169:a7c7b631e539 1039 * @}
Anna Bridge 169:a7c7b631e539 1040 */
Anna Bridge 169:a7c7b631e539 1041
Anna Bridge 169:a7c7b631e539 1042 /** @defgroup RCC_PLL_Configuration PLL Configuration
Anna Bridge 169:a7c7b631e539 1043 * @{
Anna Bridge 169:a7c7b631e539 1044 */
Anna Bridge 169:a7c7b631e539 1045
Anna Bridge 169:a7c7b631e539 1046 /** @brief Macros to enable or disable the main PLL.
Anna Bridge 169:a7c7b631e539 1047 * @note After enabling the main PLL, the application software should wait on
Anna Bridge 169:a7c7b631e539 1048 * PLLRDY flag to be set indicating that PLL clock is stable and can
Anna Bridge 169:a7c7b631e539 1049 * be used as system clock source.
Anna Bridge 169:a7c7b631e539 1050 * @note The main PLL can not be disabled if it is used as system clock source
Anna Bridge 169:a7c7b631e539 1051 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Anna Bridge 169:a7c7b631e539 1052 */
Anna Bridge 169:a7c7b631e539 1053 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Anna Bridge 169:a7c7b631e539 1054 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Anna Bridge 169:a7c7b631e539 1055
Anna Bridge 169:a7c7b631e539 1056 /** @brief Macro to configure the PLL clock source.
Anna Bridge 169:a7c7b631e539 1057 * @note This function must be used only when the main PLL is disabled.
Anna Bridge 169:a7c7b631e539 1058 * @param __PLLSOURCE__ specifies the PLL entry clock source.
Anna Bridge 169:a7c7b631e539 1059 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1060 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Anna Bridge 169:a7c7b631e539 1061 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Anna Bridge 169:a7c7b631e539 1062 *
Anna Bridge 169:a7c7b631e539 1063 */
Anna Bridge 169:a7c7b631e539 1064 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Anna Bridge 169:a7c7b631e539 1065
Anna Bridge 169:a7c7b631e539 1066 /** @brief Macro to configure the PLL multiplication factor.
Anna Bridge 169:a7c7b631e539 1067 * @note This function must be used only when the main PLL is disabled.
Anna Bridge 169:a7c7b631e539 1068 * @param __PLLM__ specifies the division factor for PLL VCO input clock
Anna Bridge 169:a7c7b631e539 1069 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Anna Bridge 169:a7c7b631e539 1070 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Anna Bridge 169:a7c7b631e539 1071 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Anna Bridge 169:a7c7b631e539 1072 * of 2 MHz to limit PLL jitter.
Anna Bridge 169:a7c7b631e539 1073 *
Anna Bridge 169:a7c7b631e539 1074 */
Anna Bridge 169:a7c7b631e539 1075 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Anna Bridge 169:a7c7b631e539 1076 /**
Anna Bridge 169:a7c7b631e539 1077 * @}
Anna Bridge 169:a7c7b631e539 1078 */
Anna Bridge 169:a7c7b631e539 1079
Anna Bridge 169:a7c7b631e539 1080 /** @defgroup RCC_Get_Clock_source Get Clock source
Anna Bridge 169:a7c7b631e539 1081 * @{
Anna Bridge 169:a7c7b631e539 1082 */
Anna Bridge 169:a7c7b631e539 1083 /**
Anna Bridge 169:a7c7b631e539 1084 * @brief Macro to configure the system clock source.
Anna Bridge 169:a7c7b631e539 1085 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
Anna Bridge 169:a7c7b631e539 1086 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1087 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Anna Bridge 169:a7c7b631e539 1088 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Anna Bridge 169:a7c7b631e539 1089 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Anna Bridge 169:a7c7b631e539 1090 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
Anna Bridge 169:a7c7b631e539 1091 * parameter is available only for STM32F446xx devices.
Anna Bridge 169:a7c7b631e539 1092 */
Anna Bridge 169:a7c7b631e539 1093 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Anna Bridge 169:a7c7b631e539 1094
Anna Bridge 169:a7c7b631e539 1095 /** @brief Macro to get the clock source used as system clock.
Anna Bridge 169:a7c7b631e539 1096 * @retval The clock source used as system clock. The returned value can be one
Anna Bridge 169:a7c7b631e539 1097 * of the following:
Anna Bridge 169:a7c7b631e539 1098 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Anna Bridge 169:a7c7b631e539 1099 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Anna Bridge 169:a7c7b631e539 1100 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Anna Bridge 169:a7c7b631e539 1101 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
Anna Bridge 169:a7c7b631e539 1102 * is available only for STM32F446xx devices.
Anna Bridge 169:a7c7b631e539 1103 */
Anna Bridge 169:a7c7b631e539 1104 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
Anna Bridge 169:a7c7b631e539 1105
Anna Bridge 169:a7c7b631e539 1106 /** @brief Macro to get the oscillator used as PLL clock source.
Anna Bridge 169:a7c7b631e539 1107 * @retval The oscillator used as PLL clock source. The returned value can be one
Anna Bridge 169:a7c7b631e539 1108 * of the following:
Anna Bridge 169:a7c7b631e539 1109 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Anna Bridge 169:a7c7b631e539 1110 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Anna Bridge 169:a7c7b631e539 1111 */
Anna Bridge 169:a7c7b631e539 1112 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Anna Bridge 169:a7c7b631e539 1113 /**
Anna Bridge 169:a7c7b631e539 1114 * @}
Anna Bridge 169:a7c7b631e539 1115 */
Anna Bridge 169:a7c7b631e539 1116
Anna Bridge 169:a7c7b631e539 1117 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Anna Bridge 169:a7c7b631e539 1118 * @{
Anna Bridge 169:a7c7b631e539 1119 */
Anna Bridge 169:a7c7b631e539 1120
Anna Bridge 169:a7c7b631e539 1121 /** @brief Macro to configure the MCO1 clock.
Anna Bridge 169:a7c7b631e539 1122 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Anna Bridge 169:a7c7b631e539 1123 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1124 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Anna Bridge 169:a7c7b631e539 1125 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Anna Bridge 169:a7c7b631e539 1126 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Anna Bridge 169:a7c7b631e539 1127 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Anna Bridge 169:a7c7b631e539 1128 * @param __MCODIV__ specifies the MCO clock prescaler.
Anna Bridge 169:a7c7b631e539 1129 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1130 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1131 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1132 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1133 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1134 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1135 */
Anna Bridge 169:a7c7b631e539 1136 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Anna Bridge 169:a7c7b631e539 1137 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Anna Bridge 169:a7c7b631e539 1138
Anna Bridge 169:a7c7b631e539 1139 /** @brief Macro to configure the MCO2 clock.
Anna Bridge 169:a7c7b631e539 1140 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Anna Bridge 169:a7c7b631e539 1141 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1142 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Anna Bridge 169:a7c7b631e539 1143 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Anna Bridge 169:a7c7b631e539 1144 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Anna Bridge 169:a7c7b631e539 1145 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Anna Bridge 169:a7c7b631e539 1146 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Anna Bridge 169:a7c7b631e539 1147 * @param __MCODIV__ specifies the MCO clock prescaler.
Anna Bridge 169:a7c7b631e539 1148 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1149 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1150 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1151 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1152 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1153 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Anna Bridge 169:a7c7b631e539 1154 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
Anna Bridge 169:a7c7b631e539 1155 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Anna Bridge 169:a7c7b631e539 1156 */
Anna Bridge 169:a7c7b631e539 1157 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Anna Bridge 169:a7c7b631e539 1158 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
Anna Bridge 169:a7c7b631e539 1159 /**
Anna Bridge 169:a7c7b631e539 1160 * @}
Anna Bridge 169:a7c7b631e539 1161 */
Anna Bridge 169:a7c7b631e539 1162
Anna Bridge 169:a7c7b631e539 1163 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Anna Bridge 169:a7c7b631e539 1164 * @brief macros to manage the specified RCC Flags and interrupts.
Anna Bridge 169:a7c7b631e539 1165 * @{
Anna Bridge 169:a7c7b631e539 1166 */
Anna Bridge 169:a7c7b631e539 1167
Anna Bridge 169:a7c7b631e539 1168 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Anna Bridge 169:a7c7b631e539 1169 * the selected interrupts).
Anna Bridge 169:a7c7b631e539 1170 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
Anna Bridge 169:a7c7b631e539 1171 * This parameter can be any combination of the following values:
Anna Bridge 169:a7c7b631e539 1172 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1173 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1174 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1175 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1176 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Anna Bridge 169:a7c7b631e539 1177 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Anna Bridge 169:a7c7b631e539 1178 */
Anna Bridge 169:a7c7b631e539 1179 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Anna Bridge 169:a7c7b631e539 1180
Anna Bridge 169:a7c7b631e539 1181 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Anna Bridge 169:a7c7b631e539 1182 * the selected interrupts).
Anna Bridge 169:a7c7b631e539 1183 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
Anna Bridge 169:a7c7b631e539 1184 * This parameter can be any combination of the following values:
Anna Bridge 169:a7c7b631e539 1185 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1186 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1187 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1188 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1189 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Anna Bridge 169:a7c7b631e539 1190 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Anna Bridge 169:a7c7b631e539 1191 */
Anna Bridge 169:a7c7b631e539 1192 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Anna Bridge 169:a7c7b631e539 1193
Anna Bridge 169:a7c7b631e539 1194 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Anna Bridge 169:a7c7b631e539 1195 * bits to clear the selected interrupt pending bits.
Anna Bridge 169:a7c7b631e539 1196 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
Anna Bridge 169:a7c7b631e539 1197 * This parameter can be any combination of the following values:
Anna Bridge 169:a7c7b631e539 1198 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1199 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1200 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1201 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1202 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Anna Bridge 169:a7c7b631e539 1203 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Anna Bridge 169:a7c7b631e539 1204 * @arg RCC_IT_CSS: Clock Security System interrupt
Anna Bridge 169:a7c7b631e539 1205 */
Anna Bridge 169:a7c7b631e539 1206 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Anna Bridge 169:a7c7b631e539 1207
Anna Bridge 169:a7c7b631e539 1208 /** @brief Check the RCC's interrupt has occurred or not.
Anna Bridge 169:a7c7b631e539 1209 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
Anna Bridge 169:a7c7b631e539 1210 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1211 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1212 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1213 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Anna Bridge 169:a7c7b631e539 1214 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Anna Bridge 169:a7c7b631e539 1215 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Anna Bridge 169:a7c7b631e539 1216 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Anna Bridge 169:a7c7b631e539 1217 * @arg RCC_IT_CSS: Clock Security System interrupt
Anna Bridge 169:a7c7b631e539 1218 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Anna Bridge 169:a7c7b631e539 1219 */
Anna Bridge 169:a7c7b631e539 1220 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Anna Bridge 169:a7c7b631e539 1221
Anna Bridge 169:a7c7b631e539 1222 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Anna Bridge 169:a7c7b631e539 1223 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Anna Bridge 169:a7c7b631e539 1224 */
Anna Bridge 169:a7c7b631e539 1225 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Anna Bridge 169:a7c7b631e539 1226
Anna Bridge 169:a7c7b631e539 1227 /** @brief Check RCC flag is set or not.
Anna Bridge 169:a7c7b631e539 1228 * @param __FLAG__ specifies the flag to check.
Anna Bridge 169:a7c7b631e539 1229 * This parameter can be one of the following values:
Anna Bridge 169:a7c7b631e539 1230 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Anna Bridge 169:a7c7b631e539 1231 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Anna Bridge 169:a7c7b631e539 1232 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Anna Bridge 169:a7c7b631e539 1233 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Anna Bridge 169:a7c7b631e539 1234 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Anna Bridge 169:a7c7b631e539 1235 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Anna Bridge 169:a7c7b631e539 1236 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Anna Bridge 169:a7c7b631e539 1237 * @arg RCC_FLAG_PINRST: Pin reset.
Anna Bridge 169:a7c7b631e539 1238 * @arg RCC_FLAG_PORRST: POR/PDR reset.
Anna Bridge 169:a7c7b631e539 1239 * @arg RCC_FLAG_SFTRST: Software reset.
Anna Bridge 169:a7c7b631e539 1240 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Anna Bridge 169:a7c7b631e539 1241 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Anna Bridge 169:a7c7b631e539 1242 * @arg RCC_FLAG_LPWRRST: Low Power reset.
Anna Bridge 169:a7c7b631e539 1243 * @retval The new state of __FLAG__ (TRUE or FALSE).
Anna Bridge 169:a7c7b631e539 1244 */
Anna Bridge 169:a7c7b631e539 1245 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
Anna Bridge 169:a7c7b631e539 1246 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
Anna Bridge 169:a7c7b631e539 1247
Anna Bridge 169:a7c7b631e539 1248 /**
Anna Bridge 169:a7c7b631e539 1249 * @}
Anna Bridge 169:a7c7b631e539 1250 */
Anna Bridge 169:a7c7b631e539 1251
Anna Bridge 169:a7c7b631e539 1252 /**
Anna Bridge 169:a7c7b631e539 1253 * @}
Anna Bridge 169:a7c7b631e539 1254 */
Anna Bridge 169:a7c7b631e539 1255
Anna Bridge 169:a7c7b631e539 1256 /* Exported functions --------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 1257 /** @addtogroup RCC_Exported_Functions
Anna Bridge 169:a7c7b631e539 1258 * @{
Anna Bridge 169:a7c7b631e539 1259 */
Anna Bridge 169:a7c7b631e539 1260
Anna Bridge 169:a7c7b631e539 1261 /** @addtogroup RCC_Exported_Functions_Group1
Anna Bridge 169:a7c7b631e539 1262 * @{
Anna Bridge 169:a7c7b631e539 1263 */
Anna Bridge 169:a7c7b631e539 1264 /* Initialization and de-initialization functions ******************************/
Anna Bridge 169:a7c7b631e539 1265 HAL_StatusTypeDef HAL_RCC_DeInit(void);
Anna Bridge 169:a7c7b631e539 1266 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Anna Bridge 169:a7c7b631e539 1267 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Anna Bridge 169:a7c7b631e539 1268 /**
Anna Bridge 169:a7c7b631e539 1269 * @}
Anna Bridge 169:a7c7b631e539 1270 */
Anna Bridge 169:a7c7b631e539 1271
Anna Bridge 169:a7c7b631e539 1272 /** @addtogroup RCC_Exported_Functions_Group2
Anna Bridge 169:a7c7b631e539 1273 * @{
Anna Bridge 169:a7c7b631e539 1274 */
Anna Bridge 169:a7c7b631e539 1275 /* Peripheral Control functions ************************************************/
Anna Bridge 169:a7c7b631e539 1276 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Anna Bridge 169:a7c7b631e539 1277 void HAL_RCC_EnableCSS(void);
Anna Bridge 169:a7c7b631e539 1278 void HAL_RCC_DisableCSS(void);
Anna Bridge 169:a7c7b631e539 1279 uint32_t HAL_RCC_GetSysClockFreq(void);
Anna Bridge 169:a7c7b631e539 1280 uint32_t HAL_RCC_GetHCLKFreq(void);
Anna Bridge 169:a7c7b631e539 1281 uint32_t HAL_RCC_GetPCLK1Freq(void);
Anna Bridge 169:a7c7b631e539 1282 uint32_t HAL_RCC_GetPCLK2Freq(void);
Anna Bridge 169:a7c7b631e539 1283 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Anna Bridge 169:a7c7b631e539 1284 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Anna Bridge 169:a7c7b631e539 1285
Anna Bridge 169:a7c7b631e539 1286 /* CSS NMI IRQ handler */
Anna Bridge 169:a7c7b631e539 1287 void HAL_RCC_NMI_IRQHandler(void);
Anna Bridge 169:a7c7b631e539 1288
Anna Bridge 169:a7c7b631e539 1289 /* User Callbacks in non blocking mode (IT mode) */
Anna Bridge 169:a7c7b631e539 1290 void HAL_RCC_CSSCallback(void);
Anna Bridge 169:a7c7b631e539 1291
Anna Bridge 169:a7c7b631e539 1292 /**
Anna Bridge 169:a7c7b631e539 1293 * @}
Anna Bridge 169:a7c7b631e539 1294 */
Anna Bridge 169:a7c7b631e539 1295
Anna Bridge 169:a7c7b631e539 1296 /**
Anna Bridge 169:a7c7b631e539 1297 * @}
Anna Bridge 169:a7c7b631e539 1298 */
Anna Bridge 169:a7c7b631e539 1299
Anna Bridge 169:a7c7b631e539 1300 /* Private types -------------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 1301 /* Private variables ---------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 1302 /* Private constants ---------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 1303 /** @defgroup RCC_Private_Constants RCC Private Constants
Anna Bridge 169:a7c7b631e539 1304 * @{
Anna Bridge 169:a7c7b631e539 1305 */
Anna Bridge 169:a7c7b631e539 1306
Anna Bridge 169:a7c7b631e539 1307 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Anna Bridge 169:a7c7b631e539 1308 * @brief RCC registers bit address in the alias region
Anna Bridge 169:a7c7b631e539 1309 * @{
Anna Bridge 169:a7c7b631e539 1310 */
Anna Bridge 169:a7c7b631e539 1311 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Anna Bridge 169:a7c7b631e539 1312 /* --- CR Register --- */
Anna Bridge 169:a7c7b631e539 1313 /* Alias word address of HSION bit */
Anna Bridge 169:a7c7b631e539 1314 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
Anna Bridge 169:a7c7b631e539 1315 #define RCC_HSION_BIT_NUMBER 0x00U
Anna Bridge 169:a7c7b631e539 1316 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
Anna Bridge 169:a7c7b631e539 1317 /* Alias word address of CSSON bit */
Anna Bridge 169:a7c7b631e539 1318 #define RCC_CSSON_BIT_NUMBER 0x13U
Anna Bridge 169:a7c7b631e539 1319 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
Anna Bridge 169:a7c7b631e539 1320 /* Alias word address of PLLON bit */
Anna Bridge 169:a7c7b631e539 1321 #define RCC_PLLON_BIT_NUMBER 0x18U
Anna Bridge 169:a7c7b631e539 1322 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
Anna Bridge 169:a7c7b631e539 1323
Anna Bridge 169:a7c7b631e539 1324 /* --- BDCR Register --- */
Anna Bridge 169:a7c7b631e539 1325 /* Alias word address of RTCEN bit */
Anna Bridge 169:a7c7b631e539 1326 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
Anna Bridge 169:a7c7b631e539 1327 #define RCC_RTCEN_BIT_NUMBER 0x0FU
Anna Bridge 169:a7c7b631e539 1328 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
Anna Bridge 169:a7c7b631e539 1329 /* Alias word address of BDRST bit */
Anna Bridge 169:a7c7b631e539 1330 #define RCC_BDRST_BIT_NUMBER 0x10U
Anna Bridge 169:a7c7b631e539 1331 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
Anna Bridge 169:a7c7b631e539 1332
Anna Bridge 169:a7c7b631e539 1333 /* --- CSR Register --- */
Anna Bridge 169:a7c7b631e539 1334 /* Alias word address of LSION bit */
Anna Bridge 169:a7c7b631e539 1335 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
Anna Bridge 169:a7c7b631e539 1336 #define RCC_LSION_BIT_NUMBER 0x00U
Anna Bridge 169:a7c7b631e539 1337 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
Anna Bridge 169:a7c7b631e539 1338
Anna Bridge 169:a7c7b631e539 1339 /* CR register byte 3 (Bits[23:16]) base address */
Anna Bridge 169:a7c7b631e539 1340 #define RCC_CR_BYTE2_ADDRESS 0x40023802U
Anna Bridge 169:a7c7b631e539 1341
Anna Bridge 169:a7c7b631e539 1342 /* CIR register byte 2 (Bits[15:8]) base address */
Anna Bridge 169:a7c7b631e539 1343 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
Anna Bridge 169:a7c7b631e539 1344
Anna Bridge 169:a7c7b631e539 1345 /* CIR register byte 3 (Bits[23:16]) base address */
Anna Bridge 169:a7c7b631e539 1346 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
Anna Bridge 169:a7c7b631e539 1347
Anna Bridge 169:a7c7b631e539 1348 /* BDCR register base address */
Anna Bridge 169:a7c7b631e539 1349 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Anna Bridge 169:a7c7b631e539 1350
Anna Bridge 169:a7c7b631e539 1351 #define RCC_DBP_TIMEOUT_VALUE 2U
Anna Bridge 169:a7c7b631e539 1352 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Anna Bridge 169:a7c7b631e539 1353
Anna Bridge 169:a7c7b631e539 1354 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Anna Bridge 169:a7c7b631e539 1355 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */
Anna Bridge 169:a7c7b631e539 1356 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */
Anna Bridge 169:a7c7b631e539 1357 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
Anna Bridge 169:a7c7b631e539 1358
Anna Bridge 169:a7c7b631e539 1359 /**
Anna Bridge 169:a7c7b631e539 1360 * @}
Anna Bridge 169:a7c7b631e539 1361 */
Anna Bridge 169:a7c7b631e539 1362
Anna Bridge 169:a7c7b631e539 1363 /**
Anna Bridge 169:a7c7b631e539 1364 * @}
Anna Bridge 169:a7c7b631e539 1365 */
Anna Bridge 169:a7c7b631e539 1366
Anna Bridge 169:a7c7b631e539 1367 /* Private macros ------------------------------------------------------------*/
Anna Bridge 169:a7c7b631e539 1368 /** @defgroup RCC_Private_Macros RCC Private Macros
Anna Bridge 169:a7c7b631e539 1369 * @{
Anna Bridge 169:a7c7b631e539 1370 */
Anna Bridge 169:a7c7b631e539 1371
Anna Bridge 169:a7c7b631e539 1372 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Anna Bridge 169:a7c7b631e539 1373 * @{
Anna Bridge 169:a7c7b631e539 1374 */
Anna Bridge 169:a7c7b631e539 1375 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
Anna Bridge 169:a7c7b631e539 1376
Anna Bridge 169:a7c7b631e539 1377 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Anna Bridge 169:a7c7b631e539 1378 ((HSE) == RCC_HSE_BYPASS))
Anna Bridge 169:a7c7b631e539 1379
Anna Bridge 169:a7c7b631e539 1380 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Anna Bridge 169:a7c7b631e539 1381 ((LSE) == RCC_LSE_BYPASS))
Anna Bridge 169:a7c7b631e539 1382
Anna Bridge 169:a7c7b631e539 1383 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Anna Bridge 169:a7c7b631e539 1384
Anna Bridge 169:a7c7b631e539 1385 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Anna Bridge 169:a7c7b631e539 1386
Anna Bridge 169:a7c7b631e539 1387 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Anna Bridge 169:a7c7b631e539 1388
Anna Bridge 169:a7c7b631e539 1389 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Anna Bridge 169:a7c7b631e539 1390 ((SOURCE) == RCC_PLLSOURCE_HSE))
Anna Bridge 169:a7c7b631e539 1391
Anna Bridge 169:a7c7b631e539 1392 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Anna Bridge 169:a7c7b631e539 1393 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Anna Bridge 169:a7c7b631e539 1394 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Anna Bridge 169:a7c7b631e539 1395 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Anna Bridge 169:a7c7b631e539 1396
Anna Bridge 169:a7c7b631e539 1397 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Anna Bridge 169:a7c7b631e539 1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Anna Bridge 169:a7c7b631e539 1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
Anna Bridge 169:a7c7b631e539 1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
Anna Bridge 169:a7c7b631e539 1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
Anna Bridge 169:a7c7b631e539 1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
Anna Bridge 169:a7c7b631e539 1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
Anna Bridge 169:a7c7b631e539 1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
Anna Bridge 169:a7c7b631e539 1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
Anna Bridge 169:a7c7b631e539 1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
Anna Bridge 169:a7c7b631e539 1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
Anna Bridge 169:a7c7b631e539 1408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
Anna Bridge 169:a7c7b631e539 1409 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
Anna Bridge 169:a7c7b631e539 1410 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
Anna Bridge 169:a7c7b631e539 1411 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
Anna Bridge 169:a7c7b631e539 1412 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
Anna Bridge 169:a7c7b631e539 1413 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
Anna Bridge 169:a7c7b631e539 1414 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
Anna Bridge 169:a7c7b631e539 1415 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
Anna Bridge 169:a7c7b631e539 1416 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
Anna Bridge 169:a7c7b631e539 1417 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
Anna Bridge 169:a7c7b631e539 1418 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
Anna Bridge 169:a7c7b631e539 1419 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
Anna Bridge 169:a7c7b631e539 1420 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
Anna Bridge 169:a7c7b631e539 1421 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
Anna Bridge 169:a7c7b631e539 1422 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
Anna Bridge 169:a7c7b631e539 1423 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
Anna Bridge 169:a7c7b631e539 1424 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
Anna Bridge 169:a7c7b631e539 1425 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
Anna Bridge 169:a7c7b631e539 1426 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
Anna Bridge 169:a7c7b631e539 1427 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
Anna Bridge 169:a7c7b631e539 1428 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
Anna Bridge 169:a7c7b631e539 1429
Anna Bridge 169:a7c7b631e539 1430 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
Anna Bridge 169:a7c7b631e539 1431
Anna Bridge 169:a7c7b631e539 1432 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
Anna Bridge 169:a7c7b631e539 1433
Anna Bridge 169:a7c7b631e539 1434 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
Anna Bridge 169:a7c7b631e539 1435
Anna Bridge 169:a7c7b631e539 1436 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Anna Bridge 169:a7c7b631e539 1437 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Anna Bridge 169:a7c7b631e539 1438 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Anna Bridge 169:a7c7b631e539 1439 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Anna Bridge 169:a7c7b631e539 1440 ((HCLK) == RCC_SYSCLK_DIV512))
Anna Bridge 169:a7c7b631e539 1441
Anna Bridge 169:a7c7b631e539 1442 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
Anna Bridge 169:a7c7b631e539 1443
Anna Bridge 169:a7c7b631e539 1444 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Anna Bridge 169:a7c7b631e539 1445 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Anna Bridge 169:a7c7b631e539 1446 ((PCLK) == RCC_HCLK_DIV16))
Anna Bridge 169:a7c7b631e539 1447
Anna Bridge 169:a7c7b631e539 1448 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Anna Bridge 169:a7c7b631e539 1449
Anna Bridge 169:a7c7b631e539 1450 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Anna Bridge 169:a7c7b631e539 1451 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Anna Bridge 169:a7c7b631e539 1452
Anna Bridge 169:a7c7b631e539 1453 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Anna Bridge 169:a7c7b631e539 1454 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Anna Bridge 169:a7c7b631e539 1455 ((DIV) == RCC_MCODIV_5))
Anna Bridge 169:a7c7b631e539 1456 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
Anna Bridge 169:a7c7b631e539 1457
Anna Bridge 169:a7c7b631e539 1458 /**
Anna Bridge 169:a7c7b631e539 1459 * @}
Anna Bridge 169:a7c7b631e539 1460 */
Anna Bridge 169:a7c7b631e539 1461
Anna Bridge 169:a7c7b631e539 1462 /**
Anna Bridge 169:a7c7b631e539 1463 * @}
Anna Bridge 169:a7c7b631e539 1464 */
Anna Bridge 169:a7c7b631e539 1465
Anna Bridge 169:a7c7b631e539 1466 /**
Anna Bridge 169:a7c7b631e539 1467 * @}
Anna Bridge 169:a7c7b631e539 1468 */
Anna Bridge 169:a7c7b631e539 1469
Anna Bridge 169:a7c7b631e539 1470 /**
Anna Bridge 169:a7c7b631e539 1471 * @}
Anna Bridge 169:a7c7b631e539 1472 */
Anna Bridge 169:a7c7b631e539 1473
Anna Bridge 169:a7c7b631e539 1474 #ifdef __cplusplus
Anna Bridge 169:a7c7b631e539 1475 }
Anna Bridge 169:a7c7b631e539 1476 #endif
Anna Bridge 169:a7c7b631e539 1477
Anna Bridge 169:a7c7b631e539 1478 #endif /* __STM32F4xx_HAL_RCC_H */
Anna Bridge 169:a7c7b631e539 1479
Anna Bridge 169:a7c7b631e539 1480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/