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TARGET_SAKURAIO_EVB_01/TOOLCHAIN_ARM_MICRO/stm32f4xx_hal_qspi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	161:aa5281ff4a02	1	/**
AnnaBridge	161:aa5281ff4a02	2	******************************************************************************
AnnaBridge	161:aa5281ff4a02	3	* @file stm32f4xx_hal_qspi.h
AnnaBridge	161:aa5281ff4a02	4	* @author MCD Application Team
AnnaBridge	161:aa5281ff4a02	5	* @brief Header file of QSPI HAL module.
AnnaBridge	161:aa5281ff4a02	6	******************************************************************************
AnnaBridge	161:aa5281ff4a02	7	* @attention
AnnaBridge	161:aa5281ff4a02	8	*
AnnaBridge	161:aa5281ff4a02	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	161:aa5281ff4a02	10	*
AnnaBridge	161:aa5281ff4a02	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	161:aa5281ff4a02	12	* are permitted provided that the following conditions are met:
AnnaBridge	161:aa5281ff4a02	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	161:aa5281ff4a02	14	* this list of conditions and the following disclaimer.
AnnaBridge	161:aa5281ff4a02	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	161:aa5281ff4a02	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	161:aa5281ff4a02	17	* and/or other materials provided with the distribution.
AnnaBridge	161:aa5281ff4a02	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	161:aa5281ff4a02	19	* may be used to endorse or promote products derived from this software
AnnaBridge	161:aa5281ff4a02	20	* without specific prior written permission.
AnnaBridge	161:aa5281ff4a02	21	*
AnnaBridge	161:aa5281ff4a02	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	161:aa5281ff4a02	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	161:aa5281ff4a02	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	161:aa5281ff4a02	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	161:aa5281ff4a02	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	161:aa5281ff4a02	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	161:aa5281ff4a02	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	161:aa5281ff4a02	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	161:aa5281ff4a02	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	161:aa5281ff4a02	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	161:aa5281ff4a02	32	*
AnnaBridge	161:aa5281ff4a02	33	******************************************************************************
AnnaBridge	161:aa5281ff4a02	34	*/
AnnaBridge	161:aa5281ff4a02	35
AnnaBridge	161:aa5281ff4a02	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	161:aa5281ff4a02	37	#ifndef __STM32F4xx_HAL_QSPI_H
AnnaBridge	161:aa5281ff4a02	38	#define __STM32F4xx_HAL_QSPI_H
AnnaBridge	161:aa5281ff4a02	39
AnnaBridge	161:aa5281ff4a02	40	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	41	extern "C" {
AnnaBridge	161:aa5281ff4a02	42	#endif
AnnaBridge	161:aa5281ff4a02	43
AnnaBridge	161:aa5281ff4a02	44	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
AnnaBridge	161:aa5281ff4a02	45	defined(STM32F412Rx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
AnnaBridge	161:aa5281ff4a02	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	47	#include "stm32f4xx_hal_def.h"
AnnaBridge	161:aa5281ff4a02	48
AnnaBridge	161:aa5281ff4a02	49	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	161:aa5281ff4a02	50	* @{
AnnaBridge	161:aa5281ff4a02	51	*/
AnnaBridge	161:aa5281ff4a02	52
AnnaBridge	161:aa5281ff4a02	53	/** @addtogroup QSPI
AnnaBridge	161:aa5281ff4a02	54	* @{
AnnaBridge	161:aa5281ff4a02	55	*/
AnnaBridge	161:aa5281ff4a02	56
AnnaBridge	161:aa5281ff4a02	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	58	/** @defgroup QSPI_Exported_Types QSPI Exported Types
AnnaBridge	161:aa5281ff4a02	59	* @{
AnnaBridge	161:aa5281ff4a02	60	*/
AnnaBridge	161:aa5281ff4a02	61
AnnaBridge	161:aa5281ff4a02	62	/**
AnnaBridge	161:aa5281ff4a02	63	* @brief QSPI Init structure definition
AnnaBridge	161:aa5281ff4a02	64	*/
AnnaBridge	161:aa5281ff4a02	65
AnnaBridge	161:aa5281ff4a02	66	typedef struct
AnnaBridge	161:aa5281ff4a02	67	{
AnnaBridge	161:aa5281ff4a02	68	uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
AnnaBridge	161:aa5281ff4a02	69	This parameter can be a number between 0 and 255 */
AnnaBridge	161:aa5281ff4a02	70
AnnaBridge	161:aa5281ff4a02	71	uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
AnnaBridge	161:aa5281ff4a02	72	This parameter can be a value between 1 and 32 */
AnnaBridge	161:aa5281ff4a02	73
AnnaBridge	161:aa5281ff4a02	74	uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
AnnaBridge	161:aa5281ff4a02	75	take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
AnnaBridge	161:aa5281ff4a02	76	This parameter can be a value of @ref QSPI_SampleShifting */
AnnaBridge	161:aa5281ff4a02	77
AnnaBridge	161:aa5281ff4a02	78	uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
AnnaBridge	161:aa5281ff4a02	79	required to address the flash memory. The flash capacity can be up to 4GB
AnnaBridge	161:aa5281ff4a02	80	(addressed using 32 bits) in indirect mode, but the addressable space in
AnnaBridge	161:aa5281ff4a02	81	memory-mapped mode is limited to 256MB
AnnaBridge	161:aa5281ff4a02	82	This parameter can be a number between 0 and 31 */
AnnaBridge	161:aa5281ff4a02	83
AnnaBridge	161:aa5281ff4a02	84	uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
AnnaBridge	161:aa5281ff4a02	85	of clock cycles which the chip select must remain high between commands.
AnnaBridge	161:aa5281ff4a02	86	This parameter can be a value of @ref QSPI_ChipSelectHighTime */
AnnaBridge	161:aa5281ff4a02	87
AnnaBridge	161:aa5281ff4a02	88	uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
AnnaBridge	161:aa5281ff4a02	89	This parameter can be a value of @ref QSPI_ClockMode */
AnnaBridge	161:aa5281ff4a02	90
AnnaBridge	161:aa5281ff4a02	91	uint32_t FlashID; /* Specifies the Flash which will be used,
AnnaBridge	161:aa5281ff4a02	92	This parameter can be a value of @ref QSPI_Flash_Select */
AnnaBridge	161:aa5281ff4a02	93
AnnaBridge	161:aa5281ff4a02	94	uint32_t DualFlash; /* Specifies the Dual Flash Mode State
AnnaBridge	161:aa5281ff4a02	95	This parameter can be a value of @ref QSPI_DualFlash_Mode */
AnnaBridge	161:aa5281ff4a02	96	}QSPI_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	97
AnnaBridge	161:aa5281ff4a02	98	/**
AnnaBridge	161:aa5281ff4a02	99	* @brief HAL QSPI State structures definition
AnnaBridge	161:aa5281ff4a02	100	*/
AnnaBridge	161:aa5281ff4a02	101	typedef enum
AnnaBridge	161:aa5281ff4a02	102	{
AnnaBridge	161:aa5281ff4a02	103	HAL_QSPI_STATE_RESET = 0x00U, /!< Peripheral not initialized /
AnnaBridge	161:aa5281ff4a02	104	HAL_QSPI_STATE_READY = 0x01U, /!< Peripheral initialized and ready for use /
AnnaBridge	161:aa5281ff4a02	105	HAL_QSPI_STATE_BUSY = 0x02U, /!< Peripheral in indirect mode and busy /
AnnaBridge	161:aa5281ff4a02	106	HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /!< Peripheral in indirect mode with transmission ongoing /
AnnaBridge	161:aa5281ff4a02	107	HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /!< Peripheral in indirect mode with reception ongoing /
AnnaBridge	161:aa5281ff4a02	108	HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /!< Peripheral in auto polling mode ongoing /
AnnaBridge	161:aa5281ff4a02	109	HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /!< Peripheral in memory mapped mode ongoing /
AnnaBridge	161:aa5281ff4a02	110	HAL_QSPI_STATE_ABORT = 0x08U, /!< Peripheral with abort request ongoing /
AnnaBridge	161:aa5281ff4a02	111	HAL_QSPI_STATE_ERROR = 0x04U /!< Peripheral in error /
AnnaBridge	161:aa5281ff4a02	112	}HAL_QSPI_StateTypeDef;
AnnaBridge	161:aa5281ff4a02	113
AnnaBridge	161:aa5281ff4a02	114	/**
AnnaBridge	161:aa5281ff4a02	115	* @brief QSPI Handle Structure definition
AnnaBridge	161:aa5281ff4a02	116	*/
AnnaBridge	161:aa5281ff4a02	117	typedef struct
AnnaBridge	161:aa5281ff4a02	118	{
AnnaBridge	161:aa5281ff4a02	119	QUADSPI_TypeDef Instance; / QSPI registers base address */
AnnaBridge	161:aa5281ff4a02	120	QSPI_InitTypeDef Init; /* QSPI communication parameters */
AnnaBridge	161:aa5281ff4a02	121	uint8_t pTxBuffPtr; / Pointer to QSPI Tx transfer Buffer */
AnnaBridge	161:aa5281ff4a02	122	__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
AnnaBridge	161:aa5281ff4a02	123	__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
AnnaBridge	161:aa5281ff4a02	124	uint8_t pRxBuffPtr; / Pointer to QSPI Rx transfer Buffer */
AnnaBridge	161:aa5281ff4a02	125	__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
AnnaBridge	161:aa5281ff4a02	126	__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
AnnaBridge	161:aa5281ff4a02	127	DMA_HandleTypeDef hdma; / QSPI Rx/Tx DMA Handle parameters */
AnnaBridge	161:aa5281ff4a02	128	__IO HAL_LockTypeDef Lock; /* Locking object */
AnnaBridge	161:aa5281ff4a02	129	__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
AnnaBridge	161:aa5281ff4a02	130	__IO uint32_t ErrorCode; /* QSPI Error code */
AnnaBridge	161:aa5281ff4a02	131	uint32_t Timeout; /* Timeout for the QSPI memory access */
AnnaBridge	161:aa5281ff4a02	132	}QSPI_HandleTypeDef;
AnnaBridge	161:aa5281ff4a02	133
AnnaBridge	161:aa5281ff4a02	134	/**
AnnaBridge	161:aa5281ff4a02	135	* @brief QSPI Command structure definition
AnnaBridge	161:aa5281ff4a02	136	*/
AnnaBridge	161:aa5281ff4a02	137	typedef struct
AnnaBridge	161:aa5281ff4a02	138	{
AnnaBridge	161:aa5281ff4a02	139	uint32_t Instruction; /* Specifies the Instruction to be sent
AnnaBridge	161:aa5281ff4a02	140	This parameter can be a value (8-bit) between 0x00 and 0xFF */
AnnaBridge	161:aa5281ff4a02	141	uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
AnnaBridge	161:aa5281ff4a02	142	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
AnnaBridge	161:aa5281ff4a02	143	uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
AnnaBridge	161:aa5281ff4a02	144	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
AnnaBridge	161:aa5281ff4a02	145	uint32_t AddressSize; /* Specifies the Address Size
AnnaBridge	161:aa5281ff4a02	146	This parameter can be a value of @ref QSPI_AddressSize */
AnnaBridge	161:aa5281ff4a02	147	uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
AnnaBridge	161:aa5281ff4a02	148	This parameter can be a value of @ref QSPI_AlternateBytesSize */
AnnaBridge	161:aa5281ff4a02	149	uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
AnnaBridge	161:aa5281ff4a02	150	This parameter can be a number between 0 and 31 */
AnnaBridge	161:aa5281ff4a02	151	uint32_t InstructionMode; /* Specifies the Instruction Mode
AnnaBridge	161:aa5281ff4a02	152	This parameter can be a value of @ref QSPI_InstructionMode */
AnnaBridge	161:aa5281ff4a02	153	uint32_t AddressMode; /* Specifies the Address Mode
AnnaBridge	161:aa5281ff4a02	154	This parameter can be a value of @ref QSPI_AddressMode */
AnnaBridge	161:aa5281ff4a02	155	uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
AnnaBridge	161:aa5281ff4a02	156	This parameter can be a value of @ref QSPI_AlternateBytesMode */
AnnaBridge	161:aa5281ff4a02	157	uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
AnnaBridge	161:aa5281ff4a02	158	This parameter can be a value of @ref QSPI_DataMode */
AnnaBridge	161:aa5281ff4a02	159	uint32_t NbData; /* Specifies the number of data to transfer.
AnnaBridge	161:aa5281ff4a02	160	This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
AnnaBridge	161:aa5281ff4a02	161	until end of memory)*/
AnnaBridge	161:aa5281ff4a02	162	uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
AnnaBridge	161:aa5281ff4a02	163	This parameter can be a value of @ref QSPI_DdrMode */
AnnaBridge	161:aa5281ff4a02	164	uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
AnnaBridge	161:aa5281ff4a02	165	system clock in DDR mode.
AnnaBridge	161:aa5281ff4a02	166	This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
AnnaBridge	161:aa5281ff4a02	167	uint32_t SIOOMode; /* Specifies the send instruction only once mode
AnnaBridge	161:aa5281ff4a02	168	This parameter can be a value of @ref QSPI_SIOOMode */
AnnaBridge	161:aa5281ff4a02	169	}QSPI_CommandTypeDef;
AnnaBridge	161:aa5281ff4a02	170
AnnaBridge	161:aa5281ff4a02	171	/**
AnnaBridge	161:aa5281ff4a02	172	* @brief QSPI Auto Polling mode configuration structure definition
AnnaBridge	161:aa5281ff4a02	173	*/
AnnaBridge	161:aa5281ff4a02	174	typedef struct
AnnaBridge	161:aa5281ff4a02	175	{
AnnaBridge	161:aa5281ff4a02	176	uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
AnnaBridge	161:aa5281ff4a02	177	This parameter can be any value between 0 and 0xFFFFFFFFU */
AnnaBridge	161:aa5281ff4a02	178	uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
AnnaBridge	161:aa5281ff4a02	179	This parameter can be any value between 0 and 0xFFFFFFFFU */
AnnaBridge	161:aa5281ff4a02	180	uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
AnnaBridge	161:aa5281ff4a02	181	This parameter can be any value between 0 and 0xFFFFU */
AnnaBridge	161:aa5281ff4a02	182	uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
AnnaBridge	161:aa5281ff4a02	183	This parameter can be any value between 1 and 4 */
AnnaBridge	161:aa5281ff4a02	184	uint32_t MatchMode; /* Specifies the method used for determining a match.
AnnaBridge	161:aa5281ff4a02	185	This parameter can be a value of @ref QSPI_MatchMode */
AnnaBridge	161:aa5281ff4a02	186	uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
AnnaBridge	161:aa5281ff4a02	187	This parameter can be a value of @ref QSPI_AutomaticStop */
AnnaBridge	161:aa5281ff4a02	188	}QSPI_AutoPollingTypeDef;
AnnaBridge	161:aa5281ff4a02	189
AnnaBridge	161:aa5281ff4a02	190	/**
AnnaBridge	161:aa5281ff4a02	191	* @brief QSPI Memory Mapped mode configuration structure definition
AnnaBridge	161:aa5281ff4a02	192	*/
AnnaBridge	161:aa5281ff4a02	193	typedef struct
AnnaBridge	161:aa5281ff4a02	194	{
AnnaBridge	161:aa5281ff4a02	195	uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
AnnaBridge	161:aa5281ff4a02	196	This parameter can be any value between 0 and 0xFFFFU */
AnnaBridge	161:aa5281ff4a02	197	uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
AnnaBridge	161:aa5281ff4a02	198	This parameter can be a value of @ref QSPI_TimeOutActivation */
AnnaBridge	161:aa5281ff4a02	199	}QSPI_MemoryMappedTypeDef;
AnnaBridge	161:aa5281ff4a02	200	/**
AnnaBridge	161:aa5281ff4a02	201	* @}
AnnaBridge	161:aa5281ff4a02	202	*/
AnnaBridge	161:aa5281ff4a02	203
AnnaBridge	161:aa5281ff4a02	204	/* Exported constants --------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	205	/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
AnnaBridge	161:aa5281ff4a02	206	* @{
AnnaBridge	161:aa5281ff4a02	207	*/
AnnaBridge	161:aa5281ff4a02	208	/** @defgroup QSPI_ErrorCode QSPI Error Code
AnnaBridge	161:aa5281ff4a02	209	* @{
AnnaBridge	161:aa5281ff4a02	210	*/
AnnaBridge	161:aa5281ff4a02	211	#define HAL_QSPI_ERROR_NONE 0x00000000U /!< No error /
AnnaBridge	161:aa5281ff4a02	212	#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /!< Timeout error /
AnnaBridge	161:aa5281ff4a02	213	#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /!< Transfer error /
AnnaBridge	161:aa5281ff4a02	214	#define HAL_QSPI_ERROR_DMA 0x00000004U /!< DMA transfer error /
AnnaBridge	161:aa5281ff4a02	215	#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /!< Invalid parameters error /
AnnaBridge	161:aa5281ff4a02	216	/**
AnnaBridge	161:aa5281ff4a02	217	* @}
AnnaBridge	161:aa5281ff4a02	218	*/
AnnaBridge	161:aa5281ff4a02	219
AnnaBridge	161:aa5281ff4a02	220	/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
AnnaBridge	161:aa5281ff4a02	221	* @{
AnnaBridge	161:aa5281ff4a02	222	*/
AnnaBridge	161:aa5281ff4a02	223	#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /!<No clock cycle shift to sample data/
AnnaBridge	161:aa5281ff4a02	224	#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /!<1/2 clock cycle shift to sample data/
AnnaBridge	161:aa5281ff4a02	225	/**
AnnaBridge	161:aa5281ff4a02	226	* @}
AnnaBridge	161:aa5281ff4a02	227	*/
AnnaBridge	161:aa5281ff4a02	228
AnnaBridge	161:aa5281ff4a02	229	/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
AnnaBridge	161:aa5281ff4a02	230	* @{
AnnaBridge	161:aa5281ff4a02	231	*/
AnnaBridge	161:aa5281ff4a02	232	#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /!<nCS stay high for at least 1 clock cycle between commands/
AnnaBridge	161:aa5281ff4a02	233	#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 2 clock cycles between commands/
AnnaBridge	161:aa5281ff4a02	234	#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 3 clock cycles between commands/
AnnaBridge	161:aa5281ff4a02	235	#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 4 clock cycles between commands/
AnnaBridge	161:aa5281ff4a02	236	#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /!<nCS stay high for at least 5 clock cycles between commands/
AnnaBridge	161:aa5281ff4a02	237	#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 6 clock cycles between commands/
AnnaBridge	161:aa5281ff4a02	238	#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 7 clock cycles between commands/
AnnaBridge	161:aa5281ff4a02	239	#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /!<nCS stay high for at least 8 clock cycles between commands/
AnnaBridge	161:aa5281ff4a02	240	/**
AnnaBridge	161:aa5281ff4a02	241	* @}
AnnaBridge	161:aa5281ff4a02	242	*/
AnnaBridge	161:aa5281ff4a02	243
AnnaBridge	161:aa5281ff4a02	244	/** @defgroup QSPI_ClockMode QSPI Clock Mode
AnnaBridge	161:aa5281ff4a02	245	* @{
AnnaBridge	161:aa5281ff4a02	246	*/
AnnaBridge	161:aa5281ff4a02	247	#define QSPI_CLOCK_MODE_0 0x00000000U /!<Clk stays low while nCS is released/
AnnaBridge	161:aa5281ff4a02	248	#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /!<Clk goes high while nCS is released/
AnnaBridge	161:aa5281ff4a02	249	/**
AnnaBridge	161:aa5281ff4a02	250	* @}
AnnaBridge	161:aa5281ff4a02	251	*/
AnnaBridge	161:aa5281ff4a02	252
AnnaBridge	161:aa5281ff4a02	253	/** @defgroup QSPI_Flash_Select QSPI Flash Select
AnnaBridge	161:aa5281ff4a02	254	* @{
AnnaBridge	161:aa5281ff4a02	255	*/
AnnaBridge	161:aa5281ff4a02	256	#define QSPI_FLASH_ID_1 0x00000000U
AnnaBridge	161:aa5281ff4a02	257	#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
AnnaBridge	161:aa5281ff4a02	258	/**
AnnaBridge	161:aa5281ff4a02	259	* @}
AnnaBridge	161:aa5281ff4a02	260	*/
AnnaBridge	161:aa5281ff4a02	261
AnnaBridge	161:aa5281ff4a02	262	/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
AnnaBridge	161:aa5281ff4a02	263	* @{
AnnaBridge	161:aa5281ff4a02	264	*/
AnnaBridge	161:aa5281ff4a02	265	#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
AnnaBridge	161:aa5281ff4a02	266	#define QSPI_DUALFLASH_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	267	/**
AnnaBridge	161:aa5281ff4a02	268	* @}
AnnaBridge	161:aa5281ff4a02	269	*/
AnnaBridge	161:aa5281ff4a02	270
AnnaBridge	161:aa5281ff4a02	271	/** @defgroup QSPI_AddressSize QSPI Address Size
AnnaBridge	161:aa5281ff4a02	272	* @{
AnnaBridge	161:aa5281ff4a02	273	*/
AnnaBridge	161:aa5281ff4a02	274	#define QSPI_ADDRESS_8_BITS 0x00000000U /!<8-bit address/
AnnaBridge	161:aa5281ff4a02	275	#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /!<16-bit address/
AnnaBridge	161:aa5281ff4a02	276	#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /!<24-bit address/
AnnaBridge	161:aa5281ff4a02	277	#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /!<32-bit address/
AnnaBridge	161:aa5281ff4a02	278	/**
AnnaBridge	161:aa5281ff4a02	279	* @}
AnnaBridge	161:aa5281ff4a02	280	*/
AnnaBridge	161:aa5281ff4a02	281
AnnaBridge	161:aa5281ff4a02	282	/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
AnnaBridge	161:aa5281ff4a02	283	* @{
AnnaBridge	161:aa5281ff4a02	284	*/
AnnaBridge	161:aa5281ff4a02	285	#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /!<8-bit alternate bytes/
AnnaBridge	161:aa5281ff4a02	286	#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /!<16-bit alternate bytes/
AnnaBridge	161:aa5281ff4a02	287	#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /!<24-bit alternate bytes/
AnnaBridge	161:aa5281ff4a02	288	#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /!<32-bit alternate bytes/
AnnaBridge	161:aa5281ff4a02	289	/**
AnnaBridge	161:aa5281ff4a02	290	* @}
AnnaBridge	161:aa5281ff4a02	291	*/
AnnaBridge	161:aa5281ff4a02	292
AnnaBridge	161:aa5281ff4a02	293	/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
AnnaBridge	161:aa5281ff4a02	294	* @{
AnnaBridge	161:aa5281ff4a02	295	*/
AnnaBridge	161:aa5281ff4a02	296	#define QSPI_INSTRUCTION_NONE 0x00000000U /!<No instruction/
AnnaBridge	161:aa5281ff4a02	297	#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /!<Instruction on a single line/
AnnaBridge	161:aa5281ff4a02	298	#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /!<Instruction on two lines/
AnnaBridge	161:aa5281ff4a02	299	#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /!<Instruction on four lines/
AnnaBridge	161:aa5281ff4a02	300	/**
AnnaBridge	161:aa5281ff4a02	301	* @}
AnnaBridge	161:aa5281ff4a02	302	*/
AnnaBridge	161:aa5281ff4a02	303
AnnaBridge	161:aa5281ff4a02	304	/** @defgroup QSPI_AddressMode QSPI Address Mode
AnnaBridge	161:aa5281ff4a02	305	* @{
AnnaBridge	161:aa5281ff4a02	306	*/
AnnaBridge	161:aa5281ff4a02	307	#define QSPI_ADDRESS_NONE 0x00000000U /!<No address/
AnnaBridge	161:aa5281ff4a02	308	#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /!<Address on a single line/
AnnaBridge	161:aa5281ff4a02	309	#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /!<Address on two lines/
AnnaBridge	161:aa5281ff4a02	310	#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /!<Address on four lines/
AnnaBridge	161:aa5281ff4a02	311	/**
AnnaBridge	161:aa5281ff4a02	312	* @}
AnnaBridge	161:aa5281ff4a02	313	*/
AnnaBridge	161:aa5281ff4a02	314
AnnaBridge	161:aa5281ff4a02	315	/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
AnnaBridge	161:aa5281ff4a02	316	* @{
AnnaBridge	161:aa5281ff4a02	317	*/
AnnaBridge	161:aa5281ff4a02	318	#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /!<No alternate bytes/
AnnaBridge	161:aa5281ff4a02	319	#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /!<Alternate bytes on a single line/
AnnaBridge	161:aa5281ff4a02	320	#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /!<Alternate bytes on two lines/
AnnaBridge	161:aa5281ff4a02	321	#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /!<Alternate bytes on four lines/
AnnaBridge	161:aa5281ff4a02	322	/**
AnnaBridge	161:aa5281ff4a02	323	* @}
AnnaBridge	161:aa5281ff4a02	324	*/
AnnaBridge	161:aa5281ff4a02	325
AnnaBridge	161:aa5281ff4a02	326	/** @defgroup QSPI_DataMode QSPI Data Mode
AnnaBridge	161:aa5281ff4a02	327	* @{
AnnaBridge	161:aa5281ff4a02	328	*/
AnnaBridge	161:aa5281ff4a02	329	#define QSPI_DATA_NONE 0x00000000U /!<No data/
AnnaBridge	161:aa5281ff4a02	330	#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /!<Data on a single line/
AnnaBridge	161:aa5281ff4a02	331	#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /!<Data on two lines/
AnnaBridge	161:aa5281ff4a02	332	#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /!<Data on four lines/
AnnaBridge	161:aa5281ff4a02	333	/**
AnnaBridge	161:aa5281ff4a02	334	* @}
AnnaBridge	161:aa5281ff4a02	335	*/
AnnaBridge	161:aa5281ff4a02	336
AnnaBridge	161:aa5281ff4a02	337	/** @defgroup QSPI_DdrMode QSPI Ddr Mode
AnnaBridge	161:aa5281ff4a02	338	* @{
AnnaBridge	161:aa5281ff4a02	339	*/
AnnaBridge	161:aa5281ff4a02	340	#define QSPI_DDR_MODE_DISABLE 0x00000000U /!<Double data rate mode disabled/
AnnaBridge	161:aa5281ff4a02	341	#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /!<Double data rate mode enabled/
AnnaBridge	161:aa5281ff4a02	342	/**
AnnaBridge	161:aa5281ff4a02	343	* @}
AnnaBridge	161:aa5281ff4a02	344	*/
AnnaBridge	161:aa5281ff4a02	345
AnnaBridge	161:aa5281ff4a02	346	/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
AnnaBridge	161:aa5281ff4a02	347	* @{
AnnaBridge	161:aa5281ff4a02	348	*/
AnnaBridge	161:aa5281ff4a02	349	#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /!<Delay the data output using analog delay in DDR mode/
AnnaBridge	161:aa5281ff4a02	350	#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /!<Delay the data output by 1/2 clock cycle in DDR mode/
AnnaBridge	161:aa5281ff4a02	351	/**
AnnaBridge	161:aa5281ff4a02	352	* @}
AnnaBridge	161:aa5281ff4a02	353	*/
AnnaBridge	161:aa5281ff4a02	354
AnnaBridge	161:aa5281ff4a02	355	/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
AnnaBridge	161:aa5281ff4a02	356	* @{
AnnaBridge	161:aa5281ff4a02	357	*/
AnnaBridge	161:aa5281ff4a02	358	#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /!<Send instruction on every transaction/
AnnaBridge	161:aa5281ff4a02	359	#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /!<Send instruction only for the first command/
AnnaBridge	161:aa5281ff4a02	360	/**
AnnaBridge	161:aa5281ff4a02	361	* @}
AnnaBridge	161:aa5281ff4a02	362	*/
AnnaBridge	161:aa5281ff4a02	363
AnnaBridge	161:aa5281ff4a02	364	/** @defgroup QSPI_MatchMode QSPI Match Mode
AnnaBridge	161:aa5281ff4a02	365	* @{
AnnaBridge	161:aa5281ff4a02	366	*/
AnnaBridge	161:aa5281ff4a02	367	#define QSPI_MATCH_MODE_AND 0x00000000U /!<AND match mode between unmasked bits/
AnnaBridge	161:aa5281ff4a02	368	#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /!<OR match mode between unmasked bits/
AnnaBridge	161:aa5281ff4a02	369	/**
AnnaBridge	161:aa5281ff4a02	370	* @}
AnnaBridge	161:aa5281ff4a02	371	*/
AnnaBridge	161:aa5281ff4a02	372
AnnaBridge	161:aa5281ff4a02	373	/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
AnnaBridge	161:aa5281ff4a02	374	* @{
AnnaBridge	161:aa5281ff4a02	375	*/
AnnaBridge	161:aa5281ff4a02	376	#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /!<AutoPolling stops only with abort or QSPI disabling/
AnnaBridge	161:aa5281ff4a02	377	#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /!<AutoPolling stops as soon as there is a match/
AnnaBridge	161:aa5281ff4a02	378	/**
AnnaBridge	161:aa5281ff4a02	379	* @}
AnnaBridge	161:aa5281ff4a02	380	*/
AnnaBridge	161:aa5281ff4a02	381
AnnaBridge	161:aa5281ff4a02	382	/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
AnnaBridge	161:aa5281ff4a02	383	* @{
AnnaBridge	161:aa5281ff4a02	384	*/
AnnaBridge	161:aa5281ff4a02	385	#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /!<Timeout counter disabled, nCS remains active/
AnnaBridge	161:aa5281ff4a02	386	#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /!<Timeout counter enabled, nCS released when timeout expires/
AnnaBridge	161:aa5281ff4a02	387	/**
AnnaBridge	161:aa5281ff4a02	388	* @}
AnnaBridge	161:aa5281ff4a02	389	*/
AnnaBridge	161:aa5281ff4a02	390
AnnaBridge	161:aa5281ff4a02	391	/** @defgroup QSPI_Flags QSPI Flags
AnnaBridge	161:aa5281ff4a02	392	* @{
AnnaBridge	161:aa5281ff4a02	393	*/
AnnaBridge	161:aa5281ff4a02	394	#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /!<Busy flag: operation is ongoing/
AnnaBridge	161:aa5281ff4a02	395	#define QSPI_FLAG_TO QUADSPI_SR_TOF /!<Timeout flag: timeout occurs in memory-mapped mode/
AnnaBridge	161:aa5281ff4a02	396	#define QSPI_FLAG_SM QUADSPI_SR_SMF /!<Status match flag: received data matches in autopolling mode/
AnnaBridge	161:aa5281ff4a02	397	#define QSPI_FLAG_FT QUADSPI_SR_FTF /!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete/
AnnaBridge	161:aa5281ff4a02	398	#define QSPI_FLAG_TC QUADSPI_SR_TCF /!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted/
AnnaBridge	161:aa5281ff4a02	399	#define QSPI_FLAG_TE QUADSPI_SR_TEF /!<Transfer error flag: invalid address is being accessed/
AnnaBridge	161:aa5281ff4a02	400	/**
AnnaBridge	161:aa5281ff4a02	401	* @}
AnnaBridge	161:aa5281ff4a02	402	*/
AnnaBridge	161:aa5281ff4a02	403
AnnaBridge	161:aa5281ff4a02	404	/** @defgroup QSPI_Interrupts QSPI Interrupts
AnnaBridge	161:aa5281ff4a02	405	* @{
AnnaBridge	161:aa5281ff4a02	406	*/
AnnaBridge	161:aa5281ff4a02	407	#define QSPI_IT_TO QUADSPI_CR_TOIE /!<Interrupt on the timeout flag/
AnnaBridge	161:aa5281ff4a02	408	#define QSPI_IT_SM QUADSPI_CR_SMIE /!<Interrupt on the status match flag/
AnnaBridge	161:aa5281ff4a02	409	#define QSPI_IT_FT QUADSPI_CR_FTIE /!<Interrupt on the fifo threshold flag/
AnnaBridge	161:aa5281ff4a02	410	#define QSPI_IT_TC QUADSPI_CR_TCIE /!<Interrupt on the transfer complete flag/
AnnaBridge	161:aa5281ff4a02	411	#define QSPI_IT_TE QUADSPI_CR_TEIE /!<Interrupt on the transfer error flag/
AnnaBridge	161:aa5281ff4a02	412	/**
AnnaBridge	161:aa5281ff4a02	413	* @}
AnnaBridge	161:aa5281ff4a02	414	*/
AnnaBridge	161:aa5281ff4a02	415
AnnaBridge	161:aa5281ff4a02	416	/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
AnnaBridge	161:aa5281ff4a02	417	* @{
AnnaBridge	161:aa5281ff4a02	418	*/
AnnaBridge	161:aa5281ff4a02	419	#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
AnnaBridge	161:aa5281ff4a02	420	/**
AnnaBridge	161:aa5281ff4a02	421	* @}
AnnaBridge	161:aa5281ff4a02	422	*/
AnnaBridge	161:aa5281ff4a02	423
AnnaBridge	161:aa5281ff4a02	424	/**
AnnaBridge	161:aa5281ff4a02	425	* @}
AnnaBridge	161:aa5281ff4a02	426	*/
AnnaBridge	161:aa5281ff4a02	427
AnnaBridge	161:aa5281ff4a02	428	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	429	/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
AnnaBridge	161:aa5281ff4a02	430	* @{
AnnaBridge	161:aa5281ff4a02	431	*/
AnnaBridge	161:aa5281ff4a02	432
AnnaBridge	161:aa5281ff4a02	433	/** @brief Reset QSPI handle state
AnnaBridge	163:e59c8e839560	434	* @param __HANDLE__ QSPI handle.
AnnaBridge	161:aa5281ff4a02	435	* @retval None
AnnaBridge	161:aa5281ff4a02	436	*/
AnnaBridge	161:aa5281ff4a02	437	#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
AnnaBridge	161:aa5281ff4a02	438
AnnaBridge	161:aa5281ff4a02	439	/** @brief Enable QSPI
AnnaBridge	163:e59c8e839560	440	* @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge	161:aa5281ff4a02	441	* @retval None
AnnaBridge	161:aa5281ff4a02	442	*/
AnnaBridge	161:aa5281ff4a02	443	#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge	161:aa5281ff4a02	444
AnnaBridge	161:aa5281ff4a02	445	/** @brief Disable QSPI
AnnaBridge	163:e59c8e839560	446	* @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge	161:aa5281ff4a02	447	* @retval None
AnnaBridge	161:aa5281ff4a02	448	*/
AnnaBridge	161:aa5281ff4a02	449	#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge	161:aa5281ff4a02	450
AnnaBridge	161:aa5281ff4a02	451	/** @brief Enables the specified QSPI interrupt.
AnnaBridge	163:e59c8e839560	452	* @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge	163:e59c8e839560	453	* @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
AnnaBridge	161:aa5281ff4a02	454	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	455	* @arg QSPI_IT_TO: QSPI Time out interrupt
AnnaBridge	161:aa5281ff4a02	456	* @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge	161:aa5281ff4a02	457	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge	161:aa5281ff4a02	458	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge	161:aa5281ff4a02	459	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge	161:aa5281ff4a02	460	* @retval None
AnnaBridge	161:aa5281ff4a02	461	*/
AnnaBridge	161:aa5281ff4a02	462	#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	463
AnnaBridge	161:aa5281ff4a02	464
AnnaBridge	161:aa5281ff4a02	465	/** @brief Disables the specified QSPI interrupt.
AnnaBridge	163:e59c8e839560	466	* @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge	163:e59c8e839560	467	* @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
AnnaBridge	161:aa5281ff4a02	468	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	469	* @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge	161:aa5281ff4a02	470	* @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge	161:aa5281ff4a02	471	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge	161:aa5281ff4a02	472	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge	161:aa5281ff4a02	473	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge	161:aa5281ff4a02	474	* @retval None
AnnaBridge	161:aa5281ff4a02	475	*/
AnnaBridge	161:aa5281ff4a02	476	#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	477
AnnaBridge	161:aa5281ff4a02	478	/** @brief Checks whether the specified QSPI interrupt source is enabled.
AnnaBridge	163:e59c8e839560	479	* @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge	163:e59c8e839560	480	* @param __INTERRUPT__ specifies the QSPI interrupt source to check.
AnnaBridge	161:aa5281ff4a02	481	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	482	* @arg QSPI_IT_TO: QSPI Time out interrupt
AnnaBridge	161:aa5281ff4a02	483	* @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge	161:aa5281ff4a02	484	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge	161:aa5281ff4a02	485	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge	161:aa5281ff4a02	486	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge	161:aa5281ff4a02	487	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	161:aa5281ff4a02	488	*/
AnnaBridge	161:aa5281ff4a02	489	#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	490
AnnaBridge	161:aa5281ff4a02	491	/**
AnnaBridge	161:aa5281ff4a02	492	* @brief Get the selected QSPI's flag status.
AnnaBridge	163:e59c8e839560	493	* @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge	163:e59c8e839560	494	* @param __FLAG__ specifies the QSPI flag to check.
AnnaBridge	161:aa5281ff4a02	495	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	496	* @arg QSPI_FLAG_BUSY: QSPI Busy flag
AnnaBridge	161:aa5281ff4a02	497	* @arg QSPI_FLAG_TO: QSPI Time out flag
AnnaBridge	161:aa5281ff4a02	498	* @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge	161:aa5281ff4a02	499	* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
AnnaBridge	161:aa5281ff4a02	500	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge	161:aa5281ff4a02	501	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge	161:aa5281ff4a02	502	* @retval None
AnnaBridge	161:aa5281ff4a02	503	*/
AnnaBridge	161:aa5281ff4a02	504	#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
AnnaBridge	161:aa5281ff4a02	505
AnnaBridge	161:aa5281ff4a02	506	/** @brief Clears the specified QSPI's flag status.
AnnaBridge	163:e59c8e839560	507	* @param __HANDLE__ specifies the QSPI Handle.
AnnaBridge	163:e59c8e839560	508	* @param __FLAG__ specifies the QSPI clear register flag that needs to be set
AnnaBridge	161:aa5281ff4a02	509	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	510	* @arg QSPI_FLAG_TO: QSPI Time out flag
AnnaBridge	161:aa5281ff4a02	511	* @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge	161:aa5281ff4a02	512	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge	161:aa5281ff4a02	513	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge	161:aa5281ff4a02	514	* @retval None
AnnaBridge	161:aa5281ff4a02	515	*/
AnnaBridge	161:aa5281ff4a02	516	#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
AnnaBridge	161:aa5281ff4a02	517	/**
AnnaBridge	161:aa5281ff4a02	518	* @}
AnnaBridge	161:aa5281ff4a02	519	*/
AnnaBridge	161:aa5281ff4a02	520
AnnaBridge	161:aa5281ff4a02	521	/* Exported functions --------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	522	/** @addtogroup QSPI_Exported_Functions
AnnaBridge	161:aa5281ff4a02	523	* @{
AnnaBridge	161:aa5281ff4a02	524	*/
AnnaBridge	161:aa5281ff4a02	525
AnnaBridge	161:aa5281ff4a02	526	/** @addtogroup QSPI_Exported_Functions_Group1
AnnaBridge	161:aa5281ff4a02	527	* @{
AnnaBridge	161:aa5281ff4a02	528	*/
AnnaBridge	161:aa5281ff4a02	529	/* Initialization/de-initialization functions ********************************/
AnnaBridge	161:aa5281ff4a02	530	HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	531	HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	532	void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	533	void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	534	/**
AnnaBridge	161:aa5281ff4a02	535	* @}
AnnaBridge	161:aa5281ff4a02	536	*/
AnnaBridge	161:aa5281ff4a02	537
AnnaBridge	161:aa5281ff4a02	538	/** @addtogroup QSPI_Exported_Functions_Group2
AnnaBridge	161:aa5281ff4a02	539	* @{
AnnaBridge	161:aa5281ff4a02	540	*/
AnnaBridge	161:aa5281ff4a02	541	/* IO operation functions *****************************************************/
AnnaBridge	161:aa5281ff4a02	542	/* QSPI IRQ handler method */
AnnaBridge	161:aa5281ff4a02	543	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	544
AnnaBridge	161:aa5281ff4a02	545	/* QSPI indirect mode */
AnnaBridge	161:aa5281ff4a02	546	HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	547	HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	548	HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	549	HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd);
AnnaBridge	161:aa5281ff4a02	550	HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
AnnaBridge	161:aa5281ff4a02	551	HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
AnnaBridge	161:aa5281ff4a02	552	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
AnnaBridge	161:aa5281ff4a02	553	HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
AnnaBridge	161:aa5281ff4a02	554
AnnaBridge	161:aa5281ff4a02	555	/* QSPI status flag polling mode */
AnnaBridge	161:aa5281ff4a02	556	HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	557	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg);
AnnaBridge	161:aa5281ff4a02	558
AnnaBridge	161:aa5281ff4a02	559	/* QSPI memory-mapped mode */
AnnaBridge	161:aa5281ff4a02	560	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg);
AnnaBridge	161:aa5281ff4a02	561	/**
AnnaBridge	161:aa5281ff4a02	562	* @}
AnnaBridge	161:aa5281ff4a02	563	*/
AnnaBridge	161:aa5281ff4a02	564
AnnaBridge	161:aa5281ff4a02	565	/** @addtogroup QSPI_Exported_Functions_Group3
AnnaBridge	161:aa5281ff4a02	566	* @{
AnnaBridge	161:aa5281ff4a02	567	*/
AnnaBridge	161:aa5281ff4a02	568	/* Callback functions in non-blocking modes ***********************************/
AnnaBridge	161:aa5281ff4a02	569	void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	570	void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	571	void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	572
AnnaBridge	161:aa5281ff4a02	573	/* QSPI indirect mode */
AnnaBridge	161:aa5281ff4a02	574	void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	575	void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	576	void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	577	void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	578	void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	579
AnnaBridge	161:aa5281ff4a02	580	/* QSPI status flag polling mode */
AnnaBridge	161:aa5281ff4a02	581	void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	582
AnnaBridge	161:aa5281ff4a02	583	/* QSPI memory-mapped mode */
AnnaBridge	161:aa5281ff4a02	584	void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	585	/**
AnnaBridge	161:aa5281ff4a02	586	* @}
AnnaBridge	161:aa5281ff4a02	587	*/
AnnaBridge	161:aa5281ff4a02	588
AnnaBridge	161:aa5281ff4a02	589	/** @addtogroup QSPI_Exported_Functions_Group4
AnnaBridge	161:aa5281ff4a02	590	* @{
AnnaBridge	161:aa5281ff4a02	591	*/
AnnaBridge	161:aa5281ff4a02	592	/* Peripheral Control and State functions ************************************/
AnnaBridge	161:aa5281ff4a02	593	HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	594	uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	595	HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	596	HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	597	void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
AnnaBridge	161:aa5281ff4a02	598	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
AnnaBridge	161:aa5281ff4a02	599	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
AnnaBridge	161:aa5281ff4a02	600	/**
AnnaBridge	161:aa5281ff4a02	601	* @}
AnnaBridge	161:aa5281ff4a02	602	*/
AnnaBridge	161:aa5281ff4a02	603
AnnaBridge	161:aa5281ff4a02	604	/* Private macros ------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	605	/** @defgroup QSPI_Private_Macros QSPI Private Macros
AnnaBridge	161:aa5281ff4a02	606	* @{
AnnaBridge	161:aa5281ff4a02	607	*/
AnnaBridge	161:aa5281ff4a02	608	/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
AnnaBridge	161:aa5281ff4a02	609	* @{
AnnaBridge	161:aa5281ff4a02	610	*/
AnnaBridge	161:aa5281ff4a02	611	#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
AnnaBridge	161:aa5281ff4a02	612	/**
AnnaBridge	161:aa5281ff4a02	613	* @}
AnnaBridge	161:aa5281ff4a02	614	*/
AnnaBridge	161:aa5281ff4a02	615
AnnaBridge	161:aa5281ff4a02	616	/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
AnnaBridge	161:aa5281ff4a02	617	* @{
AnnaBridge	161:aa5281ff4a02	618	*/
AnnaBridge	161:aa5281ff4a02	619	#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
AnnaBridge	161:aa5281ff4a02	620	/**
AnnaBridge	161:aa5281ff4a02	621	* @}
AnnaBridge	161:aa5281ff4a02	622	*/
AnnaBridge	161:aa5281ff4a02	623
AnnaBridge	161:aa5281ff4a02	624	#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) \|\| \
AnnaBridge	161:aa5281ff4a02	625	((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
AnnaBridge	161:aa5281ff4a02	626
AnnaBridge	161:aa5281ff4a02	627	/** @defgroup QSPI_FlashSize QSPI Flash Size
AnnaBridge	161:aa5281ff4a02	628	* @{
AnnaBridge	161:aa5281ff4a02	629	*/
AnnaBridge	161:aa5281ff4a02	630	#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
AnnaBridge	161:aa5281ff4a02	631	/**
AnnaBridge	161:aa5281ff4a02	632	* @}
AnnaBridge	161:aa5281ff4a02	633	*/
AnnaBridge	161:aa5281ff4a02	634
AnnaBridge	161:aa5281ff4a02	635	#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) \|\| \
AnnaBridge	161:aa5281ff4a02	636	((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) \|\| \
AnnaBridge	161:aa5281ff4a02	637	((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) \|\| \
AnnaBridge	161:aa5281ff4a02	638	((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) \|\| \
AnnaBridge	161:aa5281ff4a02	639	((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) \|\| \
AnnaBridge	161:aa5281ff4a02	640	((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) \|\| \
AnnaBridge	161:aa5281ff4a02	641	((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) \|\| \
AnnaBridge	161:aa5281ff4a02	642	((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
AnnaBridge	161:aa5281ff4a02	643
AnnaBridge	161:aa5281ff4a02	644	#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) \|\| \
AnnaBridge	161:aa5281ff4a02	645	((CLKMODE) == QSPI_CLOCK_MODE_3))
AnnaBridge	161:aa5281ff4a02	646
AnnaBridge	161:aa5281ff4a02	647	#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) \|\| \
AnnaBridge	161:aa5281ff4a02	648	((FLA) == QSPI_FLASH_ID_2))
AnnaBridge	161:aa5281ff4a02	649
AnnaBridge	161:aa5281ff4a02	650	#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	651	((MODE) == QSPI_DUALFLASH_DISABLE))
AnnaBridge	161:aa5281ff4a02	652
AnnaBridge	161:aa5281ff4a02	653
AnnaBridge	161:aa5281ff4a02	654	/** @defgroup QSPI_Instruction QSPI Instruction
AnnaBridge	161:aa5281ff4a02	655	* @{
AnnaBridge	161:aa5281ff4a02	656	*/
AnnaBridge	161:aa5281ff4a02	657	#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
AnnaBridge	161:aa5281ff4a02	658	/**
AnnaBridge	161:aa5281ff4a02	659	* @}
AnnaBridge	161:aa5281ff4a02	660	*/
AnnaBridge	161:aa5281ff4a02	661
AnnaBridge	161:aa5281ff4a02	662	#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) \|\| \
AnnaBridge	161:aa5281ff4a02	663	((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) \|\| \
AnnaBridge	161:aa5281ff4a02	664	((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) \|\| \
AnnaBridge	161:aa5281ff4a02	665	((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
AnnaBridge	161:aa5281ff4a02	666
AnnaBridge	161:aa5281ff4a02	667	#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) \|\| \
AnnaBridge	161:aa5281ff4a02	668	((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) \|\| \
AnnaBridge	161:aa5281ff4a02	669	((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) \|\| \
AnnaBridge	161:aa5281ff4a02	670	((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
AnnaBridge	161:aa5281ff4a02	671
AnnaBridge	161:aa5281ff4a02	672
AnnaBridge	161:aa5281ff4a02	673	/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
AnnaBridge	161:aa5281ff4a02	674	* @{
AnnaBridge	161:aa5281ff4a02	675	*/
AnnaBridge	161:aa5281ff4a02	676	#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
AnnaBridge	161:aa5281ff4a02	677	/**
AnnaBridge	161:aa5281ff4a02	678	* @}
AnnaBridge	161:aa5281ff4a02	679	*/
AnnaBridge	161:aa5281ff4a02	680
AnnaBridge	161:aa5281ff4a02	681	#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) \|\| \
AnnaBridge	161:aa5281ff4a02	682	((MODE) == QSPI_INSTRUCTION_1_LINE) \|\| \
AnnaBridge	161:aa5281ff4a02	683	((MODE) == QSPI_INSTRUCTION_2_LINES) \|\| \
AnnaBridge	161:aa5281ff4a02	684	((MODE) == QSPI_INSTRUCTION_4_LINES))
AnnaBridge	161:aa5281ff4a02	685
AnnaBridge	161:aa5281ff4a02	686	#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) \|\| \
AnnaBridge	161:aa5281ff4a02	687	((MODE) == QSPI_ADDRESS_1_LINE) \|\| \
AnnaBridge	161:aa5281ff4a02	688	((MODE) == QSPI_ADDRESS_2_LINES) \|\| \
AnnaBridge	161:aa5281ff4a02	689	((MODE) == QSPI_ADDRESS_4_LINES))
AnnaBridge	161:aa5281ff4a02	690
AnnaBridge	161:aa5281ff4a02	691	#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) \|\| \
AnnaBridge	161:aa5281ff4a02	692	((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) \|\| \
AnnaBridge	161:aa5281ff4a02	693	((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) \|\| \
AnnaBridge	161:aa5281ff4a02	694	((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
AnnaBridge	161:aa5281ff4a02	695
AnnaBridge	161:aa5281ff4a02	696	#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) \|\| \
AnnaBridge	161:aa5281ff4a02	697	((MODE) == QSPI_DATA_1_LINE) \|\| \
AnnaBridge	161:aa5281ff4a02	698	((MODE) == QSPI_DATA_2_LINES) \|\| \
AnnaBridge	161:aa5281ff4a02	699	((MODE) == QSPI_DATA_4_LINES))
AnnaBridge	161:aa5281ff4a02	700
AnnaBridge	161:aa5281ff4a02	701	#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	702	((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
AnnaBridge	161:aa5281ff4a02	703
AnnaBridge	161:aa5281ff4a02	704	#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) \|\| \
AnnaBridge	161:aa5281ff4a02	705	((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
AnnaBridge	161:aa5281ff4a02	706
AnnaBridge	161:aa5281ff4a02	707	#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) \|\| \
AnnaBridge	161:aa5281ff4a02	708	((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
AnnaBridge	161:aa5281ff4a02	709
AnnaBridge	161:aa5281ff4a02	710	/** @defgroup QSPI_Interval QSPI Interval
AnnaBridge	161:aa5281ff4a02	711	* @{
AnnaBridge	161:aa5281ff4a02	712	*/
AnnaBridge	161:aa5281ff4a02	713	#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
AnnaBridge	161:aa5281ff4a02	714	/**
AnnaBridge	161:aa5281ff4a02	715	* @}
AnnaBridge	161:aa5281ff4a02	716	*/
AnnaBridge	161:aa5281ff4a02	717
AnnaBridge	161:aa5281ff4a02	718	/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
AnnaBridge	161:aa5281ff4a02	719	* @{
AnnaBridge	161:aa5281ff4a02	720	*/
AnnaBridge	161:aa5281ff4a02	721	#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
AnnaBridge	161:aa5281ff4a02	722	/**
AnnaBridge	161:aa5281ff4a02	723	* @}
AnnaBridge	161:aa5281ff4a02	724	*/
AnnaBridge	161:aa5281ff4a02	725	#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) \|\| \
AnnaBridge	161:aa5281ff4a02	726	((MODE) == QSPI_MATCH_MODE_OR))
AnnaBridge	161:aa5281ff4a02	727
AnnaBridge	161:aa5281ff4a02	728	#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	729	((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
AnnaBridge	161:aa5281ff4a02	730
AnnaBridge	161:aa5281ff4a02	731	#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) \|\| \
AnnaBridge	161:aa5281ff4a02	732	((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
AnnaBridge	161:aa5281ff4a02	733
AnnaBridge	161:aa5281ff4a02	734	/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
AnnaBridge	161:aa5281ff4a02	735	* @{
AnnaBridge	161:aa5281ff4a02	736	*/
AnnaBridge	161:aa5281ff4a02	737	#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
AnnaBridge	161:aa5281ff4a02	738	/**
AnnaBridge	161:aa5281ff4a02	739	* @}
AnnaBridge	161:aa5281ff4a02	740	*/
AnnaBridge	161:aa5281ff4a02	741
AnnaBridge	161:aa5281ff4a02	742	#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) \|\| \
AnnaBridge	161:aa5281ff4a02	743	((FLAG) == QSPI_FLAG_TO) \|\| \
AnnaBridge	161:aa5281ff4a02	744	((FLAG) == QSPI_FLAG_SM) \|\| \
AnnaBridge	161:aa5281ff4a02	745	((FLAG) == QSPI_FLAG_FT) \|\| \
AnnaBridge	161:aa5281ff4a02	746	((FLAG) == QSPI_FLAG_TC) \|\| \
AnnaBridge	161:aa5281ff4a02	747	((FLAG) == QSPI_FLAG_TE))
AnnaBridge	161:aa5281ff4a02	748
AnnaBridge	161:aa5281ff4a02	749	#define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
AnnaBridge	161:aa5281ff4a02	750	/**
AnnaBridge	161:aa5281ff4a02	751	* @}
AnnaBridge	161:aa5281ff4a02	752	*/
AnnaBridge	161:aa5281ff4a02	753
AnnaBridge	161:aa5281ff4a02	754	/* Private functions ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	755	/** @defgroup QSPI_Private_Functions QSPI Private Functions
AnnaBridge	161:aa5281ff4a02	756	* @{
AnnaBridge	161:aa5281ff4a02	757	*/
AnnaBridge	161:aa5281ff4a02	758
AnnaBridge	161:aa5281ff4a02	759	/**
AnnaBridge	161:aa5281ff4a02	760	* @}
AnnaBridge	161:aa5281ff4a02	761	*/
AnnaBridge	161:aa5281ff4a02	762
AnnaBridge	161:aa5281ff4a02	763	/**
AnnaBridge	161:aa5281ff4a02	764	* @}
AnnaBridge	161:aa5281ff4a02	765	*/
AnnaBridge	161:aa5281ff4a02	766
AnnaBridge	161:aa5281ff4a02	767	/**
AnnaBridge	161:aa5281ff4a02	768	* @}
AnnaBridge	161:aa5281ff4a02	769	*/
AnnaBridge	161:aa5281ff4a02	770
AnnaBridge	161:aa5281ff4a02	771	/**
AnnaBridge	161:aa5281ff4a02	772	* @}
AnnaBridge	161:aa5281ff4a02	773	*/
AnnaBridge	161:aa5281ff4a02	774	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\|
AnnaBridge	161:aa5281ff4a02	775	STM32F413xx \|\| STM32F423xx */
AnnaBridge	161:aa5281ff4a02	776
AnnaBridge	161:aa5281ff4a02	777	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	778	}
AnnaBridge	161:aa5281ff4a02	779	#endif
AnnaBridge	161:aa5281ff4a02	780
AnnaBridge	161:aa5281ff4a02	781	#endif /* __STM32F4xx_HAL_QSPI_H */
AnnaBridge	161:aa5281ff4a02	782
AnnaBridge	161:aa5281ff4a02	783	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/