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TARGET_RO359B/TOOLCHAIN_IAR/fsl_gpio.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 143:86740a56073b | 1 | /* |
| AnnaBridge | 143:86740a56073b | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| AnnaBridge | 143:86740a56073b | 3 | * Copyright 2016-2017 NXP |
| AnnaBridge | 143:86740a56073b | 4 | * |
| AnnaBridge | 143:86740a56073b | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 143:86740a56073b | 6 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 143:86740a56073b | 7 | * |
| AnnaBridge | 143:86740a56073b | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| AnnaBridge | 143:86740a56073b | 9 | * of conditions and the following disclaimer. |
| AnnaBridge | 143:86740a56073b | 10 | * |
| AnnaBridge | 143:86740a56073b | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| AnnaBridge | 143:86740a56073b | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| AnnaBridge | 143:86740a56073b | 13 | * other materials provided with the distribution. |
| AnnaBridge | 143:86740a56073b | 14 | * |
| AnnaBridge | 143:86740a56073b | 15 | * o Neither the name of the copyright holder nor the names of its |
| AnnaBridge | 143:86740a56073b | 16 | * contributors may be used to endorse or promote products derived from this |
| AnnaBridge | 143:86740a56073b | 17 | * software without specific prior written permission. |
| AnnaBridge | 143:86740a56073b | 18 | * |
| AnnaBridge | 143:86740a56073b | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| AnnaBridge | 143:86740a56073b | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| AnnaBridge | 143:86740a56073b | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 143:86740a56073b | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| AnnaBridge | 143:86740a56073b | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 143:86740a56073b | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| AnnaBridge | 143:86740a56073b | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| AnnaBridge | 143:86740a56073b | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| AnnaBridge | 143:86740a56073b | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| AnnaBridge | 143:86740a56073b | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 143:86740a56073b | 29 | */ |
| AnnaBridge | 143:86740a56073b | 30 | |
| AnnaBridge | 143:86740a56073b | 31 | #ifndef _FSL_GPIO_H_ |
| AnnaBridge | 143:86740a56073b | 32 | #define _FSL_GPIO_H_ |
| AnnaBridge | 143:86740a56073b | 33 | |
| AnnaBridge | 143:86740a56073b | 34 | #include "fsl_common.h" |
| AnnaBridge | 143:86740a56073b | 35 | |
| AnnaBridge | 143:86740a56073b | 36 | /*! |
| AnnaBridge | 143:86740a56073b | 37 | * @addtogroup gpio |
| AnnaBridge | 143:86740a56073b | 38 | * @{ |
| AnnaBridge | 143:86740a56073b | 39 | */ |
| AnnaBridge | 143:86740a56073b | 40 | |
| AnnaBridge | 143:86740a56073b | 41 | /******************************************************************************* |
| AnnaBridge | 143:86740a56073b | 42 | * Definitions |
| AnnaBridge | 143:86740a56073b | 43 | ******************************************************************************/ |
| AnnaBridge | 143:86740a56073b | 44 | |
| AnnaBridge | 143:86740a56073b | 45 | /*! @name Driver version */ |
| AnnaBridge | 143:86740a56073b | 46 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 47 | /*! @brief GPIO driver version 2.1.1. */ |
| AnnaBridge | 143:86740a56073b | 48 | #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) |
| AnnaBridge | 143:86740a56073b | 49 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 50 | |
| AnnaBridge | 143:86740a56073b | 51 | /*! @brief GPIO direction definition */ |
| AnnaBridge | 143:86740a56073b | 52 | typedef enum _gpio_pin_direction |
| AnnaBridge | 143:86740a56073b | 53 | { |
| AnnaBridge | 143:86740a56073b | 54 | kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ |
| AnnaBridge | 143:86740a56073b | 55 | kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ |
| AnnaBridge | 143:86740a56073b | 56 | } gpio_pin_direction_t; |
| AnnaBridge | 143:86740a56073b | 57 | |
| AnnaBridge | 143:86740a56073b | 58 | #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER |
| AnnaBridge | 143:86740a56073b | 59 | /*! @brief GPIO checker attribute */ |
| AnnaBridge | 143:86740a56073b | 60 | typedef enum _gpio_checker_attribute |
| AnnaBridge | 143:86740a56073b | 61 | { |
| AnnaBridge | 143:86740a56073b | 62 | kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = |
| AnnaBridge | 143:86740a56073b | 63 | 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ |
| AnnaBridge | 143:86740a56073b | 64 | kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = |
| AnnaBridge | 143:86740a56073b | 65 | 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ |
| AnnaBridge | 143:86740a56073b | 66 | kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = |
| AnnaBridge | 143:86740a56073b | 67 | 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ |
| AnnaBridge | 143:86740a56073b | 68 | kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = |
| AnnaBridge | 143:86740a56073b | 69 | 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ |
| AnnaBridge | 143:86740a56073b | 70 | kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = |
| AnnaBridge | 143:86740a56073b | 71 | 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ |
| AnnaBridge | 143:86740a56073b | 72 | kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = |
| AnnaBridge | 143:86740a56073b | 73 | 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ |
| AnnaBridge | 143:86740a56073b | 74 | kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = |
| AnnaBridge | 143:86740a56073b | 75 | 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ |
| AnnaBridge | 143:86740a56073b | 76 | kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = |
| AnnaBridge | 143:86740a56073b | 77 | 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ |
| AnnaBridge | 143:86740a56073b | 78 | kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */ |
| AnnaBridge | 143:86740a56073b | 79 | } gpio_checker_attribute_t; |
| AnnaBridge | 143:86740a56073b | 80 | #endif |
| AnnaBridge | 143:86740a56073b | 81 | |
| AnnaBridge | 143:86740a56073b | 82 | /*! |
| AnnaBridge | 143:86740a56073b | 83 | * @brief The GPIO pin configuration structure. |
| AnnaBridge | 143:86740a56073b | 84 | * |
| AnnaBridge | 143:86740a56073b | 85 | * Each pin can only be configured as either an output pin or an input pin at a time. |
| AnnaBridge | 143:86740a56073b | 86 | * If configured as an input pin, leave the outputConfig unused. |
| AnnaBridge | 143:86740a56073b | 87 | * Note that in some use cases, the corresponding port property should be configured in advance |
| AnnaBridge | 143:86740a56073b | 88 | * with the PORT_SetPinConfig(). |
| AnnaBridge | 143:86740a56073b | 89 | */ |
| AnnaBridge | 143:86740a56073b | 90 | typedef struct _gpio_pin_config |
| AnnaBridge | 143:86740a56073b | 91 | { |
| AnnaBridge | 143:86740a56073b | 92 | gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ |
| AnnaBridge | 143:86740a56073b | 93 | /* Output configurations; ignore if configured as an input pin */ |
| AnnaBridge | 143:86740a56073b | 94 | uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ |
| AnnaBridge | 143:86740a56073b | 95 | } gpio_pin_config_t; |
| AnnaBridge | 143:86740a56073b | 96 | |
| AnnaBridge | 143:86740a56073b | 97 | /*! @} */ |
| AnnaBridge | 143:86740a56073b | 98 | |
| AnnaBridge | 143:86740a56073b | 99 | /******************************************************************************* |
| AnnaBridge | 143:86740a56073b | 100 | * API |
| AnnaBridge | 143:86740a56073b | 101 | ******************************************************************************/ |
| AnnaBridge | 143:86740a56073b | 102 | |
| AnnaBridge | 143:86740a56073b | 103 | #if defined(__cplusplus) |
| AnnaBridge | 143:86740a56073b | 104 | extern "C" { |
| AnnaBridge | 143:86740a56073b | 105 | #endif |
| AnnaBridge | 143:86740a56073b | 106 | |
| AnnaBridge | 143:86740a56073b | 107 | /*! |
| AnnaBridge | 143:86740a56073b | 108 | * @addtogroup gpio_driver |
| AnnaBridge | 143:86740a56073b | 109 | * @{ |
| AnnaBridge | 143:86740a56073b | 110 | */ |
| AnnaBridge | 143:86740a56073b | 111 | |
| AnnaBridge | 143:86740a56073b | 112 | /*! @name GPIO Configuration */ |
| AnnaBridge | 143:86740a56073b | 113 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 114 | |
| AnnaBridge | 143:86740a56073b | 115 | /*! |
| AnnaBridge | 143:86740a56073b | 116 | * @brief Initializes a GPIO pin used by the board. |
| AnnaBridge | 143:86740a56073b | 117 | * |
| AnnaBridge | 143:86740a56073b | 118 | * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. |
| AnnaBridge | 143:86740a56073b | 119 | * Then, call the GPIO_PinInit() function. |
| AnnaBridge | 143:86740a56073b | 120 | * |
| AnnaBridge | 143:86740a56073b | 121 | * This is an example to define an input pin or an output pin configuration. |
| AnnaBridge | 143:86740a56073b | 122 | * @code |
| AnnaBridge | 143:86740a56073b | 123 | * // Define a digital input pin configuration, |
| AnnaBridge | 143:86740a56073b | 124 | * gpio_pin_config_t config = |
| AnnaBridge | 143:86740a56073b | 125 | * { |
| AnnaBridge | 143:86740a56073b | 126 | * kGPIO_DigitalInput, |
| AnnaBridge | 143:86740a56073b | 127 | * 0, |
| AnnaBridge | 143:86740a56073b | 128 | * } |
| AnnaBridge | 143:86740a56073b | 129 | * //Define a digital output pin configuration, |
| AnnaBridge | 143:86740a56073b | 130 | * gpio_pin_config_t config = |
| AnnaBridge | 143:86740a56073b | 131 | * { |
| AnnaBridge | 143:86740a56073b | 132 | * kGPIO_DigitalOutput, |
| AnnaBridge | 143:86740a56073b | 133 | * 0, |
| AnnaBridge | 143:86740a56073b | 134 | * } |
| AnnaBridge | 143:86740a56073b | 135 | * @endcode |
| AnnaBridge | 143:86740a56073b | 136 | * |
| AnnaBridge | 143:86740a56073b | 137 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 138 | * @param pin GPIO port pin number |
| AnnaBridge | 143:86740a56073b | 139 | * @param config GPIO pin configuration pointer |
| AnnaBridge | 143:86740a56073b | 140 | */ |
| AnnaBridge | 143:86740a56073b | 141 | void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); |
| AnnaBridge | 143:86740a56073b | 142 | |
| AnnaBridge | 143:86740a56073b | 143 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 144 | |
| AnnaBridge | 143:86740a56073b | 145 | /*! @name GPIO Output Operations */ |
| AnnaBridge | 143:86740a56073b | 146 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 147 | |
| AnnaBridge | 143:86740a56073b | 148 | /*! |
| AnnaBridge | 143:86740a56073b | 149 | * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. |
| AnnaBridge | 143:86740a56073b | 150 | * |
| AnnaBridge | 143:86740a56073b | 151 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 152 | * @param pin GPIO pin number |
| AnnaBridge | 143:86740a56073b | 153 | * @param output GPIO pin output logic level. |
| AnnaBridge | 143:86740a56073b | 154 | * - 0: corresponding pin output low-logic level. |
| AnnaBridge | 143:86740a56073b | 155 | * - 1: corresponding pin output high-logic level. |
| AnnaBridge | 143:86740a56073b | 156 | */ |
| AnnaBridge | 143:86740a56073b | 157 | static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) |
| AnnaBridge | 143:86740a56073b | 158 | { |
| AnnaBridge | 143:86740a56073b | 159 | if (output == 0U) |
| AnnaBridge | 143:86740a56073b | 160 | { |
| AnnaBridge | 143:86740a56073b | 161 | base->PCOR = 1U << pin; |
| AnnaBridge | 143:86740a56073b | 162 | } |
| AnnaBridge | 143:86740a56073b | 163 | else |
| AnnaBridge | 143:86740a56073b | 164 | { |
| AnnaBridge | 143:86740a56073b | 165 | base->PSOR = 1U << pin; |
| AnnaBridge | 143:86740a56073b | 166 | } |
| AnnaBridge | 143:86740a56073b | 167 | } |
| AnnaBridge | 143:86740a56073b | 168 | |
| AnnaBridge | 143:86740a56073b | 169 | /*! |
| AnnaBridge | 143:86740a56073b | 170 | * @brief Sets the output level of the multiple GPIO pins to the logic 1. |
| AnnaBridge | 143:86740a56073b | 171 | * |
| AnnaBridge | 143:86740a56073b | 172 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 173 | * @param mask GPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 174 | */ |
| AnnaBridge | 143:86740a56073b | 175 | static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) |
| AnnaBridge | 143:86740a56073b | 176 | { |
| AnnaBridge | 143:86740a56073b | 177 | base->PSOR = mask; |
| AnnaBridge | 143:86740a56073b | 178 | } |
| AnnaBridge | 143:86740a56073b | 179 | |
| AnnaBridge | 143:86740a56073b | 180 | /*! |
| AnnaBridge | 143:86740a56073b | 181 | * @brief Sets the output level of the multiple GPIO pins to the logic 0. |
| AnnaBridge | 143:86740a56073b | 182 | * |
| AnnaBridge | 143:86740a56073b | 183 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 184 | * @param mask GPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 185 | */ |
| AnnaBridge | 143:86740a56073b | 186 | static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) |
| AnnaBridge | 143:86740a56073b | 187 | { |
| AnnaBridge | 143:86740a56073b | 188 | base->PCOR = mask; |
| AnnaBridge | 143:86740a56073b | 189 | } |
| AnnaBridge | 143:86740a56073b | 190 | |
| AnnaBridge | 143:86740a56073b | 191 | /*! |
| AnnaBridge | 143:86740a56073b | 192 | * @brief Reverses the current output logic of the multiple GPIO pins. |
| AnnaBridge | 143:86740a56073b | 193 | * |
| AnnaBridge | 143:86740a56073b | 194 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 195 | * @param mask GPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 196 | */ |
| AnnaBridge | 143:86740a56073b | 197 | static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) |
| AnnaBridge | 143:86740a56073b | 198 | { |
| AnnaBridge | 143:86740a56073b | 199 | base->PTOR = mask; |
| AnnaBridge | 143:86740a56073b | 200 | } |
| AnnaBridge | 143:86740a56073b | 201 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 202 | |
| AnnaBridge | 143:86740a56073b | 203 | /*! @name GPIO Input Operations */ |
| AnnaBridge | 143:86740a56073b | 204 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 205 | |
| AnnaBridge | 143:86740a56073b | 206 | /*! |
| AnnaBridge | 143:86740a56073b | 207 | * @brief Reads the current input value of the GPIO port. |
| AnnaBridge | 143:86740a56073b | 208 | * |
| AnnaBridge | 143:86740a56073b | 209 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 210 | * @param pin GPIO pin number |
| AnnaBridge | 143:86740a56073b | 211 | * @retval GPIO port input value |
| AnnaBridge | 143:86740a56073b | 212 | * - 0: corresponding pin input low-logic level. |
| AnnaBridge | 143:86740a56073b | 213 | * - 1: corresponding pin input high-logic level. |
| AnnaBridge | 143:86740a56073b | 214 | */ |
| AnnaBridge | 143:86740a56073b | 215 | static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) |
| AnnaBridge | 143:86740a56073b | 216 | { |
| AnnaBridge | 143:86740a56073b | 217 | return (((base->PDIR) >> pin) & 0x01U); |
| AnnaBridge | 143:86740a56073b | 218 | } |
| AnnaBridge | 143:86740a56073b | 219 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 220 | |
| AnnaBridge | 143:86740a56073b | 221 | /*! @name GPIO Interrupt */ |
| AnnaBridge | 143:86740a56073b | 222 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 223 | |
| AnnaBridge | 143:86740a56073b | 224 | /*! |
| AnnaBridge | 143:86740a56073b | 225 | * @brief Reads the GPIO port interrupt status flag. |
| AnnaBridge | 143:86740a56073b | 226 | * |
| AnnaBridge | 143:86740a56073b | 227 | * If a pin is configured to generate the DMA request, the corresponding flag |
| AnnaBridge | 143:86740a56073b | 228 | * is cleared automatically at the completion of the requested DMA transfer. |
| AnnaBridge | 143:86740a56073b | 229 | * Otherwise, the flag remains set until a logic one is written to that flag. |
| AnnaBridge | 143:86740a56073b | 230 | * If configured for a level sensitive interrupt that remains asserted, the flag |
| AnnaBridge | 143:86740a56073b | 231 | * is set again immediately. |
| AnnaBridge | 143:86740a56073b | 232 | * |
| AnnaBridge | 143:86740a56073b | 233 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 234 | * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the |
| AnnaBridge | 143:86740a56073b | 235 | * pin 0 and 17 have the interrupt. |
| AnnaBridge | 143:86740a56073b | 236 | */ |
| AnnaBridge | 143:86740a56073b | 237 | uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); |
| AnnaBridge | 143:86740a56073b | 238 | |
| AnnaBridge | 143:86740a56073b | 239 | /*! |
| AnnaBridge | 143:86740a56073b | 240 | * @brief Clears multiple GPIO pin interrupt status flags. |
| AnnaBridge | 143:86740a56073b | 241 | * |
| AnnaBridge | 143:86740a56073b | 242 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 243 | * @param mask GPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 244 | */ |
| AnnaBridge | 143:86740a56073b | 245 | void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); |
| AnnaBridge | 143:86740a56073b | 246 | |
| AnnaBridge | 143:86740a56073b | 247 | #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER |
| AnnaBridge | 143:86740a56073b | 248 | /*! |
| AnnaBridge | 143:86740a56073b | 249 | * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit |
| AnnaBridge | 143:86740a56073b | 250 | * words. Each 32-bit data port includes a GACR register, which defines the byte-level |
| AnnaBridge | 143:86740a56073b | 251 | * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data |
| AnnaBridge | 143:86740a56073b | 252 | * bytes in the GACR follow a standard little endian |
| AnnaBridge | 143:86740a56073b | 253 | * data convention. |
| AnnaBridge | 143:86740a56073b | 254 | * |
| AnnaBridge | 143:86740a56073b | 255 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 256 | * @param mask GPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 257 | */ |
| AnnaBridge | 143:86740a56073b | 258 | void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); |
| AnnaBridge | 143:86740a56073b | 259 | #endif |
| AnnaBridge | 143:86740a56073b | 260 | |
| AnnaBridge | 143:86740a56073b | 261 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 262 | /*! @} */ |
| AnnaBridge | 143:86740a56073b | 263 | |
| AnnaBridge | 143:86740a56073b | 264 | /*! |
| AnnaBridge | 143:86740a56073b | 265 | * @addtogroup fgpio_driver |
| AnnaBridge | 143:86740a56073b | 266 | * @{ |
| AnnaBridge | 143:86740a56073b | 267 | */ |
| AnnaBridge | 143:86740a56073b | 268 | |
| AnnaBridge | 143:86740a56073b | 269 | /* |
| AnnaBridge | 143:86740a56073b | 270 | * Introduces the FGPIO feature. |
| AnnaBridge | 143:86740a56073b | 271 | * |
| AnnaBridge | 143:86740a56073b | 272 | * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT |
| AnnaBridge | 143:86740a56073b | 273 | * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and |
| AnnaBridge | 143:86740a56073b | 274 | * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. |
| AnnaBridge | 143:86740a56073b | 275 | */ |
| AnnaBridge | 143:86740a56073b | 276 | |
| AnnaBridge | 143:86740a56073b | 277 | #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT |
| AnnaBridge | 143:86740a56073b | 278 | |
| AnnaBridge | 143:86740a56073b | 279 | /*! @name FGPIO Configuration */ |
| AnnaBridge | 143:86740a56073b | 280 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 281 | |
| AnnaBridge | 143:86740a56073b | 282 | /*! |
| AnnaBridge | 143:86740a56073b | 283 | * @brief Initializes a FGPIO pin used by the board. |
| AnnaBridge | 143:86740a56073b | 284 | * |
| AnnaBridge | 143:86740a56073b | 285 | * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. |
| AnnaBridge | 143:86740a56073b | 286 | * Then, call the FGPIO_PinInit() function. |
| AnnaBridge | 143:86740a56073b | 287 | * |
| AnnaBridge | 143:86740a56073b | 288 | * This is an example to define an input pin or an output pin configuration: |
| AnnaBridge | 143:86740a56073b | 289 | * @code |
| AnnaBridge | 143:86740a56073b | 290 | * // Define a digital input pin configuration, |
| AnnaBridge | 143:86740a56073b | 291 | * gpio_pin_config_t config = |
| AnnaBridge | 143:86740a56073b | 292 | * { |
| AnnaBridge | 143:86740a56073b | 293 | * kGPIO_DigitalInput, |
| AnnaBridge | 143:86740a56073b | 294 | * 0, |
| AnnaBridge | 143:86740a56073b | 295 | * } |
| AnnaBridge | 143:86740a56073b | 296 | * //Define a digital output pin configuration, |
| AnnaBridge | 143:86740a56073b | 297 | * gpio_pin_config_t config = |
| AnnaBridge | 143:86740a56073b | 298 | * { |
| AnnaBridge | 143:86740a56073b | 299 | * kGPIO_DigitalOutput, |
| AnnaBridge | 143:86740a56073b | 300 | * 0, |
| AnnaBridge | 143:86740a56073b | 301 | * } |
| AnnaBridge | 143:86740a56073b | 302 | * @endcode |
| AnnaBridge | 143:86740a56073b | 303 | * |
| AnnaBridge | 143:86740a56073b | 304 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 305 | * @param pin FGPIO port pin number |
| AnnaBridge | 143:86740a56073b | 306 | * @param config FGPIO pin configuration pointer |
| AnnaBridge | 143:86740a56073b | 307 | */ |
| AnnaBridge | 143:86740a56073b | 308 | void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); |
| AnnaBridge | 143:86740a56073b | 309 | |
| AnnaBridge | 143:86740a56073b | 310 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 311 | |
| AnnaBridge | 143:86740a56073b | 312 | /*! @name FGPIO Output Operations */ |
| AnnaBridge | 143:86740a56073b | 313 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 314 | |
| AnnaBridge | 143:86740a56073b | 315 | /*! |
| AnnaBridge | 143:86740a56073b | 316 | * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. |
| AnnaBridge | 143:86740a56073b | 317 | * |
| AnnaBridge | 143:86740a56073b | 318 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 319 | * @param pin FGPIO pin number |
| AnnaBridge | 143:86740a56073b | 320 | * @param output FGPIOpin output logic level. |
| AnnaBridge | 143:86740a56073b | 321 | * - 0: corresponding pin output low-logic level. |
| AnnaBridge | 143:86740a56073b | 322 | * - 1: corresponding pin output high-logic level. |
| AnnaBridge | 143:86740a56073b | 323 | */ |
| AnnaBridge | 143:86740a56073b | 324 | static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) |
| AnnaBridge | 143:86740a56073b | 325 | { |
| AnnaBridge | 143:86740a56073b | 326 | if (output == 0U) |
| AnnaBridge | 143:86740a56073b | 327 | { |
| AnnaBridge | 143:86740a56073b | 328 | base->PCOR = 1 << pin; |
| AnnaBridge | 143:86740a56073b | 329 | } |
| AnnaBridge | 143:86740a56073b | 330 | else |
| AnnaBridge | 143:86740a56073b | 331 | { |
| AnnaBridge | 143:86740a56073b | 332 | base->PSOR = 1 << pin; |
| AnnaBridge | 143:86740a56073b | 333 | } |
| AnnaBridge | 143:86740a56073b | 334 | } |
| AnnaBridge | 143:86740a56073b | 335 | |
| AnnaBridge | 143:86740a56073b | 336 | /*! |
| AnnaBridge | 143:86740a56073b | 337 | * @brief Sets the output level of the multiple FGPIO pins to the logic 1. |
| AnnaBridge | 143:86740a56073b | 338 | * |
| AnnaBridge | 143:86740a56073b | 339 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 340 | * @param mask FGPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 341 | */ |
| AnnaBridge | 143:86740a56073b | 342 | static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) |
| AnnaBridge | 143:86740a56073b | 343 | { |
| AnnaBridge | 143:86740a56073b | 344 | base->PSOR = mask; |
| AnnaBridge | 143:86740a56073b | 345 | } |
| AnnaBridge | 143:86740a56073b | 346 | |
| AnnaBridge | 143:86740a56073b | 347 | /*! |
| AnnaBridge | 143:86740a56073b | 348 | * @brief Sets the output level of the multiple FGPIO pins to the logic 0. |
| AnnaBridge | 143:86740a56073b | 349 | * |
| AnnaBridge | 143:86740a56073b | 350 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 351 | * @param mask FGPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 352 | */ |
| AnnaBridge | 143:86740a56073b | 353 | static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) |
| AnnaBridge | 143:86740a56073b | 354 | { |
| AnnaBridge | 143:86740a56073b | 355 | base->PCOR = mask; |
| AnnaBridge | 143:86740a56073b | 356 | } |
| AnnaBridge | 143:86740a56073b | 357 | |
| AnnaBridge | 143:86740a56073b | 358 | /*! |
| AnnaBridge | 143:86740a56073b | 359 | * @brief Reverses the current output logic of the multiple FGPIO pins. |
| AnnaBridge | 143:86740a56073b | 360 | * |
| AnnaBridge | 143:86740a56073b | 361 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 362 | * @param mask FGPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 363 | */ |
| AnnaBridge | 143:86740a56073b | 364 | static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) |
| AnnaBridge | 143:86740a56073b | 365 | { |
| AnnaBridge | 143:86740a56073b | 366 | base->PTOR = mask; |
| AnnaBridge | 143:86740a56073b | 367 | } |
| AnnaBridge | 143:86740a56073b | 368 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 369 | |
| AnnaBridge | 143:86740a56073b | 370 | /*! @name FGPIO Input Operations */ |
| AnnaBridge | 143:86740a56073b | 371 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 372 | |
| AnnaBridge | 143:86740a56073b | 373 | /*! |
| AnnaBridge | 143:86740a56073b | 374 | * @brief Reads the current input value of the FGPIO port. |
| AnnaBridge | 143:86740a56073b | 375 | * |
| AnnaBridge | 143:86740a56073b | 376 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 377 | * @param pin FGPIO pin number |
| AnnaBridge | 143:86740a56073b | 378 | * @retval FGPIO port input value |
| AnnaBridge | 143:86740a56073b | 379 | * - 0: corresponding pin input low-logic level. |
| AnnaBridge | 143:86740a56073b | 380 | * - 1: corresponding pin input high-logic level. |
| AnnaBridge | 143:86740a56073b | 381 | */ |
| AnnaBridge | 143:86740a56073b | 382 | static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) |
| AnnaBridge | 143:86740a56073b | 383 | { |
| AnnaBridge | 143:86740a56073b | 384 | return (((base->PDIR) >> pin) & 0x01U); |
| AnnaBridge | 143:86740a56073b | 385 | } |
| AnnaBridge | 143:86740a56073b | 386 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 387 | |
| AnnaBridge | 143:86740a56073b | 388 | /*! @name FGPIO Interrupt */ |
| AnnaBridge | 143:86740a56073b | 389 | /*@{*/ |
| AnnaBridge | 143:86740a56073b | 390 | |
| AnnaBridge | 143:86740a56073b | 391 | /*! |
| AnnaBridge | 143:86740a56073b | 392 | * @brief Reads the FGPIO port interrupt status flag. |
| AnnaBridge | 143:86740a56073b | 393 | * |
| AnnaBridge | 143:86740a56073b | 394 | * If a pin is configured to generate the DMA request, the corresponding flag |
| AnnaBridge | 143:86740a56073b | 395 | * is cleared automatically at the completion of the requested DMA transfer. |
| AnnaBridge | 143:86740a56073b | 396 | * Otherwise, the flag remains set until a logic one is written to that flag. |
| AnnaBridge | 143:86740a56073b | 397 | * If configured for a level-sensitive interrupt that remains asserted, the flag |
| AnnaBridge | 143:86740a56073b | 398 | * is set again immediately. |
| AnnaBridge | 143:86740a56073b | 399 | * |
| AnnaBridge | 143:86740a56073b | 400 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 401 | * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the |
| AnnaBridge | 143:86740a56073b | 402 | * pin 0 and 17 have the interrupt. |
| AnnaBridge | 143:86740a56073b | 403 | */ |
| AnnaBridge | 143:86740a56073b | 404 | uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); |
| AnnaBridge | 143:86740a56073b | 405 | |
| AnnaBridge | 143:86740a56073b | 406 | /*! |
| AnnaBridge | 143:86740a56073b | 407 | * @brief Clears the multiple FGPIO pin interrupt status flag. |
| AnnaBridge | 143:86740a56073b | 408 | * |
| AnnaBridge | 143:86740a56073b | 409 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 410 | * @param mask FGPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 411 | */ |
| AnnaBridge | 143:86740a56073b | 412 | void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); |
| AnnaBridge | 143:86740a56073b | 413 | |
| AnnaBridge | 143:86740a56073b | 414 | #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER |
| AnnaBridge | 143:86740a56073b | 415 | /*! |
| AnnaBridge | 143:86740a56073b | 416 | * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit |
| AnnaBridge | 143:86740a56073b | 417 | * words. Each 32-bit data port includes a GACR register, which defines the byte-level |
| AnnaBridge | 143:86740a56073b | 418 | * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data |
| AnnaBridge | 143:86740a56073b | 419 | * bytes in the GACR follow a standard little endian |
| AnnaBridge | 143:86740a56073b | 420 | * data convention. |
| AnnaBridge | 143:86740a56073b | 421 | * |
| AnnaBridge | 143:86740a56073b | 422 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 143:86740a56073b | 423 | * @param mask FGPIO pin number macro |
| AnnaBridge | 143:86740a56073b | 424 | */ |
| AnnaBridge | 143:86740a56073b | 425 | void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); |
| AnnaBridge | 143:86740a56073b | 426 | #endif |
| AnnaBridge | 143:86740a56073b | 427 | |
| AnnaBridge | 143:86740a56073b | 428 | /*@}*/ |
| AnnaBridge | 143:86740a56073b | 429 | |
| AnnaBridge | 143:86740a56073b | 430 | #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ |
| AnnaBridge | 143:86740a56073b | 431 | |
| AnnaBridge | 143:86740a56073b | 432 | #if defined(__cplusplus) |
| AnnaBridge | 143:86740a56073b | 433 | } |
| AnnaBridge | 143:86740a56073b | 434 | #endif |
| AnnaBridge | 143:86740a56073b | 435 | |
| AnnaBridge | 143:86740a56073b | 436 | /*! |
| AnnaBridge | 143:86740a56073b | 437 | * @} |
| AnnaBridge | 143:86740a56073b | 438 | */ |
| AnnaBridge | 143:86740a56073b | 439 | |
| AnnaBridge | 143:86740a56073b | 440 | #endif /* _FSL_GPIO_H_*/ |
