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TARGET_RAPIDIOT_K64F/TOOLCHAIN_ARM_STD/fsl_gpio.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 145:64910690c574 | 1 | /* |
| AnnaBridge | 145:64910690c574 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| AnnaBridge | 145:64910690c574 | 3 | * All rights reserved. |
| AnnaBridge | 145:64910690c574 | 4 | * |
| AnnaBridge | 145:64910690c574 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 145:64910690c574 | 6 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 145:64910690c574 | 7 | * |
| AnnaBridge | 145:64910690c574 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| AnnaBridge | 145:64910690c574 | 9 | * of conditions and the following disclaimer. |
| AnnaBridge | 145:64910690c574 | 10 | * |
| AnnaBridge | 145:64910690c574 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| AnnaBridge | 145:64910690c574 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| AnnaBridge | 145:64910690c574 | 13 | * other materials provided with the distribution. |
| AnnaBridge | 145:64910690c574 | 14 | * |
| AnnaBridge | 145:64910690c574 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| AnnaBridge | 145:64910690c574 | 16 | * contributors may be used to endorse or promote products derived from this |
| AnnaBridge | 145:64910690c574 | 17 | * software without specific prior written permission. |
| AnnaBridge | 145:64910690c574 | 18 | * |
| AnnaBridge | 145:64910690c574 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| AnnaBridge | 145:64910690c574 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| AnnaBridge | 145:64910690c574 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 145:64910690c574 | 22 | * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| AnnaBridge | 145:64910690c574 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 145:64910690c574 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| AnnaBridge | 145:64910690c574 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| AnnaBridge | 145:64910690c574 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| AnnaBridge | 145:64910690c574 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| AnnaBridge | 145:64910690c574 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 145:64910690c574 | 29 | */ |
| AnnaBridge | 145:64910690c574 | 30 | |
| AnnaBridge | 145:64910690c574 | 31 | #ifndef _FSL_GPIO_H_ |
| AnnaBridge | 145:64910690c574 | 32 | #define _FSL_GPIO_H_ |
| AnnaBridge | 145:64910690c574 | 33 | |
| AnnaBridge | 145:64910690c574 | 34 | #include "fsl_common.h" |
| AnnaBridge | 145:64910690c574 | 35 | |
| AnnaBridge | 145:64910690c574 | 36 | /*! |
| AnnaBridge | 145:64910690c574 | 37 | * @addtogroup gpio |
| AnnaBridge | 145:64910690c574 | 38 | * @{ |
| AnnaBridge | 145:64910690c574 | 39 | */ |
| AnnaBridge | 145:64910690c574 | 40 | |
| AnnaBridge | 145:64910690c574 | 41 | /******************************************************************************* |
| AnnaBridge | 145:64910690c574 | 42 | * Definitions |
| AnnaBridge | 145:64910690c574 | 43 | ******************************************************************************/ |
| AnnaBridge | 145:64910690c574 | 44 | |
| AnnaBridge | 145:64910690c574 | 45 | /*! @name Driver version */ |
| AnnaBridge | 145:64910690c574 | 46 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 47 | /*! @brief GPIO driver version 2.1.1. */ |
| AnnaBridge | 145:64910690c574 | 48 | #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) |
| AnnaBridge | 145:64910690c574 | 49 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 50 | |
| AnnaBridge | 145:64910690c574 | 51 | /*! @brief GPIO direction definition */ |
| AnnaBridge | 145:64910690c574 | 52 | typedef enum _gpio_pin_direction |
| AnnaBridge | 145:64910690c574 | 53 | { |
| AnnaBridge | 145:64910690c574 | 54 | kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ |
| AnnaBridge | 145:64910690c574 | 55 | kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ |
| AnnaBridge | 145:64910690c574 | 56 | } gpio_pin_direction_t; |
| AnnaBridge | 145:64910690c574 | 57 | |
| AnnaBridge | 145:64910690c574 | 58 | #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER |
| AnnaBridge | 145:64910690c574 | 59 | /*! @brief GPIO checker attribute */ |
| AnnaBridge | 145:64910690c574 | 60 | typedef enum _gpio_checker_attribute |
| AnnaBridge | 145:64910690c574 | 61 | { |
| AnnaBridge | 145:64910690c574 | 62 | kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = |
| AnnaBridge | 145:64910690c574 | 63 | 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ |
| AnnaBridge | 145:64910690c574 | 64 | kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = |
| AnnaBridge | 145:64910690c574 | 65 | 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ |
| AnnaBridge | 145:64910690c574 | 66 | kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = |
| AnnaBridge | 145:64910690c574 | 67 | 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ |
| AnnaBridge | 145:64910690c574 | 68 | kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = |
| AnnaBridge | 145:64910690c574 | 69 | 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ |
| AnnaBridge | 145:64910690c574 | 70 | kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = |
| AnnaBridge | 145:64910690c574 | 71 | 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ |
| AnnaBridge | 145:64910690c574 | 72 | kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = |
| AnnaBridge | 145:64910690c574 | 73 | 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ |
| AnnaBridge | 145:64910690c574 | 74 | kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = |
| AnnaBridge | 145:64910690c574 | 75 | 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ |
| AnnaBridge | 145:64910690c574 | 76 | kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = |
| AnnaBridge | 145:64910690c574 | 77 | 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ |
| AnnaBridge | 145:64910690c574 | 78 | kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */ |
| AnnaBridge | 145:64910690c574 | 79 | } gpio_checker_attribute_t; |
| AnnaBridge | 145:64910690c574 | 80 | #endif |
| AnnaBridge | 145:64910690c574 | 81 | |
| AnnaBridge | 145:64910690c574 | 82 | /*! |
| AnnaBridge | 145:64910690c574 | 83 | * @brief The GPIO pin configuration structure. |
| AnnaBridge | 145:64910690c574 | 84 | * |
| AnnaBridge | 145:64910690c574 | 85 | * Each pin can only be configured as either an output pin or an input pin at a time. |
| AnnaBridge | 145:64910690c574 | 86 | * If configured as an input pin, leave the outputConfig unused. |
| AnnaBridge | 145:64910690c574 | 87 | * Note that in some use cases, the corresponding port property should be configured in advance |
| AnnaBridge | 145:64910690c574 | 88 | * with the PORT_SetPinConfig(). |
| AnnaBridge | 145:64910690c574 | 89 | */ |
| AnnaBridge | 145:64910690c574 | 90 | typedef struct _gpio_pin_config |
| AnnaBridge | 145:64910690c574 | 91 | { |
| AnnaBridge | 145:64910690c574 | 92 | gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ |
| AnnaBridge | 145:64910690c574 | 93 | /* Output configurations; ignore if configured as an input pin */ |
| AnnaBridge | 145:64910690c574 | 94 | uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ |
| AnnaBridge | 145:64910690c574 | 95 | } gpio_pin_config_t; |
| AnnaBridge | 145:64910690c574 | 96 | |
| AnnaBridge | 145:64910690c574 | 97 | /*! @} */ |
| AnnaBridge | 145:64910690c574 | 98 | |
| AnnaBridge | 145:64910690c574 | 99 | /******************************************************************************* |
| AnnaBridge | 145:64910690c574 | 100 | * API |
| AnnaBridge | 145:64910690c574 | 101 | ******************************************************************************/ |
| AnnaBridge | 145:64910690c574 | 102 | |
| AnnaBridge | 145:64910690c574 | 103 | #if defined(__cplusplus) |
| AnnaBridge | 145:64910690c574 | 104 | extern "C" { |
| AnnaBridge | 145:64910690c574 | 105 | #endif |
| AnnaBridge | 145:64910690c574 | 106 | |
| AnnaBridge | 145:64910690c574 | 107 | /*! |
| AnnaBridge | 145:64910690c574 | 108 | * @addtogroup gpio_driver |
| AnnaBridge | 145:64910690c574 | 109 | * @{ |
| AnnaBridge | 145:64910690c574 | 110 | */ |
| AnnaBridge | 145:64910690c574 | 111 | |
| AnnaBridge | 145:64910690c574 | 112 | /*! @name GPIO Configuration */ |
| AnnaBridge | 145:64910690c574 | 113 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 114 | |
| AnnaBridge | 145:64910690c574 | 115 | /*! |
| AnnaBridge | 145:64910690c574 | 116 | * @brief Initializes a GPIO pin used by the board. |
| AnnaBridge | 145:64910690c574 | 117 | * |
| AnnaBridge | 145:64910690c574 | 118 | * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. |
| AnnaBridge | 145:64910690c574 | 119 | * Then, call the GPIO_PinInit() function. |
| AnnaBridge | 145:64910690c574 | 120 | * |
| AnnaBridge | 145:64910690c574 | 121 | * This is an example to define an input pin or an output pin configuration. |
| AnnaBridge | 145:64910690c574 | 122 | * @code |
| AnnaBridge | 145:64910690c574 | 123 | * // Define a digital input pin configuration, |
| AnnaBridge | 145:64910690c574 | 124 | * gpio_pin_config_t config = |
| AnnaBridge | 145:64910690c574 | 125 | * { |
| AnnaBridge | 145:64910690c574 | 126 | * kGPIO_DigitalInput, |
| AnnaBridge | 145:64910690c574 | 127 | * 0, |
| AnnaBridge | 145:64910690c574 | 128 | * } |
| AnnaBridge | 145:64910690c574 | 129 | * //Define a digital output pin configuration, |
| AnnaBridge | 145:64910690c574 | 130 | * gpio_pin_config_t config = |
| AnnaBridge | 145:64910690c574 | 131 | * { |
| AnnaBridge | 145:64910690c574 | 132 | * kGPIO_DigitalOutput, |
| AnnaBridge | 145:64910690c574 | 133 | * 0, |
| AnnaBridge | 145:64910690c574 | 134 | * } |
| AnnaBridge | 145:64910690c574 | 135 | * @endcode |
| AnnaBridge | 145:64910690c574 | 136 | * |
| AnnaBridge | 145:64910690c574 | 137 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 138 | * @param pin GPIO port pin number |
| AnnaBridge | 145:64910690c574 | 139 | * @param config GPIO pin configuration pointer |
| AnnaBridge | 145:64910690c574 | 140 | */ |
| AnnaBridge | 145:64910690c574 | 141 | void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); |
| AnnaBridge | 145:64910690c574 | 142 | |
| AnnaBridge | 145:64910690c574 | 143 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 144 | |
| AnnaBridge | 145:64910690c574 | 145 | /*! @name GPIO Output Operations */ |
| AnnaBridge | 145:64910690c574 | 146 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 147 | |
| AnnaBridge | 145:64910690c574 | 148 | /*! |
| AnnaBridge | 145:64910690c574 | 149 | * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. |
| AnnaBridge | 145:64910690c574 | 150 | * |
| AnnaBridge | 145:64910690c574 | 151 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 152 | * @param pin GPIO pin number |
| AnnaBridge | 145:64910690c574 | 153 | * @param output GPIO pin output logic level. |
| AnnaBridge | 145:64910690c574 | 154 | * - 0: corresponding pin output low-logic level. |
| AnnaBridge | 145:64910690c574 | 155 | * - 1: corresponding pin output high-logic level. |
| AnnaBridge | 145:64910690c574 | 156 | */ |
| AnnaBridge | 145:64910690c574 | 157 | static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) |
| AnnaBridge | 145:64910690c574 | 158 | { |
| AnnaBridge | 145:64910690c574 | 159 | if (output == 0U) |
| AnnaBridge | 145:64910690c574 | 160 | { |
| AnnaBridge | 145:64910690c574 | 161 | base->PCOR = 1U << pin; |
| AnnaBridge | 145:64910690c574 | 162 | } |
| AnnaBridge | 145:64910690c574 | 163 | else |
| AnnaBridge | 145:64910690c574 | 164 | { |
| AnnaBridge | 145:64910690c574 | 165 | base->PSOR = 1U << pin; |
| AnnaBridge | 145:64910690c574 | 166 | } |
| AnnaBridge | 145:64910690c574 | 167 | } |
| AnnaBridge | 145:64910690c574 | 168 | |
| AnnaBridge | 145:64910690c574 | 169 | /*! |
| AnnaBridge | 145:64910690c574 | 170 | * @brief Sets the output level of the multiple GPIO pins to the logic 1. |
| AnnaBridge | 145:64910690c574 | 171 | * |
| AnnaBridge | 145:64910690c574 | 172 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 173 | * @param mask GPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 174 | */ |
| AnnaBridge | 145:64910690c574 | 175 | static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) |
| AnnaBridge | 145:64910690c574 | 176 | { |
| AnnaBridge | 145:64910690c574 | 177 | base->PSOR = mask; |
| AnnaBridge | 145:64910690c574 | 178 | } |
| AnnaBridge | 145:64910690c574 | 179 | |
| AnnaBridge | 145:64910690c574 | 180 | /*! |
| AnnaBridge | 145:64910690c574 | 181 | * @brief Sets the output level of the multiple GPIO pins to the logic 0. |
| AnnaBridge | 145:64910690c574 | 182 | * |
| AnnaBridge | 145:64910690c574 | 183 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 184 | * @param mask GPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 185 | */ |
| AnnaBridge | 145:64910690c574 | 186 | static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) |
| AnnaBridge | 145:64910690c574 | 187 | { |
| AnnaBridge | 145:64910690c574 | 188 | base->PCOR = mask; |
| AnnaBridge | 145:64910690c574 | 189 | } |
| AnnaBridge | 145:64910690c574 | 190 | |
| AnnaBridge | 145:64910690c574 | 191 | /*! |
| AnnaBridge | 145:64910690c574 | 192 | * @brief Reverses the current output logic of the multiple GPIO pins. |
| AnnaBridge | 145:64910690c574 | 193 | * |
| AnnaBridge | 145:64910690c574 | 194 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 195 | * @param mask GPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 196 | */ |
| AnnaBridge | 145:64910690c574 | 197 | static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) |
| AnnaBridge | 145:64910690c574 | 198 | { |
| AnnaBridge | 145:64910690c574 | 199 | base->PTOR = mask; |
| AnnaBridge | 145:64910690c574 | 200 | } |
| AnnaBridge | 145:64910690c574 | 201 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 202 | |
| AnnaBridge | 145:64910690c574 | 203 | /*! @name GPIO Input Operations */ |
| AnnaBridge | 145:64910690c574 | 204 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 205 | |
| AnnaBridge | 145:64910690c574 | 206 | /*! |
| AnnaBridge | 145:64910690c574 | 207 | * @brief Reads the current input value of the GPIO port. |
| AnnaBridge | 145:64910690c574 | 208 | * |
| AnnaBridge | 145:64910690c574 | 209 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 210 | * @param pin GPIO pin number |
| AnnaBridge | 145:64910690c574 | 211 | * @retval GPIO port input value |
| AnnaBridge | 145:64910690c574 | 212 | * - 0: corresponding pin input low-logic level. |
| AnnaBridge | 145:64910690c574 | 213 | * - 1: corresponding pin input high-logic level. |
| AnnaBridge | 145:64910690c574 | 214 | */ |
| AnnaBridge | 145:64910690c574 | 215 | static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) |
| AnnaBridge | 145:64910690c574 | 216 | { |
| AnnaBridge | 145:64910690c574 | 217 | return (((base->PDIR) >> pin) & 0x01U); |
| AnnaBridge | 145:64910690c574 | 218 | } |
| AnnaBridge | 145:64910690c574 | 219 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 220 | |
| AnnaBridge | 145:64910690c574 | 221 | /*! @name GPIO Interrupt */ |
| AnnaBridge | 145:64910690c574 | 222 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 223 | |
| AnnaBridge | 145:64910690c574 | 224 | /*! |
| AnnaBridge | 145:64910690c574 | 225 | * @brief Reads the GPIO port interrupt status flag. |
| AnnaBridge | 145:64910690c574 | 226 | * |
| AnnaBridge | 145:64910690c574 | 227 | * If a pin is configured to generate the DMA request, the corresponding flag |
| AnnaBridge | 145:64910690c574 | 228 | * is cleared automatically at the completion of the requested DMA transfer. |
| AnnaBridge | 145:64910690c574 | 229 | * Otherwise, the flag remains set until a logic one is written to that flag. |
| AnnaBridge | 145:64910690c574 | 230 | * If configured for a level sensitive interrupt that remains asserted, the flag |
| AnnaBridge | 145:64910690c574 | 231 | * is set again immediately. |
| AnnaBridge | 145:64910690c574 | 232 | * |
| AnnaBridge | 145:64910690c574 | 233 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 234 | * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the |
| AnnaBridge | 145:64910690c574 | 235 | * pin 0 and 17 have the interrupt. |
| AnnaBridge | 145:64910690c574 | 236 | */ |
| AnnaBridge | 145:64910690c574 | 237 | uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); |
| AnnaBridge | 145:64910690c574 | 238 | |
| AnnaBridge | 145:64910690c574 | 239 | /*! |
| AnnaBridge | 145:64910690c574 | 240 | * @brief Clears multiple GPIO pin interrupt status flags. |
| AnnaBridge | 145:64910690c574 | 241 | * |
| AnnaBridge | 145:64910690c574 | 242 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 243 | * @param mask GPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 244 | */ |
| AnnaBridge | 145:64910690c574 | 245 | void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); |
| AnnaBridge | 145:64910690c574 | 246 | |
| AnnaBridge | 145:64910690c574 | 247 | #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER |
| AnnaBridge | 145:64910690c574 | 248 | /*! |
| AnnaBridge | 145:64910690c574 | 249 | * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit |
| AnnaBridge | 145:64910690c574 | 250 | * words. Each 32-bit data port includes a GACR register, which defines the byte-level |
| AnnaBridge | 145:64910690c574 | 251 | * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data |
| AnnaBridge | 145:64910690c574 | 252 | * bytes in the GACR follow a standard little endian |
| AnnaBridge | 145:64910690c574 | 253 | * data convention. |
| AnnaBridge | 145:64910690c574 | 254 | * |
| AnnaBridge | 145:64910690c574 | 255 | * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 256 | * @param mask GPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 257 | */ |
| AnnaBridge | 145:64910690c574 | 258 | void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); |
| AnnaBridge | 145:64910690c574 | 259 | #endif |
| AnnaBridge | 145:64910690c574 | 260 | |
| AnnaBridge | 145:64910690c574 | 261 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 262 | /*! @} */ |
| AnnaBridge | 145:64910690c574 | 263 | |
| AnnaBridge | 145:64910690c574 | 264 | /*! |
| AnnaBridge | 145:64910690c574 | 265 | * @addtogroup fgpio_driver |
| AnnaBridge | 145:64910690c574 | 266 | * @{ |
| AnnaBridge | 145:64910690c574 | 267 | */ |
| AnnaBridge | 145:64910690c574 | 268 | |
| AnnaBridge | 145:64910690c574 | 269 | /* |
| AnnaBridge | 145:64910690c574 | 270 | * Introduces the FGPIO feature. |
| AnnaBridge | 145:64910690c574 | 271 | * |
| AnnaBridge | 145:64910690c574 | 272 | * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT |
| AnnaBridge | 145:64910690c574 | 273 | * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and |
| AnnaBridge | 145:64910690c574 | 274 | * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. |
| AnnaBridge | 145:64910690c574 | 275 | */ |
| AnnaBridge | 145:64910690c574 | 276 | |
| AnnaBridge | 145:64910690c574 | 277 | #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT |
| AnnaBridge | 145:64910690c574 | 278 | |
| AnnaBridge | 145:64910690c574 | 279 | /*! @name FGPIO Configuration */ |
| AnnaBridge | 145:64910690c574 | 280 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 281 | |
| AnnaBridge | 145:64910690c574 | 282 | /*! |
| AnnaBridge | 145:64910690c574 | 283 | * @brief Initializes a FGPIO pin used by the board. |
| AnnaBridge | 145:64910690c574 | 284 | * |
| AnnaBridge | 145:64910690c574 | 285 | * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. |
| AnnaBridge | 145:64910690c574 | 286 | * Then, call the FGPIO_PinInit() function. |
| AnnaBridge | 145:64910690c574 | 287 | * |
| AnnaBridge | 145:64910690c574 | 288 | * This is an example to define an input pin or an output pin configuration: |
| AnnaBridge | 145:64910690c574 | 289 | * @code |
| AnnaBridge | 145:64910690c574 | 290 | * // Define a digital input pin configuration, |
| AnnaBridge | 145:64910690c574 | 291 | * gpio_pin_config_t config = |
| AnnaBridge | 145:64910690c574 | 292 | * { |
| AnnaBridge | 145:64910690c574 | 293 | * kGPIO_DigitalInput, |
| AnnaBridge | 145:64910690c574 | 294 | * 0, |
| AnnaBridge | 145:64910690c574 | 295 | * } |
| AnnaBridge | 145:64910690c574 | 296 | * //Define a digital output pin configuration, |
| AnnaBridge | 145:64910690c574 | 297 | * gpio_pin_config_t config = |
| AnnaBridge | 145:64910690c574 | 298 | * { |
| AnnaBridge | 145:64910690c574 | 299 | * kGPIO_DigitalOutput, |
| AnnaBridge | 145:64910690c574 | 300 | * 0, |
| AnnaBridge | 145:64910690c574 | 301 | * } |
| AnnaBridge | 145:64910690c574 | 302 | * @endcode |
| AnnaBridge | 145:64910690c574 | 303 | * |
| AnnaBridge | 145:64910690c574 | 304 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 305 | * @param pin FGPIO port pin number |
| AnnaBridge | 145:64910690c574 | 306 | * @param config FGPIO pin configuration pointer |
| AnnaBridge | 145:64910690c574 | 307 | */ |
| AnnaBridge | 145:64910690c574 | 308 | void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); |
| AnnaBridge | 145:64910690c574 | 309 | |
| AnnaBridge | 145:64910690c574 | 310 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 311 | |
| AnnaBridge | 145:64910690c574 | 312 | /*! @name FGPIO Output Operations */ |
| AnnaBridge | 145:64910690c574 | 313 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 314 | |
| AnnaBridge | 145:64910690c574 | 315 | /*! |
| AnnaBridge | 145:64910690c574 | 316 | * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. |
| AnnaBridge | 145:64910690c574 | 317 | * |
| AnnaBridge | 145:64910690c574 | 318 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 319 | * @param pin FGPIO pin number |
| AnnaBridge | 145:64910690c574 | 320 | * @param output FGPIOpin output logic level. |
| AnnaBridge | 145:64910690c574 | 321 | * - 0: corresponding pin output low-logic level. |
| AnnaBridge | 145:64910690c574 | 322 | * - 1: corresponding pin output high-logic level. |
| AnnaBridge | 145:64910690c574 | 323 | */ |
| AnnaBridge | 145:64910690c574 | 324 | static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) |
| AnnaBridge | 145:64910690c574 | 325 | { |
| AnnaBridge | 145:64910690c574 | 326 | if (output == 0U) |
| AnnaBridge | 145:64910690c574 | 327 | { |
| AnnaBridge | 145:64910690c574 | 328 | base->PCOR = 1 << pin; |
| AnnaBridge | 145:64910690c574 | 329 | } |
| AnnaBridge | 145:64910690c574 | 330 | else |
| AnnaBridge | 145:64910690c574 | 331 | { |
| AnnaBridge | 145:64910690c574 | 332 | base->PSOR = 1 << pin; |
| AnnaBridge | 145:64910690c574 | 333 | } |
| AnnaBridge | 145:64910690c574 | 334 | } |
| AnnaBridge | 145:64910690c574 | 335 | |
| AnnaBridge | 145:64910690c574 | 336 | /*! |
| AnnaBridge | 145:64910690c574 | 337 | * @brief Sets the output level of the multiple FGPIO pins to the logic 1. |
| AnnaBridge | 145:64910690c574 | 338 | * |
| AnnaBridge | 145:64910690c574 | 339 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 340 | * @param mask FGPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 341 | */ |
| AnnaBridge | 145:64910690c574 | 342 | static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) |
| AnnaBridge | 145:64910690c574 | 343 | { |
| AnnaBridge | 145:64910690c574 | 344 | base->PSOR = mask; |
| AnnaBridge | 145:64910690c574 | 345 | } |
| AnnaBridge | 145:64910690c574 | 346 | |
| AnnaBridge | 145:64910690c574 | 347 | /*! |
| AnnaBridge | 145:64910690c574 | 348 | * @brief Sets the output level of the multiple FGPIO pins to the logic 0. |
| AnnaBridge | 145:64910690c574 | 349 | * |
| AnnaBridge | 145:64910690c574 | 350 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 351 | * @param mask FGPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 352 | */ |
| AnnaBridge | 145:64910690c574 | 353 | static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) |
| AnnaBridge | 145:64910690c574 | 354 | { |
| AnnaBridge | 145:64910690c574 | 355 | base->PCOR = mask; |
| AnnaBridge | 145:64910690c574 | 356 | } |
| AnnaBridge | 145:64910690c574 | 357 | |
| AnnaBridge | 145:64910690c574 | 358 | /*! |
| AnnaBridge | 145:64910690c574 | 359 | * @brief Reverses the current output logic of the multiple FGPIO pins. |
| AnnaBridge | 145:64910690c574 | 360 | * |
| AnnaBridge | 145:64910690c574 | 361 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 362 | * @param mask FGPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 363 | */ |
| AnnaBridge | 145:64910690c574 | 364 | static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) |
| AnnaBridge | 145:64910690c574 | 365 | { |
| AnnaBridge | 145:64910690c574 | 366 | base->PTOR = mask; |
| AnnaBridge | 145:64910690c574 | 367 | } |
| AnnaBridge | 145:64910690c574 | 368 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 369 | |
| AnnaBridge | 145:64910690c574 | 370 | /*! @name FGPIO Input Operations */ |
| AnnaBridge | 145:64910690c574 | 371 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 372 | |
| AnnaBridge | 145:64910690c574 | 373 | /*! |
| AnnaBridge | 145:64910690c574 | 374 | * @brief Reads the current input value of the FGPIO port. |
| AnnaBridge | 145:64910690c574 | 375 | * |
| AnnaBridge | 145:64910690c574 | 376 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 377 | * @param pin FGPIO pin number |
| AnnaBridge | 145:64910690c574 | 378 | * @retval FGPIO port input value |
| AnnaBridge | 145:64910690c574 | 379 | * - 0: corresponding pin input low-logic level. |
| AnnaBridge | 145:64910690c574 | 380 | * - 1: corresponding pin input high-logic level. |
| AnnaBridge | 145:64910690c574 | 381 | */ |
| AnnaBridge | 145:64910690c574 | 382 | static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) |
| AnnaBridge | 145:64910690c574 | 383 | { |
| AnnaBridge | 145:64910690c574 | 384 | return (((base->PDIR) >> pin) & 0x01U); |
| AnnaBridge | 145:64910690c574 | 385 | } |
| AnnaBridge | 145:64910690c574 | 386 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 387 | |
| AnnaBridge | 145:64910690c574 | 388 | /*! @name FGPIO Interrupt */ |
| AnnaBridge | 145:64910690c574 | 389 | /*@{*/ |
| AnnaBridge | 145:64910690c574 | 390 | |
| AnnaBridge | 145:64910690c574 | 391 | /*! |
| AnnaBridge | 145:64910690c574 | 392 | * @brief Reads the FGPIO port interrupt status flag. |
| AnnaBridge | 145:64910690c574 | 393 | * |
| AnnaBridge | 145:64910690c574 | 394 | * If a pin is configured to generate the DMA request, the corresponding flag |
| AnnaBridge | 145:64910690c574 | 395 | * is cleared automatically at the completion of the requested DMA transfer. |
| AnnaBridge | 145:64910690c574 | 396 | * Otherwise, the flag remains set until a logic one is written to that flag. |
| AnnaBridge | 145:64910690c574 | 397 | * If configured for a level-sensitive interrupt that remains asserted, the flag |
| AnnaBridge | 145:64910690c574 | 398 | * is set again immediately. |
| AnnaBridge | 145:64910690c574 | 399 | * |
| AnnaBridge | 145:64910690c574 | 400 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 401 | * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the |
| AnnaBridge | 145:64910690c574 | 402 | * pin 0 and 17 have the interrupt. |
| AnnaBridge | 145:64910690c574 | 403 | */ |
| AnnaBridge | 145:64910690c574 | 404 | uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); |
| AnnaBridge | 145:64910690c574 | 405 | |
| AnnaBridge | 145:64910690c574 | 406 | /*! |
| AnnaBridge | 145:64910690c574 | 407 | * @brief Clears the multiple FGPIO pin interrupt status flag. |
| AnnaBridge | 145:64910690c574 | 408 | * |
| AnnaBridge | 145:64910690c574 | 409 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 410 | * @param mask FGPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 411 | */ |
| AnnaBridge | 145:64910690c574 | 412 | void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); |
| AnnaBridge | 145:64910690c574 | 413 | |
| AnnaBridge | 145:64910690c574 | 414 | #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER |
| AnnaBridge | 145:64910690c574 | 415 | /*! |
| AnnaBridge | 145:64910690c574 | 416 | * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit |
| AnnaBridge | 145:64910690c574 | 417 | * words. Each 32-bit data port includes a GACR register, which defines the byte-level |
| AnnaBridge | 145:64910690c574 | 418 | * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data |
| AnnaBridge | 145:64910690c574 | 419 | * bytes in the GACR follow a standard little endian |
| AnnaBridge | 145:64910690c574 | 420 | * data convention. |
| AnnaBridge | 145:64910690c574 | 421 | * |
| AnnaBridge | 145:64910690c574 | 422 | * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| AnnaBridge | 145:64910690c574 | 423 | * @param mask FGPIO pin number macro |
| AnnaBridge | 145:64910690c574 | 424 | */ |
| AnnaBridge | 145:64910690c574 | 425 | void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); |
| AnnaBridge | 145:64910690c574 | 426 | #endif |
| AnnaBridge | 145:64910690c574 | 427 | |
| AnnaBridge | 145:64910690c574 | 428 | /*@}*/ |
| AnnaBridge | 145:64910690c574 | 429 | |
| AnnaBridge | 145:64910690c574 | 430 | #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ |
| AnnaBridge | 145:64910690c574 | 431 | |
| AnnaBridge | 145:64910690c574 | 432 | #if defined(__cplusplus) |
| AnnaBridge | 145:64910690c574 | 433 | } |
| AnnaBridge | 145:64910690c574 | 434 | #endif |
| AnnaBridge | 145:64910690c574 | 435 | |
| AnnaBridge | 145:64910690c574 | 436 | /*! |
| AnnaBridge | 145:64910690c574 | 437 | * @} |
| AnnaBridge | 145:64910690c574 | 438 | */ |
| AnnaBridge | 145:64910690c574 | 439 | |
| AnnaBridge | 145:64910690c574 | 440 | #endif /* _FSL_GPIO_H_*/ |
