mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RAPIDIOT_K64F/TOOLCHAIN_ARM_STD/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/*
AnnaBridge	171:3a7713b1edbc	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge	171:3a7713b1edbc	3	* All rights reserved.
AnnaBridge	171:3a7713b1edbc	4	*
AnnaBridge	171:3a7713b1edbc	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	6	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	7	*
AnnaBridge	171:3a7713b1edbc	8	* o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	171:3a7713b1edbc	9	* of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	171:3a7713b1edbc	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	171:3a7713b1edbc	13	* other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	14	*
AnnaBridge	171:3a7713b1edbc	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge	171:3a7713b1edbc	16	* contributors may be used to endorse or promote products derived from this
AnnaBridge	171:3a7713b1edbc	17	* software without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	18	*
AnnaBridge	171:3a7713b1edbc	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	171:3a7713b1edbc	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	171:3a7713b1edbc	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	171:3a7713b1edbc	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	171:3a7713b1edbc	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	171:3a7713b1edbc	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	171:3a7713b1edbc	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	171:3a7713b1edbc	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	171:3a7713b1edbc	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	29	*/
AnnaBridge	171:3a7713b1edbc	30
AnnaBridge	171:3a7713b1edbc	31	#ifndef _FSL_CLOCK_H_
AnnaBridge	171:3a7713b1edbc	32	#define _FSL_CLOCK_H_
AnnaBridge	171:3a7713b1edbc	33
AnnaBridge	171:3a7713b1edbc	34	#include "fsl_common.h"
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/! @addtogroup clock /
AnnaBridge	171:3a7713b1edbc	37	/! @{ /
AnnaBridge	171:3a7713b1edbc	38
AnnaBridge	171:3a7713b1edbc	39	/! @file /
AnnaBridge	171:3a7713b1edbc	40
AnnaBridge	171:3a7713b1edbc	41	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	42	* Definitions
AnnaBridge	171:3a7713b1edbc	43	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	44
AnnaBridge	171:3a7713b1edbc	45	/*! @brief Configure whether driver controls clock
AnnaBridge	171:3a7713b1edbc	46	*
AnnaBridge	171:3a7713b1edbc	47	* When set to 0, peripheral drivers will enable clock in initialize function
AnnaBridge	171:3a7713b1edbc	48	* and disable clock in de-initialize function. When set to 1, peripheral
AnnaBridge	171:3a7713b1edbc	49	* driver will not control the clock, application could contol the clock out of
AnnaBridge	171:3a7713b1edbc	50	* the driver.
AnnaBridge	171:3a7713b1edbc	51	*
AnnaBridge	171:3a7713b1edbc	52	* @note All drivers share this feature switcher. If it is set to 1, application
AnnaBridge	171:3a7713b1edbc	53	* should handle clock enable and disable for all drivers.
AnnaBridge	171:3a7713b1edbc	54	*/
AnnaBridge	171:3a7713b1edbc	55	#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
AnnaBridge	171:3a7713b1edbc	56	#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
AnnaBridge	171:3a7713b1edbc	57	#endif
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	/! @name Driver version /
AnnaBridge	171:3a7713b1edbc	60	/@{/
AnnaBridge	171:3a7713b1edbc	61	/! @brief CLOCK driver version 2.2.0. /
AnnaBridge	171:3a7713b1edbc	62	#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
AnnaBridge	171:3a7713b1edbc	63	/@}/
AnnaBridge	171:3a7713b1edbc	64
AnnaBridge	171:3a7713b1edbc	65	/*! @brief External XTAL0 (OSC0) clock frequency.
AnnaBridge	171:3a7713b1edbc	66	*
AnnaBridge	171:3a7713b1edbc	67	* The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
AnnaBridge	171:3a7713b1edbc	68	* function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
AnnaBridge	171:3a7713b1edbc	69	* if XTAL0 is 8 MHz:
AnnaBridge	171:3a7713b1edbc	70	* @code
AnnaBridge	171:3a7713b1edbc	71	* CLOCK_InitOsc0(...); // Set up the OSC0
AnnaBridge	171:3a7713b1edbc	72	* CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
AnnaBridge	171:3a7713b1edbc	73	* @endcode
AnnaBridge	171:3a7713b1edbc	74	*
AnnaBridge	171:3a7713b1edbc	75	* This is important for the multicore platforms where only one core needs to set up the
AnnaBridge	171:3a7713b1edbc	76	* OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
AnnaBridge	171:3a7713b1edbc	77	* to get a valid clock frequency.
AnnaBridge	171:3a7713b1edbc	78	*/
AnnaBridge	171:3a7713b1edbc	79	extern uint32_t g_xtal0Freq;
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
AnnaBridge	171:3a7713b1edbc	82	*
AnnaBridge	171:3a7713b1edbc	83	* The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
AnnaBridge	171:3a7713b1edbc	84	* function CLOCK_SetXtal32Freq to set the value in the clock driver.
AnnaBridge	171:3a7713b1edbc	85	*
AnnaBridge	171:3a7713b1edbc	86	* This is important for the multicore platforms where only one core needs to set up
AnnaBridge	171:3a7713b1edbc	87	* the clock. All other cores need to call the CLOCK_SetXtal32Freq
AnnaBridge	171:3a7713b1edbc	88	* to get a valid clock frequency.
AnnaBridge	171:3a7713b1edbc	89	*/
AnnaBridge	171:3a7713b1edbc	90	extern uint32_t g_xtal32Freq;
AnnaBridge	171:3a7713b1edbc	91
AnnaBridge	171:3a7713b1edbc	92	/! @brief IRC48M clock frequency in Hz. /
AnnaBridge	171:3a7713b1edbc	93	#define MCG_INTERNAL_IRC_48M 48000000U
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	#if (defined(OSC) && !(defined(OSC0)))
AnnaBridge	171:3a7713b1edbc	96	#define OSC0 OSC
AnnaBridge	171:3a7713b1edbc	97	#endif
AnnaBridge	171:3a7713b1edbc	98
AnnaBridge	171:3a7713b1edbc	99	/! @brief Clock ip name array for DMAMUX. /
AnnaBridge	171:3a7713b1edbc	100	#define DMAMUX_CLOCKS \
AnnaBridge	171:3a7713b1edbc	101	{ \
AnnaBridge	171:3a7713b1edbc	102	kCLOCK_Dmamux0 \
AnnaBridge	171:3a7713b1edbc	103	}
AnnaBridge	171:3a7713b1edbc	104
AnnaBridge	171:3a7713b1edbc	105	/! @brief Clock ip name array for RTC. /
AnnaBridge	171:3a7713b1edbc	106	#define RTC_CLOCKS \
AnnaBridge	171:3a7713b1edbc	107	{ \
AnnaBridge	171:3a7713b1edbc	108	kCLOCK_Rtc0 \
AnnaBridge	171:3a7713b1edbc	109	}
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	/! @brief Clock ip name array for ENET. /
AnnaBridge	171:3a7713b1edbc	112	#define ENET_CLOCKS \
AnnaBridge	171:3a7713b1edbc	113	{ \
AnnaBridge	171:3a7713b1edbc	114	kCLOCK_Enet0 \
AnnaBridge	171:3a7713b1edbc	115	}
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117	/! @brief Clock ip name array for PORT. /
AnnaBridge	171:3a7713b1edbc	118	#define PORT_CLOCKS \
AnnaBridge	171:3a7713b1edbc	119	{ \
AnnaBridge	171:3a7713b1edbc	120	kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
AnnaBridge	171:3a7713b1edbc	121	}
AnnaBridge	171:3a7713b1edbc	122
AnnaBridge	171:3a7713b1edbc	123	/! @brief Clock ip name array for SAI. /
AnnaBridge	171:3a7713b1edbc	124	#define SAI_CLOCKS \
AnnaBridge	171:3a7713b1edbc	125	{ \
AnnaBridge	171:3a7713b1edbc	126	kCLOCK_Sai0 \
AnnaBridge	171:3a7713b1edbc	127	}
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	/! @brief Clock ip name array for FLEXBUS. /
AnnaBridge	171:3a7713b1edbc	130	#define FLEXBUS_CLOCKS \
AnnaBridge	171:3a7713b1edbc	131	{ \
AnnaBridge	171:3a7713b1edbc	132	kCLOCK_Flexbus0 \
AnnaBridge	171:3a7713b1edbc	133	}
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	/! @brief Clock ip name array for EWM. /
AnnaBridge	171:3a7713b1edbc	136	#define EWM_CLOCKS \
AnnaBridge	171:3a7713b1edbc	137	{ \
AnnaBridge	171:3a7713b1edbc	138	kCLOCK_Ewm0 \
AnnaBridge	171:3a7713b1edbc	139	}
AnnaBridge	171:3a7713b1edbc	140
AnnaBridge	171:3a7713b1edbc	141	/! @brief Clock ip name array for PIT. /
AnnaBridge	171:3a7713b1edbc	142	#define PIT_CLOCKS \
AnnaBridge	171:3a7713b1edbc	143	{ \
AnnaBridge	171:3a7713b1edbc	144	kCLOCK_Pit0 \
AnnaBridge	171:3a7713b1edbc	145	}
AnnaBridge	171:3a7713b1edbc	146
AnnaBridge	171:3a7713b1edbc	147	/! @brief Clock ip name array for DSPI. /
AnnaBridge	171:3a7713b1edbc	148	#define DSPI_CLOCKS \
AnnaBridge	171:3a7713b1edbc	149	{ \
AnnaBridge	171:3a7713b1edbc	150	kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
AnnaBridge	171:3a7713b1edbc	151	}
AnnaBridge	171:3a7713b1edbc	152
AnnaBridge	171:3a7713b1edbc	153	/! @brief Clock ip name array for LPTMR. /
AnnaBridge	171:3a7713b1edbc	154	#define LPTMR_CLOCKS \
AnnaBridge	171:3a7713b1edbc	155	{ \
AnnaBridge	171:3a7713b1edbc	156	kCLOCK_Lptmr0 \
AnnaBridge	171:3a7713b1edbc	157	}
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	/! @brief Clock ip name array for SDHC. /
AnnaBridge	171:3a7713b1edbc	160	#define SDHC_CLOCKS \
AnnaBridge	171:3a7713b1edbc	161	{ \
AnnaBridge	171:3a7713b1edbc	162	kCLOCK_Sdhc0 \
AnnaBridge	171:3a7713b1edbc	163	}
AnnaBridge	171:3a7713b1edbc	164
AnnaBridge	171:3a7713b1edbc	165	/! @brief Clock ip name array for FTM. /
AnnaBridge	171:3a7713b1edbc	166	#define FTM_CLOCKS \
AnnaBridge	171:3a7713b1edbc	167	{ \
AnnaBridge	171:3a7713b1edbc	168	kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
AnnaBridge	171:3a7713b1edbc	169	}
AnnaBridge	171:3a7713b1edbc	170
AnnaBridge	171:3a7713b1edbc	171	/! @brief Clock ip name array for EDMA. /
AnnaBridge	171:3a7713b1edbc	172	#define EDMA_CLOCKS \
AnnaBridge	171:3a7713b1edbc	173	{ \
AnnaBridge	171:3a7713b1edbc	174	kCLOCK_Dma0 \
AnnaBridge	171:3a7713b1edbc	175	}
AnnaBridge	171:3a7713b1edbc	176
AnnaBridge	171:3a7713b1edbc	177	/! @brief Clock ip name array for FLEXCAN. /
AnnaBridge	171:3a7713b1edbc	178	#define FLEXCAN_CLOCKS \
AnnaBridge	171:3a7713b1edbc	179	{ \
AnnaBridge	171:3a7713b1edbc	180	kCLOCK_Flexcan0 \
AnnaBridge	171:3a7713b1edbc	181	}
AnnaBridge	171:3a7713b1edbc	182
AnnaBridge	171:3a7713b1edbc	183	/! @brief Clock ip name array for DAC. /
AnnaBridge	171:3a7713b1edbc	184	#define DAC_CLOCKS \
AnnaBridge	171:3a7713b1edbc	185	{ \
AnnaBridge	171:3a7713b1edbc	186	kCLOCK_Dac0, kCLOCK_Dac1 \
AnnaBridge	171:3a7713b1edbc	187	}
AnnaBridge	171:3a7713b1edbc	188
AnnaBridge	171:3a7713b1edbc	189	/! @brief Clock ip name array for ADC16. /
AnnaBridge	171:3a7713b1edbc	190	#define ADC16_CLOCKS \
AnnaBridge	171:3a7713b1edbc	191	{ \
AnnaBridge	171:3a7713b1edbc	192	kCLOCK_Adc0, kCLOCK_Adc1 \
AnnaBridge	171:3a7713b1edbc	193	}
AnnaBridge	171:3a7713b1edbc	194
AnnaBridge	171:3a7713b1edbc	195	/! @brief Clock ip name array for MPU. /
AnnaBridge	171:3a7713b1edbc	196	#define SYSMPU_CLOCKS \
AnnaBridge	171:3a7713b1edbc	197	{ \
AnnaBridge	171:3a7713b1edbc	198	kCLOCK_Sysmpu0 \
AnnaBridge	171:3a7713b1edbc	199	}
AnnaBridge	171:3a7713b1edbc	200
AnnaBridge	171:3a7713b1edbc	201	/! @brief Clock ip name array for VREF. /
AnnaBridge	171:3a7713b1edbc	202	#define VREF_CLOCKS \
AnnaBridge	171:3a7713b1edbc	203	{ \
AnnaBridge	171:3a7713b1edbc	204	kCLOCK_Vref0 \
AnnaBridge	171:3a7713b1edbc	205	}
AnnaBridge	171:3a7713b1edbc	206
AnnaBridge	171:3a7713b1edbc	207	/! @brief Clock ip name array for CMT. /
AnnaBridge	171:3a7713b1edbc	208	#define CMT_CLOCKS \
AnnaBridge	171:3a7713b1edbc	209	{ \
AnnaBridge	171:3a7713b1edbc	210	kCLOCK_Cmt0 \
AnnaBridge	171:3a7713b1edbc	211	}
AnnaBridge	171:3a7713b1edbc	212
AnnaBridge	171:3a7713b1edbc	213	/! @brief Clock ip name array for UART. /
AnnaBridge	171:3a7713b1edbc	214	#define UART_CLOCKS \
AnnaBridge	171:3a7713b1edbc	215	{ \
AnnaBridge	171:3a7713b1edbc	216	kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, kCLOCK_Uart5 \
AnnaBridge	171:3a7713b1edbc	217	}
AnnaBridge	171:3a7713b1edbc	218
AnnaBridge	171:3a7713b1edbc	219	/! @brief Clock ip name array for RNGA. /
AnnaBridge	171:3a7713b1edbc	220	#define RNGA_CLOCKS \
AnnaBridge	171:3a7713b1edbc	221	{ \
AnnaBridge	171:3a7713b1edbc	222	kCLOCK_Rnga0 \
AnnaBridge	171:3a7713b1edbc	223	}
AnnaBridge	171:3a7713b1edbc	224
AnnaBridge	171:3a7713b1edbc	225	/! @brief Clock ip name array for CRC. /
AnnaBridge	171:3a7713b1edbc	226	#define CRC_CLOCKS \
AnnaBridge	171:3a7713b1edbc	227	{ \
AnnaBridge	171:3a7713b1edbc	228	kCLOCK_Crc0 \
AnnaBridge	171:3a7713b1edbc	229	}
AnnaBridge	171:3a7713b1edbc	230
AnnaBridge	171:3a7713b1edbc	231	/! @brief Clock ip name array for I2C. /
AnnaBridge	171:3a7713b1edbc	232	#define I2C_CLOCKS \
AnnaBridge	171:3a7713b1edbc	233	{ \
AnnaBridge	171:3a7713b1edbc	234	kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2 \
AnnaBridge	171:3a7713b1edbc	235	}
AnnaBridge	171:3a7713b1edbc	236
AnnaBridge	171:3a7713b1edbc	237	/! @brief Clock ip name array for PDB. /
AnnaBridge	171:3a7713b1edbc	238	#define PDB_CLOCKS \
AnnaBridge	171:3a7713b1edbc	239	{ \
AnnaBridge	171:3a7713b1edbc	240	kCLOCK_Pdb0 \
AnnaBridge	171:3a7713b1edbc	241	}
AnnaBridge	171:3a7713b1edbc	242
AnnaBridge	171:3a7713b1edbc	243	/! @brief Clock ip name array for FTF. /
AnnaBridge	171:3a7713b1edbc	244	#define FTF_CLOCKS \
AnnaBridge	171:3a7713b1edbc	245	{ \
AnnaBridge	171:3a7713b1edbc	246	kCLOCK_Ftf0 \
AnnaBridge	171:3a7713b1edbc	247	}
AnnaBridge	171:3a7713b1edbc	248
AnnaBridge	171:3a7713b1edbc	249	/! @brief Clock ip name array for CMP. /
AnnaBridge	171:3a7713b1edbc	250	#define CMP_CLOCKS \
AnnaBridge	171:3a7713b1edbc	251	{ \
AnnaBridge	171:3a7713b1edbc	252	kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
AnnaBridge	171:3a7713b1edbc	253	}
AnnaBridge	171:3a7713b1edbc	254
AnnaBridge	171:3a7713b1edbc	255	/*!
AnnaBridge	171:3a7713b1edbc	256	* @brief LPO clock frequency.
AnnaBridge	171:3a7713b1edbc	257	*/
AnnaBridge	171:3a7713b1edbc	258	#define LPO_CLK_FREQ 1000U
AnnaBridge	171:3a7713b1edbc	259
AnnaBridge	171:3a7713b1edbc	260	/! @brief Peripherals clock source definition. /
AnnaBridge	171:3a7713b1edbc	261	#define SYS_CLK kCLOCK_CoreSysClk
AnnaBridge	171:3a7713b1edbc	262	#define BUS_CLK kCLOCK_BusClk
AnnaBridge	171:3a7713b1edbc	263
AnnaBridge	171:3a7713b1edbc	264	#define I2C0_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	265	#define I2C1_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	266	#define I2C2_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	267	#define DSPI0_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	268	#define DSPI1_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	269	#define DSPI2_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	270	#define UART0_CLK_SRC SYS_CLK
AnnaBridge	171:3a7713b1edbc	271	#define UART1_CLK_SRC SYS_CLK
AnnaBridge	171:3a7713b1edbc	272	#define UART2_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	273	#define UART3_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	274	#define UART4_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	275	#define UART5_CLK_SRC BUS_CLK
AnnaBridge	171:3a7713b1edbc	276
AnnaBridge	171:3a7713b1edbc	277	/! @brief Clock name used to get clock frequency. /
AnnaBridge	171:3a7713b1edbc	278	typedef enum _clock_name
AnnaBridge	171:3a7713b1edbc	279	{
AnnaBridge	171:3a7713b1edbc	280
AnnaBridge	171:3a7713b1edbc	281	/* ----------------------------- System layer clock -------------------------------*/
AnnaBridge	171:3a7713b1edbc	282	kCLOCK_CoreSysClk, /!< Core/system clock /
AnnaBridge	171:3a7713b1edbc	283	kCLOCK_PlatClk, /!< Platform clock /
AnnaBridge	171:3a7713b1edbc	284	kCLOCK_BusClk, /!< Bus clock /
AnnaBridge	171:3a7713b1edbc	285	kCLOCK_FlexBusClk, /!< FlexBus clock /
AnnaBridge	171:3a7713b1edbc	286	kCLOCK_FlashClk, /!< Flash clock /
AnnaBridge	171:3a7713b1edbc	287	kCLOCK_FastPeriphClk, /!< Fast peripheral clock /
AnnaBridge	171:3a7713b1edbc	288	kCLOCK_PllFllSelClk, /!< The clock after SIM[PLLFLLSEL]. /
AnnaBridge	171:3a7713b1edbc	289
AnnaBridge	171:3a7713b1edbc	290	/* ---------------------------------- OSC clock -----------------------------------*/
AnnaBridge	171:3a7713b1edbc	291	kCLOCK_Er32kClk, /!< External reference 32K clock (ERCLK32K) /
AnnaBridge	171:3a7713b1edbc	292	kCLOCK_Osc0ErClk, /!< OSC0 external reference clock (OSC0ERCLK) /
AnnaBridge	171:3a7713b1edbc	293	kCLOCK_Osc1ErClk, /!< OSC1 external reference clock (OSC1ERCLK) /
AnnaBridge	171:3a7713b1edbc	294	kCLOCK_Osc0ErClkUndiv, /!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). /
AnnaBridge	171:3a7713b1edbc	295
AnnaBridge	171:3a7713b1edbc	296	/* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
AnnaBridge	171:3a7713b1edbc	297	kCLOCK_McgFixedFreqClk, /!< MCG fixed frequency clock (MCGFFCLK) /
AnnaBridge	171:3a7713b1edbc	298	kCLOCK_McgInternalRefClk, /!< MCG internal reference clock (MCGIRCLK) /
AnnaBridge	171:3a7713b1edbc	299	kCLOCK_McgFllClk, /!< MCGFLLCLK /
AnnaBridge	171:3a7713b1edbc	300	kCLOCK_McgPll0Clk, /!< MCGPLL0CLK /
AnnaBridge	171:3a7713b1edbc	301	kCLOCK_McgPll1Clk, /!< MCGPLL1CLK /
AnnaBridge	171:3a7713b1edbc	302	kCLOCK_McgExtPllClk, /!< EXT_PLLCLK /
AnnaBridge	171:3a7713b1edbc	303	kCLOCK_McgPeriphClk, /!< MCG peripheral clock (MCGPCLK) /
AnnaBridge	171:3a7713b1edbc	304	kCLOCK_McgIrc48MClk, /!< MCG IRC48M clock /
AnnaBridge	171:3a7713b1edbc	305
AnnaBridge	171:3a7713b1edbc	306	/* --------------------------------- Other clock ----------------------------------*/
AnnaBridge	171:3a7713b1edbc	307	kCLOCK_LpoClk, /!< LPO clock /
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	} clock_name_t;
AnnaBridge	171:3a7713b1edbc	310
AnnaBridge	171:3a7713b1edbc	311	/! @brief USB clock source definition. /
AnnaBridge	171:3a7713b1edbc	312	typedef enum _clock_usb_src
AnnaBridge	171:3a7713b1edbc	313	{
AnnaBridge	171:3a7713b1edbc	314	kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(1U), /!< Use PLL0. /
AnnaBridge	171:3a7713b1edbc	315	kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(3U), /!< Use IRC48M. /
AnnaBridge	171:3a7713b1edbc	316	kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /!< Use USB_CLKIN. /
AnnaBridge	171:3a7713b1edbc	317	} clock_usb_src_t;
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	/*------------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	320
AnnaBridge	171:3a7713b1edbc	321	clock_gate_t definition:
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323	31 16 0
AnnaBridge	171:3a7713b1edbc	324	-----------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	325	\| SIM_SCGC register offset \| control bit offset in SCGC \|
AnnaBridge	171:3a7713b1edbc	326	-----------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
AnnaBridge	171:3a7713b1edbc	329	SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	kCLOCK_GateSdhc0 = (0x1030 << 16) \| 17;
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	------------------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	334
AnnaBridge	171:3a7713b1edbc	335	#define CLK_GATE_REG_OFFSET_SHIFT 16U
AnnaBridge	171:3a7713b1edbc	336	#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
AnnaBridge	171:3a7713b1edbc	337	#define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge	171:3a7713b1edbc	338	#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
AnnaBridge	171:3a7713b1edbc	339
AnnaBridge	171:3a7713b1edbc	340	#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge	171:3a7713b1edbc	341	((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) \| \
AnnaBridge	171:3a7713b1edbc	342	(((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge	171:3a7713b1edbc	343
AnnaBridge	171:3a7713b1edbc	344	#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge	171:3a7713b1edbc	345	#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge	171:3a7713b1edbc	346
AnnaBridge	171:3a7713b1edbc	347	/! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. /
AnnaBridge	171:3a7713b1edbc	348	typedef enum _clock_ip_name
AnnaBridge	171:3a7713b1edbc	349	{
AnnaBridge	171:3a7713b1edbc	350	kCLOCK_IpInvalid = 0U,
AnnaBridge	171:3a7713b1edbc	351	kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
AnnaBridge	171:3a7713b1edbc	352	kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
AnnaBridge	171:3a7713b1edbc	353	kCLOCK_Uart5 = CLK_GATE_DEFINE(0x1028U, 11U),
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	kCLOCK_Enet0 = CLK_GATE_DEFINE(0x102CU, 0U),
AnnaBridge	171:3a7713b1edbc	356	kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
AnnaBridge	171:3a7713b1edbc	357	kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
AnnaBridge	171:3a7713b1edbc	358
AnnaBridge	171:3a7713b1edbc	359	kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
AnnaBridge	171:3a7713b1edbc	360	kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
AnnaBridge	171:3a7713b1edbc	361	kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
AnnaBridge	171:3a7713b1edbc	362	kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
AnnaBridge	171:3a7713b1edbc	365	kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
AnnaBridge	171:3a7713b1edbc	366	kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
AnnaBridge	171:3a7713b1edbc	367	kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
AnnaBridge	171:3a7713b1edbc	368	kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
AnnaBridge	171:3a7713b1edbc	369	kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
AnnaBridge	171:3a7713b1edbc	370	kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
AnnaBridge	171:3a7713b1edbc	371	kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
AnnaBridge	171:3a7713b1edbc	372	kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
AnnaBridge	171:3a7713b1edbc	373	kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge	171:3a7713b1edbc	374	kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge	171:3a7713b1edbc	375	kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge	171:3a7713b1edbc	376	kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
AnnaBridge	171:3a7713b1edbc	377
AnnaBridge	171:3a7713b1edbc	378	kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
AnnaBridge	171:3a7713b1edbc	379	kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
AnnaBridge	171:3a7713b1edbc	380	kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
AnnaBridge	171:3a7713b1edbc	381	kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
AnnaBridge	171:3a7713b1edbc	382	kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
AnnaBridge	171:3a7713b1edbc	383	kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
AnnaBridge	171:3a7713b1edbc	384
AnnaBridge	171:3a7713b1edbc	385	kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
AnnaBridge	171:3a7713b1edbc	386	kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
AnnaBridge	171:3a7713b1edbc	387	kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
AnnaBridge	171:3a7713b1edbc	388	kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
AnnaBridge	171:3a7713b1edbc	389	kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
AnnaBridge	171:3a7713b1edbc	390	kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
AnnaBridge	171:3a7713b1edbc	391	kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
AnnaBridge	171:3a7713b1edbc	392	kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
AnnaBridge	171:3a7713b1edbc	393	kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
AnnaBridge	171:3a7713b1edbc	394	kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
AnnaBridge	171:3a7713b1edbc	395	kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
AnnaBridge	171:3a7713b1edbc	396	kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
AnnaBridge	171:3a7713b1edbc	397	kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
AnnaBridge	171:3a7713b1edbc	398	kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
AnnaBridge	171:3a7713b1edbc	399	kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
AnnaBridge	171:3a7713b1edbc	400	kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
AnnaBridge	171:3a7713b1edbc	401
AnnaBridge	171:3a7713b1edbc	402	kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
AnnaBridge	171:3a7713b1edbc	403	kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
AnnaBridge	171:3a7713b1edbc	404	kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
AnnaBridge	171:3a7713b1edbc	405	} clock_ip_name_t;
AnnaBridge	171:3a7713b1edbc	406
AnnaBridge	171:3a7713b1edbc	407	/!@brief SIM configuration structure for clock setting. /
AnnaBridge	171:3a7713b1edbc	408	typedef struct _sim_clock_config
AnnaBridge	171:3a7713b1edbc	409	{
AnnaBridge	171:3a7713b1edbc	410	uint8_t pllFllSel; /!< PLL/FLL/IRC48M selection. /
AnnaBridge	171:3a7713b1edbc	411	uint8_t er32kSrc; /!< ERCLK32K source selection. /
AnnaBridge	171:3a7713b1edbc	412	uint32_t clkdiv1; /!< SIM_CLKDIV1. /
AnnaBridge	171:3a7713b1edbc	413	} sim_clock_config_t;
AnnaBridge	171:3a7713b1edbc	414
AnnaBridge	171:3a7713b1edbc	415	/! @brief OSC work mode. /
AnnaBridge	171:3a7713b1edbc	416	typedef enum _osc_mode
AnnaBridge	171:3a7713b1edbc	417	{
AnnaBridge	171:3a7713b1edbc	418	kOSC_ModeExt = 0U, /!< Use an external clock. /
AnnaBridge	171:3a7713b1edbc	419	#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge	171:3a7713b1edbc	420	kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /!< Oscillator low power. /
AnnaBridge	171:3a7713b1edbc	421	#else
AnnaBridge	171:3a7713b1edbc	422	kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /!< Oscillator low power. /
AnnaBridge	171:3a7713b1edbc	423	#endif
AnnaBridge	171:3a7713b1edbc	424	kOSC_ModeOscHighGain = 0U
AnnaBridge	171:3a7713b1edbc	425	#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge	171:3a7713b1edbc	426	\|
AnnaBridge	171:3a7713b1edbc	427	MCG_C2_EREFS_MASK
AnnaBridge	171:3a7713b1edbc	428	#else
AnnaBridge	171:3a7713b1edbc	429	\|
AnnaBridge	171:3a7713b1edbc	430	MCG_C2_EREFS0_MASK
AnnaBridge	171:3a7713b1edbc	431	#endif
AnnaBridge	171:3a7713b1edbc	432	#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
AnnaBridge	171:3a7713b1edbc	433	\|
AnnaBridge	171:3a7713b1edbc	434	MCG_C2_HGO_MASK, /!< Oscillator high gain. /
AnnaBridge	171:3a7713b1edbc	435	#else
AnnaBridge	171:3a7713b1edbc	436	\|
AnnaBridge	171:3a7713b1edbc	437	MCG_C2_HGO0_MASK, /!< Oscillator high gain. /
AnnaBridge	171:3a7713b1edbc	438	#endif
AnnaBridge	171:3a7713b1edbc	439	} osc_mode_t;
AnnaBridge	171:3a7713b1edbc	440
AnnaBridge	171:3a7713b1edbc	441	/! @brief Oscillator capacitor load setting./
AnnaBridge	171:3a7713b1edbc	442	enum _osc_cap_load
AnnaBridge	171:3a7713b1edbc	443	{
AnnaBridge	171:3a7713b1edbc	444	kOSC_Cap2P = OSC_CR_SC2P_MASK, /!< 2 pF capacitor load /
AnnaBridge	171:3a7713b1edbc	445	kOSC_Cap4P = OSC_CR_SC4P_MASK, /!< 4 pF capacitor load /
AnnaBridge	171:3a7713b1edbc	446	kOSC_Cap8P = OSC_CR_SC8P_MASK, /!< 8 pF capacitor load /
AnnaBridge	171:3a7713b1edbc	447	kOSC_Cap16P = OSC_CR_SC16P_MASK /!< 16 pF capacitor load /
AnnaBridge	171:3a7713b1edbc	448	};
AnnaBridge	171:3a7713b1edbc	449
AnnaBridge	171:3a7713b1edbc	450	/! @brief OSCERCLK enable mode. /
AnnaBridge	171:3a7713b1edbc	451	enum _oscer_enable_mode
AnnaBridge	171:3a7713b1edbc	452	{
AnnaBridge	171:3a7713b1edbc	453	kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /!< Enable. /
AnnaBridge	171:3a7713b1edbc	454	kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /!< Enable in stop mode. /
AnnaBridge	171:3a7713b1edbc	455	};
AnnaBridge	171:3a7713b1edbc	456
AnnaBridge	171:3a7713b1edbc	457	/! @brief OSC configuration for OSCERCLK. /
AnnaBridge	171:3a7713b1edbc	458	typedef struct _oscer_config
AnnaBridge	171:3a7713b1edbc	459	{
AnnaBridge	171:3a7713b1edbc	460	uint8_t enableMode; /!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. /
AnnaBridge	171:3a7713b1edbc	461
AnnaBridge	171:3a7713b1edbc	462	} oscer_config_t;
AnnaBridge	171:3a7713b1edbc	463
AnnaBridge	171:3a7713b1edbc	464	/*!
AnnaBridge	171:3a7713b1edbc	465	* @brief OSC Initialization Configuration Structure
AnnaBridge	171:3a7713b1edbc	466	*
AnnaBridge	171:3a7713b1edbc	467	* Defines the configuration data structure to initialize the OSC.
AnnaBridge	171:3a7713b1edbc	468	* When porting to a new board, set the following members
AnnaBridge	171:3a7713b1edbc	469	* according to the board setting:
AnnaBridge	171:3a7713b1edbc	470	* 1. freq: The external frequency.
AnnaBridge	171:3a7713b1edbc	471	* 2. workMode: The OSC module mode.
AnnaBridge	171:3a7713b1edbc	472	*/
AnnaBridge	171:3a7713b1edbc	473	typedef struct _osc_config
AnnaBridge	171:3a7713b1edbc	474	{
AnnaBridge	171:3a7713b1edbc	475	uint32_t freq; /!< External clock frequency. /
AnnaBridge	171:3a7713b1edbc	476	uint8_t capLoad; /!< Capacitor load setting. /
AnnaBridge	171:3a7713b1edbc	477	osc_mode_t workMode; /!< OSC work mode setting. /
AnnaBridge	171:3a7713b1edbc	478	oscer_config_t oscerConfig; /!< Configuration for OSCERCLK. /
AnnaBridge	171:3a7713b1edbc	479	} osc_config_t;
AnnaBridge	171:3a7713b1edbc	480
AnnaBridge	171:3a7713b1edbc	481	/! @brief MCG FLL reference clock source select. /
AnnaBridge	171:3a7713b1edbc	482	typedef enum _mcg_fll_src
AnnaBridge	171:3a7713b1edbc	483	{
AnnaBridge	171:3a7713b1edbc	484	kMCG_FllSrcExternal, /!< External reference clock is selected /
AnnaBridge	171:3a7713b1edbc	485	kMCG_FllSrcInternal /!< The slow internal reference clock is selected /
AnnaBridge	171:3a7713b1edbc	486	} mcg_fll_src_t;
AnnaBridge	171:3a7713b1edbc	487
AnnaBridge	171:3a7713b1edbc	488	/! @brief MCG internal reference clock select /
AnnaBridge	171:3a7713b1edbc	489	typedef enum _mcg_irc_mode
AnnaBridge	171:3a7713b1edbc	490	{
AnnaBridge	171:3a7713b1edbc	491	kMCG_IrcSlow, /!< Slow internal reference clock selected /
AnnaBridge	171:3a7713b1edbc	492	kMCG_IrcFast /!< Fast internal reference clock selected /
AnnaBridge	171:3a7713b1edbc	493	} mcg_irc_mode_t;
AnnaBridge	171:3a7713b1edbc	494
AnnaBridge	171:3a7713b1edbc	495	/! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference /
AnnaBridge	171:3a7713b1edbc	496	typedef enum _mcg_dmx32
AnnaBridge	171:3a7713b1edbc	497	{
AnnaBridge	171:3a7713b1edbc	498	kMCG_Dmx32Default, /!< DCO has a default range of 25% /
AnnaBridge	171:3a7713b1edbc	499	kMCG_Dmx32Fine /!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference /
AnnaBridge	171:3a7713b1edbc	500	} mcg_dmx32_t;
AnnaBridge	171:3a7713b1edbc	501
AnnaBridge	171:3a7713b1edbc	502	/! @brief MCG DCO range select /
AnnaBridge	171:3a7713b1edbc	503	typedef enum _mcg_drs
AnnaBridge	171:3a7713b1edbc	504	{
AnnaBridge	171:3a7713b1edbc	505	kMCG_DrsLow, /!< Low frequency range /
AnnaBridge	171:3a7713b1edbc	506	kMCG_DrsMid, /!< Mid frequency range /
AnnaBridge	171:3a7713b1edbc	507	kMCG_DrsMidHigh, /!< Mid-High frequency range /
AnnaBridge	171:3a7713b1edbc	508	kMCG_DrsHigh /!< High frequency range /
AnnaBridge	171:3a7713b1edbc	509	} mcg_drs_t;
AnnaBridge	171:3a7713b1edbc	510
AnnaBridge	171:3a7713b1edbc	511	/! @brief MCG PLL reference clock select /
AnnaBridge	171:3a7713b1edbc	512	typedef enum _mcg_pll_ref_src
AnnaBridge	171:3a7713b1edbc	513	{
AnnaBridge	171:3a7713b1edbc	514	kMCG_PllRefOsc0, /!< Selects OSC0 as PLL reference clock /
AnnaBridge	171:3a7713b1edbc	515	kMCG_PllRefOsc1 /!< Selects OSC1 as PLL reference clock /
AnnaBridge	171:3a7713b1edbc	516	} mcg_pll_ref_src_t;
AnnaBridge	171:3a7713b1edbc	517
AnnaBridge	171:3a7713b1edbc	518	/! @brief MCGOUT clock source. /
AnnaBridge	171:3a7713b1edbc	519	typedef enum _mcg_clkout_src
AnnaBridge	171:3a7713b1edbc	520	{
AnnaBridge	171:3a7713b1edbc	521	kMCG_ClkOutSrcOut, /!< Output of the FLL is selected (reset default) /
AnnaBridge	171:3a7713b1edbc	522	kMCG_ClkOutSrcInternal, /!< Internal reference clock is selected /
AnnaBridge	171:3a7713b1edbc	523	kMCG_ClkOutSrcExternal, /!< External reference clock is selected /
AnnaBridge	171:3a7713b1edbc	524	} mcg_clkout_src_t;
AnnaBridge	171:3a7713b1edbc	525
AnnaBridge	171:3a7713b1edbc	526	/! @brief MCG Automatic Trim Machine Select /
AnnaBridge	171:3a7713b1edbc	527	typedef enum _mcg_atm_select
AnnaBridge	171:3a7713b1edbc	528	{
AnnaBridge	171:3a7713b1edbc	529	kMCG_AtmSel32k, /!< 32 kHz Internal Reference Clock selected /
AnnaBridge	171:3a7713b1edbc	530	kMCG_AtmSel4m /!< 4 MHz Internal Reference Clock selected /
AnnaBridge	171:3a7713b1edbc	531	} mcg_atm_select_t;
AnnaBridge	171:3a7713b1edbc	532
AnnaBridge	171:3a7713b1edbc	533	/! @brief MCG OSC Clock Select /
AnnaBridge	171:3a7713b1edbc	534	typedef enum _mcg_oscsel
AnnaBridge	171:3a7713b1edbc	535	{
AnnaBridge	171:3a7713b1edbc	536	kMCG_OscselOsc, /!< Selects System Oscillator (OSCCLK) /
AnnaBridge	171:3a7713b1edbc	537	kMCG_OscselRtc, /!< Selects 32 kHz RTC Oscillator /
AnnaBridge	171:3a7713b1edbc	538	kMCG_OscselIrc /!< Selects 48 MHz IRC Oscillator /
AnnaBridge	171:3a7713b1edbc	539	} mcg_oscsel_t;
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	/! @brief MCG PLLCS select /
AnnaBridge	171:3a7713b1edbc	542	typedef enum _mcg_pll_clk_select
AnnaBridge	171:3a7713b1edbc	543	{
AnnaBridge	171:3a7713b1edbc	544	kMCG_PllClkSelPll0, /!< PLL0 output clock is selected /
AnnaBridge	171:3a7713b1edbc	545	kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
AnnaBridge	171:3a7713b1edbc	546	} mcg_pll_clk_select_t;
AnnaBridge	171:3a7713b1edbc	547
AnnaBridge	171:3a7713b1edbc	548	/! @brief MCG clock monitor mode. /
AnnaBridge	171:3a7713b1edbc	549	typedef enum _mcg_monitor_mode
AnnaBridge	171:3a7713b1edbc	550	{
AnnaBridge	171:3a7713b1edbc	551	kMCG_MonitorNone, /!< Clock monitor is disabled. /
AnnaBridge	171:3a7713b1edbc	552	kMCG_MonitorInt, /!< Trigger interrupt when clock lost. /
AnnaBridge	171:3a7713b1edbc	553	kMCG_MonitorReset /!< System reset when clock lost. /
AnnaBridge	171:3a7713b1edbc	554	} mcg_monitor_mode_t;
AnnaBridge	171:3a7713b1edbc	555
AnnaBridge	171:3a7713b1edbc	556	/! @brief MCG status. /
AnnaBridge	171:3a7713b1edbc	557	enum _mcg_status
AnnaBridge	171:3a7713b1edbc	558	{
AnnaBridge	171:3a7713b1edbc	559	kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /!< Can't switch to target mode. /
AnnaBridge	171:3a7713b1edbc	560	kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
AnnaBridge	171:3a7713b1edbc	561	function. */
AnnaBridge	171:3a7713b1edbc	562	kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /!< Invalid bus clock for ATM. /
AnnaBridge	171:3a7713b1edbc	563	kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /!< Invalid desired frequency for ATM. /
AnnaBridge	171:3a7713b1edbc	564	kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /!< IRC is used when using ATM. /
AnnaBridge	171:3a7713b1edbc	565	kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /!< Hardware fail occurs during ATM. /
AnnaBridge	171:3a7713b1edbc	566	kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
AnnaBridge	171:3a7713b1edbc	567	it is in use. */
AnnaBridge	171:3a7713b1edbc	568	};
AnnaBridge	171:3a7713b1edbc	569
AnnaBridge	171:3a7713b1edbc	570	/! @brief MCG status flags. /
AnnaBridge	171:3a7713b1edbc	571	enum _mcg_status_flags_t
AnnaBridge	171:3a7713b1edbc	572	{
AnnaBridge	171:3a7713b1edbc	573	kMCG_Osc0LostFlag = (1U << 0U), /!< OSC0 lost. /
AnnaBridge	171:3a7713b1edbc	574	kMCG_Osc0InitFlag = (1U << 1U), /!< OSC0 crystal initialized. /
AnnaBridge	171:3a7713b1edbc	575	kMCG_RtcOscLostFlag = (1U << 4U), /!< RTC OSC lost. /
AnnaBridge	171:3a7713b1edbc	576	kMCG_Pll0LostFlag = (1U << 5U), /!< PLL0 lost. /
AnnaBridge	171:3a7713b1edbc	577	kMCG_Pll0LockFlag = (1U << 6U), /!< PLL0 locked. /
AnnaBridge	171:3a7713b1edbc	578	};
AnnaBridge	171:3a7713b1edbc	579
AnnaBridge	171:3a7713b1edbc	580	/! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. /
AnnaBridge	171:3a7713b1edbc	581	enum _mcg_irclk_enable_mode
AnnaBridge	171:3a7713b1edbc	582	{
AnnaBridge	171:3a7713b1edbc	583	kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /!< MCGIRCLK enable. /
AnnaBridge	171:3a7713b1edbc	584	kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /!< MCGIRCLK enable in stop mode. /
AnnaBridge	171:3a7713b1edbc	585	};
AnnaBridge	171:3a7713b1edbc	586
AnnaBridge	171:3a7713b1edbc	587	/! @brief MCG PLL clock enable mode definition. /
AnnaBridge	171:3a7713b1edbc	588	enum _mcg_pll_enable_mode
AnnaBridge	171:3a7713b1edbc	589	{
AnnaBridge	171:3a7713b1edbc	590	kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
AnnaBridge	171:3a7713b1edbc	591	MCG clock mode. Generally, the PLL
AnnaBridge	171:3a7713b1edbc	592	is disabled in FLL modes
AnnaBridge	171:3a7713b1edbc	593	(FEI/FBI/FEE/FBE). Setting the PLL clock
AnnaBridge	171:3a7713b1edbc	594	enable independent, enables the
AnnaBridge	171:3a7713b1edbc	595	PLL in the FLL modes. */
AnnaBridge	171:3a7713b1edbc	596	kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /!< MCGPLLCLK enable in STOP mode. /
AnnaBridge	171:3a7713b1edbc	597	};
AnnaBridge	171:3a7713b1edbc	598
AnnaBridge	171:3a7713b1edbc	599	/! @brief MCG mode definitions /
AnnaBridge	171:3a7713b1edbc	600	typedef enum _mcg_mode
AnnaBridge	171:3a7713b1edbc	601	{
AnnaBridge	171:3a7713b1edbc	602	kMCG_ModeFEI = 0U, /!< FEI - FLL Engaged Internal /
AnnaBridge	171:3a7713b1edbc	603	kMCG_ModeFBI, /!< FBI - FLL Bypassed Internal /
AnnaBridge	171:3a7713b1edbc	604	kMCG_ModeBLPI, /!< BLPI - Bypassed Low Power Internal /
AnnaBridge	171:3a7713b1edbc	605	kMCG_ModeFEE, /!< FEE - FLL Engaged External /
AnnaBridge	171:3a7713b1edbc	606	kMCG_ModeFBE, /!< FBE - FLL Bypassed External /
AnnaBridge	171:3a7713b1edbc	607	kMCG_ModeBLPE, /!< BLPE - Bypassed Low Power External /
AnnaBridge	171:3a7713b1edbc	608	kMCG_ModePBE, /!< PBE - PLL Bypassed External /
AnnaBridge	171:3a7713b1edbc	609	kMCG_ModePEE, /!< PEE - PLL Engaged External /
AnnaBridge	171:3a7713b1edbc	610	kMCG_ModeError /!< Unknown mode /
AnnaBridge	171:3a7713b1edbc	611	} mcg_mode_t;
AnnaBridge	171:3a7713b1edbc	612
AnnaBridge	171:3a7713b1edbc	613	/! @brief MCG PLL configuration. /
AnnaBridge	171:3a7713b1edbc	614	typedef struct _mcg_pll_config
AnnaBridge	171:3a7713b1edbc	615	{
AnnaBridge	171:3a7713b1edbc	616	uint8_t enableMode; /!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. /
AnnaBridge	171:3a7713b1edbc	617	uint8_t prdiv; /!< Reference divider PRDIV. /
AnnaBridge	171:3a7713b1edbc	618	uint8_t vdiv; /!< VCO divider VDIV. /
AnnaBridge	171:3a7713b1edbc	619	} mcg_pll_config_t;
AnnaBridge	171:3a7713b1edbc	620
AnnaBridge	171:3a7713b1edbc	621	/*! @brief MCG mode change configuration structure
AnnaBridge	171:3a7713b1edbc	622	*
AnnaBridge	171:3a7713b1edbc	623	* When porting to a new board, set the following members
AnnaBridge	171:3a7713b1edbc	624	* according to the board setting:
AnnaBridge	171:3a7713b1edbc	625	* 1. frdiv: If the FLL uses the external reference clock, set this
AnnaBridge	171:3a7713b1edbc	626	* value to ensure that the external reference clock divided by frdiv is
AnnaBridge	171:3a7713b1edbc	627	* in the 31.25 kHz to 39.0625 kHz range.
AnnaBridge	171:3a7713b1edbc	628	* 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
AnnaBridge	171:3a7713b1edbc	629	* PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
AnnaBridge	171:3a7713b1edbc	630	* FSL_FEATURE_MCG_PLL_REF_MAX range.
AnnaBridge	171:3a7713b1edbc	631	*/
AnnaBridge	171:3a7713b1edbc	632	typedef struct _mcg_config
AnnaBridge	171:3a7713b1edbc	633	{
AnnaBridge	171:3a7713b1edbc	634	mcg_mode_t mcgMode; /!< MCG mode. /
AnnaBridge	171:3a7713b1edbc	635
AnnaBridge	171:3a7713b1edbc	636	/* ----------------------- MCGIRCCLK settings ------------------------ */
AnnaBridge	171:3a7713b1edbc	637	uint8_t irclkEnableMode; /!< MCGIRCLK enable mode. /
AnnaBridge	171:3a7713b1edbc	638	mcg_irc_mode_t ircs; /!< Source, MCG_C2[IRCS]. /
AnnaBridge	171:3a7713b1edbc	639	uint8_t fcrdiv; /!< Divider, MCG_SC[FCRDIV]. /
AnnaBridge	171:3a7713b1edbc	640
AnnaBridge	171:3a7713b1edbc	641	/* ------------------------ MCG FLL settings ------------------------- */
AnnaBridge	171:3a7713b1edbc	642	uint8_t frdiv; /!< Divider MCG_C1[FRDIV]. /
AnnaBridge	171:3a7713b1edbc	643	mcg_drs_t drs; /!< DCO range MCG_C4[DRST_DRS]. /
AnnaBridge	171:3a7713b1edbc	644	mcg_dmx32_t dmx32; /!< MCG_C4[DMX32]. /
AnnaBridge	171:3a7713b1edbc	645	mcg_oscsel_t oscsel; /!< OSC select MCG_C7[OSCSEL]. /
AnnaBridge	171:3a7713b1edbc	646
AnnaBridge	171:3a7713b1edbc	647	/* ------------------------ MCG PLL settings ------------------------- */
AnnaBridge	171:3a7713b1edbc	648	mcg_pll_config_t pll0Config; /!< MCGPLL0CLK configuration. /
AnnaBridge	171:3a7713b1edbc	649
AnnaBridge	171:3a7713b1edbc	650	} mcg_config_t;
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	653	* API
AnnaBridge	171:3a7713b1edbc	654	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	655
AnnaBridge	171:3a7713b1edbc	656	#if defined(__cplusplus)
AnnaBridge	171:3a7713b1edbc	657	extern "C" {
AnnaBridge	171:3a7713b1edbc	658	#endif /* __cplusplus */
AnnaBridge	171:3a7713b1edbc	659
AnnaBridge	171:3a7713b1edbc	660	/*!
AnnaBridge	171:3a7713b1edbc	661	* @brief Enable the clock for specific IP.
AnnaBridge	171:3a7713b1edbc	662	*
AnnaBridge	171:3a7713b1edbc	663	* @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge	171:3a7713b1edbc	664	*/
AnnaBridge	171:3a7713b1edbc	665	static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge	171:3a7713b1edbc	666	{
AnnaBridge	171:3a7713b1edbc	667	uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge	171:3a7713b1edbc	668	((volatile uint32_t )regAddr) \|= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge	171:3a7713b1edbc	669	}
AnnaBridge	171:3a7713b1edbc	670
AnnaBridge	171:3a7713b1edbc	671	/*!
AnnaBridge	171:3a7713b1edbc	672	* @brief Disable the clock for specific IP.
AnnaBridge	171:3a7713b1edbc	673	*
AnnaBridge	171:3a7713b1edbc	674	* @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge	171:3a7713b1edbc	675	*/
AnnaBridge	171:3a7713b1edbc	676	static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge	171:3a7713b1edbc	677	{
AnnaBridge	171:3a7713b1edbc	678	uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge	171:3a7713b1edbc	679	((volatile uint32_t )regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge	171:3a7713b1edbc	680	}
AnnaBridge	171:3a7713b1edbc	681
AnnaBridge	171:3a7713b1edbc	682	/*!
AnnaBridge	171:3a7713b1edbc	683	* @brief Set ERCLK32K source.
AnnaBridge	171:3a7713b1edbc	684	*
AnnaBridge	171:3a7713b1edbc	685	* @param src The value to set ERCLK32K clock source.
AnnaBridge	171:3a7713b1edbc	686	*/
AnnaBridge	171:3a7713b1edbc	687	static inline void CLOCK_SetEr32kClock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	688	{
AnnaBridge	171:3a7713b1edbc	689	SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) \| SIM_SOPT1_OSC32KSEL(src));
AnnaBridge	171:3a7713b1edbc	690	}
AnnaBridge	171:3a7713b1edbc	691
AnnaBridge	171:3a7713b1edbc	692	/*!
AnnaBridge	171:3a7713b1edbc	693	* @brief Set SDHC0 clock source.
AnnaBridge	171:3a7713b1edbc	694	*
AnnaBridge	171:3a7713b1edbc	695	* @param src The value to set SDHC0 clock source.
AnnaBridge	171:3a7713b1edbc	696	*/
AnnaBridge	171:3a7713b1edbc	697	static inline void CLOCK_SetSdhc0Clock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	698	{
AnnaBridge	171:3a7713b1edbc	699	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) \| SIM_SOPT2_SDHCSRC(src));
AnnaBridge	171:3a7713b1edbc	700	}
AnnaBridge	171:3a7713b1edbc	701
AnnaBridge	171:3a7713b1edbc	702	/*!
AnnaBridge	171:3a7713b1edbc	703	* @brief Set enet timestamp clock source.
AnnaBridge	171:3a7713b1edbc	704	*
AnnaBridge	171:3a7713b1edbc	705	* @param src The value to set enet timestamp clock source.
AnnaBridge	171:3a7713b1edbc	706	*/
AnnaBridge	171:3a7713b1edbc	707	static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	708	{
AnnaBridge	171:3a7713b1edbc	709	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) \| SIM_SOPT2_TIMESRC(src));
AnnaBridge	171:3a7713b1edbc	710	}
AnnaBridge	171:3a7713b1edbc	711
AnnaBridge	171:3a7713b1edbc	712	/*!
AnnaBridge	171:3a7713b1edbc	713	* @brief Set RMII clock source.
AnnaBridge	171:3a7713b1edbc	714	*
AnnaBridge	171:3a7713b1edbc	715	* @param src The value to set RMII clock source.
AnnaBridge	171:3a7713b1edbc	716	*/
AnnaBridge	171:3a7713b1edbc	717	static inline void CLOCK_SetRmii0Clock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	718	{
AnnaBridge	171:3a7713b1edbc	719	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) \| SIM_SOPT2_RMIISRC(src));
AnnaBridge	171:3a7713b1edbc	720	}
AnnaBridge	171:3a7713b1edbc	721
AnnaBridge	171:3a7713b1edbc	722	/*!
AnnaBridge	171:3a7713b1edbc	723	* @brief Set debug trace clock source.
AnnaBridge	171:3a7713b1edbc	724	*
AnnaBridge	171:3a7713b1edbc	725	* @param src The value to set debug trace clock source.
AnnaBridge	171:3a7713b1edbc	726	*/
AnnaBridge	171:3a7713b1edbc	727	static inline void CLOCK_SetTraceClock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	728	{
AnnaBridge	171:3a7713b1edbc	729	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) \| SIM_SOPT2_TRACECLKSEL(src));
AnnaBridge	171:3a7713b1edbc	730	}
AnnaBridge	171:3a7713b1edbc	731
AnnaBridge	171:3a7713b1edbc	732	/*!
AnnaBridge	171:3a7713b1edbc	733	* @brief Set PLLFLLSEL clock source.
AnnaBridge	171:3a7713b1edbc	734	*
AnnaBridge	171:3a7713b1edbc	735	* @param src The value to set PLLFLLSEL clock source.
AnnaBridge	171:3a7713b1edbc	736	*/
AnnaBridge	171:3a7713b1edbc	737	static inline void CLOCK_SetPllFllSelClock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	738	{
AnnaBridge	171:3a7713b1edbc	739	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) \| SIM_SOPT2_PLLFLLSEL(src));
AnnaBridge	171:3a7713b1edbc	740	}
AnnaBridge	171:3a7713b1edbc	741
AnnaBridge	171:3a7713b1edbc	742	/*!
AnnaBridge	171:3a7713b1edbc	743	* @brief Set CLKOUT source.
AnnaBridge	171:3a7713b1edbc	744	*
AnnaBridge	171:3a7713b1edbc	745	* @param src The value to set CLKOUT source.
AnnaBridge	171:3a7713b1edbc	746	*/
AnnaBridge	171:3a7713b1edbc	747	static inline void CLOCK_SetClkOutClock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	748	{
AnnaBridge	171:3a7713b1edbc	749	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) \| SIM_SOPT2_CLKOUTSEL(src));
AnnaBridge	171:3a7713b1edbc	750	}
AnnaBridge	171:3a7713b1edbc	751
AnnaBridge	171:3a7713b1edbc	752	/*!
AnnaBridge	171:3a7713b1edbc	753	* @brief Set RTC_CLKOUT source.
AnnaBridge	171:3a7713b1edbc	754	*
AnnaBridge	171:3a7713b1edbc	755	* @param src The value to set RTC_CLKOUT source.
AnnaBridge	171:3a7713b1edbc	756	*/
AnnaBridge	171:3a7713b1edbc	757	static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
AnnaBridge	171:3a7713b1edbc	758	{
AnnaBridge	171:3a7713b1edbc	759	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) \| SIM_SOPT2_RTCCLKOUTSEL(src));
AnnaBridge	171:3a7713b1edbc	760	}
AnnaBridge	171:3a7713b1edbc	761
AnnaBridge	171:3a7713b1edbc	762	/*! @brief Enable USB FS clock.
AnnaBridge	171:3a7713b1edbc	763	*
AnnaBridge	171:3a7713b1edbc	764	* @param src USB FS clock source.
AnnaBridge	171:3a7713b1edbc	765	* @param freq The frequency specified by src.
AnnaBridge	171:3a7713b1edbc	766	* @retval true The clock is set successfully.
AnnaBridge	171:3a7713b1edbc	767	* @retval false The clock source is invalid to get proper USB FS clock.
AnnaBridge	171:3a7713b1edbc	768	*/
AnnaBridge	171:3a7713b1edbc	769	bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771	/*! @brief Disable USB FS clock.
AnnaBridge	171:3a7713b1edbc	772	*
AnnaBridge	171:3a7713b1edbc	773	* Disable USB FS clock.
AnnaBridge	171:3a7713b1edbc	774	*/
AnnaBridge	171:3a7713b1edbc	775	static inline void CLOCK_DisableUsbfs0Clock(void)
AnnaBridge	171:3a7713b1edbc	776	{
AnnaBridge	171:3a7713b1edbc	777	CLOCK_DisableClock(kCLOCK_Usbfs0);
AnnaBridge	171:3a7713b1edbc	778	}
AnnaBridge	171:3a7713b1edbc	779
AnnaBridge	171:3a7713b1edbc	780	/*!
AnnaBridge	171:3a7713b1edbc	781	* @brief System clock divider
AnnaBridge	171:3a7713b1edbc	782	*
AnnaBridge	171:3a7713b1edbc	783	* Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
AnnaBridge	171:3a7713b1edbc	784	*
AnnaBridge	171:3a7713b1edbc	785	* @param outdiv1 Clock 1 output divider value.
AnnaBridge	171:3a7713b1edbc	786	*
AnnaBridge	171:3a7713b1edbc	787	* @param outdiv2 Clock 2 output divider value.
AnnaBridge	171:3a7713b1edbc	788	*
AnnaBridge	171:3a7713b1edbc	789	* @param outdiv3 Clock 3 output divider value.
AnnaBridge	171:3a7713b1edbc	790	*
AnnaBridge	171:3a7713b1edbc	791	* @param outdiv4 Clock 4 output divider value.
AnnaBridge	171:3a7713b1edbc	792	*/
AnnaBridge	171:3a7713b1edbc	793	static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
AnnaBridge	171:3a7713b1edbc	794	{
AnnaBridge	171:3a7713b1edbc	795	SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) \| SIM_CLKDIV1_OUTDIV2(outdiv2) \| SIM_CLKDIV1_OUTDIV3(outdiv3) \|
AnnaBridge	171:3a7713b1edbc	796	SIM_CLKDIV1_OUTDIV4(outdiv4);
AnnaBridge	171:3a7713b1edbc	797	}
AnnaBridge	171:3a7713b1edbc	798
AnnaBridge	171:3a7713b1edbc	799	/*!
AnnaBridge	171:3a7713b1edbc	800	* @brief Gets the clock frequency for a specific clock name.
AnnaBridge	171:3a7713b1edbc	801	*
AnnaBridge	171:3a7713b1edbc	802	* This function checks the current clock configurations and then calculates
AnnaBridge	171:3a7713b1edbc	803	* the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge	171:3a7713b1edbc	804	* The MCG must be properly configured before using this function.
AnnaBridge	171:3a7713b1edbc	805	*
AnnaBridge	171:3a7713b1edbc	806	* @param clockName Clock names defined in clock_name_t
AnnaBridge	171:3a7713b1edbc	807	* @return Clock frequency value in Hertz
AnnaBridge	171:3a7713b1edbc	808	*/
AnnaBridge	171:3a7713b1edbc	809	uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge	171:3a7713b1edbc	810
AnnaBridge	171:3a7713b1edbc	811	/*!
AnnaBridge	171:3a7713b1edbc	812	* @brief Get the core clock or system clock frequency.
AnnaBridge	171:3a7713b1edbc	813	*
AnnaBridge	171:3a7713b1edbc	814	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	815	*/
AnnaBridge	171:3a7713b1edbc	816	uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge	171:3a7713b1edbc	817
AnnaBridge	171:3a7713b1edbc	818	/*!
AnnaBridge	171:3a7713b1edbc	819	* @brief Get the platform clock frequency.
AnnaBridge	171:3a7713b1edbc	820	*
AnnaBridge	171:3a7713b1edbc	821	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	822	*/
AnnaBridge	171:3a7713b1edbc	823	uint32_t CLOCK_GetPlatClkFreq(void);
AnnaBridge	171:3a7713b1edbc	824
AnnaBridge	171:3a7713b1edbc	825	/*!
AnnaBridge	171:3a7713b1edbc	826	* @brief Get the bus clock frequency.
AnnaBridge	171:3a7713b1edbc	827	*
AnnaBridge	171:3a7713b1edbc	828	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	829	*/
AnnaBridge	171:3a7713b1edbc	830	uint32_t CLOCK_GetBusClkFreq(void);
AnnaBridge	171:3a7713b1edbc	831
AnnaBridge	171:3a7713b1edbc	832	/*!
AnnaBridge	171:3a7713b1edbc	833	* @brief Get the flexbus clock frequency.
AnnaBridge	171:3a7713b1edbc	834	*
AnnaBridge	171:3a7713b1edbc	835	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	836	*/
AnnaBridge	171:3a7713b1edbc	837	uint32_t CLOCK_GetFlexBusClkFreq(void);
AnnaBridge	171:3a7713b1edbc	838
AnnaBridge	171:3a7713b1edbc	839	/*!
AnnaBridge	171:3a7713b1edbc	840	* @brief Get the flash clock frequency.
AnnaBridge	171:3a7713b1edbc	841	*
AnnaBridge	171:3a7713b1edbc	842	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	843	*/
AnnaBridge	171:3a7713b1edbc	844	uint32_t CLOCK_GetFlashClkFreq(void);
AnnaBridge	171:3a7713b1edbc	845
AnnaBridge	171:3a7713b1edbc	846	/*!
AnnaBridge	171:3a7713b1edbc	847	* @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
AnnaBridge	171:3a7713b1edbc	848	*
AnnaBridge	171:3a7713b1edbc	849	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	850	*/
AnnaBridge	171:3a7713b1edbc	851	uint32_t CLOCK_GetPllFllSelClkFreq(void);
AnnaBridge	171:3a7713b1edbc	852
AnnaBridge	171:3a7713b1edbc	853	/*!
AnnaBridge	171:3a7713b1edbc	854	* @brief Get the external reference 32K clock frequency (ERCLK32K).
AnnaBridge	171:3a7713b1edbc	855	*
AnnaBridge	171:3a7713b1edbc	856	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	857	*/
AnnaBridge	171:3a7713b1edbc	858	uint32_t CLOCK_GetEr32kClkFreq(void);
AnnaBridge	171:3a7713b1edbc	859
AnnaBridge	171:3a7713b1edbc	860	/*!
AnnaBridge	171:3a7713b1edbc	861	* @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
AnnaBridge	171:3a7713b1edbc	862	*
AnnaBridge	171:3a7713b1edbc	863	* @return Clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	864	*/
AnnaBridge	171:3a7713b1edbc	865	uint32_t CLOCK_GetOsc0ErClkFreq(void);
AnnaBridge	171:3a7713b1edbc	866
AnnaBridge	171:3a7713b1edbc	867	/*!
AnnaBridge	171:3a7713b1edbc	868	* @brief Set the clock configure in SIM module.
AnnaBridge	171:3a7713b1edbc	869	*
AnnaBridge	171:3a7713b1edbc	870	* This function sets system layer clock settings in SIM module.
AnnaBridge	171:3a7713b1edbc	871	*
AnnaBridge	171:3a7713b1edbc	872	* @param config Pointer to the configure structure.
AnnaBridge	171:3a7713b1edbc	873	*/
AnnaBridge	171:3a7713b1edbc	874	void CLOCK_SetSimConfig(sim_clock_config_t const *config);
AnnaBridge	171:3a7713b1edbc	875
AnnaBridge	171:3a7713b1edbc	876	/*!
AnnaBridge	171:3a7713b1edbc	877	* @brief Set the system clock dividers in SIM to safe value.
AnnaBridge	171:3a7713b1edbc	878	*
AnnaBridge	171:3a7713b1edbc	879	* The system level clocks (core clock, bus clock, flexbus clock and flash clock)
AnnaBridge	171:3a7713b1edbc	880	* must be in allowed ranges. During MCG clock mode switch, the MCG output clock
AnnaBridge	171:3a7713b1edbc	881	* changes then the system level clocks may be out of range. This function could
AnnaBridge	171:3a7713b1edbc	882	* be used before MCG mode change, to make sure system level clocks are in allowed
AnnaBridge	171:3a7713b1edbc	883	* range.
AnnaBridge	171:3a7713b1edbc	884	*
AnnaBridge	171:3a7713b1edbc	885	* @param config Pointer to the configure structure.
AnnaBridge	171:3a7713b1edbc	886	*/
AnnaBridge	171:3a7713b1edbc	887	static inline void CLOCK_SetSimSafeDivs(void)
AnnaBridge	171:3a7713b1edbc	888	{
AnnaBridge	171:3a7713b1edbc	889	SIM->CLKDIV1 = 0x01240000U;
AnnaBridge	171:3a7713b1edbc	890	}
AnnaBridge	171:3a7713b1edbc	891
AnnaBridge	171:3a7713b1edbc	892	/! @name MCG frequency functions. /
AnnaBridge	171:3a7713b1edbc	893	/@{/
AnnaBridge	171:3a7713b1edbc	894
AnnaBridge	171:3a7713b1edbc	895	/*!
AnnaBridge	171:3a7713b1edbc	896	* @brief Gets the MCG output clock (MCGOUTCLK) frequency.
AnnaBridge	171:3a7713b1edbc	897	*
AnnaBridge	171:3a7713b1edbc	898	* This function gets the MCG output clock frequency in Hz based on the current MCG
AnnaBridge	171:3a7713b1edbc	899	* register value.
AnnaBridge	171:3a7713b1edbc	900	*
AnnaBridge	171:3a7713b1edbc	901	* @return The frequency of MCGOUTCLK.
AnnaBridge	171:3a7713b1edbc	902	*/
AnnaBridge	171:3a7713b1edbc	903	uint32_t CLOCK_GetOutClkFreq(void);
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	/*!
AnnaBridge	171:3a7713b1edbc	906	* @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
AnnaBridge	171:3a7713b1edbc	907	*
AnnaBridge	171:3a7713b1edbc	908	* This function gets the MCG FLL clock frequency in Hz based on the current MCG
AnnaBridge	171:3a7713b1edbc	909	* register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
AnnaBridge	171:3a7713b1edbc	910	* disabled in low power state in other modes.
AnnaBridge	171:3a7713b1edbc	911	*
AnnaBridge	171:3a7713b1edbc	912	* @return The frequency of MCGFLLCLK.
AnnaBridge	171:3a7713b1edbc	913	*/
AnnaBridge	171:3a7713b1edbc	914	uint32_t CLOCK_GetFllFreq(void);
AnnaBridge	171:3a7713b1edbc	915
AnnaBridge	171:3a7713b1edbc	916	/*!
AnnaBridge	171:3a7713b1edbc	917	* @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
AnnaBridge	171:3a7713b1edbc	918	*
AnnaBridge	171:3a7713b1edbc	919	* This function gets the MCG internal reference clock frequency in Hz based
AnnaBridge	171:3a7713b1edbc	920	* on the current MCG register value.
AnnaBridge	171:3a7713b1edbc	921	*
AnnaBridge	171:3a7713b1edbc	922	* @return The frequency of MCGIRCLK.
AnnaBridge	171:3a7713b1edbc	923	*/
AnnaBridge	171:3a7713b1edbc	924	uint32_t CLOCK_GetInternalRefClkFreq(void);
AnnaBridge	171:3a7713b1edbc	925
AnnaBridge	171:3a7713b1edbc	926	/*!
AnnaBridge	171:3a7713b1edbc	927	* @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
AnnaBridge	171:3a7713b1edbc	928	*
AnnaBridge	171:3a7713b1edbc	929	* This function gets the MCG fixed frequency clock frequency in Hz based
AnnaBridge	171:3a7713b1edbc	930	* on the current MCG register value.
AnnaBridge	171:3a7713b1edbc	931	*
AnnaBridge	171:3a7713b1edbc	932	* @return The frequency of MCGFFCLK.
AnnaBridge	171:3a7713b1edbc	933	*/
AnnaBridge	171:3a7713b1edbc	934	uint32_t CLOCK_GetFixedFreqClkFreq(void);
AnnaBridge	171:3a7713b1edbc	935
AnnaBridge	171:3a7713b1edbc	936	/*!
AnnaBridge	171:3a7713b1edbc	937	* @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
AnnaBridge	171:3a7713b1edbc	938	*
AnnaBridge	171:3a7713b1edbc	939	* This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
AnnaBridge	171:3a7713b1edbc	940	* register value.
AnnaBridge	171:3a7713b1edbc	941	*
AnnaBridge	171:3a7713b1edbc	942	* @return The frequency of MCGPLL0CLK.
AnnaBridge	171:3a7713b1edbc	943	*/
AnnaBridge	171:3a7713b1edbc	944	uint32_t CLOCK_GetPll0Freq(void);
AnnaBridge	171:3a7713b1edbc	945
AnnaBridge	171:3a7713b1edbc	946	/@}/
AnnaBridge	171:3a7713b1edbc	947
AnnaBridge	171:3a7713b1edbc	948	/! @name MCG clock configuration. /
AnnaBridge	171:3a7713b1edbc	949	/@{/
AnnaBridge	171:3a7713b1edbc	950
AnnaBridge	171:3a7713b1edbc	951	/*!
AnnaBridge	171:3a7713b1edbc	952	* @brief Enables or disables the MCG low power.
AnnaBridge	171:3a7713b1edbc	953	*
AnnaBridge	171:3a7713b1edbc	954	* Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
AnnaBridge	171:3a7713b1edbc	955	* in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
AnnaBridge	171:3a7713b1edbc	956	* PBI modes, enabling low power sets the MCG to BLPI mode.
AnnaBridge	171:3a7713b1edbc	957	* When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
AnnaBridge	171:3a7713b1edbc	958	*
AnnaBridge	171:3a7713b1edbc	959	* @param enable True to enable MCG low power, false to disable MCG low power.
AnnaBridge	171:3a7713b1edbc	960	*/
AnnaBridge	171:3a7713b1edbc	961	static inline void CLOCK_SetLowPowerEnable(bool enable)
AnnaBridge	171:3a7713b1edbc	962	{
AnnaBridge	171:3a7713b1edbc	963	if (enable)
AnnaBridge	171:3a7713b1edbc	964	{
AnnaBridge	171:3a7713b1edbc	965	MCG->C2 \|= MCG_C2_LP_MASK;
AnnaBridge	171:3a7713b1edbc	966	}
AnnaBridge	171:3a7713b1edbc	967	else
AnnaBridge	171:3a7713b1edbc	968	{
AnnaBridge	171:3a7713b1edbc	969	MCG->C2 &= ~MCG_C2_LP_MASK;
AnnaBridge	171:3a7713b1edbc	970	}
AnnaBridge	171:3a7713b1edbc	971	}
AnnaBridge	171:3a7713b1edbc	972
AnnaBridge	171:3a7713b1edbc	973	/*!
AnnaBridge	171:3a7713b1edbc	974	* @brief Configures the Internal Reference clock (MCGIRCLK).
AnnaBridge	171:3a7713b1edbc	975	*
AnnaBridge	171:3a7713b1edbc	976	* This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
AnnaBridge	171:3a7713b1edbc	977	* source. If the fast IRC is used, this function sets the fast IRC divider.
AnnaBridge	171:3a7713b1edbc	978	* This function also sets whether the \c MCGIRCLK is enabled in stop mode.
AnnaBridge	171:3a7713b1edbc	979	* Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
AnnaBridge	171:3a7713b1edbc	980	* using the function in these modes it is not allowed.
AnnaBridge	171:3a7713b1edbc	981	*
AnnaBridge	171:3a7713b1edbc	982	* @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge	171:3a7713b1edbc	983	* @param ircs MCGIRCLK clock source, choose fast or slow.
AnnaBridge	171:3a7713b1edbc	984	* @param fcrdiv Fast IRC divider setting (\c FCRDIV).
AnnaBridge	171:3a7713b1edbc	985	* @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
AnnaBridge	171:3a7713b1edbc	986	* the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge	171:3a7713b1edbc	987	* @retval kStatus_Success MCGIRCLK configuration finished successfully.
AnnaBridge	171:3a7713b1edbc	988	*/
AnnaBridge	171:3a7713b1edbc	989	status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
AnnaBridge	171:3a7713b1edbc	990
AnnaBridge	171:3a7713b1edbc	991	/*!
AnnaBridge	171:3a7713b1edbc	992	* @brief Selects the MCG external reference clock.
AnnaBridge	171:3a7713b1edbc	993	*
AnnaBridge	171:3a7713b1edbc	994	* Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
AnnaBridge	171:3a7713b1edbc	995	* and waits for the clock source to be stable. Because the external reference
AnnaBridge	171:3a7713b1edbc	996	* clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
AnnaBridge	171:3a7713b1edbc	997	*
AnnaBridge	171:3a7713b1edbc	998	* @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
AnnaBridge	171:3a7713b1edbc	999	* @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
AnnaBridge	171:3a7713b1edbc	1000	* the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge	171:3a7713b1edbc	1001	* @retval kStatus_Success External reference clock set successfully.
AnnaBridge	171:3a7713b1edbc	1002	*/
AnnaBridge	171:3a7713b1edbc	1003	status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
AnnaBridge	171:3a7713b1edbc	1004
AnnaBridge	171:3a7713b1edbc	1005	/*!
AnnaBridge	171:3a7713b1edbc	1006	* @brief Set the FLL external reference clock divider value.
AnnaBridge	171:3a7713b1edbc	1007	*
AnnaBridge	171:3a7713b1edbc	1008	* Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
AnnaBridge	171:3a7713b1edbc	1009	*
AnnaBridge	171:3a7713b1edbc	1010	* @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
AnnaBridge	171:3a7713b1edbc	1011	*/
AnnaBridge	171:3a7713b1edbc	1012	static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
AnnaBridge	171:3a7713b1edbc	1013	{
AnnaBridge	171:3a7713b1edbc	1014	MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) \| MCG_C1_FRDIV(frdiv);
AnnaBridge	171:3a7713b1edbc	1015	}
AnnaBridge	171:3a7713b1edbc	1016
AnnaBridge	171:3a7713b1edbc	1017	/*!
AnnaBridge	171:3a7713b1edbc	1018	* @brief Enables the PLL0 in FLL mode.
AnnaBridge	171:3a7713b1edbc	1019	*
AnnaBridge	171:3a7713b1edbc	1020	* This function sets us the PLL0 in FLL mode and reconfigures
AnnaBridge	171:3a7713b1edbc	1021	* the PLL0. Ensure that the PLL reference
AnnaBridge	171:3a7713b1edbc	1022	* clock is enabled before calling this function and that the PLL0 is not used as a clock source.
AnnaBridge	171:3a7713b1edbc	1023	* The function CLOCK_CalcPllDiv gets the correct PLL
AnnaBridge	171:3a7713b1edbc	1024	* divider values.
AnnaBridge	171:3a7713b1edbc	1025	*
AnnaBridge	171:3a7713b1edbc	1026	* @param config Pointer to the configuration structure.
AnnaBridge	171:3a7713b1edbc	1027	*/
AnnaBridge	171:3a7713b1edbc	1028	void CLOCK_EnablePll0(mcg_pll_config_t const *config);
AnnaBridge	171:3a7713b1edbc	1029
AnnaBridge	171:3a7713b1edbc	1030	/*!
AnnaBridge	171:3a7713b1edbc	1031	* @brief Disables the PLL0 in FLL mode.
AnnaBridge	171:3a7713b1edbc	1032	*
AnnaBridge	171:3a7713b1edbc	1033	* This function disables the PLL0 in FLL mode. It should be used together with the
AnnaBridge	171:3a7713b1edbc	1034	* @ref CLOCK_EnablePll0.
AnnaBridge	171:3a7713b1edbc	1035	*/
AnnaBridge	171:3a7713b1edbc	1036	static inline void CLOCK_DisablePll0(void)
AnnaBridge	171:3a7713b1edbc	1037	{
AnnaBridge	171:3a7713b1edbc	1038	MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK \| MCG_C5_PLLSTEN0_MASK);
AnnaBridge	171:3a7713b1edbc	1039	}
AnnaBridge	171:3a7713b1edbc	1040
AnnaBridge	171:3a7713b1edbc	1041	/*!
AnnaBridge	171:3a7713b1edbc	1042	* @brief Calculates the PLL divider setting for a desired output frequency.
AnnaBridge	171:3a7713b1edbc	1043	*
AnnaBridge	171:3a7713b1edbc	1044	* This function calculates the correct reference clock divider (\c PRDIV) and
AnnaBridge	171:3a7713b1edbc	1045	* VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
AnnaBridge	171:3a7713b1edbc	1046	* closest frequency match with the corresponding \c PRDIV/VDIV
AnnaBridge	171:3a7713b1edbc	1047	* returned from parameters. If a desired frequency is not valid, this function
AnnaBridge	171:3a7713b1edbc	1048	* returns 0.
AnnaBridge	171:3a7713b1edbc	1049	*
AnnaBridge	171:3a7713b1edbc	1050	* @param refFreq PLL reference clock frequency.
AnnaBridge	171:3a7713b1edbc	1051	* @param desireFreq Desired PLL output frequency.
AnnaBridge	171:3a7713b1edbc	1052	* @param prdiv PRDIV value to generate desired PLL frequency.
AnnaBridge	171:3a7713b1edbc	1053	* @param vdiv VDIV value to generate desired PLL frequency.
AnnaBridge	171:3a7713b1edbc	1054	* @return Closest frequency match that the PLL was able generate.
AnnaBridge	171:3a7713b1edbc	1055	*/
AnnaBridge	171:3a7713b1edbc	1056	uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t prdiv, uint8_t vdiv);
AnnaBridge	171:3a7713b1edbc	1057
AnnaBridge	171:3a7713b1edbc	1058	/@}/
AnnaBridge	171:3a7713b1edbc	1059
AnnaBridge	171:3a7713b1edbc	1060	/! @name MCG clock lock monitor functions. /
AnnaBridge	171:3a7713b1edbc	1061	/@{/
AnnaBridge	171:3a7713b1edbc	1062
AnnaBridge	171:3a7713b1edbc	1063	/*!
AnnaBridge	171:3a7713b1edbc	1064	* @brief Sets the OSC0 clock monitor mode.
AnnaBridge	171:3a7713b1edbc	1065	*
AnnaBridge	171:3a7713b1edbc	1066	* This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	171:3a7713b1edbc	1067	*
AnnaBridge	171:3a7713b1edbc	1068	* @param mode Monitor mode to set.
AnnaBridge	171:3a7713b1edbc	1069	*/
AnnaBridge	171:3a7713b1edbc	1070	void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	/*!
AnnaBridge	171:3a7713b1edbc	1073	* @brief Sets the RTC OSC clock monitor mode.
AnnaBridge	171:3a7713b1edbc	1074	*
AnnaBridge	171:3a7713b1edbc	1075	* This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	171:3a7713b1edbc	1076	*
AnnaBridge	171:3a7713b1edbc	1077	* @param mode Monitor mode to set.
AnnaBridge	171:3a7713b1edbc	1078	*/
AnnaBridge	171:3a7713b1edbc	1079	void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081	/*!
AnnaBridge	171:3a7713b1edbc	1082	* @brief Sets the PLL0 clock monitor mode.
AnnaBridge	171:3a7713b1edbc	1083	*
AnnaBridge	171:3a7713b1edbc	1084	* This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	171:3a7713b1edbc	1085	*
AnnaBridge	171:3a7713b1edbc	1086	* @param mode Monitor mode to set.
AnnaBridge	171:3a7713b1edbc	1087	*/
AnnaBridge	171:3a7713b1edbc	1088	void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	171:3a7713b1edbc	1089
AnnaBridge	171:3a7713b1edbc	1090	/*!
AnnaBridge	171:3a7713b1edbc	1091	* @brief Gets the MCG status flags.
AnnaBridge	171:3a7713b1edbc	1092	*
AnnaBridge	171:3a7713b1edbc	1093	* This function gets the MCG clock status flags. All status flags are
AnnaBridge	171:3a7713b1edbc	1094	* returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
AnnaBridge	171:3a7713b1edbc	1095	* check a specific flag, compare the return value with the flag.
AnnaBridge	171:3a7713b1edbc	1096	*
AnnaBridge	171:3a7713b1edbc	1097	* Example:
AnnaBridge	171:3a7713b1edbc	1098	* @code
AnnaBridge	171:3a7713b1edbc	1099	// To check the clock lost lock status of OSC0 and PLL0.
AnnaBridge	171:3a7713b1edbc	1100	uint32_t mcgFlags;
AnnaBridge	171:3a7713b1edbc	1101
AnnaBridge	171:3a7713b1edbc	1102	mcgFlags = CLOCK_GetStatusFlags();
AnnaBridge	171:3a7713b1edbc	1103
AnnaBridge	171:3a7713b1edbc	1104	if (mcgFlags & kMCG_Osc0LostFlag)
AnnaBridge	171:3a7713b1edbc	1105	{
AnnaBridge	171:3a7713b1edbc	1106	// OSC0 clock lock lost. Do something.
AnnaBridge	171:3a7713b1edbc	1107	}
AnnaBridge	171:3a7713b1edbc	1108	if (mcgFlags & kMCG_Pll0LostFlag)
AnnaBridge	171:3a7713b1edbc	1109	{
AnnaBridge	171:3a7713b1edbc	1110	// PLL0 clock lock lost. Do something.
AnnaBridge	171:3a7713b1edbc	1111	}
AnnaBridge	171:3a7713b1edbc	1112	@endcode
AnnaBridge	171:3a7713b1edbc	1113	*
AnnaBridge	171:3a7713b1edbc	1114	* @return Logical OR value of the @ref _mcg_status_flags_t.
AnnaBridge	171:3a7713b1edbc	1115	*/
AnnaBridge	171:3a7713b1edbc	1116	uint32_t CLOCK_GetStatusFlags(void);
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	/*!
AnnaBridge	171:3a7713b1edbc	1119	* @brief Clears the MCG status flags.
AnnaBridge	171:3a7713b1edbc	1120	*
AnnaBridge	171:3a7713b1edbc	1121	* This function clears the MCG clock lock lost status. The parameter is a logical
AnnaBridge	171:3a7713b1edbc	1122	* OR value of the flags to clear. See @ref _mcg_status_flags_t.
AnnaBridge	171:3a7713b1edbc	1123	*
AnnaBridge	171:3a7713b1edbc	1124	* Example:
AnnaBridge	171:3a7713b1edbc	1125	* @code
AnnaBridge	171:3a7713b1edbc	1126	// To clear the clock lost lock status flags of OSC0 and PLL0.
AnnaBridge	171:3a7713b1edbc	1127
AnnaBridge	171:3a7713b1edbc	1128	CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag \| kMCG_Pll0LostFlag);
AnnaBridge	171:3a7713b1edbc	1129	@endcode
AnnaBridge	171:3a7713b1edbc	1130	*
AnnaBridge	171:3a7713b1edbc	1131	* @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge	171:3a7713b1edbc	1132	* enumeration @ref _mcg_status_flags_t.
AnnaBridge	171:3a7713b1edbc	1133	*/
AnnaBridge	171:3a7713b1edbc	1134	void CLOCK_ClearStatusFlags(uint32_t mask);
AnnaBridge	171:3a7713b1edbc	1135
AnnaBridge	171:3a7713b1edbc	1136	/@}/
AnnaBridge	171:3a7713b1edbc	1137
AnnaBridge	171:3a7713b1edbc	1138	/*!
AnnaBridge	171:3a7713b1edbc	1139	* @name OSC configuration
AnnaBridge	171:3a7713b1edbc	1140	* @{
AnnaBridge	171:3a7713b1edbc	1141	*/
AnnaBridge	171:3a7713b1edbc	1142
AnnaBridge	171:3a7713b1edbc	1143	/*!
AnnaBridge	171:3a7713b1edbc	1144	* @brief Configures the OSC external reference clock (OSCERCLK).
AnnaBridge	171:3a7713b1edbc	1145	*
AnnaBridge	171:3a7713b1edbc	1146	* This function configures the OSC external reference clock (OSCERCLK).
AnnaBridge	171:3a7713b1edbc	1147	* This is an example to enable the OSCERCLK in normal and stop modes and also set
AnnaBridge	171:3a7713b1edbc	1148	* the output divider to 1:
AnnaBridge	171:3a7713b1edbc	1149	*
AnnaBridge	171:3a7713b1edbc	1150	@code
AnnaBridge	171:3a7713b1edbc	1151	oscer_config_t config =
AnnaBridge	171:3a7713b1edbc	1152	{
AnnaBridge	171:3a7713b1edbc	1153	.enableMode = kOSC_ErClkEnable \| kOSC_ErClkEnableInStop,
AnnaBridge	171:3a7713b1edbc	1154	.erclkDiv = 1U,
AnnaBridge	171:3a7713b1edbc	1155	};
AnnaBridge	171:3a7713b1edbc	1156
AnnaBridge	171:3a7713b1edbc	1157	OSC_SetExtRefClkConfig(OSC, &config);
AnnaBridge	171:3a7713b1edbc	1158	@endcode
AnnaBridge	171:3a7713b1edbc	1159	*
AnnaBridge	171:3a7713b1edbc	1160	* @param base OSC peripheral address.
AnnaBridge	171:3a7713b1edbc	1161	* @param config Pointer to the configuration structure.
AnnaBridge	171:3a7713b1edbc	1162	*/
AnnaBridge	171:3a7713b1edbc	1163	static inline void OSC_SetExtRefClkConfig(OSC_Type base, oscer_config_t const config)
AnnaBridge	171:3a7713b1edbc	1164	{
AnnaBridge	171:3a7713b1edbc	1165	uint8_t reg = base->CR;
AnnaBridge	171:3a7713b1edbc	1166
AnnaBridge	171:3a7713b1edbc	1167	reg &= ~(OSC_CR_ERCLKEN_MASK \| OSC_CR_EREFSTEN_MASK);
AnnaBridge	171:3a7713b1edbc	1168	reg \|= config->enableMode;
AnnaBridge	171:3a7713b1edbc	1169
AnnaBridge	171:3a7713b1edbc	1170	base->CR = reg;
AnnaBridge	171:3a7713b1edbc	1171	}
AnnaBridge	171:3a7713b1edbc	1172
AnnaBridge	171:3a7713b1edbc	1173	/*!
AnnaBridge	171:3a7713b1edbc	1174	* @brief Sets the capacitor load configuration for the oscillator.
AnnaBridge	171:3a7713b1edbc	1175	*
AnnaBridge	171:3a7713b1edbc	1176	* This function sets the specified capacitors configuration for the oscillator.
AnnaBridge	171:3a7713b1edbc	1177	* This should be done in the early system level initialization function call
AnnaBridge	171:3a7713b1edbc	1178	* based on the system configuration.
AnnaBridge	171:3a7713b1edbc	1179	*
AnnaBridge	171:3a7713b1edbc	1180	* @param base OSC peripheral address.
AnnaBridge	171:3a7713b1edbc	1181	* @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
AnnaBridge	171:3a7713b1edbc	1182	*
AnnaBridge	171:3a7713b1edbc	1183	* Example:
AnnaBridge	171:3a7713b1edbc	1184	@code
AnnaBridge	171:3a7713b1edbc	1185	// To enable only 2 pF and 8 pF capacitor load, please use like this.
AnnaBridge	171:3a7713b1edbc	1186	OSC_SetCapLoad(OSC, kOSC_Cap2P \| kOSC_Cap8P);
AnnaBridge	171:3a7713b1edbc	1187	@endcode
AnnaBridge	171:3a7713b1edbc	1188	*/
AnnaBridge	171:3a7713b1edbc	1189	static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
AnnaBridge	171:3a7713b1edbc	1190	{
AnnaBridge	171:3a7713b1edbc	1191	uint8_t reg = base->CR;
AnnaBridge	171:3a7713b1edbc	1192
AnnaBridge	171:3a7713b1edbc	1193	reg &= ~(OSC_CR_SC2P_MASK \| OSC_CR_SC4P_MASK \| OSC_CR_SC8P_MASK \| OSC_CR_SC16P_MASK);
AnnaBridge	171:3a7713b1edbc	1194	reg \|= capLoad;
AnnaBridge	171:3a7713b1edbc	1195
AnnaBridge	171:3a7713b1edbc	1196	base->CR = reg;
AnnaBridge	171:3a7713b1edbc	1197	}
AnnaBridge	171:3a7713b1edbc	1198
AnnaBridge	171:3a7713b1edbc	1199	/*!
AnnaBridge	171:3a7713b1edbc	1200	* @brief Initializes the OSC0.
AnnaBridge	171:3a7713b1edbc	1201	*
AnnaBridge	171:3a7713b1edbc	1202	* This function initializes the OSC0 according to the board configuration.
AnnaBridge	171:3a7713b1edbc	1203	*
AnnaBridge	171:3a7713b1edbc	1204	* @param config Pointer to the OSC0 configuration structure.
AnnaBridge	171:3a7713b1edbc	1205	*/
AnnaBridge	171:3a7713b1edbc	1206	void CLOCK_InitOsc0(osc_config_t const *config);
AnnaBridge	171:3a7713b1edbc	1207
AnnaBridge	171:3a7713b1edbc	1208	/*!
AnnaBridge	171:3a7713b1edbc	1209	* @brief Deinitializes the OSC0.
AnnaBridge	171:3a7713b1edbc	1210	*
AnnaBridge	171:3a7713b1edbc	1211	* This function deinitializes the OSC0.
AnnaBridge	171:3a7713b1edbc	1212	*/
AnnaBridge	171:3a7713b1edbc	1213	void CLOCK_DeinitOsc0(void);
AnnaBridge	171:3a7713b1edbc	1214
AnnaBridge	171:3a7713b1edbc	1215	/* @} */
AnnaBridge	171:3a7713b1edbc	1216
AnnaBridge	171:3a7713b1edbc	1217	/*!
AnnaBridge	171:3a7713b1edbc	1218	* @name External clock frequency
AnnaBridge	171:3a7713b1edbc	1219	* @{
AnnaBridge	171:3a7713b1edbc	1220	*/
AnnaBridge	171:3a7713b1edbc	1221
AnnaBridge	171:3a7713b1edbc	1222	/*!
AnnaBridge	171:3a7713b1edbc	1223	* @brief Sets the XTAL0 frequency based on board settings.
AnnaBridge	171:3a7713b1edbc	1224	*
AnnaBridge	171:3a7713b1edbc	1225	* @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	1226	*/
AnnaBridge	171:3a7713b1edbc	1227	static inline void CLOCK_SetXtal0Freq(uint32_t freq)
AnnaBridge	171:3a7713b1edbc	1228	{
AnnaBridge	171:3a7713b1edbc	1229	g_xtal0Freq = freq;
AnnaBridge	171:3a7713b1edbc	1230	}
AnnaBridge	171:3a7713b1edbc	1231
AnnaBridge	171:3a7713b1edbc	1232	/*!
AnnaBridge	171:3a7713b1edbc	1233	* @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
AnnaBridge	171:3a7713b1edbc	1234	*
AnnaBridge	171:3a7713b1edbc	1235	* @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
AnnaBridge	171:3a7713b1edbc	1236	*/
AnnaBridge	171:3a7713b1edbc	1237	static inline void CLOCK_SetXtal32Freq(uint32_t freq)
AnnaBridge	171:3a7713b1edbc	1238	{
AnnaBridge	171:3a7713b1edbc	1239	g_xtal32Freq = freq;
AnnaBridge	171:3a7713b1edbc	1240	}
AnnaBridge	171:3a7713b1edbc	1241	/* @} */
AnnaBridge	171:3a7713b1edbc	1242
AnnaBridge	171:3a7713b1edbc	1243	/*!
AnnaBridge	171:3a7713b1edbc	1244	* @name MCG auto-trim machine.
AnnaBridge	171:3a7713b1edbc	1245	* @{
AnnaBridge	171:3a7713b1edbc	1246	*/
AnnaBridge	171:3a7713b1edbc	1247
AnnaBridge	171:3a7713b1edbc	1248	/*!
AnnaBridge	171:3a7713b1edbc	1249	* @brief Auto trims the internal reference clock.
AnnaBridge	171:3a7713b1edbc	1250	*
AnnaBridge	171:3a7713b1edbc	1251	* This function trims the internal reference clock by using the external clock. If
AnnaBridge	171:3a7713b1edbc	1252	* successful, it returns the kStatus_Success and the frequency after
AnnaBridge	171:3a7713b1edbc	1253	* trimming is received in the parameter @p actualFreq. If an error occurs,
AnnaBridge	171:3a7713b1edbc	1254	* the error code is returned.
AnnaBridge	171:3a7713b1edbc	1255	*
AnnaBridge	171:3a7713b1edbc	1256	* @param extFreq External clock frequency, which should be a bus clock.
AnnaBridge	171:3a7713b1edbc	1257	* @param desireFreq Frequency to trim to.
AnnaBridge	171:3a7713b1edbc	1258	* @param actualFreq Actual frequency after trimming.
AnnaBridge	171:3a7713b1edbc	1259	* @param atms Trim fast or slow internal reference clock.
AnnaBridge	171:3a7713b1edbc	1260	* @retval kStatus_Success ATM success.
AnnaBridge	171:3a7713b1edbc	1261	* @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
AnnaBridge	171:3a7713b1edbc	1262	* @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
AnnaBridge	171:3a7713b1edbc	1263	* @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
AnnaBridge	171:3a7713b1edbc	1264	* @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
AnnaBridge	171:3a7713b1edbc	1265	*/
AnnaBridge	171:3a7713b1edbc	1266	status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
AnnaBridge	171:3a7713b1edbc	1267	/* @} */
AnnaBridge	171:3a7713b1edbc	1268
AnnaBridge	171:3a7713b1edbc	1269	/! @name MCG mode functions. /
AnnaBridge	171:3a7713b1edbc	1270	/@{/
AnnaBridge	171:3a7713b1edbc	1271
AnnaBridge	171:3a7713b1edbc	1272	/*!
AnnaBridge	171:3a7713b1edbc	1273	* @brief Gets the current MCG mode.
AnnaBridge	171:3a7713b1edbc	1274	*
AnnaBridge	171:3a7713b1edbc	1275	* This function checks the MCG registers and determines the current MCG mode.
AnnaBridge	171:3a7713b1edbc	1276	*
AnnaBridge	171:3a7713b1edbc	1277	* @return Current MCG mode or error code; See @ref mcg_mode_t.
AnnaBridge	171:3a7713b1edbc	1278	*/
AnnaBridge	171:3a7713b1edbc	1279	mcg_mode_t CLOCK_GetMode(void);
AnnaBridge	171:3a7713b1edbc	1280
AnnaBridge	171:3a7713b1edbc	1281	/*!
AnnaBridge	171:3a7713b1edbc	1282	* @brief Sets the MCG to FEI mode.
AnnaBridge	171:3a7713b1edbc	1283	*
AnnaBridge	171:3a7713b1edbc	1284	* This function sets the MCG to FEI mode. If setting to FEI mode fails
AnnaBridge	171:3a7713b1edbc	1285	* from the current mode, this function returns an error.
AnnaBridge	171:3a7713b1edbc	1286	*
AnnaBridge	171:3a7713b1edbc	1287	* @param dmx32 DMX32 in FEI mode.
AnnaBridge	171:3a7713b1edbc	1288	* @param drs The DCO range selection.
AnnaBridge	171:3a7713b1edbc	1289	* @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
AnnaBridge	171:3a7713b1edbc	1290	* NULL does not cause a delay.
AnnaBridge	171:3a7713b1edbc	1291	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1292	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1293	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	171:3a7713b1edbc	1294	* to a frequency above 32768 Hz.
AnnaBridge	171:3a7713b1edbc	1295	*/
AnnaBridge	171:3a7713b1edbc	1296	status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	171:3a7713b1edbc	1297
AnnaBridge	171:3a7713b1edbc	1298	/*!
AnnaBridge	171:3a7713b1edbc	1299	* @brief Sets the MCG to FEE mode.
AnnaBridge	171:3a7713b1edbc	1300	*
AnnaBridge	171:3a7713b1edbc	1301	* This function sets the MCG to FEE mode. If setting to FEE mode fails
AnnaBridge	171:3a7713b1edbc	1302	* from the current mode, this function returns an error.
AnnaBridge	171:3a7713b1edbc	1303	*
AnnaBridge	171:3a7713b1edbc	1304	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	171:3a7713b1edbc	1305	* @param dmx32 DMX32 in FEE mode.
AnnaBridge	171:3a7713b1edbc	1306	* @param drs The DCO range selection.
AnnaBridge	171:3a7713b1edbc	1307	* @param fllStableDelay Delay function to make sure FLL is stable. Passing
AnnaBridge	171:3a7713b1edbc	1308	* NULL does not cause a delay.
AnnaBridge	171:3a7713b1edbc	1309	*
AnnaBridge	171:3a7713b1edbc	1310	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1311	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1312	*/
AnnaBridge	171:3a7713b1edbc	1313	status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	171:3a7713b1edbc	1314
AnnaBridge	171:3a7713b1edbc	1315	/*!
AnnaBridge	171:3a7713b1edbc	1316	* @brief Sets the MCG to FBI mode.
AnnaBridge	171:3a7713b1edbc	1317	*
AnnaBridge	171:3a7713b1edbc	1318	* This function sets the MCG to FBI mode. If setting to FBI mode fails
AnnaBridge	171:3a7713b1edbc	1319	* from the current mode, this function returns an error.
AnnaBridge	171:3a7713b1edbc	1320	*
AnnaBridge	171:3a7713b1edbc	1321	* @param dmx32 DMX32 in FBI mode.
AnnaBridge	171:3a7713b1edbc	1322	* @param drs The DCO range selection.
AnnaBridge	171:3a7713b1edbc	1323	* @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge	171:3a7713b1edbc	1324	* is not used in FBI mode, this parameter can be NULL. Passing
AnnaBridge	171:3a7713b1edbc	1325	* NULL does not cause a delay.
AnnaBridge	171:3a7713b1edbc	1326	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1327	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1328	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	171:3a7713b1edbc	1329	* to frequency above 32768 Hz.
AnnaBridge	171:3a7713b1edbc	1330	*/
AnnaBridge	171:3a7713b1edbc	1331	status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	171:3a7713b1edbc	1332
AnnaBridge	171:3a7713b1edbc	1333	/*!
AnnaBridge	171:3a7713b1edbc	1334	* @brief Sets the MCG to FBE mode.
AnnaBridge	171:3a7713b1edbc	1335	*
AnnaBridge	171:3a7713b1edbc	1336	* This function sets the MCG to FBE mode. If setting to FBE mode fails
AnnaBridge	171:3a7713b1edbc	1337	* from the current mode, this function returns an error.
AnnaBridge	171:3a7713b1edbc	1338	*
AnnaBridge	171:3a7713b1edbc	1339	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	171:3a7713b1edbc	1340	* @param dmx32 DMX32 in FBE mode.
AnnaBridge	171:3a7713b1edbc	1341	* @param drs The DCO range selection.
AnnaBridge	171:3a7713b1edbc	1342	* @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge	171:3a7713b1edbc	1343	* is not used in FBE mode, this parameter can be NULL. Passing NULL
AnnaBridge	171:3a7713b1edbc	1344	* does not cause a delay.
AnnaBridge	171:3a7713b1edbc	1345	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1346	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1347	*/
AnnaBridge	171:3a7713b1edbc	1348	status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	171:3a7713b1edbc	1349
AnnaBridge	171:3a7713b1edbc	1350	/*!
AnnaBridge	171:3a7713b1edbc	1351	* @brief Sets the MCG to BLPI mode.
AnnaBridge	171:3a7713b1edbc	1352	*
AnnaBridge	171:3a7713b1edbc	1353	* This function sets the MCG to BLPI mode. If setting to BLPI mode fails
AnnaBridge	171:3a7713b1edbc	1354	* from the current mode, this function returns an error.
AnnaBridge	171:3a7713b1edbc	1355	*
AnnaBridge	171:3a7713b1edbc	1356	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1357	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1358	*/
AnnaBridge	171:3a7713b1edbc	1359	status_t CLOCK_SetBlpiMode(void);
AnnaBridge	171:3a7713b1edbc	1360
AnnaBridge	171:3a7713b1edbc	1361	/*!
AnnaBridge	171:3a7713b1edbc	1362	* @brief Sets the MCG to BLPE mode.
AnnaBridge	171:3a7713b1edbc	1363	*
AnnaBridge	171:3a7713b1edbc	1364	* This function sets the MCG to BLPE mode. If setting to BLPE mode fails
AnnaBridge	171:3a7713b1edbc	1365	* from the current mode, this function returns an error.
AnnaBridge	171:3a7713b1edbc	1366	*
AnnaBridge	171:3a7713b1edbc	1367	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1368	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1369	*/
AnnaBridge	171:3a7713b1edbc	1370	status_t CLOCK_SetBlpeMode(void);
AnnaBridge	171:3a7713b1edbc	1371
AnnaBridge	171:3a7713b1edbc	1372	/*!
AnnaBridge	171:3a7713b1edbc	1373	* @brief Sets the MCG to PBE mode.
AnnaBridge	171:3a7713b1edbc	1374	*
AnnaBridge	171:3a7713b1edbc	1375	* This function sets the MCG to PBE mode. If setting to PBE mode fails
AnnaBridge	171:3a7713b1edbc	1376	* from the current mode, this function returns an error.
AnnaBridge	171:3a7713b1edbc	1377	*
AnnaBridge	171:3a7713b1edbc	1378	* @param pllcs The PLL selection, PLLCS.
AnnaBridge	171:3a7713b1edbc	1379	* @param config Pointer to the PLL configuration.
AnnaBridge	171:3a7713b1edbc	1380	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1381	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1382	*
AnnaBridge	171:3a7713b1edbc	1383	* @note
AnnaBridge	171:3a7713b1edbc	1384	* 1. The parameter \c pllcs selects the PLL. For platforms with
AnnaBridge	171:3a7713b1edbc	1385	* only one PLL, the parameter pllcs is kept for interface compatibility.
AnnaBridge	171:3a7713b1edbc	1386	* 2. The parameter \c config is the PLL configuration structure. On some
AnnaBridge	171:3a7713b1edbc	1387	* platforms, it is possible to choose the external PLL directly, which renders the
AnnaBridge	171:3a7713b1edbc	1388	* configuration structure not necessary. In this case, pass in NULL.
AnnaBridge	171:3a7713b1edbc	1389	* For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
AnnaBridge	171:3a7713b1edbc	1390	*/
AnnaBridge	171:3a7713b1edbc	1391	status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge	171:3a7713b1edbc	1392
AnnaBridge	171:3a7713b1edbc	1393	/*!
AnnaBridge	171:3a7713b1edbc	1394	* @brief Sets the MCG to PEE mode.
AnnaBridge	171:3a7713b1edbc	1395	*
AnnaBridge	171:3a7713b1edbc	1396	* This function sets the MCG to PEE mode.
AnnaBridge	171:3a7713b1edbc	1397	*
AnnaBridge	171:3a7713b1edbc	1398	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1399	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1400	*
AnnaBridge	171:3a7713b1edbc	1401	* @note This function only changes the CLKS to use the PLL/FLL output. If the
AnnaBridge	171:3a7713b1edbc	1402	* PRDIV/VDIV are different than in the PBE mode, set them up
AnnaBridge	171:3a7713b1edbc	1403	* in PBE mode and wait. When the clock is stable, switch to PEE mode.
AnnaBridge	171:3a7713b1edbc	1404	*/
AnnaBridge	171:3a7713b1edbc	1405	status_t CLOCK_SetPeeMode(void);
AnnaBridge	171:3a7713b1edbc	1406
AnnaBridge	171:3a7713b1edbc	1407	/*!
AnnaBridge	171:3a7713b1edbc	1408	* @brief Switches the MCG to FBE mode from the external mode.
AnnaBridge	171:3a7713b1edbc	1409	*
AnnaBridge	171:3a7713b1edbc	1410	* This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
AnnaBridge	171:3a7713b1edbc	1411	* The external clock is used as the system clock souce and PLL is disabled. However,
AnnaBridge	171:3a7713b1edbc	1412	* the FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge	171:3a7713b1edbc	1413	* during the mode switch. For example, to switch from PEE mode to FEI mode:
AnnaBridge	171:3a7713b1edbc	1414	*
AnnaBridge	171:3a7713b1edbc	1415	* @code
AnnaBridge	171:3a7713b1edbc	1416	* CLOCK_ExternalModeToFbeModeQuick();
AnnaBridge	171:3a7713b1edbc	1417	* CLOCK_SetFeiMode(...);
AnnaBridge	171:3a7713b1edbc	1418	* @endcode
AnnaBridge	171:3a7713b1edbc	1419	*
AnnaBridge	171:3a7713b1edbc	1420	* @retval kStatus_Success Switched successfully.
AnnaBridge	171:3a7713b1edbc	1421	* @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
AnnaBridge	171:3a7713b1edbc	1422	*/
AnnaBridge	171:3a7713b1edbc	1423	status_t CLOCK_ExternalModeToFbeModeQuick(void);
AnnaBridge	171:3a7713b1edbc	1424
AnnaBridge	171:3a7713b1edbc	1425	/*!
AnnaBridge	171:3a7713b1edbc	1426	* @brief Switches the MCG to FBI mode from internal modes.
AnnaBridge	171:3a7713b1edbc	1427	*
AnnaBridge	171:3a7713b1edbc	1428	* This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
AnnaBridge	171:3a7713b1edbc	1429	* The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
AnnaBridge	171:3a7713b1edbc	1430	* FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge	171:3a7713b1edbc	1431	* during the mode switch. For example, to switch from PEI mode to FEE mode:
AnnaBridge	171:3a7713b1edbc	1432	*
AnnaBridge	171:3a7713b1edbc	1433	* @code
AnnaBridge	171:3a7713b1edbc	1434	* CLOCK_InternalModeToFbiModeQuick();
AnnaBridge	171:3a7713b1edbc	1435	* CLOCK_SetFeeMode(...);
AnnaBridge	171:3a7713b1edbc	1436	* @endcode
AnnaBridge	171:3a7713b1edbc	1437	*
AnnaBridge	171:3a7713b1edbc	1438	* @retval kStatus_Success Switched successfully.
AnnaBridge	171:3a7713b1edbc	1439	* @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
AnnaBridge	171:3a7713b1edbc	1440	*/
AnnaBridge	171:3a7713b1edbc	1441	status_t CLOCK_InternalModeToFbiModeQuick(void);
AnnaBridge	171:3a7713b1edbc	1442
AnnaBridge	171:3a7713b1edbc	1443	/*!
AnnaBridge	171:3a7713b1edbc	1444	* @brief Sets the MCG to FEI mode during system boot up.
AnnaBridge	171:3a7713b1edbc	1445	*
AnnaBridge	171:3a7713b1edbc	1446	* This function sets the MCG to FEI mode from the reset mode. It can also be used to
AnnaBridge	171:3a7713b1edbc	1447	* set up MCG during system boot up.
AnnaBridge	171:3a7713b1edbc	1448	*
AnnaBridge	171:3a7713b1edbc	1449	* @param dmx32 DMX32 in FEI mode.
AnnaBridge	171:3a7713b1edbc	1450	* @param drs The DCO range selection.
AnnaBridge	171:3a7713b1edbc	1451	* @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge	171:3a7713b1edbc	1452	*
AnnaBridge	171:3a7713b1edbc	1453	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1454	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1455	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	171:3a7713b1edbc	1456	* to frequency above 32768 Hz.
AnnaBridge	171:3a7713b1edbc	1457	*/
AnnaBridge	171:3a7713b1edbc	1458	status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	171:3a7713b1edbc	1459
AnnaBridge	171:3a7713b1edbc	1460	/*!
AnnaBridge	171:3a7713b1edbc	1461	* @brief Sets the MCG to FEE mode during system bootup.
AnnaBridge	171:3a7713b1edbc	1462	*
AnnaBridge	171:3a7713b1edbc	1463	* This function sets MCG to FEE mode from the reset mode. It can also be used to
AnnaBridge	171:3a7713b1edbc	1464	* set up the MCG during system boot up.
AnnaBridge	171:3a7713b1edbc	1465	*
AnnaBridge	171:3a7713b1edbc	1466	* @param oscsel OSC clock select, OSCSEL.
AnnaBridge	171:3a7713b1edbc	1467	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	171:3a7713b1edbc	1468	* @param dmx32 DMX32 in FEE mode.
AnnaBridge	171:3a7713b1edbc	1469	* @param drs The DCO range selection.
AnnaBridge	171:3a7713b1edbc	1470	* @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge	171:3a7713b1edbc	1471	*
AnnaBridge	171:3a7713b1edbc	1472	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1473	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1474	*/
AnnaBridge	171:3a7713b1edbc	1475	status_t CLOCK_BootToFeeMode(
AnnaBridge	171:3a7713b1edbc	1476	mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	171:3a7713b1edbc	1477
AnnaBridge	171:3a7713b1edbc	1478	/*!
AnnaBridge	171:3a7713b1edbc	1479	* @brief Sets the MCG to BLPI mode during system boot up.
AnnaBridge	171:3a7713b1edbc	1480	*
AnnaBridge	171:3a7713b1edbc	1481	* This function sets the MCG to BLPI mode from the reset mode. It can also be used to
AnnaBridge	171:3a7713b1edbc	1482	* set up the MCG during sytem boot up.
AnnaBridge	171:3a7713b1edbc	1483	*
AnnaBridge	171:3a7713b1edbc	1484	* @param fcrdiv Fast IRC divider, FCRDIV.
AnnaBridge	171:3a7713b1edbc	1485	* @param ircs The internal reference clock to select, IRCS.
AnnaBridge	171:3a7713b1edbc	1486	* @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge	171:3a7713b1edbc	1487	*
AnnaBridge	171:3a7713b1edbc	1488	* @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
AnnaBridge	171:3a7713b1edbc	1489	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1490	*/
AnnaBridge	171:3a7713b1edbc	1491	status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
AnnaBridge	171:3a7713b1edbc	1492
AnnaBridge	171:3a7713b1edbc	1493	/*!
AnnaBridge	171:3a7713b1edbc	1494	* @brief Sets the MCG to BLPE mode during sytem boot up.
AnnaBridge	171:3a7713b1edbc	1495	*
AnnaBridge	171:3a7713b1edbc	1496	* This function sets the MCG to BLPE mode from the reset mode. It can also be used to
AnnaBridge	171:3a7713b1edbc	1497	* set up the MCG during sytem boot up.
AnnaBridge	171:3a7713b1edbc	1498	*
AnnaBridge	171:3a7713b1edbc	1499	* @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge	171:3a7713b1edbc	1500	*
AnnaBridge	171:3a7713b1edbc	1501	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1502	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1503	*/
AnnaBridge	171:3a7713b1edbc	1504	status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
AnnaBridge	171:3a7713b1edbc	1505
AnnaBridge	171:3a7713b1edbc	1506	/*!
AnnaBridge	171:3a7713b1edbc	1507	* @brief Sets the MCG to PEE mode during system boot up.
AnnaBridge	171:3a7713b1edbc	1508	*
AnnaBridge	171:3a7713b1edbc	1509	* This function sets the MCG to PEE mode from reset mode. It can also be used to
AnnaBridge	171:3a7713b1edbc	1510	* set up the MCG during system boot up.
AnnaBridge	171:3a7713b1edbc	1511	*
AnnaBridge	171:3a7713b1edbc	1512	* @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge	171:3a7713b1edbc	1513	* @param pllcs The PLL selection, PLLCS.
AnnaBridge	171:3a7713b1edbc	1514	* @param config Pointer to the PLL configuration.
AnnaBridge	171:3a7713b1edbc	1515	*
AnnaBridge	171:3a7713b1edbc	1516	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	171:3a7713b1edbc	1517	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	171:3a7713b1edbc	1518	*/
AnnaBridge	171:3a7713b1edbc	1519	status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge	171:3a7713b1edbc	1520
AnnaBridge	171:3a7713b1edbc	1521	/*!
AnnaBridge	171:3a7713b1edbc	1522	* @brief Sets the MCG to a target mode.
AnnaBridge	171:3a7713b1edbc	1523	*
AnnaBridge	171:3a7713b1edbc	1524	* This function sets MCG to a target mode defined by the configuration
AnnaBridge	171:3a7713b1edbc	1525	* structure. If switching to the target mode fails, this function
AnnaBridge	171:3a7713b1edbc	1526	* chooses the correct path.
AnnaBridge	171:3a7713b1edbc	1527	*
AnnaBridge	171:3a7713b1edbc	1528	* @param config Pointer to the target MCG mode configuration structure.
AnnaBridge	171:3a7713b1edbc	1529	* @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
AnnaBridge	171:3a7713b1edbc	1530	*
AnnaBridge	171:3a7713b1edbc	1531	* @note If the external clock is used in the target mode, ensure that it is
AnnaBridge	171:3a7713b1edbc	1532	* enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
AnnaBridge	171:3a7713b1edbc	1533	* function.
AnnaBridge	171:3a7713b1edbc	1534	*/
AnnaBridge	171:3a7713b1edbc	1535	status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
AnnaBridge	171:3a7713b1edbc	1536
AnnaBridge	171:3a7713b1edbc	1537	/@}/
AnnaBridge	171:3a7713b1edbc	1538
AnnaBridge	171:3a7713b1edbc	1539	#if defined(__cplusplus)
AnnaBridge	171:3a7713b1edbc	1540	}
AnnaBridge	171:3a7713b1edbc	1541	#endif /* __cplusplus */
AnnaBridge	171:3a7713b1edbc	1542
AnnaBridge	171:3a7713b1edbc	1543	/! @} /
AnnaBridge	171:3a7713b1edbc	1544
AnnaBridge	171:3a7713b1edbc	1545	#endif /* _FSL_CLOCK_H_ */