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TARGET_NUCLEO_L432KC/TOOLCHAIN_ARM_STD/stm32l4xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 165:d1b4690b3f8b | 1 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2 | ****************************************************************************** |
AnnaBridge | 165:d1b4690b3f8b | 3 | * @file stm32l4xx_hal_rcc_ex.h |
AnnaBridge | 165:d1b4690b3f8b | 4 | * @author MCD Application Team |
AnnaBridge | 165:d1b4690b3f8b | 5 | * @brief Header file of RCC HAL Extended module. |
AnnaBridge | 165:d1b4690b3f8b | 6 | ****************************************************************************** |
AnnaBridge | 165:d1b4690b3f8b | 7 | * @attention |
AnnaBridge | 165:d1b4690b3f8b | 8 | * |
AnnaBridge | 165:d1b4690b3f8b | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 165:d1b4690b3f8b | 10 | * |
AnnaBridge | 165:d1b4690b3f8b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 165:d1b4690b3f8b | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 165:d1b4690b3f8b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 165:d1b4690b3f8b | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 165:d1b4690b3f8b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 165:d1b4690b3f8b | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 165:d1b4690b3f8b | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 165:d1b4690b3f8b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 165:d1b4690b3f8b | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 165:d1b4690b3f8b | 20 | * without specific prior written permission. |
AnnaBridge | 165:d1b4690b3f8b | 21 | * |
AnnaBridge | 165:d1b4690b3f8b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 165:d1b4690b3f8b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 165:d1b4690b3f8b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 165:d1b4690b3f8b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 165:d1b4690b3f8b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 165:d1b4690b3f8b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 165:d1b4690b3f8b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 165:d1b4690b3f8b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 165:d1b4690b3f8b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 165:d1b4690b3f8b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 165:d1b4690b3f8b | 32 | * |
AnnaBridge | 165:d1b4690b3f8b | 33 | ****************************************************************************** |
AnnaBridge | 165:d1b4690b3f8b | 34 | */ |
AnnaBridge | 165:d1b4690b3f8b | 35 | |
AnnaBridge | 165:d1b4690b3f8b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 37 | #ifndef __STM32L4xx_HAL_RCC_EX_H |
AnnaBridge | 165:d1b4690b3f8b | 38 | #define __STM32L4xx_HAL_RCC_EX_H |
AnnaBridge | 165:d1b4690b3f8b | 39 | |
AnnaBridge | 165:d1b4690b3f8b | 40 | #ifdef __cplusplus |
AnnaBridge | 165:d1b4690b3f8b | 41 | extern "C" { |
AnnaBridge | 165:d1b4690b3f8b | 42 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 43 | |
AnnaBridge | 165:d1b4690b3f8b | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 45 | #include "stm32l4xx_hal_def.h" |
AnnaBridge | 165:d1b4690b3f8b | 46 | |
AnnaBridge | 165:d1b4690b3f8b | 47 | /** @addtogroup STM32L4xx_HAL_Driver |
AnnaBridge | 165:d1b4690b3f8b | 48 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 49 | */ |
AnnaBridge | 165:d1b4690b3f8b | 50 | |
AnnaBridge | 165:d1b4690b3f8b | 51 | /** @addtogroup RCCEx |
AnnaBridge | 165:d1b4690b3f8b | 52 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 53 | */ |
AnnaBridge | 165:d1b4690b3f8b | 54 | |
AnnaBridge | 165:d1b4690b3f8b | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 56 | |
AnnaBridge | 165:d1b4690b3f8b | 57 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
AnnaBridge | 165:d1b4690b3f8b | 58 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 59 | */ |
AnnaBridge | 165:d1b4690b3f8b | 60 | |
AnnaBridge | 165:d1b4690b3f8b | 61 | /** |
AnnaBridge | 165:d1b4690b3f8b | 62 | * @brief PLLSAI1 Clock structure definition |
AnnaBridge | 165:d1b4690b3f8b | 63 | */ |
AnnaBridge | 165:d1b4690b3f8b | 64 | typedef struct |
AnnaBridge | 165:d1b4690b3f8b | 65 | { |
AnnaBridge | 165:d1b4690b3f8b | 66 | |
AnnaBridge | 165:d1b4690b3f8b | 67 | uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. |
AnnaBridge | 165:d1b4690b3f8b | 68 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 69 | |
AnnaBridge | 165:d1b4690b3f8b | 70 | #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 71 | uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. |
AnnaBridge | 165:d1b4690b3f8b | 72 | This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
AnnaBridge | 165:d1b4690b3f8b | 73 | #else |
AnnaBridge | 165:d1b4690b3f8b | 74 | uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. |
AnnaBridge | 165:d1b4690b3f8b | 75 | This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ |
AnnaBridge | 165:d1b4690b3f8b | 76 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 77 | |
AnnaBridge | 165:d1b4690b3f8b | 78 | uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. |
AnnaBridge | 165:d1b4690b3f8b | 79 | This parameter must be a number between 8 and 86 or 127 depending on devices. */ |
AnnaBridge | 165:d1b4690b3f8b | 80 | |
AnnaBridge | 165:d1b4690b3f8b | 81 | uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. |
AnnaBridge | 165:d1b4690b3f8b | 82 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
AnnaBridge | 165:d1b4690b3f8b | 83 | |
AnnaBridge | 165:d1b4690b3f8b | 84 | uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 85 | This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ |
AnnaBridge | 165:d1b4690b3f8b | 86 | |
AnnaBridge | 165:d1b4690b3f8b | 87 | uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. |
AnnaBridge | 165:d1b4690b3f8b | 88 | This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ |
AnnaBridge | 165:d1b4690b3f8b | 89 | |
AnnaBridge | 165:d1b4690b3f8b | 90 | uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. |
AnnaBridge | 165:d1b4690b3f8b | 91 | This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ |
AnnaBridge | 165:d1b4690b3f8b | 92 | }RCC_PLLSAI1InitTypeDef; |
AnnaBridge | 165:d1b4690b3f8b | 93 | |
AnnaBridge | 165:d1b4690b3f8b | 94 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 95 | |
AnnaBridge | 165:d1b4690b3f8b | 96 | /** |
AnnaBridge | 165:d1b4690b3f8b | 97 | * @brief PLLSAI2 Clock structure definition |
AnnaBridge | 165:d1b4690b3f8b | 98 | */ |
AnnaBridge | 165:d1b4690b3f8b | 99 | typedef struct |
AnnaBridge | 165:d1b4690b3f8b | 100 | { |
AnnaBridge | 165:d1b4690b3f8b | 101 | |
AnnaBridge | 165:d1b4690b3f8b | 102 | uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. |
AnnaBridge | 165:d1b4690b3f8b | 103 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 104 | |
AnnaBridge | 165:d1b4690b3f8b | 105 | #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 106 | uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. |
AnnaBridge | 165:d1b4690b3f8b | 107 | This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
AnnaBridge | 165:d1b4690b3f8b | 108 | #else |
AnnaBridge | 165:d1b4690b3f8b | 109 | uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. |
AnnaBridge | 165:d1b4690b3f8b | 110 | This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ |
AnnaBridge | 165:d1b4690b3f8b | 111 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 112 | |
AnnaBridge | 165:d1b4690b3f8b | 113 | uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. |
AnnaBridge | 165:d1b4690b3f8b | 114 | This parameter must be a number between 8 and 86 or 127 depending on devices. */ |
AnnaBridge | 165:d1b4690b3f8b | 115 | |
AnnaBridge | 165:d1b4690b3f8b | 116 | uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. |
AnnaBridge | 165:d1b4690b3f8b | 117 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
AnnaBridge | 165:d1b4690b3f8b | 118 | |
AnnaBridge | 165:d1b4690b3f8b | 119 | #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 120 | uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. |
AnnaBridge | 165:d1b4690b3f8b | 121 | This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ |
AnnaBridge | 165:d1b4690b3f8b | 122 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 123 | |
AnnaBridge | 165:d1b4690b3f8b | 124 | uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. |
AnnaBridge | 165:d1b4690b3f8b | 125 | This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ |
AnnaBridge | 165:d1b4690b3f8b | 126 | |
AnnaBridge | 165:d1b4690b3f8b | 127 | uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. |
AnnaBridge | 165:d1b4690b3f8b | 128 | This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ |
AnnaBridge | 165:d1b4690b3f8b | 129 | }RCC_PLLSAI2InitTypeDef; |
AnnaBridge | 165:d1b4690b3f8b | 130 | |
AnnaBridge | 165:d1b4690b3f8b | 131 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 132 | |
AnnaBridge | 165:d1b4690b3f8b | 133 | /** |
AnnaBridge | 165:d1b4690b3f8b | 134 | * @brief RCC extended clocks structure definition |
AnnaBridge | 165:d1b4690b3f8b | 135 | */ |
AnnaBridge | 165:d1b4690b3f8b | 136 | typedef struct |
AnnaBridge | 165:d1b4690b3f8b | 137 | { |
AnnaBridge | 165:d1b4690b3f8b | 138 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
AnnaBridge | 165:d1b4690b3f8b | 139 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
AnnaBridge | 165:d1b4690b3f8b | 140 | |
AnnaBridge | 165:d1b4690b3f8b | 141 | RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. |
AnnaBridge | 165:d1b4690b3f8b | 142 | This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ |
AnnaBridge | 165:d1b4690b3f8b | 143 | |
AnnaBridge | 165:d1b4690b3f8b | 144 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 145 | |
AnnaBridge | 165:d1b4690b3f8b | 146 | RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. |
AnnaBridge | 165:d1b4690b3f8b | 147 | This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ |
AnnaBridge | 165:d1b4690b3f8b | 148 | |
AnnaBridge | 165:d1b4690b3f8b | 149 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 150 | |
AnnaBridge | 165:d1b4690b3f8b | 151 | uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 152 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 153 | |
AnnaBridge | 165:d1b4690b3f8b | 154 | uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 155 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 156 | |
AnnaBridge | 165:d1b4690b3f8b | 157 | #if defined(USART3) |
AnnaBridge | 165:d1b4690b3f8b | 158 | |
AnnaBridge | 165:d1b4690b3f8b | 159 | uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 160 | This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 161 | |
AnnaBridge | 165:d1b4690b3f8b | 162 | #endif /* USART3 */ |
AnnaBridge | 165:d1b4690b3f8b | 163 | |
AnnaBridge | 165:d1b4690b3f8b | 164 | #if defined(UART4) |
AnnaBridge | 165:d1b4690b3f8b | 165 | |
AnnaBridge | 165:d1b4690b3f8b | 166 | uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 167 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 168 | |
AnnaBridge | 165:d1b4690b3f8b | 169 | #endif /* UART4 */ |
AnnaBridge | 165:d1b4690b3f8b | 170 | |
AnnaBridge | 165:d1b4690b3f8b | 171 | #if defined(UART5) |
AnnaBridge | 165:d1b4690b3f8b | 172 | |
AnnaBridge | 165:d1b4690b3f8b | 173 | uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 174 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 175 | |
AnnaBridge | 165:d1b4690b3f8b | 176 | #endif /* UART5 */ |
AnnaBridge | 165:d1b4690b3f8b | 177 | |
AnnaBridge | 165:d1b4690b3f8b | 178 | uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 179 | This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 180 | |
AnnaBridge | 165:d1b4690b3f8b | 181 | uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 182 | This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 183 | |
AnnaBridge | 165:d1b4690b3f8b | 184 | #if defined(I2C2) |
AnnaBridge | 165:d1b4690b3f8b | 185 | |
AnnaBridge | 165:d1b4690b3f8b | 186 | uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 187 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 188 | |
AnnaBridge | 165:d1b4690b3f8b | 189 | #endif /* I2C2 */ |
AnnaBridge | 165:d1b4690b3f8b | 190 | |
AnnaBridge | 165:d1b4690b3f8b | 191 | uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 192 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 193 | |
AnnaBridge | 165:d1b4690b3f8b | 194 | #if defined(I2C4) |
AnnaBridge | 165:d1b4690b3f8b | 195 | |
AnnaBridge | 165:d1b4690b3f8b | 196 | uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 197 | This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 198 | |
AnnaBridge | 165:d1b4690b3f8b | 199 | #endif /* I2C4 */ |
AnnaBridge | 165:d1b4690b3f8b | 200 | |
AnnaBridge | 165:d1b4690b3f8b | 201 | uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 202 | This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 203 | |
AnnaBridge | 165:d1b4690b3f8b | 204 | uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 205 | This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 206 | |
AnnaBridge | 165:d1b4690b3f8b | 207 | uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 208 | This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 209 | |
AnnaBridge | 165:d1b4690b3f8b | 210 | #if defined(SAI2) |
AnnaBridge | 165:d1b4690b3f8b | 211 | |
AnnaBridge | 165:d1b4690b3f8b | 212 | uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 213 | This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 214 | |
AnnaBridge | 165:d1b4690b3f8b | 215 | #endif /* SAI2 */ |
AnnaBridge | 165:d1b4690b3f8b | 216 | |
AnnaBridge | 165:d1b4690b3f8b | 217 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 165:d1b4690b3f8b | 218 | |
AnnaBridge | 165:d1b4690b3f8b | 219 | uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). |
AnnaBridge | 165:d1b4690b3f8b | 220 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 221 | |
AnnaBridge | 165:d1b4690b3f8b | 222 | #endif /* USB_OTG_FS || USB */ |
AnnaBridge | 165:d1b4690b3f8b | 223 | |
AnnaBridge | 165:d1b4690b3f8b | 224 | #if defined(SDMMC1) |
AnnaBridge | 165:d1b4690b3f8b | 225 | |
AnnaBridge | 165:d1b4690b3f8b | 226 | uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). |
AnnaBridge | 165:d1b4690b3f8b | 227 | This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 228 | |
AnnaBridge | 165:d1b4690b3f8b | 229 | #endif /* SDMMC1 */ |
AnnaBridge | 165:d1b4690b3f8b | 230 | |
AnnaBridge | 165:d1b4690b3f8b | 231 | uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). |
AnnaBridge | 165:d1b4690b3f8b | 232 | This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 233 | |
AnnaBridge | 165:d1b4690b3f8b | 234 | uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. |
AnnaBridge | 165:d1b4690b3f8b | 235 | This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 236 | |
AnnaBridge | 165:d1b4690b3f8b | 237 | #if defined(SWPMI1) |
AnnaBridge | 165:d1b4690b3f8b | 238 | |
AnnaBridge | 165:d1b4690b3f8b | 239 | uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 240 | This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 241 | |
AnnaBridge | 165:d1b4690b3f8b | 242 | #endif /* SWPMI1 */ |
AnnaBridge | 165:d1b4690b3f8b | 243 | |
AnnaBridge | 165:d1b4690b3f8b | 244 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 165:d1b4690b3f8b | 245 | |
AnnaBridge | 165:d1b4690b3f8b | 246 | uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 247 | This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 248 | |
AnnaBridge | 165:d1b4690b3f8b | 249 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 250 | uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. |
AnnaBridge | 165:d1b4690b3f8b | 251 | This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 252 | |
AnnaBridge | 165:d1b4690b3f8b | 253 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 254 | |
AnnaBridge | 165:d1b4690b3f8b | 255 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 165:d1b4690b3f8b | 256 | |
AnnaBridge | 165:d1b4690b3f8b | 257 | #if defined(LTDC) |
AnnaBridge | 165:d1b4690b3f8b | 258 | |
AnnaBridge | 165:d1b4690b3f8b | 259 | uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. |
AnnaBridge | 165:d1b4690b3f8b | 260 | This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 261 | |
AnnaBridge | 165:d1b4690b3f8b | 262 | #endif /* LTDC */ |
AnnaBridge | 165:d1b4690b3f8b | 263 | |
AnnaBridge | 165:d1b4690b3f8b | 264 | #if defined(DSI) |
AnnaBridge | 165:d1b4690b3f8b | 265 | |
AnnaBridge | 165:d1b4690b3f8b | 266 | uint32_t DsiClockSelection; /*!< Specifies DSI clock source. |
AnnaBridge | 165:d1b4690b3f8b | 267 | This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 268 | |
AnnaBridge | 165:d1b4690b3f8b | 269 | #endif /* DSI */ |
AnnaBridge | 165:d1b4690b3f8b | 270 | |
AnnaBridge | 165:d1b4690b3f8b | 271 | #if defined(OCTOSPI1) || defined(OCTOSPI2) |
AnnaBridge | 165:d1b4690b3f8b | 272 | |
AnnaBridge | 165:d1b4690b3f8b | 273 | uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. |
AnnaBridge | 165:d1b4690b3f8b | 274 | This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 275 | |
AnnaBridge | 165:d1b4690b3f8b | 276 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 277 | |
AnnaBridge | 165:d1b4690b3f8b | 278 | uint32_t RTCClockSelection; /*!< Specifies RTC clock source. |
AnnaBridge | 165:d1b4690b3f8b | 279 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
AnnaBridge | 165:d1b4690b3f8b | 280 | }RCC_PeriphCLKInitTypeDef; |
AnnaBridge | 165:d1b4690b3f8b | 281 | |
AnnaBridge | 165:d1b4690b3f8b | 282 | #if defined(CRS) |
AnnaBridge | 165:d1b4690b3f8b | 283 | |
AnnaBridge | 165:d1b4690b3f8b | 284 | /** |
AnnaBridge | 165:d1b4690b3f8b | 285 | * @brief RCC_CRS Init structure definition |
AnnaBridge | 165:d1b4690b3f8b | 286 | */ |
AnnaBridge | 165:d1b4690b3f8b | 287 | typedef struct |
AnnaBridge | 165:d1b4690b3f8b | 288 | { |
AnnaBridge | 165:d1b4690b3f8b | 289 | uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. |
AnnaBridge | 165:d1b4690b3f8b | 290 | This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ |
AnnaBridge | 165:d1b4690b3f8b | 291 | |
AnnaBridge | 165:d1b4690b3f8b | 292 | uint32_t Source; /*!< Specifies the SYNC signal source. |
AnnaBridge | 165:d1b4690b3f8b | 293 | This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ |
AnnaBridge | 165:d1b4690b3f8b | 294 | |
AnnaBridge | 165:d1b4690b3f8b | 295 | uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. |
AnnaBridge | 165:d1b4690b3f8b | 296 | This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ |
AnnaBridge | 165:d1b4690b3f8b | 297 | |
AnnaBridge | 165:d1b4690b3f8b | 298 | uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. |
AnnaBridge | 165:d1b4690b3f8b | 299 | It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) |
AnnaBridge | 165:d1b4690b3f8b | 300 | This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ |
AnnaBridge | 165:d1b4690b3f8b | 301 | |
AnnaBridge | 165:d1b4690b3f8b | 302 | uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. |
AnnaBridge | 165:d1b4690b3f8b | 303 | This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ |
AnnaBridge | 165:d1b4690b3f8b | 304 | |
AnnaBridge | 165:d1b4690b3f8b | 305 | uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. |
AnnaBridge | 165:d1b4690b3f8b | 306 | This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ |
AnnaBridge | 165:d1b4690b3f8b | 307 | |
AnnaBridge | 165:d1b4690b3f8b | 308 | }RCC_CRSInitTypeDef; |
AnnaBridge | 165:d1b4690b3f8b | 309 | |
AnnaBridge | 165:d1b4690b3f8b | 310 | /** |
AnnaBridge | 165:d1b4690b3f8b | 311 | * @brief RCC_CRS Synchronization structure definition |
AnnaBridge | 165:d1b4690b3f8b | 312 | */ |
AnnaBridge | 165:d1b4690b3f8b | 313 | typedef struct |
AnnaBridge | 165:d1b4690b3f8b | 314 | { |
AnnaBridge | 165:d1b4690b3f8b | 315 | uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. |
AnnaBridge | 165:d1b4690b3f8b | 316 | This parameter must be a number between 0 and 0xFFFF */ |
AnnaBridge | 165:d1b4690b3f8b | 317 | |
AnnaBridge | 165:d1b4690b3f8b | 318 | uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. |
AnnaBridge | 165:d1b4690b3f8b | 319 | This parameter must be a number between 0 and 0x3F */ |
AnnaBridge | 165:d1b4690b3f8b | 320 | |
AnnaBridge | 165:d1b4690b3f8b | 321 | uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter |
AnnaBridge | 165:d1b4690b3f8b | 322 | value latched in the time of the last SYNC event. |
AnnaBridge | 165:d1b4690b3f8b | 323 | This parameter must be a number between 0 and 0xFFFF */ |
AnnaBridge | 165:d1b4690b3f8b | 324 | |
AnnaBridge | 165:d1b4690b3f8b | 325 | uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the |
AnnaBridge | 165:d1b4690b3f8b | 326 | frequency error counter latched in the time of the last SYNC event. |
AnnaBridge | 165:d1b4690b3f8b | 327 | It shows whether the actual frequency is below or above the target. |
AnnaBridge | 165:d1b4690b3f8b | 328 | This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ |
AnnaBridge | 165:d1b4690b3f8b | 329 | |
AnnaBridge | 165:d1b4690b3f8b | 330 | }RCC_CRSSynchroInfoTypeDef; |
AnnaBridge | 165:d1b4690b3f8b | 331 | |
AnnaBridge | 165:d1b4690b3f8b | 332 | #endif /* CRS */ |
AnnaBridge | 165:d1b4690b3f8b | 333 | /** |
AnnaBridge | 165:d1b4690b3f8b | 334 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 335 | */ |
AnnaBridge | 165:d1b4690b3f8b | 336 | |
AnnaBridge | 165:d1b4690b3f8b | 337 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 338 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
AnnaBridge | 165:d1b4690b3f8b | 339 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 340 | */ |
AnnaBridge | 165:d1b4690b3f8b | 341 | |
AnnaBridge | 165:d1b4690b3f8b | 342 | /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 343 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 344 | */ |
AnnaBridge | 165:d1b4690b3f8b | 345 | #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ |
AnnaBridge | 165:d1b4690b3f8b | 346 | #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ |
AnnaBridge | 165:d1b4690b3f8b | 347 | /** |
AnnaBridge | 165:d1b4690b3f8b | 348 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 349 | */ |
AnnaBridge | 165:d1b4690b3f8b | 350 | |
AnnaBridge | 165:d1b4690b3f8b | 351 | /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection |
AnnaBridge | 165:d1b4690b3f8b | 352 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 353 | */ |
AnnaBridge | 165:d1b4690b3f8b | 354 | #define RCC_PERIPHCLK_USART1 0x00000001U |
AnnaBridge | 165:d1b4690b3f8b | 355 | #define RCC_PERIPHCLK_USART2 0x00000002U |
AnnaBridge | 165:d1b4690b3f8b | 356 | #if defined(USART3) |
AnnaBridge | 165:d1b4690b3f8b | 357 | #define RCC_PERIPHCLK_USART3 0x00000004U |
AnnaBridge | 165:d1b4690b3f8b | 358 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 359 | #if defined(UART4) |
AnnaBridge | 165:d1b4690b3f8b | 360 | #define RCC_PERIPHCLK_UART4 0x00000008U |
AnnaBridge | 165:d1b4690b3f8b | 361 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 362 | #if defined(UART5) |
AnnaBridge | 165:d1b4690b3f8b | 363 | #define RCC_PERIPHCLK_UART5 0x00000010U |
AnnaBridge | 165:d1b4690b3f8b | 364 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 365 | #define RCC_PERIPHCLK_LPUART1 0x00000020U |
AnnaBridge | 165:d1b4690b3f8b | 366 | #define RCC_PERIPHCLK_I2C1 0x00000040U |
AnnaBridge | 165:d1b4690b3f8b | 367 | #if defined(I2C2) |
AnnaBridge | 165:d1b4690b3f8b | 368 | #define RCC_PERIPHCLK_I2C2 0x00000080U |
AnnaBridge | 165:d1b4690b3f8b | 369 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 370 | #define RCC_PERIPHCLK_I2C3 0x00000100U |
AnnaBridge | 165:d1b4690b3f8b | 371 | #define RCC_PERIPHCLK_LPTIM1 0x00000200U |
AnnaBridge | 165:d1b4690b3f8b | 372 | #define RCC_PERIPHCLK_LPTIM2 0x00000400U |
AnnaBridge | 165:d1b4690b3f8b | 373 | #define RCC_PERIPHCLK_SAI1 0x00000800U |
AnnaBridge | 165:d1b4690b3f8b | 374 | #if defined(SAI2) |
AnnaBridge | 165:d1b4690b3f8b | 375 | #define RCC_PERIPHCLK_SAI2 0x00001000U |
AnnaBridge | 165:d1b4690b3f8b | 376 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 377 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 165:d1b4690b3f8b | 378 | #define RCC_PERIPHCLK_USB 0x00002000U |
AnnaBridge | 165:d1b4690b3f8b | 379 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 380 | #define RCC_PERIPHCLK_ADC 0x00004000U |
AnnaBridge | 165:d1b4690b3f8b | 381 | #if defined(SWPMI1) |
AnnaBridge | 165:d1b4690b3f8b | 382 | #define RCC_PERIPHCLK_SWPMI1 0x00008000U |
AnnaBridge | 165:d1b4690b3f8b | 383 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 384 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 165:d1b4690b3f8b | 385 | #define RCC_PERIPHCLK_DFSDM1 0x00010000U |
AnnaBridge | 165:d1b4690b3f8b | 386 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 387 | #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U |
AnnaBridge | 165:d1b4690b3f8b | 388 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 389 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 390 | #define RCC_PERIPHCLK_RTC 0x00020000U |
AnnaBridge | 165:d1b4690b3f8b | 391 | #define RCC_PERIPHCLK_RNG 0x00040000U |
AnnaBridge | 165:d1b4690b3f8b | 392 | #if defined(SDMMC1) |
AnnaBridge | 165:d1b4690b3f8b | 393 | #define RCC_PERIPHCLK_SDMMC1 0x00080000U |
AnnaBridge | 165:d1b4690b3f8b | 394 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 395 | #if defined(I2C4) |
AnnaBridge | 165:d1b4690b3f8b | 396 | #define RCC_PERIPHCLK_I2C4 0x00100000U |
AnnaBridge | 165:d1b4690b3f8b | 397 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 398 | #if defined(LTDC) |
AnnaBridge | 165:d1b4690b3f8b | 399 | #define RCC_PERIPHCLK_LTDC 0x00400000U |
AnnaBridge | 165:d1b4690b3f8b | 400 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 401 | #if defined(DSI) |
AnnaBridge | 165:d1b4690b3f8b | 402 | #define RCC_PERIPHCLK_DSI 0x00800000U |
AnnaBridge | 165:d1b4690b3f8b | 403 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 404 | #if defined(OCTOSPI1) || defined(OCTOSPI2) |
AnnaBridge | 165:d1b4690b3f8b | 405 | #define RCC_PERIPHCLK_OSPI 0x01000000U |
AnnaBridge | 165:d1b4690b3f8b | 406 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 407 | /** |
AnnaBridge | 165:d1b4690b3f8b | 408 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 409 | */ |
AnnaBridge | 165:d1b4690b3f8b | 410 | |
AnnaBridge | 165:d1b4690b3f8b | 411 | |
AnnaBridge | 165:d1b4690b3f8b | 412 | /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 413 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 414 | */ |
AnnaBridge | 165:d1b4690b3f8b | 415 | #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 416 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 417 | #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 418 | #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) |
AnnaBridge | 165:d1b4690b3f8b | 419 | /** |
AnnaBridge | 165:d1b4690b3f8b | 420 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 421 | */ |
AnnaBridge | 165:d1b4690b3f8b | 422 | |
AnnaBridge | 165:d1b4690b3f8b | 423 | /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 424 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 425 | */ |
AnnaBridge | 165:d1b4690b3f8b | 426 | #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 427 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 428 | #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 429 | #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) |
AnnaBridge | 165:d1b4690b3f8b | 430 | /** |
AnnaBridge | 165:d1b4690b3f8b | 431 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 432 | */ |
AnnaBridge | 165:d1b4690b3f8b | 433 | |
AnnaBridge | 165:d1b4690b3f8b | 434 | #if defined(USART3) |
AnnaBridge | 165:d1b4690b3f8b | 435 | /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 436 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 437 | */ |
AnnaBridge | 165:d1b4690b3f8b | 438 | #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 439 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 440 | #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 441 | #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) |
AnnaBridge | 165:d1b4690b3f8b | 442 | /** |
AnnaBridge | 165:d1b4690b3f8b | 443 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 444 | */ |
AnnaBridge | 165:d1b4690b3f8b | 445 | #endif /* USART3 */ |
AnnaBridge | 165:d1b4690b3f8b | 446 | |
AnnaBridge | 165:d1b4690b3f8b | 447 | #if defined(UART4) |
AnnaBridge | 165:d1b4690b3f8b | 448 | /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 449 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 450 | */ |
AnnaBridge | 165:d1b4690b3f8b | 451 | #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 452 | #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 453 | #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 454 | #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) |
AnnaBridge | 165:d1b4690b3f8b | 455 | /** |
AnnaBridge | 165:d1b4690b3f8b | 456 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 457 | */ |
AnnaBridge | 165:d1b4690b3f8b | 458 | #endif /* UART4 */ |
AnnaBridge | 165:d1b4690b3f8b | 459 | |
AnnaBridge | 165:d1b4690b3f8b | 460 | #if defined(UART5) |
AnnaBridge | 165:d1b4690b3f8b | 461 | /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 462 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 463 | */ |
AnnaBridge | 165:d1b4690b3f8b | 464 | #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 465 | #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 466 | #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 467 | #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) |
AnnaBridge | 165:d1b4690b3f8b | 468 | /** |
AnnaBridge | 165:d1b4690b3f8b | 469 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 470 | */ |
AnnaBridge | 165:d1b4690b3f8b | 471 | #endif /* UART5 */ |
AnnaBridge | 165:d1b4690b3f8b | 472 | |
AnnaBridge | 165:d1b4690b3f8b | 473 | /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 474 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 475 | */ |
AnnaBridge | 165:d1b4690b3f8b | 476 | #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 477 | #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 478 | #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 479 | #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) |
AnnaBridge | 165:d1b4690b3f8b | 480 | /** |
AnnaBridge | 165:d1b4690b3f8b | 481 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 482 | */ |
AnnaBridge | 165:d1b4690b3f8b | 483 | |
AnnaBridge | 165:d1b4690b3f8b | 484 | /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 485 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 486 | */ |
AnnaBridge | 165:d1b4690b3f8b | 487 | #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 488 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 489 | #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 490 | /** |
AnnaBridge | 165:d1b4690b3f8b | 491 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 492 | */ |
AnnaBridge | 165:d1b4690b3f8b | 493 | |
AnnaBridge | 165:d1b4690b3f8b | 494 | #if defined(I2C2) |
AnnaBridge | 165:d1b4690b3f8b | 495 | /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 496 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 497 | */ |
AnnaBridge | 165:d1b4690b3f8b | 498 | #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 499 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 500 | #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 501 | /** |
AnnaBridge | 165:d1b4690b3f8b | 502 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 503 | */ |
AnnaBridge | 165:d1b4690b3f8b | 504 | #endif /* I2C2 */ |
AnnaBridge | 165:d1b4690b3f8b | 505 | |
AnnaBridge | 165:d1b4690b3f8b | 506 | /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 507 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 508 | */ |
AnnaBridge | 165:d1b4690b3f8b | 509 | #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 510 | #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 511 | #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 512 | /** |
AnnaBridge | 165:d1b4690b3f8b | 513 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 514 | */ |
AnnaBridge | 165:d1b4690b3f8b | 515 | |
AnnaBridge | 165:d1b4690b3f8b | 516 | #if defined(I2C4) |
AnnaBridge | 165:d1b4690b3f8b | 517 | /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 518 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 519 | */ |
AnnaBridge | 165:d1b4690b3f8b | 520 | #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 521 | #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 522 | #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 523 | /** |
AnnaBridge | 165:d1b4690b3f8b | 524 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 525 | */ |
AnnaBridge | 165:d1b4690b3f8b | 526 | #endif /* I2C4 */ |
AnnaBridge | 165:d1b4690b3f8b | 527 | |
AnnaBridge | 165:d1b4690b3f8b | 528 | /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 529 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 530 | */ |
AnnaBridge | 165:d1b4690b3f8b | 531 | #define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 532 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 533 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 534 | #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 535 | #else |
AnnaBridge | 165:d1b4690b3f8b | 536 | #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 537 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 538 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 539 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 540 | #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 541 | #define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) |
AnnaBridge | 165:d1b4690b3f8b | 542 | #define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 |
AnnaBridge | 165:d1b4690b3f8b | 543 | #else |
AnnaBridge | 165:d1b4690b3f8b | 544 | #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 545 | #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL |
AnnaBridge | 165:d1b4690b3f8b | 546 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 547 | /** |
AnnaBridge | 165:d1b4690b3f8b | 548 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 549 | */ |
AnnaBridge | 165:d1b4690b3f8b | 550 | |
AnnaBridge | 165:d1b4690b3f8b | 551 | #if defined(SAI2) |
AnnaBridge | 165:d1b4690b3f8b | 552 | /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 553 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 554 | */ |
AnnaBridge | 165:d1b4690b3f8b | 555 | #define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 556 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 557 | #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 558 | #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 559 | #define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) |
AnnaBridge | 165:d1b4690b3f8b | 560 | #define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 |
AnnaBridge | 165:d1b4690b3f8b | 561 | #else |
AnnaBridge | 165:d1b4690b3f8b | 562 | #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 563 | #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 564 | #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL |
AnnaBridge | 165:d1b4690b3f8b | 565 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 566 | /** |
AnnaBridge | 165:d1b4690b3f8b | 567 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 568 | */ |
AnnaBridge | 165:d1b4690b3f8b | 569 | #endif /* SAI2 */ |
AnnaBridge | 165:d1b4690b3f8b | 570 | |
AnnaBridge | 165:d1b4690b3f8b | 571 | /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 572 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 573 | */ |
AnnaBridge | 165:d1b4690b3f8b | 574 | #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 575 | #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 576 | #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 577 | #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL |
AnnaBridge | 165:d1b4690b3f8b | 578 | /** |
AnnaBridge | 165:d1b4690b3f8b | 579 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 580 | */ |
AnnaBridge | 165:d1b4690b3f8b | 581 | |
AnnaBridge | 165:d1b4690b3f8b | 582 | /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 583 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 584 | */ |
AnnaBridge | 165:d1b4690b3f8b | 585 | #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 586 | #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 587 | #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 588 | #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL |
AnnaBridge | 165:d1b4690b3f8b | 589 | /** |
AnnaBridge | 165:d1b4690b3f8b | 590 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 591 | */ |
AnnaBridge | 165:d1b4690b3f8b | 592 | |
AnnaBridge | 165:d1b4690b3f8b | 593 | #if defined(SDMMC1) |
AnnaBridge | 165:d1b4690b3f8b | 594 | /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 595 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 596 | */ |
AnnaBridge | 165:d1b4690b3f8b | 597 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 598 | #define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ |
AnnaBridge | 165:d1b4690b3f8b | 599 | #else |
AnnaBridge | 165:d1b4690b3f8b | 600 | #define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ |
AnnaBridge | 165:d1b4690b3f8b | 601 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 602 | #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ |
AnnaBridge | 165:d1b4690b3f8b | 603 | #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ |
AnnaBridge | 165:d1b4690b3f8b | 604 | #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ |
AnnaBridge | 165:d1b4690b3f8b | 605 | #if defined(RCC_CCIPR2_SDMMCSEL) |
AnnaBridge | 165:d1b4690b3f8b | 606 | #define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ |
AnnaBridge | 165:d1b4690b3f8b | 607 | #endif /* RCC_CCIPR2_SDMMCSEL */ |
AnnaBridge | 165:d1b4690b3f8b | 608 | /** |
AnnaBridge | 165:d1b4690b3f8b | 609 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 610 | */ |
AnnaBridge | 165:d1b4690b3f8b | 611 | #endif /* SDMMC1 */ |
AnnaBridge | 165:d1b4690b3f8b | 612 | |
AnnaBridge | 165:d1b4690b3f8b | 613 | /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 614 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 615 | */ |
AnnaBridge | 165:d1b4690b3f8b | 616 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 617 | #define RCC_RNGCLKSOURCE_HSI48 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 618 | #else |
AnnaBridge | 165:d1b4690b3f8b | 619 | #define RCC_RNGCLKSOURCE_NONE 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 620 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 621 | #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 622 | #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 623 | #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
AnnaBridge | 165:d1b4690b3f8b | 624 | /** |
AnnaBridge | 165:d1b4690b3f8b | 625 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 626 | */ |
AnnaBridge | 165:d1b4690b3f8b | 627 | |
AnnaBridge | 165:d1b4690b3f8b | 628 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 165:d1b4690b3f8b | 629 | /** @defgroup RCCEx_USB_Clock_Source USB Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 630 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 631 | */ |
AnnaBridge | 165:d1b4690b3f8b | 632 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 633 | #define RCC_USBCLKSOURCE_HSI48 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 634 | #else |
AnnaBridge | 165:d1b4690b3f8b | 635 | #define RCC_USBCLKSOURCE_NONE 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 636 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 637 | #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 638 | #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 639 | #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
AnnaBridge | 165:d1b4690b3f8b | 640 | /** |
AnnaBridge | 165:d1b4690b3f8b | 641 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 642 | */ |
AnnaBridge | 165:d1b4690b3f8b | 643 | #endif /* USB_OTG_FS || USB */ |
AnnaBridge | 165:d1b4690b3f8b | 644 | |
AnnaBridge | 165:d1b4690b3f8b | 645 | /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 646 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 647 | */ |
AnnaBridge | 165:d1b4690b3f8b | 648 | #define RCC_ADCCLKSOURCE_NONE 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 649 | #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 650 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) |
AnnaBridge | 165:d1b4690b3f8b | 651 | #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 652 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ |
AnnaBridge | 165:d1b4690b3f8b | 653 | #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL |
AnnaBridge | 165:d1b4690b3f8b | 654 | /** |
AnnaBridge | 165:d1b4690b3f8b | 655 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 656 | */ |
AnnaBridge | 165:d1b4690b3f8b | 657 | |
AnnaBridge | 165:d1b4690b3f8b | 658 | #if defined(SWPMI1) |
AnnaBridge | 165:d1b4690b3f8b | 659 | /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 660 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 661 | */ |
AnnaBridge | 165:d1b4690b3f8b | 662 | #define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 663 | #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL |
AnnaBridge | 165:d1b4690b3f8b | 664 | /** |
AnnaBridge | 165:d1b4690b3f8b | 665 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 666 | */ |
AnnaBridge | 165:d1b4690b3f8b | 667 | #endif /* SWPMI1 */ |
AnnaBridge | 165:d1b4690b3f8b | 668 | |
AnnaBridge | 165:d1b4690b3f8b | 669 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 165:d1b4690b3f8b | 670 | /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 671 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 672 | */ |
AnnaBridge | 165:d1b4690b3f8b | 673 | #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 674 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 675 | #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL |
AnnaBridge | 165:d1b4690b3f8b | 676 | #else |
AnnaBridge | 165:d1b4690b3f8b | 677 | #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL |
AnnaBridge | 165:d1b4690b3f8b | 678 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 679 | /** |
AnnaBridge | 165:d1b4690b3f8b | 680 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 681 | */ |
AnnaBridge | 165:d1b4690b3f8b | 682 | |
AnnaBridge | 165:d1b4690b3f8b | 683 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 684 | /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 685 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 686 | */ |
AnnaBridge | 165:d1b4690b3f8b | 687 | #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 688 | #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 689 | #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 690 | /** |
AnnaBridge | 165:d1b4690b3f8b | 691 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 692 | */ |
AnnaBridge | 165:d1b4690b3f8b | 693 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 694 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 165:d1b4690b3f8b | 695 | |
AnnaBridge | 165:d1b4690b3f8b | 696 | #if defined(LTDC) |
AnnaBridge | 165:d1b4690b3f8b | 697 | /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 698 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 699 | */ |
AnnaBridge | 165:d1b4690b3f8b | 700 | #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 701 | #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 |
AnnaBridge | 165:d1b4690b3f8b | 702 | #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 |
AnnaBridge | 165:d1b4690b3f8b | 703 | #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR |
AnnaBridge | 165:d1b4690b3f8b | 704 | /** |
AnnaBridge | 165:d1b4690b3f8b | 705 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 706 | */ |
AnnaBridge | 165:d1b4690b3f8b | 707 | #endif /* LTDC */ |
AnnaBridge | 165:d1b4690b3f8b | 708 | |
AnnaBridge | 165:d1b4690b3f8b | 709 | #if defined(DSI) |
AnnaBridge | 165:d1b4690b3f8b | 710 | /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 711 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 712 | */ |
AnnaBridge | 165:d1b4690b3f8b | 713 | #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 714 | #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL |
AnnaBridge | 165:d1b4690b3f8b | 715 | /** |
AnnaBridge | 165:d1b4690b3f8b | 716 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 717 | */ |
AnnaBridge | 165:d1b4690b3f8b | 718 | #endif /* DSI */ |
AnnaBridge | 165:d1b4690b3f8b | 719 | |
AnnaBridge | 165:d1b4690b3f8b | 720 | #if defined(OCTOSPI1) || defined(OCTOSPI2) |
AnnaBridge | 165:d1b4690b3f8b | 721 | /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source |
AnnaBridge | 165:d1b4690b3f8b | 722 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 723 | */ |
AnnaBridge | 165:d1b4690b3f8b | 724 | #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 725 | #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 |
AnnaBridge | 165:d1b4690b3f8b | 726 | #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 |
AnnaBridge | 165:d1b4690b3f8b | 727 | /** |
AnnaBridge | 165:d1b4690b3f8b | 728 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 729 | */ |
AnnaBridge | 165:d1b4690b3f8b | 730 | #endif /* OCTOSPI1 || OCTOSPI2 */ |
AnnaBridge | 165:d1b4690b3f8b | 731 | |
AnnaBridge | 165:d1b4690b3f8b | 732 | /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line |
AnnaBridge | 165:d1b4690b3f8b | 733 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 734 | */ |
AnnaBridge | 165:d1b4690b3f8b | 735 | #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ |
AnnaBridge | 165:d1b4690b3f8b | 736 | /** |
AnnaBridge | 165:d1b4690b3f8b | 737 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 738 | */ |
AnnaBridge | 165:d1b4690b3f8b | 739 | |
AnnaBridge | 165:d1b4690b3f8b | 740 | #if defined(CRS) |
AnnaBridge | 165:d1b4690b3f8b | 741 | |
AnnaBridge | 165:d1b4690b3f8b | 742 | /** @defgroup RCCEx_CRS_Status RCCEx CRS Status |
AnnaBridge | 165:d1b4690b3f8b | 743 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 744 | */ |
AnnaBridge | 165:d1b4690b3f8b | 745 | #define RCC_CRS_NONE 0x00000000U |
AnnaBridge | 165:d1b4690b3f8b | 746 | #define RCC_CRS_TIMEOUT 0x00000001U |
AnnaBridge | 165:d1b4690b3f8b | 747 | #define RCC_CRS_SYNCOK 0x00000002U |
AnnaBridge | 165:d1b4690b3f8b | 748 | #define RCC_CRS_SYNCWARN 0x00000004U |
AnnaBridge | 165:d1b4690b3f8b | 749 | #define RCC_CRS_SYNCERR 0x00000008U |
AnnaBridge | 165:d1b4690b3f8b | 750 | #define RCC_CRS_SYNCMISS 0x00000010U |
AnnaBridge | 165:d1b4690b3f8b | 751 | #define RCC_CRS_TRIMOVF 0x00000020U |
AnnaBridge | 165:d1b4690b3f8b | 752 | /** |
AnnaBridge | 165:d1b4690b3f8b | 753 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 754 | */ |
AnnaBridge | 165:d1b4690b3f8b | 755 | |
AnnaBridge | 165:d1b4690b3f8b | 756 | /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource |
AnnaBridge | 165:d1b4690b3f8b | 757 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 758 | */ |
AnnaBridge | 165:d1b4690b3f8b | 759 | #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ |
AnnaBridge | 165:d1b4690b3f8b | 760 | #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ |
AnnaBridge | 165:d1b4690b3f8b | 761 | #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ |
AnnaBridge | 165:d1b4690b3f8b | 762 | /** |
AnnaBridge | 165:d1b4690b3f8b | 763 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 764 | */ |
AnnaBridge | 165:d1b4690b3f8b | 765 | |
AnnaBridge | 165:d1b4690b3f8b | 766 | /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider |
AnnaBridge | 165:d1b4690b3f8b | 767 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 768 | */ |
AnnaBridge | 165:d1b4690b3f8b | 769 | #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ |
AnnaBridge | 165:d1b4690b3f8b | 770 | #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ |
AnnaBridge | 165:d1b4690b3f8b | 771 | #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ |
AnnaBridge | 165:d1b4690b3f8b | 772 | #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ |
AnnaBridge | 165:d1b4690b3f8b | 773 | #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ |
AnnaBridge | 165:d1b4690b3f8b | 774 | #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ |
AnnaBridge | 165:d1b4690b3f8b | 775 | #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ |
AnnaBridge | 165:d1b4690b3f8b | 776 | #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ |
AnnaBridge | 165:d1b4690b3f8b | 777 | /** |
AnnaBridge | 165:d1b4690b3f8b | 778 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 779 | */ |
AnnaBridge | 165:d1b4690b3f8b | 780 | |
AnnaBridge | 165:d1b4690b3f8b | 781 | /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity |
AnnaBridge | 165:d1b4690b3f8b | 782 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 783 | */ |
AnnaBridge | 165:d1b4690b3f8b | 784 | #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ |
AnnaBridge | 165:d1b4690b3f8b | 785 | #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ |
AnnaBridge | 165:d1b4690b3f8b | 786 | /** |
AnnaBridge | 165:d1b4690b3f8b | 787 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 788 | */ |
AnnaBridge | 165:d1b4690b3f8b | 789 | |
AnnaBridge | 165:d1b4690b3f8b | 790 | /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault |
AnnaBridge | 165:d1b4690b3f8b | 791 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 792 | */ |
AnnaBridge | 165:d1b4690b3f8b | 793 | #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds |
AnnaBridge | 165:d1b4690b3f8b | 794 | to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ |
AnnaBridge | 165:d1b4690b3f8b | 795 | /** |
AnnaBridge | 165:d1b4690b3f8b | 796 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 797 | */ |
AnnaBridge | 165:d1b4690b3f8b | 798 | |
AnnaBridge | 165:d1b4690b3f8b | 799 | /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault |
AnnaBridge | 165:d1b4690b3f8b | 800 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 801 | */ |
AnnaBridge | 165:d1b4690b3f8b | 802 | #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ |
AnnaBridge | 165:d1b4690b3f8b | 803 | /** |
AnnaBridge | 165:d1b4690b3f8b | 804 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 805 | */ |
AnnaBridge | 165:d1b4690b3f8b | 806 | |
AnnaBridge | 165:d1b4690b3f8b | 807 | /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault |
AnnaBridge | 165:d1b4690b3f8b | 808 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 809 | */ |
AnnaBridge | 165:d1b4690b3f8b | 810 | #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. |
AnnaBridge | 165:d1b4690b3f8b | 811 | The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value |
AnnaBridge | 165:d1b4690b3f8b | 812 | corresponds to a higher output frequency */ |
AnnaBridge | 165:d1b4690b3f8b | 813 | /** |
AnnaBridge | 165:d1b4690b3f8b | 814 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 815 | */ |
AnnaBridge | 165:d1b4690b3f8b | 816 | |
AnnaBridge | 165:d1b4690b3f8b | 817 | /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection |
AnnaBridge | 165:d1b4690b3f8b | 818 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 819 | */ |
AnnaBridge | 165:d1b4690b3f8b | 820 | #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ |
AnnaBridge | 165:d1b4690b3f8b | 821 | #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ |
AnnaBridge | 165:d1b4690b3f8b | 822 | /** |
AnnaBridge | 165:d1b4690b3f8b | 823 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 824 | */ |
AnnaBridge | 165:d1b4690b3f8b | 825 | |
AnnaBridge | 165:d1b4690b3f8b | 826 | /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources |
AnnaBridge | 165:d1b4690b3f8b | 827 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 828 | */ |
AnnaBridge | 165:d1b4690b3f8b | 829 | #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ |
AnnaBridge | 165:d1b4690b3f8b | 830 | #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ |
AnnaBridge | 165:d1b4690b3f8b | 831 | #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ |
AnnaBridge | 165:d1b4690b3f8b | 832 | #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ |
AnnaBridge | 165:d1b4690b3f8b | 833 | #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ |
AnnaBridge | 165:d1b4690b3f8b | 834 | #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ |
AnnaBridge | 165:d1b4690b3f8b | 835 | #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ |
AnnaBridge | 165:d1b4690b3f8b | 836 | |
AnnaBridge | 165:d1b4690b3f8b | 837 | /** |
AnnaBridge | 165:d1b4690b3f8b | 838 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 839 | */ |
AnnaBridge | 165:d1b4690b3f8b | 840 | |
AnnaBridge | 165:d1b4690b3f8b | 841 | /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags |
AnnaBridge | 165:d1b4690b3f8b | 842 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 843 | */ |
AnnaBridge | 165:d1b4690b3f8b | 844 | #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ |
AnnaBridge | 165:d1b4690b3f8b | 845 | #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ |
AnnaBridge | 165:d1b4690b3f8b | 846 | #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ |
AnnaBridge | 165:d1b4690b3f8b | 847 | #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ |
AnnaBridge | 165:d1b4690b3f8b | 848 | #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ |
AnnaBridge | 165:d1b4690b3f8b | 849 | #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ |
AnnaBridge | 165:d1b4690b3f8b | 850 | #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ |
AnnaBridge | 165:d1b4690b3f8b | 851 | |
AnnaBridge | 165:d1b4690b3f8b | 852 | /** |
AnnaBridge | 165:d1b4690b3f8b | 853 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 854 | */ |
AnnaBridge | 165:d1b4690b3f8b | 855 | |
AnnaBridge | 165:d1b4690b3f8b | 856 | #endif /* CRS */ |
AnnaBridge | 165:d1b4690b3f8b | 857 | |
AnnaBridge | 165:d1b4690b3f8b | 858 | /** |
AnnaBridge | 165:d1b4690b3f8b | 859 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 860 | */ |
AnnaBridge | 165:d1b4690b3f8b | 861 | |
AnnaBridge | 165:d1b4690b3f8b | 862 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 863 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
AnnaBridge | 165:d1b4690b3f8b | 864 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 865 | */ |
AnnaBridge | 165:d1b4690b3f8b | 866 | |
AnnaBridge | 165:d1b4690b3f8b | 867 | |
AnnaBridge | 165:d1b4690b3f8b | 868 | /** |
AnnaBridge | 165:d1b4690b3f8b | 869 | * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. |
AnnaBridge | 165:d1b4690b3f8b | 870 | * |
AnnaBridge | 165:d1b4690b3f8b | 871 | * @note This function must be used only when the PLLSAI1 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 872 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 873 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 874 | * |
AnnaBridge | 165:d1b4690b3f8b | 875 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 876 | * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. |
AnnaBridge | 165:d1b4690b3f8b | 877 | * This parameter must be a number between Min_Data = 1 and Max_Data = 16. |
AnnaBridge | 165:d1b4690b3f8b | 878 | * |
AnnaBridge | 165:d1b4690b3f8b | 879 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 880 | * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. |
AnnaBridge | 165:d1b4690b3f8b | 881 | * This parameter must be a number between 8 and 86. |
AnnaBridge | 165:d1b4690b3f8b | 882 | * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO |
AnnaBridge | 165:d1b4690b3f8b | 883 | * output frequency is between 64 and 344 MHz. |
AnnaBridge | 165:d1b4690b3f8b | 884 | * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N |
AnnaBridge | 165:d1b4690b3f8b | 885 | * |
AnnaBridge | 165:d1b4690b3f8b | 886 | * @param __PLLSAI1P__ specifies the division factor for SAI clock. |
AnnaBridge | 165:d1b4690b3f8b | 887 | * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx |
AnnaBridge | 165:d1b4690b3f8b | 888 | * else (2 to 31). |
AnnaBridge | 165:d1b4690b3f8b | 889 | * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P |
AnnaBridge | 165:d1b4690b3f8b | 890 | * |
AnnaBridge | 165:d1b4690b3f8b | 891 | * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 892 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 165:d1b4690b3f8b | 893 | * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q |
AnnaBridge | 165:d1b4690b3f8b | 894 | * |
AnnaBridge | 165:d1b4690b3f8b | 895 | * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. |
AnnaBridge | 165:d1b4690b3f8b | 896 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 165:d1b4690b3f8b | 897 | * ADC clock frequency = f(PLLSAI1) / PLLSAI1R |
AnnaBridge | 165:d1b4690b3f8b | 898 | * |
AnnaBridge | 165:d1b4690b3f8b | 899 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 900 | */ |
AnnaBridge | 165:d1b4690b3f8b | 901 | #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 902 | |
AnnaBridge | 165:d1b4690b3f8b | 903 | #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 904 | |
AnnaBridge | 165:d1b4690b3f8b | 905 | #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 906 | WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 907 | ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 908 | ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 909 | ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 910 | (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 911 | |
AnnaBridge | 165:d1b4690b3f8b | 912 | #else |
AnnaBridge | 165:d1b4690b3f8b | 913 | |
AnnaBridge | 165:d1b4690b3f8b | 914 | #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 915 | WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 916 | (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 917 | ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 918 | ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 919 | (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 920 | |
AnnaBridge | 165:d1b4690b3f8b | 921 | #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 922 | |
AnnaBridge | 165:d1b4690b3f8b | 923 | #else |
AnnaBridge | 165:d1b4690b3f8b | 924 | |
AnnaBridge | 165:d1b4690b3f8b | 925 | #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 926 | |
AnnaBridge | 165:d1b4690b3f8b | 927 | #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 928 | WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 929 | ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 930 | ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 931 | ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 932 | |
AnnaBridge | 165:d1b4690b3f8b | 933 | #else |
AnnaBridge | 165:d1b4690b3f8b | 934 | |
AnnaBridge | 165:d1b4690b3f8b | 935 | #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 936 | WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 937 | (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 938 | ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 939 | ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 940 | |
AnnaBridge | 165:d1b4690b3f8b | 941 | #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 942 | |
AnnaBridge | 165:d1b4690b3f8b | 943 | #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 944 | |
AnnaBridge | 165:d1b4690b3f8b | 945 | /** |
AnnaBridge | 165:d1b4690b3f8b | 946 | * @brief Macro to configure the PLLSAI1 clock multiplication factor N. |
AnnaBridge | 165:d1b4690b3f8b | 947 | * |
AnnaBridge | 165:d1b4690b3f8b | 948 | * @note This function must be used only when the PLLSAI1 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 949 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 950 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 951 | * |
AnnaBridge | 165:d1b4690b3f8b | 952 | * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. |
AnnaBridge | 165:d1b4690b3f8b | 953 | * This parameter must be a number between 8 and 86. |
AnnaBridge | 165:d1b4690b3f8b | 954 | * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO |
AnnaBridge | 165:d1b4690b3f8b | 955 | * output frequency is between 64 and 344 MHz. |
AnnaBridge | 165:d1b4690b3f8b | 956 | * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N |
AnnaBridge | 165:d1b4690b3f8b | 957 | * |
AnnaBridge | 165:d1b4690b3f8b | 958 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 959 | */ |
AnnaBridge | 165:d1b4690b3f8b | 960 | #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ |
AnnaBridge | 165:d1b4690b3f8b | 961 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 962 | |
AnnaBridge | 165:d1b4690b3f8b | 963 | #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 964 | |
AnnaBridge | 165:d1b4690b3f8b | 965 | /** @brief Macro to configure the PLLSAI1 input clock division factor M. |
AnnaBridge | 165:d1b4690b3f8b | 966 | * |
AnnaBridge | 165:d1b4690b3f8b | 967 | * @note This function must be used only when the PLLSAI1 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 968 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 969 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 970 | * |
AnnaBridge | 165:d1b4690b3f8b | 971 | * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 972 | * This parameter must be a number between Min_Data = 1 and Max_Data = 16. |
AnnaBridge | 165:d1b4690b3f8b | 973 | * |
AnnaBridge | 165:d1b4690b3f8b | 974 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 975 | */ |
AnnaBridge | 165:d1b4690b3f8b | 976 | |
AnnaBridge | 165:d1b4690b3f8b | 977 | #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ |
AnnaBridge | 165:d1b4690b3f8b | 978 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 979 | |
AnnaBridge | 165:d1b4690b3f8b | 980 | #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 981 | |
AnnaBridge | 165:d1b4690b3f8b | 982 | /** @brief Macro to configure the PLLSAI1 clock division factor P. |
AnnaBridge | 165:d1b4690b3f8b | 983 | * |
AnnaBridge | 165:d1b4690b3f8b | 984 | * @note This function must be used only when the PLLSAI1 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 985 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 986 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 987 | * |
AnnaBridge | 165:d1b4690b3f8b | 988 | * @param __PLLSAI1P__ specifies the division factor for SAI clock. |
AnnaBridge | 165:d1b4690b3f8b | 989 | * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx |
AnnaBridge | 165:d1b4690b3f8b | 990 | * else (2 to 31). |
AnnaBridge | 165:d1b4690b3f8b | 991 | * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P |
AnnaBridge | 165:d1b4690b3f8b | 992 | * |
AnnaBridge | 165:d1b4690b3f8b | 993 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 994 | */ |
AnnaBridge | 165:d1b4690b3f8b | 995 | #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 996 | |
AnnaBridge | 165:d1b4690b3f8b | 997 | #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ |
AnnaBridge | 165:d1b4690b3f8b | 998 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 999 | |
AnnaBridge | 165:d1b4690b3f8b | 1000 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1001 | |
AnnaBridge | 165:d1b4690b3f8b | 1002 | #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1003 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1004 | |
AnnaBridge | 165:d1b4690b3f8b | 1005 | #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 1006 | |
AnnaBridge | 165:d1b4690b3f8b | 1007 | /** @brief Macro to configure the PLLSAI1 clock division factor Q. |
AnnaBridge | 165:d1b4690b3f8b | 1008 | * |
AnnaBridge | 165:d1b4690b3f8b | 1009 | * @note This function must be used only when the PLLSAI1 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1010 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1011 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1012 | * |
AnnaBridge | 165:d1b4690b3f8b | 1013 | * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 1014 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 165:d1b4690b3f8b | 1015 | * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q |
AnnaBridge | 165:d1b4690b3f8b | 1016 | * |
AnnaBridge | 165:d1b4690b3f8b | 1017 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1018 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1019 | #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1020 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1021 | |
AnnaBridge | 165:d1b4690b3f8b | 1022 | /** @brief Macro to configure the PLLSAI1 clock division factor R. |
AnnaBridge | 165:d1b4690b3f8b | 1023 | * |
AnnaBridge | 165:d1b4690b3f8b | 1024 | * @note This function must be used only when the PLLSAI1 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1025 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1026 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1027 | * |
AnnaBridge | 165:d1b4690b3f8b | 1028 | * @param __PLLSAI1R__ specifies the division factor for ADC clock. |
AnnaBridge | 165:d1b4690b3f8b | 1029 | * This parameter must be in the range (2, 4, 6 or 8) |
AnnaBridge | 165:d1b4690b3f8b | 1030 | * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R |
AnnaBridge | 165:d1b4690b3f8b | 1031 | * |
AnnaBridge | 165:d1b4690b3f8b | 1032 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1033 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1034 | #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1035 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1036 | |
AnnaBridge | 165:d1b4690b3f8b | 1037 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1038 | * @brief Macros to enable or disable the PLLSAI1. |
AnnaBridge | 165:d1b4690b3f8b | 1039 | * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 165:d1b4690b3f8b | 1040 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1041 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1042 | |
AnnaBridge | 165:d1b4690b3f8b | 1043 | #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) |
AnnaBridge | 165:d1b4690b3f8b | 1044 | |
AnnaBridge | 165:d1b4690b3f8b | 1045 | #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) |
AnnaBridge | 165:d1b4690b3f8b | 1046 | |
AnnaBridge | 165:d1b4690b3f8b | 1047 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1048 | * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). |
AnnaBridge | 165:d1b4690b3f8b | 1049 | * @note Enabling and disabling those clocks can be done without the need to stop the PLL. |
AnnaBridge | 165:d1b4690b3f8b | 1050 | * This is mainly used to save Power. |
AnnaBridge | 165:d1b4690b3f8b | 1051 | * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. |
AnnaBridge | 165:d1b4690b3f8b | 1052 | * This parameter can be one or a combination of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1053 | * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1054 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1055 | * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), |
AnnaBridge | 165:d1b4690b3f8b | 1056 | * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). |
AnnaBridge | 165:d1b4690b3f8b | 1057 | * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1058 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1059 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1060 | |
AnnaBridge | 165:d1b4690b3f8b | 1061 | #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
AnnaBridge | 165:d1b4690b3f8b | 1062 | |
AnnaBridge | 165:d1b4690b3f8b | 1063 | #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
AnnaBridge | 165:d1b4690b3f8b | 1064 | |
AnnaBridge | 165:d1b4690b3f8b | 1065 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1066 | * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). |
AnnaBridge | 165:d1b4690b3f8b | 1067 | * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. |
AnnaBridge | 165:d1b4690b3f8b | 1068 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1069 | * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1070 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1071 | * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), |
AnnaBridge | 165:d1b4690b3f8b | 1072 | * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). |
AnnaBridge | 165:d1b4690b3f8b | 1073 | * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1074 | * @retval SET / RESET |
AnnaBridge | 165:d1b4690b3f8b | 1075 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1076 | #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
AnnaBridge | 165:d1b4690b3f8b | 1077 | |
AnnaBridge | 165:d1b4690b3f8b | 1078 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1079 | |
AnnaBridge | 165:d1b4690b3f8b | 1080 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1081 | * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. |
AnnaBridge | 165:d1b4690b3f8b | 1082 | * |
AnnaBridge | 165:d1b4690b3f8b | 1083 | * @note This function must be used only when the PLLSAI2 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1084 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1085 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1086 | * |
AnnaBridge | 165:d1b4690b3f8b | 1087 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1088 | * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. |
AnnaBridge | 165:d1b4690b3f8b | 1089 | * This parameter must be a number between Min_Data = 1 and Max_Data = 16. |
AnnaBridge | 165:d1b4690b3f8b | 1090 | * |
AnnaBridge | 165:d1b4690b3f8b | 1091 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1092 | * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. |
AnnaBridge | 165:d1b4690b3f8b | 1093 | * This parameter must be a number between 8 and 86. |
AnnaBridge | 165:d1b4690b3f8b | 1094 | * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO |
AnnaBridge | 165:d1b4690b3f8b | 1095 | * output frequency is between 64 and 344 MHz. |
AnnaBridge | 165:d1b4690b3f8b | 1096 | * |
AnnaBridge | 165:d1b4690b3f8b | 1097 | * @param __PLLSAI2P__ specifies the division factor for SAI clock. |
AnnaBridge | 165:d1b4690b3f8b | 1098 | * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx |
AnnaBridge | 165:d1b4690b3f8b | 1099 | * else (2 to 31). |
AnnaBridge | 165:d1b4690b3f8b | 1100 | * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P |
AnnaBridge | 165:d1b4690b3f8b | 1101 | * |
AnnaBridge | 165:d1b4690b3f8b | 1102 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1103 | * @param __PLLSAI2Q__ specifies the division factor for DSI clock. |
AnnaBridge | 165:d1b4690b3f8b | 1104 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 165:d1b4690b3f8b | 1105 | * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q |
AnnaBridge | 165:d1b4690b3f8b | 1106 | * |
AnnaBridge | 165:d1b4690b3f8b | 1107 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1108 | * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. |
AnnaBridge | 165:d1b4690b3f8b | 1109 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 165:d1b4690b3f8b | 1110 | * |
AnnaBridge | 165:d1b4690b3f8b | 1111 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1112 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1113 | |
AnnaBridge | 165:d1b4690b3f8b | 1114 | #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1115 | |
AnnaBridge | 165:d1b4690b3f8b | 1116 | # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1117 | |
AnnaBridge | 165:d1b4690b3f8b | 1118 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1119 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1120 | ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1121 | ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1122 | ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1123 | (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 1124 | |
AnnaBridge | 165:d1b4690b3f8b | 1125 | # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1126 | |
AnnaBridge | 165:d1b4690b3f8b | 1127 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1128 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1129 | ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1130 | ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1131 | (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 1132 | |
AnnaBridge | 165:d1b4690b3f8b | 1133 | # else |
AnnaBridge | 165:d1b4690b3f8b | 1134 | |
AnnaBridge | 165:d1b4690b3f8b | 1135 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1136 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1137 | (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1138 | ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1139 | (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 1140 | |
AnnaBridge | 165:d1b4690b3f8b | 1141 | # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 1142 | |
AnnaBridge | 165:d1b4690b3f8b | 1143 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1144 | |
AnnaBridge | 165:d1b4690b3f8b | 1145 | # if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1146 | |
AnnaBridge | 165:d1b4690b3f8b | 1147 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1148 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1149 | ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1150 | ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1151 | ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 1152 | |
AnnaBridge | 165:d1b4690b3f8b | 1153 | # elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1154 | |
AnnaBridge | 165:d1b4690b3f8b | 1155 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1156 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1157 | ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1158 | ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 1159 | |
AnnaBridge | 165:d1b4690b3f8b | 1160 | # else |
AnnaBridge | 165:d1b4690b3f8b | 1161 | |
AnnaBridge | 165:d1b4690b3f8b | 1162 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1163 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1164 | (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ |
AnnaBridge | 165:d1b4690b3f8b | 1165 | ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) |
AnnaBridge | 165:d1b4690b3f8b | 1166 | |
AnnaBridge | 165:d1b4690b3f8b | 1167 | # endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 1168 | |
AnnaBridge | 165:d1b4690b3f8b | 1169 | #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 1170 | |
AnnaBridge | 165:d1b4690b3f8b | 1171 | |
AnnaBridge | 165:d1b4690b3f8b | 1172 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1173 | * @brief Macro to configure the PLLSAI2 clock multiplication factor N. |
AnnaBridge | 165:d1b4690b3f8b | 1174 | * |
AnnaBridge | 165:d1b4690b3f8b | 1175 | * @note This function must be used only when the PLLSAI2 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1176 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1177 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1178 | * |
AnnaBridge | 165:d1b4690b3f8b | 1179 | * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. |
AnnaBridge | 165:d1b4690b3f8b | 1180 | * This parameter must be a number between 8 and 86. |
AnnaBridge | 165:d1b4690b3f8b | 1181 | * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO |
AnnaBridge | 165:d1b4690b3f8b | 1182 | * output frequency is between 64 and 344 MHz. |
AnnaBridge | 165:d1b4690b3f8b | 1183 | * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N |
AnnaBridge | 165:d1b4690b3f8b | 1184 | * |
AnnaBridge | 165:d1b4690b3f8b | 1185 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1186 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1187 | #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1188 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1189 | |
AnnaBridge | 165:d1b4690b3f8b | 1190 | #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1191 | |
AnnaBridge | 165:d1b4690b3f8b | 1192 | /** @brief Macro to configure the PLLSAI2 input clock division factor M. |
AnnaBridge | 165:d1b4690b3f8b | 1193 | * |
AnnaBridge | 165:d1b4690b3f8b | 1194 | * @note This function must be used only when the PLLSAI2 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1195 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1196 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1197 | * |
AnnaBridge | 165:d1b4690b3f8b | 1198 | * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. |
AnnaBridge | 165:d1b4690b3f8b | 1199 | * This parameter must be a number between Min_Data = 1 and Max_Data = 16. |
AnnaBridge | 165:d1b4690b3f8b | 1200 | * |
AnnaBridge | 165:d1b4690b3f8b | 1201 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1202 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1203 | |
AnnaBridge | 165:d1b4690b3f8b | 1204 | #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1205 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1206 | |
AnnaBridge | 165:d1b4690b3f8b | 1207 | #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 1208 | |
AnnaBridge | 165:d1b4690b3f8b | 1209 | /** @brief Macro to configure the PLLSAI2 clock division factor P. |
AnnaBridge | 165:d1b4690b3f8b | 1210 | * |
AnnaBridge | 165:d1b4690b3f8b | 1211 | * @note This function must be used only when the PLLSAI2 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1212 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1213 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1214 | * |
AnnaBridge | 165:d1b4690b3f8b | 1215 | * @param __PLLSAI2P__ specifies the division factor. |
AnnaBridge | 165:d1b4690b3f8b | 1216 | * This parameter must be a number in the range (7 or 17). |
AnnaBridge | 165:d1b4690b3f8b | 1217 | * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ |
AnnaBridge | 165:d1b4690b3f8b | 1218 | * |
AnnaBridge | 165:d1b4690b3f8b | 1219 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1220 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1221 | #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1222 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1223 | |
AnnaBridge | 165:d1b4690b3f8b | 1224 | #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 1225 | |
AnnaBridge | 165:d1b4690b3f8b | 1226 | /** @brief Macro to configure the PLLSAI2 clock division factor Q. |
AnnaBridge | 165:d1b4690b3f8b | 1227 | * |
AnnaBridge | 165:d1b4690b3f8b | 1228 | * @note This function must be used only when the PLLSAI2 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1229 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1230 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1231 | * |
AnnaBridge | 165:d1b4690b3f8b | 1232 | * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 1233 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 165:d1b4690b3f8b | 1234 | * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q |
AnnaBridge | 165:d1b4690b3f8b | 1235 | * |
AnnaBridge | 165:d1b4690b3f8b | 1236 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1237 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1238 | #define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1239 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1240 | |
AnnaBridge | 165:d1b4690b3f8b | 1241 | #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 1242 | |
AnnaBridge | 165:d1b4690b3f8b | 1243 | /** @brief Macro to configure the PLLSAI2 clock division factor R. |
AnnaBridge | 165:d1b4690b3f8b | 1244 | * |
AnnaBridge | 165:d1b4690b3f8b | 1245 | * @note This function must be used only when the PLLSAI2 is disabled. |
AnnaBridge | 165:d1b4690b3f8b | 1246 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
AnnaBridge | 165:d1b4690b3f8b | 1247 | * __HAL_RCC_PLL_CONFIG() macro) |
AnnaBridge | 165:d1b4690b3f8b | 1248 | * |
AnnaBridge | 165:d1b4690b3f8b | 1249 | * @param __PLLSAI2R__ specifies the division factor. |
AnnaBridge | 165:d1b4690b3f8b | 1250 | * This parameter must be in the range (2, 4, 6 or 8). |
AnnaBridge | 165:d1b4690b3f8b | 1251 | * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__ |
AnnaBridge | 165:d1b4690b3f8b | 1252 | * |
AnnaBridge | 165:d1b4690b3f8b | 1253 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1254 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1255 | #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1256 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
AnnaBridge | 165:d1b4690b3f8b | 1257 | |
AnnaBridge | 165:d1b4690b3f8b | 1258 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1259 | * @brief Macros to enable or disable the PLLSAI2. |
AnnaBridge | 165:d1b4690b3f8b | 1260 | * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. |
AnnaBridge | 165:d1b4690b3f8b | 1261 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1262 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1263 | |
AnnaBridge | 165:d1b4690b3f8b | 1264 | #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) |
AnnaBridge | 165:d1b4690b3f8b | 1265 | |
AnnaBridge | 165:d1b4690b3f8b | 1266 | #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) |
AnnaBridge | 165:d1b4690b3f8b | 1267 | |
AnnaBridge | 165:d1b4690b3f8b | 1268 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1269 | * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). |
AnnaBridge | 165:d1b4690b3f8b | 1270 | * @note Enabling and disabling those clocks can be done without the need to stop the PLL. |
AnnaBridge | 165:d1b4690b3f8b | 1271 | * This is mainly used to save Power. |
AnnaBridge | 165:d1b4690b3f8b | 1272 | * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. |
AnnaBridge | 165:d1b4690b3f8b | 1273 | * This parameter can be one or a combination of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1274 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1275 | * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1276 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1277 | * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1278 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1279 | @if STM32L4A6xx |
AnnaBridge | 165:d1b4690b3f8b | 1280 | * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1281 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1282 | * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1283 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1284 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1285 | * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1286 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1287 | * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1288 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1289 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1290 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1291 | |
AnnaBridge | 165:d1b4690b3f8b | 1292 | #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
AnnaBridge | 165:d1b4690b3f8b | 1293 | |
AnnaBridge | 165:d1b4690b3f8b | 1294 | #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
AnnaBridge | 165:d1b4690b3f8b | 1295 | |
AnnaBridge | 165:d1b4690b3f8b | 1296 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1297 | * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). |
AnnaBridge | 165:d1b4690b3f8b | 1298 | * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. |
AnnaBridge | 165:d1b4690b3f8b | 1299 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1300 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1301 | * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1302 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1303 | * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1304 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1305 | @if STM32L4A6xx |
AnnaBridge | 165:d1b4690b3f8b | 1306 | * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1307 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1308 | * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1309 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1310 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1311 | * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve |
AnnaBridge | 165:d1b4690b3f8b | 1312 | * high-quality audio performance on SAI interface in case. |
AnnaBridge | 165:d1b4690b3f8b | 1313 | * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. |
AnnaBridge | 165:d1b4690b3f8b | 1314 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1315 | * @retval SET / RESET |
AnnaBridge | 165:d1b4690b3f8b | 1316 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1317 | #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
AnnaBridge | 165:d1b4690b3f8b | 1318 | |
AnnaBridge | 165:d1b4690b3f8b | 1319 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 1320 | |
AnnaBridge | 165:d1b4690b3f8b | 1321 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1322 | * @brief Macro to configure the SAI1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1323 | * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived |
AnnaBridge | 165:d1b4690b3f8b | 1324 | * from the PLLSAI1, system PLL or external clock (through a dedicated pin). |
AnnaBridge | 165:d1b4690b3f8b | 1325 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1326 | * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1327 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1328 | * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 |
AnnaBridge | 165:d1b4690b3f8b | 1329 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1330 | * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1331 | * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) |
AnnaBridge | 165:d1b4690b3f8b | 1332 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1333 | * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 |
AnnaBridge | 165:d1b4690b3f8b | 1334 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1335 | * |
AnnaBridge | 165:d1b4690b3f8b | 1336 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1337 | * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. |
AnnaBridge | 165:d1b4690b3f8b | 1338 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1339 | * |
AnnaBridge | 165:d1b4690b3f8b | 1340 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1341 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1342 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 1343 | #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ |
AnnaBridge | 165:d1b4690b3f8b | 1344 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1345 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1346 | #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ |
AnnaBridge | 165:d1b4690b3f8b | 1347 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1348 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 1349 | |
AnnaBridge | 165:d1b4690b3f8b | 1350 | /** @brief Macro to get the SAI1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1351 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1352 | * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1353 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1354 | * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 |
AnnaBridge | 165:d1b4690b3f8b | 1355 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1356 | * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1357 | * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) |
AnnaBridge | 165:d1b4690b3f8b | 1358 | * |
AnnaBridge | 165:d1b4690b3f8b | 1359 | * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 |
AnnaBridge | 165:d1b4690b3f8b | 1360 | * clock source when PLLs are disabled for devices without PLLSAI2. |
AnnaBridge | 165:d1b4690b3f8b | 1361 | * |
AnnaBridge | 165:d1b4690b3f8b | 1362 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1363 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 1364 | #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1365 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1366 | #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1367 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 1368 | |
AnnaBridge | 165:d1b4690b3f8b | 1369 | #if defined(SAI2) |
AnnaBridge | 165:d1b4690b3f8b | 1370 | |
AnnaBridge | 165:d1b4690b3f8b | 1371 | /** |
AnnaBridge | 165:d1b4690b3f8b | 1372 | * @brief Macro to configure the SAI2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1373 | * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived |
AnnaBridge | 165:d1b4690b3f8b | 1374 | * from the PLLSAI2, system PLL or external clock (through a dedicated pin). |
AnnaBridge | 165:d1b4690b3f8b | 1375 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1376 | * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1377 | * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1378 | * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1379 | * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) |
AnnaBridge | 165:d1b4690b3f8b | 1380 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1381 | * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 |
AnnaBridge | 165:d1b4690b3f8b | 1382 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1383 | * |
AnnaBridge | 165:d1b4690b3f8b | 1384 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1385 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1386 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 1387 | #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ |
AnnaBridge | 165:d1b4690b3f8b | 1388 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1389 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1390 | #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ |
AnnaBridge | 165:d1b4690b3f8b | 1391 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1392 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 1393 | |
AnnaBridge | 165:d1b4690b3f8b | 1394 | /** @brief Macro to get the SAI2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1395 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1396 | * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1397 | * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1398 | * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) |
AnnaBridge | 165:d1b4690b3f8b | 1399 | * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) |
AnnaBridge | 165:d1b4690b3f8b | 1400 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1401 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 1402 | #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1403 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1404 | #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1405 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 1406 | |
AnnaBridge | 165:d1b4690b3f8b | 1407 | #endif /* SAI2 */ |
AnnaBridge | 165:d1b4690b3f8b | 1408 | |
AnnaBridge | 165:d1b4690b3f8b | 1409 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1410 | * |
AnnaBridge | 165:d1b4690b3f8b | 1411 | * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1412 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1413 | * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1414 | * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1415 | * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1416 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1417 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1418 | #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1419 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1420 | |
AnnaBridge | 165:d1b4690b3f8b | 1421 | /** @brief Macro to get the I2C1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1422 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1423 | * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1424 | * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1425 | * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1426 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1427 | #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1428 | |
AnnaBridge | 165:d1b4690b3f8b | 1429 | #if defined(I2C2) |
AnnaBridge | 165:d1b4690b3f8b | 1430 | |
AnnaBridge | 165:d1b4690b3f8b | 1431 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1432 | * |
AnnaBridge | 165:d1b4690b3f8b | 1433 | * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1434 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1435 | * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1436 | * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1437 | * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1438 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1439 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1440 | #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1441 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1442 | |
AnnaBridge | 165:d1b4690b3f8b | 1443 | /** @brief Macro to get the I2C2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1444 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1445 | * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1446 | * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1447 | * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1448 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1449 | #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1450 | |
AnnaBridge | 165:d1b4690b3f8b | 1451 | #endif /* I2C2 */ |
AnnaBridge | 165:d1b4690b3f8b | 1452 | |
AnnaBridge | 165:d1b4690b3f8b | 1453 | /** @brief Macro to configure the I2C3 clock (I2C3CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1454 | * |
AnnaBridge | 165:d1b4690b3f8b | 1455 | * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1456 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1457 | * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1458 | * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1459 | * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1460 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1461 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1462 | #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1463 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1464 | |
AnnaBridge | 165:d1b4690b3f8b | 1465 | /** @brief Macro to get the I2C3 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1466 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1467 | * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1468 | * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1469 | * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1470 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1471 | #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1472 | |
AnnaBridge | 165:d1b4690b3f8b | 1473 | #if defined(I2C4) |
AnnaBridge | 165:d1b4690b3f8b | 1474 | |
AnnaBridge | 165:d1b4690b3f8b | 1475 | /** @brief Macro to configure the I2C4 clock (I2C4CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1476 | * |
AnnaBridge | 165:d1b4690b3f8b | 1477 | * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1478 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1479 | * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1480 | * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1481 | * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1482 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1483 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1484 | #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1485 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1486 | |
AnnaBridge | 165:d1b4690b3f8b | 1487 | /** @brief Macro to get the I2C4 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1488 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1489 | * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1490 | * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1491 | * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1492 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1493 | #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1494 | |
AnnaBridge | 165:d1b4690b3f8b | 1495 | #endif /* I2C4 */ |
AnnaBridge | 165:d1b4690b3f8b | 1496 | |
AnnaBridge | 165:d1b4690b3f8b | 1497 | |
AnnaBridge | 165:d1b4690b3f8b | 1498 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1499 | * |
AnnaBridge | 165:d1b4690b3f8b | 1500 | * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1501 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1502 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1503 | * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1504 | * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1505 | * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1506 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1507 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1508 | #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1509 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1510 | |
AnnaBridge | 165:d1b4690b3f8b | 1511 | /** @brief Macro to get the USART1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1512 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1513 | * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1514 | * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1515 | * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1516 | * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1517 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1518 | #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1519 | |
AnnaBridge | 165:d1b4690b3f8b | 1520 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1521 | * |
AnnaBridge | 165:d1b4690b3f8b | 1522 | * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1523 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1524 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1525 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1526 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1527 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1528 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1529 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1530 | #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1531 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1532 | |
AnnaBridge | 165:d1b4690b3f8b | 1533 | /** @brief Macro to get the USART2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1534 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1535 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1536 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1537 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1538 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1539 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1540 | #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1541 | |
AnnaBridge | 165:d1b4690b3f8b | 1542 | #if defined(USART3) |
AnnaBridge | 165:d1b4690b3f8b | 1543 | |
AnnaBridge | 165:d1b4690b3f8b | 1544 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1545 | * |
AnnaBridge | 165:d1b4690b3f8b | 1546 | * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1547 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1548 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1549 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1550 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1551 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1552 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1553 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1554 | #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1555 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1556 | |
AnnaBridge | 165:d1b4690b3f8b | 1557 | /** @brief Macro to get the USART3 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1558 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1559 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1560 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1561 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1562 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
AnnaBridge | 165:d1b4690b3f8b | 1563 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1564 | #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1565 | |
AnnaBridge | 165:d1b4690b3f8b | 1566 | #endif /* USART3 */ |
AnnaBridge | 165:d1b4690b3f8b | 1567 | |
AnnaBridge | 165:d1b4690b3f8b | 1568 | #if defined(UART4) |
AnnaBridge | 165:d1b4690b3f8b | 1569 | |
AnnaBridge | 165:d1b4690b3f8b | 1570 | /** @brief Macro to configure the UART4 clock (UART4CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1571 | * |
AnnaBridge | 165:d1b4690b3f8b | 1572 | * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1573 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1574 | * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1575 | * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1576 | * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1577 | * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1578 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1579 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1580 | #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1581 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1582 | |
AnnaBridge | 165:d1b4690b3f8b | 1583 | /** @brief Macro to get the UART4 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1584 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1585 | * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1586 | * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1587 | * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1588 | * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock |
AnnaBridge | 165:d1b4690b3f8b | 1589 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1590 | #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1591 | |
AnnaBridge | 165:d1b4690b3f8b | 1592 | #endif /* UART4 */ |
AnnaBridge | 165:d1b4690b3f8b | 1593 | |
AnnaBridge | 165:d1b4690b3f8b | 1594 | #if defined(UART5) |
AnnaBridge | 165:d1b4690b3f8b | 1595 | |
AnnaBridge | 165:d1b4690b3f8b | 1596 | /** @brief Macro to configure the UART5 clock (UART5CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1597 | * |
AnnaBridge | 165:d1b4690b3f8b | 1598 | * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1599 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1600 | * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1601 | * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1602 | * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1603 | * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1604 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1605 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1606 | #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1607 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1608 | |
AnnaBridge | 165:d1b4690b3f8b | 1609 | /** @brief Macro to get the UART5 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1610 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1611 | * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1612 | * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1613 | * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1614 | * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock |
AnnaBridge | 165:d1b4690b3f8b | 1615 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1616 | #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1617 | |
AnnaBridge | 165:d1b4690b3f8b | 1618 | #endif /* UART5 */ |
AnnaBridge | 165:d1b4690b3f8b | 1619 | |
AnnaBridge | 165:d1b4690b3f8b | 1620 | /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1621 | * |
AnnaBridge | 165:d1b4690b3f8b | 1622 | * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1623 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1624 | * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1625 | * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1626 | * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1627 | * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1628 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1629 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1630 | #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1631 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1632 | |
AnnaBridge | 165:d1b4690b3f8b | 1633 | /** @brief Macro to get the LPUART1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1634 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1635 | * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1636 | * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1637 | * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1638 | * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1639 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1640 | #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1641 | |
AnnaBridge | 165:d1b4690b3f8b | 1642 | /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1643 | * |
AnnaBridge | 165:d1b4690b3f8b | 1644 | * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1645 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1646 | * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1647 | * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1648 | * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1649 | * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1650 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1651 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1652 | #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1653 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1654 | |
AnnaBridge | 165:d1b4690b3f8b | 1655 | /** @brief Macro to get the LPTIM1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1656 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1657 | * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1658 | * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1659 | * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1660 | * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1661 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1662 | #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1663 | |
AnnaBridge | 165:d1b4690b3f8b | 1664 | /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). |
AnnaBridge | 165:d1b4690b3f8b | 1665 | * |
AnnaBridge | 165:d1b4690b3f8b | 1666 | * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1667 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1668 | * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1669 | * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1670 | * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1671 | * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock |
AnnaBridge | 165:d1b4690b3f8b | 1672 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1673 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1674 | #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1675 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1676 | |
AnnaBridge | 165:d1b4690b3f8b | 1677 | /** @brief Macro to get the LPTIM2 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1678 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1679 | * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1680 | * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1681 | * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1682 | * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1683 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1684 | #define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1685 | |
AnnaBridge | 165:d1b4690b3f8b | 1686 | #if defined(SDMMC1) |
AnnaBridge | 165:d1b4690b3f8b | 1687 | |
AnnaBridge | 165:d1b4690b3f8b | 1688 | /** @brief Macro to configure the SDMMC1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 1689 | * |
AnnaBridge | 165:d1b4690b3f8b | 1690 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1691 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1692 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1693 | * |
AnnaBridge | 165:d1b4690b3f8b | 1694 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1695 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1696 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1697 | * |
AnnaBridge | 165:d1b4690b3f8b | 1698 | * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1699 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1700 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1701 | * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1702 | * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1703 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1704 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1705 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1706 | * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1707 | * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1708 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1709 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1710 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1711 | * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1712 | * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1713 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1714 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1715 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1716 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1717 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1718 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1719 | #if defined(RCC_CCIPR2_SDMMCSEL) |
AnnaBridge | 165:d1b4690b3f8b | 1720 | #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1721 | do \ |
AnnaBridge | 165:d1b4690b3f8b | 1722 | { \ |
AnnaBridge | 165:d1b4690b3f8b | 1723 | if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ |
AnnaBridge | 165:d1b4690b3f8b | 1724 | { \ |
AnnaBridge | 165:d1b4690b3f8b | 1725 | SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ |
AnnaBridge | 165:d1b4690b3f8b | 1726 | } \ |
AnnaBridge | 165:d1b4690b3f8b | 1727 | else \ |
AnnaBridge | 165:d1b4690b3f8b | 1728 | { \ |
AnnaBridge | 165:d1b4690b3f8b | 1729 | CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ |
AnnaBridge | 165:d1b4690b3f8b | 1730 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ |
AnnaBridge | 165:d1b4690b3f8b | 1731 | } \ |
AnnaBridge | 165:d1b4690b3f8b | 1732 | } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 1733 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1734 | #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1735 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1736 | #endif /* RCC_CCIPR2_SDMMCSEL */ |
AnnaBridge | 165:d1b4690b3f8b | 1737 | |
AnnaBridge | 165:d1b4690b3f8b | 1738 | /** @brief Macro to get the SDMMC1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 1739 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1740 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1741 | * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1742 | * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1743 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1744 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1745 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1746 | * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1747 | * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1748 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1749 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1750 | @if STM32L4S9xx |
AnnaBridge | 165:d1b4690b3f8b | 1751 | * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1752 | * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1753 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1754 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock |
AnnaBridge | 165:d1b4690b3f8b | 1755 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1756 | * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1757 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1758 | #if defined(RCC_CCIPR2_SDMMCSEL) |
AnnaBridge | 165:d1b4690b3f8b | 1759 | #define __HAL_RCC_GET_SDMMC1_SOURCE() \ |
AnnaBridge | 165:d1b4690b3f8b | 1760 | ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) |
AnnaBridge | 165:d1b4690b3f8b | 1761 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1762 | #define __HAL_RCC_GET_SDMMC1_SOURCE() \ |
AnnaBridge | 165:d1b4690b3f8b | 1763 | (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1764 | #endif /* RCC_CCIPR2_SDMMCSEL */ |
AnnaBridge | 165:d1b4690b3f8b | 1765 | |
AnnaBridge | 165:d1b4690b3f8b | 1766 | #endif /* SDMMC1 */ |
AnnaBridge | 165:d1b4690b3f8b | 1767 | |
AnnaBridge | 165:d1b4690b3f8b | 1768 | /** @brief Macro to configure the RNG clock. |
AnnaBridge | 165:d1b4690b3f8b | 1769 | * |
AnnaBridge | 165:d1b4690b3f8b | 1770 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1771 | * |
AnnaBridge | 165:d1b4690b3f8b | 1772 | * @param __RNG_CLKSOURCE__ specifies the RNG clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1773 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1774 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1775 | * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1776 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1777 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1778 | * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1779 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1780 | * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock |
AnnaBridge | 165:d1b4690b3f8b | 1781 | * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock |
AnnaBridge | 165:d1b4690b3f8b | 1782 | * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock |
AnnaBridge | 165:d1b4690b3f8b | 1783 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1784 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1785 | #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1786 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1787 | |
AnnaBridge | 165:d1b4690b3f8b | 1788 | /** @brief Macro to get the RNG clock. |
AnnaBridge | 165:d1b4690b3f8b | 1789 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1790 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1791 | * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1792 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1793 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1794 | * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1795 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1796 | * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock |
AnnaBridge | 165:d1b4690b3f8b | 1797 | * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock |
AnnaBridge | 165:d1b4690b3f8b | 1798 | * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock |
AnnaBridge | 165:d1b4690b3f8b | 1799 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1800 | #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1801 | |
AnnaBridge | 165:d1b4690b3f8b | 1802 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 165:d1b4690b3f8b | 1803 | |
AnnaBridge | 165:d1b4690b3f8b | 1804 | /** @brief Macro to configure the USB clock (USBCLK). |
AnnaBridge | 165:d1b4690b3f8b | 1805 | * |
AnnaBridge | 165:d1b4690b3f8b | 1806 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1807 | * |
AnnaBridge | 165:d1b4690b3f8b | 1808 | * @param __USB_CLKSOURCE__ specifies the USB clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1809 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1810 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1811 | * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1812 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1813 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1814 | * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1815 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1816 | * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock |
AnnaBridge | 165:d1b4690b3f8b | 1817 | * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock |
AnnaBridge | 165:d1b4690b3f8b | 1818 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock |
AnnaBridge | 165:d1b4690b3f8b | 1819 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1820 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1821 | #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1822 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1823 | |
AnnaBridge | 165:d1b4690b3f8b | 1824 | /** @brief Macro to get the USB clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1825 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1826 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1827 | * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1828 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1829 | @if STM32L443xx |
AnnaBridge | 165:d1b4690b3f8b | 1830 | * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 |
AnnaBridge | 165:d1b4690b3f8b | 1831 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1832 | * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock |
AnnaBridge | 165:d1b4690b3f8b | 1833 | * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock |
AnnaBridge | 165:d1b4690b3f8b | 1834 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock |
AnnaBridge | 165:d1b4690b3f8b | 1835 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1836 | #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1837 | |
AnnaBridge | 165:d1b4690b3f8b | 1838 | #endif /* USB_OTG_FS || USB */ |
AnnaBridge | 165:d1b4690b3f8b | 1839 | |
AnnaBridge | 165:d1b4690b3f8b | 1840 | /** @brief Macro to configure the ADC interface clock. |
AnnaBridge | 165:d1b4690b3f8b | 1841 | * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1842 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1843 | * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock |
AnnaBridge | 165:d1b4690b3f8b | 1844 | * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock |
AnnaBridge | 165:d1b4690b3f8b | 1845 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1846 | * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices |
AnnaBridge | 165:d1b4690b3f8b | 1847 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1848 | * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock |
AnnaBridge | 165:d1b4690b3f8b | 1849 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1850 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1851 | #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1852 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1853 | |
AnnaBridge | 165:d1b4690b3f8b | 1854 | /** @brief Macro to get the ADC clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1855 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1856 | * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock |
AnnaBridge | 165:d1b4690b3f8b | 1857 | * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock |
AnnaBridge | 165:d1b4690b3f8b | 1858 | @if STM32L486xx |
AnnaBridge | 165:d1b4690b3f8b | 1859 | * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices |
AnnaBridge | 165:d1b4690b3f8b | 1860 | @endif |
AnnaBridge | 165:d1b4690b3f8b | 1861 | * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock |
AnnaBridge | 165:d1b4690b3f8b | 1862 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1863 | #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1864 | |
AnnaBridge | 165:d1b4690b3f8b | 1865 | #if defined(SWPMI1) |
AnnaBridge | 165:d1b4690b3f8b | 1866 | |
AnnaBridge | 165:d1b4690b3f8b | 1867 | /** @brief Macro to configure the SWPMI1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 1868 | * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1869 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1870 | * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1871 | * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1872 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1873 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1874 | #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1875 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1876 | |
AnnaBridge | 165:d1b4690b3f8b | 1877 | /** @brief Macro to get the SWPMI1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1878 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1879 | * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1880 | * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1881 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1882 | #define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1883 | |
AnnaBridge | 165:d1b4690b3f8b | 1884 | #endif /* SWPMI1 */ |
AnnaBridge | 165:d1b4690b3f8b | 1885 | |
AnnaBridge | 165:d1b4690b3f8b | 1886 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 165:d1b4690b3f8b | 1887 | /** @brief Macro to configure the DFSDM1 clock. |
AnnaBridge | 165:d1b4690b3f8b | 1888 | * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1889 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1890 | * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1891 | * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1892 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1893 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1894 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 1895 | #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1896 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1897 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1898 | #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1899 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1900 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 1901 | |
AnnaBridge | 165:d1b4690b3f8b | 1902 | /** @brief Macro to get the DFSDM1 clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1903 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1904 | * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1905 | * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock |
AnnaBridge | 165:d1b4690b3f8b | 1906 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1907 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 1908 | #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1909 | #else |
AnnaBridge | 165:d1b4690b3f8b | 1910 | #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1911 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 1912 | |
AnnaBridge | 165:d1b4690b3f8b | 1913 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 1914 | |
AnnaBridge | 165:d1b4690b3f8b | 1915 | /** @brief Macro to configure the DFSDM1 audio clock. |
AnnaBridge | 165:d1b4690b3f8b | 1916 | * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1917 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1918 | * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock |
AnnaBridge | 165:d1b4690b3f8b | 1919 | * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock |
AnnaBridge | 165:d1b4690b3f8b | 1920 | * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock |
AnnaBridge | 165:d1b4690b3f8b | 1921 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1922 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1923 | #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1924 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1925 | |
AnnaBridge | 165:d1b4690b3f8b | 1926 | /** @brief Macro to get the DFSDM1 audio clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1927 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1928 | * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock |
AnnaBridge | 165:d1b4690b3f8b | 1929 | * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock |
AnnaBridge | 165:d1b4690b3f8b | 1930 | * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock |
AnnaBridge | 165:d1b4690b3f8b | 1931 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1932 | #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1933 | |
AnnaBridge | 165:d1b4690b3f8b | 1934 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 1935 | |
AnnaBridge | 165:d1b4690b3f8b | 1936 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 165:d1b4690b3f8b | 1937 | |
AnnaBridge | 165:d1b4690b3f8b | 1938 | #if defined(LTDC) |
AnnaBridge | 165:d1b4690b3f8b | 1939 | |
AnnaBridge | 165:d1b4690b3f8b | 1940 | /** @brief Macro to configure the LTDC clock. |
AnnaBridge | 165:d1b4690b3f8b | 1941 | * @param __LTDC_CLKSOURCE__ specifies the DSI clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1942 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1943 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1944 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1945 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1946 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1947 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1948 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1949 | #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1950 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1951 | |
AnnaBridge | 165:d1b4690b3f8b | 1952 | /** @brief Macro to get the LTDC clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1953 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1954 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1955 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1956 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1957 | * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock |
AnnaBridge | 165:d1b4690b3f8b | 1958 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1959 | #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) |
AnnaBridge | 165:d1b4690b3f8b | 1960 | |
AnnaBridge | 165:d1b4690b3f8b | 1961 | #endif /* LTDC */ |
AnnaBridge | 165:d1b4690b3f8b | 1962 | |
AnnaBridge | 165:d1b4690b3f8b | 1963 | #if defined(DSI) |
AnnaBridge | 165:d1b4690b3f8b | 1964 | |
AnnaBridge | 165:d1b4690b3f8b | 1965 | /** @brief Macro to configure the DSI clock. |
AnnaBridge | 165:d1b4690b3f8b | 1966 | * @param __DSI_CLKSOURCE__ specifies the DSI clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1967 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1968 | * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock |
AnnaBridge | 165:d1b4690b3f8b | 1969 | * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock |
AnnaBridge | 165:d1b4690b3f8b | 1970 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1971 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1972 | #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1973 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1974 | |
AnnaBridge | 165:d1b4690b3f8b | 1975 | /** @brief Macro to get the DSI clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1976 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1977 | * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock |
AnnaBridge | 165:d1b4690b3f8b | 1978 | * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock |
AnnaBridge | 165:d1b4690b3f8b | 1979 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1980 | #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) |
AnnaBridge | 165:d1b4690b3f8b | 1981 | |
AnnaBridge | 165:d1b4690b3f8b | 1982 | #endif /* DSI */ |
AnnaBridge | 165:d1b4690b3f8b | 1983 | |
AnnaBridge | 165:d1b4690b3f8b | 1984 | #if defined(OCTOSPI1) || defined(OCTOSPI2) |
AnnaBridge | 165:d1b4690b3f8b | 1985 | |
AnnaBridge | 165:d1b4690b3f8b | 1986 | /** @brief Macro to configure the OctoSPI clock. |
AnnaBridge | 165:d1b4690b3f8b | 1987 | * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1988 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1989 | * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock |
AnnaBridge | 165:d1b4690b3f8b | 1990 | * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock |
AnnaBridge | 165:d1b4690b3f8b | 1991 | * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock |
AnnaBridge | 165:d1b4690b3f8b | 1992 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 1993 | */ |
AnnaBridge | 165:d1b4690b3f8b | 1994 | #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 1995 | MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) |
AnnaBridge | 165:d1b4690b3f8b | 1996 | |
AnnaBridge | 165:d1b4690b3f8b | 1997 | /** @brief Macro to get the OctoSPI clock source. |
AnnaBridge | 165:d1b4690b3f8b | 1998 | * @retval The clock source can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 1999 | * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock |
AnnaBridge | 165:d1b4690b3f8b | 2000 | * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock |
AnnaBridge | 165:d1b4690b3f8b | 2001 | * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock |
AnnaBridge | 165:d1b4690b3f8b | 2002 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2003 | #define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) |
AnnaBridge | 165:d1b4690b3f8b | 2004 | |
AnnaBridge | 165:d1b4690b3f8b | 2005 | #endif /* OCTOSPI1 || OCTOSPI2 */ |
AnnaBridge | 165:d1b4690b3f8b | 2006 | |
AnnaBridge | 165:d1b4690b3f8b | 2007 | /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management |
AnnaBridge | 165:d1b4690b3f8b | 2008 | * @brief macros to manage the specified RCC Flags and interrupts. |
AnnaBridge | 165:d1b4690b3f8b | 2009 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2010 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2011 | |
AnnaBridge | 165:d1b4690b3f8b | 2012 | /** @brief Enable PLLSAI1RDY interrupt. |
AnnaBridge | 165:d1b4690b3f8b | 2013 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2014 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2015 | #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) |
AnnaBridge | 165:d1b4690b3f8b | 2016 | |
AnnaBridge | 165:d1b4690b3f8b | 2017 | /** @brief Disable PLLSAI1RDY interrupt. |
AnnaBridge | 165:d1b4690b3f8b | 2018 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2019 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2020 | #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) |
AnnaBridge | 165:d1b4690b3f8b | 2021 | |
AnnaBridge | 165:d1b4690b3f8b | 2022 | /** @brief Clear the PLLSAI1RDY interrupt pending bit. |
AnnaBridge | 165:d1b4690b3f8b | 2023 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2024 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2025 | #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) |
AnnaBridge | 165:d1b4690b3f8b | 2026 | |
AnnaBridge | 165:d1b4690b3f8b | 2027 | /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. |
AnnaBridge | 165:d1b4690b3f8b | 2028 | * @retval TRUE or FALSE. |
AnnaBridge | 165:d1b4690b3f8b | 2029 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2030 | #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) |
AnnaBridge | 165:d1b4690b3f8b | 2031 | |
AnnaBridge | 165:d1b4690b3f8b | 2032 | /** @brief Check whether the PLLSAI1RDY flag is set or not. |
AnnaBridge | 165:d1b4690b3f8b | 2033 | * @retval TRUE or FALSE. |
AnnaBridge | 165:d1b4690b3f8b | 2034 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2035 | #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) |
AnnaBridge | 165:d1b4690b3f8b | 2036 | |
AnnaBridge | 165:d1b4690b3f8b | 2037 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2038 | |
AnnaBridge | 165:d1b4690b3f8b | 2039 | /** @brief Enable PLLSAI2RDY interrupt. |
AnnaBridge | 165:d1b4690b3f8b | 2040 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2041 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2042 | #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) |
AnnaBridge | 165:d1b4690b3f8b | 2043 | |
AnnaBridge | 165:d1b4690b3f8b | 2044 | /** @brief Disable PLLSAI2RDY interrupt. |
AnnaBridge | 165:d1b4690b3f8b | 2045 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2046 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2047 | #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) |
AnnaBridge | 165:d1b4690b3f8b | 2048 | |
AnnaBridge | 165:d1b4690b3f8b | 2049 | /** @brief Clear the PLLSAI2RDY interrupt pending bit. |
AnnaBridge | 165:d1b4690b3f8b | 2050 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2051 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2052 | #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) |
AnnaBridge | 165:d1b4690b3f8b | 2053 | |
AnnaBridge | 165:d1b4690b3f8b | 2054 | /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. |
AnnaBridge | 165:d1b4690b3f8b | 2055 | * @retval TRUE or FALSE. |
AnnaBridge | 165:d1b4690b3f8b | 2056 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2057 | #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) |
AnnaBridge | 165:d1b4690b3f8b | 2058 | |
AnnaBridge | 165:d1b4690b3f8b | 2059 | /** @brief Check whether the PLLSAI2RDY flag is set or not. |
AnnaBridge | 165:d1b4690b3f8b | 2060 | * @retval TRUE or FALSE. |
AnnaBridge | 165:d1b4690b3f8b | 2061 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2062 | #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) |
AnnaBridge | 165:d1b4690b3f8b | 2063 | |
AnnaBridge | 165:d1b4690b3f8b | 2064 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2065 | |
AnnaBridge | 165:d1b4690b3f8b | 2066 | |
AnnaBridge | 165:d1b4690b3f8b | 2067 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2068 | * @brief Enable the RCC LSE CSS Extended Interrupt Line. |
AnnaBridge | 165:d1b4690b3f8b | 2069 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2070 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2071 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2072 | |
AnnaBridge | 165:d1b4690b3f8b | 2073 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2074 | * @brief Disable the RCC LSE CSS Extended Interrupt Line. |
AnnaBridge | 165:d1b4690b3f8b | 2075 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2076 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2077 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2078 | |
AnnaBridge | 165:d1b4690b3f8b | 2079 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2080 | * @brief Enable the RCC LSE CSS Event Line. |
AnnaBridge | 165:d1b4690b3f8b | 2081 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2082 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2083 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2084 | |
AnnaBridge | 165:d1b4690b3f8b | 2085 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2086 | * @brief Disable the RCC LSE CSS Event Line. |
AnnaBridge | 165:d1b4690b3f8b | 2087 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2088 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2089 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2090 | |
AnnaBridge | 165:d1b4690b3f8b | 2091 | |
AnnaBridge | 165:d1b4690b3f8b | 2092 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2093 | * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. |
AnnaBridge | 165:d1b4690b3f8b | 2094 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2095 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2096 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2097 | |
AnnaBridge | 165:d1b4690b3f8b | 2098 | |
AnnaBridge | 165:d1b4690b3f8b | 2099 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2100 | * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. |
AnnaBridge | 165:d1b4690b3f8b | 2101 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2102 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2103 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2104 | |
AnnaBridge | 165:d1b4690b3f8b | 2105 | |
AnnaBridge | 165:d1b4690b3f8b | 2106 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2107 | * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. |
AnnaBridge | 165:d1b4690b3f8b | 2108 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2109 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2110 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2111 | |
AnnaBridge | 165:d1b4690b3f8b | 2112 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2113 | * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. |
AnnaBridge | 165:d1b4690b3f8b | 2114 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2115 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2116 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2117 | |
AnnaBridge | 165:d1b4690b3f8b | 2118 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2119 | * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. |
AnnaBridge | 165:d1b4690b3f8b | 2120 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2121 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2122 | #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
AnnaBridge | 165:d1b4690b3f8b | 2123 | do { \ |
AnnaBridge | 165:d1b4690b3f8b | 2124 | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ |
AnnaBridge | 165:d1b4690b3f8b | 2125 | __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ |
AnnaBridge | 165:d1b4690b3f8b | 2126 | } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 2127 | |
AnnaBridge | 165:d1b4690b3f8b | 2128 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2129 | * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. |
AnnaBridge | 165:d1b4690b3f8b | 2130 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2131 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2132 | #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
AnnaBridge | 165:d1b4690b3f8b | 2133 | do { \ |
AnnaBridge | 165:d1b4690b3f8b | 2134 | __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ |
AnnaBridge | 165:d1b4690b3f8b | 2135 | __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ |
AnnaBridge | 165:d1b4690b3f8b | 2136 | } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 2137 | |
AnnaBridge | 165:d1b4690b3f8b | 2138 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2139 | * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. |
AnnaBridge | 165:d1b4690b3f8b | 2140 | * @retval EXTI RCC LSE CSS Line Status. |
AnnaBridge | 165:d1b4690b3f8b | 2141 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2142 | #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2143 | |
AnnaBridge | 165:d1b4690b3f8b | 2144 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2145 | * @brief Clear the RCC LSE CSS EXTI flag. |
AnnaBridge | 165:d1b4690b3f8b | 2146 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2147 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2148 | #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2149 | |
AnnaBridge | 165:d1b4690b3f8b | 2150 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2151 | * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. |
AnnaBridge | 165:d1b4690b3f8b | 2152 | * @retval None. |
AnnaBridge | 165:d1b4690b3f8b | 2153 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2154 | #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) |
AnnaBridge | 165:d1b4690b3f8b | 2155 | |
AnnaBridge | 165:d1b4690b3f8b | 2156 | |
AnnaBridge | 165:d1b4690b3f8b | 2157 | #if defined(CRS) |
AnnaBridge | 165:d1b4690b3f8b | 2158 | |
AnnaBridge | 165:d1b4690b3f8b | 2159 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2160 | * @brief Enable the specified CRS interrupts. |
AnnaBridge | 165:d1b4690b3f8b | 2161 | * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. |
AnnaBridge | 165:d1b4690b3f8b | 2162 | * This parameter can be any combination of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 2163 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2164 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2165 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2166 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2167 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2168 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2169 | #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) |
AnnaBridge | 165:d1b4690b3f8b | 2170 | |
AnnaBridge | 165:d1b4690b3f8b | 2171 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2172 | * @brief Disable the specified CRS interrupts. |
AnnaBridge | 165:d1b4690b3f8b | 2173 | * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. |
AnnaBridge | 165:d1b4690b3f8b | 2174 | * This parameter can be any combination of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 2175 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2176 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2177 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2178 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2179 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2180 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2181 | #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) |
AnnaBridge | 165:d1b4690b3f8b | 2182 | |
AnnaBridge | 165:d1b4690b3f8b | 2183 | /** @brief Check whether the CRS interrupt has occurred or not. |
AnnaBridge | 165:d1b4690b3f8b | 2184 | * @param __INTERRUPT__ specifies the CRS interrupt source to check. |
AnnaBridge | 165:d1b4690b3f8b | 2185 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 2186 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2187 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2188 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2189 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2190 | * @retval The new state of __INTERRUPT__ (SET or RESET). |
AnnaBridge | 165:d1b4690b3f8b | 2191 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2192 | #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) |
AnnaBridge | 165:d1b4690b3f8b | 2193 | |
AnnaBridge | 165:d1b4690b3f8b | 2194 | /** @brief Clear the CRS interrupt pending bits |
AnnaBridge | 165:d1b4690b3f8b | 2195 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
AnnaBridge | 165:d1b4690b3f8b | 2196 | * This parameter can be any combination of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 2197 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2198 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2199 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2200 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2201 | * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2202 | * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2203 | * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt |
AnnaBridge | 165:d1b4690b3f8b | 2204 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2205 | /* CRS IT Error Mask */ |
AnnaBridge | 165:d1b4690b3f8b | 2206 | #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) |
AnnaBridge | 165:d1b4690b3f8b | 2207 | |
AnnaBridge | 165:d1b4690b3f8b | 2208 | #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ |
AnnaBridge | 165:d1b4690b3f8b | 2209 | if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ |
AnnaBridge | 165:d1b4690b3f8b | 2210 | { \ |
AnnaBridge | 165:d1b4690b3f8b | 2211 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ |
AnnaBridge | 165:d1b4690b3f8b | 2212 | } \ |
AnnaBridge | 165:d1b4690b3f8b | 2213 | else \ |
AnnaBridge | 165:d1b4690b3f8b | 2214 | { \ |
AnnaBridge | 165:d1b4690b3f8b | 2215 | WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ |
AnnaBridge | 165:d1b4690b3f8b | 2216 | } \ |
AnnaBridge | 165:d1b4690b3f8b | 2217 | } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 2218 | |
AnnaBridge | 165:d1b4690b3f8b | 2219 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2220 | * @brief Check whether the specified CRS flag is set or not. |
AnnaBridge | 165:d1b4690b3f8b | 2221 | * @param __FLAG__ specifies the flag to check. |
AnnaBridge | 165:d1b4690b3f8b | 2222 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 2223 | * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK |
AnnaBridge | 165:d1b4690b3f8b | 2224 | * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning |
AnnaBridge | 165:d1b4690b3f8b | 2225 | * @arg @ref RCC_CRS_FLAG_ERR Error |
AnnaBridge | 165:d1b4690b3f8b | 2226 | * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC |
AnnaBridge | 165:d1b4690b3f8b | 2227 | * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow |
AnnaBridge | 165:d1b4690b3f8b | 2228 | * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error |
AnnaBridge | 165:d1b4690b3f8b | 2229 | * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed |
AnnaBridge | 165:d1b4690b3f8b | 2230 | * @retval The new state of _FLAG_ (TRUE or FALSE). |
AnnaBridge | 165:d1b4690b3f8b | 2231 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2232 | #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) |
AnnaBridge | 165:d1b4690b3f8b | 2233 | |
AnnaBridge | 165:d1b4690b3f8b | 2234 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2235 | * @brief Clear the CRS specified FLAG. |
AnnaBridge | 165:d1b4690b3f8b | 2236 | * @param __FLAG__ specifies the flag to clear. |
AnnaBridge | 165:d1b4690b3f8b | 2237 | * This parameter can be one of the following values: |
AnnaBridge | 165:d1b4690b3f8b | 2238 | * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK |
AnnaBridge | 165:d1b4690b3f8b | 2239 | * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning |
AnnaBridge | 165:d1b4690b3f8b | 2240 | * @arg @ref RCC_CRS_FLAG_ERR Error |
AnnaBridge | 165:d1b4690b3f8b | 2241 | * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC |
AnnaBridge | 165:d1b4690b3f8b | 2242 | * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow |
AnnaBridge | 165:d1b4690b3f8b | 2243 | * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error |
AnnaBridge | 165:d1b4690b3f8b | 2244 | * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed |
AnnaBridge | 165:d1b4690b3f8b | 2245 | * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR |
AnnaBridge | 165:d1b4690b3f8b | 2246 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2247 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2248 | |
AnnaBridge | 165:d1b4690b3f8b | 2249 | /* CRS Flag Error Mask */ |
AnnaBridge | 165:d1b4690b3f8b | 2250 | #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) |
AnnaBridge | 165:d1b4690b3f8b | 2251 | |
AnnaBridge | 165:d1b4690b3f8b | 2252 | #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ |
AnnaBridge | 165:d1b4690b3f8b | 2253 | if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ |
AnnaBridge | 165:d1b4690b3f8b | 2254 | { \ |
AnnaBridge | 165:d1b4690b3f8b | 2255 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ |
AnnaBridge | 165:d1b4690b3f8b | 2256 | } \ |
AnnaBridge | 165:d1b4690b3f8b | 2257 | else \ |
AnnaBridge | 165:d1b4690b3f8b | 2258 | { \ |
AnnaBridge | 165:d1b4690b3f8b | 2259 | WRITE_REG(CRS->ICR, (__FLAG__)); \ |
AnnaBridge | 165:d1b4690b3f8b | 2260 | } \ |
AnnaBridge | 165:d1b4690b3f8b | 2261 | } while(0) |
AnnaBridge | 165:d1b4690b3f8b | 2262 | |
AnnaBridge | 165:d1b4690b3f8b | 2263 | #endif /* CRS */ |
AnnaBridge | 165:d1b4690b3f8b | 2264 | |
AnnaBridge | 165:d1b4690b3f8b | 2265 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2266 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2267 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2268 | |
AnnaBridge | 165:d1b4690b3f8b | 2269 | #if defined(CRS) |
AnnaBridge | 165:d1b4690b3f8b | 2270 | |
AnnaBridge | 165:d1b4690b3f8b | 2271 | /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features |
AnnaBridge | 165:d1b4690b3f8b | 2272 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2273 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2274 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2275 | * @brief Enable the oscillator clock for frequency error counter. |
AnnaBridge | 165:d1b4690b3f8b | 2276 | * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. |
AnnaBridge | 165:d1b4690b3f8b | 2277 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2278 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2279 | #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) |
AnnaBridge | 165:d1b4690b3f8b | 2280 | |
AnnaBridge | 165:d1b4690b3f8b | 2281 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2282 | * @brief Disable the oscillator clock for frequency error counter. |
AnnaBridge | 165:d1b4690b3f8b | 2283 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2284 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2285 | #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) |
AnnaBridge | 165:d1b4690b3f8b | 2286 | |
AnnaBridge | 165:d1b4690b3f8b | 2287 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2288 | * @brief Enable the automatic hardware adjustement of TRIM bits. |
AnnaBridge | 165:d1b4690b3f8b | 2289 | * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. |
AnnaBridge | 165:d1b4690b3f8b | 2290 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2291 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2292 | #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
AnnaBridge | 165:d1b4690b3f8b | 2293 | |
AnnaBridge | 165:d1b4690b3f8b | 2294 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2295 | * @brief Enable or disable the automatic hardware adjustement of TRIM bits. |
AnnaBridge | 165:d1b4690b3f8b | 2296 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2297 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2298 | #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
AnnaBridge | 165:d1b4690b3f8b | 2299 | |
AnnaBridge | 165:d1b4690b3f8b | 2300 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2301 | * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies |
AnnaBridge | 165:d1b4690b3f8b | 2302 | * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency |
AnnaBridge | 165:d1b4690b3f8b | 2303 | * of the synchronization source after prescaling. It is then decreased by one in order to |
AnnaBridge | 165:d1b4690b3f8b | 2304 | * reach the expected synchronization on the zero value. The formula is the following: |
AnnaBridge | 165:d1b4690b3f8b | 2305 | * RELOAD = (fTARGET / fSYNC) -1 |
AnnaBridge | 165:d1b4690b3f8b | 2306 | * @param __FTARGET__ Target frequency (value in Hz) |
AnnaBridge | 165:d1b4690b3f8b | 2307 | * @param __FSYNC__ Synchronization signal frequency (value in Hz) |
AnnaBridge | 165:d1b4690b3f8b | 2308 | * @retval None |
AnnaBridge | 165:d1b4690b3f8b | 2309 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2310 | #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) |
AnnaBridge | 165:d1b4690b3f8b | 2311 | |
AnnaBridge | 165:d1b4690b3f8b | 2312 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2313 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2314 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2315 | |
AnnaBridge | 165:d1b4690b3f8b | 2316 | #endif /* CRS */ |
AnnaBridge | 165:d1b4690b3f8b | 2317 | |
AnnaBridge | 165:d1b4690b3f8b | 2318 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2319 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2320 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2321 | |
AnnaBridge | 165:d1b4690b3f8b | 2322 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 2323 | /** @addtogroup RCCEx_Exported_Functions |
AnnaBridge | 165:d1b4690b3f8b | 2324 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2325 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2326 | |
AnnaBridge | 165:d1b4690b3f8b | 2327 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
AnnaBridge | 165:d1b4690b3f8b | 2328 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2329 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2330 | |
AnnaBridge | 165:d1b4690b3f8b | 2331 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 165:d1b4690b3f8b | 2332 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
AnnaBridge | 165:d1b4690b3f8b | 2333 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
AnnaBridge | 165:d1b4690b3f8b | 2334 | |
AnnaBridge | 165:d1b4690b3f8b | 2335 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2336 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2337 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2338 | |
AnnaBridge | 165:d1b4690b3f8b | 2339 | /** @addtogroup RCCEx_Exported_Functions_Group2 |
AnnaBridge | 165:d1b4690b3f8b | 2340 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2341 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2342 | |
AnnaBridge | 165:d1b4690b3f8b | 2343 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); |
AnnaBridge | 165:d1b4690b3f8b | 2344 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); |
AnnaBridge | 165:d1b4690b3f8b | 2345 | |
AnnaBridge | 165:d1b4690b3f8b | 2346 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2347 | |
AnnaBridge | 165:d1b4690b3f8b | 2348 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); |
AnnaBridge | 165:d1b4690b3f8b | 2349 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); |
AnnaBridge | 165:d1b4690b3f8b | 2350 | |
AnnaBridge | 165:d1b4690b3f8b | 2351 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2352 | |
AnnaBridge | 165:d1b4690b3f8b | 2353 | void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); |
AnnaBridge | 165:d1b4690b3f8b | 2354 | void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); |
AnnaBridge | 165:d1b4690b3f8b | 2355 | void HAL_RCCEx_EnableLSECSS(void); |
AnnaBridge | 165:d1b4690b3f8b | 2356 | void HAL_RCCEx_DisableLSECSS(void); |
AnnaBridge | 165:d1b4690b3f8b | 2357 | void HAL_RCCEx_EnableLSECSS_IT(void); |
AnnaBridge | 165:d1b4690b3f8b | 2358 | void HAL_RCCEx_LSECSS_IRQHandler(void); |
AnnaBridge | 165:d1b4690b3f8b | 2359 | void HAL_RCCEx_LSECSS_Callback(void); |
AnnaBridge | 165:d1b4690b3f8b | 2360 | void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); |
AnnaBridge | 165:d1b4690b3f8b | 2361 | void HAL_RCCEx_DisableLSCO(void); |
AnnaBridge | 165:d1b4690b3f8b | 2362 | void HAL_RCCEx_EnableMSIPLLMode(void); |
AnnaBridge | 165:d1b4690b3f8b | 2363 | void HAL_RCCEx_DisableMSIPLLMode(void); |
AnnaBridge | 165:d1b4690b3f8b | 2364 | |
AnnaBridge | 165:d1b4690b3f8b | 2365 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2366 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2367 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2368 | |
AnnaBridge | 165:d1b4690b3f8b | 2369 | #if defined(CRS) |
AnnaBridge | 165:d1b4690b3f8b | 2370 | |
AnnaBridge | 165:d1b4690b3f8b | 2371 | /** @addtogroup RCCEx_Exported_Functions_Group3 |
AnnaBridge | 165:d1b4690b3f8b | 2372 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2373 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2374 | |
AnnaBridge | 165:d1b4690b3f8b | 2375 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); |
AnnaBridge | 165:d1b4690b3f8b | 2376 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); |
AnnaBridge | 165:d1b4690b3f8b | 2377 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); |
AnnaBridge | 165:d1b4690b3f8b | 2378 | uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); |
AnnaBridge | 165:d1b4690b3f8b | 2379 | void HAL_RCCEx_CRS_IRQHandler(void); |
AnnaBridge | 165:d1b4690b3f8b | 2380 | void HAL_RCCEx_CRS_SyncOkCallback(void); |
AnnaBridge | 165:d1b4690b3f8b | 2381 | void HAL_RCCEx_CRS_SyncWarnCallback(void); |
AnnaBridge | 165:d1b4690b3f8b | 2382 | void HAL_RCCEx_CRS_ExpectedSyncCallback(void); |
AnnaBridge | 165:d1b4690b3f8b | 2383 | void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); |
AnnaBridge | 165:d1b4690b3f8b | 2384 | |
AnnaBridge | 165:d1b4690b3f8b | 2385 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2386 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2387 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2388 | |
AnnaBridge | 165:d1b4690b3f8b | 2389 | #endif /* CRS */ |
AnnaBridge | 165:d1b4690b3f8b | 2390 | |
AnnaBridge | 165:d1b4690b3f8b | 2391 | /** |
AnnaBridge | 165:d1b4690b3f8b | 2392 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 2393 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2394 | |
AnnaBridge | 165:d1b4690b3f8b | 2395 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 165:d1b4690b3f8b | 2396 | /** @addtogroup RCCEx_Private_Macros |
AnnaBridge | 165:d1b4690b3f8b | 2397 | * @{ |
AnnaBridge | 165:d1b4690b3f8b | 2398 | */ |
AnnaBridge | 165:d1b4690b3f8b | 2399 | |
AnnaBridge | 165:d1b4690b3f8b | 2400 | #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2401 | ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) |
AnnaBridge | 165:d1b4690b3f8b | 2402 | |
AnnaBridge | 165:d1b4690b3f8b | 2403 | #if defined(STM32L431xx) |
AnnaBridge | 165:d1b4690b3f8b | 2404 | |
AnnaBridge | 165:d1b4690b3f8b | 2405 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2406 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2407 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2408 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2409 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2410 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2411 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2412 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2413 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2414 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2415 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2416 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2417 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2418 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2419 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2420 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
AnnaBridge | 165:d1b4690b3f8b | 2421 | |
AnnaBridge | 165:d1b4690b3f8b | 2422 | #elif defined(STM32L432xx) || defined(STM32L442xx) |
AnnaBridge | 165:d1b4690b3f8b | 2423 | |
AnnaBridge | 165:d1b4690b3f8b | 2424 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2425 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2426 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2427 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2428 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2429 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2430 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2431 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2432 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2433 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2434 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2435 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2436 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2437 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) |
AnnaBridge | 165:d1b4690b3f8b | 2438 | |
AnnaBridge | 165:d1b4690b3f8b | 2439 | #elif defined(STM32L433xx) || defined(STM32L443xx) |
AnnaBridge | 165:d1b4690b3f8b | 2440 | |
AnnaBridge | 165:d1b4690b3f8b | 2441 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2442 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2443 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2444 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2445 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2446 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2447 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2448 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2449 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2450 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2451 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2452 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2453 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2454 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2455 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2456 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2457 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
AnnaBridge | 165:d1b4690b3f8b | 2458 | |
AnnaBridge | 165:d1b4690b3f8b | 2459 | #elif defined(STM32L451xx) |
AnnaBridge | 165:d1b4690b3f8b | 2460 | |
AnnaBridge | 165:d1b4690b3f8b | 2461 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2462 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2463 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2464 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2465 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2466 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2467 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2468 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2469 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2470 | (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2471 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2472 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2473 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2474 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2475 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2476 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2477 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2478 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
AnnaBridge | 165:d1b4690b3f8b | 2479 | |
AnnaBridge | 165:d1b4690b3f8b | 2480 | #elif defined(STM32L452xx) || defined(STM32L462xx) |
AnnaBridge | 165:d1b4690b3f8b | 2481 | |
AnnaBridge | 165:d1b4690b3f8b | 2482 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2483 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2484 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2485 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2486 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2487 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2488 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2489 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2490 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2491 | (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2492 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2493 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2494 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2495 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2496 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2497 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2498 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2499 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2500 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
AnnaBridge | 165:d1b4690b3f8b | 2501 | |
AnnaBridge | 165:d1b4690b3f8b | 2502 | #elif defined(STM32L471xx) |
AnnaBridge | 165:d1b4690b3f8b | 2503 | |
AnnaBridge | 165:d1b4690b3f8b | 2504 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2505 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2506 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2507 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2508 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2509 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2510 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2511 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2512 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2513 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2514 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2515 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2516 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2517 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2518 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2519 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2520 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2521 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2522 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2523 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
AnnaBridge | 165:d1b4690b3f8b | 2524 | |
AnnaBridge | 165:d1b4690b3f8b | 2525 | #elif defined(STM32L496xx) || defined(STM32L4A6xx) |
AnnaBridge | 165:d1b4690b3f8b | 2526 | |
AnnaBridge | 165:d1b4690b3f8b | 2527 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2528 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2529 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2530 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2531 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2532 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2533 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2534 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2535 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2536 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2537 | (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2538 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2539 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2540 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2541 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2542 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2543 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2544 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2545 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2546 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2547 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2548 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
AnnaBridge | 165:d1b4690b3f8b | 2549 | |
AnnaBridge | 165:d1b4690b3f8b | 2550 | #elif defined(STM32L4R5xx) || defined(STM32L4S5xx) |
AnnaBridge | 165:d1b4690b3f8b | 2551 | |
AnnaBridge | 165:d1b4690b3f8b | 2552 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2553 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2554 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2555 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2556 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2557 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2558 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2559 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2560 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2561 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2562 | (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2563 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2564 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2565 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2566 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2567 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2568 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2569 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2570 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2571 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2572 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2573 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2574 | (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)) |
AnnaBridge | 165:d1b4690b3f8b | 2575 | |
AnnaBridge | 165:d1b4690b3f8b | 2576 | #elif defined(STM32L4R7xx) || defined(STM32L4S7xx) |
AnnaBridge | 165:d1b4690b3f8b | 2577 | |
AnnaBridge | 165:d1b4690b3f8b | 2578 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2579 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2580 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2581 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2582 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2583 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2584 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2585 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2586 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2587 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2588 | (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2589 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2590 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2591 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2592 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2593 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2594 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2595 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2596 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2597 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2598 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2599 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2600 | (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2601 | (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) |
AnnaBridge | 165:d1b4690b3f8b | 2602 | |
AnnaBridge | 165:d1b4690b3f8b | 2603 | #elif defined(STM32L4R9xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 2604 | |
AnnaBridge | 165:d1b4690b3f8b | 2605 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2606 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2607 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2608 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2609 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2610 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2611 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2612 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2613 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2614 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2615 | (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2616 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2617 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2618 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2619 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2620 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2621 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2622 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2623 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2624 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2625 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2626 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2627 | (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2628 | (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2629 | (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2630 | |
AnnaBridge | 165:d1b4690b3f8b | 2631 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2632 | |
AnnaBridge | 165:d1b4690b3f8b | 2633 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2634 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2635 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2636 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2637 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2638 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2639 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2640 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2641 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2642 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2643 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2644 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2645 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2646 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2647 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2648 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2649 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2650 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2651 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2652 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2653 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
AnnaBridge | 165:d1b4690b3f8b | 2654 | |
AnnaBridge | 165:d1b4690b3f8b | 2655 | #endif /* STM32L431xx */ |
AnnaBridge | 165:d1b4690b3f8b | 2656 | |
AnnaBridge | 165:d1b4690b3f8b | 2657 | #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2658 | (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2659 | ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2660 | ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2661 | ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2662 | |
AnnaBridge | 165:d1b4690b3f8b | 2663 | #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2664 | (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2665 | ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2666 | ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2667 | ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2668 | |
AnnaBridge | 165:d1b4690b3f8b | 2669 | #if defined(USART3) |
AnnaBridge | 165:d1b4690b3f8b | 2670 | |
AnnaBridge | 165:d1b4690b3f8b | 2671 | #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2672 | (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2673 | ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2674 | ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2675 | ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2676 | |
AnnaBridge | 165:d1b4690b3f8b | 2677 | #endif /* USART3 */ |
AnnaBridge | 165:d1b4690b3f8b | 2678 | |
AnnaBridge | 165:d1b4690b3f8b | 2679 | #if defined(UART4) |
AnnaBridge | 165:d1b4690b3f8b | 2680 | |
AnnaBridge | 165:d1b4690b3f8b | 2681 | #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2682 | (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2683 | ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2684 | ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2685 | ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2686 | |
AnnaBridge | 165:d1b4690b3f8b | 2687 | #endif /* UART4 */ |
AnnaBridge | 165:d1b4690b3f8b | 2688 | |
AnnaBridge | 165:d1b4690b3f8b | 2689 | #if defined(UART5) |
AnnaBridge | 165:d1b4690b3f8b | 2690 | |
AnnaBridge | 165:d1b4690b3f8b | 2691 | #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2692 | (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2693 | ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2694 | ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2695 | ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2696 | |
AnnaBridge | 165:d1b4690b3f8b | 2697 | #endif /* UART5 */ |
AnnaBridge | 165:d1b4690b3f8b | 2698 | |
AnnaBridge | 165:d1b4690b3f8b | 2699 | #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2700 | (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2701 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2702 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2703 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2704 | |
AnnaBridge | 165:d1b4690b3f8b | 2705 | #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2706 | (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2707 | ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 165:d1b4690b3f8b | 2708 | ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2709 | |
AnnaBridge | 165:d1b4690b3f8b | 2710 | #if defined(I2C2) |
AnnaBridge | 165:d1b4690b3f8b | 2711 | |
AnnaBridge | 165:d1b4690b3f8b | 2712 | #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2713 | (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2714 | ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 165:d1b4690b3f8b | 2715 | ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2716 | |
AnnaBridge | 165:d1b4690b3f8b | 2717 | #endif /* I2C2 */ |
AnnaBridge | 165:d1b4690b3f8b | 2718 | |
AnnaBridge | 165:d1b4690b3f8b | 2719 | #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2720 | (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2721 | ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 165:d1b4690b3f8b | 2722 | ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2723 | |
AnnaBridge | 165:d1b4690b3f8b | 2724 | #if defined(I2C4) |
AnnaBridge | 165:d1b4690b3f8b | 2725 | |
AnnaBridge | 165:d1b4690b3f8b | 2726 | #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2727 | (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2728 | ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ |
AnnaBridge | 165:d1b4690b3f8b | 2729 | ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2730 | |
AnnaBridge | 165:d1b4690b3f8b | 2731 | #endif /* I2C4 */ |
AnnaBridge | 165:d1b4690b3f8b | 2732 | |
AnnaBridge | 165:d1b4690b3f8b | 2733 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2734 | |
AnnaBridge | 165:d1b4690b3f8b | 2735 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 2736 | #define IS_RCC_SAI1CLK(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2737 | (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2738 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2739 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2740 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2741 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2742 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2743 | #define IS_RCC_SAI1CLK(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2744 | (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2745 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2746 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2747 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) |
AnnaBridge | 165:d1b4690b3f8b | 2748 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 2749 | |
AnnaBridge | 165:d1b4690b3f8b | 2750 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2751 | |
AnnaBridge | 165:d1b4690b3f8b | 2752 | #define IS_RCC_SAI1CLK(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2753 | (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2754 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2755 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) |
AnnaBridge | 165:d1b4690b3f8b | 2756 | |
AnnaBridge | 165:d1b4690b3f8b | 2757 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2758 | |
AnnaBridge | 165:d1b4690b3f8b | 2759 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2760 | |
AnnaBridge | 165:d1b4690b3f8b | 2761 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 2762 | #define IS_RCC_SAI2CLK(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2763 | (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2764 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2765 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2766 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2767 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2768 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2769 | #define IS_RCC_SAI2CLK(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2770 | (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2771 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2772 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2773 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) |
AnnaBridge | 165:d1b4690b3f8b | 2774 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 2775 | |
AnnaBridge | 165:d1b4690b3f8b | 2776 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2777 | |
AnnaBridge | 165:d1b4690b3f8b | 2778 | #define IS_RCC_LPTIM1CLK(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2779 | (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2780 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2781 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2782 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) |
AnnaBridge | 165:d1b4690b3f8b | 2783 | |
AnnaBridge | 165:d1b4690b3f8b | 2784 | #define IS_RCC_LPTIM2CLK(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2785 | (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2786 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2787 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2788 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) |
AnnaBridge | 165:d1b4690b3f8b | 2789 | |
AnnaBridge | 165:d1b4690b3f8b | 2790 | #if defined(SDMMC1) |
AnnaBridge | 165:d1b4690b3f8b | 2791 | #if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) |
AnnaBridge | 165:d1b4690b3f8b | 2792 | |
AnnaBridge | 165:d1b4690b3f8b | 2793 | #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2794 | (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2795 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2796 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2797 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2798 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2799 | |
AnnaBridge | 165:d1b4690b3f8b | 2800 | #elif defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2801 | |
AnnaBridge | 165:d1b4690b3f8b | 2802 | #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2803 | (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2804 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2805 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2806 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2807 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2808 | |
AnnaBridge | 165:d1b4690b3f8b | 2809 | #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2810 | (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2811 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2812 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2813 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2814 | |
AnnaBridge | 165:d1b4690b3f8b | 2815 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2816 | #endif /* SDMMC1 */ |
AnnaBridge | 165:d1b4690b3f8b | 2817 | |
AnnaBridge | 165:d1b4690b3f8b | 2818 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2819 | |
AnnaBridge | 165:d1b4690b3f8b | 2820 | #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2821 | (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2822 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2823 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2824 | ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2825 | |
AnnaBridge | 165:d1b4690b3f8b | 2826 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2827 | |
AnnaBridge | 165:d1b4690b3f8b | 2828 | #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2829 | (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2830 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2831 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2832 | ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2833 | |
AnnaBridge | 165:d1b4690b3f8b | 2834 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2835 | |
AnnaBridge | 165:d1b4690b3f8b | 2836 | #if defined(USB_OTG_FS) || defined(USB) |
AnnaBridge | 165:d1b4690b3f8b | 2837 | #if defined(RCC_HSI48_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2838 | |
AnnaBridge | 165:d1b4690b3f8b | 2839 | #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2840 | (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2841 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2842 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2843 | ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2844 | |
AnnaBridge | 165:d1b4690b3f8b | 2845 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2846 | |
AnnaBridge | 165:d1b4690b3f8b | 2847 | #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2848 | (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2849 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2850 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2851 | ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2852 | |
AnnaBridge | 165:d1b4690b3f8b | 2853 | #endif /* RCC_HSI48_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2854 | #endif /* USB_OTG_FS || USB */ |
AnnaBridge | 165:d1b4690b3f8b | 2855 | |
AnnaBridge | 165:d1b4690b3f8b | 2856 | #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) |
AnnaBridge | 165:d1b4690b3f8b | 2857 | |
AnnaBridge | 165:d1b4690b3f8b | 2858 | #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2859 | (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2860 | ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2861 | ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2862 | ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) |
AnnaBridge | 165:d1b4690b3f8b | 2863 | |
AnnaBridge | 165:d1b4690b3f8b | 2864 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2865 | |
AnnaBridge | 165:d1b4690b3f8b | 2866 | #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2867 | (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2868 | ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2869 | ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) |
AnnaBridge | 165:d1b4690b3f8b | 2870 | |
AnnaBridge | 165:d1b4690b3f8b | 2871 | #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ |
AnnaBridge | 165:d1b4690b3f8b | 2872 | |
AnnaBridge | 165:d1b4690b3f8b | 2873 | #if defined(SWPMI1) |
AnnaBridge | 165:d1b4690b3f8b | 2874 | |
AnnaBridge | 165:d1b4690b3f8b | 2875 | #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2876 | (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2877 | ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2878 | |
AnnaBridge | 165:d1b4690b3f8b | 2879 | #endif /* SWPMI1 */ |
AnnaBridge | 165:d1b4690b3f8b | 2880 | |
AnnaBridge | 165:d1b4690b3f8b | 2881 | #if defined(DFSDM1_Filter0) |
AnnaBridge | 165:d1b4690b3f8b | 2882 | |
AnnaBridge | 165:d1b4690b3f8b | 2883 | #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2884 | (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2885 | ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) |
AnnaBridge | 165:d1b4690b3f8b | 2886 | |
AnnaBridge | 165:d1b4690b3f8b | 2887 | #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) |
AnnaBridge | 165:d1b4690b3f8b | 2888 | |
AnnaBridge | 165:d1b4690b3f8b | 2889 | #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2890 | (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2891 | ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2892 | ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) |
AnnaBridge | 165:d1b4690b3f8b | 2893 | |
AnnaBridge | 165:d1b4690b3f8b | 2894 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ |
AnnaBridge | 165:d1b4690b3f8b | 2895 | |
AnnaBridge | 165:d1b4690b3f8b | 2896 | #endif /* DFSDM1_Filter0 */ |
AnnaBridge | 165:d1b4690b3f8b | 2897 | |
AnnaBridge | 165:d1b4690b3f8b | 2898 | #if defined(LTDC) |
AnnaBridge | 165:d1b4690b3f8b | 2899 | |
AnnaBridge | 165:d1b4690b3f8b | 2900 | #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2901 | (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2902 | ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2903 | ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2904 | ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) |
AnnaBridge | 165:d1b4690b3f8b | 2905 | |
AnnaBridge | 165:d1b4690b3f8b | 2906 | #endif /* LTDC */ |
AnnaBridge | 165:d1b4690b3f8b | 2907 | |
AnnaBridge | 165:d1b4690b3f8b | 2908 | #if defined(DSI) |
AnnaBridge | 165:d1b4690b3f8b | 2909 | |
AnnaBridge | 165:d1b4690b3f8b | 2910 | #define IS_RCC_DSICLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2911 | (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2912 | ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) |
AnnaBridge | 165:d1b4690b3f8b | 2913 | |
AnnaBridge | 165:d1b4690b3f8b | 2914 | #endif /* DSI */ |
AnnaBridge | 165:d1b4690b3f8b | 2915 | |
AnnaBridge | 165:d1b4690b3f8b | 2916 | #if defined(OCTOSPI1) || defined(OCTOSPI2) |
AnnaBridge | 165:d1b4690b3f8b | 2917 | |
AnnaBridge | 165:d1b4690b3f8b | 2918 | #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ |
AnnaBridge | 165:d1b4690b3f8b | 2919 | (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2920 | ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2921 | ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) |
AnnaBridge | 165:d1b4690b3f8b | 2922 | |
AnnaBridge | 165:d1b4690b3f8b | 2923 | #endif /* OCTOSPI1 || OCTOSPI2 */ |
AnnaBridge | 165:d1b4690b3f8b | 2924 | |
AnnaBridge | 165:d1b4690b3f8b | 2925 | #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) |
AnnaBridge | 165:d1b4690b3f8b | 2926 | |
AnnaBridge | 165:d1b4690b3f8b | 2927 | #if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2928 | #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) |
AnnaBridge | 165:d1b4690b3f8b | 2929 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2930 | #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) |
AnnaBridge | 165:d1b4690b3f8b | 2931 | #endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2932 | |
AnnaBridge | 165:d1b4690b3f8b | 2933 | #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) |
AnnaBridge | 165:d1b4690b3f8b | 2934 | |
AnnaBridge | 165:d1b4690b3f8b | 2935 | #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2936 | #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) |
AnnaBridge | 165:d1b4690b3f8b | 2937 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2938 | #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) |
AnnaBridge | 165:d1b4690b3f8b | 2939 | #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2940 | |
AnnaBridge | 165:d1b4690b3f8b | 2941 | #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2942 | ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) |
AnnaBridge | 165:d1b4690b3f8b | 2943 | |
AnnaBridge | 165:d1b4690b3f8b | 2944 | #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2945 | ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) |
AnnaBridge | 165:d1b4690b3f8b | 2946 | |
AnnaBridge | 165:d1b4690b3f8b | 2947 | #if defined(RCC_PLLSAI2_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2948 | |
AnnaBridge | 165:d1b4690b3f8b | 2949 | #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) |
AnnaBridge | 165:d1b4690b3f8b | 2950 | |
AnnaBridge | 165:d1b4690b3f8b | 2951 | #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2952 | #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) |
AnnaBridge | 165:d1b4690b3f8b | 2953 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2954 | #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) |
AnnaBridge | 165:d1b4690b3f8b | 2955 | #endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2956 | |
AnnaBridge | 165:d1b4690b3f8b | 2957 | #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) |
AnnaBridge | 165:d1b4690b3f8b | 2958 | |
AnnaBridge | 165:d1b4690b3f8b | 2959 | #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2960 | #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) |
AnnaBridge | 165:d1b4690b3f8b | 2961 | #else |
AnnaBridge | 165:d1b4690b3f8b | 2962 | #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) |
AnnaBridge | 165:d1b4690b3f8b | 2963 | #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2964 | |
AnnaBridge | 165:d1b4690b3f8b | 2965 | #if defined(RCC_PLLSAI2Q_DIV_SUPPORT) |
AnnaBridge | 165:d1b4690b3f8b | 2966 | #define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2967 | ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) |
AnnaBridge | 165:d1b4690b3f8b | 2968 | #endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2969 | |
AnnaBridge | 165:d1b4690b3f8b | 2970 | #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2971 | ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) |
AnnaBridge | 165:d1b4690b3f8b | 2972 | |
AnnaBridge | 165:d1b4690b3f8b | 2973 | #endif /* RCC_PLLSAI2_SUPPORT */ |
AnnaBridge | 165:d1b4690b3f8b | 2974 | |
AnnaBridge | 165:d1b4690b3f8b | 2975 | #if defined(CRS) |
AnnaBridge | 165:d1b4690b3f8b | 2976 | |
AnnaBridge | 165:d1b4690b3f8b | 2977 | #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2978 | ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2979 | ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) |
AnnaBridge | 165:d1b4690b3f8b | 2980 | |
AnnaBridge | 165:d1b4690b3f8b | 2981 | #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2982 | ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2983 | ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2984 | ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) |
AnnaBridge | 165:d1b4690b3f8b | 2985 | |
AnnaBridge | 165:d1b4690b3f8b | 2986 | #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2987 | ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) |
AnnaBridge | 165:d1b4690b3f8b | 2988 | |
AnnaBridge | 165:d1b4690b3f8b | 2989 | #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) |
AnnaBridge | 165:d1b4690b3f8b | 2990 | |
AnnaBridge | 165:d1b4690b3f8b | 2991 | #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) |
AnnaBridge | 165:d1b4690b3f8b | 2992 | |
AnnaBridge | 165:d1b4690b3f8b | 2993 | #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) |
AnnaBridge | 165:d1b4690b3f8b | 2994 | |
AnnaBridge | 165:d1b4690b3f8b | 2995 | #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ |
AnnaBridge | 165:d1b4690b3f8b | 2996 | ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) |
AnnaBridge | 165:d1b4690b3f8b | 2997 | |
AnnaBridge | 165:d1b4690b3f8b | 2998 | #endif /* CRS */ |
AnnaBridge | 165:d1b4690b3f8b | 2999 | |
AnnaBridge | 165:d1b4690b3f8b | 3000 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3001 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3002 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3003 | |
AnnaBridge | 165:d1b4690b3f8b | 3004 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3005 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3006 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3007 | |
AnnaBridge | 165:d1b4690b3f8b | 3008 | /** |
AnnaBridge | 165:d1b4690b3f8b | 3009 | * @} |
AnnaBridge | 165:d1b4690b3f8b | 3010 | */ |
AnnaBridge | 165:d1b4690b3f8b | 3011 | |
AnnaBridge | 165:d1b4690b3f8b | 3012 | #ifdef __cplusplus |
AnnaBridge | 165:d1b4690b3f8b | 3013 | } |
AnnaBridge | 165:d1b4690b3f8b | 3014 | #endif |
AnnaBridge | 165:d1b4690b3f8b | 3015 | |
AnnaBridge | 165:d1b4690b3f8b | 3016 | #endif /* __STM32L4xx_HAL_RCC_EX_H */ |
AnnaBridge | 165:d1b4690b3f8b | 3017 | |
AnnaBridge | 165:d1b4690b3f8b | 3018 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |