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TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/stm32l1xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32l1xx_ll_system.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of SYSTEM LL module.
AnnaBridge	171:3a7713b1edbc	6	@verbatim
AnnaBridge	171:3a7713b1edbc	7	==============================================================================
AnnaBridge	171:3a7713b1edbc	8	##### How to use this driver #####
AnnaBridge	171:3a7713b1edbc	9	==============================================================================
AnnaBridge	171:3a7713b1edbc	10	[..]
AnnaBridge	171:3a7713b1edbc	11	The LL SYSTEM driver contains a set of generic APIs that can be
AnnaBridge	171:3a7713b1edbc	12	used by user:
AnnaBridge	171:3a7713b1edbc	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
AnnaBridge	171:3a7713b1edbc	14	(+) Access to DBGCMU registers
AnnaBridge	171:3a7713b1edbc	15	(+) Access to SYSCFG registers
AnnaBridge	171:3a7713b1edbc	16	(+) Access to Routing Interfaces registers
AnnaBridge	171:3a7713b1edbc	17
AnnaBridge	171:3a7713b1edbc	18	@endverbatim
AnnaBridge	171:3a7713b1edbc	19	******************************************************************************
AnnaBridge	171:3a7713b1edbc	20	* @attention
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	23	*
AnnaBridge	171:3a7713b1edbc	24	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	25	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	26	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	27	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	28	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	29	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	30	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	31	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	32	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	33	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	34	*
AnnaBridge	171:3a7713b1edbc	35	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	36	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	37	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	38	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	39	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	40	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	41	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	42	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	43	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	44	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	45	*
AnnaBridge	171:3a7713b1edbc	46	******************************************************************************
AnnaBridge	171:3a7713b1edbc	47	*/
AnnaBridge	171:3a7713b1edbc	48
AnnaBridge	171:3a7713b1edbc	49	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	50	#ifndef __STM32L1xx_LL_SYSTEM_H
AnnaBridge	171:3a7713b1edbc	51	#define __STM32L1xx_LL_SYSTEM_H
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	54	extern "C" {
AnnaBridge	171:3a7713b1edbc	55	#endif
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	#include "stm32l1xx.h"
AnnaBridge	171:3a7713b1edbc	59
AnnaBridge	171:3a7713b1edbc	60	/** @addtogroup STM32L1xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	61	* @{
AnnaBridge	171:3a7713b1edbc	62	*/
AnnaBridge	171:3a7713b1edbc	63
AnnaBridge	171:3a7713b1edbc	64	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined(RI)
AnnaBridge	171:3a7713b1edbc	65
AnnaBridge	171:3a7713b1edbc	66	/** @defgroup SYSTEM_LL SYSTEM
AnnaBridge	171:3a7713b1edbc	67	* @{
AnnaBridge	171:3a7713b1edbc	68	*/
AnnaBridge	171:3a7713b1edbc	69
AnnaBridge	171:3a7713b1edbc	70	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	71	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	74	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
AnnaBridge	171:3a7713b1edbc	75	* @{
AnnaBridge	171:3a7713b1edbc	76	*/
AnnaBridge	171:3a7713b1edbc	77
AnnaBridge	171:3a7713b1edbc	78	/**
AnnaBridge	171:3a7713b1edbc	79	* @brief Power-down in Run mode Flash key
AnnaBridge	171:3a7713b1edbc	80	*/
AnnaBridge	171:3a7713b1edbc	81	#define FLASH_PDKEY1 (0x04152637U) /!< Flash power down key1 /
AnnaBridge	171:3a7713b1edbc	82	#define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
AnnaBridge	171:3a7713b1edbc	83	to unlock the RUN_PD bit in FLASH_ACR */
AnnaBridge	171:3a7713b1edbc	84
AnnaBridge	171:3a7713b1edbc	85	/**
AnnaBridge	171:3a7713b1edbc	86	* @}
AnnaBridge	171:3a7713b1edbc	87	*/
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	90
AnnaBridge	171:3a7713b1edbc	91	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	92	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	93	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
AnnaBridge	171:3a7713b1edbc	94	* @{
AnnaBridge	171:3a7713b1edbc	95	*/
AnnaBridge	171:3a7713b1edbc	96
AnnaBridge	171:3a7713b1edbc	97	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
AnnaBridge	171:3a7713b1edbc	98	* @{
AnnaBridge	171:3a7713b1edbc	99	*/
AnnaBridge	171:3a7713b1edbc	100	#define LL_SYSCFG_REMAP_FLASH (0x00000000U) /<! Main Flash memory mapped at 0x00000000 /
AnnaBridge	171:3a7713b1edbc	101	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /<! System Flash memory mapped at 0x00000000 /
AnnaBridge	171:3a7713b1edbc	102	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /<! Embedded SRAM mapped at 0x00000000 /
AnnaBridge	171:3a7713b1edbc	103	#if defined(FSMC_R_BASE)
AnnaBridge	171:3a7713b1edbc	104	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /<! FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 /
AnnaBridge	171:3a7713b1edbc	105	#endif /* FSMC_R_BASE */
AnnaBridge	171:3a7713b1edbc	106	/**
AnnaBridge	171:3a7713b1edbc	107	* @}
AnnaBridge	171:3a7713b1edbc	108	*/
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	/** @defgroup SYSTEM_LL_EC_BOOT SYSCFG BOOT MODE
AnnaBridge	171:3a7713b1edbc	111	* @{
AnnaBridge	171:3a7713b1edbc	112	*/
AnnaBridge	171:3a7713b1edbc	113	#define LL_SYSCFG_BOOTMODE_FLASH (0x00000000U) /<! Main Flash memory boot mode /
AnnaBridge	171:3a7713b1edbc	114	#define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_MEMRMP_BOOT_MODE_0 /<! System Flash memory boot mode /
AnnaBridge	171:3a7713b1edbc	115	#if defined(FSMC_BANK1)
AnnaBridge	171:3a7713b1edbc	116	#define LL_SYSCFG_BOOTMODE_FSMC SYSCFG_MEMRMP_BOOT_MODE_1 /<! FSMC boot mode /
AnnaBridge	171:3a7713b1edbc	117	#endif /* FSMC_BANK1 */
AnnaBridge	171:3a7713b1edbc	118	#define LL_SYSCFG_BOOTMODE_SRAM SYSCFG_MEMRMP_BOOT_MODE /<! Embedded SRAM boot mode /
AnnaBridge	171:3a7713b1edbc	119	/**
AnnaBridge	171:3a7713b1edbc	120	* @}
AnnaBridge	171:3a7713b1edbc	121	*/
AnnaBridge	171:3a7713b1edbc	122
AnnaBridge	171:3a7713b1edbc	123	#if defined(LCD)
AnnaBridge	171:3a7713b1edbc	124	/** @defgroup SYSTEM_LL_EC_LCDCAPA SYSCFG LCD capacitance connection
AnnaBridge	171:3a7713b1edbc	125	* @{
AnnaBridge	171:3a7713b1edbc	126	*/
AnnaBridge	171:3a7713b1edbc	127	#define LL_SYSCFG_LCDCAPA_PB2 SYSCFG_PMC_LCD_CAPA_0 /<! controls the connection of VLCDrail2 on PB2/LCD_VCAP2 /
AnnaBridge	171:3a7713b1edbc	128	#define LL_SYSCFG_LCDCAPA_PB12 SYSCFG_PMC_LCD_CAPA_1 /<! controls the connection of VLCDrail1 on PB12/LCD_VCAP1 /
AnnaBridge	171:3a7713b1edbc	129	#define LL_SYSCFG_LCDCAPA_PB0 SYSCFG_PMC_LCD_CAPA_2 /<! controls the connection of VLCDrail3 on PB0/LCD_VCAP3 /
AnnaBridge	171:3a7713b1edbc	130	#define LL_SYSCFG_LCDCAPA_PE11 SYSCFG_PMC_LCD_CAPA_3 /<! controls the connection of VLCDrail1 on PE11/LCD_VCAP1 /
AnnaBridge	171:3a7713b1edbc	131	#define LL_SYSCFG_LCDCAPA_PE12 SYSCFG_PMC_LCD_CAPA_4 /<! controls the connection of VLCDrail3 on PE12/LCD_VCAP3 /
AnnaBridge	171:3a7713b1edbc	132	/**
AnnaBridge	171:3a7713b1edbc	133	* @}
AnnaBridge	171:3a7713b1edbc	134	*/
AnnaBridge	171:3a7713b1edbc	135
AnnaBridge	171:3a7713b1edbc	136	#endif /* LCD */
AnnaBridge	171:3a7713b1edbc	137
AnnaBridge	171:3a7713b1edbc	138	/** @defgroup SYSTEM_LL_EC_EXTI SYSCFG EXTI PORT
AnnaBridge	171:3a7713b1edbc	139	* @{
AnnaBridge	171:3a7713b1edbc	140	*/
AnnaBridge	171:3a7713b1edbc	141	#define LL_SYSCFG_EXTI_PORTA 0U /!< EXTI PORT A /
AnnaBridge	171:3a7713b1edbc	142	#define LL_SYSCFG_EXTI_PORTB 1U /!< EXTI PORT B /
AnnaBridge	171:3a7713b1edbc	143	#define LL_SYSCFG_EXTI_PORTC 2U /!< EXTI PORT C /
AnnaBridge	171:3a7713b1edbc	144	#define LL_SYSCFG_EXTI_PORTD 3U /!< EXTI PORT D /
AnnaBridge	171:3a7713b1edbc	145	#if defined(GPIOE)
AnnaBridge	171:3a7713b1edbc	146	#define LL_SYSCFG_EXTI_PORTE 4U /!< EXTI PORT E /
AnnaBridge	171:3a7713b1edbc	147	#endif /* GPIOE */
AnnaBridge	171:3a7713b1edbc	148	#if defined(GPIOF)
AnnaBridge	171:3a7713b1edbc	149	#define LL_SYSCFG_EXTI_PORTF 6U /!< EXTI PORT F /
AnnaBridge	171:3a7713b1edbc	150	#endif /* GPIOF */
AnnaBridge	171:3a7713b1edbc	151	#if defined(GPIOG)
AnnaBridge	171:3a7713b1edbc	152	#define LL_SYSCFG_EXTI_PORTG 7U /!< EXTI PORT G /
AnnaBridge	171:3a7713b1edbc	153	#endif /* GPIOG */
AnnaBridge	171:3a7713b1edbc	154	#define LL_SYSCFG_EXTI_PORTH 5U /!< EXTI PORT H /
AnnaBridge	171:3a7713b1edbc	155	/**
AnnaBridge	171:3a7713b1edbc	156	* @}
AnnaBridge	171:3a7713b1edbc	157	*/
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	/** @addtogroup SYSTEM_LL_EC_SYSCFG EXTI LINE
AnnaBridge	171:3a7713b1edbc	160	* @{
AnnaBridge	171:3a7713b1edbc	161	*/
AnnaBridge	171:3a7713b1edbc	162	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U \| 0U) /* EXTI_POSITION_0 \| EXTICR[0] */
AnnaBridge	171:3a7713b1edbc	163	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U \| 0U) /* EXTI_POSITION_4 \| EXTICR[0] */
AnnaBridge	171:3a7713b1edbc	164	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U \| 0U) /* EXTI_POSITION_8 \| EXTICR[0] */
AnnaBridge	171:3a7713b1edbc	165	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U \| 0U) /* EXTI_POSITION_12 \| EXTICR[0] */
AnnaBridge	171:3a7713b1edbc	166	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U \| 1U) /* EXTI_POSITION_0 \| EXTICR[1] */
AnnaBridge	171:3a7713b1edbc	167	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U \| 1U) /* EXTI_POSITION_4 \| EXTICR[1] */
AnnaBridge	171:3a7713b1edbc	168	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U \| 1U) /* EXTI_POSITION_8 \| EXTICR[1] */
AnnaBridge	171:3a7713b1edbc	169	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U \| 1U) /* EXTI_POSITION_12 \| EXTICR[1] */
AnnaBridge	171:3a7713b1edbc	170	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U \| 2U) /* EXTI_POSITION_0 \| EXTICR[2] */
AnnaBridge	171:3a7713b1edbc	171	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U \| 2U) /* EXTI_POSITION_4 \| EXTICR[2] */
AnnaBridge	171:3a7713b1edbc	172	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U \| 2U) /* EXTI_POSITION_8 \| EXTICR[2] */
AnnaBridge	171:3a7713b1edbc	173	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U \| 2U) /* EXTI_POSITION_12 \| EXTICR[2] */
AnnaBridge	171:3a7713b1edbc	174	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U \| 3U) /* EXTI_POSITION_0 \| EXTICR[3] */
AnnaBridge	171:3a7713b1edbc	175	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U \| 3U) /* EXTI_POSITION_4 \| EXTICR[3] */
AnnaBridge	171:3a7713b1edbc	176	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U \| 3U) /* EXTI_POSITION_8 \| EXTICR[3] */
AnnaBridge	171:3a7713b1edbc	177	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U \| 3U) /* EXTI_POSITION_12 \| EXTICR[3] */
AnnaBridge	171:3a7713b1edbc	178	/**
AnnaBridge	171:3a7713b1edbc	179	* @}
AnnaBridge	171:3a7713b1edbc	180	*/
AnnaBridge	171:3a7713b1edbc	181
AnnaBridge	171:3a7713b1edbc	182	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
AnnaBridge	171:3a7713b1edbc	183	* @{
AnnaBridge	171:3a7713b1edbc	184	*/
AnnaBridge	171:3a7713b1edbc	185	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
AnnaBridge	171:3a7713b1edbc	186	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
AnnaBridge	171:3a7713b1edbc	187	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
AnnaBridge	171:3a7713b1edbc	188	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
AnnaBridge	171:3a7713b1edbc	189	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
AnnaBridge	171:3a7713b1edbc	190	/**
AnnaBridge	171:3a7713b1edbc	191	* @}
AnnaBridge	171:3a7713b1edbc	192	*/
AnnaBridge	171:3a7713b1edbc	193
AnnaBridge	171:3a7713b1edbc	194	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
AnnaBridge	171:3a7713b1edbc	195	* @{
AnnaBridge	171:3a7713b1edbc	196	*/
AnnaBridge	171:3a7713b1edbc	197	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	198	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	199	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /!< TIM4 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	200	#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
AnnaBridge	171:3a7713b1edbc	201	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /!< TIM5 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	202	#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
AnnaBridge	171:3a7713b1edbc	203	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	204	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	205	#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
AnnaBridge	171:3a7713b1edbc	206	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC Counter stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	207	#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
AnnaBridge	171:3a7713b1edbc	208	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	209	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	210	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	211	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /!< I2C2 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	212	/**
AnnaBridge	171:3a7713b1edbc	213	* @}
AnnaBridge	171:3a7713b1edbc	214	*/
AnnaBridge	171:3a7713b1edbc	215
AnnaBridge	171:3a7713b1edbc	216	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
AnnaBridge	171:3a7713b1edbc	217	* @{
AnnaBridge	171:3a7713b1edbc	218	*/
AnnaBridge	171:3a7713b1edbc	219	#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /!< TIM9 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	220	#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /!< TIM10 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	221	#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /!< TIM11 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	222	/**
AnnaBridge	171:3a7713b1edbc	223	* @}
AnnaBridge	171:3a7713b1edbc	224	*/
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	/** @defgroup SYSTEM_LL_EC_TIM_SELECT RI TIM selection
AnnaBridge	171:3a7713b1edbc	227	* @{
AnnaBridge	171:3a7713b1edbc	228	*/
AnnaBridge	171:3a7713b1edbc	229	#define LL_RI_TIM_SELECT_NONE (0x00000000U) /!< No timer selected /
AnnaBridge	171:3a7713b1edbc	230	#define LL_RI_TIM_SELECT_TIM2 RI_ICR_TIM_0 /!< Timer 2 selected /
AnnaBridge	171:3a7713b1edbc	231	#define LL_RI_TIM_SELECT_TIM3 RI_ICR_TIM_1 /!< Timer 3 selected /
AnnaBridge	171:3a7713b1edbc	232	#define LL_RI_TIM_SELECT_TIM4 RI_ICR_TIM /!< Timer 4 selected /
AnnaBridge	171:3a7713b1edbc	233	/**
AnnaBridge	171:3a7713b1edbc	234	* @}
AnnaBridge	171:3a7713b1edbc	235	*/
AnnaBridge	171:3a7713b1edbc	236
AnnaBridge	171:3a7713b1edbc	237	/** @defgroup SYSTEM_LL_EC_INPUTCAPTURE RI Input Capture number
AnnaBridge	171:3a7713b1edbc	238	* @{
AnnaBridge	171:3a7713b1edbc	239	*/
AnnaBridge	171:3a7713b1edbc	240	#define LL_RI_INPUTCAPTURE_1 (RI_ICR_IC1 \| RI_ICR_IC1OS) /!< Input Capture 1 select output /
AnnaBridge	171:3a7713b1edbc	241	#define LL_RI_INPUTCAPTURE_2 (RI_ICR_IC2 \| RI_ICR_IC2OS) /!< Input Capture 2 select output /
AnnaBridge	171:3a7713b1edbc	242	#define LL_RI_INPUTCAPTURE_3 (RI_ICR_IC3 \| RI_ICR_IC3OS) /!< Input Capture 3 select output /
AnnaBridge	171:3a7713b1edbc	243	#define LL_RI_INPUTCAPTURE_4 (RI_ICR_IC4 \| RI_ICR_IC4OS) /!< Input Capture 4 select output /
AnnaBridge	171:3a7713b1edbc	244	/**
AnnaBridge	171:3a7713b1edbc	245	* @}
AnnaBridge	171:3a7713b1edbc	246	*/
AnnaBridge	171:3a7713b1edbc	247
AnnaBridge	171:3a7713b1edbc	248	/** @defgroup SYSTEM_LL_EC_INPUTCAPTUREROUTING RI Input Capture Routing
AnnaBridge	171:3a7713b1edbc	249	* @{
AnnaBridge	171:3a7713b1edbc	250	*/
AnnaBridge	171:3a7713b1edbc	251	/* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
AnnaBridge	171:3a7713b1edbc	252	#define LL_RI_INPUTCAPTUREROUTING_0 (0x00000000U) /!< PA0 PA1 PA2 PA3 /
AnnaBridge	171:3a7713b1edbc	253	#define LL_RI_INPUTCAPTUREROUTING_1 (0x00000001U) /!< PA4 PA5 PA6 PA7 /
AnnaBridge	171:3a7713b1edbc	254	#define LL_RI_INPUTCAPTUREROUTING_2 (0x00000002U) /!< PA8 PA9 PA10 PA11 /
AnnaBridge	171:3a7713b1edbc	255	#define LL_RI_INPUTCAPTUREROUTING_3 (0x00000003U) /!< PA12 PA13 PA14 PA15 /
AnnaBridge	171:3a7713b1edbc	256	#define LL_RI_INPUTCAPTUREROUTING_4 (0x00000004U) /!< PC0 PC1 PC2 PC3 /
AnnaBridge	171:3a7713b1edbc	257	#define LL_RI_INPUTCAPTUREROUTING_5 (0x00000005U) /!< PC4 PC5 PC6 PC7 /
AnnaBridge	171:3a7713b1edbc	258	#define LL_RI_INPUTCAPTUREROUTING_6 (0x00000006U) /!< PC8 PC9 PC10 PC11 /
AnnaBridge	171:3a7713b1edbc	259	#define LL_RI_INPUTCAPTUREROUTING_7 (0x00000007U) /!< PC12 PC13 PC14 PC15 /
AnnaBridge	171:3a7713b1edbc	260	#define LL_RI_INPUTCAPTUREROUTING_8 (0x00000008U) /!< PD0 PD1 PD2 PD3 /
AnnaBridge	171:3a7713b1edbc	261	#define LL_RI_INPUTCAPTUREROUTING_9 (0x00000009U) /!< PD4 PD5 PD6 PD7 /
AnnaBridge	171:3a7713b1edbc	262	#define LL_RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /!< PD8 PD9 PD10 PD11 /
AnnaBridge	171:3a7713b1edbc	263	#define LL_RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /!< PD12 PD13 PD14 PD15 /
AnnaBridge	171:3a7713b1edbc	264	#if defined(GPIOE)
AnnaBridge	171:3a7713b1edbc	265	#define LL_RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /!< PE0 PE1 PE2 PE3 /
AnnaBridge	171:3a7713b1edbc	266	#define LL_RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /!< PE4 PE5 PE6 PE7 /
AnnaBridge	171:3a7713b1edbc	267	#define LL_RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /!< PE8 PE9 PE10 PE11 /
AnnaBridge	171:3a7713b1edbc	268	#define LL_RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /!< PE12 PE13 PE14 PE15 /
AnnaBridge	171:3a7713b1edbc	269	#endif /* GPIOE */
AnnaBridge	171:3a7713b1edbc	270	/**
AnnaBridge	171:3a7713b1edbc	271	* @}
AnnaBridge	171:3a7713b1edbc	272	*/
AnnaBridge	171:3a7713b1edbc	273
AnnaBridge	171:3a7713b1edbc	274	/** @defgroup SYSTEM_LL_EC_IOSWITCH_LINKED_ADC RI IO Switch linked to ADC
AnnaBridge	171:3a7713b1edbc	275	* @{
AnnaBridge	171:3a7713b1edbc	276	*/
AnnaBridge	171:3a7713b1edbc	277	#define LL_RI_IOSWITCH_CH0 RI_ASCR1_CH_0 /!< CH[3:0] GR1[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	278	#define LL_RI_IOSWITCH_CH1 RI_ASCR1_CH_1 /!< CH[3:0] GR1[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	279	#define LL_RI_IOSWITCH_CH2 RI_ASCR1_CH_2 /!< CH[3:0] GR1[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	280	#define LL_RI_IOSWITCH_CH3 RI_ASCR1_CH_3 /!< CH[3:0] GR1[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	281	#define LL_RI_IOSWITCH_CH4 RI_ASCR1_CH_4 /!< CH4: Analog switch control /
AnnaBridge	171:3a7713b1edbc	282	#define LL_RI_IOSWITCH_CH5 RI_ASCR1_CH_5 /!< CH5: Comparator 1 analog switch/
AnnaBridge	171:3a7713b1edbc	283	#define LL_RI_IOSWITCH_CH6 RI_ASCR1_CH_6 /!< CH[7:6] GR2[2:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	284	#define LL_RI_IOSWITCH_CH7 RI_ASCR1_CH_7 /!< CH[7:6] GR2[2:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	285	#define LL_RI_IOSWITCH_CH8 RI_ASCR1_CH_8 /!< CH[9:8] GR3[2:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	286	#define LL_RI_IOSWITCH_CH9 RI_ASCR1_CH_9 /!< CH[9:8] GR3[2:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	287	#define LL_RI_IOSWITCH_CH10 RI_ASCR1_CH_10 /!< CH[13:10] GR8[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	288	#define LL_RI_IOSWITCH_CH11 RI_ASCR1_CH_11 /!< CH[13:10] GR8[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	289	#define LL_RI_IOSWITCH_CH12 RI_ASCR1_CH_12 /!< CH[13:10] GR8[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	290	#define LL_RI_IOSWITCH_CH13 RI_ASCR1_CH_13 /!< CH[13:10] GR8[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	291	#define LL_RI_IOSWITCH_CH14 RI_ASCR1_CH_14 /!< CH[15:14] GR9[2:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	292	#define LL_RI_IOSWITCH_CH15 RI_ASCR1_CH_15 /!< CH[15:14] GR9[2:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	293	#define LL_RI_IOSWITCH_CH18 RI_ASCR1_CH_18 /!< CH[21:18]/GR7[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	294	#define LL_RI_IOSWITCH_CH19 RI_ASCR1_CH_19 /!< CH[21:18]/GR7[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	295	#define LL_RI_IOSWITCH_CH20 RI_ASCR1_CH_20 /!< CH[21:18]/GR7[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	296	#define LL_RI_IOSWITCH_CH21 RI_ASCR1_CH_21 /!< CH[21:18]/GR7[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	297	#define LL_RI_IOSWITCH_CH22 RI_ASCR1_CH_22 /!< Analog I/O switch control of channels CH22 /
AnnaBridge	171:3a7713b1edbc	298	#define LL_RI_IOSWITCH_CH23 RI_ASCR1_CH_23 /!< Analog I/O switch control of channels CH23 /
AnnaBridge	171:3a7713b1edbc	299	#define LL_RI_IOSWITCH_CH24 RI_ASCR1_CH_24 /!< Analog I/O switch control of channels CH24 /
AnnaBridge	171:3a7713b1edbc	300	#define LL_RI_IOSWITCH_CH25 RI_ASCR1_CH_25 /!< Analog I/O switch control of channels CH25 /
AnnaBridge	171:3a7713b1edbc	301	#define LL_RI_IOSWITCH_VCOMP RI_ASCR1_VCOMP /*!< VCOMP (ADC channel 26) is an internal switch
AnnaBridge	171:3a7713b1edbc	302	used to connect selected channel to COMP1 non inverting input */
AnnaBridge	171:3a7713b1edbc	303	#if defined(RI_ASCR1_CH_27)
AnnaBridge	171:3a7713b1edbc	304	#define LL_RI_IOSWITCH_CH27 RI_ASCR1_CH_27 /!< CH[30:27]/GR11[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	305	#define LL_RI_IOSWITCH_CH28 RI_ASCR1_CH_28 /!< CH[30:27]/GR11[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	306	#define LL_RI_IOSWITCH_CH29 RI_ASCR1_CH_29 /!< CH[30:27]/GR11[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	307	#define LL_RI_IOSWITCH_CH30 RI_ASCR1_CH_30 /!< CH[30:27]/GR11[4:1]: I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	308	#define LL_RI_IOSWITCH_CH31 RI_ASCR1_CH_31 /!< CH31/GR11-5 I/O Analog switch control /
AnnaBridge	171:3a7713b1edbc	309	#endif /* RI_ASCR1_CH_27 */
AnnaBridge	171:3a7713b1edbc	310	/**
AnnaBridge	171:3a7713b1edbc	311	* @}
AnnaBridge	171:3a7713b1edbc	312	*/
AnnaBridge	171:3a7713b1edbc	313
AnnaBridge	171:3a7713b1edbc	314	/** @defgroup SYSTEM_LL_EC_IOSWITCH_NOT_LINKED_ADC RI IO Switch not linked to ADC
AnnaBridge	171:3a7713b1edbc	315	* @{
AnnaBridge	171:3a7713b1edbc	316	*/
AnnaBridge	171:3a7713b1edbc	317	#define LL_RI_IOSWITCH_GR10_1 RI_ASCR2_GR10_1 /!< GR10-1 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	318	#define LL_RI_IOSWITCH_GR10_2 RI_ASCR2_GR10_2 /!< GR10-2 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	319	#define LL_RI_IOSWITCH_GR10_3 RI_ASCR2_GR10_3 /!< GR10-3 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	320	#define LL_RI_IOSWITCH_GR10_4 RI_ASCR2_GR10_4 /!< GR10-4 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	321	#define LL_RI_IOSWITCH_GR6_1 RI_ASCR2_GR6_1 /!< GR6-1 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	322	#define LL_RI_IOSWITCH_GR6_2 RI_ASCR2_GR6_2 /!< GR6-2 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	323	#define LL_RI_IOSWITCH_GR5_1 RI_ASCR2_GR5_1 /!< GR5-1 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	324	#define LL_RI_IOSWITCH_GR5_2 RI_ASCR2_GR5_2 /!< GR5-2 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	325	#define LL_RI_IOSWITCH_GR5_3 RI_ASCR2_GR5_3 /!< GR5-3 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	326	#define LL_RI_IOSWITCH_GR4_1 RI_ASCR2_GR4_1 /!< GR4-1 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	327	#define LL_RI_IOSWITCH_GR4_2 RI_ASCR2_GR4_2 /!< GR4-2 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	328	#define LL_RI_IOSWITCH_GR4_3 RI_ASCR2_GR4_3 /!< GR4-3 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	329	#if defined(RI_ASCR2_CH0b)
AnnaBridge	171:3a7713b1edbc	330	#define LL_RI_IOSWITCH_CH0b RI_ASCR2_CH0b /!< CH0b-GR03-3 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	331	#if defined(RI_ASCR2_CH1b)
AnnaBridge	171:3a7713b1edbc	332	#define LL_RI_IOSWITCH_CH1b RI_ASCR2_CH1b /!< CH1b-GR03-4 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	333	#define LL_RI_IOSWITCH_CH2b RI_ASCR2_CH2b /!< CH2b-GR03-5 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	334	#define LL_RI_IOSWITCH_CH3b RI_ASCR2_CH3b /!< CH3b-GR09-3 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	335	#define LL_RI_IOSWITCH_CH6b RI_ASCR2_CH6b /!< CH6b-GR09-4 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	336	#define LL_RI_IOSWITCH_CH7b RI_ASCR2_CH7b /!< CH7b-GR02-3 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	337	#define LL_RI_IOSWITCH_CH8b RI_ASCR2_CH8b /!< CH8b-GR02-4 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	338	#define LL_RI_IOSWITCH_CH9b RI_ASCR2_CH9b /!< CH9b-GR02-5 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	339	#define LL_RI_IOSWITCH_CH10b RI_ASCR2_CH10b /!< CH10b-GR07-5 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	340	#define LL_RI_IOSWITCH_CH11b RI_ASCR2_CH11b /!< CH11b-GR07-6 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	341	#define LL_RI_IOSWITCH_CH12b RI_ASCR2_CH12b /!< CH12b-GR07-7 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	342	#endif /* RI_ASCR2_CH1b */
AnnaBridge	171:3a7713b1edbc	343	#define LL_RI_IOSWITCH_GR6_3 RI_ASCR2_GR6_3 /!< GR6-3 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	344	#define LL_RI_IOSWITCH_GR6_4 RI_ASCR2_GR6_4 /!< GR6-4 I/O analog switch control /
AnnaBridge	171:3a7713b1edbc	345	#endif /* RI_ASCR2_CH0b */
AnnaBridge	171:3a7713b1edbc	346	/**
AnnaBridge	171:3a7713b1edbc	347	* @}
AnnaBridge	171:3a7713b1edbc	348	*/
AnnaBridge	171:3a7713b1edbc	349
AnnaBridge	171:3a7713b1edbc	350	/** @defgroup SYSTEM_LL_EC_HSYTERESIS_PORT RI HSYTERESIS PORT
AnnaBridge	171:3a7713b1edbc	351	* @{
AnnaBridge	171:3a7713b1edbc	352	*/
AnnaBridge	171:3a7713b1edbc	353	#define LL_RI_HSYTERESIS_PORT_A 0U /!< HYSTERESIS PORT A /
AnnaBridge	171:3a7713b1edbc	354	#define LL_RI_HSYTERESIS_PORT_B 1U /!< HYSTERESIS PORT B /
AnnaBridge	171:3a7713b1edbc	355	#define LL_RI_HSYTERESIS_PORT_C 2U /!< HYSTERESIS PORT C /
AnnaBridge	171:3a7713b1edbc	356	#define LL_RI_HSYTERESIS_PORT_D 3U /!< HYSTERESIS PORT D /
AnnaBridge	171:3a7713b1edbc	357	#if defined(GPIOE)
AnnaBridge	171:3a7713b1edbc	358	#define LL_RI_HSYTERESIS_PORT_E 4U /!< HYSTERESIS PORT E /
AnnaBridge	171:3a7713b1edbc	359	#endif /* GPIOE */
AnnaBridge	171:3a7713b1edbc	360	#if defined(GPIOF)
AnnaBridge	171:3a7713b1edbc	361	#define LL_RI_HSYTERESIS_PORT_F 5U /!< HYSTERESIS PORT F /
AnnaBridge	171:3a7713b1edbc	362	#endif /* GPIOF */
AnnaBridge	171:3a7713b1edbc	363	#if defined(GPIOG)
AnnaBridge	171:3a7713b1edbc	364	#define LL_RI_HSYTERESIS_PORT_G 6U /!< HYSTERESIS PORT G /
AnnaBridge	171:3a7713b1edbc	365	#endif /* GPIOG */
AnnaBridge	171:3a7713b1edbc	366	/**
AnnaBridge	171:3a7713b1edbc	367	* @}
AnnaBridge	171:3a7713b1edbc	368	*/
AnnaBridge	171:3a7713b1edbc	369
AnnaBridge	171:3a7713b1edbc	370	/** @defgroup SYSTEM_LL_EC_PIN RI PIN
AnnaBridge	171:3a7713b1edbc	371	* @{
AnnaBridge	171:3a7713b1edbc	372	*/
AnnaBridge	171:3a7713b1edbc	373	#define LL_RI_PIN_0 ((uint16_t)0x0001U) /!< Pin 0 selected /
AnnaBridge	171:3a7713b1edbc	374	#define LL_RI_PIN_1 ((uint16_t)0x0002U) /!< Pin 1 selected /
AnnaBridge	171:3a7713b1edbc	375	#define LL_RI_PIN_2 ((uint16_t)0x0004U) /!< Pin 2 selected /
AnnaBridge	171:3a7713b1edbc	376	#define LL_RI_PIN_3 ((uint16_t)0x0008U) /!< Pin 3 selected /
AnnaBridge	171:3a7713b1edbc	377	#define LL_RI_PIN_4 ((uint16_t)0x0010U) /!< Pin 4 selected /
AnnaBridge	171:3a7713b1edbc	378	#define LL_RI_PIN_5 ((uint16_t)0x0020U) /!< Pin 5 selected /
AnnaBridge	171:3a7713b1edbc	379	#define LL_RI_PIN_6 ((uint16_t)0x0040U) /!< Pin 6 selected /
AnnaBridge	171:3a7713b1edbc	380	#define LL_RI_PIN_7 ((uint16_t)0x0080U) /!< Pin 7 selected /
AnnaBridge	171:3a7713b1edbc	381	#define LL_RI_PIN_8 ((uint16_t)0x0100U) /!< Pin 8 selected /
AnnaBridge	171:3a7713b1edbc	382	#define LL_RI_PIN_9 ((uint16_t)0x0200U) /!< Pin 9 selected /
AnnaBridge	171:3a7713b1edbc	383	#define LL_RI_PIN_10 ((uint16_t)0x0400U) /!< Pin 10 selected /
AnnaBridge	171:3a7713b1edbc	384	#define LL_RI_PIN_11 ((uint16_t)0x0800U) /!< Pin 11 selected /
AnnaBridge	171:3a7713b1edbc	385	#define LL_RI_PIN_12 ((uint16_t)0x1000U) /!< Pin 12 selected /
AnnaBridge	171:3a7713b1edbc	386	#define LL_RI_PIN_13 ((uint16_t)0x2000U) /!< Pin 13 selected /
AnnaBridge	171:3a7713b1edbc	387	#define LL_RI_PIN_14 ((uint16_t)0x4000U) /!< Pin 14 selected /
AnnaBridge	171:3a7713b1edbc	388	#define LL_RI_PIN_15 ((uint16_t)0x8000U) /!< Pin 15 selected /
AnnaBridge	171:3a7713b1edbc	389	#define LL_RI_PIN_ALL ((uint16_t)0xFFFFU) /!< All pins selected /
AnnaBridge	171:3a7713b1edbc	390	/**
AnnaBridge	171:3a7713b1edbc	391	* @}
AnnaBridge	171:3a7713b1edbc	392	*/
AnnaBridge	171:3a7713b1edbc	393
AnnaBridge	171:3a7713b1edbc	394	#if defined(RI_ASMR1_PA)
AnnaBridge	171:3a7713b1edbc	395	/** @defgroup SYSTEM_LL_EC_PORT RI PORT
AnnaBridge	171:3a7713b1edbc	396	* @{
AnnaBridge	171:3a7713b1edbc	397	*/
AnnaBridge	171:3a7713b1edbc	398	#define LL_RI_PORT_A 0U /!< PORT A /
AnnaBridge	171:3a7713b1edbc	399	#define LL_RI_PORT_B 1U /!< PORT B /
AnnaBridge	171:3a7713b1edbc	400	#define LL_RI_PORT_C 2U /!< PORT C /
AnnaBridge	171:3a7713b1edbc	401	#if defined(GPIOF)
AnnaBridge	171:3a7713b1edbc	402	#define LL_RI_PORT_F 3U /!< PORT F /
AnnaBridge	171:3a7713b1edbc	403	#endif /* GPIOF */
AnnaBridge	171:3a7713b1edbc	404	#if defined(GPIOG)
AnnaBridge	171:3a7713b1edbc	405	#define LL_RI_PORT_G 4U /!< PORT G /
AnnaBridge	171:3a7713b1edbc	406	#endif /* GPIOG */
AnnaBridge	171:3a7713b1edbc	407	/**
AnnaBridge	171:3a7713b1edbc	408	* @}
AnnaBridge	171:3a7713b1edbc	409	*/
AnnaBridge	171:3a7713b1edbc	410
AnnaBridge	171:3a7713b1edbc	411	#endif /* RI_ASMR1_PA */
AnnaBridge	171:3a7713b1edbc	412
AnnaBridge	171:3a7713b1edbc	413
AnnaBridge	171:3a7713b1edbc	414	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
AnnaBridge	171:3a7713b1edbc	415	* @{
AnnaBridge	171:3a7713b1edbc	416	*/
AnnaBridge	171:3a7713b1edbc	417	#define LL_FLASH_LATENCY_0 0x00000000U /!< FLASH Zero Latency cycle /
AnnaBridge	171:3a7713b1edbc	418	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /!< FLASH One Latency cycle /
AnnaBridge	171:3a7713b1edbc	419	/**
AnnaBridge	171:3a7713b1edbc	420	* @}
AnnaBridge	171:3a7713b1edbc	421	*/
AnnaBridge	171:3a7713b1edbc	422
AnnaBridge	171:3a7713b1edbc	423	/**
AnnaBridge	171:3a7713b1edbc	424	* @}
AnnaBridge	171:3a7713b1edbc	425	*/
AnnaBridge	171:3a7713b1edbc	426
AnnaBridge	171:3a7713b1edbc	427	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	428
AnnaBridge	171:3a7713b1edbc	429	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	430	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
AnnaBridge	171:3a7713b1edbc	431	* @{
AnnaBridge	171:3a7713b1edbc	432	*/
AnnaBridge	171:3a7713b1edbc	433
AnnaBridge	171:3a7713b1edbc	434	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
AnnaBridge	171:3a7713b1edbc	435	* @{
AnnaBridge	171:3a7713b1edbc	436	*/
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438	/**
AnnaBridge	171:3a7713b1edbc	439	* @brief Set memory mapping at address 0x00000000
AnnaBridge	171:3a7713b1edbc	440	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
AnnaBridge	171:3a7713b1edbc	441	* @param Memory This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	442	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	171:3a7713b1edbc	443	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	171:3a7713b1edbc	444	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	171:3a7713b1edbc	445	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
AnnaBridge	171:3a7713b1edbc	446	*
AnnaBridge	171:3a7713b1edbc	447	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	448	* @retval None
AnnaBridge	171:3a7713b1edbc	449	*/
AnnaBridge	171:3a7713b1edbc	450	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
AnnaBridge	171:3a7713b1edbc	451	{
AnnaBridge	171:3a7713b1edbc	452	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
AnnaBridge	171:3a7713b1edbc	453	}
AnnaBridge	171:3a7713b1edbc	454
AnnaBridge	171:3a7713b1edbc	455	/**
AnnaBridge	171:3a7713b1edbc	456	* @brief Get memory mapping at address 0x00000000
AnnaBridge	171:3a7713b1edbc	457	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
AnnaBridge	171:3a7713b1edbc	458	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	459	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	171:3a7713b1edbc	460	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	171:3a7713b1edbc	461	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	171:3a7713b1edbc	462	* @arg @ref LL_SYSCFG_REMAP_FMC (*)
AnnaBridge	171:3a7713b1edbc	463	*
AnnaBridge	171:3a7713b1edbc	464	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	465	*/
AnnaBridge	171:3a7713b1edbc	466	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
AnnaBridge	171:3a7713b1edbc	467	{
AnnaBridge	171:3a7713b1edbc	468	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
AnnaBridge	171:3a7713b1edbc	469	}
AnnaBridge	171:3a7713b1edbc	470
AnnaBridge	171:3a7713b1edbc	471	/**
AnnaBridge	171:3a7713b1edbc	472	* @brief Return the boot mode as configured by user.
AnnaBridge	171:3a7713b1edbc	473	* @rmtoll SYSCFG_MEMRMP BOOT_MODE LL_SYSCFG_GetBootMode
AnnaBridge	171:3a7713b1edbc	474	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	475	* @arg @ref LL_SYSCFG_BOOTMODE_FLASH
AnnaBridge	171:3a7713b1edbc	476	* @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH
AnnaBridge	171:3a7713b1edbc	477	* @arg @ref LL_SYSCFG_BOOTMODE_FSMC (*)
AnnaBridge	171:3a7713b1edbc	478	* @arg @ref LL_SYSCFG_BOOTMODE_SRAM
AnnaBridge	171:3a7713b1edbc	479	*
AnnaBridge	171:3a7713b1edbc	480	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	481	*/
AnnaBridge	171:3a7713b1edbc	482	__STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void)
AnnaBridge	171:3a7713b1edbc	483	{
AnnaBridge	171:3a7713b1edbc	484	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE));
AnnaBridge	171:3a7713b1edbc	485	}
AnnaBridge	171:3a7713b1edbc	486
AnnaBridge	171:3a7713b1edbc	487	/**
AnnaBridge	171:3a7713b1edbc	488	* @brief Enable internal pull-up on USB DP line.
AnnaBridge	171:3a7713b1edbc	489	* @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_EnableUSBPullUp
AnnaBridge	171:3a7713b1edbc	490	* @retval None
AnnaBridge	171:3a7713b1edbc	491	*/
AnnaBridge	171:3a7713b1edbc	492	__STATIC_INLINE void LL_SYSCFG_EnableUSBPullUp(void)
AnnaBridge	171:3a7713b1edbc	493	{
AnnaBridge	171:3a7713b1edbc	494	SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU);
AnnaBridge	171:3a7713b1edbc	495	}
AnnaBridge	171:3a7713b1edbc	496
AnnaBridge	171:3a7713b1edbc	497	/**
AnnaBridge	171:3a7713b1edbc	498	* @brief Disable internal pull-up on USB DP line.
AnnaBridge	171:3a7713b1edbc	499	* @rmtoll SYSCFG_PMC USB_PU LL_SYSCFG_DisableUSBPullUp
AnnaBridge	171:3a7713b1edbc	500	* @retval None
AnnaBridge	171:3a7713b1edbc	501	*/
AnnaBridge	171:3a7713b1edbc	502	__STATIC_INLINE void LL_SYSCFG_DisableUSBPullUp(void)
AnnaBridge	171:3a7713b1edbc	503	{
AnnaBridge	171:3a7713b1edbc	504	CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU);
AnnaBridge	171:3a7713b1edbc	505	}
AnnaBridge	171:3a7713b1edbc	506
AnnaBridge	171:3a7713b1edbc	507	#if defined(LCD)
AnnaBridge	171:3a7713b1edbc	508	/**
AnnaBridge	171:3a7713b1edbc	509	* @brief Enable decoupling capacitance connection.
AnnaBridge	171:3a7713b1edbc	510	* @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_EnableLCDCapacitanceConnection
AnnaBridge	171:3a7713b1edbc	511	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	512	* @arg @ref LL_SYSCFG_LCDCAPA_PB2
AnnaBridge	171:3a7713b1edbc	513	* @arg @ref LL_SYSCFG_LCDCAPA_PB12
AnnaBridge	171:3a7713b1edbc	514	* @arg @ref LL_SYSCFG_LCDCAPA_PB0
AnnaBridge	171:3a7713b1edbc	515	* @arg @ref LL_SYSCFG_LCDCAPA_PE11
AnnaBridge	171:3a7713b1edbc	516	* @arg @ref LL_SYSCFG_LCDCAPA_PE12
AnnaBridge	171:3a7713b1edbc	517	* @retval None
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519	__STATIC_INLINE void LL_SYSCFG_EnableLCDCapacitanceConnection(uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	520	{
AnnaBridge	171:3a7713b1edbc	521	SET_BIT(SYSCFG->PMC, Pin);
AnnaBridge	171:3a7713b1edbc	522	}
AnnaBridge	171:3a7713b1edbc	523
AnnaBridge	171:3a7713b1edbc	524	/**
AnnaBridge	171:3a7713b1edbc	525	* @brief DIsable decoupling capacitance connection.
AnnaBridge	171:3a7713b1edbc	526	* @rmtoll SYSCFG_PMC LCD_CAPA LL_SYSCFG_DisableLCDCapacitanceConnection
AnnaBridge	171:3a7713b1edbc	527	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	528	* @arg @ref LL_SYSCFG_LCDCAPA_PB2
AnnaBridge	171:3a7713b1edbc	529	* @arg @ref LL_SYSCFG_LCDCAPA_PB12
AnnaBridge	171:3a7713b1edbc	530	* @arg @ref LL_SYSCFG_LCDCAPA_PB0
AnnaBridge	171:3a7713b1edbc	531	* @arg @ref LL_SYSCFG_LCDCAPA_PE11
AnnaBridge	171:3a7713b1edbc	532	* @arg @ref LL_SYSCFG_LCDCAPA_PE12
AnnaBridge	171:3a7713b1edbc	533	* @retval None
AnnaBridge	171:3a7713b1edbc	534	*/
AnnaBridge	171:3a7713b1edbc	535	__STATIC_INLINE void LL_SYSCFG_DisableLCDCapacitanceConnection(uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	536	{
AnnaBridge	171:3a7713b1edbc	537	CLEAR_BIT(SYSCFG->PMC, Pin);
AnnaBridge	171:3a7713b1edbc	538	}
AnnaBridge	171:3a7713b1edbc	539	#endif /* LCD */
AnnaBridge	171:3a7713b1edbc	540
AnnaBridge	171:3a7713b1edbc	541	/**
AnnaBridge	171:3a7713b1edbc	542	* @brief Configure source input for the EXTI external interrupt.
AnnaBridge	171:3a7713b1edbc	543	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	544	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	545	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	546	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	547	* SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	548	* SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	549	* SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	550	* SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	551	* SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	552	* SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	553	* SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	554	* SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	555	* SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	556	* SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	557	* SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	558	* SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	559	* SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	560	* SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	561	* SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	562	* SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	563	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	564	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	565	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	566	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	567	* SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	568	* SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	569	* SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	570	* SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	571	* SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	572	* SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	573	* SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	574	* SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	575	* SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	576	* SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	577	* SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	578	* SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	579	* SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	580	* SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	581	* SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	582	* SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	583	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	584	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	585	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	586	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	587	* SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	588	* SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	589	* SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	590	* SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	591	* SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	592	* SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	593	* SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	594	* SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	595	* SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	596	* SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	597	* SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	598	* SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	599	* SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	600	* SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	601	* SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	602	* SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	603	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	604	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	605	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	606	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
AnnaBridge	171:3a7713b1edbc	607	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	608	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	171:3a7713b1edbc	609	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	171:3a7713b1edbc	610	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	171:3a7713b1edbc	611	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	171:3a7713b1edbc	612	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
AnnaBridge	171:3a7713b1edbc	613	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
AnnaBridge	171:3a7713b1edbc	614	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
AnnaBridge	171:3a7713b1edbc	615	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	171:3a7713b1edbc	616	*
AnnaBridge	171:3a7713b1edbc	617	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	618	* @param Line This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	619	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	171:3a7713b1edbc	620	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	171:3a7713b1edbc	621	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	171:3a7713b1edbc	622	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	171:3a7713b1edbc	623	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	171:3a7713b1edbc	624	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	171:3a7713b1edbc	625	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	171:3a7713b1edbc	626	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	171:3a7713b1edbc	627	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	171:3a7713b1edbc	628	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	171:3a7713b1edbc	629	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	171:3a7713b1edbc	630	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	171:3a7713b1edbc	631	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	171:3a7713b1edbc	632	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	171:3a7713b1edbc	633	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	171:3a7713b1edbc	634	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	171:3a7713b1edbc	635	* @retval None
AnnaBridge	171:3a7713b1edbc	636	*/
AnnaBridge	171:3a7713b1edbc	637	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
AnnaBridge	171:3a7713b1edbc	638	{
AnnaBridge	171:3a7713b1edbc	639	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
AnnaBridge	171:3a7713b1edbc	640	}
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	/**
AnnaBridge	171:3a7713b1edbc	643	* @brief Get the configured defined for specific EXTI Line
AnnaBridge	171:3a7713b1edbc	644	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	645	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	646	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	647	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	648	* SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	649	* SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	650	* SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	651	* SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	652	* SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	653	* SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	654	* SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	655	* SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	656	* SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	657	* SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	658	* SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	659	* SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	660	* SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	661	* SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	662	* SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	663	* SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	664	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	665	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	666	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	667	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	668	* SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	669	* SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	670	* SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	671	* SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	672	* SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	673	* SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	674	* SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	675	* SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	676	* SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	677	* SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	678	* SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	679	* SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	680	* SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	681	* SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	682	* SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	683	* SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	684	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	685	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	686	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	687	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	688	* SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	689	* SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	690	* SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	691	* SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	692	* SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	693	* SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	694	* SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	695	* SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	696	* SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	697	* SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	698	* SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	699	* SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	700	* SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	701	* SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	702	* SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	703	* SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	704	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	705	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	706	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
AnnaBridge	171:3a7713b1edbc	707	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
AnnaBridge	171:3a7713b1edbc	708	* @param Line This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	709	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	171:3a7713b1edbc	710	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	171:3a7713b1edbc	711	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	171:3a7713b1edbc	712	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	171:3a7713b1edbc	713	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	171:3a7713b1edbc	714	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	171:3a7713b1edbc	715	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	171:3a7713b1edbc	716	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	171:3a7713b1edbc	717	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	171:3a7713b1edbc	718	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	171:3a7713b1edbc	719	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	171:3a7713b1edbc	720	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	171:3a7713b1edbc	721	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	171:3a7713b1edbc	722	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	171:3a7713b1edbc	723	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	171:3a7713b1edbc	724	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	171:3a7713b1edbc	725	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	726	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	171:3a7713b1edbc	727	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	171:3a7713b1edbc	728	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	171:3a7713b1edbc	729	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	171:3a7713b1edbc	730	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
AnnaBridge	171:3a7713b1edbc	731	* @arg @ref LL_SYSCFG_EXTI_PORTF (*)
AnnaBridge	171:3a7713b1edbc	732	* @arg @ref LL_SYSCFG_EXTI_PORTG (*)
AnnaBridge	171:3a7713b1edbc	733	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	171:3a7713b1edbc	734	*
AnnaBridge	171:3a7713b1edbc	735	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	736	*/
AnnaBridge	171:3a7713b1edbc	737	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
AnnaBridge	171:3a7713b1edbc	738	{
AnnaBridge	171:3a7713b1edbc	739	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
AnnaBridge	171:3a7713b1edbc	740	}
AnnaBridge	171:3a7713b1edbc	741
AnnaBridge	171:3a7713b1edbc	742	/**
AnnaBridge	171:3a7713b1edbc	743	* @}
AnnaBridge	171:3a7713b1edbc	744	*/
AnnaBridge	171:3a7713b1edbc	745
AnnaBridge	171:3a7713b1edbc	746	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
AnnaBridge	171:3a7713b1edbc	747	* @{
AnnaBridge	171:3a7713b1edbc	748	*/
AnnaBridge	171:3a7713b1edbc	749
AnnaBridge	171:3a7713b1edbc	750	/**
AnnaBridge	171:3a7713b1edbc	751	* @brief Return the device identifier
AnnaBridge	171:3a7713b1edbc	752	* @note 0x416: Cat.1 device\n
AnnaBridge	171:3a7713b1edbc	753	* 0x429: Cat.2 device\n
AnnaBridge	171:3a7713b1edbc	754	* 0x427: Cat.3 device\n
AnnaBridge	171:3a7713b1edbc	755	* 0x436: Cat.4 device or Cat.3 device(1)\n
AnnaBridge	171:3a7713b1edbc	756	* 0x437: Cat.5 device\n
AnnaBridge	171:3a7713b1edbc	757	*
AnnaBridge	171:3a7713b1edbc	758	* (1) Cat.3 devices: STM32L15xxC or STM3216xxC devices with
AnnaBridge	171:3a7713b1edbc	759	* RPN ending with letter 'A', in WLCSP64 packages or with more then 100 pin.
AnnaBridge	171:3a7713b1edbc	760	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
AnnaBridge	171:3a7713b1edbc	761	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
AnnaBridge	171:3a7713b1edbc	762	*/
AnnaBridge	171:3a7713b1edbc	763	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
AnnaBridge	171:3a7713b1edbc	764	{
AnnaBridge	171:3a7713b1edbc	765	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
AnnaBridge	171:3a7713b1edbc	766	}
AnnaBridge	171:3a7713b1edbc	767
AnnaBridge	171:3a7713b1edbc	768	/**
AnnaBridge	171:3a7713b1edbc	769	* @brief Return the device revision identifier
AnnaBridge	171:3a7713b1edbc	770	* @note This field indicates the revision of the device.
AnnaBridge	171:3a7713b1edbc	771	For example, it is read as Cat.1 RevA -> 0x1000, Cat.2 Rev Z -> 0x1018...
AnnaBridge	171:3a7713b1edbc	772	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
AnnaBridge	171:3a7713b1edbc	773	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	171:3a7713b1edbc	774	*/
AnnaBridge	171:3a7713b1edbc	775	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
AnnaBridge	171:3a7713b1edbc	776	{
AnnaBridge	171:3a7713b1edbc	777	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
AnnaBridge	171:3a7713b1edbc	778	}
AnnaBridge	171:3a7713b1edbc	779
AnnaBridge	171:3a7713b1edbc	780	/**
AnnaBridge	171:3a7713b1edbc	781	* @brief Enable the Debug Module during SLEEP mode
AnnaBridge	171:3a7713b1edbc	782	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
AnnaBridge	171:3a7713b1edbc	783	* @retval None
AnnaBridge	171:3a7713b1edbc	784	*/
AnnaBridge	171:3a7713b1edbc	785	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
AnnaBridge	171:3a7713b1edbc	786	{
AnnaBridge	171:3a7713b1edbc	787	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
AnnaBridge	171:3a7713b1edbc	788	}
AnnaBridge	171:3a7713b1edbc	789
AnnaBridge	171:3a7713b1edbc	790	/**
AnnaBridge	171:3a7713b1edbc	791	* @brief Disable the Debug Module during SLEEP mode
AnnaBridge	171:3a7713b1edbc	792	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
AnnaBridge	171:3a7713b1edbc	793	* @retval None
AnnaBridge	171:3a7713b1edbc	794	*/
AnnaBridge	171:3a7713b1edbc	795	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
AnnaBridge	171:3a7713b1edbc	796	{
AnnaBridge	171:3a7713b1edbc	797	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
AnnaBridge	171:3a7713b1edbc	798	}
AnnaBridge	171:3a7713b1edbc	799
AnnaBridge	171:3a7713b1edbc	800	/**
AnnaBridge	171:3a7713b1edbc	801	* @brief Enable the Debug Module during STOP mode
AnnaBridge	171:3a7713b1edbc	802	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
AnnaBridge	171:3a7713b1edbc	803	* @retval None
AnnaBridge	171:3a7713b1edbc	804	*/
AnnaBridge	171:3a7713b1edbc	805	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
AnnaBridge	171:3a7713b1edbc	806	{
AnnaBridge	171:3a7713b1edbc	807	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	171:3a7713b1edbc	808	}
AnnaBridge	171:3a7713b1edbc	809
AnnaBridge	171:3a7713b1edbc	810	/**
AnnaBridge	171:3a7713b1edbc	811	* @brief Disable the Debug Module during STOP mode
AnnaBridge	171:3a7713b1edbc	812	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
AnnaBridge	171:3a7713b1edbc	813	* @retval None
AnnaBridge	171:3a7713b1edbc	814	*/
AnnaBridge	171:3a7713b1edbc	815	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
AnnaBridge	171:3a7713b1edbc	816	{
AnnaBridge	171:3a7713b1edbc	817	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	171:3a7713b1edbc	818	}
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820	/**
AnnaBridge	171:3a7713b1edbc	821	* @brief Enable the Debug Module during STANDBY mode
AnnaBridge	171:3a7713b1edbc	822	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
AnnaBridge	171:3a7713b1edbc	823	* @retval None
AnnaBridge	171:3a7713b1edbc	824	*/
AnnaBridge	171:3a7713b1edbc	825	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
AnnaBridge	171:3a7713b1edbc	826	{
AnnaBridge	171:3a7713b1edbc	827	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	171:3a7713b1edbc	828	}
AnnaBridge	171:3a7713b1edbc	829
AnnaBridge	171:3a7713b1edbc	830	/**
AnnaBridge	171:3a7713b1edbc	831	* @brief Disable the Debug Module during STANDBY mode
AnnaBridge	171:3a7713b1edbc	832	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
AnnaBridge	171:3a7713b1edbc	833	* @retval None
AnnaBridge	171:3a7713b1edbc	834	*/
AnnaBridge	171:3a7713b1edbc	835	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
AnnaBridge	171:3a7713b1edbc	836	{
AnnaBridge	171:3a7713b1edbc	837	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	171:3a7713b1edbc	838	}
AnnaBridge	171:3a7713b1edbc	839
AnnaBridge	171:3a7713b1edbc	840	/**
AnnaBridge	171:3a7713b1edbc	841	* @brief Set Trace pin assignment control
AnnaBridge	171:3a7713b1edbc	842	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
AnnaBridge	171:3a7713b1edbc	843	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
AnnaBridge	171:3a7713b1edbc	844	* @param PinAssignment This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	845	* @arg @ref LL_DBGMCU_TRACE_NONE
AnnaBridge	171:3a7713b1edbc	846	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
AnnaBridge	171:3a7713b1edbc	847	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
AnnaBridge	171:3a7713b1edbc	848	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
AnnaBridge	171:3a7713b1edbc	849	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
AnnaBridge	171:3a7713b1edbc	850	* @retval None
AnnaBridge	171:3a7713b1edbc	851	*/
AnnaBridge	171:3a7713b1edbc	852	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
AnnaBridge	171:3a7713b1edbc	853	{
AnnaBridge	171:3a7713b1edbc	854	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
AnnaBridge	171:3a7713b1edbc	855	}
AnnaBridge	171:3a7713b1edbc	856
AnnaBridge	171:3a7713b1edbc	857	/**
AnnaBridge	171:3a7713b1edbc	858	* @brief Get Trace pin assignment control
AnnaBridge	171:3a7713b1edbc	859	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
AnnaBridge	171:3a7713b1edbc	860	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
AnnaBridge	171:3a7713b1edbc	861	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	862	* @arg @ref LL_DBGMCU_TRACE_NONE
AnnaBridge	171:3a7713b1edbc	863	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
AnnaBridge	171:3a7713b1edbc	864	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
AnnaBridge	171:3a7713b1edbc	865	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
AnnaBridge	171:3a7713b1edbc	866	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
AnnaBridge	171:3a7713b1edbc	867	*/
AnnaBridge	171:3a7713b1edbc	868	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
AnnaBridge	171:3a7713b1edbc	869	{
AnnaBridge	171:3a7713b1edbc	870	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
AnnaBridge	171:3a7713b1edbc	871	}
AnnaBridge	171:3a7713b1edbc	872
AnnaBridge	171:3a7713b1edbc	873	/**
AnnaBridge	171:3a7713b1edbc	874	* @brief Freeze APB1 peripherals (group1 peripherals)
AnnaBridge	171:3a7713b1edbc	875	* @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	876	* APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	877	* APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	878	* APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	879	* APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	880	* APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	881	* APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	882	* APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	883	* APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	884	* APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	885	* APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph
AnnaBridge	171:3a7713b1edbc	886	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	887	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
AnnaBridge	171:3a7713b1edbc	888	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
AnnaBridge	171:3a7713b1edbc	889	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
AnnaBridge	171:3a7713b1edbc	890	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
AnnaBridge	171:3a7713b1edbc	891	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
AnnaBridge	171:3a7713b1edbc	892	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
AnnaBridge	171:3a7713b1edbc	893	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*)
AnnaBridge	171:3a7713b1edbc	894	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	171:3a7713b1edbc	895	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	171:3a7713b1edbc	896	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	171:3a7713b1edbc	897	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
AnnaBridge	171:3a7713b1edbc	898	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	899	* @retval None
AnnaBridge	171:3a7713b1edbc	900	*/
AnnaBridge	171:3a7713b1edbc	901	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	902	{
AnnaBridge	171:3a7713b1edbc	903	SET_BIT(DBGMCU->APB1FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	904	}
AnnaBridge	171:3a7713b1edbc	905
AnnaBridge	171:3a7713b1edbc	906	/**
AnnaBridge	171:3a7713b1edbc	907	* @brief Unfreeze APB1 peripherals (group1 peripherals)
AnnaBridge	171:3a7713b1edbc	908	* @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	909	* APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	910	* APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	911	* APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	912	* APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	913	* APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	914	* APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	915	* APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	916	* APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	917	* APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	918	* APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
AnnaBridge	171:3a7713b1edbc	919	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	920	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
AnnaBridge	171:3a7713b1edbc	921	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
AnnaBridge	171:3a7713b1edbc	922	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
AnnaBridge	171:3a7713b1edbc	923	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
AnnaBridge	171:3a7713b1edbc	924	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
AnnaBridge	171:3a7713b1edbc	925	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
AnnaBridge	171:3a7713b1edbc	926	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP (*)
AnnaBridge	171:3a7713b1edbc	927	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	171:3a7713b1edbc	928	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	171:3a7713b1edbc	929	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	171:3a7713b1edbc	930	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
AnnaBridge	171:3a7713b1edbc	931	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	932	* @retval None
AnnaBridge	171:3a7713b1edbc	933	*/
AnnaBridge	171:3a7713b1edbc	934	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	935	{
AnnaBridge	171:3a7713b1edbc	936	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	937	}
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	/**
AnnaBridge	171:3a7713b1edbc	940	* @brief Freeze APB2 peripherals
AnnaBridge	171:3a7713b1edbc	941	* @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	942	* APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	943	* APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
AnnaBridge	171:3a7713b1edbc	944	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	945	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
AnnaBridge	171:3a7713b1edbc	946	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
AnnaBridge	171:3a7713b1edbc	947	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
AnnaBridge	171:3a7713b1edbc	948	* @retval None
AnnaBridge	171:3a7713b1edbc	949	*/
AnnaBridge	171:3a7713b1edbc	950	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	951	{
AnnaBridge	171:3a7713b1edbc	952	SET_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	953	}
AnnaBridge	171:3a7713b1edbc	954
AnnaBridge	171:3a7713b1edbc	955	/**
AnnaBridge	171:3a7713b1edbc	956	* @brief Unfreeze APB2 peripherals
AnnaBridge	171:3a7713b1edbc	957	* @rmtoll APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	958	* APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	959	* APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
AnnaBridge	171:3a7713b1edbc	960	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	961	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
AnnaBridge	171:3a7713b1edbc	962	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
AnnaBridge	171:3a7713b1edbc	963	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
AnnaBridge	171:3a7713b1edbc	964	* @retval None
AnnaBridge	171:3a7713b1edbc	965	*/
AnnaBridge	171:3a7713b1edbc	966	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	967	{
AnnaBridge	171:3a7713b1edbc	968	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	969	}
AnnaBridge	171:3a7713b1edbc	970
AnnaBridge	171:3a7713b1edbc	971	/**
AnnaBridge	171:3a7713b1edbc	972	* @}
AnnaBridge	171:3a7713b1edbc	973	*/
AnnaBridge	171:3a7713b1edbc	974
AnnaBridge	171:3a7713b1edbc	975	/** @defgroup SYSTEM_LL_EF_RI RI
AnnaBridge	171:3a7713b1edbc	976	* @{
AnnaBridge	171:3a7713b1edbc	977	*/
AnnaBridge	171:3a7713b1edbc	978
AnnaBridge	171:3a7713b1edbc	979	/**
AnnaBridge	171:3a7713b1edbc	980	* @brief Configures the routing interface to map Input Capture x of TIMx to a selected I/O pin.
AnnaBridge	171:3a7713b1edbc	981	* @rmtoll RI_ICR IC1OS LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	982	* RI_ICR IC2OS LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	983	* RI_ICR IC3OS LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	984	* RI_ICR IC4OS LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	985	* RI_ICR TIM LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	986	* RI_ICR IC1 LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	987	* RI_ICR IC2 LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	988	* RI_ICR IC3 LL_RI_SetRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	989	* RI_ICR IC4 LL_RI_SetRemapInputCapture_TIM
AnnaBridge	171:3a7713b1edbc	990	* @param TIM_Select This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	991	* @arg @ref LL_RI_TIM_SELECT_NONE
AnnaBridge	171:3a7713b1edbc	992	* @arg @ref LL_RI_TIM_SELECT_TIM2
AnnaBridge	171:3a7713b1edbc	993	* @arg @ref LL_RI_TIM_SELECT_TIM3
AnnaBridge	171:3a7713b1edbc	994	* @arg @ref LL_RI_TIM_SELECT_TIM4
AnnaBridge	171:3a7713b1edbc	995	* @param InputCaptureChannel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	996	* @arg @ref LL_RI_INPUTCAPTURE_1
AnnaBridge	171:3a7713b1edbc	997	* @arg @ref LL_RI_INPUTCAPTURE_2
AnnaBridge	171:3a7713b1edbc	998	* @arg @ref LL_RI_INPUTCAPTURE_3
AnnaBridge	171:3a7713b1edbc	999	* @arg @ref LL_RI_INPUTCAPTURE_4
AnnaBridge	171:3a7713b1edbc	1000	* @param Input This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1001	* @arg @ref LL_RI_INPUTCAPTUREROUTING_0
AnnaBridge	171:3a7713b1edbc	1002	* @arg @ref LL_RI_INPUTCAPTUREROUTING_1
AnnaBridge	171:3a7713b1edbc	1003	* @arg @ref LL_RI_INPUTCAPTUREROUTING_2
AnnaBridge	171:3a7713b1edbc	1004	* @arg @ref LL_RI_INPUTCAPTUREROUTING_3
AnnaBridge	171:3a7713b1edbc	1005	* @arg @ref LL_RI_INPUTCAPTUREROUTING_4
AnnaBridge	171:3a7713b1edbc	1006	* @arg @ref LL_RI_INPUTCAPTUREROUTING_5
AnnaBridge	171:3a7713b1edbc	1007	* @arg @ref LL_RI_INPUTCAPTUREROUTING_6
AnnaBridge	171:3a7713b1edbc	1008	* @arg @ref LL_RI_INPUTCAPTUREROUTING_7
AnnaBridge	171:3a7713b1edbc	1009	* @arg @ref LL_RI_INPUTCAPTUREROUTING_8
AnnaBridge	171:3a7713b1edbc	1010	* @arg @ref LL_RI_INPUTCAPTUREROUTING_9
AnnaBridge	171:3a7713b1edbc	1011	* @arg @ref LL_RI_INPUTCAPTUREROUTING_10
AnnaBridge	171:3a7713b1edbc	1012	* @arg @ref LL_RI_INPUTCAPTUREROUTING_11
AnnaBridge	171:3a7713b1edbc	1013	* @arg @ref LL_RI_INPUTCAPTUREROUTING_12 (*)
AnnaBridge	171:3a7713b1edbc	1014	* @arg @ref LL_RI_INPUTCAPTUREROUTING_13 (*)
AnnaBridge	171:3a7713b1edbc	1015	* @arg @ref LL_RI_INPUTCAPTUREROUTING_14 (*)
AnnaBridge	171:3a7713b1edbc	1016	* @arg @ref LL_RI_INPUTCAPTUREROUTING_15 (*)
AnnaBridge	171:3a7713b1edbc	1017	*
AnnaBridge	171:3a7713b1edbc	1018	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1019	* @retval None
AnnaBridge	171:3a7713b1edbc	1020	*/
AnnaBridge	171:3a7713b1edbc	1021	__STATIC_INLINE void LL_RI_SetRemapInputCapture_TIM(uint32_t TIM_Select, uint32_t InputCaptureChannel, uint32_t Input)
AnnaBridge	171:3a7713b1edbc	1022	{
AnnaBridge	171:3a7713b1edbc	1023	MODIFY_REG(RI->ICR,
AnnaBridge	171:3a7713b1edbc	1024	RI_ICR_TIM \| (InputCaptureChannel & (RI_ICR_IC4 \| RI_ICR_IC3 \| RI_ICR_IC2 \| RI_ICR_IC1)) \| (InputCaptureChannel & (RI_ICR_IC4OS \| RI_ICR_IC3OS \| RI_ICR_IC2OS \| RI_ICR_IC1OS)),
AnnaBridge	171:3a7713b1edbc	1025	TIM_Select \| (InputCaptureChannel & (RI_ICR_IC4 \| RI_ICR_IC3 \| RI_ICR_IC2 \| RI_ICR_IC1)) \| (Input << POSITION_VAL(InputCaptureChannel)));
AnnaBridge	171:3a7713b1edbc	1026	}
AnnaBridge	171:3a7713b1edbc	1027
AnnaBridge	171:3a7713b1edbc	1028	/**
AnnaBridge	171:3a7713b1edbc	1029	* @brief Disable the TIM Input capture remap (select the standard AF)
AnnaBridge	171:3a7713b1edbc	1030	* @rmtoll RI_ICR IC1 LL_RI_DisableRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	1031	* RI_ICR IC2 LL_RI_DisableRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	1032	* RI_ICR IC3 LL_RI_DisableRemapInputCapture_TIM\n
AnnaBridge	171:3a7713b1edbc	1033	* RI_ICR IC4 LL_RI_DisableRemapInputCapture_TIM
AnnaBridge	171:3a7713b1edbc	1034	* @param InputCaptureChannel This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1035	* @arg @ref LL_RI_INPUTCAPTURE_1
AnnaBridge	171:3a7713b1edbc	1036	* @arg @ref LL_RI_INPUTCAPTURE_2
AnnaBridge	171:3a7713b1edbc	1037	* @arg @ref LL_RI_INPUTCAPTURE_3
AnnaBridge	171:3a7713b1edbc	1038	* @arg @ref LL_RI_INPUTCAPTURE_4
AnnaBridge	171:3a7713b1edbc	1039	* @retval None
AnnaBridge	171:3a7713b1edbc	1040	*/
AnnaBridge	171:3a7713b1edbc	1041	__STATIC_INLINE void LL_RI_DisableRemapInputCapture_TIM(uint32_t InputCaptureChannel)
AnnaBridge	171:3a7713b1edbc	1042	{
AnnaBridge	171:3a7713b1edbc	1043	CLEAR_BIT(RI->ICR, (InputCaptureChannel & (RI_ICR_IC4 \| RI_ICR_IC3 \| RI_ICR_IC2 \| RI_ICR_IC1)));
AnnaBridge	171:3a7713b1edbc	1044	}
AnnaBridge	171:3a7713b1edbc	1045
AnnaBridge	171:3a7713b1edbc	1046	/**
AnnaBridge	171:3a7713b1edbc	1047	* @brief Close the routing interface Input Output switches linked to ADC.
AnnaBridge	171:3a7713b1edbc	1048	* @rmtoll RI_ASCR1 CH LL_RI_CloseIOSwitchLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1049	* RI_ASCR1 VCOMP LL_RI_CloseIOSwitchLinkedToADC
AnnaBridge	171:3a7713b1edbc	1050	* @param IOSwitch This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1051	* @arg @ref LL_RI_IOSWITCH_CH0
AnnaBridge	171:3a7713b1edbc	1052	* @arg @ref LL_RI_IOSWITCH_CH1
AnnaBridge	171:3a7713b1edbc	1053	* @arg @ref LL_RI_IOSWITCH_CH2
AnnaBridge	171:3a7713b1edbc	1054	* @arg @ref LL_RI_IOSWITCH_CH3
AnnaBridge	171:3a7713b1edbc	1055	* @arg @ref LL_RI_IOSWITCH_CH4
AnnaBridge	171:3a7713b1edbc	1056	* @arg @ref LL_RI_IOSWITCH_CH5
AnnaBridge	171:3a7713b1edbc	1057	* @arg @ref LL_RI_IOSWITCH_CH6
AnnaBridge	171:3a7713b1edbc	1058	* @arg @ref LL_RI_IOSWITCH_CH7
AnnaBridge	171:3a7713b1edbc	1059	* @arg @ref LL_RI_IOSWITCH_CH8
AnnaBridge	171:3a7713b1edbc	1060	* @arg @ref LL_RI_IOSWITCH_CH9
AnnaBridge	171:3a7713b1edbc	1061	* @arg @ref LL_RI_IOSWITCH_CH10
AnnaBridge	171:3a7713b1edbc	1062	* @arg @ref LL_RI_IOSWITCH_CH11
AnnaBridge	171:3a7713b1edbc	1063	* @arg @ref LL_RI_IOSWITCH_CH12
AnnaBridge	171:3a7713b1edbc	1064	* @arg @ref LL_RI_IOSWITCH_CH13
AnnaBridge	171:3a7713b1edbc	1065	* @arg @ref LL_RI_IOSWITCH_CH14
AnnaBridge	171:3a7713b1edbc	1066	* @arg @ref LL_RI_IOSWITCH_CH15
AnnaBridge	171:3a7713b1edbc	1067	* @arg @ref LL_RI_IOSWITCH_CH18
AnnaBridge	171:3a7713b1edbc	1068	* @arg @ref LL_RI_IOSWITCH_CH19
AnnaBridge	171:3a7713b1edbc	1069	* @arg @ref LL_RI_IOSWITCH_CH20
AnnaBridge	171:3a7713b1edbc	1070	* @arg @ref LL_RI_IOSWITCH_CH21
AnnaBridge	171:3a7713b1edbc	1071	* @arg @ref LL_RI_IOSWITCH_CH22
AnnaBridge	171:3a7713b1edbc	1072	* @arg @ref LL_RI_IOSWITCH_CH23
AnnaBridge	171:3a7713b1edbc	1073	* @arg @ref LL_RI_IOSWITCH_CH24
AnnaBridge	171:3a7713b1edbc	1074	* @arg @ref LL_RI_IOSWITCH_CH25
AnnaBridge	171:3a7713b1edbc	1075	* @arg @ref LL_RI_IOSWITCH_VCOMP
AnnaBridge	171:3a7713b1edbc	1076	* @arg @ref LL_RI_IOSWITCH_CH27 (*)
AnnaBridge	171:3a7713b1edbc	1077	* @arg @ref LL_RI_IOSWITCH_CH28 (*)
AnnaBridge	171:3a7713b1edbc	1078	* @arg @ref LL_RI_IOSWITCH_CH29 (*)
AnnaBridge	171:3a7713b1edbc	1079	* @arg @ref LL_RI_IOSWITCH_CH30 (*)
AnnaBridge	171:3a7713b1edbc	1080	* @arg @ref LL_RI_IOSWITCH_CH31 (*)
AnnaBridge	171:3a7713b1edbc	1081	*
AnnaBridge	171:3a7713b1edbc	1082	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1083	* @retval None
AnnaBridge	171:3a7713b1edbc	1084	*/
AnnaBridge	171:3a7713b1edbc	1085	__STATIC_INLINE void LL_RI_CloseIOSwitchLinkedToADC(uint32_t IOSwitch)
AnnaBridge	171:3a7713b1edbc	1086	{
AnnaBridge	171:3a7713b1edbc	1087	SET_BIT(RI->ASCR1, IOSwitch);
AnnaBridge	171:3a7713b1edbc	1088	}
AnnaBridge	171:3a7713b1edbc	1089
AnnaBridge	171:3a7713b1edbc	1090	/**
AnnaBridge	171:3a7713b1edbc	1091	* @brief Open the routing interface Input Output switches linked to ADC.
AnnaBridge	171:3a7713b1edbc	1092	* @rmtoll RI_ASCR1 CH LL_RI_OpenIOSwitchLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1093	* RI_ASCR1 VCOMP LL_RI_OpenIOSwitchLinkedToADC
AnnaBridge	171:3a7713b1edbc	1094	* @param IOSwitch This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1095	* @arg @ref LL_RI_IOSWITCH_CH0
AnnaBridge	171:3a7713b1edbc	1096	* @arg @ref LL_RI_IOSWITCH_CH1
AnnaBridge	171:3a7713b1edbc	1097	* @arg @ref LL_RI_IOSWITCH_CH2
AnnaBridge	171:3a7713b1edbc	1098	* @arg @ref LL_RI_IOSWITCH_CH3
AnnaBridge	171:3a7713b1edbc	1099	* @arg @ref LL_RI_IOSWITCH_CH4
AnnaBridge	171:3a7713b1edbc	1100	* @arg @ref LL_RI_IOSWITCH_CH5
AnnaBridge	171:3a7713b1edbc	1101	* @arg @ref LL_RI_IOSWITCH_CH6
AnnaBridge	171:3a7713b1edbc	1102	* @arg @ref LL_RI_IOSWITCH_CH7
AnnaBridge	171:3a7713b1edbc	1103	* @arg @ref LL_RI_IOSWITCH_CH8
AnnaBridge	171:3a7713b1edbc	1104	* @arg @ref LL_RI_IOSWITCH_CH9
AnnaBridge	171:3a7713b1edbc	1105	* @arg @ref LL_RI_IOSWITCH_CH10
AnnaBridge	171:3a7713b1edbc	1106	* @arg @ref LL_RI_IOSWITCH_CH11
AnnaBridge	171:3a7713b1edbc	1107	* @arg @ref LL_RI_IOSWITCH_CH12
AnnaBridge	171:3a7713b1edbc	1108	* @arg @ref LL_RI_IOSWITCH_CH13
AnnaBridge	171:3a7713b1edbc	1109	* @arg @ref LL_RI_IOSWITCH_CH14
AnnaBridge	171:3a7713b1edbc	1110	* @arg @ref LL_RI_IOSWITCH_CH15
AnnaBridge	171:3a7713b1edbc	1111	* @arg @ref LL_RI_IOSWITCH_CH18
AnnaBridge	171:3a7713b1edbc	1112	* @arg @ref LL_RI_IOSWITCH_CH19
AnnaBridge	171:3a7713b1edbc	1113	* @arg @ref LL_RI_IOSWITCH_CH20
AnnaBridge	171:3a7713b1edbc	1114	* @arg @ref LL_RI_IOSWITCH_CH21
AnnaBridge	171:3a7713b1edbc	1115	* @arg @ref LL_RI_IOSWITCH_CH22
AnnaBridge	171:3a7713b1edbc	1116	* @arg @ref LL_RI_IOSWITCH_CH23
AnnaBridge	171:3a7713b1edbc	1117	* @arg @ref LL_RI_IOSWITCH_CH24
AnnaBridge	171:3a7713b1edbc	1118	* @arg @ref LL_RI_IOSWITCH_CH25
AnnaBridge	171:3a7713b1edbc	1119	* @arg @ref LL_RI_IOSWITCH_VCOMP
AnnaBridge	171:3a7713b1edbc	1120	* @arg @ref LL_RI_IOSWITCH_CH27 (*)
AnnaBridge	171:3a7713b1edbc	1121	* @arg @ref LL_RI_IOSWITCH_CH28 (*)
AnnaBridge	171:3a7713b1edbc	1122	* @arg @ref LL_RI_IOSWITCH_CH29 (*)
AnnaBridge	171:3a7713b1edbc	1123	* @arg @ref LL_RI_IOSWITCH_CH30 (*)
AnnaBridge	171:3a7713b1edbc	1124	* @arg @ref LL_RI_IOSWITCH_CH31 (*)
AnnaBridge	171:3a7713b1edbc	1125	*
AnnaBridge	171:3a7713b1edbc	1126	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1127	* @retval None
AnnaBridge	171:3a7713b1edbc	1128	*/
AnnaBridge	171:3a7713b1edbc	1129	__STATIC_INLINE void LL_RI_OpenIOSwitchLinkedToADC(uint32_t IOSwitch)
AnnaBridge	171:3a7713b1edbc	1130	{
AnnaBridge	171:3a7713b1edbc	1131	CLEAR_BIT(RI->ASCR1, IOSwitch);
AnnaBridge	171:3a7713b1edbc	1132	}
AnnaBridge	171:3a7713b1edbc	1133
AnnaBridge	171:3a7713b1edbc	1134	/**
AnnaBridge	171:3a7713b1edbc	1135	* @brief Enable the switch control mode.
AnnaBridge	171:3a7713b1edbc	1136	* @rmtoll RI_ASCR1 SCM LL_RI_EnableSwitchControlMode
AnnaBridge	171:3a7713b1edbc	1137	* @retval None
AnnaBridge	171:3a7713b1edbc	1138	*/
AnnaBridge	171:3a7713b1edbc	1139	__STATIC_INLINE void LL_RI_EnableSwitchControlMode(void)
AnnaBridge	171:3a7713b1edbc	1140	{
AnnaBridge	171:3a7713b1edbc	1141	SET_BIT(RI->ASCR1, RI_ASCR1_SCM);
AnnaBridge	171:3a7713b1edbc	1142	}
AnnaBridge	171:3a7713b1edbc	1143
AnnaBridge	171:3a7713b1edbc	1144	/**
AnnaBridge	171:3a7713b1edbc	1145	* @brief Disable the switch control mode.
AnnaBridge	171:3a7713b1edbc	1146	* @rmtoll RI_ASCR1 SCM LL_RI_DisableSwitchControlMode
AnnaBridge	171:3a7713b1edbc	1147	* @retval None
AnnaBridge	171:3a7713b1edbc	1148	*/
AnnaBridge	171:3a7713b1edbc	1149	__STATIC_INLINE void LL_RI_DisableSwitchControlMode(void)
AnnaBridge	171:3a7713b1edbc	1150	{
AnnaBridge	171:3a7713b1edbc	1151	CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM);
AnnaBridge	171:3a7713b1edbc	1152	}
AnnaBridge	171:3a7713b1edbc	1153
AnnaBridge	171:3a7713b1edbc	1154	/**
AnnaBridge	171:3a7713b1edbc	1155	* @brief Close the routing interface Input Output switches not linked to ADC.
AnnaBridge	171:3a7713b1edbc	1156	* @rmtoll RI_ASCR2 GR10_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1157	* RI_ASCR2 GR10_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1158	* RI_ASCR2 GR10_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1159	* RI_ASCR2 GR10_4 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1160	* RI_ASCR2 GR6_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1161	* RI_ASCR2 GR6_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1162	* RI_ASCR2 GR5_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1163	* RI_ASCR2 GR5_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1164	* RI_ASCR2 GR5_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1165	* RI_ASCR2 GR4_1 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1166	* RI_ASCR2 GR4_2 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1167	* RI_ASCR2 GR4_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1168	* RI_ASCR2 GR4_4 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1169	* RI_ASCR2 CH0b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1170	* RI_ASCR2 CH1b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1171	* RI_ASCR2 CH2b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1172	* RI_ASCR2 CH3b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1173	* RI_ASCR2 CH6b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1174	* RI_ASCR2 CH7b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1175	* RI_ASCR2 CH8b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1176	* RI_ASCR2 CH9b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1177	* RI_ASCR2 CH10b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1178	* RI_ASCR2 CH11b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1179	* RI_ASCR2 CH12b LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1180	* RI_ASCR2 GR6_3 LL_RI_CloseIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1181	* RI_ASCR2 GR6_4 LL_RI_CloseIOSwitchNotLinkedToADC
AnnaBridge	171:3a7713b1edbc	1182	* @param IOSwitch This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1183	* @arg @ref LL_RI_IOSWITCH_GR10_1
AnnaBridge	171:3a7713b1edbc	1184	* @arg @ref LL_RI_IOSWITCH_GR10_2
AnnaBridge	171:3a7713b1edbc	1185	* @arg @ref LL_RI_IOSWITCH_GR10_3
AnnaBridge	171:3a7713b1edbc	1186	* @arg @ref LL_RI_IOSWITCH_GR10_4
AnnaBridge	171:3a7713b1edbc	1187	* @arg @ref LL_RI_IOSWITCH_GR6_1
AnnaBridge	171:3a7713b1edbc	1188	* @arg @ref LL_RI_IOSWITCH_GR6_2
AnnaBridge	171:3a7713b1edbc	1189	* @arg @ref LL_RI_IOSWITCH_GR5_1
AnnaBridge	171:3a7713b1edbc	1190	* @arg @ref LL_RI_IOSWITCH_GR5_2
AnnaBridge	171:3a7713b1edbc	1191	* @arg @ref LL_RI_IOSWITCH_GR5_3
AnnaBridge	171:3a7713b1edbc	1192	* @arg @ref LL_RI_IOSWITCH_GR4_1
AnnaBridge	171:3a7713b1edbc	1193	* @arg @ref LL_RI_IOSWITCH_GR4_2
AnnaBridge	171:3a7713b1edbc	1194	* @arg @ref LL_RI_IOSWITCH_GR4_3
AnnaBridge	171:3a7713b1edbc	1195	* @arg @ref LL_RI_IOSWITCH_CH0b (*)
AnnaBridge	171:3a7713b1edbc	1196	* @arg @ref LL_RI_IOSWITCH_CH1b (*)
AnnaBridge	171:3a7713b1edbc	1197	* @arg @ref LL_RI_IOSWITCH_CH2b (*)
AnnaBridge	171:3a7713b1edbc	1198	* @arg @ref LL_RI_IOSWITCH_CH3b (*)
AnnaBridge	171:3a7713b1edbc	1199	* @arg @ref LL_RI_IOSWITCH_CH6b (*)
AnnaBridge	171:3a7713b1edbc	1200	* @arg @ref LL_RI_IOSWITCH_CH7b (*)
AnnaBridge	171:3a7713b1edbc	1201	* @arg @ref LL_RI_IOSWITCH_CH8b (*)
AnnaBridge	171:3a7713b1edbc	1202	* @arg @ref LL_RI_IOSWITCH_CH9b (*)
AnnaBridge	171:3a7713b1edbc	1203	* @arg @ref LL_RI_IOSWITCH_CH10b (*)
AnnaBridge	171:3a7713b1edbc	1204	* @arg @ref LL_RI_IOSWITCH_CH11b (*)
AnnaBridge	171:3a7713b1edbc	1205	* @arg @ref LL_RI_IOSWITCH_CH12b (*)
AnnaBridge	171:3a7713b1edbc	1206	* @arg @ref LL_RI_IOSWITCH_GR6_3
AnnaBridge	171:3a7713b1edbc	1207	* @arg @ref LL_RI_IOSWITCH_GR6_4
AnnaBridge	171:3a7713b1edbc	1208	*
AnnaBridge	171:3a7713b1edbc	1209	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1210	* @retval None
AnnaBridge	171:3a7713b1edbc	1211	*/
AnnaBridge	171:3a7713b1edbc	1212	__STATIC_INLINE void LL_RI_CloseIOSwitchNotLinkedToADC(uint32_t IOSwitch)
AnnaBridge	171:3a7713b1edbc	1213	{
AnnaBridge	171:3a7713b1edbc	1214	SET_BIT(RI->ASCR2, IOSwitch);
AnnaBridge	171:3a7713b1edbc	1215	}
AnnaBridge	171:3a7713b1edbc	1216
AnnaBridge	171:3a7713b1edbc	1217	/**
AnnaBridge	171:3a7713b1edbc	1218	* @brief Open the routing interface Input Output switches not linked to ADC.
AnnaBridge	171:3a7713b1edbc	1219	* @rmtoll RI_ASCR2 GR10_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1220	* RI_ASCR2 GR10_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1221	* RI_ASCR2 GR10_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1222	* RI_ASCR2 GR10_4 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1223	* RI_ASCR2 GR6_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1224	* RI_ASCR2 GR6_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1225	* RI_ASCR2 GR5_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1226	* RI_ASCR2 GR5_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1227	* RI_ASCR2 GR5_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1228	* RI_ASCR2 GR4_1 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1229	* RI_ASCR2 GR4_2 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1230	* RI_ASCR2 GR4_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1231	* RI_ASCR2 GR4_4 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1232	* RI_ASCR2 CH0b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1233	* RI_ASCR2 CH1b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1234	* RI_ASCR2 CH2b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1235	* RI_ASCR2 CH3b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1236	* RI_ASCR2 CH6b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1237	* RI_ASCR2 CH7b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1238	* RI_ASCR2 CH8b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1239	* RI_ASCR2 CH9b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1240	* RI_ASCR2 CH10b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1241	* RI_ASCR2 CH11b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1242	* RI_ASCR2 CH12b LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1243	* RI_ASCR2 GR6_3 LL_RI_OpenIOSwitchNotLinkedToADC\n
AnnaBridge	171:3a7713b1edbc	1244	* RI_ASCR2 GR6_4 LL_RI_OpenIOSwitchNotLinkedToADC
AnnaBridge	171:3a7713b1edbc	1245	* @param IOSwitch This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1246	* @arg @ref LL_RI_IOSWITCH_GR10_1
AnnaBridge	171:3a7713b1edbc	1247	* @arg @ref LL_RI_IOSWITCH_GR10_2
AnnaBridge	171:3a7713b1edbc	1248	* @arg @ref LL_RI_IOSWITCH_GR10_3
AnnaBridge	171:3a7713b1edbc	1249	* @arg @ref LL_RI_IOSWITCH_GR10_4
AnnaBridge	171:3a7713b1edbc	1250	* @arg @ref LL_RI_IOSWITCH_GR6_1
AnnaBridge	171:3a7713b1edbc	1251	* @arg @ref LL_RI_IOSWITCH_GR6_2
AnnaBridge	171:3a7713b1edbc	1252	* @arg @ref LL_RI_IOSWITCH_GR5_1
AnnaBridge	171:3a7713b1edbc	1253	* @arg @ref LL_RI_IOSWITCH_GR5_2
AnnaBridge	171:3a7713b1edbc	1254	* @arg @ref LL_RI_IOSWITCH_GR5_3
AnnaBridge	171:3a7713b1edbc	1255	* @arg @ref LL_RI_IOSWITCH_GR4_1
AnnaBridge	171:3a7713b1edbc	1256	* @arg @ref LL_RI_IOSWITCH_GR4_2
AnnaBridge	171:3a7713b1edbc	1257	* @arg @ref LL_RI_IOSWITCH_GR4_3
AnnaBridge	171:3a7713b1edbc	1258	* @arg @ref LL_RI_IOSWITCH_CH0b (*)
AnnaBridge	171:3a7713b1edbc	1259	* @arg @ref LL_RI_IOSWITCH_CH1b (*)
AnnaBridge	171:3a7713b1edbc	1260	* @arg @ref LL_RI_IOSWITCH_CH2b (*)
AnnaBridge	171:3a7713b1edbc	1261	* @arg @ref LL_RI_IOSWITCH_CH3b (*)
AnnaBridge	171:3a7713b1edbc	1262	* @arg @ref LL_RI_IOSWITCH_CH6b (*)
AnnaBridge	171:3a7713b1edbc	1263	* @arg @ref LL_RI_IOSWITCH_CH7b (*)
AnnaBridge	171:3a7713b1edbc	1264	* @arg @ref LL_RI_IOSWITCH_CH8b (*)
AnnaBridge	171:3a7713b1edbc	1265	* @arg @ref LL_RI_IOSWITCH_CH9b (*)
AnnaBridge	171:3a7713b1edbc	1266	* @arg @ref LL_RI_IOSWITCH_CH10b (*)
AnnaBridge	171:3a7713b1edbc	1267	* @arg @ref LL_RI_IOSWITCH_CH11b (*)
AnnaBridge	171:3a7713b1edbc	1268	* @arg @ref LL_RI_IOSWITCH_CH12b (*)
AnnaBridge	171:3a7713b1edbc	1269	* @arg @ref LL_RI_IOSWITCH_GR6_3
AnnaBridge	171:3a7713b1edbc	1270	* @arg @ref LL_RI_IOSWITCH_GR6_4
AnnaBridge	171:3a7713b1edbc	1271	*
AnnaBridge	171:3a7713b1edbc	1272	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1273	* @retval None
AnnaBridge	171:3a7713b1edbc	1274	*/
AnnaBridge	171:3a7713b1edbc	1275	__STATIC_INLINE void LL_RI_OpenIOSwitchNotLinkedToADC(uint32_t IOSwitch)
AnnaBridge	171:3a7713b1edbc	1276	{
AnnaBridge	171:3a7713b1edbc	1277	CLEAR_BIT(RI->ASCR2, IOSwitch);
AnnaBridge	171:3a7713b1edbc	1278	}
AnnaBridge	171:3a7713b1edbc	1279
AnnaBridge	171:3a7713b1edbc	1280	/**
AnnaBridge	171:3a7713b1edbc	1281	* @brief Enable Hysteresis of the input schmitt triger of the port X
AnnaBridge	171:3a7713b1edbc	1282	* @rmtoll RI_HYSCR1 PA LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1283	* RI_HYSCR1 PB LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1284	* RI_HYSCR1 PC LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1285	* RI_HYSCR1 PD LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1286	* RI_HYSCR1 PE LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1287	* RI_HYSCR1 PF LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1288	* RI_HYSCR1 PG LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1289	* RI_HYSCR2 PA LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1290	* RI_HYSCR2 PB LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1291	* RI_HYSCR2 PC LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1292	* RI_HYSCR2 PD LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1293	* RI_HYSCR2 PE LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1294	* RI_HYSCR2 PF LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1295	* RI_HYSCR2 PG LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1296	* RI_HYSCR3 PA LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1297	* RI_HYSCR3 PB LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1298	* RI_HYSCR3 PC LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1299	* RI_HYSCR3 PD LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1300	* RI_HYSCR3 PE LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1301	* RI_HYSCR3 PF LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1302	* RI_HYSCR3 PG LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1303	* RI_HYSCR4 PA LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1304	* RI_HYSCR4 PB LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1305	* RI_HYSCR4 PC LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1306	* RI_HYSCR4 PD LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1307	* RI_HYSCR4 PE LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1308	* RI_HYSCR4 PF LL_RI_EnableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1309	* RI_HYSCR4 PG LL_RI_EnableHysteresis
AnnaBridge	171:3a7713b1edbc	1310	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1311	* @arg @ref LL_RI_HSYTERESIS_PORT_A
AnnaBridge	171:3a7713b1edbc	1312	* @arg @ref LL_RI_HSYTERESIS_PORT_B
AnnaBridge	171:3a7713b1edbc	1313	* @arg @ref LL_RI_HSYTERESIS_PORT_C
AnnaBridge	171:3a7713b1edbc	1314	* @arg @ref LL_RI_HSYTERESIS_PORT_D
AnnaBridge	171:3a7713b1edbc	1315	* @arg @ref LL_RI_HSYTERESIS_PORT_E (*)
AnnaBridge	171:3a7713b1edbc	1316	* @arg @ref LL_RI_HSYTERESIS_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1317	* @arg @ref LL_RI_HSYTERESIS_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1318	*
AnnaBridge	171:3a7713b1edbc	1319	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1320	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1321	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1322	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1323	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1324	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1325	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1326	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1327	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1328	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1329	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1330	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1331	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1332	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1333	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1334	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1335	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1336	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1337	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1338	* @retval None
AnnaBridge	171:3a7713b1edbc	1339	*/
AnnaBridge	171:3a7713b1edbc	1340	__STATIC_INLINE void LL_RI_EnableHysteresis(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1341	{
AnnaBridge	171:3a7713b1edbc	1342	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->HYSCR1) + (Port >> 1));
AnnaBridge	171:3a7713b1edbc	1343	CLEAR_BIT(reg, Pin << (16 (Port & 1)));
AnnaBridge	171:3a7713b1edbc	1344	}
AnnaBridge	171:3a7713b1edbc	1345
AnnaBridge	171:3a7713b1edbc	1346	/**
AnnaBridge	171:3a7713b1edbc	1347	* @brief Disable Hysteresis of the input schmitt triger of the port X
AnnaBridge	171:3a7713b1edbc	1348	* @rmtoll RI_HYSCR1 PA LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1349	* RI_HYSCR1 PB LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1350	* RI_HYSCR1 PC LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1351	* RI_HYSCR1 PD LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1352	* RI_HYSCR1 PE LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1353	* RI_HYSCR1 PF LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1354	* RI_HYSCR1 PG LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1355	* RI_HYSCR2 PA LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1356	* RI_HYSCR2 PB LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1357	* RI_HYSCR2 PC LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1358	* RI_HYSCR2 PD LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1359	* RI_HYSCR2 PE LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1360	* RI_HYSCR2 PF LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1361	* RI_HYSCR2 PG LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1362	* RI_HYSCR3 PA LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1363	* RI_HYSCR3 PB LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1364	* RI_HYSCR3 PC LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1365	* RI_HYSCR3 PD LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1366	* RI_HYSCR3 PE LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1367	* RI_HYSCR3 PF LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1368	* RI_HYSCR3 PG LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1369	* RI_HYSCR4 PA LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1370	* RI_HYSCR4 PB LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1371	* RI_HYSCR4 PC LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1372	* RI_HYSCR4 PD LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1373	* RI_HYSCR4 PE LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1374	* RI_HYSCR4 PF LL_RI_DisableHysteresis\n
AnnaBridge	171:3a7713b1edbc	1375	* RI_HYSCR4 PG LL_RI_DisableHysteresis
AnnaBridge	171:3a7713b1edbc	1376	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1377	* @arg @ref LL_RI_HSYTERESIS_PORT_A
AnnaBridge	171:3a7713b1edbc	1378	* @arg @ref LL_RI_HSYTERESIS_PORT_B
AnnaBridge	171:3a7713b1edbc	1379	* @arg @ref LL_RI_HSYTERESIS_PORT_C
AnnaBridge	171:3a7713b1edbc	1380	* @arg @ref LL_RI_HSYTERESIS_PORT_D
AnnaBridge	171:3a7713b1edbc	1381	* @arg @ref LL_RI_HSYTERESIS_PORT_E (*)
AnnaBridge	171:3a7713b1edbc	1382	* @arg @ref LL_RI_HSYTERESIS_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1383	* @arg @ref LL_RI_HSYTERESIS_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1384	*
AnnaBridge	171:3a7713b1edbc	1385	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1386	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1387	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1388	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1389	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1390	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1391	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1392	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1393	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1394	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1395	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1396	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1397	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1398	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1399	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1400	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1401	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1402	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1403	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1404	* @retval None
AnnaBridge	171:3a7713b1edbc	1405	*/
AnnaBridge	171:3a7713b1edbc	1406	__STATIC_INLINE void LL_RI_DisableHysteresis(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1407	{
AnnaBridge	171:3a7713b1edbc	1408	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->HYSCR1) + ((Port >> 1) << 2));
AnnaBridge	171:3a7713b1edbc	1409	SET_BIT(reg, Pin << (16 (Port & 1)));
AnnaBridge	171:3a7713b1edbc	1410	}
AnnaBridge	171:3a7713b1edbc	1411
AnnaBridge	171:3a7713b1edbc	1412	#if defined(RI_ASMR1_PA)
AnnaBridge	171:3a7713b1edbc	1413	/**
AnnaBridge	171:3a7713b1edbc	1414	* @brief Control analog switches of port X through the ADC interface or RI_ASCRx registers.
AnnaBridge	171:3a7713b1edbc	1415	* @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1416	* RI_ASMR1 PB LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1417	* RI_ASMR1 PC LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1418	* RI_ASMR1 PF LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1419	* RI_ASMR1 PG LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1420	* RI_ASMR2 PA LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1421	* RI_ASMR2 PB LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1422	* RI_ASMR2 PC LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1423	* RI_ASMR2 PF LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1424	* RI_ASMR2 PG LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1425	* RI_ASMR3 PA LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1426	* RI_ASMR3 PB LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1427	* RI_ASMR3 PC LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1428	* RI_ASMR3 PF LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1429	* RI_ASMR3 PG LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1430	* RI_ASMR4 PA LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1431	* RI_ASMR4 PB LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1432	* RI_ASMR4 PC LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1433	* RI_ASMR4 PF LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1434	* RI_ASMR4 PG LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1435	* RI_ASMR5 PA LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1436	* RI_ASMR5 PB LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1437	* RI_ASMR5 PC LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1438	* RI_ASMR5 PF LL_RI_ControlSwitchByADC\n
AnnaBridge	171:3a7713b1edbc	1439	* RI_ASMR5 PG LL_RI_ControlSwitchByADC
AnnaBridge	171:3a7713b1edbc	1440	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1441	* @arg @ref LL_RI_PORT_A
AnnaBridge	171:3a7713b1edbc	1442	* @arg @ref LL_RI_PORT_B
AnnaBridge	171:3a7713b1edbc	1443	* @arg @ref LL_RI_PORT_C
AnnaBridge	171:3a7713b1edbc	1444	* @arg @ref LL_RI_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1445	* @arg @ref LL_RI_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1446	*
AnnaBridge	171:3a7713b1edbc	1447	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1448	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1449	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1450	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1451	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1452	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1453	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1454	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1455	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1456	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1457	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1458	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1459	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1460	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1461	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1462	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1463	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1464	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1465	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1466	* @retval None
AnnaBridge	171:3a7713b1edbc	1467	*/
AnnaBridge	171:3a7713b1edbc	1468	__STATIC_INLINE void LL_RI_ControlSwitchByADC(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1469	{
AnnaBridge	171:3a7713b1edbc	1470	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2));
AnnaBridge	171:3a7713b1edbc	1471	CLEAR_BIT(*reg, Pin);
AnnaBridge	171:3a7713b1edbc	1472	}
AnnaBridge	171:3a7713b1edbc	1473	#endif /* RI_ASMR1_PA */
AnnaBridge	171:3a7713b1edbc	1474
AnnaBridge	171:3a7713b1edbc	1475	#if defined(RI_ASMR1_PA)
AnnaBridge	171:3a7713b1edbc	1476	/**
AnnaBridge	171:3a7713b1edbc	1477	* @brief Control analog switches of port X by the timer OC.
AnnaBridge	171:3a7713b1edbc	1478	* @rmtoll RI_ASMR1 PA LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1479	* RI_ASMR1 PB LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1480	* RI_ASMR1 PC LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1481	* RI_ASMR1 PF LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1482	* RI_ASMR1 PG LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1483	* RI_ASMR2 PA LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1484	* RI_ASMR2 PB LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1485	* RI_ASMR2 PC LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1486	* RI_ASMR2 PF LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1487	* RI_ASMR2 PG LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1488	* RI_ASMR3 PA LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1489	* RI_ASMR3 PB LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1490	* RI_ASMR3 PC LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1491	* RI_ASMR3 PF LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1492	* RI_ASMR3 PG LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1493	* RI_ASMR4 PA LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1494	* RI_ASMR4 PB LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1495	* RI_ASMR4 PC LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1496	* RI_ASMR4 PF LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1497	* RI_ASMR4 PG LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1498	* RI_ASMR5 PA LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1499	* RI_ASMR5 PB LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1500	* RI_ASMR5 PC LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1501	* RI_ASMR5 PF LL_RI_ControlSwitchByTIM\n
AnnaBridge	171:3a7713b1edbc	1502	* RI_ASMR5 PG LL_RI_ControlSwitchByTIM
AnnaBridge	171:3a7713b1edbc	1503	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1504	* @arg @ref LL_RI_PORT_A
AnnaBridge	171:3a7713b1edbc	1505	* @arg @ref LL_RI_PORT_B
AnnaBridge	171:3a7713b1edbc	1506	* @arg @ref LL_RI_PORT_C
AnnaBridge	171:3a7713b1edbc	1507	* @arg @ref LL_RI_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1508	* @arg @ref LL_RI_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1509	*
AnnaBridge	171:3a7713b1edbc	1510	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1511	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1512	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1513	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1514	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1515	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1516	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1517	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1518	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1519	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1520	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1521	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1522	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1523	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1524	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1525	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1526	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1527	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1528	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1529	* @retval None
AnnaBridge	171:3a7713b1edbc	1530	*/
AnnaBridge	171:3a7713b1edbc	1531	__STATIC_INLINE void LL_RI_ControlSwitchByTIM(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1532	{
AnnaBridge	171:3a7713b1edbc	1533	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->ASMR1) + ((Port * 3U) << 2));
AnnaBridge	171:3a7713b1edbc	1534	SET_BIT(*reg, Pin);
AnnaBridge	171:3a7713b1edbc	1535	}
AnnaBridge	171:3a7713b1edbc	1536	#endif /* RI_ASMR1_PA */
AnnaBridge	171:3a7713b1edbc	1537
AnnaBridge	171:3a7713b1edbc	1538	#if defined(RI_CMR1_PA)
AnnaBridge	171:3a7713b1edbc	1539	/**
AnnaBridge	171:3a7713b1edbc	1540	* @brief Mask the input of port X during the capacitive sensing acquisition.
AnnaBridge	171:3a7713b1edbc	1541	* @rmtoll RI_CMR1 PA LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1542	* RI_CMR1 PB LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1543	* RI_CMR1 PC LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1544	* RI_CMR1 PF LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1545	* RI_CMR1 PG LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1546	* RI_CMR2 PA LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1547	* RI_CMR2 PB LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1548	* RI_CMR2 PC LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1549	* RI_CMR2 PF LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1550	* RI_CMR2 PG LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1551	* RI_CMR3 PA LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1552	* RI_CMR3 PB LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1553	* RI_CMR3 PC LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1554	* RI_CMR3 PF LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1555	* RI_CMR3 PG LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1556	* RI_CMR4 PA LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1557	* RI_CMR4 PB LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1558	* RI_CMR4 PC LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1559	* RI_CMR4 PF LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1560	* RI_CMR4 PG LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1561	* RI_CMR5 PA LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1562	* RI_CMR5 PB LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1563	* RI_CMR5 PC LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1564	* RI_CMR5 PF LL_RI_MaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1565	* RI_CMR5 PG LL_RI_MaskChannelDuringAcquisition
AnnaBridge	171:3a7713b1edbc	1566	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1567	* @arg @ref LL_RI_PORT_A
AnnaBridge	171:3a7713b1edbc	1568	* @arg @ref LL_RI_PORT_B
AnnaBridge	171:3a7713b1edbc	1569	* @arg @ref LL_RI_PORT_C
AnnaBridge	171:3a7713b1edbc	1570	* @arg @ref LL_RI_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1571	* @arg @ref LL_RI_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1572	*
AnnaBridge	171:3a7713b1edbc	1573	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1574	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1575	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1576	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1577	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1578	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1579	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1580	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1581	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1582	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1583	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1584	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1585	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1586	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1587	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1588	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1589	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1590	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1591	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1592	* @retval None
AnnaBridge	171:3a7713b1edbc	1593	*/
AnnaBridge	171:3a7713b1edbc	1594	__STATIC_INLINE void LL_RI_MaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1595	{
AnnaBridge	171:3a7713b1edbc	1596	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2));
AnnaBridge	171:3a7713b1edbc	1597	CLEAR_BIT(*reg, Pin);
AnnaBridge	171:3a7713b1edbc	1598	}
AnnaBridge	171:3a7713b1edbc	1599	#endif /* RI_CMR1_PA */
AnnaBridge	171:3a7713b1edbc	1600
AnnaBridge	171:3a7713b1edbc	1601	#if defined(RI_CMR1_PA)
AnnaBridge	171:3a7713b1edbc	1602	/**
AnnaBridge	171:3a7713b1edbc	1603	* @brief Unmask the input of port X during the capacitive sensing acquisition.
AnnaBridge	171:3a7713b1edbc	1604	* @rmtoll RI_CMR1 PA LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1605	* RI_CMR1 PB LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1606	* RI_CMR1 PC LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1607	* RI_CMR1 PF LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1608	* RI_CMR1 PG LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1609	* RI_CMR2 PA LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1610	* RI_CMR2 PB LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1611	* RI_CMR2 PC LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1612	* RI_CMR2 PF LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1613	* RI_CMR2 PG LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1614	* RI_CMR3 PA LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1615	* RI_CMR3 PB LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1616	* RI_CMR3 PC LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1617	* RI_CMR3 PF LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1618	* RI_CMR3 PG LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1619	* RI_CMR4 PA LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1620	* RI_CMR4 PB LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1621	* RI_CMR4 PC LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1622	* RI_CMR4 PF LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1623	* RI_CMR4 PG LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1624	* RI_CMR5 PA LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1625	* RI_CMR5 PB LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1626	* RI_CMR5 PC LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1627	* RI_CMR5 PF LL_RI_UnmaskChannelDuringAcquisition\n
AnnaBridge	171:3a7713b1edbc	1628	* RI_CMR5 PG LL_RI_UnmaskChannelDuringAcquisition
AnnaBridge	171:3a7713b1edbc	1629	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1630	* @arg @ref LL_RI_PORT_A
AnnaBridge	171:3a7713b1edbc	1631	* @arg @ref LL_RI_PORT_B
AnnaBridge	171:3a7713b1edbc	1632	* @arg @ref LL_RI_PORT_C
AnnaBridge	171:3a7713b1edbc	1633	* @arg @ref LL_RI_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1634	* @arg @ref LL_RI_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1635	*
AnnaBridge	171:3a7713b1edbc	1636	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1637	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1638	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1639	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1640	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1641	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1642	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1643	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1644	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1645	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1646	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1647	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1648	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1649	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1650	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1651	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1652	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1653	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1654	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1655	* @retval None
AnnaBridge	171:3a7713b1edbc	1656	*/
AnnaBridge	171:3a7713b1edbc	1657	__STATIC_INLINE void LL_RI_UnmaskChannelDuringAcquisition(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1658	{
AnnaBridge	171:3a7713b1edbc	1659	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->CMR1) + ((Port * 3U) << 2));
AnnaBridge	171:3a7713b1edbc	1660	SET_BIT(*reg, Pin);
AnnaBridge	171:3a7713b1edbc	1661	}
AnnaBridge	171:3a7713b1edbc	1662	#endif /* RI_CMR1_PA */
AnnaBridge	171:3a7713b1edbc	1663
AnnaBridge	171:3a7713b1edbc	1664	#if defined(RI_CICR1_PA)
AnnaBridge	171:3a7713b1edbc	1665	/**
AnnaBridge	171:3a7713b1edbc	1666	* @brief Identify channel for timer input capture
AnnaBridge	171:3a7713b1edbc	1667	* @rmtoll RI_CICR1 PA LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1668	* RI_CICR1 PB LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1669	* RI_CICR1 PC LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1670	* RI_CICR1 PF LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1671	* RI_CICR1 PG LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1672	* RI_CICR2 PA LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1673	* RI_CICR2 PB LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1674	* RI_CICR2 PC LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1675	* RI_CICR2 PF LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1676	* RI_CICR2 PG LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1677	* RI_CICR3 PA LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1678	* RI_CICR3 PB LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1679	* RI_CICR3 PC LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1680	* RI_CICR3 PF LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1681	* RI_CICR3 PG LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1682	* RI_CICR4 PA LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1683	* RI_CICR4 PB LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1684	* RI_CICR4 PC LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1685	* RI_CICR4 PF LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1686	* RI_CICR4 PG LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1687	* RI_CICR5 PA LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1688	* RI_CICR5 PB LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1689	* RI_CICR5 PC LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1690	* RI_CICR5 PF LL_RI_IdentifyChannelIO\n
AnnaBridge	171:3a7713b1edbc	1691	* RI_CICR5 PG LL_RI_IdentifyChannelIO
AnnaBridge	171:3a7713b1edbc	1692	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1693	* @arg @ref LL_RI_PORT_A
AnnaBridge	171:3a7713b1edbc	1694	* @arg @ref LL_RI_PORT_B
AnnaBridge	171:3a7713b1edbc	1695	* @arg @ref LL_RI_PORT_C
AnnaBridge	171:3a7713b1edbc	1696	* @arg @ref LL_RI_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1697	* @arg @ref LL_RI_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1698	*
AnnaBridge	171:3a7713b1edbc	1699	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1700	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1701	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1702	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1703	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1704	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1705	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1706	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1707	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1708	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1709	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1710	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1711	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1712	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1713	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1714	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1715	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1716	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1717	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1718	* @retval None
AnnaBridge	171:3a7713b1edbc	1719	*/
AnnaBridge	171:3a7713b1edbc	1720	__STATIC_INLINE void LL_RI_IdentifyChannelIO(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1721	{
AnnaBridge	171:3a7713b1edbc	1722	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2));
AnnaBridge	171:3a7713b1edbc	1723	CLEAR_BIT(*reg, Pin);
AnnaBridge	171:3a7713b1edbc	1724	}
AnnaBridge	171:3a7713b1edbc	1725	#endif /* RI_CICR1_PA */
AnnaBridge	171:3a7713b1edbc	1726
AnnaBridge	171:3a7713b1edbc	1727	#if defined(RI_CICR1_PA)
AnnaBridge	171:3a7713b1edbc	1728	/**
AnnaBridge	171:3a7713b1edbc	1729	* @brief Identify sampling capacitor for timer input capture
AnnaBridge	171:3a7713b1edbc	1730	* @rmtoll RI_CICR1 PA LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1731	* RI_CICR1 PB LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1732	* RI_CICR1 PC LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1733	* RI_CICR1 PF LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1734	* RI_CICR1 PG LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1735	* RI_CICR2 PA LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1736	* RI_CICR2 PB LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1737	* RI_CICR2 PC LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1738	* RI_CICR2 PF LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1739	* RI_CICR2 PG LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1740	* RI_CICR3 PA LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1741	* RI_CICR3 PB LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1742	* RI_CICR3 PC LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1743	* RI_CICR3 PF LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1744	* RI_CICR3 PG LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1745	* RI_CICR4 PA LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1746	* RI_CICR4 PB LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1747	* RI_CICR4 PC LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1748	* RI_CICR4 PF LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1749	* RI_CICR4 PG LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1750	* RI_CICR5 PA LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1751	* RI_CICR5 PB LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1752	* RI_CICR5 PC LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1753	* RI_CICR5 PF LL_RI_IdentifySamplingCapacitorIO\n
AnnaBridge	171:3a7713b1edbc	1754	* RI_CICR5 PG LL_RI_IdentifySamplingCapacitorIO
AnnaBridge	171:3a7713b1edbc	1755	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1756	* @arg @ref LL_RI_PORT_A
AnnaBridge	171:3a7713b1edbc	1757	* @arg @ref LL_RI_PORT_B
AnnaBridge	171:3a7713b1edbc	1758	* @arg @ref LL_RI_PORT_C
AnnaBridge	171:3a7713b1edbc	1759	* @arg @ref LL_RI_PORT_F (*)
AnnaBridge	171:3a7713b1edbc	1760	* @arg @ref LL_RI_PORT_G (*)
AnnaBridge	171:3a7713b1edbc	1761	*
AnnaBridge	171:3a7713b1edbc	1762	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	1763	* @param Pin This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1764	* @arg @ref LL_RI_PIN_0
AnnaBridge	171:3a7713b1edbc	1765	* @arg @ref LL_RI_PIN_1
AnnaBridge	171:3a7713b1edbc	1766	* @arg @ref LL_RI_PIN_2
AnnaBridge	171:3a7713b1edbc	1767	* @arg @ref LL_RI_PIN_3
AnnaBridge	171:3a7713b1edbc	1768	* @arg @ref LL_RI_PIN_4
AnnaBridge	171:3a7713b1edbc	1769	* @arg @ref LL_RI_PIN_5
AnnaBridge	171:3a7713b1edbc	1770	* @arg @ref LL_RI_PIN_6
AnnaBridge	171:3a7713b1edbc	1771	* @arg @ref LL_RI_PIN_7
AnnaBridge	171:3a7713b1edbc	1772	* @arg @ref LL_RI_PIN_8
AnnaBridge	171:3a7713b1edbc	1773	* @arg @ref LL_RI_PIN_9
AnnaBridge	171:3a7713b1edbc	1774	* @arg @ref LL_RI_PIN_10
AnnaBridge	171:3a7713b1edbc	1775	* @arg @ref LL_RI_PIN_11
AnnaBridge	171:3a7713b1edbc	1776	* @arg @ref LL_RI_PIN_12
AnnaBridge	171:3a7713b1edbc	1777	* @arg @ref LL_RI_PIN_13
AnnaBridge	171:3a7713b1edbc	1778	* @arg @ref LL_RI_PIN_14
AnnaBridge	171:3a7713b1edbc	1779	* @arg @ref LL_RI_PIN_15
AnnaBridge	171:3a7713b1edbc	1780	* @arg @ref LL_RI_PIN_ALL
AnnaBridge	171:3a7713b1edbc	1781	* @retval None
AnnaBridge	171:3a7713b1edbc	1782	*/
AnnaBridge	171:3a7713b1edbc	1783	__STATIC_INLINE void LL_RI_IdentifySamplingCapacitorIO(uint32_t Port, uint32_t Pin)
AnnaBridge	171:3a7713b1edbc	1784	{
AnnaBridge	171:3a7713b1edbc	1785	__IO uint32_t reg = (__IO uint32_t )(uint32_t)((uint32_t)(&RI->CICR1) + ((Port * 3U) << 2));
AnnaBridge	171:3a7713b1edbc	1786	SET_BIT(*reg, Pin);
AnnaBridge	171:3a7713b1edbc	1787	}
AnnaBridge	171:3a7713b1edbc	1788	#endif /* RI_CICR1_PA */
AnnaBridge	171:3a7713b1edbc	1789
AnnaBridge	171:3a7713b1edbc	1790	/**
AnnaBridge	171:3a7713b1edbc	1791	* @}
AnnaBridge	171:3a7713b1edbc	1792	*/
AnnaBridge	171:3a7713b1edbc	1793
AnnaBridge	171:3a7713b1edbc	1794	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
AnnaBridge	171:3a7713b1edbc	1795	* @{
AnnaBridge	171:3a7713b1edbc	1796	*/
AnnaBridge	171:3a7713b1edbc	1797
AnnaBridge	171:3a7713b1edbc	1798	/**
AnnaBridge	171:3a7713b1edbc	1799	* @brief Set FLASH Latency
AnnaBridge	171:3a7713b1edbc	1800	* @note Latetency can be modified only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
AnnaBridge	171:3a7713b1edbc	1801	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
AnnaBridge	171:3a7713b1edbc	1802	* @param Latency This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1803	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	171:3a7713b1edbc	1804	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	171:3a7713b1edbc	1805	* @retval None
AnnaBridge	171:3a7713b1edbc	1806	*/
AnnaBridge	171:3a7713b1edbc	1807	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
AnnaBridge	171:3a7713b1edbc	1808	{
AnnaBridge	171:3a7713b1edbc	1809	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
AnnaBridge	171:3a7713b1edbc	1810	}
AnnaBridge	171:3a7713b1edbc	1811
AnnaBridge	171:3a7713b1edbc	1812	/**
AnnaBridge	171:3a7713b1edbc	1813	* @brief Get FLASH Latency
AnnaBridge	171:3a7713b1edbc	1814	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
AnnaBridge	171:3a7713b1edbc	1815	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1816	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	171:3a7713b1edbc	1817	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	171:3a7713b1edbc	1818	*/
AnnaBridge	171:3a7713b1edbc	1819	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
AnnaBridge	171:3a7713b1edbc	1820	{
AnnaBridge	171:3a7713b1edbc	1821	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
AnnaBridge	171:3a7713b1edbc	1822	}
AnnaBridge	171:3a7713b1edbc	1823
AnnaBridge	171:3a7713b1edbc	1824	/**
AnnaBridge	171:3a7713b1edbc	1825	* @brief Enable Prefetch
AnnaBridge	171:3a7713b1edbc	1826	* @note Prefetch can be enabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
AnnaBridge	171:3a7713b1edbc	1827	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
AnnaBridge	171:3a7713b1edbc	1828	* @retval None
AnnaBridge	171:3a7713b1edbc	1829	*/
AnnaBridge	171:3a7713b1edbc	1830	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
AnnaBridge	171:3a7713b1edbc	1831	{
AnnaBridge	171:3a7713b1edbc	1832	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
AnnaBridge	171:3a7713b1edbc	1833	}
AnnaBridge	171:3a7713b1edbc	1834
AnnaBridge	171:3a7713b1edbc	1835	/**
AnnaBridge	171:3a7713b1edbc	1836	* @brief Disable Prefetch
AnnaBridge	171:3a7713b1edbc	1837	* @note Prefetch can be disabled only when ACC64 is set. (through function @ref LL_FLASH_Enable64bitAccess)
AnnaBridge	171:3a7713b1edbc	1838	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
AnnaBridge	171:3a7713b1edbc	1839	* @retval None
AnnaBridge	171:3a7713b1edbc	1840	*/
AnnaBridge	171:3a7713b1edbc	1841	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
AnnaBridge	171:3a7713b1edbc	1842	{
AnnaBridge	171:3a7713b1edbc	1843	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
AnnaBridge	171:3a7713b1edbc	1844	}
AnnaBridge	171:3a7713b1edbc	1845
AnnaBridge	171:3a7713b1edbc	1846	/**
AnnaBridge	171:3a7713b1edbc	1847	* @brief Check if Prefetch buffer is enabled
AnnaBridge	171:3a7713b1edbc	1848	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
AnnaBridge	171:3a7713b1edbc	1849	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1850	*/
AnnaBridge	171:3a7713b1edbc	1851	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
AnnaBridge	171:3a7713b1edbc	1852	{
AnnaBridge	171:3a7713b1edbc	1853	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
AnnaBridge	171:3a7713b1edbc	1854	}
AnnaBridge	171:3a7713b1edbc	1855
AnnaBridge	171:3a7713b1edbc	1856	/**
AnnaBridge	171:3a7713b1edbc	1857	* @brief Enable 64-bit access
AnnaBridge	171:3a7713b1edbc	1858	* @rmtoll FLASH_ACR ACC64 LL_FLASH_Enable64bitAccess
AnnaBridge	171:3a7713b1edbc	1859	* @retval None
AnnaBridge	171:3a7713b1edbc	1860	*/
AnnaBridge	171:3a7713b1edbc	1861	__STATIC_INLINE void LL_FLASH_Enable64bitAccess(void)
AnnaBridge	171:3a7713b1edbc	1862	{
AnnaBridge	171:3a7713b1edbc	1863	SET_BIT(FLASH->ACR, FLASH_ACR_ACC64);
AnnaBridge	171:3a7713b1edbc	1864	}
AnnaBridge	171:3a7713b1edbc	1865
AnnaBridge	171:3a7713b1edbc	1866	/**
AnnaBridge	171:3a7713b1edbc	1867	* @brief Disable 64-bit access
AnnaBridge	171:3a7713b1edbc	1868	* @rmtoll FLASH_ACR ACC64 LL_FLASH_Disable64bitAccess
AnnaBridge	171:3a7713b1edbc	1869	* @retval None
AnnaBridge	171:3a7713b1edbc	1870	*/
AnnaBridge	171:3a7713b1edbc	1871	__STATIC_INLINE void LL_FLASH_Disable64bitAccess(void)
AnnaBridge	171:3a7713b1edbc	1872	{
AnnaBridge	171:3a7713b1edbc	1873	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ACC64);
AnnaBridge	171:3a7713b1edbc	1874	}
AnnaBridge	171:3a7713b1edbc	1875
AnnaBridge	171:3a7713b1edbc	1876	/**
AnnaBridge	171:3a7713b1edbc	1877	* @brief Check if 64-bit access is enabled
AnnaBridge	171:3a7713b1edbc	1878	* @rmtoll FLASH_ACR ACC64 LL_FLASH_Is64bitAccessEnabled
AnnaBridge	171:3a7713b1edbc	1879	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1880	*/
AnnaBridge	171:3a7713b1edbc	1881	__STATIC_INLINE uint32_t LL_FLASH_Is64bitAccessEnabled(void)
AnnaBridge	171:3a7713b1edbc	1882	{
AnnaBridge	171:3a7713b1edbc	1883	return (READ_BIT(FLASH->ACR, FLASH_ACR_ACC64) == (FLASH_ACR_ACC64));
AnnaBridge	171:3a7713b1edbc	1884	}
AnnaBridge	171:3a7713b1edbc	1885
AnnaBridge	171:3a7713b1edbc	1886
AnnaBridge	171:3a7713b1edbc	1887	/**
AnnaBridge	171:3a7713b1edbc	1888	* @brief Enable Flash Power-down mode during run mode or Low-power run mode
AnnaBridge	171:3a7713b1edbc	1889	* @note Flash memory can be put in power-down mode only when the code is executed
AnnaBridge	171:3a7713b1edbc	1890	* from RAM
AnnaBridge	171:3a7713b1edbc	1891	* @note Flash must not be accessed when power down is enabled
AnnaBridge	171:3a7713b1edbc	1892	* @note Flash must not be put in power-down while a program or an erase operation
AnnaBridge	171:3a7713b1edbc	1893	* is on-going
AnnaBridge	171:3a7713b1edbc	1894	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
AnnaBridge	171:3a7713b1edbc	1895	* FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
AnnaBridge	171:3a7713b1edbc	1896	* FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
AnnaBridge	171:3a7713b1edbc	1897	* @retval None
AnnaBridge	171:3a7713b1edbc	1898	*/
AnnaBridge	171:3a7713b1edbc	1899	__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
AnnaBridge	171:3a7713b1edbc	1900	{
AnnaBridge	171:3a7713b1edbc	1901	/* Following values must be written consecutively to unlock the RUN_PD bit in
AnnaBridge	171:3a7713b1edbc	1902	FLASH_ACR */
AnnaBridge	171:3a7713b1edbc	1903	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
AnnaBridge	171:3a7713b1edbc	1904	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
AnnaBridge	171:3a7713b1edbc	1905	SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
AnnaBridge	171:3a7713b1edbc	1906	}
AnnaBridge	171:3a7713b1edbc	1907
AnnaBridge	171:3a7713b1edbc	1908	/**
AnnaBridge	171:3a7713b1edbc	1909	* @brief Disable Flash Power-down mode during run mode or Low-power run mode
AnnaBridge	171:3a7713b1edbc	1910	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
AnnaBridge	171:3a7713b1edbc	1911	* FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
AnnaBridge	171:3a7713b1edbc	1912	* FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
AnnaBridge	171:3a7713b1edbc	1913	* @retval None
AnnaBridge	171:3a7713b1edbc	1914	*/
AnnaBridge	171:3a7713b1edbc	1915	__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
AnnaBridge	171:3a7713b1edbc	1916	{
AnnaBridge	171:3a7713b1edbc	1917	/* Following values must be written consecutively to unlock the RUN_PD bit in
AnnaBridge	171:3a7713b1edbc	1918	FLASH_ACR */
AnnaBridge	171:3a7713b1edbc	1919	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
AnnaBridge	171:3a7713b1edbc	1920	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
AnnaBridge	171:3a7713b1edbc	1921	CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
AnnaBridge	171:3a7713b1edbc	1922	}
AnnaBridge	171:3a7713b1edbc	1923
AnnaBridge	171:3a7713b1edbc	1924	/**
AnnaBridge	171:3a7713b1edbc	1925	* @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
AnnaBridge	171:3a7713b1edbc	1926	* @note Flash must not be put in power-down while a program or an erase operation
AnnaBridge	171:3a7713b1edbc	1927	* is on-going
AnnaBridge	171:3a7713b1edbc	1928	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
AnnaBridge	171:3a7713b1edbc	1929	* @retval None
AnnaBridge	171:3a7713b1edbc	1930	*/
AnnaBridge	171:3a7713b1edbc	1931	__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
AnnaBridge	171:3a7713b1edbc	1932	{
AnnaBridge	171:3a7713b1edbc	1933	SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
AnnaBridge	171:3a7713b1edbc	1934	}
AnnaBridge	171:3a7713b1edbc	1935
AnnaBridge	171:3a7713b1edbc	1936	/**
AnnaBridge	171:3a7713b1edbc	1937	* @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
AnnaBridge	171:3a7713b1edbc	1938	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
AnnaBridge	171:3a7713b1edbc	1939	* @retval None
AnnaBridge	171:3a7713b1edbc	1940	*/
AnnaBridge	171:3a7713b1edbc	1941	__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
AnnaBridge	171:3a7713b1edbc	1942	{
AnnaBridge	171:3a7713b1edbc	1943	CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
AnnaBridge	171:3a7713b1edbc	1944	}
AnnaBridge	171:3a7713b1edbc	1945
AnnaBridge	171:3a7713b1edbc	1946	/**
AnnaBridge	171:3a7713b1edbc	1947	* @}
AnnaBridge	171:3a7713b1edbc	1948	*/
AnnaBridge	171:3a7713b1edbc	1949
AnnaBridge	171:3a7713b1edbc	1950	/**
AnnaBridge	171:3a7713b1edbc	1951	* @}
AnnaBridge	171:3a7713b1edbc	1952	*/
AnnaBridge	171:3a7713b1edbc	1953
AnnaBridge	171:3a7713b1edbc	1954	/**
AnnaBridge	171:3a7713b1edbc	1955	* @}
AnnaBridge	171:3a7713b1edbc	1956	*/
AnnaBridge	171:3a7713b1edbc	1957
AnnaBridge	171:3a7713b1edbc	1958	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined(RI) */
AnnaBridge	171:3a7713b1edbc	1959
AnnaBridge	171:3a7713b1edbc	1960	/**
AnnaBridge	171:3a7713b1edbc	1961	* @}
AnnaBridge	171:3a7713b1edbc	1962	*/
AnnaBridge	171:3a7713b1edbc	1963
AnnaBridge	171:3a7713b1edbc	1964	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1965	}
AnnaBridge	171:3a7713b1edbc	1966	#endif
AnnaBridge	171:3a7713b1edbc	1967
AnnaBridge	171:3a7713b1edbc	1968	#endif /* __STM32L1xx_LL_SYSTEM_H */
AnnaBridge	171:3a7713b1edbc	1969
AnnaBridge	171:3a7713b1edbc	1970	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/