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TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/stm32l1xx_ll_spi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l1xx_ll_spi.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of SPI LL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32L1xx_LL_SPI_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32L1xx_LL_SPI_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32l1xx.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32L1xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @defgroup SPI_LL SPI
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 62 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 63 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge 171:3a7713b1edbc 64 * @{
AnnaBridge 171:3a7713b1edbc 65 */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /**
AnnaBridge 171:3a7713b1edbc 68 * @brief SPI Init structures definition
AnnaBridge 171:3a7713b1edbc 69 */
AnnaBridge 171:3a7713b1edbc 70 typedef struct
AnnaBridge 171:3a7713b1edbc 71 {
AnnaBridge 171:3a7713b1edbc 72 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge 171:3a7713b1edbc 73 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge 171:3a7713b1edbc 78 This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge 171:3a7713b1edbc 83 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge 171:3a7713b1edbc 88 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge 171:3a7713b1edbc 93 This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge 171:3a7713b1edbc 98 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge 171:3a7713b1edbc 103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge 171:3a7713b1edbc 104 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge 171:3a7713b1edbc 109 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge 171:3a7713b1edbc 114 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge 171:3a7713b1edbc 119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 } LL_SPI_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /**
AnnaBridge 171:3a7713b1edbc 126 * @}
AnnaBridge 171:3a7713b1edbc 127 */
AnnaBridge 171:3a7713b1edbc 128 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 131 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge 171:3a7713b1edbc 132 * @{
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 171:3a7713b1edbc 136 * @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge 171:3a7713b1edbc 137 * @{
AnnaBridge 171:3a7713b1edbc 138 */
AnnaBridge 171:3a7713b1edbc 139 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
AnnaBridge 171:3a7713b1edbc 140 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
AnnaBridge 171:3a7713b1edbc 141 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
AnnaBridge 171:3a7713b1edbc 142 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
AnnaBridge 171:3a7713b1edbc 143 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
AnnaBridge 171:3a7713b1edbc 144 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
AnnaBridge 171:3a7713b1edbc 145 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
AnnaBridge 171:3a7713b1edbc 146 /**
AnnaBridge 171:3a7713b1edbc 147 * @}
AnnaBridge 171:3a7713b1edbc 148 */
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 /** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge 171:3a7713b1edbc 151 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge 171:3a7713b1edbc 152 * @{
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
AnnaBridge 171:3a7713b1edbc 155 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
AnnaBridge 171:3a7713b1edbc 156 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
AnnaBridge 171:3a7713b1edbc 157 /**
AnnaBridge 171:3a7713b1edbc 158 * @}
AnnaBridge 171:3a7713b1edbc 159 */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge 171:3a7713b1edbc 162 * @{
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
AnnaBridge 171:3a7713b1edbc 165 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
AnnaBridge 171:3a7713b1edbc 166 /**
AnnaBridge 171:3a7713b1edbc 167 * @}
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 #if defined (SPI_CR2_FRF)
AnnaBridge 171:3a7713b1edbc 171 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge 171:3a7713b1edbc 172 * @{
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
AnnaBridge 171:3a7713b1edbc 175 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
AnnaBridge 171:3a7713b1edbc 176 /**
AnnaBridge 171:3a7713b1edbc 177 * @}
AnnaBridge 171:3a7713b1edbc 178 */
AnnaBridge 171:3a7713b1edbc 179 #endif /* SPI_CR2_FRF */
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 /** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge 171:3a7713b1edbc 182 * @{
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
AnnaBridge 171:3a7713b1edbc 185 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
AnnaBridge 171:3a7713b1edbc 186 /**
AnnaBridge 171:3a7713b1edbc 187 * @}
AnnaBridge 171:3a7713b1edbc 188 */
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge 171:3a7713b1edbc 191 * @{
AnnaBridge 171:3a7713b1edbc 192 */
AnnaBridge 171:3a7713b1edbc 193 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
AnnaBridge 171:3a7713b1edbc 194 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
AnnaBridge 171:3a7713b1edbc 195 /**
AnnaBridge 171:3a7713b1edbc 196 * @}
AnnaBridge 171:3a7713b1edbc 197 */
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge 171:3a7713b1edbc 200 * @{
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
AnnaBridge 171:3a7713b1edbc 203 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
AnnaBridge 171:3a7713b1edbc 204 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
AnnaBridge 171:3a7713b1edbc 205 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
AnnaBridge 171:3a7713b1edbc 206 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
AnnaBridge 171:3a7713b1edbc 207 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
AnnaBridge 171:3a7713b1edbc 208 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
AnnaBridge 171:3a7713b1edbc 209 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
AnnaBridge 171:3a7713b1edbc 210 /**
AnnaBridge 171:3a7713b1edbc 211 * @}
AnnaBridge 171:3a7713b1edbc 212 */
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge 171:3a7713b1edbc 215 * @{
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
AnnaBridge 171:3a7713b1edbc 218 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
AnnaBridge 171:3a7713b1edbc 219 /**
AnnaBridge 171:3a7713b1edbc 220 * @}
AnnaBridge 171:3a7713b1edbc 221 */
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge 171:3a7713b1edbc 224 * @{
AnnaBridge 171:3a7713b1edbc 225 */
AnnaBridge 171:3a7713b1edbc 226 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
AnnaBridge 171:3a7713b1edbc 227 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
AnnaBridge 171:3a7713b1edbc 228 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
AnnaBridge 171:3a7713b1edbc 229 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
AnnaBridge 171:3a7713b1edbc 230 /**
AnnaBridge 171:3a7713b1edbc 231 * @}
AnnaBridge 171:3a7713b1edbc 232 */
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge 171:3a7713b1edbc 235 * @{
AnnaBridge 171:3a7713b1edbc 236 */
AnnaBridge 171:3a7713b1edbc 237 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
AnnaBridge 171:3a7713b1edbc 238 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
AnnaBridge 171:3a7713b1edbc 239 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
AnnaBridge 171:3a7713b1edbc 240 /**
AnnaBridge 171:3a7713b1edbc 241 * @}
AnnaBridge 171:3a7713b1edbc 242 */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge 171:3a7713b1edbc 245 * @{
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
AnnaBridge 171:3a7713b1edbc 248 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @}
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge 171:3a7713b1edbc 255 * @{
AnnaBridge 171:3a7713b1edbc 256 */
AnnaBridge 171:3a7713b1edbc 257 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
AnnaBridge 171:3a7713b1edbc 258 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
AnnaBridge 171:3a7713b1edbc 259 /**
AnnaBridge 171:3a7713b1edbc 260 * @}
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 /**
AnnaBridge 171:3a7713b1edbc 265 * @}
AnnaBridge 171:3a7713b1edbc 266 */
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 269 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge 171:3a7713b1edbc 270 * @{
AnnaBridge 171:3a7713b1edbc 271 */
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 171:3a7713b1edbc 274 * @{
AnnaBridge 171:3a7713b1edbc 275 */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 /**
AnnaBridge 171:3a7713b1edbc 278 * @brief Write a value in SPI register
AnnaBridge 171:3a7713b1edbc 279 * @param __INSTANCE__ SPI Instance
AnnaBridge 171:3a7713b1edbc 280 * @param __REG__ Register to be written
AnnaBridge 171:3a7713b1edbc 281 * @param __VALUE__ Value to be written in the register
AnnaBridge 171:3a7713b1edbc 282 * @retval None
AnnaBridge 171:3a7713b1edbc 283 */
AnnaBridge 171:3a7713b1edbc 284 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /**
AnnaBridge 171:3a7713b1edbc 287 * @brief Read a value in SPI register
AnnaBridge 171:3a7713b1edbc 288 * @param __INSTANCE__ SPI Instance
AnnaBridge 171:3a7713b1edbc 289 * @param __REG__ Register to be read
AnnaBridge 171:3a7713b1edbc 290 * @retval Register value
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 171:3a7713b1edbc 293 /**
AnnaBridge 171:3a7713b1edbc 294 * @}
AnnaBridge 171:3a7713b1edbc 295 */
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /**
AnnaBridge 171:3a7713b1edbc 298 * @}
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 302 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge 171:3a7713b1edbc 303 * @{
AnnaBridge 171:3a7713b1edbc 304 */
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 /** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge 171:3a7713b1edbc 307 * @{
AnnaBridge 171:3a7713b1edbc 308 */
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /**
AnnaBridge 171:3a7713b1edbc 311 * @brief Enable SPI peripheral
AnnaBridge 171:3a7713b1edbc 312 * @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge 171:3a7713b1edbc 313 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 314 * @retval None
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 317 {
AnnaBridge 171:3a7713b1edbc 318 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge 171:3a7713b1edbc 319 }
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 /**
AnnaBridge 171:3a7713b1edbc 322 * @brief Disable SPI peripheral
AnnaBridge 171:3a7713b1edbc 323 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge 171:3a7713b1edbc 324 * @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge 171:3a7713b1edbc 325 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 326 * @retval None
AnnaBridge 171:3a7713b1edbc 327 */
AnnaBridge 171:3a7713b1edbc 328 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 329 {
AnnaBridge 171:3a7713b1edbc 330 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge 171:3a7713b1edbc 331 }
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 /**
AnnaBridge 171:3a7713b1edbc 334 * @brief Check if SPI peripheral is enabled
AnnaBridge 171:3a7713b1edbc 335 * @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge 171:3a7713b1edbc 336 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 337 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 340 {
AnnaBridge 171:3a7713b1edbc 341 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge 171:3a7713b1edbc 342 }
AnnaBridge 171:3a7713b1edbc 343
AnnaBridge 171:3a7713b1edbc 344 /**
AnnaBridge 171:3a7713b1edbc 345 * @brief Set SPI operation mode to Master or Slave
AnnaBridge 171:3a7713b1edbc 346 * @note This bit should not be changed when communication is ongoing.
AnnaBridge 171:3a7713b1edbc 347 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge 171:3a7713b1edbc 348 * CR1 SSI LL_SPI_SetMode
AnnaBridge 171:3a7713b1edbc 349 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 350 * @param Mode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 351 * @arg @ref LL_SPI_MODE_MASTER
AnnaBridge 171:3a7713b1edbc 352 * @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge 171:3a7713b1edbc 353 * @retval None
AnnaBridge 171:3a7713b1edbc 354 */
AnnaBridge 171:3a7713b1edbc 355 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge 171:3a7713b1edbc 356 {
AnnaBridge 171:3a7713b1edbc 357 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
AnnaBridge 171:3a7713b1edbc 358 }
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /**
AnnaBridge 171:3a7713b1edbc 361 * @brief Get SPI operation mode (Master or Slave)
AnnaBridge 171:3a7713b1edbc 362 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge 171:3a7713b1edbc 363 * CR1 SSI LL_SPI_GetMode
AnnaBridge 171:3a7713b1edbc 364 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 365 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 366 * @arg @ref LL_SPI_MODE_MASTER
AnnaBridge 171:3a7713b1edbc 367 * @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge 171:3a7713b1edbc 368 */
AnnaBridge 171:3a7713b1edbc 369 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 370 {
AnnaBridge 171:3a7713b1edbc 371 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
AnnaBridge 171:3a7713b1edbc 372 }
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 #if defined (SPI_CR2_FRF)
AnnaBridge 171:3a7713b1edbc 375 /**
AnnaBridge 171:3a7713b1edbc 376 * @brief Set serial protocol used
AnnaBridge 171:3a7713b1edbc 377 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 171:3a7713b1edbc 378 * @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge 171:3a7713b1edbc 379 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 380 * @param Standard This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 381 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge 171:3a7713b1edbc 382 * @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge 171:3a7713b1edbc 383 * @retval None
AnnaBridge 171:3a7713b1edbc 384 */
AnnaBridge 171:3a7713b1edbc 385 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge 171:3a7713b1edbc 386 {
AnnaBridge 171:3a7713b1edbc 387 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge 171:3a7713b1edbc 388 }
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 /**
AnnaBridge 171:3a7713b1edbc 391 * @brief Get serial protocol used
AnnaBridge 171:3a7713b1edbc 392 * @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge 171:3a7713b1edbc 393 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 394 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 395 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge 171:3a7713b1edbc 396 * @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 399 {
AnnaBridge 171:3a7713b1edbc 400 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge 171:3a7713b1edbc 401 }
AnnaBridge 171:3a7713b1edbc 402 #endif /* SPI_CR2_FRF */
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 /**
AnnaBridge 171:3a7713b1edbc 405 * @brief Set clock phase
AnnaBridge 171:3a7713b1edbc 406 * @note This bit should not be changed when communication is ongoing.
AnnaBridge 171:3a7713b1edbc 407 * This bit is not used in SPI TI mode.
AnnaBridge 171:3a7713b1edbc 408 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge 171:3a7713b1edbc 409 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 410 * @param ClockPhase This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 411 * @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge 171:3a7713b1edbc 412 * @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge 171:3a7713b1edbc 413 * @retval None
AnnaBridge 171:3a7713b1edbc 414 */
AnnaBridge 171:3a7713b1edbc 415 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge 171:3a7713b1edbc 416 {
AnnaBridge 171:3a7713b1edbc 417 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge 171:3a7713b1edbc 418 }
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 /**
AnnaBridge 171:3a7713b1edbc 421 * @brief Get clock phase
AnnaBridge 171:3a7713b1edbc 422 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge 171:3a7713b1edbc 423 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 424 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 425 * @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge 171:3a7713b1edbc 426 * @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge 171:3a7713b1edbc 427 */
AnnaBridge 171:3a7713b1edbc 428 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 429 {
AnnaBridge 171:3a7713b1edbc 430 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge 171:3a7713b1edbc 431 }
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 /**
AnnaBridge 171:3a7713b1edbc 434 * @brief Set clock polarity
AnnaBridge 171:3a7713b1edbc 435 * @note This bit should not be changed when communication is ongoing.
AnnaBridge 171:3a7713b1edbc 436 * This bit is not used in SPI TI mode.
AnnaBridge 171:3a7713b1edbc 437 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge 171:3a7713b1edbc 438 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 439 * @param ClockPolarity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 440 * @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge 171:3a7713b1edbc 441 * @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge 171:3a7713b1edbc 442 * @retval None
AnnaBridge 171:3a7713b1edbc 443 */
AnnaBridge 171:3a7713b1edbc 444 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge 171:3a7713b1edbc 445 {
AnnaBridge 171:3a7713b1edbc 446 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge 171:3a7713b1edbc 447 }
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 /**
AnnaBridge 171:3a7713b1edbc 450 * @brief Get clock polarity
AnnaBridge 171:3a7713b1edbc 451 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge 171:3a7713b1edbc 452 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 453 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 454 * @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge 171:3a7713b1edbc 455 * @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge 171:3a7713b1edbc 456 */
AnnaBridge 171:3a7713b1edbc 457 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 458 {
AnnaBridge 171:3a7713b1edbc 459 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge 171:3a7713b1edbc 460 }
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 /**
AnnaBridge 171:3a7713b1edbc 463 * @brief Set baud rate prescaler
AnnaBridge 171:3a7713b1edbc 464 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge 171:3a7713b1edbc 465 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge 171:3a7713b1edbc 466 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 467 * @param BaudRate This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 468 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge 171:3a7713b1edbc 469 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge 171:3a7713b1edbc 470 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge 171:3a7713b1edbc 471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge 171:3a7713b1edbc 472 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge 171:3a7713b1edbc 473 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge 171:3a7713b1edbc 474 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge 171:3a7713b1edbc 475 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge 171:3a7713b1edbc 476 * @retval None
AnnaBridge 171:3a7713b1edbc 477 */
AnnaBridge 171:3a7713b1edbc 478 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge 171:3a7713b1edbc 479 {
AnnaBridge 171:3a7713b1edbc 480 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge 171:3a7713b1edbc 481 }
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /**
AnnaBridge 171:3a7713b1edbc 484 * @brief Get baud rate prescaler
AnnaBridge 171:3a7713b1edbc 485 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge 171:3a7713b1edbc 486 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 487 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 488 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge 171:3a7713b1edbc 489 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge 171:3a7713b1edbc 490 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge 171:3a7713b1edbc 491 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge 171:3a7713b1edbc 492 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge 171:3a7713b1edbc 493 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge 171:3a7713b1edbc 494 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge 171:3a7713b1edbc 495 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge 171:3a7713b1edbc 496 */
AnnaBridge 171:3a7713b1edbc 497 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 498 {
AnnaBridge 171:3a7713b1edbc 499 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge 171:3a7713b1edbc 500 }
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 /**
AnnaBridge 171:3a7713b1edbc 503 * @brief Set transfer bit order
AnnaBridge 171:3a7713b1edbc 504 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge 171:3a7713b1edbc 505 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge 171:3a7713b1edbc 506 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 507 * @param BitOrder This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 508 * @arg @ref LL_SPI_LSB_FIRST
AnnaBridge 171:3a7713b1edbc 509 * @arg @ref LL_SPI_MSB_FIRST
AnnaBridge 171:3a7713b1edbc 510 * @retval None
AnnaBridge 171:3a7713b1edbc 511 */
AnnaBridge 171:3a7713b1edbc 512 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge 171:3a7713b1edbc 513 {
AnnaBridge 171:3a7713b1edbc 514 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge 171:3a7713b1edbc 515 }
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 /**
AnnaBridge 171:3a7713b1edbc 518 * @brief Get transfer bit order
AnnaBridge 171:3a7713b1edbc 519 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge 171:3a7713b1edbc 520 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 521 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 522 * @arg @ref LL_SPI_LSB_FIRST
AnnaBridge 171:3a7713b1edbc 523 * @arg @ref LL_SPI_MSB_FIRST
AnnaBridge 171:3a7713b1edbc 524 */
AnnaBridge 171:3a7713b1edbc 525 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 526 {
AnnaBridge 171:3a7713b1edbc 527 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge 171:3a7713b1edbc 528 }
AnnaBridge 171:3a7713b1edbc 529
AnnaBridge 171:3a7713b1edbc 530 /**
AnnaBridge 171:3a7713b1edbc 531 * @brief Set transfer direction mode
AnnaBridge 171:3a7713b1edbc 532 * @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge 171:3a7713b1edbc 533 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge 171:3a7713b1edbc 534 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge 171:3a7713b1edbc 535 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge 171:3a7713b1edbc 536 * CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge 171:3a7713b1edbc 537 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 538 * @param TransferDirection This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 539 * @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge 171:3a7713b1edbc 540 * @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge 171:3a7713b1edbc 541 * @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge 171:3a7713b1edbc 542 * @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge 171:3a7713b1edbc 543 * @retval None
AnnaBridge 171:3a7713b1edbc 544 */
AnnaBridge 171:3a7713b1edbc 545 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge 171:3a7713b1edbc 546 {
AnnaBridge 171:3a7713b1edbc 547 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge 171:3a7713b1edbc 548 }
AnnaBridge 171:3a7713b1edbc 549
AnnaBridge 171:3a7713b1edbc 550 /**
AnnaBridge 171:3a7713b1edbc 551 * @brief Get transfer direction mode
AnnaBridge 171:3a7713b1edbc 552 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge 171:3a7713b1edbc 553 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge 171:3a7713b1edbc 554 * CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge 171:3a7713b1edbc 555 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 556 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 557 * @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge 171:3a7713b1edbc 558 * @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge 171:3a7713b1edbc 559 * @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge 171:3a7713b1edbc 560 * @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge 171:3a7713b1edbc 561 */
AnnaBridge 171:3a7713b1edbc 562 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 563 {
AnnaBridge 171:3a7713b1edbc 564 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
AnnaBridge 171:3a7713b1edbc 565 }
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 /**
AnnaBridge 171:3a7713b1edbc 568 * @brief Set frame data width
AnnaBridge 171:3a7713b1edbc 569 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
AnnaBridge 171:3a7713b1edbc 570 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 571 * @param DataWidth This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 572 * @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge 171:3a7713b1edbc 573 * @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge 171:3a7713b1edbc 574 * @retval None
AnnaBridge 171:3a7713b1edbc 575 */
AnnaBridge 171:3a7713b1edbc 576 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge 171:3a7713b1edbc 577 {
AnnaBridge 171:3a7713b1edbc 578 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
AnnaBridge 171:3a7713b1edbc 579 }
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 /**
AnnaBridge 171:3a7713b1edbc 582 * @brief Get frame data width
AnnaBridge 171:3a7713b1edbc 583 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
AnnaBridge 171:3a7713b1edbc 584 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 585 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 586 * @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge 171:3a7713b1edbc 587 * @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge 171:3a7713b1edbc 588 */
AnnaBridge 171:3a7713b1edbc 589 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 590 {
AnnaBridge 171:3a7713b1edbc 591 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
AnnaBridge 171:3a7713b1edbc 592 }
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /**
AnnaBridge 171:3a7713b1edbc 595 * @}
AnnaBridge 171:3a7713b1edbc 596 */
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge 171:3a7713b1edbc 599 * @{
AnnaBridge 171:3a7713b1edbc 600 */
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 /**
AnnaBridge 171:3a7713b1edbc 603 * @brief Enable CRC
AnnaBridge 171:3a7713b1edbc 604 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 171:3a7713b1edbc 605 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge 171:3a7713b1edbc 606 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 607 * @retval None
AnnaBridge 171:3a7713b1edbc 608 */
AnnaBridge 171:3a7713b1edbc 609 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 610 {
AnnaBridge 171:3a7713b1edbc 611 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge 171:3a7713b1edbc 612 }
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 /**
AnnaBridge 171:3a7713b1edbc 615 * @brief Disable CRC
AnnaBridge 171:3a7713b1edbc 616 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 171:3a7713b1edbc 617 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge 171:3a7713b1edbc 618 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 619 * @retval None
AnnaBridge 171:3a7713b1edbc 620 */
AnnaBridge 171:3a7713b1edbc 621 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 622 {
AnnaBridge 171:3a7713b1edbc 623 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge 171:3a7713b1edbc 624 }
AnnaBridge 171:3a7713b1edbc 625
AnnaBridge 171:3a7713b1edbc 626 /**
AnnaBridge 171:3a7713b1edbc 627 * @brief Check if CRC is enabled
AnnaBridge 171:3a7713b1edbc 628 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 171:3a7713b1edbc 629 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge 171:3a7713b1edbc 630 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 631 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 632 */
AnnaBridge 171:3a7713b1edbc 633 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 634 {
AnnaBridge 171:3a7713b1edbc 635 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge 171:3a7713b1edbc 636 }
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638 /**
AnnaBridge 171:3a7713b1edbc 639 * @brief Set CRCNext to transfer CRC on the line
AnnaBridge 171:3a7713b1edbc 640 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge 171:3a7713b1edbc 641 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge 171:3a7713b1edbc 642 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 643 * @retval None
AnnaBridge 171:3a7713b1edbc 644 */
AnnaBridge 171:3a7713b1edbc 645 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 646 {
AnnaBridge 171:3a7713b1edbc 647 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge 171:3a7713b1edbc 648 }
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /**
AnnaBridge 171:3a7713b1edbc 651 * @brief Set polynomial for CRC calculation
AnnaBridge 171:3a7713b1edbc 652 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge 171:3a7713b1edbc 653 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 654 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 655 * @retval None
AnnaBridge 171:3a7713b1edbc 656 */
AnnaBridge 171:3a7713b1edbc 657 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge 171:3a7713b1edbc 658 {
AnnaBridge 171:3a7713b1edbc 659 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge 171:3a7713b1edbc 660 }
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 /**
AnnaBridge 171:3a7713b1edbc 663 * @brief Get polynomial for CRC calculation
AnnaBridge 171:3a7713b1edbc 664 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge 171:3a7713b1edbc 665 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 666 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 667 */
AnnaBridge 171:3a7713b1edbc 668 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 669 {
AnnaBridge 171:3a7713b1edbc 670 return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge 171:3a7713b1edbc 671 }
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /**
AnnaBridge 171:3a7713b1edbc 674 * @brief Get Rx CRC
AnnaBridge 171:3a7713b1edbc 675 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge 171:3a7713b1edbc 676 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 677 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 678 */
AnnaBridge 171:3a7713b1edbc 679 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 680 {
AnnaBridge 171:3a7713b1edbc 681 return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge 171:3a7713b1edbc 682 }
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 /**
AnnaBridge 171:3a7713b1edbc 685 * @brief Get Tx CRC
AnnaBridge 171:3a7713b1edbc 686 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge 171:3a7713b1edbc 687 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 688 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 689 */
AnnaBridge 171:3a7713b1edbc 690 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 691 {
AnnaBridge 171:3a7713b1edbc 692 return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge 171:3a7713b1edbc 693 }
AnnaBridge 171:3a7713b1edbc 694
AnnaBridge 171:3a7713b1edbc 695 /**
AnnaBridge 171:3a7713b1edbc 696 * @}
AnnaBridge 171:3a7713b1edbc 697 */
AnnaBridge 171:3a7713b1edbc 698
AnnaBridge 171:3a7713b1edbc 699 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge 171:3a7713b1edbc 700 * @{
AnnaBridge 171:3a7713b1edbc 701 */
AnnaBridge 171:3a7713b1edbc 702
AnnaBridge 171:3a7713b1edbc 703 /**
AnnaBridge 171:3a7713b1edbc 704 * @brief Set NSS mode
AnnaBridge 171:3a7713b1edbc 705 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge 171:3a7713b1edbc 706 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge 171:3a7713b1edbc 707 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge 171:3a7713b1edbc 708 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 709 * @param NSS This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 710 * @arg @ref LL_SPI_NSS_SOFT
AnnaBridge 171:3a7713b1edbc 711 * @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge 171:3a7713b1edbc 712 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge 171:3a7713b1edbc 713 * @retval None
AnnaBridge 171:3a7713b1edbc 714 */
AnnaBridge 171:3a7713b1edbc 715 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge 171:3a7713b1edbc 716 {
AnnaBridge 171:3a7713b1edbc 717 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge 171:3a7713b1edbc 718 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge 171:3a7713b1edbc 719 }
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721 /**
AnnaBridge 171:3a7713b1edbc 722 * @brief Get NSS mode
AnnaBridge 171:3a7713b1edbc 723 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge 171:3a7713b1edbc 724 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge 171:3a7713b1edbc 725 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 726 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 727 * @arg @ref LL_SPI_NSS_SOFT
AnnaBridge 171:3a7713b1edbc 728 * @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge 171:3a7713b1edbc 729 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge 171:3a7713b1edbc 730 */
AnnaBridge 171:3a7713b1edbc 731 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 732 {
AnnaBridge 171:3a7713b1edbc 733 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge 171:3a7713b1edbc 734 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge 171:3a7713b1edbc 735 return (Ssm | Ssoe);
AnnaBridge 171:3a7713b1edbc 736 }
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /**
AnnaBridge 171:3a7713b1edbc 739 * @}
AnnaBridge 171:3a7713b1edbc 740 */
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge 171:3a7713b1edbc 743 * @{
AnnaBridge 171:3a7713b1edbc 744 */
AnnaBridge 171:3a7713b1edbc 745
AnnaBridge 171:3a7713b1edbc 746 /**
AnnaBridge 171:3a7713b1edbc 747 * @brief Check if Rx buffer is not empty
AnnaBridge 171:3a7713b1edbc 748 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge 171:3a7713b1edbc 749 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 750 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 751 */
AnnaBridge 171:3a7713b1edbc 752 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 753 {
AnnaBridge 171:3a7713b1edbc 754 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge 171:3a7713b1edbc 755 }
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 /**
AnnaBridge 171:3a7713b1edbc 758 * @brief Check if Tx buffer is empty
AnnaBridge 171:3a7713b1edbc 759 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge 171:3a7713b1edbc 760 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 761 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 762 */
AnnaBridge 171:3a7713b1edbc 763 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 764 {
AnnaBridge 171:3a7713b1edbc 765 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge 171:3a7713b1edbc 766 }
AnnaBridge 171:3a7713b1edbc 767
AnnaBridge 171:3a7713b1edbc 768 /**
AnnaBridge 171:3a7713b1edbc 769 * @brief Get CRC error flag
AnnaBridge 171:3a7713b1edbc 770 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge 171:3a7713b1edbc 771 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 772 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 773 */
AnnaBridge 171:3a7713b1edbc 774 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 775 {
AnnaBridge 171:3a7713b1edbc 776 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge 171:3a7713b1edbc 777 }
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /**
AnnaBridge 171:3a7713b1edbc 780 * @brief Get mode fault error flag
AnnaBridge 171:3a7713b1edbc 781 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge 171:3a7713b1edbc 782 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 783 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 784 */
AnnaBridge 171:3a7713b1edbc 785 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 786 {
AnnaBridge 171:3a7713b1edbc 787 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge 171:3a7713b1edbc 788 }
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 /**
AnnaBridge 171:3a7713b1edbc 791 * @brief Get overrun error flag
AnnaBridge 171:3a7713b1edbc 792 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge 171:3a7713b1edbc 793 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 794 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 795 */
AnnaBridge 171:3a7713b1edbc 796 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 797 {
AnnaBridge 171:3a7713b1edbc 798 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge 171:3a7713b1edbc 799 }
AnnaBridge 171:3a7713b1edbc 800
AnnaBridge 171:3a7713b1edbc 801 /**
AnnaBridge 171:3a7713b1edbc 802 * @brief Get busy flag
AnnaBridge 171:3a7713b1edbc 803 * @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge 171:3a7713b1edbc 804 * -When the SPI is correctly disabled
AnnaBridge 171:3a7713b1edbc 805 * -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge 171:3a7713b1edbc 806 * -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge 171:3a7713b1edbc 807 * sent
AnnaBridge 171:3a7713b1edbc 808 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge 171:3a7713b1edbc 809 * each data transfer.
AnnaBridge 171:3a7713b1edbc 810 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge 171:3a7713b1edbc 811 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 812 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 813 */
AnnaBridge 171:3a7713b1edbc 814 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 815 {
AnnaBridge 171:3a7713b1edbc 816 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge 171:3a7713b1edbc 817 }
AnnaBridge 171:3a7713b1edbc 818
AnnaBridge 171:3a7713b1edbc 819 /**
AnnaBridge 171:3a7713b1edbc 820 * @brief Get frame format error flag
AnnaBridge 171:3a7713b1edbc 821 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge 171:3a7713b1edbc 822 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 823 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 824 */
AnnaBridge 171:3a7713b1edbc 825 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 826 {
AnnaBridge 171:3a7713b1edbc 827 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge 171:3a7713b1edbc 828 }
AnnaBridge 171:3a7713b1edbc 829
AnnaBridge 171:3a7713b1edbc 830 /**
AnnaBridge 171:3a7713b1edbc 831 * @brief Clear CRC error flag
AnnaBridge 171:3a7713b1edbc 832 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge 171:3a7713b1edbc 833 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 834 * @retval None
AnnaBridge 171:3a7713b1edbc 835 */
AnnaBridge 171:3a7713b1edbc 836 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 837 {
AnnaBridge 171:3a7713b1edbc 838 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge 171:3a7713b1edbc 839 }
AnnaBridge 171:3a7713b1edbc 840
AnnaBridge 171:3a7713b1edbc 841 /**
AnnaBridge 171:3a7713b1edbc 842 * @brief Clear mode fault error flag
AnnaBridge 171:3a7713b1edbc 843 * @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge 171:3a7713b1edbc 844 * register followed by a write access to the SPIx_CR1 register
AnnaBridge 171:3a7713b1edbc 845 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge 171:3a7713b1edbc 846 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 847 * @retval None
AnnaBridge 171:3a7713b1edbc 848 */
AnnaBridge 171:3a7713b1edbc 849 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 850 {
AnnaBridge 171:3a7713b1edbc 851 __IO uint32_t tmpreg;
AnnaBridge 171:3a7713b1edbc 852 tmpreg = SPIx->SR;
AnnaBridge 171:3a7713b1edbc 853 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 854 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge 171:3a7713b1edbc 855 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 856 }
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /**
AnnaBridge 171:3a7713b1edbc 859 * @brief Clear overrun error flag
AnnaBridge 171:3a7713b1edbc 860 * @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge 171:3a7713b1edbc 861 * register followed by a read access to the SPIx_SR register
AnnaBridge 171:3a7713b1edbc 862 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge 171:3a7713b1edbc 863 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 864 * @retval None
AnnaBridge 171:3a7713b1edbc 865 */
AnnaBridge 171:3a7713b1edbc 866 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 867 {
AnnaBridge 171:3a7713b1edbc 868 __IO uint32_t tmpreg;
AnnaBridge 171:3a7713b1edbc 869 tmpreg = SPIx->DR;
AnnaBridge 171:3a7713b1edbc 870 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 871 tmpreg = SPIx->SR;
AnnaBridge 171:3a7713b1edbc 872 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 873 }
AnnaBridge 171:3a7713b1edbc 874
AnnaBridge 171:3a7713b1edbc 875 /**
AnnaBridge 171:3a7713b1edbc 876 * @brief Clear frame format error flag
AnnaBridge 171:3a7713b1edbc 877 * @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge 171:3a7713b1edbc 878 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge 171:3a7713b1edbc 879 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 880 * @retval None
AnnaBridge 171:3a7713b1edbc 881 */
AnnaBridge 171:3a7713b1edbc 882 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 883 {
AnnaBridge 171:3a7713b1edbc 884 __IO uint32_t tmpreg;
AnnaBridge 171:3a7713b1edbc 885 tmpreg = SPIx->SR;
AnnaBridge 171:3a7713b1edbc 886 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 887 }
AnnaBridge 171:3a7713b1edbc 888
AnnaBridge 171:3a7713b1edbc 889 /**
AnnaBridge 171:3a7713b1edbc 890 * @}
AnnaBridge 171:3a7713b1edbc 891 */
AnnaBridge 171:3a7713b1edbc 892
AnnaBridge 171:3a7713b1edbc 893 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge 171:3a7713b1edbc 894 * @{
AnnaBridge 171:3a7713b1edbc 895 */
AnnaBridge 171:3a7713b1edbc 896
AnnaBridge 171:3a7713b1edbc 897 /**
AnnaBridge 171:3a7713b1edbc 898 * @brief Enable error interrupt
AnnaBridge 171:3a7713b1edbc 899 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge 171:3a7713b1edbc 900 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge 171:3a7713b1edbc 901 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 902 * @retval None
AnnaBridge 171:3a7713b1edbc 903 */
AnnaBridge 171:3a7713b1edbc 904 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 905 {
AnnaBridge 171:3a7713b1edbc 906 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge 171:3a7713b1edbc 907 }
AnnaBridge 171:3a7713b1edbc 908
AnnaBridge 171:3a7713b1edbc 909 /**
AnnaBridge 171:3a7713b1edbc 910 * @brief Enable Rx buffer not empty interrupt
AnnaBridge 171:3a7713b1edbc 911 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge 171:3a7713b1edbc 912 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 913 * @retval None
AnnaBridge 171:3a7713b1edbc 914 */
AnnaBridge 171:3a7713b1edbc 915 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 916 {
AnnaBridge 171:3a7713b1edbc 917 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge 171:3a7713b1edbc 918 }
AnnaBridge 171:3a7713b1edbc 919
AnnaBridge 171:3a7713b1edbc 920 /**
AnnaBridge 171:3a7713b1edbc 921 * @brief Enable Tx buffer empty interrupt
AnnaBridge 171:3a7713b1edbc 922 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge 171:3a7713b1edbc 923 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 924 * @retval None
AnnaBridge 171:3a7713b1edbc 925 */
AnnaBridge 171:3a7713b1edbc 926 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 927 {
AnnaBridge 171:3a7713b1edbc 928 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge 171:3a7713b1edbc 929 }
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 /**
AnnaBridge 171:3a7713b1edbc 932 * @brief Disable error interrupt
AnnaBridge 171:3a7713b1edbc 933 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge 171:3a7713b1edbc 934 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge 171:3a7713b1edbc 935 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 936 * @retval None
AnnaBridge 171:3a7713b1edbc 937 */
AnnaBridge 171:3a7713b1edbc 938 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 939 {
AnnaBridge 171:3a7713b1edbc 940 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge 171:3a7713b1edbc 941 }
AnnaBridge 171:3a7713b1edbc 942
AnnaBridge 171:3a7713b1edbc 943 /**
AnnaBridge 171:3a7713b1edbc 944 * @brief Disable Rx buffer not empty interrupt
AnnaBridge 171:3a7713b1edbc 945 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge 171:3a7713b1edbc 946 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 947 * @retval None
AnnaBridge 171:3a7713b1edbc 948 */
AnnaBridge 171:3a7713b1edbc 949 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 950 {
AnnaBridge 171:3a7713b1edbc 951 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge 171:3a7713b1edbc 952 }
AnnaBridge 171:3a7713b1edbc 953
AnnaBridge 171:3a7713b1edbc 954 /**
AnnaBridge 171:3a7713b1edbc 955 * @brief Disable Tx buffer empty interrupt
AnnaBridge 171:3a7713b1edbc 956 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge 171:3a7713b1edbc 957 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 958 * @retval None
AnnaBridge 171:3a7713b1edbc 959 */
AnnaBridge 171:3a7713b1edbc 960 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 961 {
AnnaBridge 171:3a7713b1edbc 962 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge 171:3a7713b1edbc 963 }
AnnaBridge 171:3a7713b1edbc 964
AnnaBridge 171:3a7713b1edbc 965 /**
AnnaBridge 171:3a7713b1edbc 966 * @brief Check if error interrupt is enabled
AnnaBridge 171:3a7713b1edbc 967 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge 171:3a7713b1edbc 968 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 969 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 970 */
AnnaBridge 171:3a7713b1edbc 971 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 972 {
AnnaBridge 171:3a7713b1edbc 973 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge 171:3a7713b1edbc 974 }
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 /**
AnnaBridge 171:3a7713b1edbc 977 * @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge 171:3a7713b1edbc 978 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge 171:3a7713b1edbc 979 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 980 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 981 */
AnnaBridge 171:3a7713b1edbc 982 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 983 {
AnnaBridge 171:3a7713b1edbc 984 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge 171:3a7713b1edbc 985 }
AnnaBridge 171:3a7713b1edbc 986
AnnaBridge 171:3a7713b1edbc 987 /**
AnnaBridge 171:3a7713b1edbc 988 * @brief Check if Tx buffer empty interrupt
AnnaBridge 171:3a7713b1edbc 989 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge 171:3a7713b1edbc 990 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 991 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 992 */
AnnaBridge 171:3a7713b1edbc 993 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 994 {
AnnaBridge 171:3a7713b1edbc 995 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge 171:3a7713b1edbc 996 }
AnnaBridge 171:3a7713b1edbc 997
AnnaBridge 171:3a7713b1edbc 998 /**
AnnaBridge 171:3a7713b1edbc 999 * @}
AnnaBridge 171:3a7713b1edbc 1000 */
AnnaBridge 171:3a7713b1edbc 1001
AnnaBridge 171:3a7713b1edbc 1002 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge 171:3a7713b1edbc 1003 * @{
AnnaBridge 171:3a7713b1edbc 1004 */
AnnaBridge 171:3a7713b1edbc 1005
AnnaBridge 171:3a7713b1edbc 1006 /**
AnnaBridge 171:3a7713b1edbc 1007 * @brief Enable DMA Rx
AnnaBridge 171:3a7713b1edbc 1008 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge 171:3a7713b1edbc 1009 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1010 * @retval None
AnnaBridge 171:3a7713b1edbc 1011 */
AnnaBridge 171:3a7713b1edbc 1012 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1013 {
AnnaBridge 171:3a7713b1edbc 1014 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge 171:3a7713b1edbc 1015 }
AnnaBridge 171:3a7713b1edbc 1016
AnnaBridge 171:3a7713b1edbc 1017 /**
AnnaBridge 171:3a7713b1edbc 1018 * @brief Disable DMA Rx
AnnaBridge 171:3a7713b1edbc 1019 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge 171:3a7713b1edbc 1020 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1021 * @retval None
AnnaBridge 171:3a7713b1edbc 1022 */
AnnaBridge 171:3a7713b1edbc 1023 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1024 {
AnnaBridge 171:3a7713b1edbc 1025 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge 171:3a7713b1edbc 1026 }
AnnaBridge 171:3a7713b1edbc 1027
AnnaBridge 171:3a7713b1edbc 1028 /**
AnnaBridge 171:3a7713b1edbc 1029 * @brief Check if DMA Rx is enabled
AnnaBridge 171:3a7713b1edbc 1030 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge 171:3a7713b1edbc 1031 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1032 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1033 */
AnnaBridge 171:3a7713b1edbc 1034 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1035 {
AnnaBridge 171:3a7713b1edbc 1036 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge 171:3a7713b1edbc 1037 }
AnnaBridge 171:3a7713b1edbc 1038
AnnaBridge 171:3a7713b1edbc 1039 /**
AnnaBridge 171:3a7713b1edbc 1040 * @brief Enable DMA Tx
AnnaBridge 171:3a7713b1edbc 1041 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge 171:3a7713b1edbc 1042 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1043 * @retval None
AnnaBridge 171:3a7713b1edbc 1044 */
AnnaBridge 171:3a7713b1edbc 1045 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1046 {
AnnaBridge 171:3a7713b1edbc 1047 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge 171:3a7713b1edbc 1048 }
AnnaBridge 171:3a7713b1edbc 1049
AnnaBridge 171:3a7713b1edbc 1050 /**
AnnaBridge 171:3a7713b1edbc 1051 * @brief Disable DMA Tx
AnnaBridge 171:3a7713b1edbc 1052 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge 171:3a7713b1edbc 1053 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1054 * @retval None
AnnaBridge 171:3a7713b1edbc 1055 */
AnnaBridge 171:3a7713b1edbc 1056 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1057 {
AnnaBridge 171:3a7713b1edbc 1058 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge 171:3a7713b1edbc 1059 }
AnnaBridge 171:3a7713b1edbc 1060
AnnaBridge 171:3a7713b1edbc 1061 /**
AnnaBridge 171:3a7713b1edbc 1062 * @brief Check if DMA Tx is enabled
AnnaBridge 171:3a7713b1edbc 1063 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge 171:3a7713b1edbc 1064 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1065 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1066 */
AnnaBridge 171:3a7713b1edbc 1067 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1068 {
AnnaBridge 171:3a7713b1edbc 1069 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge 171:3a7713b1edbc 1070 }
AnnaBridge 171:3a7713b1edbc 1071
AnnaBridge 171:3a7713b1edbc 1072 /**
AnnaBridge 171:3a7713b1edbc 1073 * @brief Get the data register address used for DMA transfer
AnnaBridge 171:3a7713b1edbc 1074 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge 171:3a7713b1edbc 1075 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1076 * @retval Address of data register
AnnaBridge 171:3a7713b1edbc 1077 */
AnnaBridge 171:3a7713b1edbc 1078 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1079 {
AnnaBridge 171:3a7713b1edbc 1080 return (uint32_t) & (SPIx->DR);
AnnaBridge 171:3a7713b1edbc 1081 }
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 /**
AnnaBridge 171:3a7713b1edbc 1084 * @}
AnnaBridge 171:3a7713b1edbc 1085 */
AnnaBridge 171:3a7713b1edbc 1086
AnnaBridge 171:3a7713b1edbc 1087 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge 171:3a7713b1edbc 1088 * @{
AnnaBridge 171:3a7713b1edbc 1089 */
AnnaBridge 171:3a7713b1edbc 1090
AnnaBridge 171:3a7713b1edbc 1091 /**
AnnaBridge 171:3a7713b1edbc 1092 * @brief Read 8-Bits in the data register
AnnaBridge 171:3a7713b1edbc 1093 * @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge 171:3a7713b1edbc 1094 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1095 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 1096 */
AnnaBridge 171:3a7713b1edbc 1097 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1098 {
AnnaBridge 171:3a7713b1edbc 1099 return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge 171:3a7713b1edbc 1100 }
AnnaBridge 171:3a7713b1edbc 1101
AnnaBridge 171:3a7713b1edbc 1102 /**
AnnaBridge 171:3a7713b1edbc 1103 * @brief Read 16-Bits in the data register
AnnaBridge 171:3a7713b1edbc 1104 * @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge 171:3a7713b1edbc 1105 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1106 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 1107 */
AnnaBridge 171:3a7713b1edbc 1108 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1109 {
AnnaBridge 171:3a7713b1edbc 1110 return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge 171:3a7713b1edbc 1111 }
AnnaBridge 171:3a7713b1edbc 1112
AnnaBridge 171:3a7713b1edbc 1113 /**
AnnaBridge 171:3a7713b1edbc 1114 * @brief Write 8-Bits in the data register
AnnaBridge 171:3a7713b1edbc 1115 * @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge 171:3a7713b1edbc 1116 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1117 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 1118 * @retval None
AnnaBridge 171:3a7713b1edbc 1119 */
AnnaBridge 171:3a7713b1edbc 1120 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge 171:3a7713b1edbc 1121 {
AnnaBridge 171:3a7713b1edbc 1122 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
AnnaBridge 171:3a7713b1edbc 1123 *spidr = TxData;
AnnaBridge 171:3a7713b1edbc 1124 }
AnnaBridge 171:3a7713b1edbc 1125
AnnaBridge 171:3a7713b1edbc 1126 /**
AnnaBridge 171:3a7713b1edbc 1127 * @brief Write 16-Bits in the data register
AnnaBridge 171:3a7713b1edbc 1128 * @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge 171:3a7713b1edbc 1129 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1130 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 1131 * @retval None
AnnaBridge 171:3a7713b1edbc 1132 */
AnnaBridge 171:3a7713b1edbc 1133 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge 171:3a7713b1edbc 1134 {
AnnaBridge 171:3a7713b1edbc 1135 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
AnnaBridge 171:3a7713b1edbc 1136 *spidr = TxData;
AnnaBridge 171:3a7713b1edbc 1137 }
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139 /**
AnnaBridge 171:3a7713b1edbc 1140 * @}
AnnaBridge 171:3a7713b1edbc 1141 */
AnnaBridge 171:3a7713b1edbc 1142 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 1143 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 1144 * @{
AnnaBridge 171:3a7713b1edbc 1145 */
AnnaBridge 171:3a7713b1edbc 1146
AnnaBridge 171:3a7713b1edbc 1147 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge 171:3a7713b1edbc 1148 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge 171:3a7713b1edbc 1149 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge 171:3a7713b1edbc 1150
AnnaBridge 171:3a7713b1edbc 1151 /**
AnnaBridge 171:3a7713b1edbc 1152 * @}
AnnaBridge 171:3a7713b1edbc 1153 */
AnnaBridge 171:3a7713b1edbc 1154 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 1155 /**
AnnaBridge 171:3a7713b1edbc 1156 * @}
AnnaBridge 171:3a7713b1edbc 1157 */
AnnaBridge 171:3a7713b1edbc 1158
AnnaBridge 171:3a7713b1edbc 1159 /**
AnnaBridge 171:3a7713b1edbc 1160 * @}
AnnaBridge 171:3a7713b1edbc 1161 */
AnnaBridge 171:3a7713b1edbc 1162
AnnaBridge 171:3a7713b1edbc 1163 #if defined(SPI_I2S_SUPPORT)
AnnaBridge 171:3a7713b1edbc 1164 /** @defgroup I2S_LL I2S
AnnaBridge 171:3a7713b1edbc 1165 * @{
AnnaBridge 171:3a7713b1edbc 1166 */
AnnaBridge 171:3a7713b1edbc 1167
AnnaBridge 171:3a7713b1edbc 1168 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1169 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1170 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1171
AnnaBridge 171:3a7713b1edbc 1172 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1173 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 1174 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge 171:3a7713b1edbc 1175 * @{
AnnaBridge 171:3a7713b1edbc 1176 */
AnnaBridge 171:3a7713b1edbc 1177
AnnaBridge 171:3a7713b1edbc 1178 /**
AnnaBridge 171:3a7713b1edbc 1179 * @brief I2S Init structure definition
AnnaBridge 171:3a7713b1edbc 1180 */
AnnaBridge 171:3a7713b1edbc 1181
AnnaBridge 171:3a7713b1edbc 1182 typedef struct
AnnaBridge 171:3a7713b1edbc 1183 {
AnnaBridge 171:3a7713b1edbc 1184 uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge 171:3a7713b1edbc 1185 This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge 171:3a7713b1edbc 1186
AnnaBridge 171:3a7713b1edbc 1187 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge 171:3a7713b1edbc 1190 This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge 171:3a7713b1edbc 1191
AnnaBridge 171:3a7713b1edbc 1192 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge 171:3a7713b1edbc 1193
AnnaBridge 171:3a7713b1edbc 1194
AnnaBridge 171:3a7713b1edbc 1195 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge 171:3a7713b1edbc 1196 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge 171:3a7713b1edbc 1197
AnnaBridge 171:3a7713b1edbc 1198 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge 171:3a7713b1edbc 1199
AnnaBridge 171:3a7713b1edbc 1200
AnnaBridge 171:3a7713b1edbc 1201 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge 171:3a7713b1edbc 1202 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge 171:3a7713b1edbc 1203
AnnaBridge 171:3a7713b1edbc 1204 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge 171:3a7713b1edbc 1205
AnnaBridge 171:3a7713b1edbc 1206
AnnaBridge 171:3a7713b1edbc 1207 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge 171:3a7713b1edbc 1208 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge 171:3a7713b1edbc 1209
AnnaBridge 171:3a7713b1edbc 1210 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge 171:3a7713b1edbc 1211 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge 171:3a7713b1edbc 1212
AnnaBridge 171:3a7713b1edbc 1213
AnnaBridge 171:3a7713b1edbc 1214 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge 171:3a7713b1edbc 1215 This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge 171:3a7713b1edbc 1216
AnnaBridge 171:3a7713b1edbc 1217 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge 171:3a7713b1edbc 1218
AnnaBridge 171:3a7713b1edbc 1219 } LL_I2S_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 1220
AnnaBridge 171:3a7713b1edbc 1221 /**
AnnaBridge 171:3a7713b1edbc 1222 * @}
AnnaBridge 171:3a7713b1edbc 1223 */
AnnaBridge 171:3a7713b1edbc 1224 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 171:3a7713b1edbc 1225
AnnaBridge 171:3a7713b1edbc 1226 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1227 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge 171:3a7713b1edbc 1228 * @{
AnnaBridge 171:3a7713b1edbc 1229 */
AnnaBridge 171:3a7713b1edbc 1230
AnnaBridge 171:3a7713b1edbc 1231 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 171:3a7713b1edbc 1232 * @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge 171:3a7713b1edbc 1233 * @{
AnnaBridge 171:3a7713b1edbc 1234 */
AnnaBridge 171:3a7713b1edbc 1235 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
AnnaBridge 171:3a7713b1edbc 1236 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
AnnaBridge 171:3a7713b1edbc 1237 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
AnnaBridge 171:3a7713b1edbc 1238 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
AnnaBridge 171:3a7713b1edbc 1239 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
AnnaBridge 171:3a7713b1edbc 1240 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
AnnaBridge 171:3a7713b1edbc 1241 /**
AnnaBridge 171:3a7713b1edbc 1242 * @}
AnnaBridge 171:3a7713b1edbc 1243 */
AnnaBridge 171:3a7713b1edbc 1244
AnnaBridge 171:3a7713b1edbc 1245 /** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge 171:3a7713b1edbc 1246 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge 171:3a7713b1edbc 1247 * @{
AnnaBridge 171:3a7713b1edbc 1248 */
AnnaBridge 171:3a7713b1edbc 1249 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
AnnaBridge 171:3a7713b1edbc 1250 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
AnnaBridge 171:3a7713b1edbc 1251 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
AnnaBridge 171:3a7713b1edbc 1252 /**
AnnaBridge 171:3a7713b1edbc 1253 * @}
AnnaBridge 171:3a7713b1edbc 1254 */
AnnaBridge 171:3a7713b1edbc 1255
AnnaBridge 171:3a7713b1edbc 1256 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge 171:3a7713b1edbc 1257 * @{
AnnaBridge 171:3a7713b1edbc 1258 */
AnnaBridge 171:3a7713b1edbc 1259 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
AnnaBridge 171:3a7713b1edbc 1260 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
AnnaBridge 171:3a7713b1edbc 1261 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
AnnaBridge 171:3a7713b1edbc 1262 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
AnnaBridge 171:3a7713b1edbc 1263 /**
AnnaBridge 171:3a7713b1edbc 1264 * @}
AnnaBridge 171:3a7713b1edbc 1265 */
AnnaBridge 171:3a7713b1edbc 1266
AnnaBridge 171:3a7713b1edbc 1267 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge 171:3a7713b1edbc 1268 * @{
AnnaBridge 171:3a7713b1edbc 1269 */
AnnaBridge 171:3a7713b1edbc 1270 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
AnnaBridge 171:3a7713b1edbc 1271 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
AnnaBridge 171:3a7713b1edbc 1272 /**
AnnaBridge 171:3a7713b1edbc 1273 * @}
AnnaBridge 171:3a7713b1edbc 1274 */
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge 171:3a7713b1edbc 1277 * @{
AnnaBridge 171:3a7713b1edbc 1278 */
AnnaBridge 171:3a7713b1edbc 1279 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
AnnaBridge 171:3a7713b1edbc 1280 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
AnnaBridge 171:3a7713b1edbc 1281 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
AnnaBridge 171:3a7713b1edbc 1282 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
AnnaBridge 171:3a7713b1edbc 1283 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
AnnaBridge 171:3a7713b1edbc 1284 /**
AnnaBridge 171:3a7713b1edbc 1285 * @}
AnnaBridge 171:3a7713b1edbc 1286 */
AnnaBridge 171:3a7713b1edbc 1287
AnnaBridge 171:3a7713b1edbc 1288 /** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge 171:3a7713b1edbc 1289 * @{
AnnaBridge 171:3a7713b1edbc 1290 */
AnnaBridge 171:3a7713b1edbc 1291 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
AnnaBridge 171:3a7713b1edbc 1292 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
AnnaBridge 171:3a7713b1edbc 1293 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
AnnaBridge 171:3a7713b1edbc 1294 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
AnnaBridge 171:3a7713b1edbc 1295 /**
AnnaBridge 171:3a7713b1edbc 1296 * @}
AnnaBridge 171:3a7713b1edbc 1297 */
AnnaBridge 171:3a7713b1edbc 1298
AnnaBridge 171:3a7713b1edbc 1299 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge 171:3a7713b1edbc 1300 * @{
AnnaBridge 171:3a7713b1edbc 1301 */
AnnaBridge 171:3a7713b1edbc 1302 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
AnnaBridge 171:3a7713b1edbc 1303 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
AnnaBridge 171:3a7713b1edbc 1304 /**
AnnaBridge 171:3a7713b1edbc 1305 * @}
AnnaBridge 171:3a7713b1edbc 1306 */
AnnaBridge 171:3a7713b1edbc 1307
AnnaBridge 171:3a7713b1edbc 1308 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 1309
AnnaBridge 171:3a7713b1edbc 1310 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge 171:3a7713b1edbc 1311 * @{
AnnaBridge 171:3a7713b1edbc 1312 */
AnnaBridge 171:3a7713b1edbc 1313 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
AnnaBridge 171:3a7713b1edbc 1314 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
AnnaBridge 171:3a7713b1edbc 1315 /**
AnnaBridge 171:3a7713b1edbc 1316 * @}
AnnaBridge 171:3a7713b1edbc 1317 */
AnnaBridge 171:3a7713b1edbc 1318
AnnaBridge 171:3a7713b1edbc 1319 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge 171:3a7713b1edbc 1320 * @{
AnnaBridge 171:3a7713b1edbc 1321 */
AnnaBridge 171:3a7713b1edbc 1322
AnnaBridge 171:3a7713b1edbc 1323 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
AnnaBridge 171:3a7713b1edbc 1324 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
AnnaBridge 171:3a7713b1edbc 1325 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
AnnaBridge 171:3a7713b1edbc 1326 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
AnnaBridge 171:3a7713b1edbc 1327 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
AnnaBridge 171:3a7713b1edbc 1328 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
AnnaBridge 171:3a7713b1edbc 1329 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
AnnaBridge 171:3a7713b1edbc 1330 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
AnnaBridge 171:3a7713b1edbc 1331 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
AnnaBridge 171:3a7713b1edbc 1332 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
AnnaBridge 171:3a7713b1edbc 1333 /**
AnnaBridge 171:3a7713b1edbc 1334 * @}
AnnaBridge 171:3a7713b1edbc 1335 */
AnnaBridge 171:3a7713b1edbc 1336 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 1337
AnnaBridge 171:3a7713b1edbc 1338 /**
AnnaBridge 171:3a7713b1edbc 1339 * @}
AnnaBridge 171:3a7713b1edbc 1340 */
AnnaBridge 171:3a7713b1edbc 1341
AnnaBridge 171:3a7713b1edbc 1342 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1343 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge 171:3a7713b1edbc 1344 * @{
AnnaBridge 171:3a7713b1edbc 1345 */
AnnaBridge 171:3a7713b1edbc 1346
AnnaBridge 171:3a7713b1edbc 1347 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 171:3a7713b1edbc 1348 * @{
AnnaBridge 171:3a7713b1edbc 1349 */
AnnaBridge 171:3a7713b1edbc 1350
AnnaBridge 171:3a7713b1edbc 1351 /**
AnnaBridge 171:3a7713b1edbc 1352 * @brief Write a value in I2S register
AnnaBridge 171:3a7713b1edbc 1353 * @param __INSTANCE__ I2S Instance
AnnaBridge 171:3a7713b1edbc 1354 * @param __REG__ Register to be written
AnnaBridge 171:3a7713b1edbc 1355 * @param __VALUE__ Value to be written in the register
AnnaBridge 171:3a7713b1edbc 1356 * @retval None
AnnaBridge 171:3a7713b1edbc 1357 */
AnnaBridge 171:3a7713b1edbc 1358 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 171:3a7713b1edbc 1359
AnnaBridge 171:3a7713b1edbc 1360 /**
AnnaBridge 171:3a7713b1edbc 1361 * @brief Read a value in I2S register
AnnaBridge 171:3a7713b1edbc 1362 * @param __INSTANCE__ I2S Instance
AnnaBridge 171:3a7713b1edbc 1363 * @param __REG__ Register to be read
AnnaBridge 171:3a7713b1edbc 1364 * @retval Register value
AnnaBridge 171:3a7713b1edbc 1365 */
AnnaBridge 171:3a7713b1edbc 1366 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 171:3a7713b1edbc 1367 /**
AnnaBridge 171:3a7713b1edbc 1368 * @}
AnnaBridge 171:3a7713b1edbc 1369 */
AnnaBridge 171:3a7713b1edbc 1370
AnnaBridge 171:3a7713b1edbc 1371 /**
AnnaBridge 171:3a7713b1edbc 1372 * @}
AnnaBridge 171:3a7713b1edbc 1373 */
AnnaBridge 171:3a7713b1edbc 1374
AnnaBridge 171:3a7713b1edbc 1375
AnnaBridge 171:3a7713b1edbc 1376 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1377
AnnaBridge 171:3a7713b1edbc 1378 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge 171:3a7713b1edbc 1379 * @{
AnnaBridge 171:3a7713b1edbc 1380 */
AnnaBridge 171:3a7713b1edbc 1381
AnnaBridge 171:3a7713b1edbc 1382 /** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge 171:3a7713b1edbc 1383 * @{
AnnaBridge 171:3a7713b1edbc 1384 */
AnnaBridge 171:3a7713b1edbc 1385
AnnaBridge 171:3a7713b1edbc 1386 /**
AnnaBridge 171:3a7713b1edbc 1387 * @brief Select I2S mode and Enable I2S peripheral
AnnaBridge 171:3a7713b1edbc 1388 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge 171:3a7713b1edbc 1389 * I2SCFGR I2SE LL_I2S_Enable
AnnaBridge 171:3a7713b1edbc 1390 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1391 * @retval None
AnnaBridge 171:3a7713b1edbc 1392 */
AnnaBridge 171:3a7713b1edbc 1393 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1394 {
AnnaBridge 171:3a7713b1edbc 1395 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
AnnaBridge 171:3a7713b1edbc 1396 }
AnnaBridge 171:3a7713b1edbc 1397
AnnaBridge 171:3a7713b1edbc 1398 /**
AnnaBridge 171:3a7713b1edbc 1399 * @brief Disable I2S peripheral
AnnaBridge 171:3a7713b1edbc 1400 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge 171:3a7713b1edbc 1401 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1402 * @retval None
AnnaBridge 171:3a7713b1edbc 1403 */
AnnaBridge 171:3a7713b1edbc 1404 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1405 {
AnnaBridge 171:3a7713b1edbc 1406 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
AnnaBridge 171:3a7713b1edbc 1407 }
AnnaBridge 171:3a7713b1edbc 1408
AnnaBridge 171:3a7713b1edbc 1409 /**
AnnaBridge 171:3a7713b1edbc 1410 * @brief Check if I2S peripheral is enabled
AnnaBridge 171:3a7713b1edbc 1411 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge 171:3a7713b1edbc 1412 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1413 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1414 */
AnnaBridge 171:3a7713b1edbc 1415 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1416 {
AnnaBridge 171:3a7713b1edbc 1417 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge 171:3a7713b1edbc 1418 }
AnnaBridge 171:3a7713b1edbc 1419
AnnaBridge 171:3a7713b1edbc 1420 /**
AnnaBridge 171:3a7713b1edbc 1421 * @brief Set I2S data frame length
AnnaBridge 171:3a7713b1edbc 1422 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge 171:3a7713b1edbc 1423 * I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge 171:3a7713b1edbc 1424 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1425 * @param DataFormat This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1426 * @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge 171:3a7713b1edbc 1427 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge 171:3a7713b1edbc 1428 * @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge 171:3a7713b1edbc 1429 * @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge 171:3a7713b1edbc 1430 * @retval None
AnnaBridge 171:3a7713b1edbc 1431 */
AnnaBridge 171:3a7713b1edbc 1432 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge 171:3a7713b1edbc 1433 {
AnnaBridge 171:3a7713b1edbc 1434 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge 171:3a7713b1edbc 1435 }
AnnaBridge 171:3a7713b1edbc 1436
AnnaBridge 171:3a7713b1edbc 1437 /**
AnnaBridge 171:3a7713b1edbc 1438 * @brief Get I2S data frame length
AnnaBridge 171:3a7713b1edbc 1439 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge 171:3a7713b1edbc 1440 * I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge 171:3a7713b1edbc 1441 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1442 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1443 * @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge 171:3a7713b1edbc 1444 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge 171:3a7713b1edbc 1445 * @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge 171:3a7713b1edbc 1446 * @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge 171:3a7713b1edbc 1447 */
AnnaBridge 171:3a7713b1edbc 1448 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1449 {
AnnaBridge 171:3a7713b1edbc 1450 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
AnnaBridge 171:3a7713b1edbc 1451 }
AnnaBridge 171:3a7713b1edbc 1452
AnnaBridge 171:3a7713b1edbc 1453 /**
AnnaBridge 171:3a7713b1edbc 1454 * @brief Set I2S clock polarity
AnnaBridge 171:3a7713b1edbc 1455 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge 171:3a7713b1edbc 1456 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1457 * @param ClockPolarity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1458 * @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge 171:3a7713b1edbc 1459 * @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge 171:3a7713b1edbc 1460 * @retval None
AnnaBridge 171:3a7713b1edbc 1461 */
AnnaBridge 171:3a7713b1edbc 1462 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge 171:3a7713b1edbc 1463 {
AnnaBridge 171:3a7713b1edbc 1464 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge 171:3a7713b1edbc 1465 }
AnnaBridge 171:3a7713b1edbc 1466
AnnaBridge 171:3a7713b1edbc 1467 /**
AnnaBridge 171:3a7713b1edbc 1468 * @brief Get I2S clock polarity
AnnaBridge 171:3a7713b1edbc 1469 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge 171:3a7713b1edbc 1470 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1471 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1472 * @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge 171:3a7713b1edbc 1473 * @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge 171:3a7713b1edbc 1474 */
AnnaBridge 171:3a7713b1edbc 1475 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1476 {
AnnaBridge 171:3a7713b1edbc 1477 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge 171:3a7713b1edbc 1478 }
AnnaBridge 171:3a7713b1edbc 1479
AnnaBridge 171:3a7713b1edbc 1480 /**
AnnaBridge 171:3a7713b1edbc 1481 * @brief Set I2S standard protocol
AnnaBridge 171:3a7713b1edbc 1482 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge 171:3a7713b1edbc 1483 * I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge 171:3a7713b1edbc 1484 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1485 * @param Standard This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1486 * @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge 171:3a7713b1edbc 1487 * @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge 171:3a7713b1edbc 1488 * @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge 171:3a7713b1edbc 1489 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge 171:3a7713b1edbc 1490 * @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge 171:3a7713b1edbc 1491 * @retval None
AnnaBridge 171:3a7713b1edbc 1492 */
AnnaBridge 171:3a7713b1edbc 1493 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge 171:3a7713b1edbc 1494 {
AnnaBridge 171:3a7713b1edbc 1495 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge 171:3a7713b1edbc 1496 }
AnnaBridge 171:3a7713b1edbc 1497
AnnaBridge 171:3a7713b1edbc 1498 /**
AnnaBridge 171:3a7713b1edbc 1499 * @brief Get I2S standard protocol
AnnaBridge 171:3a7713b1edbc 1500 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge 171:3a7713b1edbc 1501 * I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge 171:3a7713b1edbc 1502 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1503 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1504 * @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge 171:3a7713b1edbc 1505 * @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge 171:3a7713b1edbc 1506 * @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge 171:3a7713b1edbc 1507 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge 171:3a7713b1edbc 1508 * @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge 171:3a7713b1edbc 1509 */
AnnaBridge 171:3a7713b1edbc 1510 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1511 {
AnnaBridge 171:3a7713b1edbc 1512 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
AnnaBridge 171:3a7713b1edbc 1513 }
AnnaBridge 171:3a7713b1edbc 1514
AnnaBridge 171:3a7713b1edbc 1515 /**
AnnaBridge 171:3a7713b1edbc 1516 * @brief Set I2S transfer mode
AnnaBridge 171:3a7713b1edbc 1517 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge 171:3a7713b1edbc 1518 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1519 * @param Mode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1520 * @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge 171:3a7713b1edbc 1521 * @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge 171:3a7713b1edbc 1522 * @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge 171:3a7713b1edbc 1523 * @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge 171:3a7713b1edbc 1524 * @retval None
AnnaBridge 171:3a7713b1edbc 1525 */
AnnaBridge 171:3a7713b1edbc 1526 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge 171:3a7713b1edbc 1527 {
AnnaBridge 171:3a7713b1edbc 1528 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge 171:3a7713b1edbc 1529 }
AnnaBridge 171:3a7713b1edbc 1530
AnnaBridge 171:3a7713b1edbc 1531 /**
AnnaBridge 171:3a7713b1edbc 1532 * @brief Get I2S transfer mode
AnnaBridge 171:3a7713b1edbc 1533 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge 171:3a7713b1edbc 1534 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1535 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1536 * @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge 171:3a7713b1edbc 1537 * @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge 171:3a7713b1edbc 1538 * @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge 171:3a7713b1edbc 1539 * @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge 171:3a7713b1edbc 1540 */
AnnaBridge 171:3a7713b1edbc 1541 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1542 {
AnnaBridge 171:3a7713b1edbc 1543 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge 171:3a7713b1edbc 1544 }
AnnaBridge 171:3a7713b1edbc 1545
AnnaBridge 171:3a7713b1edbc 1546 /**
AnnaBridge 171:3a7713b1edbc 1547 * @brief Set I2S linear prescaler
AnnaBridge 171:3a7713b1edbc 1548 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge 171:3a7713b1edbc 1549 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1550 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 1551 * @retval None
AnnaBridge 171:3a7713b1edbc 1552 */
AnnaBridge 171:3a7713b1edbc 1553 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge 171:3a7713b1edbc 1554 {
AnnaBridge 171:3a7713b1edbc 1555 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge 171:3a7713b1edbc 1556 }
AnnaBridge 171:3a7713b1edbc 1557
AnnaBridge 171:3a7713b1edbc 1558 /**
AnnaBridge 171:3a7713b1edbc 1559 * @brief Get I2S linear prescaler
AnnaBridge 171:3a7713b1edbc 1560 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge 171:3a7713b1edbc 1561 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1562 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 1563 */
AnnaBridge 171:3a7713b1edbc 1564 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1565 {
AnnaBridge 171:3a7713b1edbc 1566 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge 171:3a7713b1edbc 1567 }
AnnaBridge 171:3a7713b1edbc 1568
AnnaBridge 171:3a7713b1edbc 1569 /**
AnnaBridge 171:3a7713b1edbc 1570 * @brief Set I2S parity prescaler
AnnaBridge 171:3a7713b1edbc 1571 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge 171:3a7713b1edbc 1572 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1573 * @param PrescalerParity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1574 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge 171:3a7713b1edbc 1575 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge 171:3a7713b1edbc 1576 * @retval None
AnnaBridge 171:3a7713b1edbc 1577 */
AnnaBridge 171:3a7713b1edbc 1578 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge 171:3a7713b1edbc 1579 {
AnnaBridge 171:3a7713b1edbc 1580 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge 171:3a7713b1edbc 1581 }
AnnaBridge 171:3a7713b1edbc 1582
AnnaBridge 171:3a7713b1edbc 1583 /**
AnnaBridge 171:3a7713b1edbc 1584 * @brief Get I2S parity prescaler
AnnaBridge 171:3a7713b1edbc 1585 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge 171:3a7713b1edbc 1586 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1587 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1588 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge 171:3a7713b1edbc 1589 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge 171:3a7713b1edbc 1590 */
AnnaBridge 171:3a7713b1edbc 1591 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1592 {
AnnaBridge 171:3a7713b1edbc 1593 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge 171:3a7713b1edbc 1594 }
AnnaBridge 171:3a7713b1edbc 1595
AnnaBridge 171:3a7713b1edbc 1596 /**
AnnaBridge 171:3a7713b1edbc 1597 * @brief Enable the master clock ouput (Pin MCK)
AnnaBridge 171:3a7713b1edbc 1598 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge 171:3a7713b1edbc 1599 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1600 * @retval None
AnnaBridge 171:3a7713b1edbc 1601 */
AnnaBridge 171:3a7713b1edbc 1602 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1603 {
AnnaBridge 171:3a7713b1edbc 1604 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge 171:3a7713b1edbc 1605 }
AnnaBridge 171:3a7713b1edbc 1606
AnnaBridge 171:3a7713b1edbc 1607 /**
AnnaBridge 171:3a7713b1edbc 1608 * @brief Disable the master clock ouput (Pin MCK)
AnnaBridge 171:3a7713b1edbc 1609 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge 171:3a7713b1edbc 1610 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1611 * @retval None
AnnaBridge 171:3a7713b1edbc 1612 */
AnnaBridge 171:3a7713b1edbc 1613 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1614 {
AnnaBridge 171:3a7713b1edbc 1615 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge 171:3a7713b1edbc 1616 }
AnnaBridge 171:3a7713b1edbc 1617
AnnaBridge 171:3a7713b1edbc 1618 /**
AnnaBridge 171:3a7713b1edbc 1619 * @brief Check if the master clock ouput (Pin MCK) is enabled
AnnaBridge 171:3a7713b1edbc 1620 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge 171:3a7713b1edbc 1621 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1622 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1623 */
AnnaBridge 171:3a7713b1edbc 1624 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1625 {
AnnaBridge 171:3a7713b1edbc 1626 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge 171:3a7713b1edbc 1627 }
AnnaBridge 171:3a7713b1edbc 1628
AnnaBridge 171:3a7713b1edbc 1629 /**
AnnaBridge 171:3a7713b1edbc 1630 * @}
AnnaBridge 171:3a7713b1edbc 1631 */
AnnaBridge 171:3a7713b1edbc 1632
AnnaBridge 171:3a7713b1edbc 1633 /** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge 171:3a7713b1edbc 1634 * @{
AnnaBridge 171:3a7713b1edbc 1635 */
AnnaBridge 171:3a7713b1edbc 1636
AnnaBridge 171:3a7713b1edbc 1637 /**
AnnaBridge 171:3a7713b1edbc 1638 * @brief Check if Rx buffer is not empty
AnnaBridge 171:3a7713b1edbc 1639 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge 171:3a7713b1edbc 1640 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1641 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1642 */
AnnaBridge 171:3a7713b1edbc 1643 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1644 {
AnnaBridge 171:3a7713b1edbc 1645 return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge 171:3a7713b1edbc 1646 }
AnnaBridge 171:3a7713b1edbc 1647
AnnaBridge 171:3a7713b1edbc 1648 /**
AnnaBridge 171:3a7713b1edbc 1649 * @brief Check if Tx buffer is empty
AnnaBridge 171:3a7713b1edbc 1650 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge 171:3a7713b1edbc 1651 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1652 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1653 */
AnnaBridge 171:3a7713b1edbc 1654 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1655 {
AnnaBridge 171:3a7713b1edbc 1656 return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge 171:3a7713b1edbc 1657 }
AnnaBridge 171:3a7713b1edbc 1658
AnnaBridge 171:3a7713b1edbc 1659 /**
AnnaBridge 171:3a7713b1edbc 1660 * @brief Get busy flag
AnnaBridge 171:3a7713b1edbc 1661 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge 171:3a7713b1edbc 1662 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1663 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1664 */
AnnaBridge 171:3a7713b1edbc 1665 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1666 {
AnnaBridge 171:3a7713b1edbc 1667 return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge 171:3a7713b1edbc 1668 }
AnnaBridge 171:3a7713b1edbc 1669
AnnaBridge 171:3a7713b1edbc 1670 /**
AnnaBridge 171:3a7713b1edbc 1671 * @brief Get overrun error flag
AnnaBridge 171:3a7713b1edbc 1672 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge 171:3a7713b1edbc 1673 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1674 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1675 */
AnnaBridge 171:3a7713b1edbc 1676 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1677 {
AnnaBridge 171:3a7713b1edbc 1678 return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge 171:3a7713b1edbc 1679 }
AnnaBridge 171:3a7713b1edbc 1680
AnnaBridge 171:3a7713b1edbc 1681 /**
AnnaBridge 171:3a7713b1edbc 1682 * @brief Get underrun error flag
AnnaBridge 171:3a7713b1edbc 1683 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge 171:3a7713b1edbc 1684 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1685 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1686 */
AnnaBridge 171:3a7713b1edbc 1687 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1688 {
AnnaBridge 171:3a7713b1edbc 1689 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge 171:3a7713b1edbc 1690 }
AnnaBridge 171:3a7713b1edbc 1691
AnnaBridge 171:3a7713b1edbc 1692 /**
AnnaBridge 171:3a7713b1edbc 1693 * @brief Get frame format error flag
AnnaBridge 171:3a7713b1edbc 1694 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
AnnaBridge 171:3a7713b1edbc 1695 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1696 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1697 */
AnnaBridge 171:3a7713b1edbc 1698 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1699 {
AnnaBridge 171:3a7713b1edbc 1700 return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge 171:3a7713b1edbc 1701 }
AnnaBridge 171:3a7713b1edbc 1702
AnnaBridge 171:3a7713b1edbc 1703 /**
AnnaBridge 171:3a7713b1edbc 1704 * @brief Get channel side flag.
AnnaBridge 171:3a7713b1edbc 1705 * @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge 171:3a7713b1edbc 1706 * 1: Channel Right has to be transmitted or has been received\n
AnnaBridge 171:3a7713b1edbc 1707 * It has no significance in PCM mode.
AnnaBridge 171:3a7713b1edbc 1708 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge 171:3a7713b1edbc 1709 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1710 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1711 */
AnnaBridge 171:3a7713b1edbc 1712 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1713 {
AnnaBridge 171:3a7713b1edbc 1714 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge 171:3a7713b1edbc 1715 }
AnnaBridge 171:3a7713b1edbc 1716
AnnaBridge 171:3a7713b1edbc 1717 /**
AnnaBridge 171:3a7713b1edbc 1718 * @brief Clear overrun error flag
AnnaBridge 171:3a7713b1edbc 1719 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge 171:3a7713b1edbc 1720 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1721 * @retval None
AnnaBridge 171:3a7713b1edbc 1722 */
AnnaBridge 171:3a7713b1edbc 1723 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1724 {
AnnaBridge 171:3a7713b1edbc 1725 LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge 171:3a7713b1edbc 1726 }
AnnaBridge 171:3a7713b1edbc 1727
AnnaBridge 171:3a7713b1edbc 1728 /**
AnnaBridge 171:3a7713b1edbc 1729 * @brief Clear underrun error flag
AnnaBridge 171:3a7713b1edbc 1730 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge 171:3a7713b1edbc 1731 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1732 * @retval None
AnnaBridge 171:3a7713b1edbc 1733 */
AnnaBridge 171:3a7713b1edbc 1734 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1735 {
AnnaBridge 171:3a7713b1edbc 1736 __IO uint32_t tmpreg;
AnnaBridge 171:3a7713b1edbc 1737 tmpreg = SPIx->SR;
AnnaBridge 171:3a7713b1edbc 1738 (void)tmpreg;
AnnaBridge 171:3a7713b1edbc 1739 }
AnnaBridge 171:3a7713b1edbc 1740
AnnaBridge 171:3a7713b1edbc 1741 /**
AnnaBridge 171:3a7713b1edbc 1742 * @brief Clear frame format error flag
AnnaBridge 171:3a7713b1edbc 1743 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
AnnaBridge 171:3a7713b1edbc 1744 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1745 * @retval None
AnnaBridge 171:3a7713b1edbc 1746 */
AnnaBridge 171:3a7713b1edbc 1747 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1748 {
AnnaBridge 171:3a7713b1edbc 1749 LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge 171:3a7713b1edbc 1750 }
AnnaBridge 171:3a7713b1edbc 1751
AnnaBridge 171:3a7713b1edbc 1752 /**
AnnaBridge 171:3a7713b1edbc 1753 * @}
AnnaBridge 171:3a7713b1edbc 1754 */
AnnaBridge 171:3a7713b1edbc 1755
AnnaBridge 171:3a7713b1edbc 1756 /** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge 171:3a7713b1edbc 1757 * @{
AnnaBridge 171:3a7713b1edbc 1758 */
AnnaBridge 171:3a7713b1edbc 1759
AnnaBridge 171:3a7713b1edbc 1760 /**
AnnaBridge 171:3a7713b1edbc 1761 * @brief Enable error IT
AnnaBridge 171:3a7713b1edbc 1762 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge 171:3a7713b1edbc 1763 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge 171:3a7713b1edbc 1764 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1765 * @retval None
AnnaBridge 171:3a7713b1edbc 1766 */
AnnaBridge 171:3a7713b1edbc 1767 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1768 {
AnnaBridge 171:3a7713b1edbc 1769 LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge 171:3a7713b1edbc 1770 }
AnnaBridge 171:3a7713b1edbc 1771
AnnaBridge 171:3a7713b1edbc 1772 /**
AnnaBridge 171:3a7713b1edbc 1773 * @brief Enable Rx buffer not empty IT
AnnaBridge 171:3a7713b1edbc 1774 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge 171:3a7713b1edbc 1775 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1776 * @retval None
AnnaBridge 171:3a7713b1edbc 1777 */
AnnaBridge 171:3a7713b1edbc 1778 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1779 {
AnnaBridge 171:3a7713b1edbc 1780 LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge 171:3a7713b1edbc 1781 }
AnnaBridge 171:3a7713b1edbc 1782
AnnaBridge 171:3a7713b1edbc 1783 /**
AnnaBridge 171:3a7713b1edbc 1784 * @brief Enable Tx buffer empty IT
AnnaBridge 171:3a7713b1edbc 1785 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge 171:3a7713b1edbc 1786 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1787 * @retval None
AnnaBridge 171:3a7713b1edbc 1788 */
AnnaBridge 171:3a7713b1edbc 1789 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1790 {
AnnaBridge 171:3a7713b1edbc 1791 LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge 171:3a7713b1edbc 1792 }
AnnaBridge 171:3a7713b1edbc 1793
AnnaBridge 171:3a7713b1edbc 1794 /**
AnnaBridge 171:3a7713b1edbc 1795 * @brief Disable error IT
AnnaBridge 171:3a7713b1edbc 1796 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge 171:3a7713b1edbc 1797 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge 171:3a7713b1edbc 1798 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1799 * @retval None
AnnaBridge 171:3a7713b1edbc 1800 */
AnnaBridge 171:3a7713b1edbc 1801 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1802 {
AnnaBridge 171:3a7713b1edbc 1803 LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge 171:3a7713b1edbc 1804 }
AnnaBridge 171:3a7713b1edbc 1805
AnnaBridge 171:3a7713b1edbc 1806 /**
AnnaBridge 171:3a7713b1edbc 1807 * @brief Disable Rx buffer not empty IT
AnnaBridge 171:3a7713b1edbc 1808 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge 171:3a7713b1edbc 1809 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1810 * @retval None
AnnaBridge 171:3a7713b1edbc 1811 */
AnnaBridge 171:3a7713b1edbc 1812 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1813 {
AnnaBridge 171:3a7713b1edbc 1814 LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge 171:3a7713b1edbc 1815 }
AnnaBridge 171:3a7713b1edbc 1816
AnnaBridge 171:3a7713b1edbc 1817 /**
AnnaBridge 171:3a7713b1edbc 1818 * @brief Disable Tx buffer empty IT
AnnaBridge 171:3a7713b1edbc 1819 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge 171:3a7713b1edbc 1820 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1821 * @retval None
AnnaBridge 171:3a7713b1edbc 1822 */
AnnaBridge 171:3a7713b1edbc 1823 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1824 {
AnnaBridge 171:3a7713b1edbc 1825 LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge 171:3a7713b1edbc 1826 }
AnnaBridge 171:3a7713b1edbc 1827
AnnaBridge 171:3a7713b1edbc 1828 /**
AnnaBridge 171:3a7713b1edbc 1829 * @brief Check if ERR IT is enabled
AnnaBridge 171:3a7713b1edbc 1830 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge 171:3a7713b1edbc 1831 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1832 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1833 */
AnnaBridge 171:3a7713b1edbc 1834 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1835 {
AnnaBridge 171:3a7713b1edbc 1836 return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge 171:3a7713b1edbc 1837 }
AnnaBridge 171:3a7713b1edbc 1838
AnnaBridge 171:3a7713b1edbc 1839 /**
AnnaBridge 171:3a7713b1edbc 1840 * @brief Check if RXNE IT is enabled
AnnaBridge 171:3a7713b1edbc 1841 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge 171:3a7713b1edbc 1842 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1843 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1844 */
AnnaBridge 171:3a7713b1edbc 1845 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1846 {
AnnaBridge 171:3a7713b1edbc 1847 return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge 171:3a7713b1edbc 1848 }
AnnaBridge 171:3a7713b1edbc 1849
AnnaBridge 171:3a7713b1edbc 1850 /**
AnnaBridge 171:3a7713b1edbc 1851 * @brief Check if TXE IT is enabled
AnnaBridge 171:3a7713b1edbc 1852 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge 171:3a7713b1edbc 1853 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1854 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1855 */
AnnaBridge 171:3a7713b1edbc 1856 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1857 {
AnnaBridge 171:3a7713b1edbc 1858 return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge 171:3a7713b1edbc 1859 }
AnnaBridge 171:3a7713b1edbc 1860
AnnaBridge 171:3a7713b1edbc 1861 /**
AnnaBridge 171:3a7713b1edbc 1862 * @}
AnnaBridge 171:3a7713b1edbc 1863 */
AnnaBridge 171:3a7713b1edbc 1864
AnnaBridge 171:3a7713b1edbc 1865 /** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge 171:3a7713b1edbc 1866 * @{
AnnaBridge 171:3a7713b1edbc 1867 */
AnnaBridge 171:3a7713b1edbc 1868
AnnaBridge 171:3a7713b1edbc 1869 /**
AnnaBridge 171:3a7713b1edbc 1870 * @brief Enable DMA Rx
AnnaBridge 171:3a7713b1edbc 1871 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge 171:3a7713b1edbc 1872 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1873 * @retval None
AnnaBridge 171:3a7713b1edbc 1874 */
AnnaBridge 171:3a7713b1edbc 1875 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1876 {
AnnaBridge 171:3a7713b1edbc 1877 LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge 171:3a7713b1edbc 1878 }
AnnaBridge 171:3a7713b1edbc 1879
AnnaBridge 171:3a7713b1edbc 1880 /**
AnnaBridge 171:3a7713b1edbc 1881 * @brief Disable DMA Rx
AnnaBridge 171:3a7713b1edbc 1882 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge 171:3a7713b1edbc 1883 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1884 * @retval None
AnnaBridge 171:3a7713b1edbc 1885 */
AnnaBridge 171:3a7713b1edbc 1886 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1887 {
AnnaBridge 171:3a7713b1edbc 1888 LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge 171:3a7713b1edbc 1889 }
AnnaBridge 171:3a7713b1edbc 1890
AnnaBridge 171:3a7713b1edbc 1891 /**
AnnaBridge 171:3a7713b1edbc 1892 * @brief Check if DMA Rx is enabled
AnnaBridge 171:3a7713b1edbc 1893 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge 171:3a7713b1edbc 1894 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1895 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1896 */
AnnaBridge 171:3a7713b1edbc 1897 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1898 {
AnnaBridge 171:3a7713b1edbc 1899 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge 171:3a7713b1edbc 1900 }
AnnaBridge 171:3a7713b1edbc 1901
AnnaBridge 171:3a7713b1edbc 1902 /**
AnnaBridge 171:3a7713b1edbc 1903 * @brief Enable DMA Tx
AnnaBridge 171:3a7713b1edbc 1904 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge 171:3a7713b1edbc 1905 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1906 * @retval None
AnnaBridge 171:3a7713b1edbc 1907 */
AnnaBridge 171:3a7713b1edbc 1908 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1909 {
AnnaBridge 171:3a7713b1edbc 1910 LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge 171:3a7713b1edbc 1911 }
AnnaBridge 171:3a7713b1edbc 1912
AnnaBridge 171:3a7713b1edbc 1913 /**
AnnaBridge 171:3a7713b1edbc 1914 * @brief Disable DMA Tx
AnnaBridge 171:3a7713b1edbc 1915 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge 171:3a7713b1edbc 1916 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1917 * @retval None
AnnaBridge 171:3a7713b1edbc 1918 */
AnnaBridge 171:3a7713b1edbc 1919 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1920 {
AnnaBridge 171:3a7713b1edbc 1921 LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge 171:3a7713b1edbc 1922 }
AnnaBridge 171:3a7713b1edbc 1923
AnnaBridge 171:3a7713b1edbc 1924 /**
AnnaBridge 171:3a7713b1edbc 1925 * @brief Check if DMA Tx is enabled
AnnaBridge 171:3a7713b1edbc 1926 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge 171:3a7713b1edbc 1927 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1928 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1929 */
AnnaBridge 171:3a7713b1edbc 1930 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1931 {
AnnaBridge 171:3a7713b1edbc 1932 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge 171:3a7713b1edbc 1933 }
AnnaBridge 171:3a7713b1edbc 1934
AnnaBridge 171:3a7713b1edbc 1935 /**
AnnaBridge 171:3a7713b1edbc 1936 * @}
AnnaBridge 171:3a7713b1edbc 1937 */
AnnaBridge 171:3a7713b1edbc 1938
AnnaBridge 171:3a7713b1edbc 1939 /** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge 171:3a7713b1edbc 1940 * @{
AnnaBridge 171:3a7713b1edbc 1941 */
AnnaBridge 171:3a7713b1edbc 1942
AnnaBridge 171:3a7713b1edbc 1943 /**
AnnaBridge 171:3a7713b1edbc 1944 * @brief Read 16-Bits in data register
AnnaBridge 171:3a7713b1edbc 1945 * @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge 171:3a7713b1edbc 1946 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1947 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 1948 */
AnnaBridge 171:3a7713b1edbc 1949 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge 171:3a7713b1edbc 1950 {
AnnaBridge 171:3a7713b1edbc 1951 return LL_SPI_ReceiveData16(SPIx);
AnnaBridge 171:3a7713b1edbc 1952 }
AnnaBridge 171:3a7713b1edbc 1953
AnnaBridge 171:3a7713b1edbc 1954 /**
AnnaBridge 171:3a7713b1edbc 1955 * @brief Write 16-Bits in data register
AnnaBridge 171:3a7713b1edbc 1956 * @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge 171:3a7713b1edbc 1957 * @param SPIx SPI Instance
AnnaBridge 171:3a7713b1edbc 1958 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 1959 * @retval None
AnnaBridge 171:3a7713b1edbc 1960 */
AnnaBridge 171:3a7713b1edbc 1961 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge 171:3a7713b1edbc 1962 {
AnnaBridge 171:3a7713b1edbc 1963 LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge 171:3a7713b1edbc 1964 }
AnnaBridge 171:3a7713b1edbc 1965
AnnaBridge 171:3a7713b1edbc 1966 /**
AnnaBridge 171:3a7713b1edbc 1967 * @}
AnnaBridge 171:3a7713b1edbc 1968 */
AnnaBridge 171:3a7713b1edbc 1969
AnnaBridge 171:3a7713b1edbc 1970 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 1971 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 1972 * @{
AnnaBridge 171:3a7713b1edbc 1973 */
AnnaBridge 171:3a7713b1edbc 1974
AnnaBridge 171:3a7713b1edbc 1975 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge 171:3a7713b1edbc 1976 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge 171:3a7713b1edbc 1977 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge 171:3a7713b1edbc 1978 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge 171:3a7713b1edbc 1979
AnnaBridge 171:3a7713b1edbc 1980 /**
AnnaBridge 171:3a7713b1edbc 1981 * @}
AnnaBridge 171:3a7713b1edbc 1982 */
AnnaBridge 171:3a7713b1edbc 1983 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 1984
AnnaBridge 171:3a7713b1edbc 1985 /**
AnnaBridge 171:3a7713b1edbc 1986 * @}
AnnaBridge 171:3a7713b1edbc 1987 */
AnnaBridge 171:3a7713b1edbc 1988
AnnaBridge 171:3a7713b1edbc 1989 /**
AnnaBridge 171:3a7713b1edbc 1990 * @}
AnnaBridge 171:3a7713b1edbc 1991 */
AnnaBridge 171:3a7713b1edbc 1992 #endif /* SPI_I2S_SUPPORT */
AnnaBridge 171:3a7713b1edbc 1993
AnnaBridge 171:3a7713b1edbc 1994 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
AnnaBridge 171:3a7713b1edbc 1995
AnnaBridge 171:3a7713b1edbc 1996 /**
AnnaBridge 171:3a7713b1edbc 1997 * @}
AnnaBridge 171:3a7713b1edbc 1998 */
AnnaBridge 171:3a7713b1edbc 1999
AnnaBridge 171:3a7713b1edbc 2000 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 2001 }
AnnaBridge 171:3a7713b1edbc 2002 #endif
AnnaBridge 171:3a7713b1edbc 2003
AnnaBridge 171:3a7713b1edbc 2004 #endif /* __STM32L1xx_LL_SPI_H */
AnnaBridge 171:3a7713b1edbc 2005
AnnaBridge 171:3a7713b1edbc 2006 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/