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TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32l1xx_ll_dma.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of DMA LL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32L1xx_LL_DMA_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32L1xx_LL_DMA_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32l1xx.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32L1xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @defgroup DMA_LL DMA
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	171:3a7713b1edbc	60	* @{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62	/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge	171:3a7713b1edbc	63	static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge	171:3a7713b1edbc	64	{
AnnaBridge	171:3a7713b1edbc	65	(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge	171:3a7713b1edbc	66	(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge	171:3a7713b1edbc	67	(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge	171:3a7713b1edbc	68	(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge	171:3a7713b1edbc	69	(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge	171:3a7713b1edbc	70	(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge	171:3a7713b1edbc	71	(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge	171:3a7713b1edbc	72	};
AnnaBridge	171:3a7713b1edbc	73	/**
AnnaBridge	171:3a7713b1edbc	74	* @}
AnnaBridge	171:3a7713b1edbc	75	*/
AnnaBridge	171:3a7713b1edbc	76
AnnaBridge	171:3a7713b1edbc	77	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	78
AnnaBridge	171:3a7713b1edbc	79	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	80	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	81	/** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge	171:3a7713b1edbc	82	* @{
AnnaBridge	171:3a7713b1edbc	83	*/
AnnaBridge	171:3a7713b1edbc	84	/**
AnnaBridge	171:3a7713b1edbc	85	* @}
AnnaBridge	171:3a7713b1edbc	86	*/
AnnaBridge	171:3a7713b1edbc	87	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	90	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	91	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	171:3a7713b1edbc	92	* @{
AnnaBridge	171:3a7713b1edbc	93	*/
AnnaBridge	171:3a7713b1edbc	94	typedef struct
AnnaBridge	171:3a7713b1edbc	95	{
AnnaBridge	171:3a7713b1edbc	96	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	171:3a7713b1edbc	97	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	171:3a7713b1edbc	98
AnnaBridge	171:3a7713b1edbc	99	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	171:3a7713b1edbc	102	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	171:3a7713b1edbc	105
AnnaBridge	171:3a7713b1edbc	106	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	171:3a7713b1edbc	107	from memory to memory or from peripheral to memory.
AnnaBridge	171:3a7713b1edbc	108	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	171:3a7713b1edbc	111
AnnaBridge	171:3a7713b1edbc	112	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	171:3a7713b1edbc	113	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	171:3a7713b1edbc	114	@note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge	171:3a7713b1edbc	115	data transfer direction is configured on the selected Channel
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	171:3a7713b1edbc	118
AnnaBridge	171:3a7713b1edbc	119	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	171:3a7713b1edbc	120	is incremented or not.
AnnaBridge	171:3a7713b1edbc	121	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	171:3a7713b1edbc	122
AnnaBridge	171:3a7713b1edbc	123	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	171:3a7713b1edbc	124
AnnaBridge	171:3a7713b1edbc	125	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	171:3a7713b1edbc	126	is incremented or not.
AnnaBridge	171:3a7713b1edbc	127	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	171:3a7713b1edbc	130
AnnaBridge	171:3a7713b1edbc	131	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	171:3a7713b1edbc	132	in case of memory to memory transfer direction.
AnnaBridge	171:3a7713b1edbc	133	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	171:3a7713b1edbc	136
AnnaBridge	171:3a7713b1edbc	137	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	171:3a7713b1edbc	138	in case of memory to memory transfer direction.
AnnaBridge	171:3a7713b1edbc	139	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	171:3a7713b1edbc	140
AnnaBridge	171:3a7713b1edbc	141	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	171:3a7713b1edbc	142
AnnaBridge	171:3a7713b1edbc	143	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	171:3a7713b1edbc	144	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	171:3a7713b1edbc	145	or MemorySize parameters depending in the transfer direction.
AnnaBridge	171:3a7713b1edbc	146	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	171:3a7713b1edbc	147
AnnaBridge	171:3a7713b1edbc	148	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	171:3a7713b1edbc	149
AnnaBridge	171:3a7713b1edbc	150	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	171:3a7713b1edbc	151	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	171:3a7713b1edbc	152
AnnaBridge	171:3a7713b1edbc	153	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge	171:3a7713b1edbc	154
AnnaBridge	171:3a7713b1edbc	155	} LL_DMA_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	156	/**
AnnaBridge	171:3a7713b1edbc	157	* @}
AnnaBridge	171:3a7713b1edbc	158	*/
AnnaBridge	171:3a7713b1edbc	159	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	171:3a7713b1edbc	160
AnnaBridge	171:3a7713b1edbc	161	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	162	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	171:3a7713b1edbc	163	* @{
AnnaBridge	171:3a7713b1edbc	164	*/
AnnaBridge	171:3a7713b1edbc	165	/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	171:3a7713b1edbc	166	* @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge	171:3a7713b1edbc	167	* @{
AnnaBridge	171:3a7713b1edbc	168	*/
AnnaBridge	171:3a7713b1edbc	169	#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /!< Channel 1 global flag /
AnnaBridge	171:3a7713b1edbc	170	#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	171	#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	171:3a7713b1edbc	172	#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	171:3a7713b1edbc	173	#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /!< Channel 2 global flag /
AnnaBridge	171:3a7713b1edbc	174	#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	175	#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	171:3a7713b1edbc	176	#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	171:3a7713b1edbc	177	#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /!< Channel 3 global flag /
AnnaBridge	171:3a7713b1edbc	178	#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	179	#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	171:3a7713b1edbc	180	#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	171:3a7713b1edbc	181	#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /!< Channel 4 global flag /
AnnaBridge	171:3a7713b1edbc	182	#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	183	#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	171:3a7713b1edbc	184	#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	171:3a7713b1edbc	185	#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /!< Channel 5 global flag /
AnnaBridge	171:3a7713b1edbc	186	#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	187	#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	171:3a7713b1edbc	188	#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	171:3a7713b1edbc	189	#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /!< Channel 6 global flag /
AnnaBridge	171:3a7713b1edbc	190	#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	191	#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	171:3a7713b1edbc	192	#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	171:3a7713b1edbc	193	#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /!< Channel 7 global flag /
AnnaBridge	171:3a7713b1edbc	194	#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	195	#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	171:3a7713b1edbc	196	#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	171:3a7713b1edbc	197	/**
AnnaBridge	171:3a7713b1edbc	198	* @}
AnnaBridge	171:3a7713b1edbc	199	*/
AnnaBridge	171:3a7713b1edbc	200
AnnaBridge	171:3a7713b1edbc	201	/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	171:3a7713b1edbc	202	* @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge	171:3a7713b1edbc	203	* @{
AnnaBridge	171:3a7713b1edbc	204	*/
AnnaBridge	171:3a7713b1edbc	205	#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /!< Channel 1 global flag /
AnnaBridge	171:3a7713b1edbc	206	#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /!< Channel 1 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	207	#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /!< Channel 1 half transfer flag /
AnnaBridge	171:3a7713b1edbc	208	#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /!< Channel 1 transfer error flag /
AnnaBridge	171:3a7713b1edbc	209	#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /!< Channel 2 global flag /
AnnaBridge	171:3a7713b1edbc	210	#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /!< Channel 2 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	211	#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /!< Channel 2 half transfer flag /
AnnaBridge	171:3a7713b1edbc	212	#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /!< Channel 2 transfer error flag /
AnnaBridge	171:3a7713b1edbc	213	#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /!< Channel 3 global flag /
AnnaBridge	171:3a7713b1edbc	214	#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /!< Channel 3 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	215	#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /!< Channel 3 half transfer flag /
AnnaBridge	171:3a7713b1edbc	216	#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /!< Channel 3 transfer error flag /
AnnaBridge	171:3a7713b1edbc	217	#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /!< Channel 4 global flag /
AnnaBridge	171:3a7713b1edbc	218	#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /!< Channel 4 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	219	#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /!< Channel 4 half transfer flag /
AnnaBridge	171:3a7713b1edbc	220	#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /!< Channel 4 transfer error flag /
AnnaBridge	171:3a7713b1edbc	221	#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /!< Channel 5 global flag /
AnnaBridge	171:3a7713b1edbc	222	#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /!< Channel 5 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	223	#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /!< Channel 5 half transfer flag /
AnnaBridge	171:3a7713b1edbc	224	#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /!< Channel 5 transfer error flag /
AnnaBridge	171:3a7713b1edbc	225	#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /!< Channel 6 global flag /
AnnaBridge	171:3a7713b1edbc	226	#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /!< Channel 6 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	227	#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /!< Channel 6 half transfer flag /
AnnaBridge	171:3a7713b1edbc	228	#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /!< Channel 6 transfer error flag /
AnnaBridge	171:3a7713b1edbc	229	#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /!< Channel 7 global flag /
AnnaBridge	171:3a7713b1edbc	230	#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /!< Channel 7 transfer complete flag /
AnnaBridge	171:3a7713b1edbc	231	#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /!< Channel 7 half transfer flag /
AnnaBridge	171:3a7713b1edbc	232	#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /!< Channel 7 transfer error flag /
AnnaBridge	171:3a7713b1edbc	233	/**
AnnaBridge	171:3a7713b1edbc	234	* @}
AnnaBridge	171:3a7713b1edbc	235	*/
AnnaBridge	171:3a7713b1edbc	236
AnnaBridge	171:3a7713b1edbc	237	/** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge	171:3a7713b1edbc	238	* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge	171:3a7713b1edbc	239	* @{
AnnaBridge	171:3a7713b1edbc	240	*/
AnnaBridge	171:3a7713b1edbc	241	#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /!< Transfer complete interrupt /
AnnaBridge	171:3a7713b1edbc	242	#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /!< Half Transfer interrupt /
AnnaBridge	171:3a7713b1edbc	243	#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /!< Transfer error interrupt /
AnnaBridge	171:3a7713b1edbc	244	/**
AnnaBridge	171:3a7713b1edbc	245	* @}
AnnaBridge	171:3a7713b1edbc	246	*/
AnnaBridge	171:3a7713b1edbc	247
AnnaBridge	171:3a7713b1edbc	248	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	171:3a7713b1edbc	249	* @{
AnnaBridge	171:3a7713b1edbc	250	*/
AnnaBridge	171:3a7713b1edbc	251	#define LL_DMA_CHANNEL_1 0x00000001U /!< DMA Channel 1 /
AnnaBridge	171:3a7713b1edbc	252	#define LL_DMA_CHANNEL_2 0x00000002U /!< DMA Channel 2 /
AnnaBridge	171:3a7713b1edbc	253	#define LL_DMA_CHANNEL_3 0x00000003U /!< DMA Channel 3 /
AnnaBridge	171:3a7713b1edbc	254	#define LL_DMA_CHANNEL_4 0x00000004U /!< DMA Channel 4 /
AnnaBridge	171:3a7713b1edbc	255	#define LL_DMA_CHANNEL_5 0x00000005U /!< DMA Channel 5 /
AnnaBridge	171:3a7713b1edbc	256	#define LL_DMA_CHANNEL_6 0x00000006U /!< DMA Channel 6 /
AnnaBridge	171:3a7713b1edbc	257	#define LL_DMA_CHANNEL_7 0x00000007U /!< DMA Channel 7 /
AnnaBridge	171:3a7713b1edbc	258	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	259	#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). /
AnnaBridge	171:3a7713b1edbc	260	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	171:3a7713b1edbc	261	/**
AnnaBridge	171:3a7713b1edbc	262	* @}
AnnaBridge	171:3a7713b1edbc	263	*/
AnnaBridge	171:3a7713b1edbc	264
AnnaBridge	171:3a7713b1edbc	265	/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge	171:3a7713b1edbc	266	* @{
AnnaBridge	171:3a7713b1edbc	267	*/
AnnaBridge	171:3a7713b1edbc	268	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	171:3a7713b1edbc	269	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /!< Memory to peripheral direction /
AnnaBridge	171:3a7713b1edbc	270	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /!< Memory to memory direction /
AnnaBridge	171:3a7713b1edbc	271	/**
AnnaBridge	171:3a7713b1edbc	272	* @}
AnnaBridge	171:3a7713b1edbc	273	*/
AnnaBridge	171:3a7713b1edbc	274
AnnaBridge	171:3a7713b1edbc	275	/** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge	171:3a7713b1edbc	276	* @{
AnnaBridge	171:3a7713b1edbc	277	*/
AnnaBridge	171:3a7713b1edbc	278	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	171:3a7713b1edbc	279	#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /!< Circular Mode /
AnnaBridge	171:3a7713b1edbc	280	/**
AnnaBridge	171:3a7713b1edbc	281	* @}
AnnaBridge	171:3a7713b1edbc	282	*/
AnnaBridge	171:3a7713b1edbc	283
AnnaBridge	171:3a7713b1edbc	284	/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge	171:3a7713b1edbc	285	* @{
AnnaBridge	171:3a7713b1edbc	286	*/
AnnaBridge	171:3a7713b1edbc	287	#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	171:3a7713b1edbc	288	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	171:3a7713b1edbc	289	/**
AnnaBridge	171:3a7713b1edbc	290	* @}
AnnaBridge	171:3a7713b1edbc	291	*/
AnnaBridge	171:3a7713b1edbc	292
AnnaBridge	171:3a7713b1edbc	293	/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge	171:3a7713b1edbc	294	* @{
AnnaBridge	171:3a7713b1edbc	295	*/
AnnaBridge	171:3a7713b1edbc	296	#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /!< Memory increment mode Enable /
AnnaBridge	171:3a7713b1edbc	297	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	171:3a7713b1edbc	298	/**
AnnaBridge	171:3a7713b1edbc	299	* @}
AnnaBridge	171:3a7713b1edbc	300	*/
AnnaBridge	171:3a7713b1edbc	301
AnnaBridge	171:3a7713b1edbc	302	/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge	171:3a7713b1edbc	303	* @{
AnnaBridge	171:3a7713b1edbc	304	*/
AnnaBridge	171:3a7713b1edbc	305	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	171:3a7713b1edbc	306	#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	171:3a7713b1edbc	307	#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	171:3a7713b1edbc	308	/**
AnnaBridge	171:3a7713b1edbc	309	* @}
AnnaBridge	171:3a7713b1edbc	310	*/
AnnaBridge	171:3a7713b1edbc	311
AnnaBridge	171:3a7713b1edbc	312	/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge	171:3a7713b1edbc	313	* @{
AnnaBridge	171:3a7713b1edbc	314	*/
AnnaBridge	171:3a7713b1edbc	315	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	171:3a7713b1edbc	316	#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	171:3a7713b1edbc	317	#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	171:3a7713b1edbc	318	/**
AnnaBridge	171:3a7713b1edbc	319	* @}
AnnaBridge	171:3a7713b1edbc	320	*/
AnnaBridge	171:3a7713b1edbc	321
AnnaBridge	171:3a7713b1edbc	322	/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge	171:3a7713b1edbc	323	* @{
AnnaBridge	171:3a7713b1edbc	324	*/
AnnaBridge	171:3a7713b1edbc	325	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	171:3a7713b1edbc	326	#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /!< Priority level : Medium /
AnnaBridge	171:3a7713b1edbc	327	#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /!< Priority level : High /
AnnaBridge	171:3a7713b1edbc	328	#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /!< Priority level : Very_High /
AnnaBridge	171:3a7713b1edbc	329	/**
AnnaBridge	171:3a7713b1edbc	330	* @}
AnnaBridge	171:3a7713b1edbc	331	*/
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333
AnnaBridge	171:3a7713b1edbc	334	/**
AnnaBridge	171:3a7713b1edbc	335	* @}
AnnaBridge	171:3a7713b1edbc	336	*/
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	339	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	171:3a7713b1edbc	340	* @{
AnnaBridge	171:3a7713b1edbc	341	*/
AnnaBridge	171:3a7713b1edbc	342
AnnaBridge	171:3a7713b1edbc	343	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	171:3a7713b1edbc	344	* @{
AnnaBridge	171:3a7713b1edbc	345	*/
AnnaBridge	171:3a7713b1edbc	346	/**
AnnaBridge	171:3a7713b1edbc	347	* @brief Write a value in DMA register
AnnaBridge	171:3a7713b1edbc	348	* @param __INSTANCE__ DMA Instance
AnnaBridge	171:3a7713b1edbc	349	* @param __REG__ Register to be written
AnnaBridge	171:3a7713b1edbc	350	* @param __VALUE__ Value to be written in the register
AnnaBridge	171:3a7713b1edbc	351	* @retval None
AnnaBridge	171:3a7713b1edbc	352	*/
AnnaBridge	171:3a7713b1edbc	353	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	/**
AnnaBridge	171:3a7713b1edbc	356	* @brief Read a value in DMA register
AnnaBridge	171:3a7713b1edbc	357	* @param __INSTANCE__ DMA Instance
AnnaBridge	171:3a7713b1edbc	358	* @param __REG__ Register to be read
AnnaBridge	171:3a7713b1edbc	359	* @retval Register value
AnnaBridge	171:3a7713b1edbc	360	*/
AnnaBridge	171:3a7713b1edbc	361	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	171:3a7713b1edbc	362	/**
AnnaBridge	171:3a7713b1edbc	363	* @}
AnnaBridge	171:3a7713b1edbc	364	*/
AnnaBridge	171:3a7713b1edbc	365
AnnaBridge	171:3a7713b1edbc	366	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge	171:3a7713b1edbc	367	* @{
AnnaBridge	171:3a7713b1edbc	368	*/
AnnaBridge	171:3a7713b1edbc	369	/**
AnnaBridge	171:3a7713b1edbc	370	* @brief Convert DMAx_Channely into DMAx
AnnaBridge	171:3a7713b1edbc	371	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	171:3a7713b1edbc	372	* @retval DMAx
AnnaBridge	171:3a7713b1edbc	373	*/
AnnaBridge	171:3a7713b1edbc	374	#if defined(DMA2)
AnnaBridge	171:3a7713b1edbc	375	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge	171:3a7713b1edbc	376	(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge	171:3a7713b1edbc	377	#else
AnnaBridge	171:3a7713b1edbc	378	#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge	171:3a7713b1edbc	379	#endif
AnnaBridge	171:3a7713b1edbc	380
AnnaBridge	171:3a7713b1edbc	381	/**
AnnaBridge	171:3a7713b1edbc	382	* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge	171:3a7713b1edbc	383	* @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge	171:3a7713b1edbc	384	* @retval LL_DMA_CHANNEL_y
AnnaBridge	171:3a7713b1edbc	385	*/
AnnaBridge	171:3a7713b1edbc	386	#if defined (DMA2)
AnnaBridge	171:3a7713b1edbc	387	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	171:3a7713b1edbc	388	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	171:3a7713b1edbc	389	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	171:3a7713b1edbc	390	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	171:3a7713b1edbc	391	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	171:3a7713b1edbc	392	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	171:3a7713b1edbc	393	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	171:3a7713b1edbc	394	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	171:3a7713b1edbc	395	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	171:3a7713b1edbc	396	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	171:3a7713b1edbc	397	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	171:3a7713b1edbc	398	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	171:3a7713b1edbc	399	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	171:3a7713b1edbc	400	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	171:3a7713b1edbc	401	LL_DMA_CHANNEL_7)
AnnaBridge	171:3a7713b1edbc	402	#else
AnnaBridge	171:3a7713b1edbc	403	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	171:3a7713b1edbc	404	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	171:3a7713b1edbc	405	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	171:3a7713b1edbc	406	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	171:3a7713b1edbc	407	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	171:3a7713b1edbc	408	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	171:3a7713b1edbc	409	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	171:3a7713b1edbc	410	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	171:3a7713b1edbc	411	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	171:3a7713b1edbc	412	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	171:3a7713b1edbc	413	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	171:3a7713b1edbc	414	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	171:3a7713b1edbc	415	LL_DMA_CHANNEL_7)
AnnaBridge	171:3a7713b1edbc	416	#endif
AnnaBridge	171:3a7713b1edbc	417	#else
AnnaBridge	171:3a7713b1edbc	418	#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge	171:3a7713b1edbc	419	(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge	171:3a7713b1edbc	420	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge	171:3a7713b1edbc	421	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge	171:3a7713b1edbc	422	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge	171:3a7713b1edbc	423	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge	171:3a7713b1edbc	424	((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge	171:3a7713b1edbc	425	LL_DMA_CHANNEL_7)
AnnaBridge	171:3a7713b1edbc	426	#endif
AnnaBridge	171:3a7713b1edbc	427
AnnaBridge	171:3a7713b1edbc	428	/**
AnnaBridge	171:3a7713b1edbc	429	* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge	171:3a7713b1edbc	430	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	171:3a7713b1edbc	431	* @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge	171:3a7713b1edbc	432	* @retval DMAx_Channely
AnnaBridge	171:3a7713b1edbc	433	*/
AnnaBridge	171:3a7713b1edbc	434	#if defined (DMA2)
AnnaBridge	171:3a7713b1edbc	435	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
AnnaBridge	171:3a7713b1edbc	436	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	437	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	171:3a7713b1edbc	438	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	171:3a7713b1edbc	439	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	171:3a7713b1edbc	440	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	171:3a7713b1edbc	441	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	171:3a7713b1edbc	442	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	171:3a7713b1edbc	443	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	171:3a7713b1edbc	444	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	171:3a7713b1edbc	445	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	171:3a7713b1edbc	446	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	171:3a7713b1edbc	447	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	171:3a7713b1edbc	448	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
AnnaBridge	171:3a7713b1edbc	449	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
AnnaBridge	171:3a7713b1edbc	450	DMA2_Channel7)
AnnaBridge	171:3a7713b1edbc	451	#else
AnnaBridge	171:3a7713b1edbc	452	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	453	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	171:3a7713b1edbc	454	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge	171:3a7713b1edbc	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	171:3a7713b1edbc	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge	171:3a7713b1edbc	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	171:3a7713b1edbc	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge	171:3a7713b1edbc	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	171:3a7713b1edbc	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge	171:3a7713b1edbc	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	171:3a7713b1edbc	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge	171:3a7713b1edbc	463	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	171:3a7713b1edbc	464	DMA1_Channel7)
AnnaBridge	171:3a7713b1edbc	465	#endif
AnnaBridge	171:3a7713b1edbc	466	#else
AnnaBridge	171:3a7713b1edbc	467	#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	468	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge	171:3a7713b1edbc	469	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge	171:3a7713b1edbc	470	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge	171:3a7713b1edbc	471	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge	171:3a7713b1edbc	472	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge	171:3a7713b1edbc	473	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge	171:3a7713b1edbc	474	DMA1_Channel7)
AnnaBridge	171:3a7713b1edbc	475	#endif
AnnaBridge	171:3a7713b1edbc	476
AnnaBridge	171:3a7713b1edbc	477	/**
AnnaBridge	171:3a7713b1edbc	478	* @}
AnnaBridge	171:3a7713b1edbc	479	*/
AnnaBridge	171:3a7713b1edbc	480
AnnaBridge	171:3a7713b1edbc	481	/**
AnnaBridge	171:3a7713b1edbc	482	* @}
AnnaBridge	171:3a7713b1edbc	483	*/
AnnaBridge	171:3a7713b1edbc	484
AnnaBridge	171:3a7713b1edbc	485	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	486	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	171:3a7713b1edbc	487	* @{
AnnaBridge	171:3a7713b1edbc	488	*/
AnnaBridge	171:3a7713b1edbc	489
AnnaBridge	171:3a7713b1edbc	490	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	171:3a7713b1edbc	491	* @{
AnnaBridge	171:3a7713b1edbc	492	*/
AnnaBridge	171:3a7713b1edbc	493	/**
AnnaBridge	171:3a7713b1edbc	494	* @brief Enable DMA channel.
AnnaBridge	171:3a7713b1edbc	495	* @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge	171:3a7713b1edbc	496	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	497	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	498	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	499	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	500	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	501	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	502	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	503	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	504	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	505	* @retval None
AnnaBridge	171:3a7713b1edbc	506	*/
AnnaBridge	171:3a7713b1edbc	507	__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	508	{
AnnaBridge	171:3a7713b1edbc	509	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	171:3a7713b1edbc	510	}
AnnaBridge	171:3a7713b1edbc	511
AnnaBridge	171:3a7713b1edbc	512	/**
AnnaBridge	171:3a7713b1edbc	513	* @brief Disable DMA channel.
AnnaBridge	171:3a7713b1edbc	514	* @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge	171:3a7713b1edbc	515	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	516	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	517	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	518	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	519	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	520	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	521	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	522	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	523	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	524	* @retval None
AnnaBridge	171:3a7713b1edbc	525	*/
AnnaBridge	171:3a7713b1edbc	526	__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	527	{
AnnaBridge	171:3a7713b1edbc	528	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge	171:3a7713b1edbc	529	}
AnnaBridge	171:3a7713b1edbc	530
AnnaBridge	171:3a7713b1edbc	531	/**
AnnaBridge	171:3a7713b1edbc	532	* @brief Check if DMA channel is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	533	* @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge	171:3a7713b1edbc	534	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	535	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	536	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	537	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	538	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	539	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	540	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	541	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	542	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	543	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	544	*/
AnnaBridge	171:3a7713b1edbc	545	__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	546	{
AnnaBridge	171:3a7713b1edbc	547	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	548	DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge	171:3a7713b1edbc	549	}
AnnaBridge	171:3a7713b1edbc	550
AnnaBridge	171:3a7713b1edbc	551	/**
AnnaBridge	171:3a7713b1edbc	552	* @brief Configure all parameters link to DMA transfer.
AnnaBridge	171:3a7713b1edbc	553	* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	171:3a7713b1edbc	554	* CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge	171:3a7713b1edbc	555	* CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	171:3a7713b1edbc	556	* CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	171:3a7713b1edbc	557	* CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	171:3a7713b1edbc	558	* CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	171:3a7713b1edbc	559	* CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	171:3a7713b1edbc	560	* CCR PL LL_DMA_ConfigTransfer
AnnaBridge	171:3a7713b1edbc	561	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	562	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	563	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	564	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	565	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	566	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	567	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	568	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	569	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	570	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	171:3a7713b1edbc	571	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	171:3a7713b1edbc	572	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	171:3a7713b1edbc	573	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	171:3a7713b1edbc	574	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	171:3a7713b1edbc	575	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	171:3a7713b1edbc	576	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	171:3a7713b1edbc	577	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	171:3a7713b1edbc	578	* @retval None
AnnaBridge	171:3a7713b1edbc	579	*/
AnnaBridge	171:3a7713b1edbc	580	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	171:3a7713b1edbc	581	{
AnnaBridge	171:3a7713b1edbc	582	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	583	DMA_CCR_DIR \| DMA_CCR_MEM2MEM \| DMA_CCR_CIRC \| DMA_CCR_PINC \| DMA_CCR_MINC \| DMA_CCR_PSIZE \| DMA_CCR_MSIZE \| DMA_CCR_PL,
AnnaBridge	171:3a7713b1edbc	584	Configuration);
AnnaBridge	171:3a7713b1edbc	585	}
AnnaBridge	171:3a7713b1edbc	586
AnnaBridge	171:3a7713b1edbc	587	/**
AnnaBridge	171:3a7713b1edbc	588	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	171:3a7713b1edbc	589	* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge	171:3a7713b1edbc	590	* CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge	171:3a7713b1edbc	591	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	592	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	593	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	594	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	595	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	596	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	597	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	598	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	599	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	600	* @param Direction This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	601	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	171:3a7713b1edbc	602	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	171:3a7713b1edbc	603	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	171:3a7713b1edbc	604	* @retval None
AnnaBridge	171:3a7713b1edbc	605	*/
AnnaBridge	171:3a7713b1edbc	606	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge	171:3a7713b1edbc	607	{
AnnaBridge	171:3a7713b1edbc	608	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	609	DMA_CCR_DIR \| DMA_CCR_MEM2MEM, Direction);
AnnaBridge	171:3a7713b1edbc	610	}
AnnaBridge	171:3a7713b1edbc	611
AnnaBridge	171:3a7713b1edbc	612	/**
AnnaBridge	171:3a7713b1edbc	613	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	171:3a7713b1edbc	614	* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge	171:3a7713b1edbc	615	* CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge	171:3a7713b1edbc	616	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	617	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	618	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	619	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	620	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	621	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	622	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	623	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	624	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	625	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	626	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	171:3a7713b1edbc	627	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	171:3a7713b1edbc	628	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	171:3a7713b1edbc	629	*/
AnnaBridge	171:3a7713b1edbc	630	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	631	{
AnnaBridge	171:3a7713b1edbc	632	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	633	DMA_CCR_DIR \| DMA_CCR_MEM2MEM));
AnnaBridge	171:3a7713b1edbc	634	}
AnnaBridge	171:3a7713b1edbc	635
AnnaBridge	171:3a7713b1edbc	636	/**
AnnaBridge	171:3a7713b1edbc	637	* @brief Set DMA mode circular or normal.
AnnaBridge	171:3a7713b1edbc	638	* @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge	171:3a7713b1edbc	639	* data transfer is configured on the selected Channel.
AnnaBridge	171:3a7713b1edbc	640	* @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge	171:3a7713b1edbc	641	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	642	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	643	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	644	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	645	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	646	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	647	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	648	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	649	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	650	* @param Mode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	651	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	171:3a7713b1edbc	652	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	171:3a7713b1edbc	653	* @retval None
AnnaBridge	171:3a7713b1edbc	654	*/
AnnaBridge	171:3a7713b1edbc	655	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge	171:3a7713b1edbc	656	{
AnnaBridge	171:3a7713b1edbc	657	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge	171:3a7713b1edbc	658	Mode);
AnnaBridge	171:3a7713b1edbc	659	}
AnnaBridge	171:3a7713b1edbc	660
AnnaBridge	171:3a7713b1edbc	661	/**
AnnaBridge	171:3a7713b1edbc	662	* @brief Get DMA mode circular or normal.
AnnaBridge	171:3a7713b1edbc	663	* @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge	171:3a7713b1edbc	664	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	665	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	666	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	667	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	668	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	669	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	670	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	671	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	672	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	673	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	674	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	171:3a7713b1edbc	675	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	171:3a7713b1edbc	676	*/
AnnaBridge	171:3a7713b1edbc	677	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	678	{
AnnaBridge	171:3a7713b1edbc	679	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	680	DMA_CCR_CIRC));
AnnaBridge	171:3a7713b1edbc	681	}
AnnaBridge	171:3a7713b1edbc	682
AnnaBridge	171:3a7713b1edbc	683	/**
AnnaBridge	171:3a7713b1edbc	684	* @brief Set Peripheral increment mode.
AnnaBridge	171:3a7713b1edbc	685	* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	171:3a7713b1edbc	686	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	687	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	688	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	689	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	690	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	691	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	692	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	693	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	694	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	695	* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	696	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	171:3a7713b1edbc	697	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	171:3a7713b1edbc	698	* @retval None
AnnaBridge	171:3a7713b1edbc	699	*/
AnnaBridge	171:3a7713b1edbc	700	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge	171:3a7713b1edbc	701	{
AnnaBridge	171:3a7713b1edbc	702	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge	171:3a7713b1edbc	703	PeriphOrM2MSrcIncMode);
AnnaBridge	171:3a7713b1edbc	704	}
AnnaBridge	171:3a7713b1edbc	705
AnnaBridge	171:3a7713b1edbc	706	/**
AnnaBridge	171:3a7713b1edbc	707	* @brief Get Peripheral increment mode.
AnnaBridge	171:3a7713b1edbc	708	* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	171:3a7713b1edbc	709	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	710	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	711	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	712	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	713	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	714	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	715	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	716	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	717	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	718	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	719	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	171:3a7713b1edbc	720	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	171:3a7713b1edbc	721	*/
AnnaBridge	171:3a7713b1edbc	722	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	723	{
AnnaBridge	171:3a7713b1edbc	724	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	725	DMA_CCR_PINC));
AnnaBridge	171:3a7713b1edbc	726	}
AnnaBridge	171:3a7713b1edbc	727
AnnaBridge	171:3a7713b1edbc	728	/**
AnnaBridge	171:3a7713b1edbc	729	* @brief Set Memory increment mode.
AnnaBridge	171:3a7713b1edbc	730	* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	171:3a7713b1edbc	731	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	732	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	733	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	734	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	735	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	736	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	737	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	738	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	739	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	740	* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	741	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	171:3a7713b1edbc	742	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	171:3a7713b1edbc	743	* @retval None
AnnaBridge	171:3a7713b1edbc	744	*/
AnnaBridge	171:3a7713b1edbc	745	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge	171:3a7713b1edbc	746	{
AnnaBridge	171:3a7713b1edbc	747	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge	171:3a7713b1edbc	748	MemoryOrM2MDstIncMode);
AnnaBridge	171:3a7713b1edbc	749	}
AnnaBridge	171:3a7713b1edbc	750
AnnaBridge	171:3a7713b1edbc	751	/**
AnnaBridge	171:3a7713b1edbc	752	* @brief Get Memory increment mode.
AnnaBridge	171:3a7713b1edbc	753	* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	171:3a7713b1edbc	754	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	755	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	756	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	757	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	758	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	759	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	760	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	761	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	762	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	763	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	764	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	171:3a7713b1edbc	765	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	171:3a7713b1edbc	766	*/
AnnaBridge	171:3a7713b1edbc	767	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	768	{
AnnaBridge	171:3a7713b1edbc	769	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	770	DMA_CCR_MINC));
AnnaBridge	171:3a7713b1edbc	771	}
AnnaBridge	171:3a7713b1edbc	772
AnnaBridge	171:3a7713b1edbc	773	/**
AnnaBridge	171:3a7713b1edbc	774	* @brief Set Peripheral size.
AnnaBridge	171:3a7713b1edbc	775	* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	171:3a7713b1edbc	776	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	777	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	778	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	779	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	780	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	781	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	782	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	783	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	784	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	785	* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	786	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	171:3a7713b1edbc	787	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	171:3a7713b1edbc	788	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	171:3a7713b1edbc	789	* @retval None
AnnaBridge	171:3a7713b1edbc	790	*/
AnnaBridge	171:3a7713b1edbc	791	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge	171:3a7713b1edbc	792	{
AnnaBridge	171:3a7713b1edbc	793	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge	171:3a7713b1edbc	794	PeriphOrM2MSrcDataSize);
AnnaBridge	171:3a7713b1edbc	795	}
AnnaBridge	171:3a7713b1edbc	796
AnnaBridge	171:3a7713b1edbc	797	/**
AnnaBridge	171:3a7713b1edbc	798	* @brief Get Peripheral size.
AnnaBridge	171:3a7713b1edbc	799	* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	171:3a7713b1edbc	800	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	801	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	802	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	803	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	804	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	805	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	806	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	807	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	808	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	809	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	810	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	171:3a7713b1edbc	811	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	171:3a7713b1edbc	812	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	171:3a7713b1edbc	813	*/
AnnaBridge	171:3a7713b1edbc	814	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	815	{
AnnaBridge	171:3a7713b1edbc	816	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	817	DMA_CCR_PSIZE));
AnnaBridge	171:3a7713b1edbc	818	}
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820	/**
AnnaBridge	171:3a7713b1edbc	821	* @brief Set Memory size.
AnnaBridge	171:3a7713b1edbc	822	* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge	171:3a7713b1edbc	823	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	824	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	825	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	826	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	827	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	828	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	829	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	830	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	831	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	832	* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	833	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	171:3a7713b1edbc	834	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	171:3a7713b1edbc	835	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	171:3a7713b1edbc	836	* @retval None
AnnaBridge	171:3a7713b1edbc	837	*/
AnnaBridge	171:3a7713b1edbc	838	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge	171:3a7713b1edbc	839	{
AnnaBridge	171:3a7713b1edbc	840	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge	171:3a7713b1edbc	841	MemoryOrM2MDstDataSize);
AnnaBridge	171:3a7713b1edbc	842	}
AnnaBridge	171:3a7713b1edbc	843
AnnaBridge	171:3a7713b1edbc	844	/**
AnnaBridge	171:3a7713b1edbc	845	* @brief Get Memory size.
AnnaBridge	171:3a7713b1edbc	846	* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge	171:3a7713b1edbc	847	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	848	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	849	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	850	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	851	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	852	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	853	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	854	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	855	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	856	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	857	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	171:3a7713b1edbc	858	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	171:3a7713b1edbc	859	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	171:3a7713b1edbc	860	*/
AnnaBridge	171:3a7713b1edbc	861	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	862	{
AnnaBridge	171:3a7713b1edbc	863	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	864	DMA_CCR_MSIZE));
AnnaBridge	171:3a7713b1edbc	865	}
AnnaBridge	171:3a7713b1edbc	866
AnnaBridge	171:3a7713b1edbc	867	/**
AnnaBridge	171:3a7713b1edbc	868	* @brief Set Channel priority level.
AnnaBridge	171:3a7713b1edbc	869	* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge	171:3a7713b1edbc	870	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	871	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	872	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	873	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	874	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	875	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	876	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	877	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	878	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	879	* @param Priority This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	880	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	171:3a7713b1edbc	881	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	171:3a7713b1edbc	882	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	171:3a7713b1edbc	883	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	171:3a7713b1edbc	884	* @retval None
AnnaBridge	171:3a7713b1edbc	885	*/
AnnaBridge	171:3a7713b1edbc	886	__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge	171:3a7713b1edbc	887	{
AnnaBridge	171:3a7713b1edbc	888	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge	171:3a7713b1edbc	889	Priority);
AnnaBridge	171:3a7713b1edbc	890	}
AnnaBridge	171:3a7713b1edbc	891
AnnaBridge	171:3a7713b1edbc	892	/**
AnnaBridge	171:3a7713b1edbc	893	* @brief Get Channel priority level.
AnnaBridge	171:3a7713b1edbc	894	* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge	171:3a7713b1edbc	895	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	896	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	897	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	898	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	899	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	900	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	901	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	902	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	903	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	904	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	905	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	171:3a7713b1edbc	906	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	171:3a7713b1edbc	907	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	171:3a7713b1edbc	908	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	171:3a7713b1edbc	909	*/
AnnaBridge	171:3a7713b1edbc	910	__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	911	{
AnnaBridge	171:3a7713b1edbc	912	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	913	DMA_CCR_PL));
AnnaBridge	171:3a7713b1edbc	914	}
AnnaBridge	171:3a7713b1edbc	915
AnnaBridge	171:3a7713b1edbc	916	/**
AnnaBridge	171:3a7713b1edbc	917	* @brief Set Number of data to transfer.
AnnaBridge	171:3a7713b1edbc	918	* @note This action has no effect if
AnnaBridge	171:3a7713b1edbc	919	* channel is enabled.
AnnaBridge	171:3a7713b1edbc	920	* @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge	171:3a7713b1edbc	921	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	922	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	923	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	924	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	925	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	926	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	927	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	928	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	929	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	930	* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	171:3a7713b1edbc	931	* @retval None
AnnaBridge	171:3a7713b1edbc	932	*/
AnnaBridge	171:3a7713b1edbc	933	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge	171:3a7713b1edbc	934	{
AnnaBridge	171:3a7713b1edbc	935	MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	171:3a7713b1edbc	936	DMA_CNDTR_NDT, NbData);
AnnaBridge	171:3a7713b1edbc	937	}
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	/**
AnnaBridge	171:3a7713b1edbc	940	* @brief Get Number of data to transfer.
AnnaBridge	171:3a7713b1edbc	941	* @note Once the channel is enabled, the return value indicate the
AnnaBridge	171:3a7713b1edbc	942	* remaining bytes to be transmitted.
AnnaBridge	171:3a7713b1edbc	943	* @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge	171:3a7713b1edbc	944	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	945	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	946	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	947	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	948	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	949	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	950	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	951	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	952	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	953	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	954	*/
AnnaBridge	171:3a7713b1edbc	955	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	956	{
AnnaBridge	171:3a7713b1edbc	957	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge	171:3a7713b1edbc	958	DMA_CNDTR_NDT));
AnnaBridge	171:3a7713b1edbc	959	}
AnnaBridge	171:3a7713b1edbc	960
AnnaBridge	171:3a7713b1edbc	961	/**
AnnaBridge	171:3a7713b1edbc	962	* @brief Configure the Source and Destination addresses.
AnnaBridge	171:3a7713b1edbc	963	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	171:3a7713b1edbc	964	* @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge	171:3a7713b1edbc	965	* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge	171:3a7713b1edbc	966	* CMAR MA LL_DMA_ConfigAddresses
AnnaBridge	171:3a7713b1edbc	967	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	968	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	969	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	970	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	971	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	972	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	973	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	974	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	975	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	976	* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	977	* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	978	* @param Direction This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	979	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	171:3a7713b1edbc	980	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	171:3a7713b1edbc	981	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	171:3a7713b1edbc	982	* @retval None
AnnaBridge	171:3a7713b1edbc	983	*/
AnnaBridge	171:3a7713b1edbc	984	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge	171:3a7713b1edbc	985	uint32_t DstAddress, uint32_t Direction)
AnnaBridge	171:3a7713b1edbc	986	{
AnnaBridge	171:3a7713b1edbc	987	/* Direction Memory to Periph */
AnnaBridge	171:3a7713b1edbc	988	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	171:3a7713b1edbc	989	{
AnnaBridge	171:3a7713b1edbc	990	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge	171:3a7713b1edbc	991	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge	171:3a7713b1edbc	992	}
AnnaBridge	171:3a7713b1edbc	993	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	171:3a7713b1edbc	994	else
AnnaBridge	171:3a7713b1edbc	995	{
AnnaBridge	171:3a7713b1edbc	996	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge	171:3a7713b1edbc	997	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge	171:3a7713b1edbc	998	}
AnnaBridge	171:3a7713b1edbc	999	}
AnnaBridge	171:3a7713b1edbc	1000
AnnaBridge	171:3a7713b1edbc	1001	/**
AnnaBridge	171:3a7713b1edbc	1002	* @brief Set the Memory address.
AnnaBridge	171:3a7713b1edbc	1003	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	171:3a7713b1edbc	1004	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	171:3a7713b1edbc	1005	* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge	171:3a7713b1edbc	1006	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1007	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1008	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1009	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1010	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1011	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1012	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1013	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1014	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1015	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1016	* @retval None
AnnaBridge	171:3a7713b1edbc	1017	*/
AnnaBridge	171:3a7713b1edbc	1018	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	171:3a7713b1edbc	1019	{
AnnaBridge	171:3a7713b1edbc	1020	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	171:3a7713b1edbc	1021	}
AnnaBridge	171:3a7713b1edbc	1022
AnnaBridge	171:3a7713b1edbc	1023	/**
AnnaBridge	171:3a7713b1edbc	1024	* @brief Set the Peripheral address.
AnnaBridge	171:3a7713b1edbc	1025	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	171:3a7713b1edbc	1026	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	171:3a7713b1edbc	1027	* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge	171:3a7713b1edbc	1028	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1029	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1030	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1031	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1032	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1033	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1034	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1035	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1036	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1037	* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1038	* @retval None
AnnaBridge	171:3a7713b1edbc	1039	*/
AnnaBridge	171:3a7713b1edbc	1040	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge	171:3a7713b1edbc	1041	{
AnnaBridge	171:3a7713b1edbc	1042	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge	171:3a7713b1edbc	1043	}
AnnaBridge	171:3a7713b1edbc	1044
AnnaBridge	171:3a7713b1edbc	1045	/**
AnnaBridge	171:3a7713b1edbc	1046	* @brief Get Memory address.
AnnaBridge	171:3a7713b1edbc	1047	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	171:3a7713b1edbc	1048	* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge	171:3a7713b1edbc	1049	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1050	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1051	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1052	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1053	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1054	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1055	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1056	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1057	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1058	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1059	*/
AnnaBridge	171:3a7713b1edbc	1060	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1061	{
AnnaBridge	171:3a7713b1edbc	1062	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	171:3a7713b1edbc	1063	}
AnnaBridge	171:3a7713b1edbc	1064
AnnaBridge	171:3a7713b1edbc	1065	/**
AnnaBridge	171:3a7713b1edbc	1066	* @brief Get Peripheral address.
AnnaBridge	171:3a7713b1edbc	1067	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	171:3a7713b1edbc	1068	* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge	171:3a7713b1edbc	1069	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1070	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1071	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1072	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1073	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1074	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1075	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1076	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1077	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1078	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1079	*/
AnnaBridge	171:3a7713b1edbc	1080	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1081	{
AnnaBridge	171:3a7713b1edbc	1082	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	171:3a7713b1edbc	1083	}
AnnaBridge	171:3a7713b1edbc	1084
AnnaBridge	171:3a7713b1edbc	1085	/**
AnnaBridge	171:3a7713b1edbc	1086	* @brief Set the Memory to Memory Source address.
AnnaBridge	171:3a7713b1edbc	1087	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	171:3a7713b1edbc	1088	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	171:3a7713b1edbc	1089	* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	171:3a7713b1edbc	1090	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1091	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1092	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1093	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1094	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1095	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1096	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1097	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1098	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1099	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1100	* @retval None
AnnaBridge	171:3a7713b1edbc	1101	*/
AnnaBridge	171:3a7713b1edbc	1102	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	171:3a7713b1edbc	1103	{
AnnaBridge	171:3a7713b1edbc	1104	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge	171:3a7713b1edbc	1105	}
AnnaBridge	171:3a7713b1edbc	1106
AnnaBridge	171:3a7713b1edbc	1107	/**
AnnaBridge	171:3a7713b1edbc	1108	* @brief Set the Memory to Memory Destination address.
AnnaBridge	171:3a7713b1edbc	1109	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	171:3a7713b1edbc	1110	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	171:3a7713b1edbc	1111	* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge	171:3a7713b1edbc	1112	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1113	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1114	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1115	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1116	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1117	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1118	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1119	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1120	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1121	* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1122	* @retval None
AnnaBridge	171:3a7713b1edbc	1123	*/
AnnaBridge	171:3a7713b1edbc	1124	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge	171:3a7713b1edbc	1125	{
AnnaBridge	171:3a7713b1edbc	1126	WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge	171:3a7713b1edbc	1127	}
AnnaBridge	171:3a7713b1edbc	1128
AnnaBridge	171:3a7713b1edbc	1129	/**
AnnaBridge	171:3a7713b1edbc	1130	* @brief Get the Memory to Memory Source address.
AnnaBridge	171:3a7713b1edbc	1131	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	171:3a7713b1edbc	1132	* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	171:3a7713b1edbc	1133	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1134	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1135	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1136	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1137	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1138	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1139	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1140	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1141	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1142	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1143	*/
AnnaBridge	171:3a7713b1edbc	1144	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1145	{
AnnaBridge	171:3a7713b1edbc	1146	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge	171:3a7713b1edbc	1147	}
AnnaBridge	171:3a7713b1edbc	1148
AnnaBridge	171:3a7713b1edbc	1149	/**
AnnaBridge	171:3a7713b1edbc	1150	* @brief Get the Memory to Memory Destination address.
AnnaBridge	171:3a7713b1edbc	1151	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	171:3a7713b1edbc	1152	* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge	171:3a7713b1edbc	1153	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1154	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1155	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1156	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1157	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1158	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1159	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1160	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1161	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1162	* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge	171:3a7713b1edbc	1163	*/
AnnaBridge	171:3a7713b1edbc	1164	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1165	{
AnnaBridge	171:3a7713b1edbc	1166	return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge	171:3a7713b1edbc	1167	}
AnnaBridge	171:3a7713b1edbc	1168
AnnaBridge	171:3a7713b1edbc	1169
AnnaBridge	171:3a7713b1edbc	1170	/**
AnnaBridge	171:3a7713b1edbc	1171	* @}
AnnaBridge	171:3a7713b1edbc	1172	*/
AnnaBridge	171:3a7713b1edbc	1173
AnnaBridge	171:3a7713b1edbc	1174	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	171:3a7713b1edbc	1175	* @{
AnnaBridge	171:3a7713b1edbc	1176	*/
AnnaBridge	171:3a7713b1edbc	1177
AnnaBridge	171:3a7713b1edbc	1178	/**
AnnaBridge	171:3a7713b1edbc	1179	* @brief Get Channel 1 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1180	* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge	171:3a7713b1edbc	1181	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1182	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1183	*/
AnnaBridge	171:3a7713b1edbc	1184	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1185	{
AnnaBridge	171:3a7713b1edbc	1186	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge	171:3a7713b1edbc	1187	}
AnnaBridge	171:3a7713b1edbc	1188
AnnaBridge	171:3a7713b1edbc	1189	/**
AnnaBridge	171:3a7713b1edbc	1190	* @brief Get Channel 2 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1191	* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge	171:3a7713b1edbc	1192	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1193	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1194	*/
AnnaBridge	171:3a7713b1edbc	1195	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1196	{
AnnaBridge	171:3a7713b1edbc	1197	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge	171:3a7713b1edbc	1198	}
AnnaBridge	171:3a7713b1edbc	1199
AnnaBridge	171:3a7713b1edbc	1200	/**
AnnaBridge	171:3a7713b1edbc	1201	* @brief Get Channel 3 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1202	* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge	171:3a7713b1edbc	1203	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1204	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1205	*/
AnnaBridge	171:3a7713b1edbc	1206	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1207	{
AnnaBridge	171:3a7713b1edbc	1208	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge	171:3a7713b1edbc	1209	}
AnnaBridge	171:3a7713b1edbc	1210
AnnaBridge	171:3a7713b1edbc	1211	/**
AnnaBridge	171:3a7713b1edbc	1212	* @brief Get Channel 4 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1213	* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge	171:3a7713b1edbc	1214	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1215	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1216	*/
AnnaBridge	171:3a7713b1edbc	1217	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1218	{
AnnaBridge	171:3a7713b1edbc	1219	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge	171:3a7713b1edbc	1220	}
AnnaBridge	171:3a7713b1edbc	1221
AnnaBridge	171:3a7713b1edbc	1222	/**
AnnaBridge	171:3a7713b1edbc	1223	* @brief Get Channel 5 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1224	* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge	171:3a7713b1edbc	1225	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1226	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1227	*/
AnnaBridge	171:3a7713b1edbc	1228	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1229	{
AnnaBridge	171:3a7713b1edbc	1230	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge	171:3a7713b1edbc	1231	}
AnnaBridge	171:3a7713b1edbc	1232
AnnaBridge	171:3a7713b1edbc	1233	/**
AnnaBridge	171:3a7713b1edbc	1234	* @brief Get Channel 6 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1235	* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge	171:3a7713b1edbc	1236	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1237	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1238	*/
AnnaBridge	171:3a7713b1edbc	1239	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1240	{
AnnaBridge	171:3a7713b1edbc	1241	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge	171:3a7713b1edbc	1242	}
AnnaBridge	171:3a7713b1edbc	1243
AnnaBridge	171:3a7713b1edbc	1244	/**
AnnaBridge	171:3a7713b1edbc	1245	* @brief Get Channel 7 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1246	* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge	171:3a7713b1edbc	1247	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1248	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1249	*/
AnnaBridge	171:3a7713b1edbc	1250	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1251	{
AnnaBridge	171:3a7713b1edbc	1252	return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge	171:3a7713b1edbc	1253	}
AnnaBridge	171:3a7713b1edbc	1254
AnnaBridge	171:3a7713b1edbc	1255	/**
AnnaBridge	171:3a7713b1edbc	1256	* @brief Get Channel 1 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1257	* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	171:3a7713b1edbc	1258	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1259	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1260	*/
AnnaBridge	171:3a7713b1edbc	1261	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1262	{
AnnaBridge	171:3a7713b1edbc	1263	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge	171:3a7713b1edbc	1264	}
AnnaBridge	171:3a7713b1edbc	1265
AnnaBridge	171:3a7713b1edbc	1266	/**
AnnaBridge	171:3a7713b1edbc	1267	* @brief Get Channel 2 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1268	* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	171:3a7713b1edbc	1269	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1270	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1271	*/
AnnaBridge	171:3a7713b1edbc	1272	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1273	{
AnnaBridge	171:3a7713b1edbc	1274	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge	171:3a7713b1edbc	1275	}
AnnaBridge	171:3a7713b1edbc	1276
AnnaBridge	171:3a7713b1edbc	1277	/**
AnnaBridge	171:3a7713b1edbc	1278	* @brief Get Channel 3 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1279	* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	171:3a7713b1edbc	1280	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1281	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1282	*/
AnnaBridge	171:3a7713b1edbc	1283	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1284	{
AnnaBridge	171:3a7713b1edbc	1285	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge	171:3a7713b1edbc	1286	}
AnnaBridge	171:3a7713b1edbc	1287
AnnaBridge	171:3a7713b1edbc	1288	/**
AnnaBridge	171:3a7713b1edbc	1289	* @brief Get Channel 4 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1290	* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	171:3a7713b1edbc	1291	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1292	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1293	*/
AnnaBridge	171:3a7713b1edbc	1294	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1295	{
AnnaBridge	171:3a7713b1edbc	1296	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge	171:3a7713b1edbc	1297	}
AnnaBridge	171:3a7713b1edbc	1298
AnnaBridge	171:3a7713b1edbc	1299	/**
AnnaBridge	171:3a7713b1edbc	1300	* @brief Get Channel 5 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1301	* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge	171:3a7713b1edbc	1302	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1303	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1304	*/
AnnaBridge	171:3a7713b1edbc	1305	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1306	{
AnnaBridge	171:3a7713b1edbc	1307	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge	171:3a7713b1edbc	1308	}
AnnaBridge	171:3a7713b1edbc	1309
AnnaBridge	171:3a7713b1edbc	1310	/**
AnnaBridge	171:3a7713b1edbc	1311	* @brief Get Channel 6 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1312	* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	171:3a7713b1edbc	1313	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1314	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1315	*/
AnnaBridge	171:3a7713b1edbc	1316	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1317	{
AnnaBridge	171:3a7713b1edbc	1318	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge	171:3a7713b1edbc	1319	}
AnnaBridge	171:3a7713b1edbc	1320
AnnaBridge	171:3a7713b1edbc	1321	/**
AnnaBridge	171:3a7713b1edbc	1322	* @brief Get Channel 7 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1323	* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	171:3a7713b1edbc	1324	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1325	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1326	*/
AnnaBridge	171:3a7713b1edbc	1327	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1328	{
AnnaBridge	171:3a7713b1edbc	1329	return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge	171:3a7713b1edbc	1330	}
AnnaBridge	171:3a7713b1edbc	1331
AnnaBridge	171:3a7713b1edbc	1332	/**
AnnaBridge	171:3a7713b1edbc	1333	* @brief Get Channel 1 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1334	* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	171:3a7713b1edbc	1335	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1336	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1337	*/
AnnaBridge	171:3a7713b1edbc	1338	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1339	{
AnnaBridge	171:3a7713b1edbc	1340	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge	171:3a7713b1edbc	1341	}
AnnaBridge	171:3a7713b1edbc	1342
AnnaBridge	171:3a7713b1edbc	1343	/**
AnnaBridge	171:3a7713b1edbc	1344	* @brief Get Channel 2 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1345	* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	171:3a7713b1edbc	1346	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1347	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1348	*/
AnnaBridge	171:3a7713b1edbc	1349	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1350	{
AnnaBridge	171:3a7713b1edbc	1351	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge	171:3a7713b1edbc	1352	}
AnnaBridge	171:3a7713b1edbc	1353
AnnaBridge	171:3a7713b1edbc	1354	/**
AnnaBridge	171:3a7713b1edbc	1355	* @brief Get Channel 3 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1356	* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	171:3a7713b1edbc	1357	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1358	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1359	*/
AnnaBridge	171:3a7713b1edbc	1360	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1361	{
AnnaBridge	171:3a7713b1edbc	1362	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge	171:3a7713b1edbc	1363	}
AnnaBridge	171:3a7713b1edbc	1364
AnnaBridge	171:3a7713b1edbc	1365	/**
AnnaBridge	171:3a7713b1edbc	1366	* @brief Get Channel 4 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1367	* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	171:3a7713b1edbc	1368	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1369	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1370	*/
AnnaBridge	171:3a7713b1edbc	1371	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1372	{
AnnaBridge	171:3a7713b1edbc	1373	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge	171:3a7713b1edbc	1374	}
AnnaBridge	171:3a7713b1edbc	1375
AnnaBridge	171:3a7713b1edbc	1376	/**
AnnaBridge	171:3a7713b1edbc	1377	* @brief Get Channel 5 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1378	* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge	171:3a7713b1edbc	1379	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1380	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1381	*/
AnnaBridge	171:3a7713b1edbc	1382	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1383	{
AnnaBridge	171:3a7713b1edbc	1384	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge	171:3a7713b1edbc	1385	}
AnnaBridge	171:3a7713b1edbc	1386
AnnaBridge	171:3a7713b1edbc	1387	/**
AnnaBridge	171:3a7713b1edbc	1388	* @brief Get Channel 6 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1389	* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	171:3a7713b1edbc	1390	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1391	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1392	*/
AnnaBridge	171:3a7713b1edbc	1393	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1394	{
AnnaBridge	171:3a7713b1edbc	1395	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge	171:3a7713b1edbc	1396	}
AnnaBridge	171:3a7713b1edbc	1397
AnnaBridge	171:3a7713b1edbc	1398	/**
AnnaBridge	171:3a7713b1edbc	1399	* @brief Get Channel 7 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1400	* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	171:3a7713b1edbc	1401	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1402	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1403	*/
AnnaBridge	171:3a7713b1edbc	1404	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1405	{
AnnaBridge	171:3a7713b1edbc	1406	return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge	171:3a7713b1edbc	1407	}
AnnaBridge	171:3a7713b1edbc	1408
AnnaBridge	171:3a7713b1edbc	1409	/**
AnnaBridge	171:3a7713b1edbc	1410	* @brief Get Channel 1 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1411	* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	171:3a7713b1edbc	1412	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1413	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1414	*/
AnnaBridge	171:3a7713b1edbc	1415	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1416	{
AnnaBridge	171:3a7713b1edbc	1417	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge	171:3a7713b1edbc	1418	}
AnnaBridge	171:3a7713b1edbc	1419
AnnaBridge	171:3a7713b1edbc	1420	/**
AnnaBridge	171:3a7713b1edbc	1421	* @brief Get Channel 2 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1422	* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	171:3a7713b1edbc	1423	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1424	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1425	*/
AnnaBridge	171:3a7713b1edbc	1426	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1427	{
AnnaBridge	171:3a7713b1edbc	1428	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge	171:3a7713b1edbc	1429	}
AnnaBridge	171:3a7713b1edbc	1430
AnnaBridge	171:3a7713b1edbc	1431	/**
AnnaBridge	171:3a7713b1edbc	1432	* @brief Get Channel 3 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1433	* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	171:3a7713b1edbc	1434	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1435	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1436	*/
AnnaBridge	171:3a7713b1edbc	1437	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1438	{
AnnaBridge	171:3a7713b1edbc	1439	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge	171:3a7713b1edbc	1440	}
AnnaBridge	171:3a7713b1edbc	1441
AnnaBridge	171:3a7713b1edbc	1442	/**
AnnaBridge	171:3a7713b1edbc	1443	* @brief Get Channel 4 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1444	* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	171:3a7713b1edbc	1445	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1446	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1447	*/
AnnaBridge	171:3a7713b1edbc	1448	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1449	{
AnnaBridge	171:3a7713b1edbc	1450	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge	171:3a7713b1edbc	1451	}
AnnaBridge	171:3a7713b1edbc	1452
AnnaBridge	171:3a7713b1edbc	1453	/**
AnnaBridge	171:3a7713b1edbc	1454	* @brief Get Channel 5 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1455	* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge	171:3a7713b1edbc	1456	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1457	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1458	*/
AnnaBridge	171:3a7713b1edbc	1459	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1460	{
AnnaBridge	171:3a7713b1edbc	1461	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge	171:3a7713b1edbc	1462	}
AnnaBridge	171:3a7713b1edbc	1463
AnnaBridge	171:3a7713b1edbc	1464	/**
AnnaBridge	171:3a7713b1edbc	1465	* @brief Get Channel 6 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1466	* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	171:3a7713b1edbc	1467	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1468	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1469	*/
AnnaBridge	171:3a7713b1edbc	1470	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1471	{
AnnaBridge	171:3a7713b1edbc	1472	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge	171:3a7713b1edbc	1473	}
AnnaBridge	171:3a7713b1edbc	1474
AnnaBridge	171:3a7713b1edbc	1475	/**
AnnaBridge	171:3a7713b1edbc	1476	* @brief Get Channel 7 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1477	* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	171:3a7713b1edbc	1478	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1479	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1480	*/
AnnaBridge	171:3a7713b1edbc	1481	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1482	{
AnnaBridge	171:3a7713b1edbc	1483	return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge	171:3a7713b1edbc	1484	}
AnnaBridge	171:3a7713b1edbc	1485
AnnaBridge	171:3a7713b1edbc	1486	/**
AnnaBridge	171:3a7713b1edbc	1487	* @brief Clear Channel 1 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1488	* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge	171:3a7713b1edbc	1489	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1490	* @retval None
AnnaBridge	171:3a7713b1edbc	1491	*/
AnnaBridge	171:3a7713b1edbc	1492	__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1493	{
AnnaBridge	171:3a7713b1edbc	1494	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge	171:3a7713b1edbc	1495	}
AnnaBridge	171:3a7713b1edbc	1496
AnnaBridge	171:3a7713b1edbc	1497	/**
AnnaBridge	171:3a7713b1edbc	1498	* @brief Clear Channel 2 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1499	* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge	171:3a7713b1edbc	1500	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1501	* @retval None
AnnaBridge	171:3a7713b1edbc	1502	*/
AnnaBridge	171:3a7713b1edbc	1503	__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1504	{
AnnaBridge	171:3a7713b1edbc	1505	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge	171:3a7713b1edbc	1506	}
AnnaBridge	171:3a7713b1edbc	1507
AnnaBridge	171:3a7713b1edbc	1508	/**
AnnaBridge	171:3a7713b1edbc	1509	* @brief Clear Channel 3 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1510	* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge	171:3a7713b1edbc	1511	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1512	* @retval None
AnnaBridge	171:3a7713b1edbc	1513	*/
AnnaBridge	171:3a7713b1edbc	1514	__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1515	{
AnnaBridge	171:3a7713b1edbc	1516	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge	171:3a7713b1edbc	1517	}
AnnaBridge	171:3a7713b1edbc	1518
AnnaBridge	171:3a7713b1edbc	1519	/**
AnnaBridge	171:3a7713b1edbc	1520	* @brief Clear Channel 4 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1521	* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge	171:3a7713b1edbc	1522	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1523	* @retval None
AnnaBridge	171:3a7713b1edbc	1524	*/
AnnaBridge	171:3a7713b1edbc	1525	__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1526	{
AnnaBridge	171:3a7713b1edbc	1527	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge	171:3a7713b1edbc	1528	}
AnnaBridge	171:3a7713b1edbc	1529
AnnaBridge	171:3a7713b1edbc	1530	/**
AnnaBridge	171:3a7713b1edbc	1531	* @brief Clear Channel 5 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1532	* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge	171:3a7713b1edbc	1533	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1534	* @retval None
AnnaBridge	171:3a7713b1edbc	1535	*/
AnnaBridge	171:3a7713b1edbc	1536	__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1537	{
AnnaBridge	171:3a7713b1edbc	1538	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge	171:3a7713b1edbc	1539	}
AnnaBridge	171:3a7713b1edbc	1540
AnnaBridge	171:3a7713b1edbc	1541	/**
AnnaBridge	171:3a7713b1edbc	1542	* @brief Clear Channel 6 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1543	* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge	171:3a7713b1edbc	1544	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1545	* @retval None
AnnaBridge	171:3a7713b1edbc	1546	*/
AnnaBridge	171:3a7713b1edbc	1547	__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1548	{
AnnaBridge	171:3a7713b1edbc	1549	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge	171:3a7713b1edbc	1550	}
AnnaBridge	171:3a7713b1edbc	1551
AnnaBridge	171:3a7713b1edbc	1552	/**
AnnaBridge	171:3a7713b1edbc	1553	* @brief Clear Channel 7 global interrupt flag.
AnnaBridge	171:3a7713b1edbc	1554	* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge	171:3a7713b1edbc	1555	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1556	* @retval None
AnnaBridge	171:3a7713b1edbc	1557	*/
AnnaBridge	171:3a7713b1edbc	1558	__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1559	{
AnnaBridge	171:3a7713b1edbc	1560	SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge	171:3a7713b1edbc	1561	}
AnnaBridge	171:3a7713b1edbc	1562
AnnaBridge	171:3a7713b1edbc	1563	/**
AnnaBridge	171:3a7713b1edbc	1564	* @brief Clear Channel 1 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1565	* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	171:3a7713b1edbc	1566	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1567	* @retval None
AnnaBridge	171:3a7713b1edbc	1568	*/
AnnaBridge	171:3a7713b1edbc	1569	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1570	{
AnnaBridge	171:3a7713b1edbc	1571	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge	171:3a7713b1edbc	1572	}
AnnaBridge	171:3a7713b1edbc	1573
AnnaBridge	171:3a7713b1edbc	1574	/**
AnnaBridge	171:3a7713b1edbc	1575	* @brief Clear Channel 2 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1576	* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	171:3a7713b1edbc	1577	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1578	* @retval None
AnnaBridge	171:3a7713b1edbc	1579	*/
AnnaBridge	171:3a7713b1edbc	1580	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1581	{
AnnaBridge	171:3a7713b1edbc	1582	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge	171:3a7713b1edbc	1583	}
AnnaBridge	171:3a7713b1edbc	1584
AnnaBridge	171:3a7713b1edbc	1585	/**
AnnaBridge	171:3a7713b1edbc	1586	* @brief Clear Channel 3 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1587	* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	171:3a7713b1edbc	1588	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1589	* @retval None
AnnaBridge	171:3a7713b1edbc	1590	*/
AnnaBridge	171:3a7713b1edbc	1591	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1592	{
AnnaBridge	171:3a7713b1edbc	1593	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge	171:3a7713b1edbc	1594	}
AnnaBridge	171:3a7713b1edbc	1595
AnnaBridge	171:3a7713b1edbc	1596	/**
AnnaBridge	171:3a7713b1edbc	1597	* @brief Clear Channel 4 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1598	* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	171:3a7713b1edbc	1599	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1600	* @retval None
AnnaBridge	171:3a7713b1edbc	1601	*/
AnnaBridge	171:3a7713b1edbc	1602	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1603	{
AnnaBridge	171:3a7713b1edbc	1604	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge	171:3a7713b1edbc	1605	}
AnnaBridge	171:3a7713b1edbc	1606
AnnaBridge	171:3a7713b1edbc	1607	/**
AnnaBridge	171:3a7713b1edbc	1608	* @brief Clear Channel 5 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1609	* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	171:3a7713b1edbc	1610	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1611	* @retval None
AnnaBridge	171:3a7713b1edbc	1612	*/
AnnaBridge	171:3a7713b1edbc	1613	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1614	{
AnnaBridge	171:3a7713b1edbc	1615	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge	171:3a7713b1edbc	1616	}
AnnaBridge	171:3a7713b1edbc	1617
AnnaBridge	171:3a7713b1edbc	1618	/**
AnnaBridge	171:3a7713b1edbc	1619	* @brief Clear Channel 6 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1620	* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	171:3a7713b1edbc	1621	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1622	* @retval None
AnnaBridge	171:3a7713b1edbc	1623	*/
AnnaBridge	171:3a7713b1edbc	1624	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1625	{
AnnaBridge	171:3a7713b1edbc	1626	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge	171:3a7713b1edbc	1627	}
AnnaBridge	171:3a7713b1edbc	1628
AnnaBridge	171:3a7713b1edbc	1629	/**
AnnaBridge	171:3a7713b1edbc	1630	* @brief Clear Channel 7 transfer complete flag.
AnnaBridge	171:3a7713b1edbc	1631	* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	171:3a7713b1edbc	1632	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1633	* @retval None
AnnaBridge	171:3a7713b1edbc	1634	*/
AnnaBridge	171:3a7713b1edbc	1635	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1636	{
AnnaBridge	171:3a7713b1edbc	1637	SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge	171:3a7713b1edbc	1638	}
AnnaBridge	171:3a7713b1edbc	1639
AnnaBridge	171:3a7713b1edbc	1640	/**
AnnaBridge	171:3a7713b1edbc	1641	* @brief Clear Channel 1 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1642	* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	171:3a7713b1edbc	1643	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1644	* @retval None
AnnaBridge	171:3a7713b1edbc	1645	*/
AnnaBridge	171:3a7713b1edbc	1646	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1647	{
AnnaBridge	171:3a7713b1edbc	1648	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge	171:3a7713b1edbc	1649	}
AnnaBridge	171:3a7713b1edbc	1650
AnnaBridge	171:3a7713b1edbc	1651	/**
AnnaBridge	171:3a7713b1edbc	1652	* @brief Clear Channel 2 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1653	* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	171:3a7713b1edbc	1654	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1655	* @retval None
AnnaBridge	171:3a7713b1edbc	1656	*/
AnnaBridge	171:3a7713b1edbc	1657	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1658	{
AnnaBridge	171:3a7713b1edbc	1659	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge	171:3a7713b1edbc	1660	}
AnnaBridge	171:3a7713b1edbc	1661
AnnaBridge	171:3a7713b1edbc	1662	/**
AnnaBridge	171:3a7713b1edbc	1663	* @brief Clear Channel 3 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1664	* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	171:3a7713b1edbc	1665	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1666	* @retval None
AnnaBridge	171:3a7713b1edbc	1667	*/
AnnaBridge	171:3a7713b1edbc	1668	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1669	{
AnnaBridge	171:3a7713b1edbc	1670	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge	171:3a7713b1edbc	1671	}
AnnaBridge	171:3a7713b1edbc	1672
AnnaBridge	171:3a7713b1edbc	1673	/**
AnnaBridge	171:3a7713b1edbc	1674	* @brief Clear Channel 4 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1675	* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	171:3a7713b1edbc	1676	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1677	* @retval None
AnnaBridge	171:3a7713b1edbc	1678	*/
AnnaBridge	171:3a7713b1edbc	1679	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1680	{
AnnaBridge	171:3a7713b1edbc	1681	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge	171:3a7713b1edbc	1682	}
AnnaBridge	171:3a7713b1edbc	1683
AnnaBridge	171:3a7713b1edbc	1684	/**
AnnaBridge	171:3a7713b1edbc	1685	* @brief Clear Channel 5 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1686	* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	171:3a7713b1edbc	1687	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1688	* @retval None
AnnaBridge	171:3a7713b1edbc	1689	*/
AnnaBridge	171:3a7713b1edbc	1690	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1691	{
AnnaBridge	171:3a7713b1edbc	1692	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge	171:3a7713b1edbc	1693	}
AnnaBridge	171:3a7713b1edbc	1694
AnnaBridge	171:3a7713b1edbc	1695	/**
AnnaBridge	171:3a7713b1edbc	1696	* @brief Clear Channel 6 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1697	* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	171:3a7713b1edbc	1698	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1699	* @retval None
AnnaBridge	171:3a7713b1edbc	1700	*/
AnnaBridge	171:3a7713b1edbc	1701	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1702	{
AnnaBridge	171:3a7713b1edbc	1703	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge	171:3a7713b1edbc	1704	}
AnnaBridge	171:3a7713b1edbc	1705
AnnaBridge	171:3a7713b1edbc	1706	/**
AnnaBridge	171:3a7713b1edbc	1707	* @brief Clear Channel 7 half transfer flag.
AnnaBridge	171:3a7713b1edbc	1708	* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	171:3a7713b1edbc	1709	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1710	* @retval None
AnnaBridge	171:3a7713b1edbc	1711	*/
AnnaBridge	171:3a7713b1edbc	1712	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1713	{
AnnaBridge	171:3a7713b1edbc	1714	SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge	171:3a7713b1edbc	1715	}
AnnaBridge	171:3a7713b1edbc	1716
AnnaBridge	171:3a7713b1edbc	1717	/**
AnnaBridge	171:3a7713b1edbc	1718	* @brief Clear Channel 1 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1719	* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	171:3a7713b1edbc	1720	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1721	* @retval None
AnnaBridge	171:3a7713b1edbc	1722	*/
AnnaBridge	171:3a7713b1edbc	1723	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1724	{
AnnaBridge	171:3a7713b1edbc	1725	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge	171:3a7713b1edbc	1726	}
AnnaBridge	171:3a7713b1edbc	1727
AnnaBridge	171:3a7713b1edbc	1728	/**
AnnaBridge	171:3a7713b1edbc	1729	* @brief Clear Channel 2 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1730	* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	171:3a7713b1edbc	1731	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1732	* @retval None
AnnaBridge	171:3a7713b1edbc	1733	*/
AnnaBridge	171:3a7713b1edbc	1734	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1735	{
AnnaBridge	171:3a7713b1edbc	1736	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge	171:3a7713b1edbc	1737	}
AnnaBridge	171:3a7713b1edbc	1738
AnnaBridge	171:3a7713b1edbc	1739	/**
AnnaBridge	171:3a7713b1edbc	1740	* @brief Clear Channel 3 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1741	* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	171:3a7713b1edbc	1742	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1743	* @retval None
AnnaBridge	171:3a7713b1edbc	1744	*/
AnnaBridge	171:3a7713b1edbc	1745	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1746	{
AnnaBridge	171:3a7713b1edbc	1747	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge	171:3a7713b1edbc	1748	}
AnnaBridge	171:3a7713b1edbc	1749
AnnaBridge	171:3a7713b1edbc	1750	/**
AnnaBridge	171:3a7713b1edbc	1751	* @brief Clear Channel 4 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1752	* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	171:3a7713b1edbc	1753	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1754	* @retval None
AnnaBridge	171:3a7713b1edbc	1755	*/
AnnaBridge	171:3a7713b1edbc	1756	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1757	{
AnnaBridge	171:3a7713b1edbc	1758	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge	171:3a7713b1edbc	1759	}
AnnaBridge	171:3a7713b1edbc	1760
AnnaBridge	171:3a7713b1edbc	1761	/**
AnnaBridge	171:3a7713b1edbc	1762	* @brief Clear Channel 5 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1763	* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	171:3a7713b1edbc	1764	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1765	* @retval None
AnnaBridge	171:3a7713b1edbc	1766	*/
AnnaBridge	171:3a7713b1edbc	1767	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1768	{
AnnaBridge	171:3a7713b1edbc	1769	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge	171:3a7713b1edbc	1770	}
AnnaBridge	171:3a7713b1edbc	1771
AnnaBridge	171:3a7713b1edbc	1772	/**
AnnaBridge	171:3a7713b1edbc	1773	* @brief Clear Channel 6 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1774	* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	171:3a7713b1edbc	1775	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1776	* @retval None
AnnaBridge	171:3a7713b1edbc	1777	*/
AnnaBridge	171:3a7713b1edbc	1778	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1779	{
AnnaBridge	171:3a7713b1edbc	1780	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge	171:3a7713b1edbc	1781	}
AnnaBridge	171:3a7713b1edbc	1782
AnnaBridge	171:3a7713b1edbc	1783	/**
AnnaBridge	171:3a7713b1edbc	1784	* @brief Clear Channel 7 transfer error flag.
AnnaBridge	171:3a7713b1edbc	1785	* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	171:3a7713b1edbc	1786	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1787	* @retval None
AnnaBridge	171:3a7713b1edbc	1788	*/
AnnaBridge	171:3a7713b1edbc	1789	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	171:3a7713b1edbc	1790	{
AnnaBridge	171:3a7713b1edbc	1791	SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge	171:3a7713b1edbc	1792	}
AnnaBridge	171:3a7713b1edbc	1793
AnnaBridge	171:3a7713b1edbc	1794	/**
AnnaBridge	171:3a7713b1edbc	1795	* @}
AnnaBridge	171:3a7713b1edbc	1796	*/
AnnaBridge	171:3a7713b1edbc	1797
AnnaBridge	171:3a7713b1edbc	1798	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	171:3a7713b1edbc	1799	* @{
AnnaBridge	171:3a7713b1edbc	1800	*/
AnnaBridge	171:3a7713b1edbc	1801	/**
AnnaBridge	171:3a7713b1edbc	1802	* @brief Enable Transfer complete interrupt.
AnnaBridge	171:3a7713b1edbc	1803	* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge	171:3a7713b1edbc	1804	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1805	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1806	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1807	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1808	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1809	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1810	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1811	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1812	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1813	* @retval None
AnnaBridge	171:3a7713b1edbc	1814	*/
AnnaBridge	171:3a7713b1edbc	1815	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1816	{
AnnaBridge	171:3a7713b1edbc	1817	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	171:3a7713b1edbc	1818	}
AnnaBridge	171:3a7713b1edbc	1819
AnnaBridge	171:3a7713b1edbc	1820	/**
AnnaBridge	171:3a7713b1edbc	1821	* @brief Enable Half transfer interrupt.
AnnaBridge	171:3a7713b1edbc	1822	* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge	171:3a7713b1edbc	1823	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1824	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1825	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1826	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1827	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1828	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1829	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1830	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1831	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1832	* @retval None
AnnaBridge	171:3a7713b1edbc	1833	*/
AnnaBridge	171:3a7713b1edbc	1834	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1835	{
AnnaBridge	171:3a7713b1edbc	1836	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	171:3a7713b1edbc	1837	}
AnnaBridge	171:3a7713b1edbc	1838
AnnaBridge	171:3a7713b1edbc	1839	/**
AnnaBridge	171:3a7713b1edbc	1840	* @brief Enable Transfer error interrupt.
AnnaBridge	171:3a7713b1edbc	1841	* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge	171:3a7713b1edbc	1842	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1843	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1844	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1845	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1846	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1847	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1848	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1849	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1850	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1851	* @retval None
AnnaBridge	171:3a7713b1edbc	1852	*/
AnnaBridge	171:3a7713b1edbc	1853	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1854	{
AnnaBridge	171:3a7713b1edbc	1855	SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	171:3a7713b1edbc	1856	}
AnnaBridge	171:3a7713b1edbc	1857
AnnaBridge	171:3a7713b1edbc	1858	/**
AnnaBridge	171:3a7713b1edbc	1859	* @brief Disable Transfer complete interrupt.
AnnaBridge	171:3a7713b1edbc	1860	* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge	171:3a7713b1edbc	1861	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1862	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1863	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1864	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1865	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1866	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1867	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1868	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1869	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1870	* @retval None
AnnaBridge	171:3a7713b1edbc	1871	*/
AnnaBridge	171:3a7713b1edbc	1872	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1873	{
AnnaBridge	171:3a7713b1edbc	1874	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge	171:3a7713b1edbc	1875	}
AnnaBridge	171:3a7713b1edbc	1876
AnnaBridge	171:3a7713b1edbc	1877	/**
AnnaBridge	171:3a7713b1edbc	1878	* @brief Disable Half transfer interrupt.
AnnaBridge	171:3a7713b1edbc	1879	* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge	171:3a7713b1edbc	1880	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1881	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1882	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1883	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1884	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1885	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1886	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1887	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1888	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1889	* @retval None
AnnaBridge	171:3a7713b1edbc	1890	*/
AnnaBridge	171:3a7713b1edbc	1891	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1892	{
AnnaBridge	171:3a7713b1edbc	1893	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge	171:3a7713b1edbc	1894	}
AnnaBridge	171:3a7713b1edbc	1895
AnnaBridge	171:3a7713b1edbc	1896	/**
AnnaBridge	171:3a7713b1edbc	1897	* @brief Disable Transfer error interrupt.
AnnaBridge	171:3a7713b1edbc	1898	* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge	171:3a7713b1edbc	1899	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1900	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1901	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1902	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1903	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1904	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1905	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1906	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1907	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1908	* @retval None
AnnaBridge	171:3a7713b1edbc	1909	*/
AnnaBridge	171:3a7713b1edbc	1910	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1911	{
AnnaBridge	171:3a7713b1edbc	1912	CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge	171:3a7713b1edbc	1913	}
AnnaBridge	171:3a7713b1edbc	1914
AnnaBridge	171:3a7713b1edbc	1915	/**
AnnaBridge	171:3a7713b1edbc	1916	* @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge	171:3a7713b1edbc	1917	* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	171:3a7713b1edbc	1918	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1919	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1920	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1921	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1922	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1923	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1924	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1925	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1926	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1927	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1928	*/
AnnaBridge	171:3a7713b1edbc	1929	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1930	{
AnnaBridge	171:3a7713b1edbc	1931	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	1932	DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge	171:3a7713b1edbc	1933	}
AnnaBridge	171:3a7713b1edbc	1934
AnnaBridge	171:3a7713b1edbc	1935	/**
AnnaBridge	171:3a7713b1edbc	1936	* @brief Check if Half transfer Interrupt is enabled.
AnnaBridge	171:3a7713b1edbc	1937	* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	171:3a7713b1edbc	1938	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1939	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1940	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1941	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1942	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1943	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1944	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1945	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1946	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1947	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1948	*/
AnnaBridge	171:3a7713b1edbc	1949	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1950	{
AnnaBridge	171:3a7713b1edbc	1951	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	1952	DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge	171:3a7713b1edbc	1953	}
AnnaBridge	171:3a7713b1edbc	1954
AnnaBridge	171:3a7713b1edbc	1955	/**
AnnaBridge	171:3a7713b1edbc	1956	* @brief Check if Transfer error Interrupt is enabled.
AnnaBridge	171:3a7713b1edbc	1957	* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	171:3a7713b1edbc	1958	* @param DMAx DMAx Instance
AnnaBridge	171:3a7713b1edbc	1959	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1960	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	171:3a7713b1edbc	1961	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	171:3a7713b1edbc	1962	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	171:3a7713b1edbc	1963	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	171:3a7713b1edbc	1964	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	171:3a7713b1edbc	1965	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	171:3a7713b1edbc	1966	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	171:3a7713b1edbc	1967	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1968	*/
AnnaBridge	171:3a7713b1edbc	1969	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1970	{
AnnaBridge	171:3a7713b1edbc	1971	return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge	171:3a7713b1edbc	1972	DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge	171:3a7713b1edbc	1973	}
AnnaBridge	171:3a7713b1edbc	1974
AnnaBridge	171:3a7713b1edbc	1975	/**
AnnaBridge	171:3a7713b1edbc	1976	* @}
AnnaBridge	171:3a7713b1edbc	1977	*/
AnnaBridge	171:3a7713b1edbc	1978
AnnaBridge	171:3a7713b1edbc	1979	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	1980	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	171:3a7713b1edbc	1981	* @{
AnnaBridge	171:3a7713b1edbc	1982	*/
AnnaBridge	171:3a7713b1edbc	1983
AnnaBridge	171:3a7713b1edbc	1984	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	171:3a7713b1edbc	1985	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge	171:3a7713b1edbc	1986	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	171:3a7713b1edbc	1987
AnnaBridge	171:3a7713b1edbc	1988	/**
AnnaBridge	171:3a7713b1edbc	1989	* @}
AnnaBridge	171:3a7713b1edbc	1990	*/
AnnaBridge	171:3a7713b1edbc	1991	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	1992
AnnaBridge	171:3a7713b1edbc	1993	/**
AnnaBridge	171:3a7713b1edbc	1994	* @}
AnnaBridge	171:3a7713b1edbc	1995	*/
AnnaBridge	171:3a7713b1edbc	1996
AnnaBridge	171:3a7713b1edbc	1997	/**
AnnaBridge	171:3a7713b1edbc	1998	* @}
AnnaBridge	171:3a7713b1edbc	1999	*/
AnnaBridge	171:3a7713b1edbc	2000
AnnaBridge	171:3a7713b1edbc	2001	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	171:3a7713b1edbc	2002
AnnaBridge	171:3a7713b1edbc	2003	/**
AnnaBridge	171:3a7713b1edbc	2004	* @}
AnnaBridge	171:3a7713b1edbc	2005	*/
AnnaBridge	171:3a7713b1edbc	2006
AnnaBridge	171:3a7713b1edbc	2007	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2008	}
AnnaBridge	171:3a7713b1edbc	2009	#endif
AnnaBridge	171:3a7713b1edbc	2010
AnnaBridge	171:3a7713b1edbc	2011	#endif /* __STM32L1xx_LL_DMA_H */
AnnaBridge	171:3a7713b1edbc	2012
AnnaBridge	171:3a7713b1edbc	2013	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/