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TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_hal_spi.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_hal_spi.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of SPI HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32L1xx_HAL_SPI_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32L1xx_HAL_SPI_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32l1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32L1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup SPI |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup SPI_Exported_Types SPI Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 58 | */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | /** |
| AnnaBridge | 171:3a7713b1edbc | 61 | * @brief SPI Configuration Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 62 | */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 64 | { |
| AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
| AnnaBridge | 171:3a7713b1edbc | 66 | This parameter can be a value of @ref SPI_mode */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | uint32_t Direction; /*!< Specifies the SPI Directional mode state. |
| AnnaBridge | 171:3a7713b1edbc | 69 | This parameter can be a value of @ref SPI_Direction_mode */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | |
| AnnaBridge | 171:3a7713b1edbc | 71 | uint32_t DataSize; /*!< Specifies the SPI data size. |
| AnnaBridge | 171:3a7713b1edbc | 72 | This parameter can be a value of @ref SPI_data_size */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
| AnnaBridge | 171:3a7713b1edbc | 75 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
| AnnaBridge | 171:3a7713b1edbc | 78 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | |
| AnnaBridge | 171:3a7713b1edbc | 80 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
| AnnaBridge | 171:3a7713b1edbc | 81 | hardware (NSS pin) or by software using the SSI bit. |
| AnnaBridge | 171:3a7713b1edbc | 82 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| AnnaBridge | 171:3a7713b1edbc | 85 | used to configure the transmit and receive SCK clock. |
| AnnaBridge | 171:3a7713b1edbc | 86 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
| AnnaBridge | 171:3a7713b1edbc | 87 | @note The communication clock is derived from the master |
| AnnaBridge | 171:3a7713b1edbc | 88 | clock. The slave clock does not need to be set */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| AnnaBridge | 171:3a7713b1edbc | 91 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | |
| AnnaBridge | 171:3a7713b1edbc | 93 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
| AnnaBridge | 171:3a7713b1edbc | 94 | This parameter can be a value of @ref SPI_TI_mode */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | |
| AnnaBridge | 171:3a7713b1edbc | 96 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
| AnnaBridge | 171:3a7713b1edbc | 97 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | |
| AnnaBridge | 171:3a7713b1edbc | 99 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
| AnnaBridge | 171:3a7713b1edbc | 100 | This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | |
| AnnaBridge | 171:3a7713b1edbc | 102 | }SPI_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 103 | |
| AnnaBridge | 171:3a7713b1edbc | 104 | /** |
| AnnaBridge | 171:3a7713b1edbc | 105 | * @brief HAL SPI State structure definition |
| AnnaBridge | 171:3a7713b1edbc | 106 | */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | typedef enum |
| AnnaBridge | 171:3a7713b1edbc | 108 | { |
| AnnaBridge | 171:3a7713b1edbc | 109 | HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | |
| AnnaBridge | 171:3a7713b1edbc | 117 | }HAL_SPI_StateTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 118 | |
| AnnaBridge | 171:3a7713b1edbc | 119 | /** |
| AnnaBridge | 171:3a7713b1edbc | 120 | * @brief SPI handle Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 121 | */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | typedef struct __SPI_HandleTypeDef |
| AnnaBridge | 171:3a7713b1edbc | 123 | { |
| AnnaBridge | 171:3a7713b1edbc | 124 | SPI_TypeDef *Instance; /* SPI registers base address */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | |
| AnnaBridge | 171:3a7713b1edbc | 126 | SPI_InitTypeDef Init; /* SPI communication parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | |
| AnnaBridge | 171:3a7713b1edbc | 128 | uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | |
| AnnaBridge | 171:3a7713b1edbc | 130 | uint16_t TxXferSize; /* SPI Tx transfer size */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | |
| AnnaBridge | 171:3a7713b1edbc | 132 | __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | |
| AnnaBridge | 171:3a7713b1edbc | 134 | uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | |
| AnnaBridge | 171:3a7713b1edbc | 136 | uint16_t RxXferSize; /* SPI Rx transfer size */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | |
| AnnaBridge | 171:3a7713b1edbc | 138 | __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | |
| AnnaBridge | 171:3a7713b1edbc | 142 | DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | |
| AnnaBridge | 171:3a7713b1edbc | 144 | void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | |
| AnnaBridge | 171:3a7713b1edbc | 146 | void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | |
| AnnaBridge | 171:3a7713b1edbc | 148 | HAL_LockTypeDef Lock; /* SPI locking object */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | |
| AnnaBridge | 171:3a7713b1edbc | 150 | __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | |
| AnnaBridge | 171:3a7713b1edbc | 152 | __IO uint32_t ErrorCode; /* SPI Error code */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | |
| AnnaBridge | 171:3a7713b1edbc | 154 | }SPI_HandleTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 155 | /** |
| AnnaBridge | 171:3a7713b1edbc | 156 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 157 | */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | |
| AnnaBridge | 171:3a7713b1edbc | 159 | |
| AnnaBridge | 171:3a7713b1edbc | 160 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 161 | |
| AnnaBridge | 171:3a7713b1edbc | 162 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 163 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 164 | */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | |
| AnnaBridge | 171:3a7713b1edbc | 166 | /** @defgroup SPI_Error_Codes SPI Error Codes |
| AnnaBridge | 171:3a7713b1edbc | 167 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 168 | */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define HAL_SPI_ERROR_NONE (0x00U) /*!< No error */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define HAL_SPI_ERROR_MODF (0x01U) /*!< MODF error */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define HAL_SPI_ERROR_CRC (0x02U) /*!< CRC error */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define HAL_SPI_ERROR_OVR (0x04U) /*!< OVR error */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define HAL_SPI_ERROR_FRE (0x08U) /*!< FRE error */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define HAL_SPI_ERROR_DMA (0x10U) /*!< DMA transfer error */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define HAL_SPI_ERROR_FLAG (0x20U) /*!< Flag: RXNE,TXE, BSY */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | |
| AnnaBridge | 171:3a7713b1edbc | 177 | /** |
| AnnaBridge | 171:3a7713b1edbc | 178 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 179 | */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | |
| AnnaBridge | 171:3a7713b1edbc | 181 | /** @defgroup SPI_mode SPI mode |
| AnnaBridge | 171:3a7713b1edbc | 182 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 183 | */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define SPI_MODE_SLAVE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
| AnnaBridge | 171:3a7713b1edbc | 186 | |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 188 | ((MODE) == SPI_MODE_MASTER)) |
| AnnaBridge | 171:3a7713b1edbc | 189 | /** |
| AnnaBridge | 171:3a7713b1edbc | 190 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 191 | */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | |
| AnnaBridge | 171:3a7713b1edbc | 193 | /** @defgroup SPI_Direction_mode SPI Direction mode |
| AnnaBridge | 171:3a7713b1edbc | 194 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 195 | */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define SPI_DIRECTION_2LINES (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
| AnnaBridge | 171:3a7713b1edbc | 199 | |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 171:3a7713b1edbc | 201 | ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ |
| AnnaBridge | 171:3a7713b1edbc | 202 | ((MODE) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 171:3a7713b1edbc | 203 | |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ |
| AnnaBridge | 171:3a7713b1edbc | 205 | ((MODE) == SPI_DIRECTION_1LINE)) |
| AnnaBridge | 171:3a7713b1edbc | 206 | |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) |
| AnnaBridge | 171:3a7713b1edbc | 208 | |
| AnnaBridge | 171:3a7713b1edbc | 209 | /** |
| AnnaBridge | 171:3a7713b1edbc | 210 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 211 | */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | |
| AnnaBridge | 171:3a7713b1edbc | 213 | /** @defgroup SPI_data_size SPI data size |
| AnnaBridge | 171:3a7713b1edbc | 214 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 215 | */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define SPI_DATASIZE_8BIT (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define SPI_DATASIZE_16BIT SPI_CR1_DFF |
| AnnaBridge | 171:3a7713b1edbc | 218 | |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 220 | ((DATASIZE) == SPI_DATASIZE_8BIT)) |
| AnnaBridge | 171:3a7713b1edbc | 221 | /** |
| AnnaBridge | 171:3a7713b1edbc | 222 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 223 | */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | |
| AnnaBridge | 171:3a7713b1edbc | 225 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
| AnnaBridge | 171:3a7713b1edbc | 226 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 227 | */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define SPI_POLARITY_LOW (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
| AnnaBridge | 171:3a7713b1edbc | 230 | |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ |
| AnnaBridge | 171:3a7713b1edbc | 232 | ((CPOL) == SPI_POLARITY_HIGH)) |
| AnnaBridge | 171:3a7713b1edbc | 233 | /** |
| AnnaBridge | 171:3a7713b1edbc | 234 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 235 | */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | |
| AnnaBridge | 171:3a7713b1edbc | 237 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
| AnnaBridge | 171:3a7713b1edbc | 238 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 239 | */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define SPI_PHASE_1EDGE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
| AnnaBridge | 171:3a7713b1edbc | 242 | |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 244 | ((CPHA) == SPI_PHASE_2EDGE)) |
| AnnaBridge | 171:3a7713b1edbc | 245 | /** |
| AnnaBridge | 171:3a7713b1edbc | 246 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 247 | */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | |
| AnnaBridge | 171:3a7713b1edbc | 249 | /** @defgroup SPI_Slave_Select_management SPI Slave Select management |
| AnnaBridge | 171:3a7713b1edbc | 250 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 251 | */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define SPI_NSS_SOFT SPI_CR1_SSM |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define SPI_NSS_HARD_INPUT (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) |
| AnnaBridge | 171:3a7713b1edbc | 255 | |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 257 | ((NSS) == SPI_NSS_HARD_INPUT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 258 | ((NSS) == SPI_NSS_HARD_OUTPUT)) |
| AnnaBridge | 171:3a7713b1edbc | 259 | /** |
| AnnaBridge | 171:3a7713b1edbc | 260 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 261 | */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | |
| AnnaBridge | 171:3a7713b1edbc | 263 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 265 | */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
| AnnaBridge | 171:3a7713b1edbc | 274 | |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 276 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 277 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 278 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ |
| AnnaBridge | 171:3a7713b1edbc | 279 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ |
| AnnaBridge | 171:3a7713b1edbc | 280 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ |
| AnnaBridge | 171:3a7713b1edbc | 281 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ |
| AnnaBridge | 171:3a7713b1edbc | 282 | ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) |
| AnnaBridge | 171:3a7713b1edbc | 283 | /** |
| AnnaBridge | 171:3a7713b1edbc | 284 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 285 | */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | |
| AnnaBridge | 171:3a7713b1edbc | 287 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission |
| AnnaBridge | 171:3a7713b1edbc | 288 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 289 | */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define SPI_FIRSTBIT_MSB (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 294 | ((BIT) == SPI_FIRSTBIT_LSB)) |
| AnnaBridge | 171:3a7713b1edbc | 295 | /** |
| AnnaBridge | 171:3a7713b1edbc | 296 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 297 | */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | |
| AnnaBridge | 171:3a7713b1edbc | 299 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
| AnnaBridge | 171:3a7713b1edbc | 300 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 301 | */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define SPI_CRCCALCULATION_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
| AnnaBridge | 171:3a7713b1edbc | 304 | |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 306 | ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 307 | |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) |
| AnnaBridge | 171:3a7713b1edbc | 309 | /** |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 311 | */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | |
| AnnaBridge | 171:3a7713b1edbc | 313 | /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 315 | */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define SPI_IT_TXE SPI_CR2_TXEIE |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define SPI_IT_ERR SPI_CR2_ERRIE |
| AnnaBridge | 171:3a7713b1edbc | 319 | /** |
| AnnaBridge | 171:3a7713b1edbc | 320 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 321 | */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | |
| AnnaBridge | 171:3a7713b1edbc | 323 | /** @defgroup SPI_Flag_definition SPI Flag definition |
| AnnaBridge | 171:3a7713b1edbc | 324 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 325 | */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define SPI_FLAG_RXNE SPI_SR_RXNE |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define SPI_FLAG_TXE SPI_SR_TXE |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define SPI_FLAG_MODF SPI_SR_MODF |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define SPI_FLAG_OVR SPI_SR_OVR |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define SPI_FLAG_BSY SPI_SR_BSY |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define SPI_FLAG_FRE SPI_SR_FRE |
| AnnaBridge | 171:3a7713b1edbc | 333 | |
| AnnaBridge | 171:3a7713b1edbc | 334 | /** |
| AnnaBridge | 171:3a7713b1edbc | 335 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 336 | */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | |
| AnnaBridge | 171:3a7713b1edbc | 338 | /** |
| AnnaBridge | 171:3a7713b1edbc | 339 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 340 | */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | |
| AnnaBridge | 171:3a7713b1edbc | 342 | |
| AnnaBridge | 171:3a7713b1edbc | 343 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 344 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 346 | */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | |
| AnnaBridge | 171:3a7713b1edbc | 348 | /** @brief Reset SPI handle state |
| AnnaBridge | 171:3a7713b1edbc | 349 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 350 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 351 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 352 | */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 354 | |
| AnnaBridge | 171:3a7713b1edbc | 355 | /** @brief Enable or disable the specified SPI interrupts. |
| AnnaBridge | 171:3a7713b1edbc | 356 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 357 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 358 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| AnnaBridge | 171:3a7713b1edbc | 359 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 360 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 361 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 364 | */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 367 | |
| AnnaBridge | 171:3a7713b1edbc | 368 | /** @brief Check if the specified SPI interrupt source is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 370 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @param __INTERRUPT__: specifies the SPI interrupt source to check. |
| AnnaBridge | 171:3a7713b1edbc | 372 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 373 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @arg SPI_IT_ERR: Error interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 376 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 377 | */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 171:3a7713b1edbc | 379 | |
| AnnaBridge | 171:3a7713b1edbc | 380 | /** @brief Check whether the specified SPI flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 382 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 383 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 384 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 385 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
| AnnaBridge | 171:3a7713b1edbc | 386 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @arg SPI_FLAG_CRCERR: CRC error flag |
| AnnaBridge | 171:3a7713b1edbc | 388 | * @arg SPI_FLAG_MODF: Mode fault flag |
| AnnaBridge | 171:3a7713b1edbc | 389 | * @arg SPI_FLAG_OVR: Overrun flag |
| AnnaBridge | 171:3a7713b1edbc | 390 | * @arg SPI_FLAG_BSY: Busy flag |
| AnnaBridge | 171:3a7713b1edbc | 391 | * @arg SPI_FLAG_FRE: Frame format error flag |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 393 | */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 395 | |
| AnnaBridge | 171:3a7713b1edbc | 396 | /** @brief Clear the SPI CRCERR pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 398 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 399 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 400 | */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) |
| AnnaBridge | 171:3a7713b1edbc | 402 | |
| AnnaBridge | 171:3a7713b1edbc | 403 | /** @brief Clear the SPI MODF pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 404 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 405 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 406 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 407 | */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 409 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 410 | __IO uint32_t tmpreg_modf; \ |
| AnnaBridge | 171:3a7713b1edbc | 411 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 171:3a7713b1edbc | 412 | CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ |
| AnnaBridge | 171:3a7713b1edbc | 413 | UNUSED(tmpreg_modf); \ |
| AnnaBridge | 171:3a7713b1edbc | 414 | }while(0) |
| AnnaBridge | 171:3a7713b1edbc | 415 | |
| AnnaBridge | 171:3a7713b1edbc | 416 | /** @brief Clear the SPI OVR pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 417 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 418 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 419 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 420 | */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 422 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 423 | __IO uint32_t tmpreg_ovr; \ |
| AnnaBridge | 171:3a7713b1edbc | 424 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
| AnnaBridge | 171:3a7713b1edbc | 425 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 171:3a7713b1edbc | 426 | UNUSED(tmpreg_ovr); \ |
| AnnaBridge | 171:3a7713b1edbc | 427 | }while(0) |
| AnnaBridge | 171:3a7713b1edbc | 428 | |
| AnnaBridge | 171:3a7713b1edbc | 429 | /** @brief Clear the SPI FRE pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 430 | * @param __HANDLE__: specifies the SPI handle. |
| AnnaBridge | 171:3a7713b1edbc | 431 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 432 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 433 | */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 435 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 436 | __IO uint32_t tmpreg_fre; \ |
| AnnaBridge | 171:3a7713b1edbc | 437 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
| AnnaBridge | 171:3a7713b1edbc | 438 | UNUSED(tmpreg_fre); \ |
| AnnaBridge | 171:3a7713b1edbc | 439 | }while(0) |
| AnnaBridge | 171:3a7713b1edbc | 440 | |
| AnnaBridge | 171:3a7713b1edbc | 441 | /** @brief Enables the SPI. |
| AnnaBridge | 171:3a7713b1edbc | 442 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 443 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 444 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 445 | */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 171:3a7713b1edbc | 447 | |
| AnnaBridge | 171:3a7713b1edbc | 448 | /** @brief Disables the SPI. |
| AnnaBridge | 171:3a7713b1edbc | 449 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 450 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 451 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 452 | */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
| AnnaBridge | 171:3a7713b1edbc | 454 | /** |
| AnnaBridge | 171:3a7713b1edbc | 455 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 456 | */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | |
| AnnaBridge | 171:3a7713b1edbc | 458 | |
| AnnaBridge | 171:3a7713b1edbc | 459 | /* Private macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 460 | /** @defgroup SPI_Private_Macros SPI Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 461 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 462 | */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | |
| AnnaBridge | 171:3a7713b1edbc | 464 | /** @brief Sets the SPI transmit-only mode. |
| AnnaBridge | 171:3a7713b1edbc | 465 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 466 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 467 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 468 | */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 171:3a7713b1edbc | 470 | |
| AnnaBridge | 171:3a7713b1edbc | 471 | /** @brief Sets the SPI receive-only mode. |
| AnnaBridge | 171:3a7713b1edbc | 472 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 473 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 475 | */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
| AnnaBridge | 171:3a7713b1edbc | 477 | |
| AnnaBridge | 171:3a7713b1edbc | 478 | /** @brief Resets the CRC calculation of the SPI. |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @param __HANDLE__: specifies the SPI Handle. |
| AnnaBridge | 171:3a7713b1edbc | 480 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 482 | */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 484 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) |
| AnnaBridge | 171:3a7713b1edbc | 485 | /** |
| AnnaBridge | 171:3a7713b1edbc | 486 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 487 | */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | |
| AnnaBridge | 171:3a7713b1edbc | 489 | /* Include SPI HAL Extension module */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #include "stm32l1xx_hal_spi_ex.h" |
| AnnaBridge | 171:3a7713b1edbc | 491 | |
| AnnaBridge | 171:3a7713b1edbc | 492 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 493 | /** @addtogroup SPI_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 494 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 495 | */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | |
| AnnaBridge | 171:3a7713b1edbc | 497 | /* Initialization/de-initialization functions **********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 498 | /** @addtogroup SPI_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 499 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 500 | */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 502 | HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 503 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 504 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 505 | /** |
| AnnaBridge | 171:3a7713b1edbc | 506 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 507 | */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | |
| AnnaBridge | 171:3a7713b1edbc | 509 | /* I/O operation functions *****************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 510 | /** @addtogroup SPI_Exported_Functions_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 511 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 512 | */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 514 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 515 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 516 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 517 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 518 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 519 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 520 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 521 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 522 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 523 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 524 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 525 | |
| AnnaBridge | 171:3a7713b1edbc | 526 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 527 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 528 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 529 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 530 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 531 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 532 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 533 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 534 | /** |
| AnnaBridge | 171:3a7713b1edbc | 535 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 536 | */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | |
| AnnaBridge | 171:3a7713b1edbc | 538 | |
| AnnaBridge | 171:3a7713b1edbc | 539 | /* Peripheral State and Control functions **************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 540 | /** @addtogroup SPI_Exported_Functions_Group3 |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 542 | */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 544 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
| AnnaBridge | 171:3a7713b1edbc | 545 | |
| AnnaBridge | 171:3a7713b1edbc | 546 | /** |
| AnnaBridge | 171:3a7713b1edbc | 547 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 548 | */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | |
| AnnaBridge | 171:3a7713b1edbc | 550 | /** |
| AnnaBridge | 171:3a7713b1edbc | 551 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 552 | */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | |
| AnnaBridge | 171:3a7713b1edbc | 554 | |
| AnnaBridge | 171:3a7713b1edbc | 555 | /** |
| AnnaBridge | 171:3a7713b1edbc | 556 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 557 | */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | |
| AnnaBridge | 171:3a7713b1edbc | 559 | /** |
| AnnaBridge | 171:3a7713b1edbc | 560 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 561 | */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | |
| AnnaBridge | 171:3a7713b1edbc | 563 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 564 | } |
| AnnaBridge | 171:3a7713b1edbc | 565 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 566 | |
| AnnaBridge | 171:3a7713b1edbc | 567 | #endif /* __STM32L1xx_HAL_SPI_H */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | |
| AnnaBridge | 171:3a7713b1edbc | 569 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
