mbed official
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l1xx_hal_i2s.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_hal_i2s.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of I2S HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32L1xx_HAL_I2S_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32L1xx_HAL_I2S_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | #if defined(STM32L100xC) || \ |
| AnnaBridge | 171:3a7713b1edbc | 45 | defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || defined(STM32L151xDX) || \ |
| AnnaBridge | 171:3a7713b1edbc | 46 | defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L151xE) || defined(STM32L151xDX) || \ |
| AnnaBridge | 171:3a7713b1edbc | 47 | defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 50 | #include "stm32l1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 51 | |
| AnnaBridge | 171:3a7713b1edbc | 52 | /** @addtogroup STM32L1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 53 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 54 | */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | |
| AnnaBridge | 171:3a7713b1edbc | 56 | /** @addtogroup I2S |
| AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 58 | */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 61 | /** @defgroup I2S_Exported_Types I2S Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 62 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 63 | */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | |
| AnnaBridge | 171:3a7713b1edbc | 65 | /** |
| AnnaBridge | 171:3a7713b1edbc | 66 | * @brief I2S Init structure definition |
| AnnaBridge | 171:3a7713b1edbc | 67 | */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 69 | { |
| AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t Mode; /*!< Specifies the I2S operating mode. |
| AnnaBridge | 171:3a7713b1edbc | 71 | This parameter can be a value of @ref I2S_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | uint32_t Standard; /*!< Specifies the standard used for the I2S communication. |
| AnnaBridge | 171:3a7713b1edbc | 74 | This parameter can be a value of @ref I2S_Standard */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | |
| AnnaBridge | 171:3a7713b1edbc | 76 | uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. |
| AnnaBridge | 171:3a7713b1edbc | 77 | This parameter can be a value of @ref I2S_Data_Format */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. |
| AnnaBridge | 171:3a7713b1edbc | 80 | This parameter can be a value of @ref I2S_MCLK_Output */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | |
| AnnaBridge | 171:3a7713b1edbc | 82 | uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. |
| AnnaBridge | 171:3a7713b1edbc | 83 | This parameter can be a value of @ref I2S_Audio_Frequency */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. |
| AnnaBridge | 171:3a7713b1edbc | 86 | This parameter can be a value of @ref I2S_Clock_Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | |
| AnnaBridge | 171:3a7713b1edbc | 88 | }I2S_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | /** |
| AnnaBridge | 171:3a7713b1edbc | 91 | * @brief HAL State structures definition |
| AnnaBridge | 171:3a7713b1edbc | 92 | */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | typedef enum |
| AnnaBridge | 171:3a7713b1edbc | 94 | { |
| AnnaBridge | 171:3a7713b1edbc | 95 | HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S pause state: used in case of DMA */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | }HAL_I2S_StateTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 103 | |
| AnnaBridge | 171:3a7713b1edbc | 104 | /** |
| AnnaBridge | 171:3a7713b1edbc | 105 | * @brief I2S handle Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 106 | */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 108 | { |
| AnnaBridge | 171:3a7713b1edbc | 109 | SPI_TypeDef *Instance; /* I2S registers base address */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | |
| AnnaBridge | 171:3a7713b1edbc | 111 | I2S_InitTypeDef Init; /* I2S communication parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | |
| AnnaBridge | 171:3a7713b1edbc | 113 | uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | |
| AnnaBridge | 171:3a7713b1edbc | 115 | __IO uint16_t TxXferSize; /* I2S Tx transfer size */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | |
| AnnaBridge | 171:3a7713b1edbc | 117 | __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | |
| AnnaBridge | 171:3a7713b1edbc | 119 | uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | |
| AnnaBridge | 171:3a7713b1edbc | 121 | __IO uint16_t RxXferSize; /* I2S Rx transfer size */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | |
| AnnaBridge | 171:3a7713b1edbc | 123 | __IO uint16_t RxXferCount; /* I2S Rx transfer counter |
| AnnaBridge | 171:3a7713b1edbc | 124 | (This field is initialized at the |
| AnnaBridge | 171:3a7713b1edbc | 125 | same value as transfer size at the |
| AnnaBridge | 171:3a7713b1edbc | 126 | beginning of the transfer and |
| AnnaBridge | 171:3a7713b1edbc | 127 | decremented when a sample is received. |
| AnnaBridge | 171:3a7713b1edbc | 128 | NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | |
| AnnaBridge | 171:3a7713b1edbc | 130 | DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | |
| AnnaBridge | 171:3a7713b1edbc | 132 | DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | |
| AnnaBridge | 171:3a7713b1edbc | 134 | __IO HAL_LockTypeDef Lock; /* I2S locking object */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | |
| AnnaBridge | 171:3a7713b1edbc | 136 | __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | |
| AnnaBridge | 171:3a7713b1edbc | 138 | __IO uint32_t ErrorCode; /* I2S Error code */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | }I2S_HandleTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 141 | /** |
| AnnaBridge | 171:3a7713b1edbc | 142 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 143 | */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | |
| AnnaBridge | 171:3a7713b1edbc | 145 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 146 | /** @defgroup I2S_Exported_Constants I2S Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 147 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 148 | */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | |
| AnnaBridge | 171:3a7713b1edbc | 150 | /** @defgroup I2S_Error_Codes I2S Error Codes |
| AnnaBridge | 171:3a7713b1edbc | 151 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 152 | */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define HAL_I2S_ERROR_NONE (0x00U) /*!< No error */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define HAL_I2S_ERROR_UDR (0x01U) /*!< I2S Underrun error */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define HAL_I2S_ERROR_OVR (0x02U) /*!< I2S Overrun error */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define HAL_I2S_ERROR_FRE (0x04U) /*!< I2S Frame format error */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define HAL_I2S_ERROR_DMA (0x08U) /*!< DMA transfer error */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | |
| AnnaBridge | 171:3a7713b1edbc | 160 | /** |
| AnnaBridge | 171:3a7713b1edbc | 161 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 162 | */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | /** @defgroup I2S_Mode I2S Mode |
| AnnaBridge | 171:3a7713b1edbc | 165 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 166 | */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define I2S_MODE_SLAVE_TX (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define I2S_MODE_SLAVE_RX (0x00000100U) |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define I2S_MODE_MASTER_TX (0x00000200U) |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define I2S_MODE_MASTER_RX (0x00000300U) |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ |
| AnnaBridge | 171:3a7713b1edbc | 173 | ((MODE) == I2S_MODE_SLAVE_RX) || \ |
| AnnaBridge | 171:3a7713b1edbc | 174 | ((MODE) == I2S_MODE_MASTER_TX) || \ |
| AnnaBridge | 171:3a7713b1edbc | 175 | ((MODE) == I2S_MODE_MASTER_RX)) |
| AnnaBridge | 171:3a7713b1edbc | 176 | /** |
| AnnaBridge | 171:3a7713b1edbc | 177 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 178 | */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | |
| AnnaBridge | 171:3a7713b1edbc | 180 | /** @defgroup I2S_Standard I2S Standard |
| AnnaBridge | 171:3a7713b1edbc | 181 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 182 | */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define I2S_STANDARD_PHILIPS (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0) |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1) |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ |
| AnnaBridge | 171:3a7713b1edbc | 187 | SPI_I2SCFGR_I2SSTD_1)) |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ |
| AnnaBridge | 171:3a7713b1edbc | 189 | SPI_I2SCFGR_I2SSTD_1 |\ |
| AnnaBridge | 171:3a7713b1edbc | 190 | SPI_I2SCFGR_PCMSYNC)) |
| AnnaBridge | 171:3a7713b1edbc | 191 | |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ |
| AnnaBridge | 171:3a7713b1edbc | 193 | ((STANDARD) == I2S_STANDARD_MSB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 194 | ((STANDARD) == I2S_STANDARD_LSB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 195 | ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 196 | ((STANDARD) == I2S_STANDARD_PCM_LONG)) |
| AnnaBridge | 171:3a7713b1edbc | 197 | |
| AnnaBridge | 171:3a7713b1edbc | 198 | /** |
| AnnaBridge | 171:3a7713b1edbc | 199 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 200 | */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | |
| AnnaBridge | 171:3a7713b1edbc | 202 | /** @defgroup I2S_Data_Format I2S Data Format |
| AnnaBridge | 171:3a7713b1edbc | 203 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 204 | */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define I2S_DATAFORMAT_16B (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN) |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) |
| AnnaBridge | 171:3a7713b1edbc | 209 | |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 211 | ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ |
| AnnaBridge | 171:3a7713b1edbc | 212 | ((FORMAT) == I2S_DATAFORMAT_24B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 213 | ((FORMAT) == I2S_DATAFORMAT_32B)) |
| AnnaBridge | 171:3a7713b1edbc | 214 | /** |
| AnnaBridge | 171:3a7713b1edbc | 215 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 216 | */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | |
| AnnaBridge | 171:3a7713b1edbc | 218 | /** @defgroup I2S_MCLK_Output I2S MCLK Output |
| AnnaBridge | 171:3a7713b1edbc | 219 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 220 | */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define I2S_MCLKOUTPUT_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 223 | |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 225 | ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 226 | /** |
| AnnaBridge | 171:3a7713b1edbc | 227 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 228 | */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | |
| AnnaBridge | 171:3a7713b1edbc | 230 | /** @defgroup I2S_Audio_Frequency I2S Audio Frequency |
| AnnaBridge | 171:3a7713b1edbc | 231 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 232 | */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define I2S_AUDIOFREQ_192K (192000U) |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define I2S_AUDIOFREQ_96K (96000U) |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define I2S_AUDIOFREQ_48K (48000U) |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define I2S_AUDIOFREQ_44K (44100U) |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define I2S_AUDIOFREQ_32K (32000U) |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define I2S_AUDIOFREQ_22K (22050U) |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define I2S_AUDIOFREQ_16K (16000U) |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define I2S_AUDIOFREQ_11K (11025U) |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define I2S_AUDIOFREQ_8K (8000U) |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define I2S_AUDIOFREQ_DEFAULT (2U) |
| AnnaBridge | 171:3a7713b1edbc | 243 | |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ |
| AnnaBridge | 171:3a7713b1edbc | 245 | ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ |
| AnnaBridge | 171:3a7713b1edbc | 246 | ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) |
| AnnaBridge | 171:3a7713b1edbc | 247 | /** |
| AnnaBridge | 171:3a7713b1edbc | 248 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 249 | */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | |
| AnnaBridge | 171:3a7713b1edbc | 251 | /** @defgroup I2S_Clock_Polarity I2S Clock Polarity |
| AnnaBridge | 171:3a7713b1edbc | 252 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 253 | */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define I2S_CPOL_LOW (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) |
| AnnaBridge | 171:3a7713b1edbc | 256 | |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ |
| AnnaBridge | 171:3a7713b1edbc | 258 | ((CPOL) == I2S_CPOL_HIGH)) |
| AnnaBridge | 171:3a7713b1edbc | 259 | /** |
| AnnaBridge | 171:3a7713b1edbc | 260 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 261 | */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | |
| AnnaBridge | 171:3a7713b1edbc | 263 | /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 265 | */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define I2S_IT_TXE SPI_CR2_TXEIE |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define I2S_IT_RXNE SPI_CR2_RXNEIE |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define I2S_IT_ERR SPI_CR2_ERRIE |
| AnnaBridge | 171:3a7713b1edbc | 269 | /** |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 271 | */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | |
| AnnaBridge | 171:3a7713b1edbc | 273 | /** @defgroup I2S_Flag_definition I2S Flag definition |
| AnnaBridge | 171:3a7713b1edbc | 274 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 275 | */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define I2S_FLAG_TXE SPI_SR_TXE |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define I2S_FLAG_RXNE SPI_SR_RXNE |
| AnnaBridge | 171:3a7713b1edbc | 278 | |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define I2S_FLAG_UDR SPI_SR_UDR |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define I2S_FLAG_OVR SPI_SR_OVR |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define I2S_FLAG_FRE SPI_SR_FRE |
| AnnaBridge | 171:3a7713b1edbc | 282 | |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define I2S_FLAG_BSY SPI_SR_BSY |
| AnnaBridge | 171:3a7713b1edbc | 285 | /** |
| AnnaBridge | 171:3a7713b1edbc | 286 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 287 | */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | |
| AnnaBridge | 171:3a7713b1edbc | 289 | /** |
| AnnaBridge | 171:3a7713b1edbc | 290 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 291 | */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 294 | /** @defgroup I2S_Exported_macros I2S Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 295 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 296 | */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | |
| AnnaBridge | 171:3a7713b1edbc | 298 | /** @brief Reset I2S handle state |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @param __HANDLE__: specifies the I2S Handle. |
| AnnaBridge | 171:3a7713b1edbc | 300 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 301 | */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 303 | |
| AnnaBridge | 171:3a7713b1edbc | 304 | /** @brief Enable or disable the specified SPI peripheral (in I2S mode). |
| AnnaBridge | 171:3a7713b1edbc | 305 | * @param __HANDLE__: specifies the I2S Handle. |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 307 | */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
| AnnaBridge | 171:3a7713b1edbc | 310 | |
| AnnaBridge | 171:3a7713b1edbc | 311 | /** @brief Enable or disable the specified I2S interrupts. |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @param __HANDLE__: specifies the I2S Handle. |
| AnnaBridge | 171:3a7713b1edbc | 313 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| AnnaBridge | 171:3a7713b1edbc | 314 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 315 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 316 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 317 | * @arg I2S_IT_ERR: Error interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 318 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 319 | */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) |
| AnnaBridge | 171:3a7713b1edbc | 322 | |
| AnnaBridge | 171:3a7713b1edbc | 323 | /** @brief Checks if the specified I2S interrupt source is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 324 | * @param __HANDLE__: specifies the I2S Handle. |
| AnnaBridge | 171:3a7713b1edbc | 325 | * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. |
| AnnaBridge | 171:3a7713b1edbc | 326 | * @param __INTERRUPT__: specifies the I2S interrupt source to check. |
| AnnaBridge | 171:3a7713b1edbc | 327 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 328 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 329 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 330 | * @arg I2S_IT_ERR: Error interrupt enable |
| AnnaBridge | 171:3a7713b1edbc | 331 | * @retval The new state of __IT__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 332 | */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| AnnaBridge | 171:3a7713b1edbc | 334 | |
| AnnaBridge | 171:3a7713b1edbc | 335 | /** @brief Checks whether the specified I2S flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 336 | * @param __HANDLE__: specifies the I2S Handle. |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 338 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 339 | * @arg I2S_FLAG_RXNE: Receive buffer not empty flag |
| AnnaBridge | 171:3a7713b1edbc | 340 | * @arg I2S_FLAG_TXE: Transmit buffer empty flag |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @arg I2S_FLAG_UDR: Underrun flag |
| AnnaBridge | 171:3a7713b1edbc | 342 | * @arg I2S_FLAG_OVR: Overrun flag |
| AnnaBridge | 171:3a7713b1edbc | 343 | * @arg I2S_FLAG_FRE: Frame error flag |
| AnnaBridge | 171:3a7713b1edbc | 344 | * @arg I2S_FLAG_CHSIDE: Channel Side flag |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @arg I2S_FLAG_BSY: Busy flag |
| AnnaBridge | 171:3a7713b1edbc | 346 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 347 | */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 349 | |
| AnnaBridge | 171:3a7713b1edbc | 350 | /** @brief Clears the I2S OVR pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 351 | * @param __HANDLE__: specifies the I2S Handle. |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 353 | */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\ |
| AnnaBridge | 171:3a7713b1edbc | 355 | tmpreg = (__HANDLE__)->Instance->SR;\ |
| AnnaBridge | 171:3a7713b1edbc | 356 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 357 | }while(0) |
| AnnaBridge | 171:3a7713b1edbc | 358 | /** @brief Clears the I2S UDR pending flag. |
| AnnaBridge | 171:3a7713b1edbc | 359 | * @param __HANDLE__: specifies the I2S Handle. |
| AnnaBridge | 171:3a7713b1edbc | 360 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 361 | */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR) |
| AnnaBridge | 171:3a7713b1edbc | 363 | /** |
| AnnaBridge | 171:3a7713b1edbc | 364 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 365 | */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | |
| AnnaBridge | 171:3a7713b1edbc | 367 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 368 | /** @addtogroup I2S_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 370 | */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | |
| AnnaBridge | 171:3a7713b1edbc | 372 | /** @addtogroup I2S_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 373 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 374 | */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | /* Initialization/de-initialization functions ********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 376 | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 377 | HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 378 | void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 379 | void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 380 | /** |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 382 | */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | |
| AnnaBridge | 171:3a7713b1edbc | 384 | /** @addtogroup I2S_Exported_Functions_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 385 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 386 | */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | /* I/O operation functions ***************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 388 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 390 | HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 391 | |
| AnnaBridge | 171:3a7713b1edbc | 392 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 394 | HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 395 | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 396 | |
| AnnaBridge | 171:3a7713b1edbc | 397 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 399 | HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| AnnaBridge | 171:3a7713b1edbc | 400 | |
| AnnaBridge | 171:3a7713b1edbc | 401 | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 402 | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 403 | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 404 | |
| AnnaBridge | 171:3a7713b1edbc | 405 | /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ |
| AnnaBridge | 171:3a7713b1edbc | 406 | void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 407 | void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 408 | void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 409 | void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 410 | void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 411 | /** |
| AnnaBridge | 171:3a7713b1edbc | 412 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 413 | */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | |
| AnnaBridge | 171:3a7713b1edbc | 415 | /** @addtogroup I2S_Exported_Functions_Group3 |
| AnnaBridge | 171:3a7713b1edbc | 416 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 417 | */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | /* Peripheral Control and State functions ************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 419 | HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 420 | uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); |
| AnnaBridge | 171:3a7713b1edbc | 421 | /** |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 423 | */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | |
| AnnaBridge | 171:3a7713b1edbc | 425 | /** |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 427 | */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | |
| AnnaBridge | 171:3a7713b1edbc | 429 | |
| AnnaBridge | 171:3a7713b1edbc | 430 | /** |
| AnnaBridge | 171:3a7713b1edbc | 431 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 432 | */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | |
| AnnaBridge | 171:3a7713b1edbc | 434 | /** |
| AnnaBridge | 171:3a7713b1edbc | 435 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 436 | */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #endif /* STM32L100xC || |
| AnnaBridge | 171:3a7713b1edbc | 438 | STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE || STM32L151xDX ||\\ |
| AnnaBridge | 171:3a7713b1edbc | 439 | STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L152xDX || STM32L151xE || STM32L151xDX ||\\ |
| AnnaBridge | 171:3a7713b1edbc | 440 | STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | |
| AnnaBridge | 171:3a7713b1edbc | 442 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 443 | } |
| AnnaBridge | 171:3a7713b1edbc | 444 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 445 | |
| AnnaBridge | 171:3a7713b1edbc | 446 | #endif /* __STM32L1xx_HAL_I2S_H */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | |
| AnnaBridge | 171:3a7713b1edbc | 448 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
