mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_H743ZI/TOOLCHAIN_GCC_ARM/stm32h7xx_ll_pwr.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_pwr.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of PWR LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef STM32H7xx_LL_PWR_H
AnnaBridge	172:65be27845400	22	#define STM32H7xx_LL_PWR_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	#if defined(PWR)
AnnaBridge	172:65be27845400	36
AnnaBridge	172:65be27845400	37	/** @defgroup PWR_LL PWR
AnnaBridge	172:65be27845400	38	* @{
AnnaBridge	172:65be27845400	39	*/
AnnaBridge	172:65be27845400	40
AnnaBridge	172:65be27845400	41	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	42	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	43	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	44	/** @defgroup PWR_LL_Private_Constants PWR Private Constants
AnnaBridge	172:65be27845400	45	* @{
AnnaBridge	172:65be27845400	46	*/
AnnaBridge	172:65be27845400	47
AnnaBridge	172:65be27845400	48	/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
AnnaBridge	172:65be27845400	49	* @brief Flags defines which can be used with LL_PWR_WriteReg function
AnnaBridge	172:65be27845400	50	* @{
AnnaBridge	172:65be27845400	51	*/
AnnaBridge	172:65be27845400	52	/* Wake-Up Pins PWR register offsets */
AnnaBridge	172:65be27845400	53	#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
AnnaBridge	172:65be27845400	54	#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU
AnnaBridge	172:65be27845400	55	/**
AnnaBridge	172:65be27845400	56	* @}
AnnaBridge	172:65be27845400	57	*/
AnnaBridge	172:65be27845400	58	/**
AnnaBridge	172:65be27845400	59	* @}
AnnaBridge	172:65be27845400	60	*/
AnnaBridge	172:65be27845400	61	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	62	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	63	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	64	/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
AnnaBridge	172:65be27845400	65	* @{
AnnaBridge	172:65be27845400	66	*/
AnnaBridge	172:65be27845400	67
AnnaBridge	172:65be27845400	68	/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	172:65be27845400	69	* @brief Flags defines which can be used with LL_PWR_WriteReg function
AnnaBridge	172:65be27845400	70	* @{
AnnaBridge	172:65be27845400	71	*/
AnnaBridge	172:65be27845400	72	#define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /!< Clear CPU STANDBY, STOP and HOLD flags /
AnnaBridge	172:65be27845400	73	#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /!< Clear WKUP pin 6 /
AnnaBridge	172:65be27845400	74	#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /!< Clear WKUP pin 5 /
AnnaBridge	172:65be27845400	75	#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /!< Clear WKUP pin 4 /
AnnaBridge	172:65be27845400	76	#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /!< Clear WKUP pin 3 /
AnnaBridge	172:65be27845400	77	#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /!< Clear WKUP pin 2 /
AnnaBridge	172:65be27845400	78	#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /!< Clear WKUP pin 1 /
AnnaBridge	172:65be27845400	79	/**
AnnaBridge	172:65be27845400	80	* @}
AnnaBridge	172:65be27845400	81	*/
AnnaBridge	172:65be27845400	82
AnnaBridge	172:65be27845400	83	/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	172:65be27845400	84	* @brief Flags defines which can be used with LL_PWR_ReadReg function
AnnaBridge	172:65be27845400	85	* @{
AnnaBridge	172:65be27845400	86	*/
AnnaBridge	172:65be27845400	87	#define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /!< Analog Voltage Detect Output /
AnnaBridge	172:65be27845400	88	#define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /!< Power voltage detector output flag /
AnnaBridge	172:65be27845400	89	#define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /!< Current actual used VOS for VDD11 Voltage Scaling /
AnnaBridge	172:65be27845400	90	#define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /!< Ready bit for current actual used VOS for VDD11 Voltage Scaling /
AnnaBridge	172:65be27845400	91
AnnaBridge	172:65be27845400	92	#define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /!< Temperature high threshold flag /
AnnaBridge	172:65be27845400	93	#define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /!< Temperature low threshold flag /
AnnaBridge	172:65be27845400	94	#define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /!< VBAT high threshold flag /
AnnaBridge	172:65be27845400	95	#define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /!< VBAT low threshold flag /
AnnaBridge	172:65be27845400	96	#define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /!< Backup Regulator ready flag /
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	#define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /!< USB supply ready flag /
AnnaBridge	172:65be27845400	99
AnnaBridge	172:65be27845400	100	#define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /!< D2 domain DSTANDBY Flag /
AnnaBridge	172:65be27845400	101	#define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /!< D1 domain DSTANDBY Flag /
AnnaBridge	172:65be27845400	102	#define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /!< System STANDBY Flag /
AnnaBridge	172:65be27845400	103	#define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /!< STOP Flag /
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	#define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /!< Voltage scaling ready flag /
AnnaBridge	172:65be27845400	106
AnnaBridge	172:65be27845400	107	#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /!< Wakeup Pin Flag 6 /
AnnaBridge	172:65be27845400	108	#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /!< Wakeup Pin Flag 5 /
AnnaBridge	172:65be27845400	109	#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /!< Wakeup Pin Flag 4 /
AnnaBridge	172:65be27845400	110	#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /!< Wakeup Pin Flag 3 /
AnnaBridge	172:65be27845400	111	#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /!< Wakeup Pin Flag 2 /
AnnaBridge	172:65be27845400	112	#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /!< Wakeup Pin Flag 1 /
AnnaBridge	172:65be27845400	113	/**
AnnaBridge	172:65be27845400	114	* @}
AnnaBridge	172:65be27845400	115	*/
AnnaBridge	172:65be27845400	116
AnnaBridge	172:65be27845400	117	/** @defgroup PWR_LL_EC_MODE_PWR Power mode
AnnaBridge	172:65be27845400	118	* @{
AnnaBridge	172:65be27845400	119	*/
AnnaBridge	172:65be27845400	120	#define LL_PWR_CPU_MODE_D1STOP 0x00000000U /!< Enter D1 domain to Stop mode when the CPU enters deepsleep /
AnnaBridge	172:65be27845400	121	#define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /!< Enter D1 domain to Standby mode when the CPU enters deepsleep /
AnnaBridge	172:65be27845400	122	#define LL_PWR_CPU_MODE_D2STOP 0x00000000U /!< Enter Stop mode when the CPU enters deepsleep /
AnnaBridge	172:65be27845400	123	#define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /!< Enter D3 domain to Standby mode when the CPU enters deepsleep /
AnnaBridge	172:65be27845400	124	#define LL_PWR_CPU_MODE_D3STOP 0x00000000U /!< Enter Stop mode when the CPU enters deepsleep /
AnnaBridge	172:65be27845400	125	#define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /!< Enter D3 domain to Standby mode when the CPU enter deepsleep /
AnnaBridge	172:65be27845400	126	#define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /!< Keep system D3 domain in RUN mode when the CPU enter deepsleep /
AnnaBridge	172:65be27845400	127	/**
AnnaBridge	172:65be27845400	128	* @}
AnnaBridge	172:65be27845400	129	*/
AnnaBridge	172:65be27845400	130
AnnaBridge	172:65be27845400	131	/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
AnnaBridge	172:65be27845400	132	* @{
AnnaBridge	172:65be27845400	133	*/
AnnaBridge	172:65be27845400	134	#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /* Select voltage scale 3 */
AnnaBridge	172:65be27845400	135	#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /* Select voltage scale 2 */
AnnaBridge	172:65be27845400	136	#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 \| PWR_D3CR_VOS_1) /* Select voltage scale 1 */
AnnaBridge	172:65be27845400	137	/**
AnnaBridge	172:65be27845400	138	* @}
AnnaBridge	172:65be27845400	139	*/
AnnaBridge	172:65be27845400	140
AnnaBridge	172:65be27845400	141	/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
AnnaBridge	172:65be27845400	142	* @{
AnnaBridge	172:65be27845400	143	*/
AnnaBridge	172:65be27845400	144	#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /* Select voltage scale 5 when system enters STOP mode */
AnnaBridge	172:65be27845400	145	#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /* Select voltage scale 4 when system enters STOP mode */
AnnaBridge	172:65be27845400	146	#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 \| PWR_CR1_SVOS_1) /* Select voltage scale 3 when system enters STOP mode */
AnnaBridge	172:65be27845400	147	/**
AnnaBridge	172:65be27845400	148	* @}
AnnaBridge	172:65be27845400	149	*/
AnnaBridge	172:65be27845400	150
AnnaBridge	172:65be27845400	151	/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
AnnaBridge	172:65be27845400	152	* @{
AnnaBridge	172:65be27845400	153	*/
AnnaBridge	172:65be27845400	154	#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /!< Voltage Regulator in main mode during deepsleep mode /
AnnaBridge	172:65be27845400	155	#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /!< Voltage Regulator in low-power mode during deepsleep mode /
AnnaBridge	172:65be27845400	156	/**
AnnaBridge	172:65be27845400	157	* @}
AnnaBridge	172:65be27845400	158	*/
AnnaBridge	172:65be27845400	159
AnnaBridge	172:65be27845400	160	/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
AnnaBridge	172:65be27845400	161	* @{
AnnaBridge	172:65be27845400	162	*/
AnnaBridge	172:65be27845400	163	#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /!< Voltage threshold detected by PVD 1.95 V /
AnnaBridge	172:65be27845400	164	#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /!< Voltage threshold detected by PVD 2.1 V /
AnnaBridge	172:65be27845400	165	#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /!< Voltage threshold detected by PVD 2.25 V /
AnnaBridge	172:65be27845400	166	#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /!< Voltage threshold detected by PVD 2.4 V /
AnnaBridge	172:65be27845400	167	#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /!< Voltage threshold detected by PVD 2.55 V /
AnnaBridge	172:65be27845400	168	#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /!< Voltage threshold detected by PVD 2.7 V /
AnnaBridge	172:65be27845400	169	#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /!< Voltage threshold detected by PVD 2.85 V /
AnnaBridge	172:65be27845400	170	#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /!< External voltage level on PVD_IN pin, compared to internal VREFINT level. /
AnnaBridge	172:65be27845400	171	/**
AnnaBridge	172:65be27845400	172	* @}
AnnaBridge	172:65be27845400	173	*/
AnnaBridge	172:65be27845400	174
AnnaBridge	172:65be27845400	175	/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
AnnaBridge	172:65be27845400	176	* @{
AnnaBridge	172:65be27845400	177	*/
AnnaBridge	172:65be27845400	178	#define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /!< Analog Voltage threshold detected by AVD 1.7 V /
AnnaBridge	172:65be27845400	179	#define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /!< Analog Voltage threshold detected by AVD 2.1 V /
AnnaBridge	172:65be27845400	180	#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /!< Analog Voltage threshold detected by AVD 2.5 V /
AnnaBridge	172:65be27845400	181	#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /!< Analog Voltage threshold detected by AVD 2.8 V /
AnnaBridge	172:65be27845400	182
AnnaBridge	172:65be27845400	183	/**
AnnaBridge	172:65be27845400	184	* @}
AnnaBridge	172:65be27845400	185	*/
AnnaBridge	172:65be27845400	186
AnnaBridge	172:65be27845400	187	/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
AnnaBridge	172:65be27845400	188	* @{
AnnaBridge	172:65be27845400	189	*/
AnnaBridge	172:65be27845400	190	#define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /!< Charge the Battery through a 5 kO resistor /
AnnaBridge	172:65be27845400	191	#define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /!< Charge the Battery through a 1.5 kO resistor /
AnnaBridge	172:65be27845400	192	/**
AnnaBridge	172:65be27845400	193	* @}
AnnaBridge	172:65be27845400	194	*/
AnnaBridge	172:65be27845400	195
AnnaBridge	172:65be27845400	196	/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
AnnaBridge	172:65be27845400	197	* @{
AnnaBridge	172:65be27845400	198	*/
AnnaBridge	172:65be27845400	199	#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /!< Wake-Up pin 1 : PA0 /
AnnaBridge	172:65be27845400	200	#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /!< Wake-Up pin 2 : PA2 /
AnnaBridge	172:65be27845400	201	#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /!< Wake-Up pin 3 : PC1 /
AnnaBridge	172:65be27845400	202	#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /!< Wake-Up pin 4 : PC13 /
AnnaBridge	172:65be27845400	203	#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /!< Wake-Up pin 5 : PI8 /
AnnaBridge	172:65be27845400	204	#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /!< Wake-Up pin 6 : PI11 /
AnnaBridge	172:65be27845400	205	/**
AnnaBridge	172:65be27845400	206	* @}
AnnaBridge	172:65be27845400	207	*/
AnnaBridge	172:65be27845400	208
AnnaBridge	172:65be27845400	209	/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
AnnaBridge	172:65be27845400	210	* @{
AnnaBridge	172:65be27845400	211	*/
AnnaBridge	172:65be27845400	212	#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /!< Configure Wake-Up pin in no pull /
AnnaBridge	172:65be27845400	213	#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /!< Configure Wake-Up pin in pull Up /
AnnaBridge	172:65be27845400	214	#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /!< Configure Wake-Up pin in pull Down /
AnnaBridge	172:65be27845400	215	/**
AnnaBridge	172:65be27845400	216	* @}
AnnaBridge	172:65be27845400	217	*/
AnnaBridge	172:65be27845400	218
AnnaBridge	172:65be27845400	219	/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
AnnaBridge	172:65be27845400	220	* @{
AnnaBridge	172:65be27845400	221	*/
AnnaBridge	172:65be27845400	222	#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */
AnnaBridge	172:65be27845400	223	#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /* LDO Bypassed. The Core domain is supplied from an external source */
AnnaBridge	172:65be27845400	224	/**
AnnaBridge	172:65be27845400	225	* @}
AnnaBridge	172:65be27845400	226	*/
AnnaBridge	172:65be27845400	227
AnnaBridge	172:65be27845400	228	/**
AnnaBridge	172:65be27845400	229	* @}
AnnaBridge	172:65be27845400	230	*/
AnnaBridge	172:65be27845400	231	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	232	/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
AnnaBridge	172:65be27845400	233	* @{
AnnaBridge	172:65be27845400	234	*/
AnnaBridge	172:65be27845400	235
AnnaBridge	172:65be27845400	236	/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
AnnaBridge	172:65be27845400	237	* @{
AnnaBridge	172:65be27845400	238	*/
AnnaBridge	172:65be27845400	239
AnnaBridge	172:65be27845400	240	/**
AnnaBridge	172:65be27845400	241	* @brief Write a value in PWR register
AnnaBridge	172:65be27845400	242	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	243	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	244	* @retval None
AnnaBridge	172:65be27845400	245	*/
AnnaBridge	172:65be27845400	246	#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	247
AnnaBridge	172:65be27845400	248	/**
AnnaBridge	172:65be27845400	249	* @brief Read a value in PWR register
AnnaBridge	172:65be27845400	250	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	251	* @retval Register value
AnnaBridge	172:65be27845400	252	*/
AnnaBridge	172:65be27845400	253	#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
AnnaBridge	172:65be27845400	254	/**
AnnaBridge	172:65be27845400	255	* @}
AnnaBridge	172:65be27845400	256	*/
AnnaBridge	172:65be27845400	257
AnnaBridge	172:65be27845400	258	/**
AnnaBridge	172:65be27845400	259	* @}
AnnaBridge	172:65be27845400	260	*/
AnnaBridge	172:65be27845400	261	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	262	/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
AnnaBridge	172:65be27845400	263	* @{
AnnaBridge	172:65be27845400	264	*/
AnnaBridge	172:65be27845400	265
AnnaBridge	172:65be27845400	266	/** @defgroup PWR_LL_EF_Configuration Configuration
AnnaBridge	172:65be27845400	267	* @{
AnnaBridge	172:65be27845400	268	*/
AnnaBridge	172:65be27845400	269
AnnaBridge	172:65be27845400	270	/**
AnnaBridge	172:65be27845400	271	* @brief Set the voltage Regulator mode during deep sleep mode
AnnaBridge	172:65be27845400	272	* @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS
AnnaBridge	172:65be27845400	273	* @param RegulMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	274	* @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge	172:65be27845400	275	* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge	172:65be27845400	276	* @retval None
AnnaBridge	172:65be27845400	277	*/
AnnaBridge	172:65be27845400	278	__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
AnnaBridge	172:65be27845400	279	{
AnnaBridge	172:65be27845400	280	MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
AnnaBridge	172:65be27845400	281	}
AnnaBridge	172:65be27845400	282
AnnaBridge	172:65be27845400	283	/**
AnnaBridge	172:65be27845400	284	* @brief Get the voltage Regulator mode during deep sleep mode
AnnaBridge	172:65be27845400	285	* @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS
AnnaBridge	172:65be27845400	286	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	287	* @arg @ref LL_PWR_REGU_DSMODE_MAIN
AnnaBridge	172:65be27845400	288	* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
AnnaBridge	172:65be27845400	289	*/
AnnaBridge	172:65be27845400	290	__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
AnnaBridge	172:65be27845400	291	{
AnnaBridge	172:65be27845400	292	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
AnnaBridge	172:65be27845400	293	}
AnnaBridge	172:65be27845400	294
AnnaBridge	172:65be27845400	295	/**
AnnaBridge	172:65be27845400	296	* @brief Enable Power Voltage Detector
AnnaBridge	172:65be27845400	297	* @rmtoll CR1 PVDEN LL_PWR_EnablePVD
AnnaBridge	172:65be27845400	298	* @retval None
AnnaBridge	172:65be27845400	299	*/
AnnaBridge	172:65be27845400	300	__STATIC_INLINE void LL_PWR_EnablePVD(void)
AnnaBridge	172:65be27845400	301	{
AnnaBridge	172:65be27845400	302	SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
AnnaBridge	172:65be27845400	303	}
AnnaBridge	172:65be27845400	304
AnnaBridge	172:65be27845400	305	/**
AnnaBridge	172:65be27845400	306	* @brief Disable Power Voltage Detector
AnnaBridge	172:65be27845400	307	* @rmtoll CR1 PVDEN LL_PWR_DisablePVD
AnnaBridge	172:65be27845400	308	* @retval None
AnnaBridge	172:65be27845400	309	*/
AnnaBridge	172:65be27845400	310	__STATIC_INLINE void LL_PWR_DisablePVD(void)
AnnaBridge	172:65be27845400	311	{
AnnaBridge	172:65be27845400	312	CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
AnnaBridge	172:65be27845400	313	}
AnnaBridge	172:65be27845400	314
AnnaBridge	172:65be27845400	315	/**
AnnaBridge	172:65be27845400	316	* @brief Check if Power Voltage Detector is enabled
AnnaBridge	172:65be27845400	317	* @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD
AnnaBridge	172:65be27845400	318	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	319	*/
AnnaBridge	172:65be27845400	320	__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
AnnaBridge	172:65be27845400	321	{
AnnaBridge	172:65be27845400	322	return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	323	}
AnnaBridge	172:65be27845400	324
AnnaBridge	172:65be27845400	325	/**
AnnaBridge	172:65be27845400	326	* @brief Configure the voltage threshold detected by the Power Voltage Detector
AnnaBridge	172:65be27845400	327	* @rmtoll CR1 PLS LL_PWR_SetPVDLevel
AnnaBridge	172:65be27845400	328	* @param PVDLevel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	329	* @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge	172:65be27845400	330	* @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge	172:65be27845400	331	* @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge	172:65be27845400	332	* @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge	172:65be27845400	333	* @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge	172:65be27845400	334	* @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge	172:65be27845400	335	* @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge	172:65be27845400	336	* @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge	172:65be27845400	337	* @retval None
AnnaBridge	172:65be27845400	338	*/
AnnaBridge	172:65be27845400	339	__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
AnnaBridge	172:65be27845400	340	{
AnnaBridge	172:65be27845400	341	MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
AnnaBridge	172:65be27845400	342	}
AnnaBridge	172:65be27845400	343
AnnaBridge	172:65be27845400	344	/**
AnnaBridge	172:65be27845400	345	* @brief Get the voltage threshold detection
AnnaBridge	172:65be27845400	346	* @rmtoll CR1 PLS LL_PWR_GetPVDLevel
AnnaBridge	172:65be27845400	347	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	348	* @arg @ref LL_PWR_PVDLEVEL_0
AnnaBridge	172:65be27845400	349	* @arg @ref LL_PWR_PVDLEVEL_1
AnnaBridge	172:65be27845400	350	* @arg @ref LL_PWR_PVDLEVEL_2
AnnaBridge	172:65be27845400	351	* @arg @ref LL_PWR_PVDLEVEL_3
AnnaBridge	172:65be27845400	352	* @arg @ref LL_PWR_PVDLEVEL_4
AnnaBridge	172:65be27845400	353	* @arg @ref LL_PWR_PVDLEVEL_5
AnnaBridge	172:65be27845400	354	* @arg @ref LL_PWR_PVDLEVEL_6
AnnaBridge	172:65be27845400	355	* @arg @ref LL_PWR_PVDLEVEL_7
AnnaBridge	172:65be27845400	356	*/
AnnaBridge	172:65be27845400	357	__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
AnnaBridge	172:65be27845400	358	{
AnnaBridge	172:65be27845400	359	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
AnnaBridge	172:65be27845400	360	}
AnnaBridge	172:65be27845400	361
AnnaBridge	172:65be27845400	362	/**
AnnaBridge	172:65be27845400	363	* @brief Enable access to the backup domain
AnnaBridge	172:65be27845400	364	* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
AnnaBridge	172:65be27845400	365	* @retval None
AnnaBridge	172:65be27845400	366	*/
AnnaBridge	172:65be27845400	367	__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
AnnaBridge	172:65be27845400	368	{
AnnaBridge	172:65be27845400	369	SET_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge	172:65be27845400	370	}
AnnaBridge	172:65be27845400	371
AnnaBridge	172:65be27845400	372	/**
AnnaBridge	172:65be27845400	373	* @brief Disable access to the backup domain
AnnaBridge	172:65be27845400	374	* @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
AnnaBridge	172:65be27845400	375	* @retval None
AnnaBridge	172:65be27845400	376	*/
AnnaBridge	172:65be27845400	377	__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
AnnaBridge	172:65be27845400	378	{
AnnaBridge	172:65be27845400	379	CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
AnnaBridge	172:65be27845400	380	}
AnnaBridge	172:65be27845400	381
AnnaBridge	172:65be27845400	382	/**
AnnaBridge	172:65be27845400	383	* @brief Check if the backup domain is enabled
AnnaBridge	172:65be27845400	384	* @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
AnnaBridge	172:65be27845400	385	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	386	*/
AnnaBridge	172:65be27845400	387	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
AnnaBridge	172:65be27845400	388	{
AnnaBridge	172:65be27845400	389	return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	390	}
AnnaBridge	172:65be27845400	391
AnnaBridge	172:65be27845400	392	/**
AnnaBridge	172:65be27845400	393	* @brief Enable the Flash Power Down in Stop Mode
AnnaBridge	172:65be27845400	394	* @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown
AnnaBridge	172:65be27845400	395	* @retval None
AnnaBridge	172:65be27845400	396	*/
AnnaBridge	172:65be27845400	397	__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
AnnaBridge	172:65be27845400	398	{
AnnaBridge	172:65be27845400	399	SET_BIT(PWR->CR1, PWR_CR1_FLPS);
AnnaBridge	172:65be27845400	400	}
AnnaBridge	172:65be27845400	401
AnnaBridge	172:65be27845400	402	/**
AnnaBridge	172:65be27845400	403	* @brief Disable the Flash Power Down in Stop Mode
AnnaBridge	172:65be27845400	404	* @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown
AnnaBridge	172:65be27845400	405	* @retval None
AnnaBridge	172:65be27845400	406	*/
AnnaBridge	172:65be27845400	407	__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
AnnaBridge	172:65be27845400	408	{
AnnaBridge	172:65be27845400	409	CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
AnnaBridge	172:65be27845400	410	}
AnnaBridge	172:65be27845400	411
AnnaBridge	172:65be27845400	412	/**
AnnaBridge	172:65be27845400	413	* @brief Check if the Flash Power Down in Stop Mode is enabled
AnnaBridge	172:65be27845400	414	* @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown
AnnaBridge	172:65be27845400	415	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	416	*/
AnnaBridge	172:65be27845400	417	__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
AnnaBridge	172:65be27845400	418	{
AnnaBridge	172:65be27845400	419	return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	420	}
AnnaBridge	172:65be27845400	421
AnnaBridge	172:65be27845400	422	/**
AnnaBridge	172:65be27845400	423	* @brief Set the internal Regulator output voltage in STOP mode
AnnaBridge	172:65be27845400	424	* @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling
AnnaBridge	172:65be27845400	425	* @param VoltageScaling This parameter can be one of the following values:
AnnaBridge	172:65be27845400	426	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
AnnaBridge	172:65be27845400	427	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
AnnaBridge	172:65be27845400	428	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
AnnaBridge	172:65be27845400	429	* @retval None
AnnaBridge	172:65be27845400	430	*/
AnnaBridge	172:65be27845400	431	__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
AnnaBridge	172:65be27845400	432	{
AnnaBridge	172:65be27845400	433	MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
AnnaBridge	172:65be27845400	434	}
AnnaBridge	172:65be27845400	435
AnnaBridge	172:65be27845400	436	/**
AnnaBridge	172:65be27845400	437	* @brief Get the internal Regulator output voltage in STOP mode
AnnaBridge	172:65be27845400	438	* @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling
AnnaBridge	172:65be27845400	439	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	440	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
AnnaBridge	172:65be27845400	441	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
AnnaBridge	172:65be27845400	442	* @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
AnnaBridge	172:65be27845400	443	*/
AnnaBridge	172:65be27845400	444	__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
AnnaBridge	172:65be27845400	445	{
AnnaBridge	172:65be27845400	446	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
AnnaBridge	172:65be27845400	447	}
AnnaBridge	172:65be27845400	448
AnnaBridge	172:65be27845400	449	/**
AnnaBridge	172:65be27845400	450	* @brief Enable Analog Power Voltage Detector
AnnaBridge	172:65be27845400	451	* @rmtoll CR1 AVDEN LL_PWR_EnableAVD
AnnaBridge	172:65be27845400	452	* @retval None
AnnaBridge	172:65be27845400	453	*/
AnnaBridge	172:65be27845400	454	__STATIC_INLINE void LL_PWR_EnableAVD(void)
AnnaBridge	172:65be27845400	455	{
AnnaBridge	172:65be27845400	456	SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
AnnaBridge	172:65be27845400	457	}
AnnaBridge	172:65be27845400	458
AnnaBridge	172:65be27845400	459	/**
AnnaBridge	172:65be27845400	460	* @brief Disable Analog Power Voltage Detector
AnnaBridge	172:65be27845400	461	* @rmtoll CR1 AVDEN LL_PWR_DisableAVD
AnnaBridge	172:65be27845400	462	* @retval None
AnnaBridge	172:65be27845400	463	*/
AnnaBridge	172:65be27845400	464	__STATIC_INLINE void LL_PWR_DisableAVD(void)
AnnaBridge	172:65be27845400	465	{
AnnaBridge	172:65be27845400	466	CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
AnnaBridge	172:65be27845400	467	}
AnnaBridge	172:65be27845400	468
AnnaBridge	172:65be27845400	469	/**
AnnaBridge	172:65be27845400	470	* @brief Check if Analog Power Voltage Detector is enabled
AnnaBridge	172:65be27845400	471	* @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD
AnnaBridge	172:65be27845400	472	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	473	*/
AnnaBridge	172:65be27845400	474	__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
AnnaBridge	172:65be27845400	475	{
AnnaBridge	172:65be27845400	476	return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	477	}
AnnaBridge	172:65be27845400	478
AnnaBridge	172:65be27845400	479	/**
AnnaBridge	172:65be27845400	480	* @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
AnnaBridge	172:65be27845400	481	* @rmtoll CR1 ALS LL_PWR_SetAVDLevel
AnnaBridge	172:65be27845400	482	* @param AVDLevel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	483	* @arg @ref LL_PWR_AVDLEVEL_0
AnnaBridge	172:65be27845400	484	* @arg @ref LL_PWR_AVDLEVEL_1
AnnaBridge	172:65be27845400	485	* @arg @ref LL_PWR_AVDLEVEL_2
AnnaBridge	172:65be27845400	486	* @arg @ref LL_PWR_AVDLEVEL_3
AnnaBridge	172:65be27845400	487	* @retval None
AnnaBridge	172:65be27845400	488	*/
AnnaBridge	172:65be27845400	489	__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
AnnaBridge	172:65be27845400	490	{
AnnaBridge	172:65be27845400	491	MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
AnnaBridge	172:65be27845400	492	}
AnnaBridge	172:65be27845400	493
AnnaBridge	172:65be27845400	494	/**
AnnaBridge	172:65be27845400	495	* @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
AnnaBridge	172:65be27845400	496	* @rmtoll CR1 ALS LL_PWR_GetAVDLevel
AnnaBridge	172:65be27845400	497	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	498	* @arg @ref LL_PWR_AVDLEVEL_0
AnnaBridge	172:65be27845400	499	* @arg @ref LL_PWR_AVDLEVEL_1
AnnaBridge	172:65be27845400	500	* @arg @ref LL_PWR_AVDLEVEL_2
AnnaBridge	172:65be27845400	501	* @arg @ref LL_PWR_AVDLEVEL_3
AnnaBridge	172:65be27845400	502	*/
AnnaBridge	172:65be27845400	503	__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
AnnaBridge	172:65be27845400	504	{
AnnaBridge	172:65be27845400	505	return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
AnnaBridge	172:65be27845400	506	}
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	/**
AnnaBridge	172:65be27845400	509	* @brief Enable Backup Regulator
AnnaBridge	172:65be27845400	510	* @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator
AnnaBridge	172:65be27845400	511	* @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
AnnaBridge	172:65be27845400	512	* VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
AnnaBridge	172:65be27845400	513	* SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
AnnaBridge	172:65be27845400	514	* the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
AnnaBridge	172:65be27845400	515	* the data written into the RAM will be maintained in the Standby and VBAT modes.
AnnaBridge	172:65be27845400	516	* @retval None
AnnaBridge	172:65be27845400	517	*/
AnnaBridge	172:65be27845400	518	__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
AnnaBridge	172:65be27845400	519	{
AnnaBridge	172:65be27845400	520	SET_BIT(PWR->CR2, PWR_CR2_BREN);
AnnaBridge	172:65be27845400	521	}
AnnaBridge	172:65be27845400	522
AnnaBridge	172:65be27845400	523	/**
AnnaBridge	172:65be27845400	524	* @brief Disable Backup Regulator
AnnaBridge	172:65be27845400	525	* @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator
AnnaBridge	172:65be27845400	526	* @retval None
AnnaBridge	172:65be27845400	527	*/
AnnaBridge	172:65be27845400	528	__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
AnnaBridge	172:65be27845400	529	{
AnnaBridge	172:65be27845400	530	CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
AnnaBridge	172:65be27845400	531	}
AnnaBridge	172:65be27845400	532
AnnaBridge	172:65be27845400	533	/**
AnnaBridge	172:65be27845400	534	* @brief Check if the backup Regulator is enabled
AnnaBridge	172:65be27845400	535	* @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator
AnnaBridge	172:65be27845400	536	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	537	*/
AnnaBridge	172:65be27845400	538	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
AnnaBridge	172:65be27845400	539	{
AnnaBridge	172:65be27845400	540	return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	541	}
AnnaBridge	172:65be27845400	542
AnnaBridge	172:65be27845400	543	/**
AnnaBridge	172:65be27845400	544	* @brief Enable VBAT and Temperature monitoring
AnnaBridge	172:65be27845400	545	* @rmtoll CR2 MONEN LL_PWR_EnableMonitoring
AnnaBridge	172:65be27845400	546	* @retval None
AnnaBridge	172:65be27845400	547	*/
AnnaBridge	172:65be27845400	548	__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
AnnaBridge	172:65be27845400	549	{
AnnaBridge	172:65be27845400	550	SET_BIT(PWR->CR2, PWR_CR2_MONEN);
AnnaBridge	172:65be27845400	551	}
AnnaBridge	172:65be27845400	552
AnnaBridge	172:65be27845400	553	/**
AnnaBridge	172:65be27845400	554	* @brief Disable VBAT and Temperature monitoring
AnnaBridge	172:65be27845400	555	* @rmtoll CR2 MONEN LL_PWR_DisableMonitoring
AnnaBridge	172:65be27845400	556	* @retval None
AnnaBridge	172:65be27845400	557	*/
AnnaBridge	172:65be27845400	558	__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
AnnaBridge	172:65be27845400	559	{
AnnaBridge	172:65be27845400	560	CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
AnnaBridge	172:65be27845400	561	}
AnnaBridge	172:65be27845400	562
AnnaBridge	172:65be27845400	563	/**
AnnaBridge	172:65be27845400	564	* @brief Check if the VBAT and Temperature monitoring is enabled
AnnaBridge	172:65be27845400	565	* @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring
AnnaBridge	172:65be27845400	566	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	567	*/
AnnaBridge	172:65be27845400	568	__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
AnnaBridge	172:65be27845400	569	{
AnnaBridge	172:65be27845400	570	return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	571	}
AnnaBridge	172:65be27845400	572
AnnaBridge	172:65be27845400	573	/**
AnnaBridge	172:65be27845400	574	* @brief Configure the PWR supply
AnnaBridge	172:65be27845400	575	* @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
AnnaBridge	172:65be27845400	576	* @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
AnnaBridge	172:65be27845400	577	* @rmtoll CR3 SCUEN LL_PWR_ConfigSupply
AnnaBridge	172:65be27845400	578	* @param SupplySource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	579	* @arg @ref LL_PWR_LDO_SUPPLY
AnnaBridge	172:65be27845400	580	* @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
AnnaBridge	172:65be27845400	581	* @retval None
AnnaBridge	172:65be27845400	582	*/
AnnaBridge	172:65be27845400	583	__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
AnnaBridge	172:65be27845400	584	{
AnnaBridge	172:65be27845400	585	/* Set the power supply configuration */
AnnaBridge	172:65be27845400	586	MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN \| PWR_CR3_LDOEN \| PWR_CR3_BYPASS), SupplySource);
AnnaBridge	172:65be27845400	587	}
AnnaBridge	172:65be27845400	588
AnnaBridge	172:65be27845400	589	/**
AnnaBridge	172:65be27845400	590	* @brief Get the PWR supply
AnnaBridge	172:65be27845400	591	* @rmtoll CR3 BYPASS LL_PWR_GetSupply
AnnaBridge	172:65be27845400	592	* @rmtoll CR3 LDOEN LL_PWR_GetSupply
AnnaBridge	172:65be27845400	593	* @rmtoll CR3 SCUEN LL_PWR_GetSupply
AnnaBridge	172:65be27845400	594	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	595	* @arg @ref LL_PWR_LDO_SUPPLY
AnnaBridge	172:65be27845400	596	* @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
AnnaBridge	172:65be27845400	597	*/
AnnaBridge	172:65be27845400	598	__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
AnnaBridge	172:65be27845400	599	{
AnnaBridge	172:65be27845400	600	/* Get the power supply configuration */
AnnaBridge	172:65be27845400	601	return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN \| PWR_CR3_LDOEN \| PWR_CR3_BYPASS)));
AnnaBridge	172:65be27845400	602	}
AnnaBridge	172:65be27845400	603
AnnaBridge	172:65be27845400	604	/**
AnnaBridge	172:65be27845400	605	* @brief Enable battery charging
AnnaBridge	172:65be27845400	606	* @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging
AnnaBridge	172:65be27845400	607	* @retval None
AnnaBridge	172:65be27845400	608	*/
AnnaBridge	172:65be27845400	609	__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
AnnaBridge	172:65be27845400	610	{
AnnaBridge	172:65be27845400	611	SET_BIT(PWR->CR3, PWR_CR3_VBE);
AnnaBridge	172:65be27845400	612	}
AnnaBridge	172:65be27845400	613
AnnaBridge	172:65be27845400	614	/**
AnnaBridge	172:65be27845400	615	* @brief Disable battery charging
AnnaBridge	172:65be27845400	616	* @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging
AnnaBridge	172:65be27845400	617	* @retval None
AnnaBridge	172:65be27845400	618	*/
AnnaBridge	172:65be27845400	619	__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
AnnaBridge	172:65be27845400	620	{
AnnaBridge	172:65be27845400	621	CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
AnnaBridge	172:65be27845400	622	}
AnnaBridge	172:65be27845400	623
AnnaBridge	172:65be27845400	624	/**
AnnaBridge	172:65be27845400	625	* @brief Check if battery charging is enabled
AnnaBridge	172:65be27845400	626	* @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging
AnnaBridge	172:65be27845400	627	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	628	*/
AnnaBridge	172:65be27845400	629	__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
AnnaBridge	172:65be27845400	630	{
AnnaBridge	172:65be27845400	631	return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	632	}
AnnaBridge	172:65be27845400	633
AnnaBridge	172:65be27845400	634	/**
AnnaBridge	172:65be27845400	635	* @brief Set the Battery charge resistor impedance
AnnaBridge	172:65be27845400	636	* @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor
AnnaBridge	172:65be27845400	637	* @param Resistor This parameter can be one of the following values:
AnnaBridge	172:65be27845400	638	* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
AnnaBridge	172:65be27845400	639	* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
AnnaBridge	172:65be27845400	640	* @retval None
AnnaBridge	172:65be27845400	641	*/
AnnaBridge	172:65be27845400	642	__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
AnnaBridge	172:65be27845400	643	{
AnnaBridge	172:65be27845400	644	MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
AnnaBridge	172:65be27845400	645	}
AnnaBridge	172:65be27845400	646
AnnaBridge	172:65be27845400	647	/**
AnnaBridge	172:65be27845400	648	* @brief Get the Battery charge resistor impedance
AnnaBridge	172:65be27845400	649	* @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor
AnnaBridge	172:65be27845400	650	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	651	* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
AnnaBridge	172:65be27845400	652	* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
AnnaBridge	172:65be27845400	653	*/
AnnaBridge	172:65be27845400	654	__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
AnnaBridge	172:65be27845400	655	{
AnnaBridge	172:65be27845400	656	return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
AnnaBridge	172:65be27845400	657	}
AnnaBridge	172:65be27845400	658
AnnaBridge	172:65be27845400	659	/**
AnnaBridge	172:65be27845400	660	* @brief Enable the USB regulator
AnnaBridge	172:65be27845400	661	* @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg
AnnaBridge	172:65be27845400	662	* @retval None
AnnaBridge	172:65be27845400	663	*/
AnnaBridge	172:65be27845400	664	__STATIC_INLINE void LL_PWR_EnableUSBReg(void)
AnnaBridge	172:65be27845400	665	{
AnnaBridge	172:65be27845400	666	SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
AnnaBridge	172:65be27845400	667	}
AnnaBridge	172:65be27845400	668
AnnaBridge	172:65be27845400	669	/**
AnnaBridge	172:65be27845400	670	* @brief Disable the USB regulator
AnnaBridge	172:65be27845400	671	* @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg
AnnaBridge	172:65be27845400	672	* @retval None
AnnaBridge	172:65be27845400	673	*/
AnnaBridge	172:65be27845400	674	__STATIC_INLINE void LL_PWR_DisableUSBReg(void)
AnnaBridge	172:65be27845400	675	{
AnnaBridge	172:65be27845400	676	CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
AnnaBridge	172:65be27845400	677	}
AnnaBridge	172:65be27845400	678
AnnaBridge	172:65be27845400	679	/**
AnnaBridge	172:65be27845400	680	* @brief Check if the USB regulator is enabled
AnnaBridge	172:65be27845400	681	* @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg
AnnaBridge	172:65be27845400	682	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	683	*/
AnnaBridge	172:65be27845400	684	__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
AnnaBridge	172:65be27845400	685	{
AnnaBridge	172:65be27845400	686	return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	687	}
AnnaBridge	172:65be27845400	688
AnnaBridge	172:65be27845400	689	/**
AnnaBridge	172:65be27845400	690	* @brief Enable the USB voltage detector
AnnaBridge	172:65be27845400	691	* @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector
AnnaBridge	172:65be27845400	692	* @retval None
AnnaBridge	172:65be27845400	693	*/
AnnaBridge	172:65be27845400	694	__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
AnnaBridge	172:65be27845400	695	{
AnnaBridge	172:65be27845400	696	SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
AnnaBridge	172:65be27845400	697	}
AnnaBridge	172:65be27845400	698
AnnaBridge	172:65be27845400	699	/**
AnnaBridge	172:65be27845400	700	* @brief Disable the USB voltage detector
AnnaBridge	172:65be27845400	701	* @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector
AnnaBridge	172:65be27845400	702	* @retval None
AnnaBridge	172:65be27845400	703	*/
AnnaBridge	172:65be27845400	704	__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
AnnaBridge	172:65be27845400	705	{
AnnaBridge	172:65be27845400	706	CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
AnnaBridge	172:65be27845400	707	}
AnnaBridge	172:65be27845400	708
AnnaBridge	172:65be27845400	709	/**
AnnaBridge	172:65be27845400	710	* @brief Check if the USB voltage detector is enabled
AnnaBridge	172:65be27845400	711	* @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
AnnaBridge	172:65be27845400	712	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	713	*/
AnnaBridge	172:65be27845400	714	__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
AnnaBridge	172:65be27845400	715	{
AnnaBridge	172:65be27845400	716	return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	717	}
AnnaBridge	172:65be27845400	718
AnnaBridge	172:65be27845400	719	/**
AnnaBridge	172:65be27845400	720	* @brief Set the D1 domain Power Down mode when the CPU enters deepsleep
AnnaBridge	172:65be27845400	721	* @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode\n
AnnaBridge	172:65be27845400	722	* @param PDMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	723	* @arg @ref LL_PWR_CPU_MODE_D1STOP
AnnaBridge	172:65be27845400	724	* @arg @ref LL_PWR_CPU_MODE_D1STANDBY
AnnaBridge	172:65be27845400	725	* @retval None
AnnaBridge	172:65be27845400	726	*/
AnnaBridge	172:65be27845400	727	__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
AnnaBridge	172:65be27845400	728	{
AnnaBridge	172:65be27845400	729	MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
AnnaBridge	172:65be27845400	730	}
AnnaBridge	172:65be27845400	731
AnnaBridge	172:65be27845400	732	/**
AnnaBridge	172:65be27845400	733	* @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep
AnnaBridge	172:65be27845400	734	* @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode\n
AnnaBridge	172:65be27845400	735	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	736	* @arg @ref LL_PWR_CPU_MODE_D1STOP
AnnaBridge	172:65be27845400	737	* @arg @ref LL_PWR_CPU_MODE_D1STANDBY
AnnaBridge	172:65be27845400	738	*/
AnnaBridge	172:65be27845400	739	__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
AnnaBridge	172:65be27845400	740	{
AnnaBridge	172:65be27845400	741	return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
AnnaBridge	172:65be27845400	742	}
AnnaBridge	172:65be27845400	743
AnnaBridge	172:65be27845400	744	/**
AnnaBridge	172:65be27845400	745	* @brief Set the D2 domain Power Down mode when the CPU enters deepsleep
AnnaBridge	172:65be27845400	746	* @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode\n
AnnaBridge	172:65be27845400	747	* @param PDMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	748	* @arg @ref LL_PWR_CPU_MODE_D2STOP
AnnaBridge	172:65be27845400	749	* @arg @ref LL_PWR_CPU_MODE_D2STANDBY
AnnaBridge	172:65be27845400	750	* @retval None
AnnaBridge	172:65be27845400	751	*/
AnnaBridge	172:65be27845400	752	__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
AnnaBridge	172:65be27845400	753	{
AnnaBridge	172:65be27845400	754	MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
AnnaBridge	172:65be27845400	755	}
AnnaBridge	172:65be27845400	756
AnnaBridge	172:65be27845400	757	/**
AnnaBridge	172:65be27845400	758	* @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep
AnnaBridge	172:65be27845400	759	* @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode\n
AnnaBridge	172:65be27845400	760	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	761	* @arg @ref LL_PWR_CPU_MODE_D2STOP
AnnaBridge	172:65be27845400	762	* @arg @ref LL_PWR_CPU_MODE_D2STANDBY
AnnaBridge	172:65be27845400	763	*/
AnnaBridge	172:65be27845400	764	__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
AnnaBridge	172:65be27845400	765	{
AnnaBridge	172:65be27845400	766	return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
AnnaBridge	172:65be27845400	767	}
AnnaBridge	172:65be27845400	768
AnnaBridge	172:65be27845400	769	/**
AnnaBridge	172:65be27845400	770	* @brief Set the D3 domain Power Down mode when the CPU enters deepsleep
AnnaBridge	172:65be27845400	771	* @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode\n
AnnaBridge	172:65be27845400	772	* @param PDMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	773	* @arg @ref LL_PWR_CPU_MODE_D3STOP
AnnaBridge	172:65be27845400	774	* @arg @ref LL_PWR_CPU_MODE_D3STANDBY
AnnaBridge	172:65be27845400	775	* @retval None
AnnaBridge	172:65be27845400	776	*/
AnnaBridge	172:65be27845400	777	__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
AnnaBridge	172:65be27845400	778	{
AnnaBridge	172:65be27845400	779	MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
AnnaBridge	172:65be27845400	780	}
AnnaBridge	172:65be27845400	781
AnnaBridge	172:65be27845400	782	/**
AnnaBridge	172:65be27845400	783	* @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep
AnnaBridge	172:65be27845400	784	* @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode\n
AnnaBridge	172:65be27845400	785	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	786	* @arg @ref LL_PWR_CPU_MODE_D3STOP
AnnaBridge	172:65be27845400	787	* @arg @ref LL_PWR_CPU_MODE_D3STANDBY
AnnaBridge	172:65be27845400	788	*/
AnnaBridge	172:65be27845400	789	__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
AnnaBridge	172:65be27845400	790	{
AnnaBridge	172:65be27845400	791	return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
AnnaBridge	172:65be27845400	792	}
AnnaBridge	172:65be27845400	793
AnnaBridge	172:65be27845400	794	/**
AnnaBridge	172:65be27845400	795	* @brief D3 domain remains in Run mode regardless of CPU subsystem modes
AnnaBridge	172:65be27845400	796	* @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode\n
AnnaBridge	172:65be27845400	797	* @retval None
AnnaBridge	172:65be27845400	798	*/
AnnaBridge	172:65be27845400	799	__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
AnnaBridge	172:65be27845400	800	{
AnnaBridge	172:65be27845400	801	SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
AnnaBridge	172:65be27845400	802	}
AnnaBridge	172:65be27845400	803
AnnaBridge	172:65be27845400	804	/**
AnnaBridge	172:65be27845400	805	* @brief D3 domain follows CPU subsystem modes
AnnaBridge	172:65be27845400	806	* @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode\n
AnnaBridge	172:65be27845400	807	* @retval None
AnnaBridge	172:65be27845400	808	*/
AnnaBridge	172:65be27845400	809	__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
AnnaBridge	172:65be27845400	810	{
AnnaBridge	172:65be27845400	811	CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
AnnaBridge	172:65be27845400	812	}
AnnaBridge	172:65be27845400	813
AnnaBridge	172:65be27845400	814	/**
AnnaBridge	172:65be27845400	815	* @brief Check if D3 is kept in Run mode when CPU enters low power mode
AnnaBridge	172:65be27845400	816	* @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode\n
AnnaBridge	172:65be27845400	817	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	818	*/
AnnaBridge	172:65be27845400	819	__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
AnnaBridge	172:65be27845400	820	{
AnnaBridge	172:65be27845400	821	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	822	}
AnnaBridge	172:65be27845400	823
AnnaBridge	172:65be27845400	824	/**
AnnaBridge	172:65be27845400	825	* @brief Set the main internal Regulator output voltage
AnnaBridge	172:65be27845400	826	* @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling
AnnaBridge	172:65be27845400	827	* @param VoltageScaling This parameter can be one of the following values:
AnnaBridge	172:65be27845400	828	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
AnnaBridge	172:65be27845400	829	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
AnnaBridge	172:65be27845400	830	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
AnnaBridge	172:65be27845400	831	* @retval None
AnnaBridge	172:65be27845400	832	*/
AnnaBridge	172:65be27845400	833	__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
AnnaBridge	172:65be27845400	834	{
AnnaBridge	172:65be27845400	835	MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
AnnaBridge	172:65be27845400	836	}
AnnaBridge	172:65be27845400	837
AnnaBridge	172:65be27845400	838	/**
AnnaBridge	172:65be27845400	839	* @brief Get the main internal Regulator output voltage
AnnaBridge	172:65be27845400	840	* @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling
AnnaBridge	172:65be27845400	841	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	842	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
AnnaBridge	172:65be27845400	843	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
AnnaBridge	172:65be27845400	844	* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
AnnaBridge	172:65be27845400	845	*/
AnnaBridge	172:65be27845400	846	__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
AnnaBridge	172:65be27845400	847	{
AnnaBridge	172:65be27845400	848	return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
AnnaBridge	172:65be27845400	849	}
AnnaBridge	172:65be27845400	850
AnnaBridge	172:65be27845400	851	/**
AnnaBridge	172:65be27845400	852	* @brief Enable the WakeUp PINx functionality
AnnaBridge	172:65be27845400	853	* @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n
AnnaBridge	172:65be27845400	854	* WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n
AnnaBridge	172:65be27845400	855	* WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n
AnnaBridge	172:65be27845400	856	* WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n
AnnaBridge	172:65be27845400	857	* WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n
AnnaBridge	172:65be27845400	858	* WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin
AnnaBridge	172:65be27845400	859	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	860	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	861	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	862	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	863	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	864	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	865	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	866	* @retval None
AnnaBridge	172:65be27845400	867	*/
AnnaBridge	172:65be27845400	868	__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	869	{
AnnaBridge	172:65be27845400	870	SET_BIT(PWR->WKUPEPR, WakeUpPin);
AnnaBridge	172:65be27845400	871	}
AnnaBridge	172:65be27845400	872
AnnaBridge	172:65be27845400	873	/**
AnnaBridge	172:65be27845400	874	* @brief Disable the WakeUp PINx functionality
AnnaBridge	172:65be27845400	875	* @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n
AnnaBridge	172:65be27845400	876	* WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n
AnnaBridge	172:65be27845400	877	* WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n
AnnaBridge	172:65be27845400	878	* WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n
AnnaBridge	172:65be27845400	879	* WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n
AnnaBridge	172:65be27845400	880	* WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin
AnnaBridge	172:65be27845400	881	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	882	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	883	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	884	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	885	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	886	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	887	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	888	* @retval None
AnnaBridge	172:65be27845400	889	*/
AnnaBridge	172:65be27845400	890	__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	891	{
AnnaBridge	172:65be27845400	892	CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
AnnaBridge	172:65be27845400	893	}
AnnaBridge	172:65be27845400	894
AnnaBridge	172:65be27845400	895	/**
AnnaBridge	172:65be27845400	896	* @brief Check if the WakeUp PINx functionality is enabled
AnnaBridge	172:65be27845400	897	* @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	172:65be27845400	898	* WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	172:65be27845400	899	* WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	172:65be27845400	900	* WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	172:65be27845400	901	* WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n
AnnaBridge	172:65be27845400	902	* WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin
AnnaBridge	172:65be27845400	903	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	904	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	905	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	906	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	907	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	908	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	909	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	910	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	911	*/
AnnaBridge	172:65be27845400	912	__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	913	{
AnnaBridge	172:65be27845400	914	return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	915	}
AnnaBridge	172:65be27845400	916
AnnaBridge	172:65be27845400	917	/**
AnnaBridge	172:65be27845400	918	* @brief Set the Wake-Up pin polarity low for the event detection
AnnaBridge	172:65be27845400	919	* @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	920	* WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	921	* WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	922	* WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	923	* WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	924	* WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow
AnnaBridge	172:65be27845400	925	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	926	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	927	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	928	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	929	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	930	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	931	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	932	* @retval None
AnnaBridge	172:65be27845400	933	*/
AnnaBridge	172:65be27845400	934	__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	935	{
AnnaBridge	172:65be27845400	936	SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
AnnaBridge	172:65be27845400	937	}
AnnaBridge	172:65be27845400	938
AnnaBridge	172:65be27845400	939	/**
AnnaBridge	172:65be27845400	940	* @brief Set the Wake-Up pin polarity high for the event detection
AnnaBridge	172:65be27845400	941	* @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	172:65be27845400	942	* WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	172:65be27845400	943	* WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	172:65be27845400	944	* WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	172:65be27845400	945	* WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
AnnaBridge	172:65be27845400	946	* WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh
AnnaBridge	172:65be27845400	947	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	948	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	949	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	950	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	951	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	952	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	953	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	954	* @retval None
AnnaBridge	172:65be27845400	955	*/
AnnaBridge	172:65be27845400	956	__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	957	{
AnnaBridge	172:65be27845400	958	CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
AnnaBridge	172:65be27845400	959	}
AnnaBridge	172:65be27845400	960
AnnaBridge	172:65be27845400	961	/**
AnnaBridge	172:65be27845400	962	* @brief Get the Wake-Up pin polarity for the event detection
AnnaBridge	172:65be27845400	963	* @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	964	* WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	965	* WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	966	* WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	967	* WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n
AnnaBridge	172:65be27845400	968	* WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow
AnnaBridge	172:65be27845400	969	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	970	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	971	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	972	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	973	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	974	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	975	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	976	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	977	*/
AnnaBridge	172:65be27845400	978	__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	979	{
AnnaBridge	172:65be27845400	980	return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	981	}
AnnaBridge	172:65be27845400	982
AnnaBridge	172:65be27845400	983	/**
AnnaBridge	172:65be27845400	984	* @brief Set the Wake-Up pin Pull None
AnnaBridge	172:65be27845400	985	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	172:65be27845400	986	* WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	172:65be27845400	987	* WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	172:65be27845400	988	* WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	172:65be27845400	989	* WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
AnnaBridge	172:65be27845400	990	* WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone
AnnaBridge	172:65be27845400	991	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	992	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	993	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	994	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	995	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	996	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	997	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	998	* @retval None
AnnaBridge	172:65be27845400	999	*/
AnnaBridge	172:65be27845400	1000	__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	1001	{
AnnaBridge	172:65be27845400	1002	MODIFY_REG(PWR->WKUPEPR, \
AnnaBridge	172:65be27845400	1003	(PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
AnnaBridge	172:65be27845400	1004	(LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	172:65be27845400	1005	}
AnnaBridge	172:65be27845400	1006
AnnaBridge	172:65be27845400	1007	/**
AnnaBridge	172:65be27845400	1008	* @brief Set the Wake-Up pin Pull Up
AnnaBridge	172:65be27845400	1009	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	172:65be27845400	1010	* WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	172:65be27845400	1011	* WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	172:65be27845400	1012	* WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	172:65be27845400	1013	* WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
AnnaBridge	172:65be27845400	1014	* WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp
AnnaBridge	172:65be27845400	1015	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1016	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	1017	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	1018	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	1019	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	1020	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	1021	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	1022	* @retval None
AnnaBridge	172:65be27845400	1023	*/
AnnaBridge	172:65be27845400	1024	__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	1025	{
AnnaBridge	172:65be27845400	1026	MODIFY_REG(PWR->WKUPEPR, \
AnnaBridge	172:65be27845400	1027	(PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
AnnaBridge	172:65be27845400	1028	(LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	172:65be27845400	1029	}
AnnaBridge	172:65be27845400	1030
AnnaBridge	172:65be27845400	1031	/**
AnnaBridge	172:65be27845400	1032	* @brief Set the Wake-Up pin Pull Down
AnnaBridge	172:65be27845400	1033	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	172:65be27845400	1034	* WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	172:65be27845400	1035	* WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	172:65be27845400	1036	* WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	172:65be27845400	1037	* WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
AnnaBridge	172:65be27845400	1038	* WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown
AnnaBridge	172:65be27845400	1039	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1040	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	1041	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	1042	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	1043	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	1044	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	1045	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	1046	* @retval None
AnnaBridge	172:65be27845400	1047	*/
AnnaBridge	172:65be27845400	1048	__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	1049	{
AnnaBridge	172:65be27845400	1050	MODIFY_REG(PWR->WKUPEPR, \
AnnaBridge	172:65be27845400	1051	(PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
AnnaBridge	172:65be27845400	1052	(LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	172:65be27845400	1053	}
AnnaBridge	172:65be27845400	1054
AnnaBridge	172:65be27845400	1055	/**
AnnaBridge	172:65be27845400	1056	* @brief Get the Wake-Up pin pull
AnnaBridge	172:65be27845400	1057	* @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	172:65be27845400	1058	* WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	172:65be27845400	1059	* WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	172:65be27845400	1060	* WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	172:65be27845400	1061	* WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n
AnnaBridge	172:65be27845400	1062	* WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull
AnnaBridge	172:65be27845400	1063	* @param WakeUpPin This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1064	* @arg @ref LL_PWR_WAKEUP_PIN1
AnnaBridge	172:65be27845400	1065	* @arg @ref LL_PWR_WAKEUP_PIN2
AnnaBridge	172:65be27845400	1066	* @arg @ref LL_PWR_WAKEUP_PIN3
AnnaBridge	172:65be27845400	1067	* @arg @ref LL_PWR_WAKEUP_PIN4
AnnaBridge	172:65be27845400	1068	* @arg @ref LL_PWR_WAKEUP_PIN5
AnnaBridge	172:65be27845400	1069	* @arg @ref LL_PWR_WAKEUP_PIN6
AnnaBridge	172:65be27845400	1070	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1071	* @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
AnnaBridge	172:65be27845400	1072	* @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
AnnaBridge	172:65be27845400	1073	* @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
AnnaBridge	172:65be27845400	1074	*/
AnnaBridge	172:65be27845400	1075	__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
AnnaBridge	172:65be27845400	1076	{
AnnaBridge	172:65be27845400	1077	register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
AnnaBridge	172:65be27845400	1078
AnnaBridge	172:65be27845400	1079	return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
AnnaBridge	172:65be27845400	1080	}
AnnaBridge	172:65be27845400	1081
AnnaBridge	172:65be27845400	1082	/**
AnnaBridge	172:65be27845400	1083	* @}
AnnaBridge	172:65be27845400	1084	*/
AnnaBridge	172:65be27845400	1085
AnnaBridge	172:65be27845400	1086	/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	172:65be27845400	1087	* @{
AnnaBridge	172:65be27845400	1088	*/
AnnaBridge	172:65be27845400	1089
AnnaBridge	172:65be27845400	1090	/**
AnnaBridge	172:65be27845400	1091	* @brief Indicate whether VDD voltage is below the selected PVD threshold
AnnaBridge	172:65be27845400	1092	* @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
AnnaBridge	172:65be27845400	1093	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1094	*/
AnnaBridge	172:65be27845400	1095	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
AnnaBridge	172:65be27845400	1096	{
AnnaBridge	172:65be27845400	1097	return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1098	}
AnnaBridge	172:65be27845400	1099
AnnaBridge	172:65be27845400	1100	/**
AnnaBridge	172:65be27845400	1101	* @brief Indicate whether the voltage level is ready for current actual used VOS
AnnaBridge	172:65be27845400	1102	* @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
AnnaBridge	172:65be27845400	1103	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1104	*/
AnnaBridge	172:65be27845400	1105	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
AnnaBridge	172:65be27845400	1106	{
AnnaBridge	172:65be27845400	1107	return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1108	}
AnnaBridge	172:65be27845400	1109
AnnaBridge	172:65be27845400	1110	/**
AnnaBridge	172:65be27845400	1111	* @brief Indicate whether VDDA voltage is below the selected AVD threshold
AnnaBridge	172:65be27845400	1112	* @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO
AnnaBridge	172:65be27845400	1113	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1114	*/
AnnaBridge	172:65be27845400	1115	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
AnnaBridge	172:65be27845400	1116	{
AnnaBridge	172:65be27845400	1117	return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1118	}
AnnaBridge	172:65be27845400	1119
AnnaBridge	172:65be27845400	1120	/**
AnnaBridge	172:65be27845400	1121	* @brief Get Backup Regulator ready Flag
AnnaBridge	172:65be27845400	1122	* @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR
AnnaBridge	172:65be27845400	1123	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1124	*/
AnnaBridge	172:65be27845400	1125	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
AnnaBridge	172:65be27845400	1126	{
AnnaBridge	172:65be27845400	1127	return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1128	}
AnnaBridge	172:65be27845400	1129
AnnaBridge	172:65be27845400	1130	/**
AnnaBridge	172:65be27845400	1131	* @brief Indicate whether the VBAT level is above or below low threshold
AnnaBridge	172:65be27845400	1132	* @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL
AnnaBridge	172:65be27845400	1133	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1134	*/
AnnaBridge	172:65be27845400	1135	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
AnnaBridge	172:65be27845400	1136	{
AnnaBridge	172:65be27845400	1137	return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1138	}
AnnaBridge	172:65be27845400	1139
AnnaBridge	172:65be27845400	1140	/**
AnnaBridge	172:65be27845400	1141	* @brief Indicate whether the VBAT level is above or below high threshold
AnnaBridge	172:65be27845400	1142	* @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH
AnnaBridge	172:65be27845400	1143	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1144	*/
AnnaBridge	172:65be27845400	1145	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
AnnaBridge	172:65be27845400	1146	{
AnnaBridge	172:65be27845400	1147	return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1148	}
AnnaBridge	172:65be27845400	1149
AnnaBridge	172:65be27845400	1150	/**
AnnaBridge	172:65be27845400	1151	* @brief Indicate whether the CPU temperature level is above or below low threshold
AnnaBridge	172:65be27845400	1152	* @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL
AnnaBridge	172:65be27845400	1153	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1154	*/
AnnaBridge	172:65be27845400	1155	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
AnnaBridge	172:65be27845400	1156	{
AnnaBridge	172:65be27845400	1157	return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1158	}
AnnaBridge	172:65be27845400	1159
AnnaBridge	172:65be27845400	1160	/**
AnnaBridge	172:65be27845400	1161	* @brief Indicate whether the CPU temperature level is above or below high threshold
AnnaBridge	172:65be27845400	1162	* @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH
AnnaBridge	172:65be27845400	1163	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1164	*/
AnnaBridge	172:65be27845400	1165	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
AnnaBridge	172:65be27845400	1166	{
AnnaBridge	172:65be27845400	1167	return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1168	}
AnnaBridge	172:65be27845400	1169
AnnaBridge	172:65be27845400	1170	/**
AnnaBridge	172:65be27845400	1171	* @brief Indicate whether the USB supply is ready or not
AnnaBridge	172:65be27845400	1172	* @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB
AnnaBridge	172:65be27845400	1173	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1174	*/
AnnaBridge	172:65be27845400	1175	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
AnnaBridge	172:65be27845400	1176	{
AnnaBridge	172:65be27845400	1177	return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1178	}
AnnaBridge	172:65be27845400	1179
AnnaBridge	172:65be27845400	1180	/**
AnnaBridge	172:65be27845400	1181	* @brief Get CPU System Stop Flag
AnnaBridge	172:65be27845400	1182	* @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP
AnnaBridge	172:65be27845400	1183	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1184	*/
AnnaBridge	172:65be27845400	1185	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
AnnaBridge	172:65be27845400	1186	{
AnnaBridge	172:65be27845400	1187	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1188	}
AnnaBridge	172:65be27845400	1189
AnnaBridge	172:65be27845400	1190	/**
AnnaBridge	172:65be27845400	1191	* @brief Get CPU System Standby Flag
AnnaBridge	172:65be27845400	1192	* @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB
AnnaBridge	172:65be27845400	1193	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1194	*/
AnnaBridge	172:65be27845400	1195	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
AnnaBridge	172:65be27845400	1196	{
AnnaBridge	172:65be27845400	1197	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1198	}
AnnaBridge	172:65be27845400	1199
AnnaBridge	172:65be27845400	1200	/**
AnnaBridge	172:65be27845400	1201	* @brief Get CPU D1 Domain Standby Flag
AnnaBridge	172:65be27845400	1202	* @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1
AnnaBridge	172:65be27845400	1203	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1204	*/
AnnaBridge	172:65be27845400	1205	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
AnnaBridge	172:65be27845400	1206	{
AnnaBridge	172:65be27845400	1207	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1208	}
AnnaBridge	172:65be27845400	1209
AnnaBridge	172:65be27845400	1210	/**
AnnaBridge	172:65be27845400	1211	* @brief Get CPU D2 Domain Standby Flag
AnnaBridge	172:65be27845400	1212	* @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2
AnnaBridge	172:65be27845400	1213	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1214	*/
AnnaBridge	172:65be27845400	1215	__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
AnnaBridge	172:65be27845400	1216	{
AnnaBridge	172:65be27845400	1217	return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1218	}
AnnaBridge	172:65be27845400	1219
AnnaBridge	172:65be27845400	1220	/**
AnnaBridge	172:65be27845400	1221	* @brief Indicate whether the Regulator is ready in the selected voltage range
AnnaBridge	172:65be27845400	1222	* or if its output voltage is still changing to the required voltage level
AnnaBridge	172:65be27845400	1223	* @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS
AnnaBridge	172:65be27845400	1224	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1225	*/
AnnaBridge	172:65be27845400	1226	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
AnnaBridge	172:65be27845400	1227	{
AnnaBridge	172:65be27845400	1228	return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1229	}
AnnaBridge	172:65be27845400	1230
AnnaBridge	172:65be27845400	1231	/**
AnnaBridge	172:65be27845400	1232	* @brief Get Wake-up Flag 6
AnnaBridge	172:65be27845400	1233	* @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6
AnnaBridge	172:65be27845400	1234	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1235	*/
AnnaBridge	172:65be27845400	1236	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
AnnaBridge	172:65be27845400	1237	{
AnnaBridge	172:65be27845400	1238	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1239	}
AnnaBridge	172:65be27845400	1240
AnnaBridge	172:65be27845400	1241	/**
AnnaBridge	172:65be27845400	1242	* @brief Get Wake-up Flag 5
AnnaBridge	172:65be27845400	1243	* @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
AnnaBridge	172:65be27845400	1244	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1245	*/
AnnaBridge	172:65be27845400	1246	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
AnnaBridge	172:65be27845400	1247	{
AnnaBridge	172:65be27845400	1248	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1249	}
AnnaBridge	172:65be27845400	1250
AnnaBridge	172:65be27845400	1251	/**
AnnaBridge	172:65be27845400	1252	* @brief Get Wake-up Flag 4
AnnaBridge	172:65be27845400	1253	* @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
AnnaBridge	172:65be27845400	1254	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1255	*/
AnnaBridge	172:65be27845400	1256	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
AnnaBridge	172:65be27845400	1257	{
AnnaBridge	172:65be27845400	1258	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1259	}
AnnaBridge	172:65be27845400	1260
AnnaBridge	172:65be27845400	1261	/**
AnnaBridge	172:65be27845400	1262	* @brief Get Wake-up Flag 3
AnnaBridge	172:65be27845400	1263	* @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
AnnaBridge	172:65be27845400	1264	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1265	*/
AnnaBridge	172:65be27845400	1266	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
AnnaBridge	172:65be27845400	1267	{
AnnaBridge	172:65be27845400	1268	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1269	}
AnnaBridge	172:65be27845400	1270
AnnaBridge	172:65be27845400	1271	/**
AnnaBridge	172:65be27845400	1272	* @brief Get Wake-up Flag 2
AnnaBridge	172:65be27845400	1273	* @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
AnnaBridge	172:65be27845400	1274	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1275	*/
AnnaBridge	172:65be27845400	1276	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
AnnaBridge	172:65be27845400	1277	{
AnnaBridge	172:65be27845400	1278	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1279	}
AnnaBridge	172:65be27845400	1280
AnnaBridge	172:65be27845400	1281	/**
AnnaBridge	172:65be27845400	1282	* @brief Get Wake-up Flag 1
AnnaBridge	172:65be27845400	1283	* @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
AnnaBridge	172:65be27845400	1284	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1285	*/
AnnaBridge	172:65be27845400	1286	__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
AnnaBridge	172:65be27845400	1287	{
AnnaBridge	172:65be27845400	1288	return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1289	}
AnnaBridge	172:65be27845400	1290
AnnaBridge	172:65be27845400	1291	/**
AnnaBridge	172:65be27845400	1292	* @brief Clear CPU STANDBY, STOP and HOLD flags
AnnaBridge	172:65be27845400	1293	* @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU
AnnaBridge	172:65be27845400	1294	* @retval None
AnnaBridge	172:65be27845400	1295	*/
AnnaBridge	172:65be27845400	1296	__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
AnnaBridge	172:65be27845400	1297	{
AnnaBridge	172:65be27845400	1298	SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
AnnaBridge	172:65be27845400	1299	}
AnnaBridge	172:65be27845400	1300
AnnaBridge	172:65be27845400	1301	/**
AnnaBridge	172:65be27845400	1302	* @brief Clear Wake-up Flag 6
AnnaBridge	172:65be27845400	1303	* @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6
AnnaBridge	172:65be27845400	1304	* @retval None
AnnaBridge	172:65be27845400	1305	*/
AnnaBridge	172:65be27845400	1306	__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
AnnaBridge	172:65be27845400	1307	{
AnnaBridge	172:65be27845400	1308	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
AnnaBridge	172:65be27845400	1309	}
AnnaBridge	172:65be27845400	1310
AnnaBridge	172:65be27845400	1311	/**
AnnaBridge	172:65be27845400	1312	* @brief Clear Wake-up Flag 5
AnnaBridge	172:65be27845400	1313	* @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
AnnaBridge	172:65be27845400	1314	* @retval None
AnnaBridge	172:65be27845400	1315	*/
AnnaBridge	172:65be27845400	1316	__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
AnnaBridge	172:65be27845400	1317	{
AnnaBridge	172:65be27845400	1318	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
AnnaBridge	172:65be27845400	1319	}
AnnaBridge	172:65be27845400	1320
AnnaBridge	172:65be27845400	1321	/**
AnnaBridge	172:65be27845400	1322	* @brief Clear Wake-up Flag 4
AnnaBridge	172:65be27845400	1323	* @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
AnnaBridge	172:65be27845400	1324	* @retval None
AnnaBridge	172:65be27845400	1325	*/
AnnaBridge	172:65be27845400	1326	__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
AnnaBridge	172:65be27845400	1327	{
AnnaBridge	172:65be27845400	1328	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
AnnaBridge	172:65be27845400	1329	}
AnnaBridge	172:65be27845400	1330
AnnaBridge	172:65be27845400	1331	/**
AnnaBridge	172:65be27845400	1332	* @brief Clear Wake-up Flag 3
AnnaBridge	172:65be27845400	1333	* @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
AnnaBridge	172:65be27845400	1334	* @retval None
AnnaBridge	172:65be27845400	1335	*/
AnnaBridge	172:65be27845400	1336	__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
AnnaBridge	172:65be27845400	1337	{
AnnaBridge	172:65be27845400	1338	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
AnnaBridge	172:65be27845400	1339	}
AnnaBridge	172:65be27845400	1340
AnnaBridge	172:65be27845400	1341	/**
AnnaBridge	172:65be27845400	1342	* @brief Clear Wake-up Flag 2
AnnaBridge	172:65be27845400	1343	* @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
AnnaBridge	172:65be27845400	1344	* @retval None
AnnaBridge	172:65be27845400	1345	*/
AnnaBridge	172:65be27845400	1346	__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
AnnaBridge	172:65be27845400	1347	{
AnnaBridge	172:65be27845400	1348	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
AnnaBridge	172:65be27845400	1349	}
AnnaBridge	172:65be27845400	1350
AnnaBridge	172:65be27845400	1351	/**
AnnaBridge	172:65be27845400	1352	* @brief Clear Wake-up Flag 1
AnnaBridge	172:65be27845400	1353	* @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
AnnaBridge	172:65be27845400	1354	* @retval None
AnnaBridge	172:65be27845400	1355	*/
AnnaBridge	172:65be27845400	1356	__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
AnnaBridge	172:65be27845400	1357	{
AnnaBridge	172:65be27845400	1358	WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
AnnaBridge	172:65be27845400	1359	}
AnnaBridge	172:65be27845400	1360
AnnaBridge	172:65be27845400	1361	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	1362	/** @defgroup PWR_LL_EF_Init De-initialization function
AnnaBridge	172:65be27845400	1363	* @{
AnnaBridge	172:65be27845400	1364	*/
AnnaBridge	172:65be27845400	1365	ErrorStatus LL_PWR_DeInit(void);
AnnaBridge	172:65be27845400	1366	/**
AnnaBridge	172:65be27845400	1367	* @}
AnnaBridge	172:65be27845400	1368	*/
AnnaBridge	172:65be27845400	1369	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	1370
AnnaBridge	172:65be27845400	1371
AnnaBridge	172:65be27845400	1372	/**
AnnaBridge	172:65be27845400	1373	* @}
AnnaBridge	172:65be27845400	1374	*/
AnnaBridge	172:65be27845400	1375
AnnaBridge	172:65be27845400	1376	/**
AnnaBridge	172:65be27845400	1377	* @}
AnnaBridge	172:65be27845400	1378	*/
AnnaBridge	172:65be27845400	1379
AnnaBridge	172:65be27845400	1380	/**
AnnaBridge	172:65be27845400	1381	* @}
AnnaBridge	172:65be27845400	1382	*/
AnnaBridge	172:65be27845400	1383
AnnaBridge	172:65be27845400	1384	#endif /* defined(PWR) */
AnnaBridge	172:65be27845400	1385
AnnaBridge	172:65be27845400	1386	/**
AnnaBridge	172:65be27845400	1387	* @}
AnnaBridge	172:65be27845400	1388	*/
AnnaBridge	172:65be27845400	1389
AnnaBridge	172:65be27845400	1390	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1391	}
AnnaBridge	172:65be27845400	1392	#endif
AnnaBridge	172:65be27845400	1393
AnnaBridge	172:65be27845400	1394	#endif /* STM32H7xx_LL_PWR_H */
AnnaBridge	172:65be27845400	1395
AnnaBridge	172:65be27845400	1396	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/