mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_H743ZI/TOOLCHAIN_GCC_ARM/stm32h7xx_ll_cortex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32h7xx_ll_cortex.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of CORTEX LL module.
AnnaBridge 172:65be27845400 6 @verbatim
AnnaBridge 172:65be27845400 7 ==============================================================================
AnnaBridge 172:65be27845400 8 ##### How to use this driver #####
AnnaBridge 172:65be27845400 9 ==============================================================================
AnnaBridge 172:65be27845400 10 [..]
AnnaBridge 172:65be27845400 11 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 172:65be27845400 12 used by user:
AnnaBridge 172:65be27845400 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 172:65be27845400 14 functions
AnnaBridge 172:65be27845400 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 172:65be27845400 16 (+) MPU API to configure and enable regions
AnnaBridge 172:65be27845400 17 (+) API to access to MCU info (CPUID register)
AnnaBridge 172:65be27845400 18 (+) API to enable fault handler (SHCSR accesses)
AnnaBridge 172:65be27845400 19
AnnaBridge 172:65be27845400 20 @endverbatim
AnnaBridge 172:65be27845400 21 ******************************************************************************
AnnaBridge 172:65be27845400 22 * @attention
AnnaBridge 172:65be27845400 23 *
AnnaBridge 172:65be27845400 24 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge 172:65be27845400 25 * All rights reserved.</center></h2>
AnnaBridge 172:65be27845400 26 *
AnnaBridge 172:65be27845400 27 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 172:65be27845400 28 * the "License"; You may not use this file except in compliance with the
AnnaBridge 172:65be27845400 29 * License. You may obtain a copy of the License at:
AnnaBridge 172:65be27845400 30 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 172:65be27845400 31 *
AnnaBridge 172:65be27845400 32 ******************************************************************************
AnnaBridge 172:65be27845400 33 */
AnnaBridge 172:65be27845400 34
AnnaBridge 172:65be27845400 35 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 36 #ifndef STM32H7xx_LL_CORTEX_H
AnnaBridge 172:65be27845400 37 #define STM32H7xx_LL_CORTEX_H
AnnaBridge 172:65be27845400 38
AnnaBridge 172:65be27845400 39 #ifdef __cplusplus
AnnaBridge 172:65be27845400 40 extern "C" {
AnnaBridge 172:65be27845400 41 #endif
AnnaBridge 172:65be27845400 42
AnnaBridge 172:65be27845400 43 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 44 #include "stm32h7xx.h"
AnnaBridge 172:65be27845400 45
AnnaBridge 172:65be27845400 46 /** @addtogroup STM32H7xx_LL_Driver
AnnaBridge 172:65be27845400 47 * @{
AnnaBridge 172:65be27845400 48 */
AnnaBridge 172:65be27845400 49
AnnaBridge 172:65be27845400 50 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 172:65be27845400 51 * @{
AnnaBridge 172:65be27845400 52 */
AnnaBridge 172:65be27845400 53
AnnaBridge 172:65be27845400 54 /* Private types -------------------------------------------------------------*/
AnnaBridge 172:65be27845400 55 /* Private variables ---------------------------------------------------------*/
AnnaBridge 172:65be27845400 56
AnnaBridge 172:65be27845400 57 /* Private constants ---------------------------------------------------------*/
AnnaBridge 172:65be27845400 58
AnnaBridge 172:65be27845400 59 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 60
AnnaBridge 172:65be27845400 61 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 62 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 63 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 172:65be27845400 64 * @{
AnnaBridge 172:65be27845400 65 */
AnnaBridge 172:65be27845400 66
AnnaBridge 172:65be27845400 67 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 172:65be27845400 68 * @{
AnnaBridge 172:65be27845400 69 */
AnnaBridge 172:65be27845400 70 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 172:65be27845400 71 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 172:65be27845400 72 /**
AnnaBridge 172:65be27845400 73 * @}
AnnaBridge 172:65be27845400 74 */
AnnaBridge 172:65be27845400 75
AnnaBridge 172:65be27845400 76 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
AnnaBridge 172:65be27845400 77 * @{
AnnaBridge 172:65be27845400 78 */
AnnaBridge 172:65be27845400 79 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
AnnaBridge 172:65be27845400 80 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
AnnaBridge 172:65be27845400 81 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
AnnaBridge 172:65be27845400 82 /**
AnnaBridge 172:65be27845400 83 * @}
AnnaBridge 172:65be27845400 84 */
AnnaBridge 172:65be27845400 85
AnnaBridge 172:65be27845400 86 #if __MPU_PRESENT
AnnaBridge 172:65be27845400 87
AnnaBridge 172:65be27845400 88 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 172:65be27845400 89 * @{
AnnaBridge 172:65be27845400 90 */
AnnaBridge 172:65be27845400 91 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */
AnnaBridge 172:65be27845400 92 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 172:65be27845400 93 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 172:65be27845400 94 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 172:65be27845400 95 /**
AnnaBridge 172:65be27845400 96 * @}
AnnaBridge 172:65be27845400 97 */
AnnaBridge 172:65be27845400 98
AnnaBridge 172:65be27845400 99 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 172:65be27845400 100 * @{
AnnaBridge 172:65be27845400 101 */
AnnaBridge 172:65be27845400 102 #define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */
AnnaBridge 172:65be27845400 103 #define LL_MPU_REGION_NUMBER1 0x01UL /*!< REGION Number 1 */
AnnaBridge 172:65be27845400 104 #define LL_MPU_REGION_NUMBER2 0x02UL /*!< REGION Number 2 */
AnnaBridge 172:65be27845400 105 #define LL_MPU_REGION_NUMBER3 0x03UL /*!< REGION Number 3 */
AnnaBridge 172:65be27845400 106 #define LL_MPU_REGION_NUMBER4 0x04UL /*!< REGION Number 4 */
AnnaBridge 172:65be27845400 107 #define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */
AnnaBridge 172:65be27845400 108 #define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */
AnnaBridge 172:65be27845400 109 #define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */
AnnaBridge 172:65be27845400 110 #define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */
AnnaBridge 172:65be27845400 111 #define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */
AnnaBridge 172:65be27845400 112 #define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */
AnnaBridge 172:65be27845400 113 #define LL_MPU_REGION_NUMBER11 0x0BUL /*!< REGION Number 11 */
AnnaBridge 172:65be27845400 114 #define LL_MPU_REGION_NUMBER12 0x0CUL /*!< REGION Number 12 */
AnnaBridge 172:65be27845400 115 #define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */
AnnaBridge 172:65be27845400 116 #define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */
AnnaBridge 172:65be27845400 117 #define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */
AnnaBridge 172:65be27845400 118 /**
AnnaBridge 172:65be27845400 119 * @}
AnnaBridge 172:65be27845400 120 */
AnnaBridge 172:65be27845400 121
AnnaBridge 172:65be27845400 122 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 172:65be27845400 123 * @{
AnnaBridge 172:65be27845400 124 */
AnnaBridge 172:65be27845400 125 #define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 172:65be27845400 126 #define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 172:65be27845400 127 #define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 172:65be27845400 128 #define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 172:65be27845400 129 #define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 172:65be27845400 130 #define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 131 #define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 132 #define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 133 #define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 134 #define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 135 #define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 136 #define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 137 #define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 138 #define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 139 #define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 172:65be27845400 140 #define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 141 #define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 142 #define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 143 #define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 144 #define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 145 #define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 146 #define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 147 #define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 148 #define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 149 #define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 172:65be27845400 150 #define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 172:65be27845400 151 #define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 172:65be27845400 152 #define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
AnnaBridge 172:65be27845400 153 /**
AnnaBridge 172:65be27845400 154 * @}
AnnaBridge 172:65be27845400 155 */
AnnaBridge 172:65be27845400 156
AnnaBridge 172:65be27845400 157 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 172:65be27845400 158 * @{
AnnaBridge 172:65be27845400 159 */
AnnaBridge 172:65be27845400 160 #define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 172:65be27845400 161 #define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 172:65be27845400 162 #define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 172:65be27845400 163 #define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 172:65be27845400 164 #define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 172:65be27845400 165 #define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
AnnaBridge 172:65be27845400 166 /**
AnnaBridge 172:65be27845400 167 * @}
AnnaBridge 172:65be27845400 168 */
AnnaBridge 172:65be27845400 169
AnnaBridge 172:65be27845400 170 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 172:65be27845400 171 * @{
AnnaBridge 172:65be27845400 172 */
AnnaBridge 172:65be27845400 173 #define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 172:65be27845400 174 #define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 172:65be27845400 175 #define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 172:65be27845400 176 #define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
AnnaBridge 172:65be27845400 177 /**
AnnaBridge 172:65be27845400 178 * @}
AnnaBridge 172:65be27845400 179 */
AnnaBridge 172:65be27845400 180
AnnaBridge 172:65be27845400 181 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 172:65be27845400 182 * @{
AnnaBridge 172:65be27845400 183 */
AnnaBridge 172:65be27845400 184 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */
AnnaBridge 172:65be27845400 185 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 172:65be27845400 186 /**
AnnaBridge 172:65be27845400 187 * @}
AnnaBridge 172:65be27845400 188 */
AnnaBridge 172:65be27845400 189
AnnaBridge 172:65be27845400 190 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 172:65be27845400 191 * @{
AnnaBridge 172:65be27845400 192 */
AnnaBridge 172:65be27845400 193 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 172:65be27845400 194 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL /*!< Not Shareable memory attribute */
AnnaBridge 172:65be27845400 195 /**
AnnaBridge 172:65be27845400 196 * @}
AnnaBridge 172:65be27845400 197 */
AnnaBridge 172:65be27845400 198
AnnaBridge 172:65be27845400 199 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 172:65be27845400 200 * @{
AnnaBridge 172:65be27845400 201 */
AnnaBridge 172:65be27845400 202 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 172:65be27845400 203 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL /*!< Not Cacheable memory attribute */
AnnaBridge 172:65be27845400 204 /**
AnnaBridge 172:65be27845400 205 * @}
AnnaBridge 172:65be27845400 206 */
AnnaBridge 172:65be27845400 207
AnnaBridge 172:65be27845400 208 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 172:65be27845400 209 * @{
AnnaBridge 172:65be27845400 210 */
AnnaBridge 172:65be27845400 211 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 172:65be27845400 212 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL /*!< Not Bufferable memory attribute */
AnnaBridge 172:65be27845400 213 /**
AnnaBridge 172:65be27845400 214 * @}
AnnaBridge 172:65be27845400 215 */
AnnaBridge 172:65be27845400 216 #endif /* __MPU_PRESENT */
AnnaBridge 172:65be27845400 217 /**
AnnaBridge 172:65be27845400 218 * @}
AnnaBridge 172:65be27845400 219 */
AnnaBridge 172:65be27845400 220
AnnaBridge 172:65be27845400 221 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 222
AnnaBridge 172:65be27845400 223 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 224 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 172:65be27845400 225 * @{
AnnaBridge 172:65be27845400 226 */
AnnaBridge 172:65be27845400 227
AnnaBridge 172:65be27845400 228 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 172:65be27845400 229 * @{
AnnaBridge 172:65be27845400 230 */
AnnaBridge 172:65be27845400 231
AnnaBridge 172:65be27845400 232 /**
AnnaBridge 172:65be27845400 233 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 172:65be27845400 234 * @note It can be used in timeout function on application side.
AnnaBridge 172:65be27845400 235 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 172:65be27845400 236 * @retval State of bit (1 or 0).
AnnaBridge 172:65be27845400 237 */
AnnaBridge 172:65be27845400 238 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 172:65be27845400 239 {
AnnaBridge 172:65be27845400 240 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
AnnaBridge 172:65be27845400 241 }
AnnaBridge 172:65be27845400 242
AnnaBridge 172:65be27845400 243 /**
AnnaBridge 172:65be27845400 244 * @brief Configures the SysTick clock source
AnnaBridge 172:65be27845400 245 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 172:65be27845400 246 * @param Source This parameter can be one of the following values:
AnnaBridge 172:65be27845400 247 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 172:65be27845400 248 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 172:65be27845400 249 * @retval None
AnnaBridge 172:65be27845400 250 */
AnnaBridge 172:65be27845400 251 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 172:65be27845400 252 {
AnnaBridge 172:65be27845400 253 MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
AnnaBridge 172:65be27845400 254 }
AnnaBridge 172:65be27845400 255
AnnaBridge 172:65be27845400 256 /**
AnnaBridge 172:65be27845400 257 * @brief Get the SysTick clock source
AnnaBridge 172:65be27845400 258 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 172:65be27845400 259 * @retval Returned value can be one of the following values:
AnnaBridge 172:65be27845400 260 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 172:65be27845400 261 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 172:65be27845400 262 */
AnnaBridge 172:65be27845400 263 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 172:65be27845400 264 {
AnnaBridge 172:65be27845400 265 return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
AnnaBridge 172:65be27845400 266 }
AnnaBridge 172:65be27845400 267
AnnaBridge 172:65be27845400 268 /**
AnnaBridge 172:65be27845400 269 * @brief Enable SysTick exception request
AnnaBridge 172:65be27845400 270 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 172:65be27845400 271 * @retval None
AnnaBridge 172:65be27845400 272 */
AnnaBridge 172:65be27845400 273 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 172:65be27845400 274 {
AnnaBridge 172:65be27845400 275 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 172:65be27845400 276 }
AnnaBridge 172:65be27845400 277
AnnaBridge 172:65be27845400 278 /**
AnnaBridge 172:65be27845400 279 * @brief Disable SysTick exception request
AnnaBridge 172:65be27845400 280 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 172:65be27845400 281 * @retval None
AnnaBridge 172:65be27845400 282 */
AnnaBridge 172:65be27845400 283 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 172:65be27845400 284 {
AnnaBridge 172:65be27845400 285 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 172:65be27845400 286 }
AnnaBridge 172:65be27845400 287
AnnaBridge 172:65be27845400 288 /**
AnnaBridge 172:65be27845400 289 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 172:65be27845400 290 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 172:65be27845400 291 * @retval State of bit (1 or 0).
AnnaBridge 172:65be27845400 292 */
AnnaBridge 172:65be27845400 293 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 172:65be27845400 294 {
AnnaBridge 172:65be27845400 295 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
AnnaBridge 172:65be27845400 296 }
AnnaBridge 172:65be27845400 297
AnnaBridge 172:65be27845400 298 /**
AnnaBridge 172:65be27845400 299 * @}
AnnaBridge 172:65be27845400 300 */
AnnaBridge 172:65be27845400 301
AnnaBridge 172:65be27845400 302 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 172:65be27845400 303 * @{
AnnaBridge 172:65be27845400 304 */
AnnaBridge 172:65be27845400 305
AnnaBridge 172:65be27845400 306 /**
AnnaBridge 172:65be27845400 307 * @brief Processor uses sleep as its low power mode
AnnaBridge 172:65be27845400 308 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 172:65be27845400 309 * @retval None
AnnaBridge 172:65be27845400 310 */
AnnaBridge 172:65be27845400 311 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 172:65be27845400 312 {
AnnaBridge 172:65be27845400 313 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 314 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
AnnaBridge 172:65be27845400 315 }
AnnaBridge 172:65be27845400 316
AnnaBridge 172:65be27845400 317 /**
AnnaBridge 172:65be27845400 318 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 172:65be27845400 319 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 172:65be27845400 320 * @retval None
AnnaBridge 172:65be27845400 321 */
AnnaBridge 172:65be27845400 322 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 172:65be27845400 323 {
AnnaBridge 172:65be27845400 324 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 325 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
AnnaBridge 172:65be27845400 326 }
AnnaBridge 172:65be27845400 327
AnnaBridge 172:65be27845400 328 /**
AnnaBridge 172:65be27845400 329 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 172:65be27845400 330 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 172:65be27845400 331 * empty main application.
AnnaBridge 172:65be27845400 332 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 172:65be27845400 333 * @retval None
AnnaBridge 172:65be27845400 334 */
AnnaBridge 172:65be27845400 335 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 172:65be27845400 336 {
AnnaBridge 172:65be27845400 337 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 338 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
AnnaBridge 172:65be27845400 339 }
AnnaBridge 172:65be27845400 340
AnnaBridge 172:65be27845400 341 /**
AnnaBridge 172:65be27845400 342 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 172:65be27845400 343 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 172:65be27845400 344 * @retval None
AnnaBridge 172:65be27845400 345 */
AnnaBridge 172:65be27845400 346 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 172:65be27845400 347 {
AnnaBridge 172:65be27845400 348 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 349 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
AnnaBridge 172:65be27845400 350 }
AnnaBridge 172:65be27845400 351
AnnaBridge 172:65be27845400 352 /**
AnnaBridge 172:65be27845400 353 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 172:65be27845400 354 * processor.
AnnaBridge 172:65be27845400 355 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 172:65be27845400 356 * @retval None
AnnaBridge 172:65be27845400 357 */
AnnaBridge 172:65be27845400 358 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 172:65be27845400 359 {
AnnaBridge 172:65be27845400 360 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 361 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
AnnaBridge 172:65be27845400 362 }
AnnaBridge 172:65be27845400 363
AnnaBridge 172:65be27845400 364 /**
AnnaBridge 172:65be27845400 365 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 172:65be27845400 366 * excluded
AnnaBridge 172:65be27845400 367 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 172:65be27845400 368 * @retval None
AnnaBridge 172:65be27845400 369 */
AnnaBridge 172:65be27845400 370 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 172:65be27845400 371 {
AnnaBridge 172:65be27845400 372 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 172:65be27845400 373 CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
AnnaBridge 172:65be27845400 374 }
AnnaBridge 172:65be27845400 375
AnnaBridge 172:65be27845400 376 /**
AnnaBridge 172:65be27845400 377 * @}
AnnaBridge 172:65be27845400 378 */
AnnaBridge 172:65be27845400 379
AnnaBridge 172:65be27845400 380 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
AnnaBridge 172:65be27845400 381 * @{
AnnaBridge 172:65be27845400 382 */
AnnaBridge 172:65be27845400 383
AnnaBridge 172:65be27845400 384 /**
AnnaBridge 172:65be27845400 385 * @brief Enable a fault in System handler control register (SHCSR)
AnnaBridge 172:65be27845400 386 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
AnnaBridge 172:65be27845400 387 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 172:65be27845400 388 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 172:65be27845400 389 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 172:65be27845400 390 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 172:65be27845400 391 * @retval None
AnnaBridge 172:65be27845400 392 */
AnnaBridge 172:65be27845400 393 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
AnnaBridge 172:65be27845400 394 {
AnnaBridge 172:65be27845400 395 /* Enable the system handler fault */
AnnaBridge 172:65be27845400 396 SET_BIT(SCB->SHCSR, Fault);
AnnaBridge 172:65be27845400 397 }
AnnaBridge 172:65be27845400 398
AnnaBridge 172:65be27845400 399 /**
AnnaBridge 172:65be27845400 400 * @brief Disable a fault in System handler control register (SHCSR)
AnnaBridge 172:65be27845400 401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
AnnaBridge 172:65be27845400 402 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 172:65be27845400 403 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 172:65be27845400 404 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 172:65be27845400 405 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 172:65be27845400 406 * @retval None
AnnaBridge 172:65be27845400 407 */
AnnaBridge 172:65be27845400 408 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
AnnaBridge 172:65be27845400 409 {
AnnaBridge 172:65be27845400 410 /* Disable the system handler fault */
AnnaBridge 172:65be27845400 411 CLEAR_BIT(SCB->SHCSR, Fault);
AnnaBridge 172:65be27845400 412 }
AnnaBridge 172:65be27845400 413
AnnaBridge 172:65be27845400 414 /**
AnnaBridge 172:65be27845400 415 * @}
AnnaBridge 172:65be27845400 416 */
AnnaBridge 172:65be27845400 417
AnnaBridge 172:65be27845400 418 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 172:65be27845400 419 * @{
AnnaBridge 172:65be27845400 420 */
AnnaBridge 172:65be27845400 421
AnnaBridge 172:65be27845400 422 /**
AnnaBridge 172:65be27845400 423 * @brief Get Implementer code
AnnaBridge 172:65be27845400 424 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 172:65be27845400 425 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 172:65be27845400 426 */
AnnaBridge 172:65be27845400 427 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 172:65be27845400 428 {
AnnaBridge 172:65be27845400 429 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 172:65be27845400 430 }
AnnaBridge 172:65be27845400 431
AnnaBridge 172:65be27845400 432 /**
AnnaBridge 172:65be27845400 433 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 172:65be27845400 434 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 172:65be27845400 435 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 172:65be27845400 436 */
AnnaBridge 172:65be27845400 437 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 172:65be27845400 438 {
AnnaBridge 172:65be27845400 439 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 172:65be27845400 440 }
AnnaBridge 172:65be27845400 441
AnnaBridge 172:65be27845400 442 /**
AnnaBridge 172:65be27845400 443 * @brief Get Constant number
AnnaBridge 172:65be27845400 444 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
AnnaBridge 172:65be27845400 445 * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
AnnaBridge 172:65be27845400 446 */
AnnaBridge 172:65be27845400 447 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
AnnaBridge 172:65be27845400 448 {
AnnaBridge 172:65be27845400 449 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 172:65be27845400 450 }
AnnaBridge 172:65be27845400 451
AnnaBridge 172:65be27845400 452 /**
AnnaBridge 172:65be27845400 453 * @brief Get Part number
AnnaBridge 172:65be27845400 454 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 172:65be27845400 455 * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
AnnaBridge 172:65be27845400 456 */
AnnaBridge 172:65be27845400 457 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 172:65be27845400 458 {
AnnaBridge 172:65be27845400 459 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 172:65be27845400 460 }
AnnaBridge 172:65be27845400 461
AnnaBridge 172:65be27845400 462 /**
AnnaBridge 172:65be27845400 463 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 172:65be27845400 464 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 172:65be27845400 465 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 172:65be27845400 466 */
AnnaBridge 172:65be27845400 467 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 172:65be27845400 468 {
AnnaBridge 172:65be27845400 469 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 172:65be27845400 470 }
AnnaBridge 172:65be27845400 471
AnnaBridge 172:65be27845400 472 /**
AnnaBridge 172:65be27845400 473 * @}
AnnaBridge 172:65be27845400 474 */
AnnaBridge 172:65be27845400 475
AnnaBridge 172:65be27845400 476 #if __MPU_PRESENT
AnnaBridge 172:65be27845400 477 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 172:65be27845400 478 * @{
AnnaBridge 172:65be27845400 479 */
AnnaBridge 172:65be27845400 480
AnnaBridge 172:65be27845400 481 /**
AnnaBridge 172:65be27845400 482 * @brief Enable MPU with input options
AnnaBridge 172:65be27845400 483 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 172:65be27845400 484 * @param Options This parameter can be one of the following values:
AnnaBridge 172:65be27845400 485 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 172:65be27845400 486 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 172:65be27845400 487 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 172:65be27845400 488 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 172:65be27845400 489 * @retval None
AnnaBridge 172:65be27845400 490 */
AnnaBridge 172:65be27845400 491 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 172:65be27845400 492 {
AnnaBridge 172:65be27845400 493 /* Enable the MPU*/
AnnaBridge 172:65be27845400 494 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 172:65be27845400 495 /* Ensure MPU settings take effects */
AnnaBridge 172:65be27845400 496 __DSB();
AnnaBridge 172:65be27845400 497 /* Sequence instruction fetches using update settings */
AnnaBridge 172:65be27845400 498 __ISB();
AnnaBridge 172:65be27845400 499 }
AnnaBridge 172:65be27845400 500
AnnaBridge 172:65be27845400 501 /**
AnnaBridge 172:65be27845400 502 * @brief Disable MPU
AnnaBridge 172:65be27845400 503 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 172:65be27845400 504 * @retval None
AnnaBridge 172:65be27845400 505 */
AnnaBridge 172:65be27845400 506 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 172:65be27845400 507 {
AnnaBridge 172:65be27845400 508 /* Make sure outstanding transfers are done */
AnnaBridge 172:65be27845400 509 __DMB();
AnnaBridge 172:65be27845400 510 /* Disable MPU*/
AnnaBridge 172:65be27845400 511 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 172:65be27845400 512 }
AnnaBridge 172:65be27845400 513
AnnaBridge 172:65be27845400 514 /**
AnnaBridge 172:65be27845400 515 * @brief Check if MPU is enabled or not
AnnaBridge 172:65be27845400 516 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 172:65be27845400 517 * @retval State of bit (1 or 0).
AnnaBridge 172:65be27845400 518 */
AnnaBridge 172:65be27845400 519 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 172:65be27845400 520 {
AnnaBridge 172:65be27845400 521 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
AnnaBridge 172:65be27845400 522 }
AnnaBridge 172:65be27845400 523
AnnaBridge 172:65be27845400 524 /**
AnnaBridge 172:65be27845400 525 * @brief Enable a MPU region
AnnaBridge 172:65be27845400 526 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 172:65be27845400 527 * @param Region This parameter can be one of the following values:
AnnaBridge 172:65be27845400 528 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 172:65be27845400 529 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 172:65be27845400 530 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 172:65be27845400 531 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 172:65be27845400 532 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 172:65be27845400 533 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 172:65be27845400 534 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 172:65be27845400 535 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 172:65be27845400 536 * @arg @ref LL_MPU_REGION_NUMBER8
AnnaBridge 172:65be27845400 537 * @arg @ref LL_MPU_REGION_NUMBER9
AnnaBridge 172:65be27845400 538 * @arg @ref LL_MPU_REGION_NUMBER10
AnnaBridge 172:65be27845400 539 * @arg @ref LL_MPU_REGION_NUMBER11
AnnaBridge 172:65be27845400 540 * @arg @ref LL_MPU_REGION_NUMBER12
AnnaBridge 172:65be27845400 541 * @arg @ref LL_MPU_REGION_NUMBER13
AnnaBridge 172:65be27845400 542 * @arg @ref LL_MPU_REGION_NUMBER14
AnnaBridge 172:65be27845400 543 * @arg @ref LL_MPU_REGION_NUMBER15
AnnaBridge 172:65be27845400 544 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
AnnaBridge 172:65be27845400 545 * @retval None
AnnaBridge 172:65be27845400 546 */
AnnaBridge 172:65be27845400 547 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 172:65be27845400 548 {
AnnaBridge 172:65be27845400 549 /* Set Region number */
AnnaBridge 172:65be27845400 550 WRITE_REG(MPU->RNR, Region);
AnnaBridge 172:65be27845400 551 /* Enable the MPU region */
AnnaBridge 172:65be27845400 552 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 172:65be27845400 553 }
AnnaBridge 172:65be27845400 554
AnnaBridge 172:65be27845400 555 /**
AnnaBridge 172:65be27845400 556 * @brief Configure and enable a region
AnnaBridge 172:65be27845400 557 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 558 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 559 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 560 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 561 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 562 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 563 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 564 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 172:65be27845400 565 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 172:65be27845400 566 * @param Region This parameter can be one of the following values:
AnnaBridge 172:65be27845400 567 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 172:65be27845400 568 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 172:65be27845400 569 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 172:65be27845400 570 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 172:65be27845400 571 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 172:65be27845400 572 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 172:65be27845400 573 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 172:65be27845400 574 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 172:65be27845400 575 * @arg @ref LL_MPU_REGION_NUMBER8
AnnaBridge 172:65be27845400 576 * @arg @ref LL_MPU_REGION_NUMBER9
AnnaBridge 172:65be27845400 577 * @arg @ref LL_MPU_REGION_NUMBER10
AnnaBridge 172:65be27845400 578 * @arg @ref LL_MPU_REGION_NUMBER11
AnnaBridge 172:65be27845400 579 * @arg @ref LL_MPU_REGION_NUMBER12
AnnaBridge 172:65be27845400 580 * @arg @ref LL_MPU_REGION_NUMBER13
AnnaBridge 172:65be27845400 581 * @arg @ref LL_MPU_REGION_NUMBER14
AnnaBridge 172:65be27845400 582 * @arg @ref LL_MPU_REGION_NUMBER15
AnnaBridge 172:65be27845400 583 * @param Address Value of region base address
AnnaBridge 172:65be27845400 584 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 172:65be27845400 585 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 172:65be27845400 586 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 172:65be27845400 587 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 172:65be27845400 588 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 172:65be27845400 589 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 172:65be27845400 590 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 172:65be27845400 591 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 172:65be27845400 592 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 172:65be27845400 593 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 172:65be27845400 594 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 172:65be27845400 595 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 172:65be27845400 596 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 172:65be27845400 597 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 172:65be27845400 598 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 172:65be27845400 599 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
AnnaBridge 172:65be27845400 600 * @retval None
AnnaBridge 172:65be27845400 601 */
AnnaBridge 172:65be27845400 602 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 172:65be27845400 603 {
AnnaBridge 172:65be27845400 604 /* Set Region number */
AnnaBridge 172:65be27845400 605 WRITE_REG(MPU->RNR, Region);
AnnaBridge 172:65be27845400 606 /* Set base address */
AnnaBridge 172:65be27845400 607 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 172:65be27845400 608 /* Configure MPU */
AnnaBridge 172:65be27845400 609 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
AnnaBridge 172:65be27845400 610 }
AnnaBridge 172:65be27845400 611
AnnaBridge 172:65be27845400 612 /**
AnnaBridge 172:65be27845400 613 * @brief Disable a region
AnnaBridge 172:65be27845400 614 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 172:65be27845400 615 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 172:65be27845400 616 * @param Region This parameter can be one of the following values:
AnnaBridge 172:65be27845400 617 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 172:65be27845400 618 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 172:65be27845400 619 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 172:65be27845400 620 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 172:65be27845400 621 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 172:65be27845400 622 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 172:65be27845400 623 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 172:65be27845400 624 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 172:65be27845400 625 * @arg @ref LL_MPU_REGION_NUMBER8
AnnaBridge 172:65be27845400 626 * @arg @ref LL_MPU_REGION_NUMBER9
AnnaBridge 172:65be27845400 627 * @arg @ref LL_MPU_REGION_NUMBER10
AnnaBridge 172:65be27845400 628 * @arg @ref LL_MPU_REGION_NUMBER11
AnnaBridge 172:65be27845400 629 * @arg @ref LL_MPU_REGION_NUMBER12
AnnaBridge 172:65be27845400 630 * @arg @ref LL_MPU_REGION_NUMBER13
AnnaBridge 172:65be27845400 631 * @arg @ref LL_MPU_REGION_NUMBER14
AnnaBridge 172:65be27845400 632 * @arg @ref LL_MPU_REGION_NUMBER15
AnnaBridge 172:65be27845400 633 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
AnnaBridge 172:65be27845400 634 * @retval None
AnnaBridge 172:65be27845400 635 */
AnnaBridge 172:65be27845400 636 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 172:65be27845400 637 {
AnnaBridge 172:65be27845400 638 /* Set Region number */
AnnaBridge 172:65be27845400 639 WRITE_REG(MPU->RNR, Region);
AnnaBridge 172:65be27845400 640 /* Disable the MPU region */
AnnaBridge 172:65be27845400 641 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 172:65be27845400 642 }
AnnaBridge 172:65be27845400 643
AnnaBridge 172:65be27845400 644 /**
AnnaBridge 172:65be27845400 645 * @}
AnnaBridge 172:65be27845400 646 */
AnnaBridge 172:65be27845400 647
AnnaBridge 172:65be27845400 648 #endif /* __MPU_PRESENT */
AnnaBridge 172:65be27845400 649 /**
AnnaBridge 172:65be27845400 650 * @}
AnnaBridge 172:65be27845400 651 */
AnnaBridge 172:65be27845400 652
AnnaBridge 172:65be27845400 653 /**
AnnaBridge 172:65be27845400 654 * @}
AnnaBridge 172:65be27845400 655 */
AnnaBridge 172:65be27845400 656
AnnaBridge 172:65be27845400 657 /**
AnnaBridge 172:65be27845400 658 * @}
AnnaBridge 172:65be27845400 659 */
AnnaBridge 172:65be27845400 660
AnnaBridge 172:65be27845400 661 #ifdef __cplusplus
AnnaBridge 172:65be27845400 662 }
AnnaBridge 172:65be27845400 663 #endif
AnnaBridge 172:65be27845400 664
AnnaBridge 172:65be27845400 665 #endif /* STM32H7xx_LL_CORTEX_H */
AnnaBridge 172:65be27845400 666
AnnaBridge 172:65be27845400 667 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/