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TARGET_NUCLEO_H743ZI/TOOLCHAIN_GCC_ARM/stm32h7xx_hal_qspi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32h7xx_hal_qspi.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of QSPI HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
AnnaBridge 172:65be27845400 10 * All rights reserved.</center></h2>
AnnaBridge 172:65be27845400 11 *
AnnaBridge 172:65be27845400 12 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 172:65be27845400 13 * the "License"; You may not use this file except in compliance with the
AnnaBridge 172:65be27845400 14 * License. You may obtain a copy of the License at:
AnnaBridge 172:65be27845400 15 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 172:65be27845400 16 *
AnnaBridge 172:65be27845400 17 ******************************************************************************
AnnaBridge 172:65be27845400 18 */
AnnaBridge 172:65be27845400 19
AnnaBridge 172:65be27845400 20 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 21 #ifndef STM32H7xx_HAL_QSPI_H
AnnaBridge 172:65be27845400 22 #define STM32H7xx_HAL_QSPI_H
AnnaBridge 172:65be27845400 23
AnnaBridge 172:65be27845400 24 #ifdef __cplusplus
AnnaBridge 172:65be27845400 25 extern "C" {
AnnaBridge 172:65be27845400 26 #endif
AnnaBridge 172:65be27845400 27
AnnaBridge 172:65be27845400 28 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 29 #include "stm32h7xx_hal_def.h"
AnnaBridge 172:65be27845400 30
AnnaBridge 172:65be27845400 31 /** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge 172:65be27845400 32 * @{
AnnaBridge 172:65be27845400 33 */
AnnaBridge 172:65be27845400 34
AnnaBridge 172:65be27845400 35 /** @addtogroup QSPI
AnnaBridge 172:65be27845400 36 * @{
AnnaBridge 172:65be27845400 37 */
AnnaBridge 172:65be27845400 38
AnnaBridge 172:65be27845400 39 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 40 /** @defgroup QSPI_Exported_Types QSPI Exported Types
AnnaBridge 172:65be27845400 41 * @{
AnnaBridge 172:65be27845400 42 */
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 /**
AnnaBridge 172:65be27845400 45 * @brief QSPI Init structure definition
AnnaBridge 172:65be27845400 46 */
AnnaBridge 172:65be27845400 47
AnnaBridge 172:65be27845400 48 typedef struct
AnnaBridge 172:65be27845400 49 {
AnnaBridge 172:65be27845400 50 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
AnnaBridge 172:65be27845400 51 This parameter can be a number between 0 and 255 */
AnnaBridge 172:65be27845400 52
AnnaBridge 172:65be27845400 53 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
AnnaBridge 172:65be27845400 54 This parameter can be a value between 1 and 32 */
AnnaBridge 172:65be27845400 55
AnnaBridge 172:65be27845400 56 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
AnnaBridge 172:65be27845400 57 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
AnnaBridge 172:65be27845400 58 This parameter can be a value of @ref QSPI_SampleShifting */
AnnaBridge 172:65be27845400 59
AnnaBridge 172:65be27845400 60 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
AnnaBridge 172:65be27845400 61 required to address the flash memory. The flash capacity can be up to 4GB
AnnaBridge 172:65be27845400 62 (addressed using 32 bits) in indirect mode, but the addressable space in
AnnaBridge 172:65be27845400 63 memory-mapped mode is limited to 256MB
AnnaBridge 172:65be27845400 64 This parameter can be a number between 0 and 31 */
AnnaBridge 172:65be27845400 65
AnnaBridge 172:65be27845400 66 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
AnnaBridge 172:65be27845400 67 of clock cycles which the chip select must remain high between commands.
AnnaBridge 172:65be27845400 68 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
AnnaBridge 172:65be27845400 69
AnnaBridge 172:65be27845400 70 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
AnnaBridge 172:65be27845400 71 This parameter can be a value of @ref QSPI_ClockMode */
AnnaBridge 172:65be27845400 72
AnnaBridge 172:65be27845400 73 uint32_t FlashID; /* Specifies the Flash which will be used,
AnnaBridge 172:65be27845400 74 This parameter can be a value of @ref QSPI_Flash_Select */
AnnaBridge 172:65be27845400 75
AnnaBridge 172:65be27845400 76 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
AnnaBridge 172:65be27845400 77 This parameter can be a value of @ref QSPI_DualFlash_Mode */
AnnaBridge 172:65be27845400 78 }QSPI_InitTypeDef;
AnnaBridge 172:65be27845400 79
AnnaBridge 172:65be27845400 80 /**
AnnaBridge 172:65be27845400 81 * @brief HAL QSPI State structures definition
AnnaBridge 172:65be27845400 82 */
AnnaBridge 172:65be27845400 83 typedef enum
AnnaBridge 172:65be27845400 84 {
AnnaBridge 172:65be27845400 85 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
AnnaBridge 172:65be27845400 86 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
AnnaBridge 172:65be27845400 87 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
AnnaBridge 172:65be27845400 88 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
AnnaBridge 172:65be27845400 89 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
AnnaBridge 172:65be27845400 90 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
AnnaBridge 172:65be27845400 91 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
AnnaBridge 172:65be27845400 92 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
AnnaBridge 172:65be27845400 93 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
AnnaBridge 172:65be27845400 94 }HAL_QSPI_StateTypeDef;
AnnaBridge 172:65be27845400 95
AnnaBridge 172:65be27845400 96 /**
AnnaBridge 172:65be27845400 97 * @brief QSPI Handle Structure definition
AnnaBridge 172:65be27845400 98 */
AnnaBridge 172:65be27845400 99 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 100 typedef struct __QSPI_HandleTypeDef
AnnaBridge 172:65be27845400 101 #else
AnnaBridge 172:65be27845400 102 typedef struct
AnnaBridge 172:65be27845400 103 #endif/* USE_HAL_QSPI_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 104 {
AnnaBridge 172:65be27845400 105 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
AnnaBridge 172:65be27845400 106 QSPI_InitTypeDef Init; /* QSPI communication parameters */
AnnaBridge 172:65be27845400 107 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
AnnaBridge 172:65be27845400 108 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
AnnaBridge 172:65be27845400 109 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
AnnaBridge 172:65be27845400 110 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
AnnaBridge 172:65be27845400 111 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
AnnaBridge 172:65be27845400 112 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
AnnaBridge 172:65be27845400 113 MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
AnnaBridge 172:65be27845400 114 __IO HAL_LockTypeDef Lock; /* Locking object */
AnnaBridge 172:65be27845400 115 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
AnnaBridge 172:65be27845400 116 __IO uint32_t ErrorCode; /* QSPI Error code */
AnnaBridge 172:65be27845400 117 uint32_t Timeout; /* Timeout for the QSPI memory access */
AnnaBridge 172:65be27845400 118 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 119 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 120 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 121 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 122 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 123 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 124 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 125 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 126 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 127
AnnaBridge 172:65be27845400 128 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 129 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 130 #endif
AnnaBridge 172:65be27845400 131 }QSPI_HandleTypeDef;
AnnaBridge 172:65be27845400 132
AnnaBridge 172:65be27845400 133 /**
AnnaBridge 172:65be27845400 134 * @brief QSPI Command structure definition
AnnaBridge 172:65be27845400 135 */
AnnaBridge 172:65be27845400 136 typedef struct
AnnaBridge 172:65be27845400 137 {
AnnaBridge 172:65be27845400 138 uint32_t Instruction; /* Specifies the Instruction to be sent
AnnaBridge 172:65be27845400 139 This parameter can be a value (8-bit) between 0x00 and 0xFF */
AnnaBridge 172:65be27845400 140 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
AnnaBridge 172:65be27845400 141 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 142 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
AnnaBridge 172:65be27845400 143 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 144 uint32_t AddressSize; /* Specifies the Address Size
AnnaBridge 172:65be27845400 145 This parameter can be a value of @ref QSPI_AddressSize */
AnnaBridge 172:65be27845400 146 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
AnnaBridge 172:65be27845400 147 This parameter can be a value of @ref QSPI_AlternateBytesSize */
AnnaBridge 172:65be27845400 148 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
AnnaBridge 172:65be27845400 149 This parameter can be a number between 0 and 31 */
AnnaBridge 172:65be27845400 150 uint32_t InstructionMode; /* Specifies the Instruction Mode
AnnaBridge 172:65be27845400 151 This parameter can be a value of @ref QSPI_InstructionMode */
AnnaBridge 172:65be27845400 152 uint32_t AddressMode; /* Specifies the Address Mode
AnnaBridge 172:65be27845400 153 This parameter can be a value of @ref QSPI_AddressMode */
AnnaBridge 172:65be27845400 154 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
AnnaBridge 172:65be27845400 155 This parameter can be a value of @ref QSPI_AlternateBytesMode */
AnnaBridge 172:65be27845400 156 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
AnnaBridge 172:65be27845400 157 This parameter can be a value of @ref QSPI_DataMode */
AnnaBridge 172:65be27845400 158 uint32_t NbData; /* Specifies the number of data to transfer.
AnnaBridge 172:65be27845400 159 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
AnnaBridge 172:65be27845400 160 until end of memory)*/
AnnaBridge 172:65be27845400 161 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
AnnaBridge 172:65be27845400 162 This parameter can be a value of @ref QSPI_DdrMode */
AnnaBridge 172:65be27845400 163 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
AnnaBridge 172:65be27845400 164 system clock in DDR mode.
AnnaBridge 172:65be27845400 165 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
AnnaBridge 172:65be27845400 166 uint32_t SIOOMode; /* Specifies the send instruction only once mode
AnnaBridge 172:65be27845400 167 This parameter can be a value of @ref QSPI_SIOOMode */
AnnaBridge 172:65be27845400 168 }QSPI_CommandTypeDef;
AnnaBridge 172:65be27845400 169
AnnaBridge 172:65be27845400 170 /**
AnnaBridge 172:65be27845400 171 * @brief QSPI Auto Polling mode configuration structure definition
AnnaBridge 172:65be27845400 172 */
AnnaBridge 172:65be27845400 173 typedef struct
AnnaBridge 172:65be27845400 174 {
AnnaBridge 172:65be27845400 175 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
AnnaBridge 172:65be27845400 176 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 177 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
AnnaBridge 172:65be27845400 178 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 179 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
AnnaBridge 172:65be27845400 180 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 172:65be27845400 181 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
AnnaBridge 172:65be27845400 182 This parameter can be any value between 1 and 4 */
AnnaBridge 172:65be27845400 183 uint32_t MatchMode; /* Specifies the method used for determining a match.
AnnaBridge 172:65be27845400 184 This parameter can be a value of @ref QSPI_MatchMode */
AnnaBridge 172:65be27845400 185 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
AnnaBridge 172:65be27845400 186 This parameter can be a value of @ref QSPI_AutomaticStop */
AnnaBridge 172:65be27845400 187 }QSPI_AutoPollingTypeDef;
AnnaBridge 172:65be27845400 188
AnnaBridge 172:65be27845400 189 /**
AnnaBridge 172:65be27845400 190 * @brief QSPI Memory Mapped mode configuration structure definition
AnnaBridge 172:65be27845400 191 */
AnnaBridge 172:65be27845400 192 typedef struct
AnnaBridge 172:65be27845400 193 {
AnnaBridge 172:65be27845400 194 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
AnnaBridge 172:65be27845400 195 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 172:65be27845400 196 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
AnnaBridge 172:65be27845400 197 This parameter can be a value of @ref QSPI_TimeOutActivation */
AnnaBridge 172:65be27845400 198 }QSPI_MemoryMappedTypeDef;
AnnaBridge 172:65be27845400 199
AnnaBridge 172:65be27845400 200 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 201 /**
AnnaBridge 172:65be27845400 202 * @brief HAL QSPI Callback ID enumeration definition
AnnaBridge 172:65be27845400 203 */
AnnaBridge 172:65be27845400 204 typedef enum
AnnaBridge 172:65be27845400 205 {
AnnaBridge 172:65be27845400 206 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
AnnaBridge 172:65be27845400 207 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
AnnaBridge 172:65be27845400 208 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
AnnaBridge 172:65be27845400 209 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
AnnaBridge 172:65be27845400 210 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
AnnaBridge 172:65be27845400 211 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
AnnaBridge 172:65be27845400 212 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
AnnaBridge 172:65be27845400 213 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
AnnaBridge 172:65be27845400 214
AnnaBridge 172:65be27845400 215 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
AnnaBridge 172:65be27845400 216 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
AnnaBridge 172:65be27845400 217 }HAL_QSPI_CallbackIDTypeDef;
AnnaBridge 172:65be27845400 218
AnnaBridge 172:65be27845400 219 /**
AnnaBridge 172:65be27845400 220 * @brief HAL QSPI Callback pointer definition
AnnaBridge 172:65be27845400 221 */
AnnaBridge 172:65be27845400 222 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 223 #endif
AnnaBridge 172:65be27845400 224 /**
AnnaBridge 172:65be27845400 225 * @}
AnnaBridge 172:65be27845400 226 */
AnnaBridge 172:65be27845400 227
AnnaBridge 172:65be27845400 228 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 229 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
AnnaBridge 172:65be27845400 230 * @{
AnnaBridge 172:65be27845400 231 */
AnnaBridge 172:65be27845400 232
AnnaBridge 172:65be27845400 233 /** @defgroup QSPI_ErrorCode QSPI Error Code
AnnaBridge 172:65be27845400 234 * @{
AnnaBridge 172:65be27845400 235 */
AnnaBridge 172:65be27845400 236 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
AnnaBridge 172:65be27845400 237 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
AnnaBridge 172:65be27845400 238 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
AnnaBridge 172:65be27845400 239 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
AnnaBridge 172:65be27845400 240 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
AnnaBridge 172:65be27845400 241 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 242 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
AnnaBridge 172:65be27845400 243 #endif
AnnaBridge 172:65be27845400 244 /**
AnnaBridge 172:65be27845400 245 * @}
AnnaBridge 172:65be27845400 246 */
AnnaBridge 172:65be27845400 247
AnnaBridge 172:65be27845400 248 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
AnnaBridge 172:65be27845400 249 * @{
AnnaBridge 172:65be27845400 250 */
AnnaBridge 172:65be27845400 251 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
AnnaBridge 172:65be27845400 252 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
AnnaBridge 172:65be27845400 253 /**
AnnaBridge 172:65be27845400 254 * @}
AnnaBridge 172:65be27845400 255 */
AnnaBridge 172:65be27845400 256
AnnaBridge 172:65be27845400 257 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
AnnaBridge 172:65be27845400 258 * @{
AnnaBridge 172:65be27845400 259 */
AnnaBridge 172:65be27845400 260 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
AnnaBridge 172:65be27845400 261 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
AnnaBridge 172:65be27845400 262 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
AnnaBridge 172:65be27845400 263 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
AnnaBridge 172:65be27845400 264 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
AnnaBridge 172:65be27845400 265 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
AnnaBridge 172:65be27845400 266 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
AnnaBridge 172:65be27845400 267 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
AnnaBridge 172:65be27845400 268 /**
AnnaBridge 172:65be27845400 269 * @}
AnnaBridge 172:65be27845400 270 */
AnnaBridge 172:65be27845400 271
AnnaBridge 172:65be27845400 272 /** @defgroup QSPI_ClockMode QSPI Clock Mode
AnnaBridge 172:65be27845400 273 * @{
AnnaBridge 172:65be27845400 274 */
AnnaBridge 172:65be27845400 275 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
AnnaBridge 172:65be27845400 276 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
AnnaBridge 172:65be27845400 277 /**
AnnaBridge 172:65be27845400 278 * @}
AnnaBridge 172:65be27845400 279 */
AnnaBridge 172:65be27845400 280
AnnaBridge 172:65be27845400 281 /** @defgroup QSPI_Flash_Select QSPI Flash Select
AnnaBridge 172:65be27845400 282 * @{
AnnaBridge 172:65be27845400 283 */
AnnaBridge 172:65be27845400 284 #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/
AnnaBridge 172:65be27845400 285 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
AnnaBridge 172:65be27845400 286 /**
AnnaBridge 172:65be27845400 287 * @}
AnnaBridge 172:65be27845400 288 */
AnnaBridge 172:65be27845400 289
AnnaBridge 172:65be27845400 290 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
AnnaBridge 172:65be27845400 291 * @{
AnnaBridge 172:65be27845400 292 */
AnnaBridge 172:65be27845400 293 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
AnnaBridge 172:65be27845400 294 #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/
AnnaBridge 172:65be27845400 295 /**
AnnaBridge 172:65be27845400 296 * @}
AnnaBridge 172:65be27845400 297 */
AnnaBridge 172:65be27845400 298
AnnaBridge 172:65be27845400 299 /** @defgroup QSPI_AddressSize QSPI Address Size
AnnaBridge 172:65be27845400 300 * @{
AnnaBridge 172:65be27845400 301 */
AnnaBridge 172:65be27845400 302 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
AnnaBridge 172:65be27845400 303 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
AnnaBridge 172:65be27845400 304 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
AnnaBridge 172:65be27845400 305 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
AnnaBridge 172:65be27845400 306 /**
AnnaBridge 172:65be27845400 307 * @}
AnnaBridge 172:65be27845400 308 */
AnnaBridge 172:65be27845400 309
AnnaBridge 172:65be27845400 310 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
AnnaBridge 172:65be27845400 311 * @{
AnnaBridge 172:65be27845400 312 */
AnnaBridge 172:65be27845400 313 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
AnnaBridge 172:65be27845400 314 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
AnnaBridge 172:65be27845400 315 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
AnnaBridge 172:65be27845400 316 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
AnnaBridge 172:65be27845400 317 /**
AnnaBridge 172:65be27845400 318 * @}
AnnaBridge 172:65be27845400 319 */
AnnaBridge 172:65be27845400 320
AnnaBridge 172:65be27845400 321 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
AnnaBridge 172:65be27845400 322 * @{
AnnaBridge 172:65be27845400 323 */
AnnaBridge 172:65be27845400 324 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
AnnaBridge 172:65be27845400 325 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
AnnaBridge 172:65be27845400 326 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
AnnaBridge 172:65be27845400 327 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
AnnaBridge 172:65be27845400 328 /**
AnnaBridge 172:65be27845400 329 * @}
AnnaBridge 172:65be27845400 330 */
AnnaBridge 172:65be27845400 331
AnnaBridge 172:65be27845400 332 /** @defgroup QSPI_AddressMode QSPI Address Mode
AnnaBridge 172:65be27845400 333 * @{
AnnaBridge 172:65be27845400 334 */
AnnaBridge 172:65be27845400 335 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
AnnaBridge 172:65be27845400 336 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
AnnaBridge 172:65be27845400 337 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
AnnaBridge 172:65be27845400 338 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
AnnaBridge 172:65be27845400 339 /**
AnnaBridge 172:65be27845400 340 * @}
AnnaBridge 172:65be27845400 341 */
AnnaBridge 172:65be27845400 342
AnnaBridge 172:65be27845400 343 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
AnnaBridge 172:65be27845400 344 * @{
AnnaBridge 172:65be27845400 345 */
AnnaBridge 172:65be27845400 346 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
AnnaBridge 172:65be27845400 347 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
AnnaBridge 172:65be27845400 348 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
AnnaBridge 172:65be27845400 349 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
AnnaBridge 172:65be27845400 350 /**
AnnaBridge 172:65be27845400 351 * @}
AnnaBridge 172:65be27845400 352 */
AnnaBridge 172:65be27845400 353
AnnaBridge 172:65be27845400 354 /** @defgroup QSPI_DataMode QSPI Data Mode
AnnaBridge 172:65be27845400 355 * @{
AnnaBridge 172:65be27845400 356 */
AnnaBridge 172:65be27845400 357 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
AnnaBridge 172:65be27845400 358 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
AnnaBridge 172:65be27845400 359 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
AnnaBridge 172:65be27845400 360 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
AnnaBridge 172:65be27845400 361 /**
AnnaBridge 172:65be27845400 362 * @}
AnnaBridge 172:65be27845400 363 */
AnnaBridge 172:65be27845400 364
AnnaBridge 172:65be27845400 365 /** @defgroup QSPI_DdrMode QSPI DDR Mode
AnnaBridge 172:65be27845400 366 * @{
AnnaBridge 172:65be27845400 367 */
AnnaBridge 172:65be27845400 368 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
AnnaBridge 172:65be27845400 369 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
AnnaBridge 172:65be27845400 370 /**
AnnaBridge 172:65be27845400 371 * @}
AnnaBridge 172:65be27845400 372 */
AnnaBridge 172:65be27845400 373
AnnaBridge 172:65be27845400 374 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
AnnaBridge 172:65be27845400 375 * @{
AnnaBridge 172:65be27845400 376 */
AnnaBridge 172:65be27845400 377 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
AnnaBridge 172:65be27845400 378 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
AnnaBridge 172:65be27845400 379 /**
AnnaBridge 172:65be27845400 380 * @}
AnnaBridge 172:65be27845400 381 */
AnnaBridge 172:65be27845400 382
AnnaBridge 172:65be27845400 383 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
AnnaBridge 172:65be27845400 384 * @{
AnnaBridge 172:65be27845400 385 */
AnnaBridge 172:65be27845400 386 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
AnnaBridge 172:65be27845400 387 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
AnnaBridge 172:65be27845400 388 /**
AnnaBridge 172:65be27845400 389 * @}
AnnaBridge 172:65be27845400 390 */
AnnaBridge 172:65be27845400 391
AnnaBridge 172:65be27845400 392 /** @defgroup QSPI_MatchMode QSPI Match Mode
AnnaBridge 172:65be27845400 393 * @{
AnnaBridge 172:65be27845400 394 */
AnnaBridge 172:65be27845400 395 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
AnnaBridge 172:65be27845400 396 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
AnnaBridge 172:65be27845400 397 /**
AnnaBridge 172:65be27845400 398 * @}
AnnaBridge 172:65be27845400 399 */
AnnaBridge 172:65be27845400 400
AnnaBridge 172:65be27845400 401 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
AnnaBridge 172:65be27845400 402 * @{
AnnaBridge 172:65be27845400 403 */
AnnaBridge 172:65be27845400 404 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
AnnaBridge 172:65be27845400 405 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
AnnaBridge 172:65be27845400 406 /**
AnnaBridge 172:65be27845400 407 * @}
AnnaBridge 172:65be27845400 408 */
AnnaBridge 172:65be27845400 409
AnnaBridge 172:65be27845400 410 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
AnnaBridge 172:65be27845400 411 * @{
AnnaBridge 172:65be27845400 412 */
AnnaBridge 172:65be27845400 413 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
AnnaBridge 172:65be27845400 414 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
AnnaBridge 172:65be27845400 415 /**
AnnaBridge 172:65be27845400 416 * @}
AnnaBridge 172:65be27845400 417 */
AnnaBridge 172:65be27845400 418
AnnaBridge 172:65be27845400 419 /** @defgroup QSPI_Flags QSPI Flags
AnnaBridge 172:65be27845400 420 * @{
AnnaBridge 172:65be27845400 421 */
AnnaBridge 172:65be27845400 422 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
AnnaBridge 172:65be27845400 423 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
AnnaBridge 172:65be27845400 424 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
AnnaBridge 172:65be27845400 425 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
AnnaBridge 172:65be27845400 426 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
AnnaBridge 172:65be27845400 427 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
AnnaBridge 172:65be27845400 428 /**
AnnaBridge 172:65be27845400 429 * @}
AnnaBridge 172:65be27845400 430 */
AnnaBridge 172:65be27845400 431
AnnaBridge 172:65be27845400 432 /** @defgroup QSPI_Interrupts QSPI Interrupts
AnnaBridge 172:65be27845400 433 * @{
AnnaBridge 172:65be27845400 434 */
AnnaBridge 172:65be27845400 435 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
AnnaBridge 172:65be27845400 436 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
AnnaBridge 172:65be27845400 437 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
AnnaBridge 172:65be27845400 438 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
AnnaBridge 172:65be27845400 439 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
AnnaBridge 172:65be27845400 440 /**
AnnaBridge 172:65be27845400 441 * @}
AnnaBridge 172:65be27845400 442 */
AnnaBridge 172:65be27845400 443
AnnaBridge 172:65be27845400 444 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
AnnaBridge 172:65be27845400 445 * @brief QSPI Timeout definition
AnnaBridge 172:65be27845400 446 * @{
AnnaBridge 172:65be27845400 447 */
AnnaBridge 172:65be27845400 448 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
AnnaBridge 172:65be27845400 449 /**
AnnaBridge 172:65be27845400 450 * @}
AnnaBridge 172:65be27845400 451 */
AnnaBridge 172:65be27845400 452
AnnaBridge 172:65be27845400 453 /**
AnnaBridge 172:65be27845400 454 * @}
AnnaBridge 172:65be27845400 455 */
AnnaBridge 172:65be27845400 456
AnnaBridge 172:65be27845400 457 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 172:65be27845400 458 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
AnnaBridge 172:65be27845400 459 * @{
AnnaBridge 172:65be27845400 460 */
AnnaBridge 172:65be27845400 461 /** @brief Reset QSPI handle state.
AnnaBridge 172:65be27845400 462 * @param __HANDLE__: QSPI handle.
AnnaBridge 172:65be27845400 463 * @retval None
AnnaBridge 172:65be27845400 464 */
AnnaBridge 172:65be27845400 465 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 466 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
AnnaBridge 172:65be27845400 467 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
AnnaBridge 172:65be27845400 468 (__HANDLE__)->MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 469 (__HANDLE__)->MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 470 } while(0)
AnnaBridge 172:65be27845400 471 #else
AnnaBridge 172:65be27845400 472 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
AnnaBridge 172:65be27845400 473 #endif
AnnaBridge 172:65be27845400 474
AnnaBridge 172:65be27845400 475 /** @brief Enable the QSPI peripheral.
AnnaBridge 172:65be27845400 476 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 172:65be27845400 477 * @retval None
AnnaBridge 172:65be27845400 478 */
AnnaBridge 172:65be27845400 479 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 172:65be27845400 480
AnnaBridge 172:65be27845400 481 /** @brief Disable the QSPI peripheral.
AnnaBridge 172:65be27845400 482 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 172:65be27845400 483 * @retval None
AnnaBridge 172:65be27845400 484 */
AnnaBridge 172:65be27845400 485 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 172:65be27845400 486
AnnaBridge 172:65be27845400 487 /** @brief Enable the specified QSPI interrupt.
AnnaBridge 172:65be27845400 488 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 172:65be27845400 489 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
AnnaBridge 172:65be27845400 490 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 491 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 172:65be27845400 492 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 172:65be27845400 493 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 172:65be27845400 494 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 172:65be27845400 495 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 172:65be27845400 496 * @retval None
AnnaBridge 172:65be27845400 497 */
AnnaBridge 172:65be27845400 498 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 172:65be27845400 499
AnnaBridge 172:65be27845400 500
AnnaBridge 172:65be27845400 501 /** @brief Disable the specified QSPI interrupt.
AnnaBridge 172:65be27845400 502 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 172:65be27845400 503 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
AnnaBridge 172:65be27845400 504 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 505 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 172:65be27845400 506 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 172:65be27845400 507 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 172:65be27845400 508 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 172:65be27845400 509 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 172:65be27845400 510 * @retval None
AnnaBridge 172:65be27845400 511 */
AnnaBridge 172:65be27845400 512 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 172:65be27845400 513
AnnaBridge 172:65be27845400 514 /** @brief Check whether the specified QSPI interrupt source is enabled or not.
AnnaBridge 172:65be27845400 515 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 172:65be27845400 516 * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
AnnaBridge 172:65be27845400 517 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 518 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 172:65be27845400 519 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 172:65be27845400 520 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 172:65be27845400 521 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 172:65be27845400 522 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 172:65be27845400 523 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 172:65be27845400 524 */
AnnaBridge 172:65be27845400 525 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 172:65be27845400 526
AnnaBridge 172:65be27845400 527 /**
AnnaBridge 172:65be27845400 528 * @brief Check whether the selected QSPI flag is set or not.
AnnaBridge 172:65be27845400 529 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 172:65be27845400 530 * @param __FLAG__: specifies the QSPI flag to check.
AnnaBridge 172:65be27845400 531 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 532 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
AnnaBridge 172:65be27845400 533 * @arg QSPI_FLAG_TO: QSPI Timeout flag
AnnaBridge 172:65be27845400 534 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 172:65be27845400 535 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
AnnaBridge 172:65be27845400 536 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 172:65be27845400 537 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 172:65be27845400 538 * @retval None
AnnaBridge 172:65be27845400 539 */
AnnaBridge 172:65be27845400 540 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
AnnaBridge 172:65be27845400 541
AnnaBridge 172:65be27845400 542 /** @brief Clears the specified QSPI's flag status.
AnnaBridge 172:65be27845400 543 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 172:65be27845400 544 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
AnnaBridge 172:65be27845400 545 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 546 * @arg QSPI_FLAG_TO: QSPI Timeout flag
AnnaBridge 172:65be27845400 547 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 172:65be27845400 548 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 172:65be27845400 549 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 172:65be27845400 550 * @retval None
AnnaBridge 172:65be27845400 551 */
AnnaBridge 172:65be27845400 552 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
AnnaBridge 172:65be27845400 553 /**
AnnaBridge 172:65be27845400 554 * @}
AnnaBridge 172:65be27845400 555 */
AnnaBridge 172:65be27845400 556
AnnaBridge 172:65be27845400 557 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 558 /** @addtogroup QSPI_Exported_Functions
AnnaBridge 172:65be27845400 559 * @{
AnnaBridge 172:65be27845400 560 */
AnnaBridge 172:65be27845400 561 /* Initialization/de-initialization functions ********************************/
AnnaBridge 172:65be27845400 562 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 563 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 564 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 565 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 566
AnnaBridge 172:65be27845400 567 /* IO operation functions *****************************************************/
AnnaBridge 172:65be27845400 568 /* QSPI IRQ handler method */
AnnaBridge 172:65be27845400 569 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 570
AnnaBridge 172:65be27845400 571 /* QSPI indirect mode */
AnnaBridge 172:65be27845400 572 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
AnnaBridge 172:65be27845400 573 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 172:65be27845400 574 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 172:65be27845400 575 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
AnnaBridge 172:65be27845400 576 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 172:65be27845400 577 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 172:65be27845400 578 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 172:65be27845400 579 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 172:65be27845400 580
AnnaBridge 172:65be27845400 581 /* QSPI status flag polling mode */
AnnaBridge 172:65be27845400 582 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
AnnaBridge 172:65be27845400 583 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
AnnaBridge 172:65be27845400 584
AnnaBridge 172:65be27845400 585 /* QSPI memory-mapped mode */
AnnaBridge 172:65be27845400 586 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
AnnaBridge 172:65be27845400 587
AnnaBridge 172:65be27845400 588 /* Callback functions in non-blocking modes ***********************************/
AnnaBridge 172:65be27845400 589 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 590 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 591 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 592
AnnaBridge 172:65be27845400 593 /* QSPI indirect mode */
AnnaBridge 172:65be27845400 594 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 595 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 596 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 597
AnnaBridge 172:65be27845400 598 /* QSPI status flag polling mode */
AnnaBridge 172:65be27845400 599 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 600
AnnaBridge 172:65be27845400 601 /* QSPI memory-mapped mode */
AnnaBridge 172:65be27845400 602 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 603
AnnaBridge 172:65be27845400 604 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 605 /* QSPI callback registering/unregistering */
AnnaBridge 172:65be27845400 606 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
AnnaBridge 172:65be27845400 607 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
AnnaBridge 172:65be27845400 608 #endif
AnnaBridge 172:65be27845400 609 /**
AnnaBridge 172:65be27845400 610 * @}
AnnaBridge 172:65be27845400 611 */
AnnaBridge 172:65be27845400 612
AnnaBridge 172:65be27845400 613 /** @addtogroup QSPI_Exported_Functions_Group3
AnnaBridge 172:65be27845400 614 * @{
AnnaBridge 172:65be27845400 615 */
AnnaBridge 172:65be27845400 616 /* Peripheral Control and State functions ************************************/
AnnaBridge 172:65be27845400 617 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 618 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 619 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 620 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 621 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
AnnaBridge 172:65be27845400 622 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
AnnaBridge 172:65be27845400 623 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
AnnaBridge 172:65be27845400 624 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
AnnaBridge 172:65be27845400 625 /**
AnnaBridge 172:65be27845400 626 * @}
AnnaBridge 172:65be27845400 627 */
AnnaBridge 172:65be27845400 628
AnnaBridge 172:65be27845400 629 /* End of exported functions -------------------------------------------------*/
AnnaBridge 172:65be27845400 630
AnnaBridge 172:65be27845400 631 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 632 /** @defgroup QSPI_Private_Macros QSPI Private Macros
AnnaBridge 172:65be27845400 633 * @{
AnnaBridge 172:65be27845400 634 */
AnnaBridge 172:65be27845400 635 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
AnnaBridge 172:65be27845400 636
AnnaBridge 172:65be27845400 637 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
AnnaBridge 172:65be27845400 638
AnnaBridge 172:65be27845400 639 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
AnnaBridge 172:65be27845400 640 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
AnnaBridge 172:65be27845400 641
AnnaBridge 172:65be27845400 642 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
AnnaBridge 172:65be27845400 643
AnnaBridge 172:65be27845400 644 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
AnnaBridge 172:65be27845400 645 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
AnnaBridge 172:65be27845400 646 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
AnnaBridge 172:65be27845400 647 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
AnnaBridge 172:65be27845400 648 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
AnnaBridge 172:65be27845400 649 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
AnnaBridge 172:65be27845400 650 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
AnnaBridge 172:65be27845400 651 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
AnnaBridge 172:65be27845400 652
AnnaBridge 172:65be27845400 653 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
AnnaBridge 172:65be27845400 654 ((CLKMODE) == QSPI_CLOCK_MODE_3))
AnnaBridge 172:65be27845400 655
AnnaBridge 172:65be27845400 656
AnnaBridge 172:65be27845400 657 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
AnnaBridge 172:65be27845400 658 ((FLASH_ID) == QSPI_FLASH_ID_2))
AnnaBridge 172:65be27845400 659
AnnaBridge 172:65be27845400 660 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
AnnaBridge 172:65be27845400 661 ((MODE) == QSPI_DUALFLASH_DISABLE))
AnnaBridge 172:65be27845400 662
AnnaBridge 172:65be27845400 663 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
AnnaBridge 172:65be27845400 664
AnnaBridge 172:65be27845400 665 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
AnnaBridge 172:65be27845400 666 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
AnnaBridge 172:65be27845400 667 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
AnnaBridge 172:65be27845400 668 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
AnnaBridge 172:65be27845400 669
AnnaBridge 172:65be27845400 670 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
AnnaBridge 172:65be27845400 671 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
AnnaBridge 172:65be27845400 672 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
AnnaBridge 172:65be27845400 673 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
AnnaBridge 172:65be27845400 674
AnnaBridge 172:65be27845400 675 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
AnnaBridge 172:65be27845400 676
AnnaBridge 172:65be27845400 677 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
AnnaBridge 172:65be27845400 678 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
AnnaBridge 172:65be27845400 679 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
AnnaBridge 172:65be27845400 680 ((MODE) == QSPI_INSTRUCTION_4_LINES))
AnnaBridge 172:65be27845400 681
AnnaBridge 172:65be27845400 682 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
AnnaBridge 172:65be27845400 683 ((MODE) == QSPI_ADDRESS_1_LINE) || \
AnnaBridge 172:65be27845400 684 ((MODE) == QSPI_ADDRESS_2_LINES) || \
AnnaBridge 172:65be27845400 685 ((MODE) == QSPI_ADDRESS_4_LINES))
AnnaBridge 172:65be27845400 686
AnnaBridge 172:65be27845400 687 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
AnnaBridge 172:65be27845400 688 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
AnnaBridge 172:65be27845400 689 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
AnnaBridge 172:65be27845400 690 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
AnnaBridge 172:65be27845400 691
AnnaBridge 172:65be27845400 692 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
AnnaBridge 172:65be27845400 693 ((MODE) == QSPI_DATA_1_LINE) || \
AnnaBridge 172:65be27845400 694 ((MODE) == QSPI_DATA_2_LINES) || \
AnnaBridge 172:65be27845400 695 ((MODE) == QSPI_DATA_4_LINES))
AnnaBridge 172:65be27845400 696
AnnaBridge 172:65be27845400 697 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
AnnaBridge 172:65be27845400 698 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
AnnaBridge 172:65be27845400 699
AnnaBridge 172:65be27845400 700 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
AnnaBridge 172:65be27845400 701 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
AnnaBridge 172:65be27845400 702
AnnaBridge 172:65be27845400 703 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
AnnaBridge 172:65be27845400 704 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
AnnaBridge 172:65be27845400 705
AnnaBridge 172:65be27845400 706 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
AnnaBridge 172:65be27845400 707
AnnaBridge 172:65be27845400 708 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
AnnaBridge 172:65be27845400 709
AnnaBridge 172:65be27845400 710 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
AnnaBridge 172:65be27845400 711 ((MODE) == QSPI_MATCH_MODE_OR))
AnnaBridge 172:65be27845400 712
AnnaBridge 172:65be27845400 713 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
AnnaBridge 172:65be27845400 714 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
AnnaBridge 172:65be27845400 715
AnnaBridge 172:65be27845400 716 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
AnnaBridge 172:65be27845400 717 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
AnnaBridge 172:65be27845400 718
AnnaBridge 172:65be27845400 719 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
AnnaBridge 172:65be27845400 720 /**
AnnaBridge 172:65be27845400 721 * @}
AnnaBridge 172:65be27845400 722 */
AnnaBridge 172:65be27845400 723 /* End of private macros -----------------------------------------------------*/
AnnaBridge 172:65be27845400 724
AnnaBridge 172:65be27845400 725 /**
AnnaBridge 172:65be27845400 726 * @}
AnnaBridge 172:65be27845400 727 */
AnnaBridge 172:65be27845400 728
AnnaBridge 172:65be27845400 729 /**
AnnaBridge 172:65be27845400 730 * @}
AnnaBridge 172:65be27845400 731 */
AnnaBridge 172:65be27845400 732
AnnaBridge 172:65be27845400 733 /**
AnnaBridge 172:65be27845400 734 * @}
AnnaBridge 172:65be27845400 735 */
AnnaBridge 172:65be27845400 736 #ifdef __cplusplus
AnnaBridge 172:65be27845400 737 }
AnnaBridge 172:65be27845400 738 #endif
AnnaBridge 172:65be27845400 739
AnnaBridge 172:65be27845400 740 #endif /* STM32H7xx_HAL_QSPI_H */
AnnaBridge 172:65be27845400 741
AnnaBridge 172:65be27845400 742 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/