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TARGET_NUCLEO_H743ZI/TOOLCHAIN_GCC_ARM/stm32h7xx_hal_cortex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32h7xx_hal_cortex.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief Header file of CORTEX HAL module. |
| AnnaBridge | 172:65be27845400 | 6 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 7 | * @attention |
| AnnaBridge | 172:65be27845400 | 8 | * |
| AnnaBridge | 172:65be27845400 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. |
| AnnaBridge | 172:65be27845400 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 172:65be27845400 | 11 | * |
| AnnaBridge | 172:65be27845400 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 172:65be27845400 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 172:65be27845400 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 172:65be27845400 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 172:65be27845400 | 16 | * |
| AnnaBridge | 172:65be27845400 | 17 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 18 | */ |
| AnnaBridge | 172:65be27845400 | 19 | |
| AnnaBridge | 172:65be27845400 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 21 | #ifndef STM32H7xx_HAL_CORTEX_H |
| AnnaBridge | 172:65be27845400 | 22 | #define STM32H7xx_HAL_CORTEX_H |
| AnnaBridge | 172:65be27845400 | 23 | |
| AnnaBridge | 172:65be27845400 | 24 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 25 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 26 | #endif |
| AnnaBridge | 172:65be27845400 | 27 | |
| AnnaBridge | 172:65be27845400 | 28 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 29 | #include "stm32h7xx_hal_def.h" |
| AnnaBridge | 172:65be27845400 | 30 | |
| AnnaBridge | 172:65be27845400 | 31 | /** @addtogroup STM32H7xx_HAL_Driver |
| AnnaBridge | 172:65be27845400 | 32 | * @{ |
| AnnaBridge | 172:65be27845400 | 33 | */ |
| AnnaBridge | 172:65be27845400 | 34 | |
| AnnaBridge | 172:65be27845400 | 35 | /** @addtogroup CORTEX |
| AnnaBridge | 172:65be27845400 | 36 | * @{ |
| AnnaBridge | 172:65be27845400 | 37 | */ |
| AnnaBridge | 172:65be27845400 | 38 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 39 | /** @defgroup CORTEX_Exported_Types Cortex Exported Types |
| AnnaBridge | 172:65be27845400 | 40 | * @{ |
| AnnaBridge | 172:65be27845400 | 41 | */ |
| AnnaBridge | 172:65be27845400 | 42 | |
| AnnaBridge | 172:65be27845400 | 43 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 172:65be27845400 | 44 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
| AnnaBridge | 172:65be27845400 | 45 | * @brief MPU Region initialization structure |
| AnnaBridge | 172:65be27845400 | 46 | * @{ |
| AnnaBridge | 172:65be27845400 | 47 | */ |
| AnnaBridge | 172:65be27845400 | 48 | typedef struct |
| AnnaBridge | 172:65be27845400 | 49 | { |
| AnnaBridge | 172:65be27845400 | 50 | uint8_t Enable; /*!< Specifies the status of the region. |
| AnnaBridge | 172:65be27845400 | 51 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
| AnnaBridge | 172:65be27845400 | 52 | uint8_t Number; /*!< Specifies the number of the region to protect. |
| AnnaBridge | 172:65be27845400 | 53 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
| AnnaBridge | 172:65be27845400 | 54 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
| AnnaBridge | 172:65be27845400 | 55 | uint8_t Size; /*!< Specifies the size of the region to protect. |
| AnnaBridge | 172:65be27845400 | 56 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
| AnnaBridge | 172:65be27845400 | 57 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
| AnnaBridge | 172:65be27845400 | 58 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| AnnaBridge | 172:65be27845400 | 59 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
| AnnaBridge | 172:65be27845400 | 60 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
| AnnaBridge | 172:65be27845400 | 61 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
| AnnaBridge | 172:65be27845400 | 62 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
| AnnaBridge | 172:65be27845400 | 63 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
| AnnaBridge | 172:65be27845400 | 64 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
| AnnaBridge | 172:65be27845400 | 65 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
| AnnaBridge | 172:65be27845400 | 66 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
| AnnaBridge | 172:65be27845400 | 67 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
| AnnaBridge | 172:65be27845400 | 68 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
| AnnaBridge | 172:65be27845400 | 69 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
| AnnaBridge | 172:65be27845400 | 70 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
| AnnaBridge | 172:65be27845400 | 71 | }MPU_Region_InitTypeDef; |
| AnnaBridge | 172:65be27845400 | 72 | /** |
| AnnaBridge | 172:65be27845400 | 73 | * @} |
| AnnaBridge | 172:65be27845400 | 74 | */ |
| AnnaBridge | 172:65be27845400 | 75 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 172:65be27845400 | 76 | |
| AnnaBridge | 172:65be27845400 | 77 | /** |
| AnnaBridge | 172:65be27845400 | 78 | * @} |
| AnnaBridge | 172:65be27845400 | 79 | */ |
| AnnaBridge | 172:65be27845400 | 80 | |
| AnnaBridge | 172:65be27845400 | 81 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 82 | |
| AnnaBridge | 172:65be27845400 | 83 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
| AnnaBridge | 172:65be27845400 | 84 | * @{ |
| AnnaBridge | 172:65be27845400 | 85 | */ |
| AnnaBridge | 172:65be27845400 | 86 | |
| AnnaBridge | 172:65be27845400 | 87 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
| AnnaBridge | 172:65be27845400 | 88 | * @{ |
| AnnaBridge | 172:65be27845400 | 89 | */ |
| AnnaBridge | 172:65be27845400 | 90 | #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority |
| AnnaBridge | 172:65be27845400 | 91 | 4 bits for subpriority */ |
| AnnaBridge | 172:65be27845400 | 92 | #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority |
| AnnaBridge | 172:65be27845400 | 93 | 3 bits for subpriority */ |
| AnnaBridge | 172:65be27845400 | 94 | #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority |
| AnnaBridge | 172:65be27845400 | 95 | 2 bits for subpriority */ |
| AnnaBridge | 172:65be27845400 | 96 | #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority |
| AnnaBridge | 172:65be27845400 | 97 | 1 bits for subpriority */ |
| AnnaBridge | 172:65be27845400 | 98 | #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority |
| AnnaBridge | 172:65be27845400 | 99 | 0 bits for subpriority */ |
| AnnaBridge | 172:65be27845400 | 100 | /** |
| AnnaBridge | 172:65be27845400 | 101 | * @} |
| AnnaBridge | 172:65be27845400 | 102 | */ |
| AnnaBridge | 172:65be27845400 | 103 | |
| AnnaBridge | 172:65be27845400 | 104 | /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source |
| AnnaBridge | 172:65be27845400 | 105 | * @{ |
| AnnaBridge | 172:65be27845400 | 106 | */ |
| AnnaBridge | 172:65be27845400 | 107 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) |
| AnnaBridge | 172:65be27845400 | 108 | #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) |
| AnnaBridge | 172:65be27845400 | 109 | |
| AnnaBridge | 172:65be27845400 | 110 | /** |
| AnnaBridge | 172:65be27845400 | 111 | * @} |
| AnnaBridge | 172:65be27845400 | 112 | */ |
| AnnaBridge | 172:65be27845400 | 113 | |
| AnnaBridge | 172:65be27845400 | 114 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 172:65be27845400 | 115 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control |
| AnnaBridge | 172:65be27845400 | 116 | * @{ |
| AnnaBridge | 172:65be27845400 | 117 | */ |
| AnnaBridge | 172:65be27845400 | 118 | #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) |
| AnnaBridge | 172:65be27845400 | 119 | #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) |
| AnnaBridge | 172:65be27845400 | 120 | #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) |
| AnnaBridge | 172:65be27845400 | 121 | #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) |
| AnnaBridge | 172:65be27845400 | 122 | /** |
| AnnaBridge | 172:65be27845400 | 123 | * @} |
| AnnaBridge | 172:65be27845400 | 124 | */ |
| AnnaBridge | 172:65be27845400 | 125 | |
| AnnaBridge | 172:65be27845400 | 126 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
| AnnaBridge | 172:65be27845400 | 127 | * @{ |
| AnnaBridge | 172:65be27845400 | 128 | */ |
| AnnaBridge | 172:65be27845400 | 129 | #define MPU_REGION_ENABLE ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 130 | #define MPU_REGION_DISABLE ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 131 | /** |
| AnnaBridge | 172:65be27845400 | 132 | * @} |
| AnnaBridge | 172:65be27845400 | 133 | */ |
| AnnaBridge | 172:65be27845400 | 134 | |
| AnnaBridge | 172:65be27845400 | 135 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
| AnnaBridge | 172:65be27845400 | 136 | * @{ |
| AnnaBridge | 172:65be27845400 | 137 | */ |
| AnnaBridge | 172:65be27845400 | 138 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 139 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 140 | /** |
| AnnaBridge | 172:65be27845400 | 141 | * @} |
| AnnaBridge | 172:65be27845400 | 142 | */ |
| AnnaBridge | 172:65be27845400 | 143 | |
| AnnaBridge | 172:65be27845400 | 144 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
| AnnaBridge | 172:65be27845400 | 145 | * @{ |
| AnnaBridge | 172:65be27845400 | 146 | */ |
| AnnaBridge | 172:65be27845400 | 147 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 148 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 149 | /** |
| AnnaBridge | 172:65be27845400 | 150 | * @} |
| AnnaBridge | 172:65be27845400 | 151 | */ |
| AnnaBridge | 172:65be27845400 | 152 | |
| AnnaBridge | 172:65be27845400 | 153 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
| AnnaBridge | 172:65be27845400 | 154 | * @{ |
| AnnaBridge | 172:65be27845400 | 155 | */ |
| AnnaBridge | 172:65be27845400 | 156 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 157 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 158 | /** |
| AnnaBridge | 172:65be27845400 | 159 | * @} |
| AnnaBridge | 172:65be27845400 | 160 | */ |
| AnnaBridge | 172:65be27845400 | 161 | |
| AnnaBridge | 172:65be27845400 | 162 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
| AnnaBridge | 172:65be27845400 | 163 | * @{ |
| AnnaBridge | 172:65be27845400 | 164 | */ |
| AnnaBridge | 172:65be27845400 | 165 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 166 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 167 | /** |
| AnnaBridge | 172:65be27845400 | 168 | * @} |
| AnnaBridge | 172:65be27845400 | 169 | */ |
| AnnaBridge | 172:65be27845400 | 170 | |
| AnnaBridge | 172:65be27845400 | 171 | /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels |
| AnnaBridge | 172:65be27845400 | 172 | * @{ |
| AnnaBridge | 172:65be27845400 | 173 | */ |
| AnnaBridge | 172:65be27845400 | 174 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 175 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 176 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
| AnnaBridge | 172:65be27845400 | 177 | /** |
| AnnaBridge | 172:65be27845400 | 178 | * @} |
| AnnaBridge | 172:65be27845400 | 179 | */ |
| AnnaBridge | 172:65be27845400 | 180 | |
| AnnaBridge | 172:65be27845400 | 181 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
| AnnaBridge | 172:65be27845400 | 182 | * @{ |
| AnnaBridge | 172:65be27845400 | 183 | */ |
| AnnaBridge | 172:65be27845400 | 184 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
| AnnaBridge | 172:65be27845400 | 185 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
| AnnaBridge | 172:65be27845400 | 186 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
| AnnaBridge | 172:65be27845400 | 187 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
| AnnaBridge | 172:65be27845400 | 188 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
| AnnaBridge | 172:65be27845400 | 189 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
| AnnaBridge | 172:65be27845400 | 190 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
| AnnaBridge | 172:65be27845400 | 191 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
| AnnaBridge | 172:65be27845400 | 192 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
| AnnaBridge | 172:65be27845400 | 193 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
| AnnaBridge | 172:65be27845400 | 194 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
| AnnaBridge | 172:65be27845400 | 195 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
| AnnaBridge | 172:65be27845400 | 196 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
| AnnaBridge | 172:65be27845400 | 197 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
| AnnaBridge | 172:65be27845400 | 198 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
| AnnaBridge | 172:65be27845400 | 199 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
| AnnaBridge | 172:65be27845400 | 200 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
| AnnaBridge | 172:65be27845400 | 201 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
| AnnaBridge | 172:65be27845400 | 202 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
| AnnaBridge | 172:65be27845400 | 203 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
| AnnaBridge | 172:65be27845400 | 204 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
| AnnaBridge | 172:65be27845400 | 205 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
| AnnaBridge | 172:65be27845400 | 206 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
| AnnaBridge | 172:65be27845400 | 207 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
| AnnaBridge | 172:65be27845400 | 208 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
| AnnaBridge | 172:65be27845400 | 209 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
| AnnaBridge | 172:65be27845400 | 210 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
| AnnaBridge | 172:65be27845400 | 211 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
| AnnaBridge | 172:65be27845400 | 212 | /** |
| AnnaBridge | 172:65be27845400 | 213 | * @} |
| AnnaBridge | 172:65be27845400 | 214 | */ |
| AnnaBridge | 172:65be27845400 | 215 | |
| AnnaBridge | 172:65be27845400 | 216 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
| AnnaBridge | 172:65be27845400 | 217 | * @{ |
| AnnaBridge | 172:65be27845400 | 218 | */ |
| AnnaBridge | 172:65be27845400 | 219 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 220 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 221 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
| AnnaBridge | 172:65be27845400 | 222 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
| AnnaBridge | 172:65be27845400 | 223 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
| AnnaBridge | 172:65be27845400 | 224 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
| AnnaBridge | 172:65be27845400 | 225 | /** |
| AnnaBridge | 172:65be27845400 | 226 | * @} |
| AnnaBridge | 172:65be27845400 | 227 | */ |
| AnnaBridge | 172:65be27845400 | 228 | |
| AnnaBridge | 172:65be27845400 | 229 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
| AnnaBridge | 172:65be27845400 | 230 | * @{ |
| AnnaBridge | 172:65be27845400 | 231 | */ |
| AnnaBridge | 172:65be27845400 | 232 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
| AnnaBridge | 172:65be27845400 | 233 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
| AnnaBridge | 172:65be27845400 | 234 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
| AnnaBridge | 172:65be27845400 | 235 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
| AnnaBridge | 172:65be27845400 | 236 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
| AnnaBridge | 172:65be27845400 | 237 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
| AnnaBridge | 172:65be27845400 | 238 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
| AnnaBridge | 172:65be27845400 | 239 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
| AnnaBridge | 172:65be27845400 | 240 | #define MPU_REGION_NUMBER8 ((uint8_t)0x08) |
| AnnaBridge | 172:65be27845400 | 241 | #define MPU_REGION_NUMBER9 ((uint8_t)0x09) |
| AnnaBridge | 172:65be27845400 | 242 | #define MPU_REGION_NUMBER10 ((uint8_t)0x0A) |
| AnnaBridge | 172:65be27845400 | 243 | #define MPU_REGION_NUMBER11 ((uint8_t)0x0B) |
| AnnaBridge | 172:65be27845400 | 244 | #define MPU_REGION_NUMBER12 ((uint8_t)0x0C) |
| AnnaBridge | 172:65be27845400 | 245 | #define MPU_REGION_NUMBER13 ((uint8_t)0x0D) |
| AnnaBridge | 172:65be27845400 | 246 | #define MPU_REGION_NUMBER14 ((uint8_t)0x0E) |
| AnnaBridge | 172:65be27845400 | 247 | #define MPU_REGION_NUMBER15 ((uint8_t)0x0F) |
| AnnaBridge | 172:65be27845400 | 248 | |
| AnnaBridge | 172:65be27845400 | 249 | /** |
| AnnaBridge | 172:65be27845400 | 250 | * @} |
| AnnaBridge | 172:65be27845400 | 251 | */ |
| AnnaBridge | 172:65be27845400 | 252 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 172:65be27845400 | 253 | |
| AnnaBridge | 172:65be27845400 | 254 | /** |
| AnnaBridge | 172:65be27845400 | 255 | * @} |
| AnnaBridge | 172:65be27845400 | 256 | */ |
| AnnaBridge | 172:65be27845400 | 257 | |
| AnnaBridge | 172:65be27845400 | 258 | |
| AnnaBridge | 172:65be27845400 | 259 | /* Exported Macros -----------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 260 | /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros |
| AnnaBridge | 172:65be27845400 | 261 | * @{ |
| AnnaBridge | 172:65be27845400 | 262 | */ |
| AnnaBridge | 172:65be27845400 | 263 | |
| AnnaBridge | 172:65be27845400 | 264 | /** |
| AnnaBridge | 172:65be27845400 | 265 | * @} |
| AnnaBridge | 172:65be27845400 | 266 | */ |
| AnnaBridge | 172:65be27845400 | 267 | |
| AnnaBridge | 172:65be27845400 | 268 | |
| AnnaBridge | 172:65be27845400 | 269 | |
| AnnaBridge | 172:65be27845400 | 270 | /** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier |
| AnnaBridge | 172:65be27845400 | 271 | * @{ |
| AnnaBridge | 172:65be27845400 | 272 | */ |
| AnnaBridge | 172:65be27845400 | 273 | #define CM7_CPUID ((uint32_t)0x00000003) |
| AnnaBridge | 172:65be27845400 | 274 | |
| AnnaBridge | 172:65be27845400 | 275 | /** |
| AnnaBridge | 172:65be27845400 | 276 | * @} |
| AnnaBridge | 172:65be27845400 | 277 | */ |
| AnnaBridge | 172:65be27845400 | 278 | |
| AnnaBridge | 172:65be27845400 | 279 | |
| AnnaBridge | 172:65be27845400 | 280 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 281 | /** @addtogroup CORTEX_Exported_Functions |
| AnnaBridge | 172:65be27845400 | 282 | * @{ |
| AnnaBridge | 172:65be27845400 | 283 | */ |
| AnnaBridge | 172:65be27845400 | 284 | |
| AnnaBridge | 172:65be27845400 | 285 | /** @addtogroup CORTEX_Exported_Functions_Group1 |
| AnnaBridge | 172:65be27845400 | 286 | * @{ |
| AnnaBridge | 172:65be27845400 | 287 | */ |
| AnnaBridge | 172:65be27845400 | 288 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 172:65be27845400 | 289 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
| AnnaBridge | 172:65be27845400 | 290 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
| AnnaBridge | 172:65be27845400 | 291 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
| AnnaBridge | 172:65be27845400 | 292 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
| AnnaBridge | 172:65be27845400 | 293 | void HAL_NVIC_SystemReset(void); |
| AnnaBridge | 172:65be27845400 | 294 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
| AnnaBridge | 172:65be27845400 | 295 | /** |
| AnnaBridge | 172:65be27845400 | 296 | * @} |
| AnnaBridge | 172:65be27845400 | 297 | */ |
| AnnaBridge | 172:65be27845400 | 298 | |
| AnnaBridge | 172:65be27845400 | 299 | /** @addtogroup CORTEX_Exported_Functions_Group2 |
| AnnaBridge | 172:65be27845400 | 300 | * @{ |
| AnnaBridge | 172:65be27845400 | 301 | */ |
| AnnaBridge | 172:65be27845400 | 302 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 172:65be27845400 | 303 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 172:65be27845400 | 304 | void HAL_MPU_Enable(uint32_t MPU_Control); |
| AnnaBridge | 172:65be27845400 | 305 | void HAL_MPU_Disable(void); |
| AnnaBridge | 172:65be27845400 | 306 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
| AnnaBridge | 172:65be27845400 | 307 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 172:65be27845400 | 308 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
| AnnaBridge | 172:65be27845400 | 309 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
| AnnaBridge | 172:65be27845400 | 310 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 172:65be27845400 | 311 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 172:65be27845400 | 312 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
| AnnaBridge | 172:65be27845400 | 313 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
| AnnaBridge | 172:65be27845400 | 314 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
| AnnaBridge | 172:65be27845400 | 315 | void HAL_SYSTICK_IRQHandler(void); |
| AnnaBridge | 172:65be27845400 | 316 | void HAL_SYSTICK_Callback(void); |
| AnnaBridge | 172:65be27845400 | 317 | uint32_t HAL_GetCurrentCPUID(void); |
| AnnaBridge | 172:65be27845400 | 318 | |
| AnnaBridge | 172:65be27845400 | 319 | |
| AnnaBridge | 172:65be27845400 | 320 | /** |
| AnnaBridge | 172:65be27845400 | 321 | * @} |
| AnnaBridge | 172:65be27845400 | 322 | */ |
| AnnaBridge | 172:65be27845400 | 323 | |
| AnnaBridge | 172:65be27845400 | 324 | /** |
| AnnaBridge | 172:65be27845400 | 325 | * @} |
| AnnaBridge | 172:65be27845400 | 326 | */ |
| AnnaBridge | 172:65be27845400 | 327 | |
| AnnaBridge | 172:65be27845400 | 328 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 329 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 330 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 331 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 332 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
| AnnaBridge | 172:65be27845400 | 333 | * @{ |
| AnnaBridge | 172:65be27845400 | 334 | */ |
| AnnaBridge | 172:65be27845400 | 335 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
| AnnaBridge | 172:65be27845400 | 336 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
| AnnaBridge | 172:65be27845400 | 337 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
| AnnaBridge | 172:65be27845400 | 338 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
| AnnaBridge | 172:65be27845400 | 339 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
| AnnaBridge | 172:65be27845400 | 340 | |
| AnnaBridge | 172:65be27845400 | 341 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) |
| AnnaBridge | 172:65be27845400 | 342 | |
| AnnaBridge | 172:65be27845400 | 343 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) |
| AnnaBridge | 172:65be27845400 | 344 | |
| AnnaBridge | 172:65be27845400 | 345 | #define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00) |
| AnnaBridge | 172:65be27845400 | 346 | |
| AnnaBridge | 172:65be27845400 | 347 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
| AnnaBridge | 172:65be27845400 | 348 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
| AnnaBridge | 172:65be27845400 | 349 | |
| AnnaBridge | 172:65be27845400 | 350 | #if (__MPU_PRESENT == 1) |
| AnnaBridge | 172:65be27845400 | 351 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
| AnnaBridge | 172:65be27845400 | 352 | ((STATE) == MPU_REGION_DISABLE)) |
| AnnaBridge | 172:65be27845400 | 353 | |
| AnnaBridge | 172:65be27845400 | 354 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
| AnnaBridge | 172:65be27845400 | 355 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
| AnnaBridge | 172:65be27845400 | 356 | |
| AnnaBridge | 172:65be27845400 | 357 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
| AnnaBridge | 172:65be27845400 | 358 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
| AnnaBridge | 172:65be27845400 | 359 | |
| AnnaBridge | 172:65be27845400 | 360 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
| AnnaBridge | 172:65be27845400 | 361 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
| AnnaBridge | 172:65be27845400 | 362 | |
| AnnaBridge | 172:65be27845400 | 363 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
| AnnaBridge | 172:65be27845400 | 364 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
| AnnaBridge | 172:65be27845400 | 365 | |
| AnnaBridge | 172:65be27845400 | 366 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
| AnnaBridge | 172:65be27845400 | 367 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
| AnnaBridge | 172:65be27845400 | 368 | ((TYPE) == MPU_TEX_LEVEL2)) |
| AnnaBridge | 172:65be27845400 | 369 | |
| AnnaBridge | 172:65be27845400 | 370 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
| AnnaBridge | 172:65be27845400 | 371 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
| AnnaBridge | 172:65be27845400 | 372 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
| AnnaBridge | 172:65be27845400 | 373 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
| AnnaBridge | 172:65be27845400 | 374 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
| AnnaBridge | 172:65be27845400 | 375 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
| AnnaBridge | 172:65be27845400 | 376 | |
| AnnaBridge | 172:65be27845400 | 377 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
| AnnaBridge | 172:65be27845400 | 378 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
| AnnaBridge | 172:65be27845400 | 379 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
| AnnaBridge | 172:65be27845400 | 380 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
| AnnaBridge | 172:65be27845400 | 381 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
| AnnaBridge | 172:65be27845400 | 382 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
| AnnaBridge | 172:65be27845400 | 383 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
| AnnaBridge | 172:65be27845400 | 384 | ((NUMBER) == MPU_REGION_NUMBER7) || \ |
| AnnaBridge | 172:65be27845400 | 385 | ((NUMBER) == MPU_REGION_NUMBER8) || \ |
| AnnaBridge | 172:65be27845400 | 386 | ((NUMBER) == MPU_REGION_NUMBER9) || \ |
| AnnaBridge | 172:65be27845400 | 387 | ((NUMBER) == MPU_REGION_NUMBER10) || \ |
| AnnaBridge | 172:65be27845400 | 388 | ((NUMBER) == MPU_REGION_NUMBER11) || \ |
| AnnaBridge | 172:65be27845400 | 389 | ((NUMBER) == MPU_REGION_NUMBER12) || \ |
| AnnaBridge | 172:65be27845400 | 390 | ((NUMBER) == MPU_REGION_NUMBER13) || \ |
| AnnaBridge | 172:65be27845400 | 391 | ((NUMBER) == MPU_REGION_NUMBER14) || \ |
| AnnaBridge | 172:65be27845400 | 392 | ((NUMBER) == MPU_REGION_NUMBER15)) |
| AnnaBridge | 172:65be27845400 | 393 | |
| AnnaBridge | 172:65be27845400 | 394 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
| AnnaBridge | 172:65be27845400 | 395 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
| AnnaBridge | 172:65be27845400 | 396 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
| AnnaBridge | 172:65be27845400 | 397 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
| AnnaBridge | 172:65be27845400 | 398 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
| AnnaBridge | 172:65be27845400 | 399 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
| AnnaBridge | 172:65be27845400 | 400 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
| AnnaBridge | 172:65be27845400 | 401 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
| AnnaBridge | 172:65be27845400 | 402 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
| AnnaBridge | 172:65be27845400 | 403 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
| AnnaBridge | 172:65be27845400 | 404 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
| AnnaBridge | 172:65be27845400 | 405 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
| AnnaBridge | 172:65be27845400 | 406 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
| AnnaBridge | 172:65be27845400 | 407 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
| AnnaBridge | 172:65be27845400 | 408 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
| AnnaBridge | 172:65be27845400 | 409 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
| AnnaBridge | 172:65be27845400 | 410 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
| AnnaBridge | 172:65be27845400 | 411 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
| AnnaBridge | 172:65be27845400 | 412 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
| AnnaBridge | 172:65be27845400 | 413 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
| AnnaBridge | 172:65be27845400 | 414 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
| AnnaBridge | 172:65be27845400 | 415 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
| AnnaBridge | 172:65be27845400 | 416 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
| AnnaBridge | 172:65be27845400 | 417 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
| AnnaBridge | 172:65be27845400 | 418 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
| AnnaBridge | 172:65be27845400 | 419 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
| AnnaBridge | 172:65be27845400 | 420 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
| AnnaBridge | 172:65be27845400 | 421 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
| AnnaBridge | 172:65be27845400 | 422 | |
| AnnaBridge | 172:65be27845400 | 423 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
| AnnaBridge | 172:65be27845400 | 424 | #endif /* __MPU_PRESENT */ |
| AnnaBridge | 172:65be27845400 | 425 | |
| AnnaBridge | 172:65be27845400 | 426 | /** |
| AnnaBridge | 172:65be27845400 | 427 | * @} |
| AnnaBridge | 172:65be27845400 | 428 | */ |
| AnnaBridge | 172:65be27845400 | 429 | |
| AnnaBridge | 172:65be27845400 | 430 | /** |
| AnnaBridge | 172:65be27845400 | 431 | * @} |
| AnnaBridge | 172:65be27845400 | 432 | */ |
| AnnaBridge | 172:65be27845400 | 433 | |
| AnnaBridge | 172:65be27845400 | 434 | /** |
| AnnaBridge | 172:65be27845400 | 435 | * @} |
| AnnaBridge | 172:65be27845400 | 436 | */ |
| AnnaBridge | 172:65be27845400 | 437 | |
| AnnaBridge | 172:65be27845400 | 438 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 439 | } |
| AnnaBridge | 172:65be27845400 | 440 | #endif |
| AnnaBridge | 172:65be27845400 | 441 | |
| AnnaBridge | 172:65be27845400 | 442 | #endif /* STM32H7xx_HAL_CORTEX_H */ |
| AnnaBridge | 172:65be27845400 | 443 | |
| AnnaBridge | 172:65be27845400 | 444 | |
| AnnaBridge | 172:65be27845400 | 445 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
