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TARGET_NUCLEO_H743ZI/TOOLCHAIN_GCC_ARM/stm32h743xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32h743xx.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File.
AnnaBridge 172:65be27845400 6 *
AnnaBridge 172:65be27845400 7 * This file contains:
AnnaBridge 172:65be27845400 8 * - Data structures and the address mapping for all peripherals
AnnaBridge 172:65be27845400 9 * - Peripheral's registers declarations and bits definition
AnnaBridge 172:65be27845400 10 * - Macros to access peripheral's registers hardware
AnnaBridge 172:65be27845400 11 *
AnnaBridge 172:65be27845400 12 ******************************************************************************
AnnaBridge 172:65be27845400 13 * @attention
AnnaBridge 172:65be27845400 14 *
AnnaBridge 172:65be27845400 15 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
AnnaBridge 172:65be27845400 16 * All rights reserved.</center></h2>
AnnaBridge 172:65be27845400 17 *
AnnaBridge 172:65be27845400 18 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 172:65be27845400 19 * the "License"; You may not use this file except in compliance with the
AnnaBridge 172:65be27845400 20 * License. You may obtain a copy of the License at:
AnnaBridge 172:65be27845400 21 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 172:65be27845400 22 *
AnnaBridge 172:65be27845400 23 ******************************************************************************
AnnaBridge 172:65be27845400 24 */
AnnaBridge 172:65be27845400 25
AnnaBridge 172:65be27845400 26 /** @addtogroup CMSIS_Device
AnnaBridge 172:65be27845400 27 * @{
AnnaBridge 172:65be27845400 28 */
AnnaBridge 172:65be27845400 29
AnnaBridge 172:65be27845400 30 /** @addtogroup stm32h743xx
AnnaBridge 172:65be27845400 31 * @{
AnnaBridge 172:65be27845400 32 */
AnnaBridge 172:65be27845400 33
AnnaBridge 172:65be27845400 34 #ifndef STM32H743xx_H
AnnaBridge 172:65be27845400 35 #define STM32H743xx_H
AnnaBridge 172:65be27845400 36
AnnaBridge 172:65be27845400 37 #ifdef __cplusplus
AnnaBridge 172:65be27845400 38 extern "C" {
AnnaBridge 172:65be27845400 39 #endif /* __cplusplus */
AnnaBridge 172:65be27845400 40
AnnaBridge 172:65be27845400 41 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 172:65be27845400 42 * @{
AnnaBridge 172:65be27845400 43 */
AnnaBridge 172:65be27845400 44
AnnaBridge 172:65be27845400 45 /**
AnnaBridge 172:65be27845400 46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
AnnaBridge 172:65be27845400 47 * in @ref Library_configuration_section
AnnaBridge 172:65be27845400 48 */
AnnaBridge 172:65be27845400 49 typedef enum
AnnaBridge 172:65be27845400 50 {
AnnaBridge 172:65be27845400 51 /****** Cortex-M Processor Exceptions Numbers *****************************************************************/
AnnaBridge 172:65be27845400 52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 172:65be27845400 53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
AnnaBridge 172:65be27845400 54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
AnnaBridge 172:65be27845400 55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
AnnaBridge 172:65be27845400 56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
AnnaBridge 172:65be27845400 57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
AnnaBridge 172:65be27845400 58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
AnnaBridge 172:65be27845400 59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
AnnaBridge 172:65be27845400 60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
AnnaBridge 172:65be27845400 61 /****** STM32 specific Interrupt Numbers **********************************************************************/
AnnaBridge 172:65be27845400 62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 172:65be27845400 63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
AnnaBridge 172:65be27845400 64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 172:65be27845400 65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
AnnaBridge 172:65be27845400 66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 172:65be27845400 67 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 172:65be27845400 68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 172:65be27845400 69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 172:65be27845400 70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 172:65be27845400 71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 172:65be27845400 72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 172:65be27845400 73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
AnnaBridge 172:65be27845400 74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
AnnaBridge 172:65be27845400 75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
AnnaBridge 172:65be27845400 76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
AnnaBridge 172:65be27845400 77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
AnnaBridge 172:65be27845400 78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
AnnaBridge 172:65be27845400 79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
AnnaBridge 172:65be27845400 80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
AnnaBridge 172:65be27845400 81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
AnnaBridge 172:65be27845400 82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
AnnaBridge 172:65be27845400 83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
AnnaBridge 172:65be27845400 84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
AnnaBridge 172:65be27845400 85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 172:65be27845400 86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
AnnaBridge 172:65be27845400 87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
AnnaBridge 172:65be27845400 88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
AnnaBridge 172:65be27845400 89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 172:65be27845400 90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 172:65be27845400 91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 172:65be27845400 92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 172:65be27845400 93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 172:65be27845400 94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 172:65be27845400 95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 172:65be27845400 96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 172:65be27845400 97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 172:65be27845400 98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 172:65be27845400 99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 172:65be27845400 100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 172:65be27845400 101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
AnnaBridge 172:65be27845400 102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 172:65be27845400 103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 172:65be27845400 104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
AnnaBridge 172:65be27845400 105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
AnnaBridge 172:65be27845400 106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
AnnaBridge 172:65be27845400 107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
AnnaBridge 172:65be27845400 108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
AnnaBridge 172:65be27845400 109 FMC_IRQn = 48, /*!< FMC global Interrupt */
AnnaBridge 172:65be27845400 110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
AnnaBridge 172:65be27845400 111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
AnnaBridge 172:65be27845400 112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
AnnaBridge 172:65be27845400 113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
AnnaBridge 172:65be27845400 114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
AnnaBridge 172:65be27845400 115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
AnnaBridge 172:65be27845400 116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
AnnaBridge 172:65be27845400 117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
AnnaBridge 172:65be27845400 118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
AnnaBridge 172:65be27845400 119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
AnnaBridge 172:65be27845400 120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
AnnaBridge 172:65be27845400 121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
AnnaBridge 172:65be27845400 122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
AnnaBridge 172:65be27845400 123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
AnnaBridge 172:65be27845400 124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
AnnaBridge 172:65be27845400 125 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
AnnaBridge 172:65be27845400 126 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
AnnaBridge 172:65be27845400 127 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
AnnaBridge 172:65be27845400 128 USART6_IRQn = 71, /*!< USART6 global interrupt */
AnnaBridge 172:65be27845400 129 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
AnnaBridge 172:65be27845400 130 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
AnnaBridge 172:65be27845400 131 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
AnnaBridge 172:65be27845400 132 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
AnnaBridge 172:65be27845400 133 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
AnnaBridge 172:65be27845400 134 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
AnnaBridge 172:65be27845400 135 DCMI_IRQn = 78, /*!< DCMI global interrupt */
AnnaBridge 172:65be27845400 136 RNG_IRQn = 80, /*!< RNG global interrupt */
AnnaBridge 172:65be27845400 137 FPU_IRQn = 81, /*!< FPU global interrupt */
AnnaBridge 172:65be27845400 138 UART7_IRQn = 82, /*!< UART7 global interrupt */
AnnaBridge 172:65be27845400 139 UART8_IRQn = 83, /*!< UART8 global interrupt */
AnnaBridge 172:65be27845400 140 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
AnnaBridge 172:65be27845400 141 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
AnnaBridge 172:65be27845400 142 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
AnnaBridge 172:65be27845400 143 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
AnnaBridge 172:65be27845400 144 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
AnnaBridge 172:65be27845400 145 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
AnnaBridge 172:65be27845400 146 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
AnnaBridge 172:65be27845400 147 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
AnnaBridge 172:65be27845400 148 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
AnnaBridge 172:65be27845400 149 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
AnnaBridge 172:65be27845400 150 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
AnnaBridge 172:65be27845400 151 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
AnnaBridge 172:65be27845400 152 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
AnnaBridge 172:65be27845400 153 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
AnnaBridge 172:65be27845400 154 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
AnnaBridge 172:65be27845400 155 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
AnnaBridge 172:65be27845400 156 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
AnnaBridge 172:65be27845400 157 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
AnnaBridge 172:65be27845400 158 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
AnnaBridge 172:65be27845400 159 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
AnnaBridge 172:65be27845400 160 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
AnnaBridge 172:65be27845400 161 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
AnnaBridge 172:65be27845400 162 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
AnnaBridge 172:65be27845400 163 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
AnnaBridge 172:65be27845400 164 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
AnnaBridge 172:65be27845400 165 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
AnnaBridge 172:65be27845400 166 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
AnnaBridge 172:65be27845400 167 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
AnnaBridge 172:65be27845400 168 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
AnnaBridge 172:65be27845400 169 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
AnnaBridge 172:65be27845400 170 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
AnnaBridge 172:65be27845400 171 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
AnnaBridge 172:65be27845400 172 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
AnnaBridge 172:65be27845400 173 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
AnnaBridge 172:65be27845400 174 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
AnnaBridge 172:65be27845400 175 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
AnnaBridge 172:65be27845400 176 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
AnnaBridge 172:65be27845400 177 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
AnnaBridge 172:65be27845400 178 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
AnnaBridge 172:65be27845400 179 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
AnnaBridge 172:65be27845400 180 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
AnnaBridge 172:65be27845400 181 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
AnnaBridge 172:65be27845400 182 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
AnnaBridge 172:65be27845400 183 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
AnnaBridge 172:65be27845400 184 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
AnnaBridge 172:65be27845400 185 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
AnnaBridge 172:65be27845400 186 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
AnnaBridge 172:65be27845400 187 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
AnnaBridge 172:65be27845400 188 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
AnnaBridge 172:65be27845400 189 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
AnnaBridge 172:65be27845400 190 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
AnnaBridge 172:65be27845400 191 COMP_IRQn = 137 , /*!< COMP global Interrupt */
AnnaBridge 172:65be27845400 192 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
AnnaBridge 172:65be27845400 193 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
AnnaBridge 172:65be27845400 194 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
AnnaBridge 172:65be27845400 195 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
AnnaBridge 172:65be27845400 196 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
AnnaBridge 172:65be27845400 197 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
AnnaBridge 172:65be27845400 198 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
AnnaBridge 172:65be27845400 199 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
AnnaBridge 172:65be27845400 200 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
AnnaBridge 172:65be27845400 201 } IRQn_Type;
AnnaBridge 172:65be27845400 202
AnnaBridge 172:65be27845400 203 /**
AnnaBridge 172:65be27845400 204 * @}
AnnaBridge 172:65be27845400 205 */
AnnaBridge 172:65be27845400 206
AnnaBridge 172:65be27845400 207 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 172:65be27845400 208 * @{
AnnaBridge 172:65be27845400 209 */
AnnaBridge 172:65be27845400 210
AnnaBridge 172:65be27845400 211
AnnaBridge 172:65be27845400 212
AnnaBridge 172:65be27845400 213
AnnaBridge 172:65be27845400 214 /**
AnnaBridge 172:65be27845400 215 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
AnnaBridge 172:65be27845400 216 */
AnnaBridge 172:65be27845400 217 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
AnnaBridge 172:65be27845400 218 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
AnnaBridge 172:65be27845400 219 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
AnnaBridge 172:65be27845400 220 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 172:65be27845400 221 #define __FPU_PRESENT 1 /*!< FPU present */
AnnaBridge 172:65be27845400 222 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
AnnaBridge 172:65be27845400 223 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
AnnaBridge 172:65be27845400 224 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
AnnaBridge 172:65be27845400 225
AnnaBridge 172:65be27845400 226 /**
AnnaBridge 172:65be27845400 227 * @}
AnnaBridge 172:65be27845400 228 */
AnnaBridge 172:65be27845400 229
AnnaBridge 172:65be27845400 230
AnnaBridge 172:65be27845400 231
AnnaBridge 172:65be27845400 232
AnnaBridge 172:65be27845400 233 #include "system_stm32h7xx.h"
AnnaBridge 172:65be27845400 234 #include <stdint.h>
AnnaBridge 172:65be27845400 235
AnnaBridge 172:65be27845400 236 /** @addtogroup Peripheral_registers_structures
AnnaBridge 172:65be27845400 237 * @{
AnnaBridge 172:65be27845400 238 */
AnnaBridge 172:65be27845400 239
AnnaBridge 172:65be27845400 240 /**
AnnaBridge 172:65be27845400 241 * @brief Analog to Digital Converter
AnnaBridge 172:65be27845400 242 */
AnnaBridge 172:65be27845400 243
AnnaBridge 172:65be27845400 244 typedef struct
AnnaBridge 172:65be27845400 245 {
AnnaBridge 172:65be27845400 246 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 247 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 248 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 249 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 250 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
AnnaBridge 172:65be27845400 251 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
AnnaBridge 172:65be27845400 252 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
AnnaBridge 172:65be27845400 253 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
AnnaBridge 172:65be27845400 254 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
AnnaBridge 172:65be27845400 255 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
AnnaBridge 172:65be27845400 256 uint32_t RESERVED1; /*!< Reserved, 0x028 */
AnnaBridge 172:65be27845400 257 uint32_t RESERVED2; /*!< Reserved, 0x02C */
AnnaBridge 172:65be27845400 258 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
AnnaBridge 172:65be27845400 259 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
AnnaBridge 172:65be27845400 260 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
AnnaBridge 172:65be27845400 261 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
AnnaBridge 172:65be27845400 262 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 263 uint32_t RESERVED3; /*!< Reserved, 0x044 */
AnnaBridge 172:65be27845400 264 uint32_t RESERVED4; /*!< Reserved, 0x048 */
AnnaBridge 172:65be27845400 265 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 266 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
AnnaBridge 172:65be27845400 267 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
AnnaBridge 172:65be27845400 268 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
AnnaBridge 172:65be27845400 269 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
AnnaBridge 172:65be27845400 270 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
AnnaBridge 172:65be27845400 271 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
AnnaBridge 172:65be27845400 272 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
AnnaBridge 172:65be27845400 273 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
AnnaBridge 172:65be27845400 274 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
AnnaBridge 172:65be27845400 275 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
AnnaBridge 172:65be27845400 276 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
AnnaBridge 172:65be27845400 277 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
AnnaBridge 172:65be27845400 278 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
AnnaBridge 172:65be27845400 279 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
AnnaBridge 172:65be27845400 280 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
AnnaBridge 172:65be27845400 281 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
AnnaBridge 172:65be27845400 282 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
AnnaBridge 172:65be27845400 283 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
AnnaBridge 172:65be27845400 284 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
AnnaBridge 172:65be27845400 285 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
AnnaBridge 172:65be27845400 286 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
AnnaBridge 172:65be27845400 287 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
AnnaBridge 172:65be27845400 288 } ADC_TypeDef;
AnnaBridge 172:65be27845400 289
AnnaBridge 172:65be27845400 290
AnnaBridge 172:65be27845400 291 typedef struct
AnnaBridge 172:65be27845400 292 {
AnnaBridge 172:65be27845400 293 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
AnnaBridge 172:65be27845400 294 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
AnnaBridge 172:65be27845400 295 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
AnnaBridge 172:65be27845400 296 __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
AnnaBridge 172:65be27845400 297 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
AnnaBridge 172:65be27845400 298
AnnaBridge 172:65be27845400 299 } ADC_Common_TypeDef;
AnnaBridge 172:65be27845400 300
AnnaBridge 172:65be27845400 301 /**
AnnaBridge 172:65be27845400 302 * @brief VREFBUF
AnnaBridge 172:65be27845400 303 */
AnnaBridge 172:65be27845400 304
AnnaBridge 172:65be27845400 305 typedef struct
AnnaBridge 172:65be27845400 306 {
AnnaBridge 172:65be27845400 307 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 308 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 309 } VREFBUF_TypeDef;
AnnaBridge 172:65be27845400 310
AnnaBridge 172:65be27845400 311
AnnaBridge 172:65be27845400 312 /**
AnnaBridge 172:65be27845400 313 * @brief FD Controller Area Network
AnnaBridge 172:65be27845400 314 */
AnnaBridge 172:65be27845400 315
AnnaBridge 172:65be27845400 316 typedef struct
AnnaBridge 172:65be27845400 317 {
AnnaBridge 172:65be27845400 318 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
AnnaBridge 172:65be27845400 319 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
AnnaBridge 172:65be27845400 320 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
AnnaBridge 172:65be27845400 321 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
AnnaBridge 172:65be27845400 322 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
AnnaBridge 172:65be27845400 323 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
AnnaBridge 172:65be27845400 324 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
AnnaBridge 172:65be27845400 325 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
AnnaBridge 172:65be27845400 326 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
AnnaBridge 172:65be27845400 327 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
AnnaBridge 172:65be27845400 328 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
AnnaBridge 172:65be27845400 329 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
AnnaBridge 172:65be27845400 330 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
AnnaBridge 172:65be27845400 331 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
AnnaBridge 172:65be27845400 332 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
AnnaBridge 172:65be27845400 333 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
AnnaBridge 172:65be27845400 334 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
AnnaBridge 172:65be27845400 335 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
AnnaBridge 172:65be27845400 336 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
AnnaBridge 172:65be27845400 337 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
AnnaBridge 172:65be27845400 338 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
AnnaBridge 172:65be27845400 339 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
AnnaBridge 172:65be27845400 340 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
AnnaBridge 172:65be27845400 341 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
AnnaBridge 172:65be27845400 342 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
AnnaBridge 172:65be27845400 343 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
AnnaBridge 172:65be27845400 344 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
AnnaBridge 172:65be27845400 345 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
AnnaBridge 172:65be27845400 346 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
AnnaBridge 172:65be27845400 347 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
AnnaBridge 172:65be27845400 348 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
AnnaBridge 172:65be27845400 349 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
AnnaBridge 172:65be27845400 350 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
AnnaBridge 172:65be27845400 351 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
AnnaBridge 172:65be27845400 352 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
AnnaBridge 172:65be27845400 353 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
AnnaBridge 172:65be27845400 354 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
AnnaBridge 172:65be27845400 355 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
AnnaBridge 172:65be27845400 356 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
AnnaBridge 172:65be27845400 357 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
AnnaBridge 172:65be27845400 358 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
AnnaBridge 172:65be27845400 359 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
AnnaBridge 172:65be27845400 360 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
AnnaBridge 172:65be27845400 361 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
AnnaBridge 172:65be27845400 362 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
AnnaBridge 172:65be27845400 363 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
AnnaBridge 172:65be27845400 364 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
AnnaBridge 172:65be27845400 365 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
AnnaBridge 172:65be27845400 366 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
AnnaBridge 172:65be27845400 367 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
AnnaBridge 172:65be27845400 368 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
AnnaBridge 172:65be27845400 369 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
AnnaBridge 172:65be27845400 370 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
AnnaBridge 172:65be27845400 371 } FDCAN_GlobalTypeDef;
AnnaBridge 172:65be27845400 372
AnnaBridge 172:65be27845400 373 /**
AnnaBridge 172:65be27845400 374 * @brief TTFD Controller Area Network
AnnaBridge 172:65be27845400 375 */
AnnaBridge 172:65be27845400 376
AnnaBridge 172:65be27845400 377 typedef struct
AnnaBridge 172:65be27845400 378 {
AnnaBridge 172:65be27845400 379 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
AnnaBridge 172:65be27845400 380 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
AnnaBridge 172:65be27845400 381 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
AnnaBridge 172:65be27845400 382 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
AnnaBridge 172:65be27845400 383 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
AnnaBridge 172:65be27845400 384 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
AnnaBridge 172:65be27845400 385 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
AnnaBridge 172:65be27845400 386 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
AnnaBridge 172:65be27845400 387 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
AnnaBridge 172:65be27845400 388 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
AnnaBridge 172:65be27845400 389 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
AnnaBridge 172:65be27845400 390 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
AnnaBridge 172:65be27845400 391 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
AnnaBridge 172:65be27845400 392 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
AnnaBridge 172:65be27845400 393 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
AnnaBridge 172:65be27845400 394 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
AnnaBridge 172:65be27845400 395 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
AnnaBridge 172:65be27845400 396 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
AnnaBridge 172:65be27845400 397 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
AnnaBridge 172:65be27845400 398 } TTCAN_TypeDef;
AnnaBridge 172:65be27845400 399
AnnaBridge 172:65be27845400 400 /**
AnnaBridge 172:65be27845400 401 * @brief FD Controller Area Network
AnnaBridge 172:65be27845400 402 */
AnnaBridge 172:65be27845400 403
AnnaBridge 172:65be27845400 404 typedef struct
AnnaBridge 172:65be27845400 405 {
AnnaBridge 172:65be27845400 406 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 407 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 408 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 409 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 410 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 411 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 412 } FDCAN_ClockCalibrationUnit_TypeDef;
AnnaBridge 172:65be27845400 413
AnnaBridge 172:65be27845400 414
AnnaBridge 172:65be27845400 415 /**
AnnaBridge 172:65be27845400 416 * @brief Consumer Electronics Control
AnnaBridge 172:65be27845400 417 */
AnnaBridge 172:65be27845400 418
AnnaBridge 172:65be27845400 419 typedef struct
AnnaBridge 172:65be27845400 420 {
AnnaBridge 172:65be27845400 421 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
AnnaBridge 172:65be27845400 422 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
AnnaBridge 172:65be27845400 423 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
AnnaBridge 172:65be27845400 424 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
AnnaBridge 172:65be27845400 425 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
AnnaBridge 172:65be27845400 426 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
AnnaBridge 172:65be27845400 427 }CEC_TypeDef;
AnnaBridge 172:65be27845400 428
AnnaBridge 172:65be27845400 429 /**
AnnaBridge 172:65be27845400 430 * @brief CRC calculation unit
AnnaBridge 172:65be27845400 431 */
AnnaBridge 172:65be27845400 432
AnnaBridge 172:65be27845400 433 typedef struct
AnnaBridge 172:65be27845400 434 {
AnnaBridge 172:65be27845400 435 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 436 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 437 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 438 uint32_t RESERVED2; /*!< Reserved, 0x0C */
AnnaBridge 172:65be27845400 439 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 440 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 441 } CRC_TypeDef;
AnnaBridge 172:65be27845400 442
AnnaBridge 172:65be27845400 443
AnnaBridge 172:65be27845400 444 /**
AnnaBridge 172:65be27845400 445 * @brief Clock Recovery System
AnnaBridge 172:65be27845400 446 */
AnnaBridge 172:65be27845400 447 typedef struct
AnnaBridge 172:65be27845400 448 {
AnnaBridge 172:65be27845400 449 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 450 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 451 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 452 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 453 } CRS_TypeDef;
AnnaBridge 172:65be27845400 454
AnnaBridge 172:65be27845400 455
AnnaBridge 172:65be27845400 456 /**
AnnaBridge 172:65be27845400 457 * @brief Digital to Analog Converter
AnnaBridge 172:65be27845400 458 */
AnnaBridge 172:65be27845400 459
AnnaBridge 172:65be27845400 460 typedef struct
AnnaBridge 172:65be27845400 461 {
AnnaBridge 172:65be27845400 462 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 463 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 464 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 465 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 466 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 467 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 468 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 469 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 470 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 471 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 472 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 473 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 474 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 475 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 476 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 477 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 478 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
AnnaBridge 172:65be27845400 479 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
AnnaBridge 172:65be27845400 480 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 481 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 482 } DAC_TypeDef;
AnnaBridge 172:65be27845400 483
AnnaBridge 172:65be27845400 484 /**
AnnaBridge 172:65be27845400 485 * @brief DFSDM module registers
AnnaBridge 172:65be27845400 486 */
AnnaBridge 172:65be27845400 487 typedef struct
AnnaBridge 172:65be27845400 488 {
AnnaBridge 172:65be27845400 489 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
AnnaBridge 172:65be27845400 490 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
AnnaBridge 172:65be27845400 491 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
AnnaBridge 172:65be27845400 492 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
AnnaBridge 172:65be27845400 493 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
AnnaBridge 172:65be27845400 494 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
AnnaBridge 172:65be27845400 495 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
AnnaBridge 172:65be27845400 496 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
AnnaBridge 172:65be27845400 497 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
AnnaBridge 172:65be27845400 498 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
AnnaBridge 172:65be27845400 499 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
AnnaBridge 172:65be27845400 500 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
AnnaBridge 172:65be27845400 501 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
AnnaBridge 172:65be27845400 502 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
AnnaBridge 172:65be27845400 503 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
AnnaBridge 172:65be27845400 504 } DFSDM_Filter_TypeDef;
AnnaBridge 172:65be27845400 505
AnnaBridge 172:65be27845400 506 /**
AnnaBridge 172:65be27845400 507 * @brief DFSDM channel configuration registers
AnnaBridge 172:65be27845400 508 */
AnnaBridge 172:65be27845400 509 typedef struct
AnnaBridge 172:65be27845400 510 {
AnnaBridge 172:65be27845400 511 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 512 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 513 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
AnnaBridge 172:65be27845400 514 short circuit detector register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 515 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 516 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 517 } DFSDM_Channel_TypeDef;
AnnaBridge 172:65be27845400 518
AnnaBridge 172:65be27845400 519 /**
AnnaBridge 172:65be27845400 520 * @brief Debug MCU
AnnaBridge 172:65be27845400 521 */
AnnaBridge 172:65be27845400 522 typedef struct
AnnaBridge 172:65be27845400 523 {
AnnaBridge 172:65be27845400 524 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 172:65be27845400 525 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 526 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
AnnaBridge 172:65be27845400 527 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 528 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
AnnaBridge 172:65be27845400 529 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 530 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
AnnaBridge 172:65be27845400 531 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 532 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
AnnaBridge 172:65be27845400 533 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 534 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
AnnaBridge 172:65be27845400 535 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
AnnaBridge 172:65be27845400 536 }DBGMCU_TypeDef;
AnnaBridge 172:65be27845400 537 /**
AnnaBridge 172:65be27845400 538 * @brief DCMI
AnnaBridge 172:65be27845400 539 */
AnnaBridge 172:65be27845400 540
AnnaBridge 172:65be27845400 541 typedef struct
AnnaBridge 172:65be27845400 542 {
AnnaBridge 172:65be27845400 543 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 544 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 545 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 546 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 547 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 548 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 549 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 550 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 551 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
AnnaBridge 172:65be27845400 552 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
AnnaBridge 172:65be27845400 553 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 554 } DCMI_TypeDef;
AnnaBridge 172:65be27845400 555
AnnaBridge 172:65be27845400 556 /**
AnnaBridge 172:65be27845400 557 * @brief DMA Controller
AnnaBridge 172:65be27845400 558 */
AnnaBridge 172:65be27845400 559
AnnaBridge 172:65be27845400 560 typedef struct
AnnaBridge 172:65be27845400 561 {
AnnaBridge 172:65be27845400 562 __IO uint32_t CR; /*!< DMA stream x configuration register */
AnnaBridge 172:65be27845400 563 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
AnnaBridge 172:65be27845400 564 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
AnnaBridge 172:65be27845400 565 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
AnnaBridge 172:65be27845400 566 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
AnnaBridge 172:65be27845400 567 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
AnnaBridge 172:65be27845400 568 } DMA_Stream_TypeDef;
AnnaBridge 172:65be27845400 569
AnnaBridge 172:65be27845400 570 typedef struct
AnnaBridge 172:65be27845400 571 {
AnnaBridge 172:65be27845400 572 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 573 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 574 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 575 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 576 } DMA_TypeDef;
AnnaBridge 172:65be27845400 577
AnnaBridge 172:65be27845400 578 typedef struct
AnnaBridge 172:65be27845400 579 {
AnnaBridge 172:65be27845400 580 __IO uint32_t CCR; /*!< DMA channel x configuration register */
AnnaBridge 172:65be27845400 581 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
AnnaBridge 172:65be27845400 582 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
AnnaBridge 172:65be27845400 583 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
AnnaBridge 172:65be27845400 584 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
AnnaBridge 172:65be27845400 585 } BDMA_Channel_TypeDef;
AnnaBridge 172:65be27845400 586
AnnaBridge 172:65be27845400 587 typedef struct
AnnaBridge 172:65be27845400 588 {
AnnaBridge 172:65be27845400 589 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 590 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 591 } BDMA_TypeDef;
AnnaBridge 172:65be27845400 592
AnnaBridge 172:65be27845400 593 typedef struct
AnnaBridge 172:65be27845400 594 {
AnnaBridge 172:65be27845400 595 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
AnnaBridge 172:65be27845400 596 }DMAMUX_Channel_TypeDef;
AnnaBridge 172:65be27845400 597
AnnaBridge 172:65be27845400 598 typedef struct
AnnaBridge 172:65be27845400 599 {
AnnaBridge 172:65be27845400 600 __IO uint32_t CSR; /*!< DMA Channel Status Register */
AnnaBridge 172:65be27845400 601 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
AnnaBridge 172:65be27845400 602 }DMAMUX_ChannelStatus_TypeDef;
AnnaBridge 172:65be27845400 603
AnnaBridge 172:65be27845400 604 typedef struct
AnnaBridge 172:65be27845400 605 {
AnnaBridge 172:65be27845400 606 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
AnnaBridge 172:65be27845400 607 }DMAMUX_RequestGen_TypeDef;
AnnaBridge 172:65be27845400 608
AnnaBridge 172:65be27845400 609 typedef struct
AnnaBridge 172:65be27845400 610 {
AnnaBridge 172:65be27845400 611 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
AnnaBridge 172:65be27845400 612 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
AnnaBridge 172:65be27845400 613 }DMAMUX_RequestGenStatus_TypeDef;
AnnaBridge 172:65be27845400 614
AnnaBridge 172:65be27845400 615 /**
AnnaBridge 172:65be27845400 616 * @brief MDMA Controller
AnnaBridge 172:65be27845400 617 */
AnnaBridge 172:65be27845400 618 typedef struct
AnnaBridge 172:65be27845400 619 {
AnnaBridge 172:65be27845400 620 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
AnnaBridge 172:65be27845400 621 }MDMA_TypeDef;
AnnaBridge 172:65be27845400 622
AnnaBridge 172:65be27845400 623 typedef struct
AnnaBridge 172:65be27845400 624 {
AnnaBridge 172:65be27845400 625 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 626 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 627 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 628 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 629 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
AnnaBridge 172:65be27845400 630 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
AnnaBridge 172:65be27845400 631 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
AnnaBridge 172:65be27845400 632 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
AnnaBridge 172:65be27845400 633 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
AnnaBridge 172:65be27845400 634 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
AnnaBridge 172:65be27845400 635 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
AnnaBridge 172:65be27845400 636 uint32_t RESERVED0; /*!< Reserved, 0x68 */
AnnaBridge 172:65be27845400 637 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
AnnaBridge 172:65be27845400 638 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
AnnaBridge 172:65be27845400 639 }MDMA_Channel_TypeDef;
AnnaBridge 172:65be27845400 640
AnnaBridge 172:65be27845400 641 /**
AnnaBridge 172:65be27845400 642 * @brief DMA2D Controller
AnnaBridge 172:65be27845400 643 */
AnnaBridge 172:65be27845400 644
AnnaBridge 172:65be27845400 645 typedef struct
AnnaBridge 172:65be27845400 646 {
AnnaBridge 172:65be27845400 647 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 648 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 649 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 650 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 651 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 652 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 653 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 654 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 655 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 656 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 657 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 658 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 659 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 660 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 661 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 662 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 663 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 664 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 665 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 666 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 667 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
AnnaBridge 172:65be27845400 668 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
AnnaBridge 172:65be27845400 669 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
AnnaBridge 172:65be27845400 670 } DMA2D_TypeDef;
AnnaBridge 172:65be27845400 671
AnnaBridge 172:65be27845400 672
AnnaBridge 172:65be27845400 673 /**
AnnaBridge 172:65be27845400 674 * @brief Ethernet MAC
AnnaBridge 172:65be27845400 675 */
AnnaBridge 172:65be27845400 676 typedef struct
AnnaBridge 172:65be27845400 677 {
AnnaBridge 172:65be27845400 678 __IO uint32_t MACCR;
AnnaBridge 172:65be27845400 679 __IO uint32_t MACECR;
AnnaBridge 172:65be27845400 680 __IO uint32_t MACPFR;
AnnaBridge 172:65be27845400 681 __IO uint32_t MACWTR;
AnnaBridge 172:65be27845400 682 __IO uint32_t MACHT0R;
AnnaBridge 172:65be27845400 683 __IO uint32_t MACHT1R;
AnnaBridge 172:65be27845400 684 uint32_t RESERVED1[14];
AnnaBridge 172:65be27845400 685 __IO uint32_t MACVTR;
AnnaBridge 172:65be27845400 686 uint32_t RESERVED2;
AnnaBridge 172:65be27845400 687 __IO uint32_t MACVHTR;
AnnaBridge 172:65be27845400 688 uint32_t RESERVED3;
AnnaBridge 172:65be27845400 689 __IO uint32_t MACVIR;
AnnaBridge 172:65be27845400 690 __IO uint32_t MACIVIR;
AnnaBridge 172:65be27845400 691 uint32_t RESERVED4[2];
AnnaBridge 172:65be27845400 692 __IO uint32_t MACTFCR;
AnnaBridge 172:65be27845400 693 uint32_t RESERVED5[7];
AnnaBridge 172:65be27845400 694 __IO uint32_t MACRFCR;
AnnaBridge 172:65be27845400 695 uint32_t RESERVED6[7];
AnnaBridge 172:65be27845400 696 __IO uint32_t MACISR;
AnnaBridge 172:65be27845400 697 __IO uint32_t MACIER;
AnnaBridge 172:65be27845400 698 __IO uint32_t MACRXTXSR;
AnnaBridge 172:65be27845400 699 uint32_t RESERVED7;
AnnaBridge 172:65be27845400 700 __IO uint32_t MACPCSR;
AnnaBridge 172:65be27845400 701 __IO uint32_t MACRWKPFR;
AnnaBridge 172:65be27845400 702 uint32_t RESERVED8[2];
AnnaBridge 172:65be27845400 703 __IO uint32_t MACLCSR;
AnnaBridge 172:65be27845400 704 __IO uint32_t MACLTCR;
AnnaBridge 172:65be27845400 705 __IO uint32_t MACLETR;
AnnaBridge 172:65be27845400 706 __IO uint32_t MAC1USTCR;
AnnaBridge 172:65be27845400 707 uint32_t RESERVED9[12];
AnnaBridge 172:65be27845400 708 __IO uint32_t MACVR;
AnnaBridge 172:65be27845400 709 __IO uint32_t MACDR;
AnnaBridge 172:65be27845400 710 uint32_t RESERVED10;
AnnaBridge 172:65be27845400 711 __IO uint32_t MACHWF0R;
AnnaBridge 172:65be27845400 712 __IO uint32_t MACHWF1R;
AnnaBridge 172:65be27845400 713 __IO uint32_t MACHWF2R;
AnnaBridge 172:65be27845400 714 uint32_t RESERVED11[54];
AnnaBridge 172:65be27845400 715 __IO uint32_t MACMDIOAR;
AnnaBridge 172:65be27845400 716 __IO uint32_t MACMDIODR;
AnnaBridge 172:65be27845400 717 uint32_t RESERVED12[2];
AnnaBridge 172:65be27845400 718 __IO uint32_t MACARPAR;
AnnaBridge 172:65be27845400 719 uint32_t RESERVED13[59];
AnnaBridge 172:65be27845400 720 __IO uint32_t MACA0HR;
AnnaBridge 172:65be27845400 721 __IO uint32_t MACA0LR;
AnnaBridge 172:65be27845400 722 __IO uint32_t MACA1HR;
AnnaBridge 172:65be27845400 723 __IO uint32_t MACA1LR;
AnnaBridge 172:65be27845400 724 __IO uint32_t MACA2HR;
AnnaBridge 172:65be27845400 725 __IO uint32_t MACA2LR;
AnnaBridge 172:65be27845400 726 __IO uint32_t MACA3HR;
AnnaBridge 172:65be27845400 727 __IO uint32_t MACA3LR;
AnnaBridge 172:65be27845400 728 uint32_t RESERVED14[248];
AnnaBridge 172:65be27845400 729 __IO uint32_t MMCCR;
AnnaBridge 172:65be27845400 730 __IO uint32_t MMCRIR;
AnnaBridge 172:65be27845400 731 __IO uint32_t MMCTIR;
AnnaBridge 172:65be27845400 732 __IO uint32_t MMCRIMR;
AnnaBridge 172:65be27845400 733 __IO uint32_t MMCTIMR;
AnnaBridge 172:65be27845400 734 uint32_t RESERVED15[14];
AnnaBridge 172:65be27845400 735 __IO uint32_t MMCTSCGPR;
AnnaBridge 172:65be27845400 736 __IO uint32_t MMCTMCGPR;
AnnaBridge 172:65be27845400 737 int32_t RESERVED16[5];
AnnaBridge 172:65be27845400 738 __IO uint32_t MMCTPCGR;
AnnaBridge 172:65be27845400 739 uint32_t RESERVED17[10];
AnnaBridge 172:65be27845400 740 __IO uint32_t MMCRCRCEPR;
AnnaBridge 172:65be27845400 741 __IO uint32_t MMCRAEPR;
AnnaBridge 172:65be27845400 742 uint32_t RESERVED18[10];
AnnaBridge 172:65be27845400 743 __IO uint32_t MMCRUPGR;
AnnaBridge 172:65be27845400 744 uint32_t RESERVED19[9];
AnnaBridge 172:65be27845400 745 __IO uint32_t MMCTLPIMSTR;
AnnaBridge 172:65be27845400 746 __IO uint32_t MMCTLPITCR;
AnnaBridge 172:65be27845400 747 __IO uint32_t MMCRLPIMSTR;
AnnaBridge 172:65be27845400 748 __IO uint32_t MMCRLPITCR;
AnnaBridge 172:65be27845400 749 uint32_t RESERVED20[65];
AnnaBridge 172:65be27845400 750 __IO uint32_t MACL3L4C0R;
AnnaBridge 172:65be27845400 751 __IO uint32_t MACL4A0R;
AnnaBridge 172:65be27845400 752 uint32_t RESERVED21[2];
AnnaBridge 172:65be27845400 753 __IO uint32_t MACL3A0R0R;
AnnaBridge 172:65be27845400 754 __IO uint32_t MACL3A1R0R;
AnnaBridge 172:65be27845400 755 __IO uint32_t MACL3A2R0R;
AnnaBridge 172:65be27845400 756 __IO uint32_t MACL3A3R0R;
AnnaBridge 172:65be27845400 757 uint32_t RESERVED22[4];
AnnaBridge 172:65be27845400 758 __IO uint32_t MACL3L4C1R;
AnnaBridge 172:65be27845400 759 __IO uint32_t MACL4A1R;
AnnaBridge 172:65be27845400 760 uint32_t RESERVED23[2];
AnnaBridge 172:65be27845400 761 __IO uint32_t MACL3A0R1R;
AnnaBridge 172:65be27845400 762 __IO uint32_t MACL3A1R1R;
AnnaBridge 172:65be27845400 763 __IO uint32_t MACL3A2R1R;
AnnaBridge 172:65be27845400 764 __IO uint32_t MACL3A3R1R;
AnnaBridge 172:65be27845400 765 uint32_t RESERVED24[108];
AnnaBridge 172:65be27845400 766 __IO uint32_t MACTSCR;
AnnaBridge 172:65be27845400 767 __IO uint32_t MACSSIR;
AnnaBridge 172:65be27845400 768 __IO uint32_t MACSTSR;
AnnaBridge 172:65be27845400 769 __IO uint32_t MACSTNR;
AnnaBridge 172:65be27845400 770 __IO uint32_t MACSTSUR;
AnnaBridge 172:65be27845400 771 __IO uint32_t MACSTNUR;
AnnaBridge 172:65be27845400 772 __IO uint32_t MACTSAR;
AnnaBridge 172:65be27845400 773 uint32_t RESERVED25;
AnnaBridge 172:65be27845400 774 __IO uint32_t MACTSSR;
AnnaBridge 172:65be27845400 775 uint32_t RESERVED26[3];
AnnaBridge 172:65be27845400 776 __IO uint32_t MACTTSSNR;
AnnaBridge 172:65be27845400 777 __IO uint32_t MACTTSSSR;
AnnaBridge 172:65be27845400 778 uint32_t RESERVED27[2];
AnnaBridge 172:65be27845400 779 __IO uint32_t MACACR;
AnnaBridge 172:65be27845400 780 uint32_t RESERVED28;
AnnaBridge 172:65be27845400 781 __IO uint32_t MACATSNR;
AnnaBridge 172:65be27845400 782 __IO uint32_t MACATSSR;
AnnaBridge 172:65be27845400 783 __IO uint32_t MACTSIACR;
AnnaBridge 172:65be27845400 784 __IO uint32_t MACTSEACR;
AnnaBridge 172:65be27845400 785 __IO uint32_t MACTSICNR;
AnnaBridge 172:65be27845400 786 __IO uint32_t MACTSECNR;
AnnaBridge 172:65be27845400 787 uint32_t RESERVED29[4];
AnnaBridge 172:65be27845400 788 __IO uint32_t MACPPSCR;
AnnaBridge 172:65be27845400 789 uint32_t RESERVED30[3];
AnnaBridge 172:65be27845400 790 __IO uint32_t MACPPSTTSR;
AnnaBridge 172:65be27845400 791 __IO uint32_t MACPPSTTNR;
AnnaBridge 172:65be27845400 792 __IO uint32_t MACPPSIR;
AnnaBridge 172:65be27845400 793 __IO uint32_t MACPPSWR;
AnnaBridge 172:65be27845400 794 uint32_t RESERVED31[12];
AnnaBridge 172:65be27845400 795 __IO uint32_t MACPOCR;
AnnaBridge 172:65be27845400 796 __IO uint32_t MACSPI0R;
AnnaBridge 172:65be27845400 797 __IO uint32_t MACSPI1R;
AnnaBridge 172:65be27845400 798 __IO uint32_t MACSPI2R;
AnnaBridge 172:65be27845400 799 __IO uint32_t MACLMIR;
AnnaBridge 172:65be27845400 800 uint32_t RESERVED32[11];
AnnaBridge 172:65be27845400 801 __IO uint32_t MTLOMR;
AnnaBridge 172:65be27845400 802 uint32_t RESERVED33[7];
AnnaBridge 172:65be27845400 803 __IO uint32_t MTLISR;
AnnaBridge 172:65be27845400 804 uint32_t RESERVED34[55];
AnnaBridge 172:65be27845400 805 __IO uint32_t MTLTQOMR;
AnnaBridge 172:65be27845400 806 __IO uint32_t MTLTQUR;
AnnaBridge 172:65be27845400 807 __IO uint32_t MTLTQDR;
AnnaBridge 172:65be27845400 808 uint32_t RESERVED35[8];
AnnaBridge 172:65be27845400 809 __IO uint32_t MTLQICSR;
AnnaBridge 172:65be27845400 810 __IO uint32_t MTLRQOMR;
AnnaBridge 172:65be27845400 811 __IO uint32_t MTLRQMPOCR;
AnnaBridge 172:65be27845400 812 __IO uint32_t MTLRQDR;
AnnaBridge 172:65be27845400 813 uint32_t RESERVED36[177];
AnnaBridge 172:65be27845400 814 __IO uint32_t DMAMR;
AnnaBridge 172:65be27845400 815 __IO uint32_t DMASBMR;
AnnaBridge 172:65be27845400 816 __IO uint32_t DMAISR;
AnnaBridge 172:65be27845400 817 __IO uint32_t DMADSR;
AnnaBridge 172:65be27845400 818 uint32_t RESERVED37[60];
AnnaBridge 172:65be27845400 819 __IO uint32_t DMACCR;
AnnaBridge 172:65be27845400 820 __IO uint32_t DMACTCR;
AnnaBridge 172:65be27845400 821 __IO uint32_t DMACRCR;
AnnaBridge 172:65be27845400 822 uint32_t RESERVED38[2];
AnnaBridge 172:65be27845400 823 __IO uint32_t DMACTDLAR;
AnnaBridge 172:65be27845400 824 uint32_t RESERVED39;
AnnaBridge 172:65be27845400 825 __IO uint32_t DMACRDLAR;
AnnaBridge 172:65be27845400 826 __IO uint32_t DMACTDTPR;
AnnaBridge 172:65be27845400 827 uint32_t RESERVED40;
AnnaBridge 172:65be27845400 828 __IO uint32_t DMACRDTPR;
AnnaBridge 172:65be27845400 829 __IO uint32_t DMACTDRLR;
AnnaBridge 172:65be27845400 830 __IO uint32_t DMACRDRLR;
AnnaBridge 172:65be27845400 831 __IO uint32_t DMACIER;
AnnaBridge 172:65be27845400 832 __IO uint32_t DMACRIWTR;
AnnaBridge 172:65be27845400 833 __IO uint32_t DMACSFCSR;
AnnaBridge 172:65be27845400 834 uint32_t RESERVED41;
AnnaBridge 172:65be27845400 835 __IO uint32_t DMACCATDR;
AnnaBridge 172:65be27845400 836 uint32_t RESERVED42;
AnnaBridge 172:65be27845400 837 __IO uint32_t DMACCARDR;
AnnaBridge 172:65be27845400 838 uint32_t RESERVED43;
AnnaBridge 172:65be27845400 839 __IO uint32_t DMACCATBR;
AnnaBridge 172:65be27845400 840 uint32_t RESERVED44;
AnnaBridge 172:65be27845400 841 __IO uint32_t DMACCARBR;
AnnaBridge 172:65be27845400 842 __IO uint32_t DMACSR;
AnnaBridge 172:65be27845400 843 uint32_t RESERVED45[2];
AnnaBridge 172:65be27845400 844 __IO uint32_t DMACMFCR;
AnnaBridge 172:65be27845400 845 }ETH_TypeDef;
AnnaBridge 172:65be27845400 846 /**
AnnaBridge 172:65be27845400 847 * @brief External Interrupt/Event Controller
AnnaBridge 172:65be27845400 848 */
AnnaBridge 172:65be27845400 849
AnnaBridge 172:65be27845400 850 typedef struct
AnnaBridge 172:65be27845400 851 {
AnnaBridge 172:65be27845400 852 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 853 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 854 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 855 __IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
AnnaBridge 172:65be27845400 856 __IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
AnnaBridge 172:65be27845400 857 __IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
AnnaBridge 172:65be27845400 858 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
AnnaBridge 172:65be27845400 859 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 860 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 861 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 862 __IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
AnnaBridge 172:65be27845400 863 __IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
AnnaBridge 172:65be27845400 864 __IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
AnnaBridge 172:65be27845400 865 uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
AnnaBridge 172:65be27845400 866 __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 867 __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 868 __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 869 __IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
AnnaBridge 172:65be27845400 870 __IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
AnnaBridge 172:65be27845400 871 __IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
AnnaBridge 172:65be27845400 872 uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
AnnaBridge 172:65be27845400 873 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
AnnaBridge 172:65be27845400 874 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
AnnaBridge 172:65be27845400 875 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
AnnaBridge 172:65be27845400 876 uint32_t RESERVED4; /*!< Reserved, 0x8C */
AnnaBridge 172:65be27845400 877 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
AnnaBridge 172:65be27845400 878 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
AnnaBridge 172:65be27845400 879 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
AnnaBridge 172:65be27845400 880 uint32_t RESERVED5; /*!< Reserved, 0x9C */
AnnaBridge 172:65be27845400 881 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
AnnaBridge 172:65be27845400 882 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
AnnaBridge 172:65be27845400 883 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
AnnaBridge 172:65be27845400 884 }EXTI_TypeDef;
AnnaBridge 172:65be27845400 885
AnnaBridge 172:65be27845400 886 typedef struct
AnnaBridge 172:65be27845400 887 {
AnnaBridge 172:65be27845400 888 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 889 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 890 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 891 uint32_t RESERVED1; /*!< Reserved, 0x0C */
AnnaBridge 172:65be27845400 892 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 893 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 894 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 895 uint32_t RESERVED2; /*!< Reserved, 0x1C */
AnnaBridge 172:65be27845400 896 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 897 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 898 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 899 }EXTI_Core_TypeDef;
AnnaBridge 172:65be27845400 900
AnnaBridge 172:65be27845400 901
AnnaBridge 172:65be27845400 902 /**
AnnaBridge 172:65be27845400 903 * @brief FLASH Registers
AnnaBridge 172:65be27845400 904 */
AnnaBridge 172:65be27845400 905
AnnaBridge 172:65be27845400 906 typedef struct
AnnaBridge 172:65be27845400 907 {
AnnaBridge 172:65be27845400 908 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 909 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
AnnaBridge 172:65be27845400 910 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 911 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
AnnaBridge 172:65be27845400 912 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
AnnaBridge 172:65be27845400 913 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
AnnaBridge 172:65be27845400 914 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 915 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 916 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 917 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 918 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
AnnaBridge 172:65be27845400 919 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
AnnaBridge 172:65be27845400 920 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
AnnaBridge 172:65be27845400 921 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
AnnaBridge 172:65be27845400 922 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
AnnaBridge 172:65be27845400 923 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
AnnaBridge 172:65be27845400 924 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 925 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 926 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
AnnaBridge 172:65be27845400 927 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
AnnaBridge 172:65be27845400 928 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
AnnaBridge 172:65be27845400 929 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
AnnaBridge 172:65be27845400 930 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
AnnaBridge 172:65be27845400 931 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
AnnaBridge 172:65be27845400 932 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
AnnaBridge 172:65be27845400 933 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
AnnaBridge 172:65be27845400 934 uint32_t RESERVED2; /*!< Reserved, 0x108 */
AnnaBridge 172:65be27845400 935 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
AnnaBridge 172:65be27845400 936 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
AnnaBridge 172:65be27845400 937 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
AnnaBridge 172:65be27845400 938 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
AnnaBridge 172:65be27845400 939 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
AnnaBridge 172:65be27845400 940 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
AnnaBridge 172:65be27845400 941 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
AnnaBridge 172:65be27845400 942 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
AnnaBridge 172:65be27845400 943 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
AnnaBridge 172:65be27845400 944 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
AnnaBridge 172:65be27845400 945 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
AnnaBridge 172:65be27845400 946 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
AnnaBridge 172:65be27845400 947 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
AnnaBridge 172:65be27845400 948 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
AnnaBridge 172:65be27845400 949 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
AnnaBridge 172:65be27845400 950 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
AnnaBridge 172:65be27845400 951 } FLASH_TypeDef;
AnnaBridge 172:65be27845400 952
AnnaBridge 172:65be27845400 953 /**
AnnaBridge 172:65be27845400 954 * @brief Flexible Memory Controller
AnnaBridge 172:65be27845400 955 */
AnnaBridge 172:65be27845400 956
AnnaBridge 172:65be27845400 957 typedef struct
AnnaBridge 172:65be27845400 958 {
AnnaBridge 172:65be27845400 959 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
AnnaBridge 172:65be27845400 960 } FMC_Bank1_TypeDef;
AnnaBridge 172:65be27845400 961
AnnaBridge 172:65be27845400 962 /**
AnnaBridge 172:65be27845400 963 * @brief Flexible Memory Controller Bank1E
AnnaBridge 172:65be27845400 964 */
AnnaBridge 172:65be27845400 965
AnnaBridge 172:65be27845400 966 typedef struct
AnnaBridge 172:65be27845400 967 {
AnnaBridge 172:65be27845400 968 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
AnnaBridge 172:65be27845400 969 } FMC_Bank1E_TypeDef;
AnnaBridge 172:65be27845400 970
AnnaBridge 172:65be27845400 971 /**
AnnaBridge 172:65be27845400 972 * @brief Flexible Memory Controller Bank2
AnnaBridge 172:65be27845400 973 */
AnnaBridge 172:65be27845400 974
AnnaBridge 172:65be27845400 975 typedef struct
AnnaBridge 172:65be27845400 976 {
AnnaBridge 172:65be27845400 977 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
AnnaBridge 172:65be27845400 978 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
AnnaBridge 172:65be27845400 979 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
AnnaBridge 172:65be27845400 980 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
AnnaBridge 172:65be27845400 981 uint32_t RESERVED0; /*!< Reserved, 0x70 */
AnnaBridge 172:65be27845400 982 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
AnnaBridge 172:65be27845400 983 } FMC_Bank2_TypeDef;
AnnaBridge 172:65be27845400 984
AnnaBridge 172:65be27845400 985 /**
AnnaBridge 172:65be27845400 986 * @brief Flexible Memory Controller Bank3
AnnaBridge 172:65be27845400 987 */
AnnaBridge 172:65be27845400 988
AnnaBridge 172:65be27845400 989 typedef struct
AnnaBridge 172:65be27845400 990 {
AnnaBridge 172:65be27845400 991 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
AnnaBridge 172:65be27845400 992 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
AnnaBridge 172:65be27845400 993 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
AnnaBridge 172:65be27845400 994 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
AnnaBridge 172:65be27845400 995 uint32_t RESERVED; /*!< Reserved, 0x90 */
AnnaBridge 172:65be27845400 996 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
AnnaBridge 172:65be27845400 997 } FMC_Bank3_TypeDef;
AnnaBridge 172:65be27845400 998
AnnaBridge 172:65be27845400 999 /**
AnnaBridge 172:65be27845400 1000 * @brief Flexible Memory Controller Bank5 and 6
AnnaBridge 172:65be27845400 1001 */
AnnaBridge 172:65be27845400 1002
AnnaBridge 172:65be27845400 1003
AnnaBridge 172:65be27845400 1004 typedef struct
AnnaBridge 172:65be27845400 1005 {
AnnaBridge 172:65be27845400 1006 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
AnnaBridge 172:65be27845400 1007 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
AnnaBridge 172:65be27845400 1008 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
AnnaBridge 172:65be27845400 1009 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
AnnaBridge 172:65be27845400 1010 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
AnnaBridge 172:65be27845400 1011 } FMC_Bank5_6_TypeDef;
AnnaBridge 172:65be27845400 1012
AnnaBridge 172:65be27845400 1013 /**
AnnaBridge 172:65be27845400 1014 * @brief General Purpose I/O
AnnaBridge 172:65be27845400 1015 */
AnnaBridge 172:65be27845400 1016
AnnaBridge 172:65be27845400 1017 typedef struct
AnnaBridge 172:65be27845400 1018 {
AnnaBridge 172:65be27845400 1019 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1020 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1021 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1022 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1023 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1024 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1025 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1026 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1027 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
AnnaBridge 172:65be27845400 1028 } GPIO_TypeDef;
AnnaBridge 172:65be27845400 1029
AnnaBridge 172:65be27845400 1030 /**
AnnaBridge 172:65be27845400 1031 * @brief Operational Amplifier (OPAMP)
AnnaBridge 172:65be27845400 1032 */
AnnaBridge 172:65be27845400 1033
AnnaBridge 172:65be27845400 1034 typedef struct
AnnaBridge 172:65be27845400 1035 {
AnnaBridge 172:65be27845400 1036 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1037 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1038 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1039 } OPAMP_TypeDef;
AnnaBridge 172:65be27845400 1040
AnnaBridge 172:65be27845400 1041 /**
AnnaBridge 172:65be27845400 1042 * @brief System configuration controller
AnnaBridge 172:65be27845400 1043 */
AnnaBridge 172:65be27845400 1044
AnnaBridge 172:65be27845400 1045 typedef struct
AnnaBridge 172:65be27845400 1046 {
AnnaBridge 172:65be27845400 1047 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1048 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1049 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 172:65be27845400 1050 uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
AnnaBridge 172:65be27845400 1051 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1052 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1053 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1054 uint32_t RESERVED3[62]; /*!< Reserved, 0x2C-0x120 */
AnnaBridge 172:65be27845400 1055 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
AnnaBridge 172:65be27845400 1056 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
AnnaBridge 172:65be27845400 1057 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
AnnaBridge 172:65be27845400 1058 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
AnnaBridge 172:65be27845400 1059 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
AnnaBridge 172:65be27845400 1060 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
AnnaBridge 172:65be27845400 1061 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
AnnaBridge 172:65be27845400 1062 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
AnnaBridge 172:65be27845400 1063 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
AnnaBridge 172:65be27845400 1064 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
AnnaBridge 172:65be27845400 1065 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
AnnaBridge 172:65be27845400 1066 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
AnnaBridge 172:65be27845400 1067 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
AnnaBridge 172:65be27845400 1068 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
AnnaBridge 172:65be27845400 1069 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
AnnaBridge 172:65be27845400 1070 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
AnnaBridge 172:65be27845400 1071 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
AnnaBridge 172:65be27845400 1072 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
AnnaBridge 172:65be27845400 1073 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
AnnaBridge 172:65be27845400 1074 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
AnnaBridge 172:65be27845400 1075
AnnaBridge 172:65be27845400 1076 } SYSCFG_TypeDef;
AnnaBridge 172:65be27845400 1077
AnnaBridge 172:65be27845400 1078 /**
AnnaBridge 172:65be27845400 1079 * @brief Inter-integrated Circuit Interface
AnnaBridge 172:65be27845400 1080 */
AnnaBridge 172:65be27845400 1081
AnnaBridge 172:65be27845400 1082 typedef struct
AnnaBridge 172:65be27845400 1083 {
AnnaBridge 172:65be27845400 1084 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1085 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1086 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1087 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1088 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1089 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1090 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1091 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1092 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1093 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1094 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1095 } I2C_TypeDef;
AnnaBridge 172:65be27845400 1096
AnnaBridge 172:65be27845400 1097 /**
AnnaBridge 172:65be27845400 1098 * @brief Independent WATCHDOG
AnnaBridge 172:65be27845400 1099 */
AnnaBridge 172:65be27845400 1100
AnnaBridge 172:65be27845400 1101 typedef struct
AnnaBridge 172:65be27845400 1102 {
AnnaBridge 172:65be27845400 1103 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1104 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1105 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1106 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1107 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1108 } IWDG_TypeDef;
AnnaBridge 172:65be27845400 1109
AnnaBridge 172:65be27845400 1110
AnnaBridge 172:65be27845400 1111 /**
AnnaBridge 172:65be27845400 1112 * @brief JPEG Codec
AnnaBridge 172:65be27845400 1113 */
AnnaBridge 172:65be27845400 1114 typedef struct
AnnaBridge 172:65be27845400 1115 {
AnnaBridge 172:65be27845400 1116 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
AnnaBridge 172:65be27845400 1117 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
AnnaBridge 172:65be27845400 1118 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
AnnaBridge 172:65be27845400 1119 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
AnnaBridge 172:65be27845400 1120 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
AnnaBridge 172:65be27845400 1121 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
AnnaBridge 172:65be27845400 1122 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
AnnaBridge 172:65be27845400 1123 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
AnnaBridge 172:65be27845400 1124 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
AnnaBridge 172:65be27845400 1125 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
AnnaBridge 172:65be27845400 1126 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
AnnaBridge 172:65be27845400 1127 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
AnnaBridge 172:65be27845400 1128 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
AnnaBridge 172:65be27845400 1129 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
AnnaBridge 172:65be27845400 1130 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
AnnaBridge 172:65be27845400 1131 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
AnnaBridge 172:65be27845400 1132 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
AnnaBridge 172:65be27845400 1133 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
AnnaBridge 172:65be27845400 1134 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
AnnaBridge 172:65be27845400 1135 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
AnnaBridge 172:65be27845400 1136 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
AnnaBridge 172:65be27845400 1137 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
AnnaBridge 172:65be27845400 1138 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
AnnaBridge 172:65be27845400 1139 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
AnnaBridge 172:65be27845400 1140 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
AnnaBridge 172:65be27845400 1141 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
AnnaBridge 172:65be27845400 1142 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
AnnaBridge 172:65be27845400 1143 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
AnnaBridge 172:65be27845400 1144 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
AnnaBridge 172:65be27845400 1145
AnnaBridge 172:65be27845400 1146 } JPEG_TypeDef;
AnnaBridge 172:65be27845400 1147
AnnaBridge 172:65be27845400 1148
AnnaBridge 172:65be27845400 1149 /**
AnnaBridge 172:65be27845400 1150 * @brief LCD-TFT Display Controller
AnnaBridge 172:65be27845400 1151 */
AnnaBridge 172:65be27845400 1152
AnnaBridge 172:65be27845400 1153 typedef struct
AnnaBridge 172:65be27845400 1154 {
AnnaBridge 172:65be27845400 1155 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
AnnaBridge 172:65be27845400 1156 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1157 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1158 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1159 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1160 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1161 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
AnnaBridge 172:65be27845400 1162 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1163 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
AnnaBridge 172:65be27845400 1164 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1165 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
AnnaBridge 172:65be27845400 1166 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 1167 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 1168 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1169 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1170 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1171 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1172 } LTDC_TypeDef;
AnnaBridge 172:65be27845400 1173
AnnaBridge 172:65be27845400 1174 /**
AnnaBridge 172:65be27845400 1175 * @brief LCD-TFT Display layer x Controller
AnnaBridge 172:65be27845400 1176 */
AnnaBridge 172:65be27845400 1177
AnnaBridge 172:65be27845400 1178 typedef struct
AnnaBridge 172:65be27845400 1179 {
AnnaBridge 172:65be27845400 1180 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
AnnaBridge 172:65be27845400 1181 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
AnnaBridge 172:65be27845400 1182 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
AnnaBridge 172:65be27845400 1183 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
AnnaBridge 172:65be27845400 1184 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
AnnaBridge 172:65be27845400 1185 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
AnnaBridge 172:65be27845400 1186 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
AnnaBridge 172:65be27845400 1187 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
AnnaBridge 172:65be27845400 1188 uint32_t RESERVED0[2]; /*!< Reserved */
AnnaBridge 172:65be27845400 1189 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
AnnaBridge 172:65be27845400 1190 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
AnnaBridge 172:65be27845400 1191 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
AnnaBridge 172:65be27845400 1192 uint32_t RESERVED1[3]; /*!< Reserved */
AnnaBridge 172:65be27845400 1193 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
AnnaBridge 172:65be27845400 1194
AnnaBridge 172:65be27845400 1195 } LTDC_Layer_TypeDef;
AnnaBridge 172:65be27845400 1196
AnnaBridge 172:65be27845400 1197
AnnaBridge 172:65be27845400 1198 /**
AnnaBridge 172:65be27845400 1199 * @brief Power Control
AnnaBridge 172:65be27845400 1200 */
AnnaBridge 172:65be27845400 1201
AnnaBridge 172:65be27845400 1202 typedef struct
AnnaBridge 172:65be27845400 1203 {
AnnaBridge 172:65be27845400 1204 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1205 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1206 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1207 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1208 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1209 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1210 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1211 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1212 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1213 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1214 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1215 } PWR_TypeDef;
AnnaBridge 172:65be27845400 1216
AnnaBridge 172:65be27845400 1217 /**
AnnaBridge 172:65be27845400 1218 * @brief Reset and Clock Control
AnnaBridge 172:65be27845400 1219 */
AnnaBridge 172:65be27845400 1220
AnnaBridge 172:65be27845400 1221 typedef struct
AnnaBridge 172:65be27845400 1222 {
AnnaBridge 172:65be27845400 1223 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1224 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1225 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1226 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1227 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1228 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1229 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1230 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1231 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1232 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1233 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1234 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1235 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1236 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 1237 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 1238 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1239 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1240 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1241 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1242 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
AnnaBridge 172:65be27845400 1243 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
AnnaBridge 172:65be27845400 1244 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
AnnaBridge 172:65be27845400 1245 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
AnnaBridge 172:65be27845400 1246 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
AnnaBridge 172:65be27845400 1247 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
AnnaBridge 172:65be27845400 1248 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
AnnaBridge 172:65be27845400 1249 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
AnnaBridge 172:65be27845400 1250 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
AnnaBridge 172:65be27845400 1251 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
AnnaBridge 172:65be27845400 1252 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
AnnaBridge 172:65be27845400 1253 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
AnnaBridge 172:65be27845400 1254 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
AnnaBridge 172:65be27845400 1255 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
AnnaBridge 172:65be27845400 1256 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
AnnaBridge 172:65be27845400 1257 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
AnnaBridge 172:65be27845400 1258 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
AnnaBridge 172:65be27845400 1259 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
AnnaBridge 172:65be27845400 1260 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
AnnaBridge 172:65be27845400 1261 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
AnnaBridge 172:65be27845400 1262 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
AnnaBridge 172:65be27845400 1263 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
AnnaBridge 172:65be27845400 1264 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
AnnaBridge 172:65be27845400 1265 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
AnnaBridge 172:65be27845400 1266 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
AnnaBridge 172:65be27845400 1267 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
AnnaBridge 172:65be27845400 1268 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
AnnaBridge 172:65be27845400 1269 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
AnnaBridge 172:65be27845400 1270 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
AnnaBridge 172:65be27845400 1271 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
AnnaBridge 172:65be27845400 1272 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
AnnaBridge 172:65be27845400 1273 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
AnnaBridge 172:65be27845400 1274 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
AnnaBridge 172:65be27845400 1275 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
AnnaBridge 172:65be27845400 1276 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
AnnaBridge 172:65be27845400 1277 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
AnnaBridge 172:65be27845400 1278 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
AnnaBridge 172:65be27845400 1279 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
AnnaBridge 172:65be27845400 1280 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
AnnaBridge 172:65be27845400 1281 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
AnnaBridge 172:65be27845400 1282 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
AnnaBridge 172:65be27845400 1283 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
AnnaBridge 172:65be27845400 1284 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
AnnaBridge 172:65be27845400 1285 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
AnnaBridge 172:65be27845400 1286 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
AnnaBridge 172:65be27845400 1287 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
AnnaBridge 172:65be27845400 1288
AnnaBridge 172:65be27845400 1289 } RCC_TypeDef;
AnnaBridge 172:65be27845400 1290
AnnaBridge 172:65be27845400 1291 typedef struct
AnnaBridge 172:65be27845400 1292 {
AnnaBridge 172:65be27845400 1293 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1294 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1295 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1296 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1297 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1298 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1299 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1300 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1301 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1302 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1303 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1304 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1305 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1306 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1307 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1308 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 1309 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */
AnnaBridge 172:65be27845400 1310 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */
AnnaBridge 172:65be27845400 1311 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */
AnnaBridge 172:65be27845400 1312 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */
AnnaBridge 172:65be27845400 1313 uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */
AnnaBridge 172:65be27845400 1314
AnnaBridge 172:65be27845400 1315 } RCC_Core_TypeDef;
AnnaBridge 172:65be27845400 1316
AnnaBridge 172:65be27845400 1317 /**
AnnaBridge 172:65be27845400 1318 * @brief Real-Time Clock
AnnaBridge 172:65be27845400 1319 */
AnnaBridge 172:65be27845400 1320 typedef struct
AnnaBridge 172:65be27845400 1321 {
AnnaBridge 172:65be27845400 1322 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1323 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1324 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1325 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1326 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1327 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1328 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1329 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1330 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1331 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1332 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1333 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1334 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1335 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 1336 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 1337 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1338 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1339 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1340 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1341 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 1342 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 172:65be27845400 1343 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 172:65be27845400 1344 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 172:65be27845400 1345 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 172:65be27845400 1346 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 172:65be27845400 1347 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 172:65be27845400 1348 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 172:65be27845400 1349 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 172:65be27845400 1350 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 172:65be27845400 1351 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 172:65be27845400 1352 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 172:65be27845400 1353 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 172:65be27845400 1354 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 172:65be27845400 1355 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 172:65be27845400 1356 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 172:65be27845400 1357 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 172:65be27845400 1358 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 172:65be27845400 1359 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 172:65be27845400 1360 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 172:65be27845400 1361 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 172:65be27845400 1362 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
AnnaBridge 172:65be27845400 1363 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
AnnaBridge 172:65be27845400 1364 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
AnnaBridge 172:65be27845400 1365 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
AnnaBridge 172:65be27845400 1366 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
AnnaBridge 172:65be27845400 1367 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
AnnaBridge 172:65be27845400 1368 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
AnnaBridge 172:65be27845400 1369 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
AnnaBridge 172:65be27845400 1370 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
AnnaBridge 172:65be27845400 1371 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
AnnaBridge 172:65be27845400 1372 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
AnnaBridge 172:65be27845400 1373 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
AnnaBridge 172:65be27845400 1374 } RTC_TypeDef;
AnnaBridge 172:65be27845400 1375
AnnaBridge 172:65be27845400 1376 /**
AnnaBridge 172:65be27845400 1377 * @brief Serial Audio Interface
AnnaBridge 172:65be27845400 1378 */
AnnaBridge 172:65be27845400 1379
AnnaBridge 172:65be27845400 1380 typedef struct
AnnaBridge 172:65be27845400 1381 {
AnnaBridge 172:65be27845400 1382 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1383 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
AnnaBridge 172:65be27845400 1384 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1385 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1386 } SAI_TypeDef;
AnnaBridge 172:65be27845400 1387
AnnaBridge 172:65be27845400 1388 typedef struct
AnnaBridge 172:65be27845400 1389 {
AnnaBridge 172:65be27845400 1390 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1391 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1392 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1393 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1394 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1395 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1396 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1397 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1398 } SAI_Block_TypeDef;
AnnaBridge 172:65be27845400 1399
AnnaBridge 172:65be27845400 1400 /**
AnnaBridge 172:65be27845400 1401 * @brief SPDIF-RX Interface
AnnaBridge 172:65be27845400 1402 */
AnnaBridge 172:65be27845400 1403
AnnaBridge 172:65be27845400 1404 typedef struct
AnnaBridge 172:65be27845400 1405 {
AnnaBridge 172:65be27845400 1406 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1407 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1408 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1409 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1410 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1411 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1412 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1413 uint32_t RESERVED2; /*!< Reserved, 0x1A */
AnnaBridge 172:65be27845400 1414 } SPDIFRX_TypeDef;
AnnaBridge 172:65be27845400 1415
AnnaBridge 172:65be27845400 1416
AnnaBridge 172:65be27845400 1417 /**
AnnaBridge 172:65be27845400 1418 * @brief Secure digital input/output Interface
AnnaBridge 172:65be27845400 1419 */
AnnaBridge 172:65be27845400 1420
AnnaBridge 172:65be27845400 1421 typedef struct
AnnaBridge 172:65be27845400 1422 {
AnnaBridge 172:65be27845400 1423 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1424 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1425 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1426 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1427 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1428 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1429 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1430 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1431 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1432 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1433 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1434 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1435 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1436 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 1437 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 1438 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1439 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1440 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
AnnaBridge 172:65be27845400 1441 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
AnnaBridge 172:65be27845400 1442 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
AnnaBridge 172:65be27845400 1443 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
AnnaBridge 172:65be27845400 1444 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
AnnaBridge 172:65be27845400 1445 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
AnnaBridge 172:65be27845400 1446 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
AnnaBridge 172:65be27845400 1447 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
AnnaBridge 172:65be27845400 1448 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
AnnaBridge 172:65be27845400 1449 } SDMMC_TypeDef;
AnnaBridge 172:65be27845400 1450
AnnaBridge 172:65be27845400 1451
AnnaBridge 172:65be27845400 1452 /**
AnnaBridge 172:65be27845400 1453 * @brief Delay Block DLYB
AnnaBridge 172:65be27845400 1454 */
AnnaBridge 172:65be27845400 1455
AnnaBridge 172:65be27845400 1456 typedef struct
AnnaBridge 172:65be27845400 1457 {
AnnaBridge 172:65be27845400 1458 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1459 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1460 } DLYB_TypeDef;
AnnaBridge 172:65be27845400 1461
AnnaBridge 172:65be27845400 1462 /**
AnnaBridge 172:65be27845400 1463 * @brief HW Semaphore HSEM
AnnaBridge 172:65be27845400 1464 */
AnnaBridge 172:65be27845400 1465
AnnaBridge 172:65be27845400 1466 typedef struct
AnnaBridge 172:65be27845400 1467 {
AnnaBridge 172:65be27845400 1468 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
AnnaBridge 172:65be27845400 1469 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
AnnaBridge 172:65be27845400 1470 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
AnnaBridge 172:65be27845400 1471 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
AnnaBridge 172:65be27845400 1472 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
AnnaBridge 172:65be27845400 1473 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
AnnaBridge 172:65be27845400 1474 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
AnnaBridge 172:65be27845400 1475 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
AnnaBridge 172:65be27845400 1476 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
AnnaBridge 172:65be27845400 1477
AnnaBridge 172:65be27845400 1478 } HSEM_TypeDef;
AnnaBridge 172:65be27845400 1479
AnnaBridge 172:65be27845400 1480 typedef struct
AnnaBridge 172:65be27845400 1481 {
AnnaBridge 172:65be27845400 1482 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
AnnaBridge 172:65be27845400 1483 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
AnnaBridge 172:65be27845400 1484 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
AnnaBridge 172:65be27845400 1485 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
AnnaBridge 172:65be27845400 1486 } HSEM_Common_TypeDef;
AnnaBridge 172:65be27845400 1487
AnnaBridge 172:65be27845400 1488 /**
AnnaBridge 172:65be27845400 1489 * @brief Serial Peripheral Interface
AnnaBridge 172:65be27845400 1490 */
AnnaBridge 172:65be27845400 1491
AnnaBridge 172:65be27845400 1492 typedef struct
AnnaBridge 172:65be27845400 1493 {
AnnaBridge 172:65be27845400 1494 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1495 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1496 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1497 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1498 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1499 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1500 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1501 uint32_t RESERVED0; /*!< Reserved, 0x1C */
AnnaBridge 172:65be27845400 1502 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1503 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
AnnaBridge 172:65be27845400 1504 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1505 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
AnnaBridge 172:65be27845400 1506 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1507 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1508 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1509 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 1510 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
AnnaBridge 172:65be27845400 1511
AnnaBridge 172:65be27845400 1512 } SPI_TypeDef;
AnnaBridge 172:65be27845400 1513 /**
AnnaBridge 172:65be27845400 1514 * @brief QUAD Serial Peripheral Interface
AnnaBridge 172:65be27845400 1515 */
AnnaBridge 172:65be27845400 1516
AnnaBridge 172:65be27845400 1517 typedef struct
AnnaBridge 172:65be27845400 1518 {
AnnaBridge 172:65be27845400 1519 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1520 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1521 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1522 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1523 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1524 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1525 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1526 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1527 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1528 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1529 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1530 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1531 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1532 } QUADSPI_TypeDef;
AnnaBridge 172:65be27845400 1533
AnnaBridge 172:65be27845400 1534 /**
AnnaBridge 172:65be27845400 1535 * @brief TIM
AnnaBridge 172:65be27845400 1536 */
AnnaBridge 172:65be27845400 1537
AnnaBridge 172:65be27845400 1538 typedef struct
AnnaBridge 172:65be27845400 1539 {
AnnaBridge 172:65be27845400 1540 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1541 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1542 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1543 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1544 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1545 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1546 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1547 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1548 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1549 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1550 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1551 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1552 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1553 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 172:65be27845400 1554 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 172:65be27845400 1555 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1556 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1557 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1558 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1559 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 172:65be27845400 1560 uint32_t RESERVED1; /*!< Reserved, 0x50 */
AnnaBridge 172:65be27845400 1561 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
AnnaBridge 172:65be27845400 1562 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
AnnaBridge 172:65be27845400 1563 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
AnnaBridge 172:65be27845400 1564 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
AnnaBridge 172:65be27845400 1565 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
AnnaBridge 172:65be27845400 1566 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
AnnaBridge 172:65be27845400 1567 } TIM_TypeDef;
AnnaBridge 172:65be27845400 1568
AnnaBridge 172:65be27845400 1569 /**
AnnaBridge 172:65be27845400 1570 * @brief LPTIMIMER
AnnaBridge 172:65be27845400 1571 */
AnnaBridge 172:65be27845400 1572 typedef struct
AnnaBridge 172:65be27845400 1573 {
AnnaBridge 172:65be27845400 1574 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1575 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1576 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1577 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1578 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1579 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1580 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1581 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1582 uint32_t RESERVED1; /*!< Reserved, 0x20 */
AnnaBridge 172:65be27845400 1583 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1584 } LPTIM_TypeDef;
AnnaBridge 172:65be27845400 1585
AnnaBridge 172:65be27845400 1586 /**
AnnaBridge 172:65be27845400 1587 * @brief Comparator
AnnaBridge 172:65be27845400 1588 */
AnnaBridge 172:65be27845400 1589 typedef struct
AnnaBridge 172:65be27845400 1590 {
AnnaBridge 172:65be27845400 1591 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1592 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1593 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1594 } COMPOPT_TypeDef;
AnnaBridge 172:65be27845400 1595
AnnaBridge 172:65be27845400 1596 typedef struct
AnnaBridge 172:65be27845400 1597 {
AnnaBridge 172:65be27845400 1598 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
AnnaBridge 172:65be27845400 1599 } COMP_TypeDef;
AnnaBridge 172:65be27845400 1600
AnnaBridge 172:65be27845400 1601 typedef struct
AnnaBridge 172:65be27845400 1602 {
AnnaBridge 172:65be27845400 1603 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1604 } COMP_Common_TypeDef;
AnnaBridge 172:65be27845400 1605 /**
AnnaBridge 172:65be27845400 1606 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 172:65be27845400 1607 */
AnnaBridge 172:65be27845400 1608
AnnaBridge 172:65be27845400 1609 typedef struct
AnnaBridge 172:65be27845400 1610 {
AnnaBridge 172:65be27845400 1611 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1612 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1613 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1614 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1615 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1616 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1617 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1618 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1619 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1620 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1621 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1622 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1623 } USART_TypeDef;
AnnaBridge 172:65be27845400 1624
AnnaBridge 172:65be27845400 1625 /**
AnnaBridge 172:65be27845400 1626 * @brief Single Wire Protocol Master Interface SPWMI
AnnaBridge 172:65be27845400 1627 */
AnnaBridge 172:65be27845400 1628 typedef struct
AnnaBridge 172:65be27845400 1629 {
AnnaBridge 172:65be27845400 1630 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1631 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1632 uint32_t RESERVED1; /*!< Reserved, 0x08 */
AnnaBridge 172:65be27845400 1633 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1634 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1635 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1636 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1637 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1638 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1639 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1640 } SWPMI_TypeDef;
AnnaBridge 172:65be27845400 1641
AnnaBridge 172:65be27845400 1642 /**
AnnaBridge 172:65be27845400 1643 * @brief Window WATCHDOG
AnnaBridge 172:65be27845400 1644 */
AnnaBridge 172:65be27845400 1645
AnnaBridge 172:65be27845400 1646 typedef struct
AnnaBridge 172:65be27845400 1647 {
AnnaBridge 172:65be27845400 1648 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1649 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1650 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1651 } WWDG_TypeDef;
AnnaBridge 172:65be27845400 1652
AnnaBridge 172:65be27845400 1653
AnnaBridge 172:65be27845400 1654 /**
AnnaBridge 172:65be27845400 1655 * @brief RAM_ECC_Specific_Registers
AnnaBridge 172:65be27845400 1656 */
AnnaBridge 172:65be27845400 1657 typedef struct
AnnaBridge 172:65be27845400 1658 {
AnnaBridge 172:65be27845400 1659 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
AnnaBridge 172:65be27845400 1660 __IO uint32_t SR; /*!< RAMECC monitor status register */
AnnaBridge 172:65be27845400 1661 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
AnnaBridge 172:65be27845400 1662 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
AnnaBridge 172:65be27845400 1663 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
AnnaBridge 172:65be27845400 1664 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
AnnaBridge 172:65be27845400 1665 } RAMECC_MonitorTypeDef;
AnnaBridge 172:65be27845400 1666
AnnaBridge 172:65be27845400 1667 typedef struct
AnnaBridge 172:65be27845400 1668 {
AnnaBridge 172:65be27845400 1669 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
AnnaBridge 172:65be27845400 1670 } RAMECC_TypeDef;
AnnaBridge 172:65be27845400 1671 /**
AnnaBridge 172:65be27845400 1672 * @}
AnnaBridge 172:65be27845400 1673 */
AnnaBridge 172:65be27845400 1674
AnnaBridge 172:65be27845400 1675
AnnaBridge 172:65be27845400 1676
AnnaBridge 172:65be27845400 1677 /**
AnnaBridge 172:65be27845400 1678 * @brief High resolution Timer (HRTIM)
AnnaBridge 172:65be27845400 1679 */
AnnaBridge 172:65be27845400 1680 /* HRTIM master registers definition */
AnnaBridge 172:65be27845400 1681 typedef struct
AnnaBridge 172:65be27845400 1682 {
AnnaBridge 172:65be27845400 1683 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1684 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1685 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1686 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
AnnaBridge 172:65be27845400 1687 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1688 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1689 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1690 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1691 uint32_t RESERVED0; /*!< Reserved, 0x20 */
AnnaBridge 172:65be27845400 1692 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1693 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1694 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1695 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
AnnaBridge 172:65be27845400 1696 }HRTIM_Master_TypeDef;
AnnaBridge 172:65be27845400 1697
AnnaBridge 172:65be27845400 1698 /* HRTIM Timer A to E registers definition */
AnnaBridge 172:65be27845400 1699 typedef struct
AnnaBridge 172:65be27845400 1700 {
AnnaBridge 172:65be27845400 1701 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1702 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1703 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1704 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1705 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1706 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1707 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1708 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1709 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1710 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1711 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1712 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1713 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1714 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
AnnaBridge 172:65be27845400 1715 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
AnnaBridge 172:65be27845400 1716 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1717 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1718 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1719 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1720 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
AnnaBridge 172:65be27845400 1721 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
AnnaBridge 172:65be27845400 1722 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
AnnaBridge 172:65be27845400 1723 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
AnnaBridge 172:65be27845400 1724 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
AnnaBridge 172:65be27845400 1725 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
AnnaBridge 172:65be27845400 1726 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
AnnaBridge 172:65be27845400 1727 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
AnnaBridge 172:65be27845400 1728 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
AnnaBridge 172:65be27845400 1729 }HRTIM_Timerx_TypeDef;
AnnaBridge 172:65be27845400 1730
AnnaBridge 172:65be27845400 1731 /* HRTIM common register definition */
AnnaBridge 172:65be27845400 1732 typedef struct
AnnaBridge 172:65be27845400 1733 {
AnnaBridge 172:65be27845400 1734 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1735 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1736 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1737 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
AnnaBridge 172:65be27845400 1738 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
AnnaBridge 172:65be27845400 1739 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
AnnaBridge 172:65be27845400 1740 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
AnnaBridge 172:65be27845400 1741 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
AnnaBridge 172:65be27845400 1742 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
AnnaBridge 172:65be27845400 1743 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
AnnaBridge 172:65be27845400 1744 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
AnnaBridge 172:65be27845400 1745 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
AnnaBridge 172:65be27845400 1746 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
AnnaBridge 172:65be27845400 1747 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
AnnaBridge 172:65be27845400 1748 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
AnnaBridge 172:65be27845400 1749 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
AnnaBridge 172:65be27845400 1750 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
AnnaBridge 172:65be27845400 1751 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
AnnaBridge 172:65be27845400 1752 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
AnnaBridge 172:65be27845400 1753 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
AnnaBridge 172:65be27845400 1754 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
AnnaBridge 172:65be27845400 1755 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
AnnaBridge 172:65be27845400 1756 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
AnnaBridge 172:65be27845400 1757 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
AnnaBridge 172:65be27845400 1758 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
AnnaBridge 172:65be27845400 1759 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
AnnaBridge 172:65be27845400 1760 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
AnnaBridge 172:65be27845400 1761 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
AnnaBridge 172:65be27845400 1762 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
AnnaBridge 172:65be27845400 1763 }HRTIM_Common_TypeDef;
AnnaBridge 172:65be27845400 1764
AnnaBridge 172:65be27845400 1765 /* HRTIM register definition */
AnnaBridge 172:65be27845400 1766 typedef struct {
AnnaBridge 172:65be27845400 1767 HRTIM_Master_TypeDef sMasterRegs;
AnnaBridge 172:65be27845400 1768 HRTIM_Timerx_TypeDef sTimerxRegs[5];
AnnaBridge 172:65be27845400 1769 uint32_t RESERVED0[32];
AnnaBridge 172:65be27845400 1770 HRTIM_Common_TypeDef sCommonRegs;
AnnaBridge 172:65be27845400 1771 }HRTIM_TypeDef;
AnnaBridge 172:65be27845400 1772 /**
AnnaBridge 172:65be27845400 1773 * @brief RNG
AnnaBridge 172:65be27845400 1774 */
AnnaBridge 172:65be27845400 1775
AnnaBridge 172:65be27845400 1776 typedef struct
AnnaBridge 172:65be27845400 1777 {
AnnaBridge 172:65be27845400 1778 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
AnnaBridge 172:65be27845400 1779 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
AnnaBridge 172:65be27845400 1780 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
AnnaBridge 172:65be27845400 1781 } RNG_TypeDef;
AnnaBridge 172:65be27845400 1782
AnnaBridge 172:65be27845400 1783 /**
AnnaBridge 172:65be27845400 1784 * @brief MDIOS
AnnaBridge 172:65be27845400 1785 */
AnnaBridge 172:65be27845400 1786
AnnaBridge 172:65be27845400 1787 typedef struct
AnnaBridge 172:65be27845400 1788 {
AnnaBridge 172:65be27845400 1789 __IO uint32_t CR;
AnnaBridge 172:65be27845400 1790 __IO uint32_t WRFR;
AnnaBridge 172:65be27845400 1791 __IO uint32_t CWRFR;
AnnaBridge 172:65be27845400 1792 __IO uint32_t RDFR;
AnnaBridge 172:65be27845400 1793 __IO uint32_t CRDFR;
AnnaBridge 172:65be27845400 1794 __IO uint32_t SR;
AnnaBridge 172:65be27845400 1795 __IO uint32_t CLRFR;
AnnaBridge 172:65be27845400 1796 uint32_t RESERVED[57];
AnnaBridge 172:65be27845400 1797 __IO uint32_t DINR0;
AnnaBridge 172:65be27845400 1798 __IO uint32_t DINR1;
AnnaBridge 172:65be27845400 1799 __IO uint32_t DINR2;
AnnaBridge 172:65be27845400 1800 __IO uint32_t DINR3;
AnnaBridge 172:65be27845400 1801 __IO uint32_t DINR4;
AnnaBridge 172:65be27845400 1802 __IO uint32_t DINR5;
AnnaBridge 172:65be27845400 1803 __IO uint32_t DINR6;
AnnaBridge 172:65be27845400 1804 __IO uint32_t DINR7;
AnnaBridge 172:65be27845400 1805 __IO uint32_t DINR8;
AnnaBridge 172:65be27845400 1806 __IO uint32_t DINR9;
AnnaBridge 172:65be27845400 1807 __IO uint32_t DINR10;
AnnaBridge 172:65be27845400 1808 __IO uint32_t DINR11;
AnnaBridge 172:65be27845400 1809 __IO uint32_t DINR12;
AnnaBridge 172:65be27845400 1810 __IO uint32_t DINR13;
AnnaBridge 172:65be27845400 1811 __IO uint32_t DINR14;
AnnaBridge 172:65be27845400 1812 __IO uint32_t DINR15;
AnnaBridge 172:65be27845400 1813 __IO uint32_t DINR16;
AnnaBridge 172:65be27845400 1814 __IO uint32_t DINR17;
AnnaBridge 172:65be27845400 1815 __IO uint32_t DINR18;
AnnaBridge 172:65be27845400 1816 __IO uint32_t DINR19;
AnnaBridge 172:65be27845400 1817 __IO uint32_t DINR20;
AnnaBridge 172:65be27845400 1818 __IO uint32_t DINR21;
AnnaBridge 172:65be27845400 1819 __IO uint32_t DINR22;
AnnaBridge 172:65be27845400 1820 __IO uint32_t DINR23;
AnnaBridge 172:65be27845400 1821 __IO uint32_t DINR24;
AnnaBridge 172:65be27845400 1822 __IO uint32_t DINR25;
AnnaBridge 172:65be27845400 1823 __IO uint32_t DINR26;
AnnaBridge 172:65be27845400 1824 __IO uint32_t DINR27;
AnnaBridge 172:65be27845400 1825 __IO uint32_t DINR28;
AnnaBridge 172:65be27845400 1826 __IO uint32_t DINR29;
AnnaBridge 172:65be27845400 1827 __IO uint32_t DINR30;
AnnaBridge 172:65be27845400 1828 __IO uint32_t DINR31;
AnnaBridge 172:65be27845400 1829 __IO uint32_t DOUTR0;
AnnaBridge 172:65be27845400 1830 __IO uint32_t DOUTR1;
AnnaBridge 172:65be27845400 1831 __IO uint32_t DOUTR2;
AnnaBridge 172:65be27845400 1832 __IO uint32_t DOUTR3;
AnnaBridge 172:65be27845400 1833 __IO uint32_t DOUTR4;
AnnaBridge 172:65be27845400 1834 __IO uint32_t DOUTR5;
AnnaBridge 172:65be27845400 1835 __IO uint32_t DOUTR6;
AnnaBridge 172:65be27845400 1836 __IO uint32_t DOUTR7;
AnnaBridge 172:65be27845400 1837 __IO uint32_t DOUTR8;
AnnaBridge 172:65be27845400 1838 __IO uint32_t DOUTR9;
AnnaBridge 172:65be27845400 1839 __IO uint32_t DOUTR10;
AnnaBridge 172:65be27845400 1840 __IO uint32_t DOUTR11;
AnnaBridge 172:65be27845400 1841 __IO uint32_t DOUTR12;
AnnaBridge 172:65be27845400 1842 __IO uint32_t DOUTR13;
AnnaBridge 172:65be27845400 1843 __IO uint32_t DOUTR14;
AnnaBridge 172:65be27845400 1844 __IO uint32_t DOUTR15;
AnnaBridge 172:65be27845400 1845 __IO uint32_t DOUTR16;
AnnaBridge 172:65be27845400 1846 __IO uint32_t DOUTR17;
AnnaBridge 172:65be27845400 1847 __IO uint32_t DOUTR18;
AnnaBridge 172:65be27845400 1848 __IO uint32_t DOUTR19;
AnnaBridge 172:65be27845400 1849 __IO uint32_t DOUTR20;
AnnaBridge 172:65be27845400 1850 __IO uint32_t DOUTR21;
AnnaBridge 172:65be27845400 1851 __IO uint32_t DOUTR22;
AnnaBridge 172:65be27845400 1852 __IO uint32_t DOUTR23;
AnnaBridge 172:65be27845400 1853 __IO uint32_t DOUTR24;
AnnaBridge 172:65be27845400 1854 __IO uint32_t DOUTR25;
AnnaBridge 172:65be27845400 1855 __IO uint32_t DOUTR26;
AnnaBridge 172:65be27845400 1856 __IO uint32_t DOUTR27;
AnnaBridge 172:65be27845400 1857 __IO uint32_t DOUTR28;
AnnaBridge 172:65be27845400 1858 __IO uint32_t DOUTR29;
AnnaBridge 172:65be27845400 1859 __IO uint32_t DOUTR30;
AnnaBridge 172:65be27845400 1860 __IO uint32_t DOUTR31;
AnnaBridge 172:65be27845400 1861 } MDIOS_TypeDef;
AnnaBridge 172:65be27845400 1862
AnnaBridge 172:65be27845400 1863
AnnaBridge 172:65be27845400 1864 /**
AnnaBridge 172:65be27845400 1865 * @brief USB_OTG_Core_Registers
AnnaBridge 172:65be27845400 1866 */
AnnaBridge 172:65be27845400 1867 typedef struct
AnnaBridge 172:65be27845400 1868 {
AnnaBridge 172:65be27845400 1869 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 172:65be27845400 1870 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 172:65be27845400 1871 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 172:65be27845400 1872 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 172:65be27845400 1873 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 172:65be27845400 1874 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 172:65be27845400 1875 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 172:65be27845400 1876 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 172:65be27845400 1877 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 172:65be27845400 1878 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 172:65be27845400 1879 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 172:65be27845400 1880 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 172:65be27845400 1881 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 172:65be27845400 1882 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 172:65be27845400 1883 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 172:65be27845400 1884 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
AnnaBridge 172:65be27845400 1885 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
AnnaBridge 172:65be27845400 1886 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
AnnaBridge 172:65be27845400 1887 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
AnnaBridge 172:65be27845400 1888 uint32_t Reserved6; /*!< Reserved 050h */
AnnaBridge 172:65be27845400 1889 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
AnnaBridge 172:65be27845400 1890 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
AnnaBridge 172:65be27845400 1891 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
AnnaBridge 172:65be27845400 1892 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
AnnaBridge 172:65be27845400 1893 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
AnnaBridge 172:65be27845400 1894 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 172:65be27845400 1895 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 172:65be27845400 1896 } USB_OTG_GlobalTypeDef;
AnnaBridge 172:65be27845400 1897
AnnaBridge 172:65be27845400 1898
AnnaBridge 172:65be27845400 1899 /**
AnnaBridge 172:65be27845400 1900 * @brief USB_OTG_device_Registers
AnnaBridge 172:65be27845400 1901 */
AnnaBridge 172:65be27845400 1902 typedef struct
AnnaBridge 172:65be27845400 1903 {
AnnaBridge 172:65be27845400 1904 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 172:65be27845400 1905 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 172:65be27845400 1906 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 172:65be27845400 1907 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 172:65be27845400 1908 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 172:65be27845400 1909 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 172:65be27845400 1910 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 172:65be27845400 1911 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 172:65be27845400 1912 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 172:65be27845400 1913 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 172:65be27845400 1914 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 172:65be27845400 1915 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 172:65be27845400 1916 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 172:65be27845400 1917 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 172:65be27845400 1918 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 172:65be27845400 1919 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 172:65be27845400 1920 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 172:65be27845400 1921 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 172:65be27845400 1922 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 172:65be27845400 1923 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 172:65be27845400 1924 } USB_OTG_DeviceTypeDef;
AnnaBridge 172:65be27845400 1925
AnnaBridge 172:65be27845400 1926
AnnaBridge 172:65be27845400 1927 /**
AnnaBridge 172:65be27845400 1928 * @brief USB_OTG_IN_Endpoint-Specific_Register
AnnaBridge 172:65be27845400 1929 */
AnnaBridge 172:65be27845400 1930 typedef struct
AnnaBridge 172:65be27845400 1931 {
AnnaBridge 172:65be27845400 1932 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 172:65be27845400 1933 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 172:65be27845400 1934 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 172:65be27845400 1935 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 172:65be27845400 1936 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 172:65be27845400 1937 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 172:65be27845400 1938 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 172:65be27845400 1939 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 172:65be27845400 1940 } USB_OTG_INEndpointTypeDef;
AnnaBridge 172:65be27845400 1941
AnnaBridge 172:65be27845400 1942
AnnaBridge 172:65be27845400 1943 /**
AnnaBridge 172:65be27845400 1944 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
AnnaBridge 172:65be27845400 1945 */
AnnaBridge 172:65be27845400 1946 typedef struct
AnnaBridge 172:65be27845400 1947 {
AnnaBridge 172:65be27845400 1948 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 172:65be27845400 1949 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 172:65be27845400 1950 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 172:65be27845400 1951 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 172:65be27845400 1952 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 172:65be27845400 1953 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 172:65be27845400 1954 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 172:65be27845400 1955 } USB_OTG_OUTEndpointTypeDef;
AnnaBridge 172:65be27845400 1956
AnnaBridge 172:65be27845400 1957
AnnaBridge 172:65be27845400 1958 /**
AnnaBridge 172:65be27845400 1959 * @brief USB_OTG_Host_Mode_Register_Structures
AnnaBridge 172:65be27845400 1960 */
AnnaBridge 172:65be27845400 1961 typedef struct
AnnaBridge 172:65be27845400 1962 {
AnnaBridge 172:65be27845400 1963 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 172:65be27845400 1964 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 172:65be27845400 1965 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 172:65be27845400 1966 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 172:65be27845400 1967 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 172:65be27845400 1968 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 172:65be27845400 1969 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 172:65be27845400 1970 } USB_OTG_HostTypeDef;
AnnaBridge 172:65be27845400 1971
AnnaBridge 172:65be27845400 1972 /**
AnnaBridge 172:65be27845400 1973 * @brief USB_OTG_Host_Channel_Specific_Registers
AnnaBridge 172:65be27845400 1974 */
AnnaBridge 172:65be27845400 1975 typedef struct
AnnaBridge 172:65be27845400 1976 {
AnnaBridge 172:65be27845400 1977 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 172:65be27845400 1978 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 172:65be27845400 1979 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 172:65be27845400 1980 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 172:65be27845400 1981 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 172:65be27845400 1982 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 172:65be27845400 1983 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 172:65be27845400 1984 } USB_OTG_HostChannelTypeDef;
AnnaBridge 172:65be27845400 1985 /**
AnnaBridge 172:65be27845400 1986 * @}
AnnaBridge 172:65be27845400 1987 */
AnnaBridge 172:65be27845400 1988
AnnaBridge 172:65be27845400 1989
AnnaBridge 172:65be27845400 1990 /** @addtogroup Peripheral_memory_map
AnnaBridge 172:65be27845400 1991 * @{
AnnaBridge 172:65be27845400 1992 */
AnnaBridge 172:65be27845400 1993 #define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
AnnaBridge 172:65be27845400 1994 #define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
AnnaBridge 172:65be27845400 1995 #define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
AnnaBridge 172:65be27845400 1996 #define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
AnnaBridge 172:65be27845400 1997 #define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
AnnaBridge 172:65be27845400 1998 #define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
AnnaBridge 172:65be27845400 1999
AnnaBridge 172:65be27845400 2000 #define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
AnnaBridge 172:65be27845400 2001 #define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
AnnaBridge 172:65be27845400 2002
AnnaBridge 172:65be27845400 2003 #define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
AnnaBridge 172:65be27845400 2004 #define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
AnnaBridge 172:65be27845400 2005
AnnaBridge 172:65be27845400 2006 #define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
AnnaBridge 172:65be27845400 2007 #define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
AnnaBridge 172:65be27845400 2008
AnnaBridge 172:65be27845400 2009 #define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
AnnaBridge 172:65be27845400 2010 #define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
AnnaBridge 172:65be27845400 2011 #define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
AnnaBridge 172:65be27845400 2012
AnnaBridge 172:65be27845400 2013 /* Legacy define */
AnnaBridge 172:65be27845400 2014 #define FLASH_BASE FLASH_BANK1_BASE
AnnaBridge 172:65be27845400 2015
AnnaBridge 172:65be27845400 2016 /*!< Device electronic signature memory map */
AnnaBridge 172:65be27845400 2017 #define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
AnnaBridge 172:65be27845400 2018 #define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
AnnaBridge 172:65be27845400 2019
AnnaBridge 172:65be27845400 2020
AnnaBridge 172:65be27845400 2021 /*!< Peripheral memory map */
AnnaBridge 172:65be27845400 2022 #define D2_APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 172:65be27845400 2023 #define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
AnnaBridge 172:65be27845400 2024 #define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
AnnaBridge 172:65be27845400 2025 #define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
AnnaBridge 172:65be27845400 2026
AnnaBridge 172:65be27845400 2027 #define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
AnnaBridge 172:65be27845400 2028 #define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
AnnaBridge 172:65be27845400 2029
AnnaBridge 172:65be27845400 2030 #define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
AnnaBridge 172:65be27845400 2031 #define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
AnnaBridge 172:65be27845400 2032
AnnaBridge 172:65be27845400 2033 /*!< Legacy Peripheral memory map */
AnnaBridge 172:65be27845400 2034 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 172:65be27845400 2035 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
AnnaBridge 172:65be27845400 2036 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
AnnaBridge 172:65be27845400 2037 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
AnnaBridge 172:65be27845400 2038
AnnaBridge 172:65be27845400 2039
AnnaBridge 172:65be27845400 2040 /*!< D1_AHB1PERIPH peripherals */
AnnaBridge 172:65be27845400 2041
AnnaBridge 172:65be27845400 2042 #define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2043 #define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
AnnaBridge 172:65be27845400 2044 #define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
AnnaBridge 172:65be27845400 2045 #define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
AnnaBridge 172:65be27845400 2046 #define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
AnnaBridge 172:65be27845400 2047 #define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
AnnaBridge 172:65be27845400 2048 #define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
AnnaBridge 172:65be27845400 2049 #define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
AnnaBridge 172:65be27845400 2050 #define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
AnnaBridge 172:65be27845400 2051 #define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
AnnaBridge 172:65be27845400 2052
AnnaBridge 172:65be27845400 2053 /*!< D2_AHB1PERIPH peripherals */
AnnaBridge 172:65be27845400 2054
AnnaBridge 172:65be27845400 2055 #define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2056 #define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
AnnaBridge 172:65be27845400 2057 #define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
AnnaBridge 172:65be27845400 2058 #define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
AnnaBridge 172:65be27845400 2059 #define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
AnnaBridge 172:65be27845400 2060 #define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
AnnaBridge 172:65be27845400 2061 #define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
AnnaBridge 172:65be27845400 2062 #define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
AnnaBridge 172:65be27845400 2063 #define ETH_MAC_BASE (ETH_BASE)
AnnaBridge 172:65be27845400 2064
AnnaBridge 172:65be27845400 2065 /*!< USB registers base address */
AnnaBridge 172:65be27845400 2066 #define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
AnnaBridge 172:65be27845400 2067 #define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
AnnaBridge 172:65be27845400 2068 #define USB_OTG_GLOBAL_BASE (0x000UL)
AnnaBridge 172:65be27845400 2069 #define USB_OTG_DEVICE_BASE (0x800UL)
AnnaBridge 172:65be27845400 2070 #define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
AnnaBridge 172:65be27845400 2071 #define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
AnnaBridge 172:65be27845400 2072 #define USB_OTG_EP_REG_SIZE (0x20UL)
AnnaBridge 172:65be27845400 2073 #define USB_OTG_HOST_BASE (0x400UL)
AnnaBridge 172:65be27845400 2074 #define USB_OTG_HOST_PORT_BASE (0x440UL)
AnnaBridge 172:65be27845400 2075 #define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
AnnaBridge 172:65be27845400 2076 #define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
AnnaBridge 172:65be27845400 2077 #define USB_OTG_PCGCCTL_BASE (0xE00UL)
AnnaBridge 172:65be27845400 2078 #define USB_OTG_FIFO_BASE (0x1000UL)
AnnaBridge 172:65be27845400 2079 #define USB_OTG_FIFO_SIZE (0x1000UL)
AnnaBridge 172:65be27845400 2080
AnnaBridge 172:65be27845400 2081 /*!< D2_AHB2PERIPH peripherals */
AnnaBridge 172:65be27845400 2082
AnnaBridge 172:65be27845400 2083 #define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2084 #define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
AnnaBridge 172:65be27845400 2085 #define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
AnnaBridge 172:65be27845400 2086 #define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
AnnaBridge 172:65be27845400 2087 #define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
AnnaBridge 172:65be27845400 2088
AnnaBridge 172:65be27845400 2089 /*!< D3_AHB1PERIPH peripherals */
AnnaBridge 172:65be27845400 2090 #define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2091 #define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
AnnaBridge 172:65be27845400 2092 #define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
AnnaBridge 172:65be27845400 2093 #define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
AnnaBridge 172:65be27845400 2094 #define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
AnnaBridge 172:65be27845400 2095 #define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
AnnaBridge 172:65be27845400 2096 #define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
AnnaBridge 172:65be27845400 2097 #define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
AnnaBridge 172:65be27845400 2098 #define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
AnnaBridge 172:65be27845400 2099 #define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
AnnaBridge 172:65be27845400 2100 #define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
AnnaBridge 172:65be27845400 2101 #define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
AnnaBridge 172:65be27845400 2102 #define RCC_C1_BASE (RCC_BASE + 0x130UL)
AnnaBridge 172:65be27845400 2103 #define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
AnnaBridge 172:65be27845400 2104 #define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
AnnaBridge 172:65be27845400 2105 #define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
AnnaBridge 172:65be27845400 2106 #define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
AnnaBridge 172:65be27845400 2107 #define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
AnnaBridge 172:65be27845400 2108 #define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
AnnaBridge 172:65be27845400 2109 #define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
AnnaBridge 172:65be27845400 2110 #define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
AnnaBridge 172:65be27845400 2111
AnnaBridge 172:65be27845400 2112 /*!< D1_APB1PERIPH peripherals */
AnnaBridge 172:65be27845400 2113 #define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
AnnaBridge 172:65be27845400 2114 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
AnnaBridge 172:65be27845400 2115 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
AnnaBridge 172:65be27845400 2116 #define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
AnnaBridge 172:65be27845400 2117
AnnaBridge 172:65be27845400 2118 /*!< D2_APB1PERIPH peripherals */
AnnaBridge 172:65be27845400 2119 #define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2120 #define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
AnnaBridge 172:65be27845400 2121 #define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
AnnaBridge 172:65be27845400 2122 #define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
AnnaBridge 172:65be27845400 2123 #define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
AnnaBridge 172:65be27845400 2124 #define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
AnnaBridge 172:65be27845400 2125 #define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
AnnaBridge 172:65be27845400 2126 #define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
AnnaBridge 172:65be27845400 2127 #define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
AnnaBridge 172:65be27845400 2128 #define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
AnnaBridge 172:65be27845400 2129
AnnaBridge 172:65be27845400 2130
AnnaBridge 172:65be27845400 2131 #define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
AnnaBridge 172:65be27845400 2132 #define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
AnnaBridge 172:65be27845400 2133 #define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
AnnaBridge 172:65be27845400 2134 #define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
AnnaBridge 172:65be27845400 2135 #define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
AnnaBridge 172:65be27845400 2136 #define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
AnnaBridge 172:65be27845400 2137 #define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
AnnaBridge 172:65be27845400 2138 #define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
AnnaBridge 172:65be27845400 2139 #define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
AnnaBridge 172:65be27845400 2140 #define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
AnnaBridge 172:65be27845400 2141 #define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
AnnaBridge 172:65be27845400 2142 #define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
AnnaBridge 172:65be27845400 2143 #define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
AnnaBridge 172:65be27845400 2144 #define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
AnnaBridge 172:65be27845400 2145 #define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
AnnaBridge 172:65be27845400 2146 #define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
AnnaBridge 172:65be27845400 2147 #define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
AnnaBridge 172:65be27845400 2148 #define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
AnnaBridge 172:65be27845400 2149 #define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
AnnaBridge 172:65be27845400 2150 #define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
AnnaBridge 172:65be27845400 2151 #define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
AnnaBridge 172:65be27845400 2152 #define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
AnnaBridge 172:65be27845400 2153 #define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
AnnaBridge 172:65be27845400 2154 #define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
AnnaBridge 172:65be27845400 2155
AnnaBridge 172:65be27845400 2156 /*!< D2_APB2PERIPH peripherals */
AnnaBridge 172:65be27845400 2157
AnnaBridge 172:65be27845400 2158 #define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2159 #define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
AnnaBridge 172:65be27845400 2160 #define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
AnnaBridge 172:65be27845400 2161 #define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
AnnaBridge 172:65be27845400 2162 #define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
AnnaBridge 172:65be27845400 2163 #define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
AnnaBridge 172:65be27845400 2164 #define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
AnnaBridge 172:65be27845400 2165 #define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
AnnaBridge 172:65be27845400 2166 #define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
AnnaBridge 172:65be27845400 2167 #define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
AnnaBridge 172:65be27845400 2168 #define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
AnnaBridge 172:65be27845400 2169 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
AnnaBridge 172:65be27845400 2170 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
AnnaBridge 172:65be27845400 2171 #define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
AnnaBridge 172:65be27845400 2172 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
AnnaBridge 172:65be27845400 2173 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
AnnaBridge 172:65be27845400 2174 #define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
AnnaBridge 172:65be27845400 2175 #define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
AnnaBridge 172:65be27845400 2176 #define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
AnnaBridge 172:65be27845400 2177 #define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
AnnaBridge 172:65be27845400 2178 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
AnnaBridge 172:65be27845400 2179 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
AnnaBridge 172:65be27845400 2180 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
AnnaBridge 172:65be27845400 2181 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
AnnaBridge 172:65be27845400 2182 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
AnnaBridge 172:65be27845400 2183 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
AnnaBridge 172:65be27845400 2184 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
AnnaBridge 172:65be27845400 2185 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
AnnaBridge 172:65be27845400 2186 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
AnnaBridge 172:65be27845400 2187 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
AnnaBridge 172:65be27845400 2188 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
AnnaBridge 172:65be27845400 2189 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
AnnaBridge 172:65be27845400 2190 #define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
AnnaBridge 172:65be27845400 2191 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
AnnaBridge 172:65be27845400 2192 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
AnnaBridge 172:65be27845400 2193 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
AnnaBridge 172:65be27845400 2194 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
AnnaBridge 172:65be27845400 2195 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
AnnaBridge 172:65be27845400 2196 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
AnnaBridge 172:65be27845400 2197
AnnaBridge 172:65be27845400 2198
AnnaBridge 172:65be27845400 2199 /*!< D3_APB1PERIPH peripherals */
AnnaBridge 172:65be27845400 2200 #define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2201 #define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
AnnaBridge 172:65be27845400 2202 #define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
AnnaBridge 172:65be27845400 2203 #define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
AnnaBridge 172:65be27845400 2204 #define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
AnnaBridge 172:65be27845400 2205 #define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
AnnaBridge 172:65be27845400 2206 #define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
AnnaBridge 172:65be27845400 2207 #define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
AnnaBridge 172:65be27845400 2208 #define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
AnnaBridge 172:65be27845400 2209 #define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
AnnaBridge 172:65be27845400 2210 #define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
AnnaBridge 172:65be27845400 2211 #define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
AnnaBridge 172:65be27845400 2212 #define COMP1_BASE (COMP12_BASE + 0x0CUL)
AnnaBridge 172:65be27845400 2213 #define COMP2_BASE (COMP12_BASE + 0x10UL)
AnnaBridge 172:65be27845400 2214 #define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
AnnaBridge 172:65be27845400 2215 #define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
AnnaBridge 172:65be27845400 2216 #define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
AnnaBridge 172:65be27845400 2217
AnnaBridge 172:65be27845400 2218
AnnaBridge 172:65be27845400 2219 #define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
AnnaBridge 172:65be27845400 2220 #define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
AnnaBridge 172:65be27845400 2221 #define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
AnnaBridge 172:65be27845400 2222
AnnaBridge 172:65be27845400 2223
AnnaBridge 172:65be27845400 2224
AnnaBridge 172:65be27845400 2225
AnnaBridge 172:65be27845400 2226 #define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
AnnaBridge 172:65be27845400 2227 #define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
AnnaBridge 172:65be27845400 2228 #define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
AnnaBridge 172:65be27845400 2229 #define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
AnnaBridge 172:65be27845400 2230 #define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
AnnaBridge 172:65be27845400 2231 #define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
AnnaBridge 172:65be27845400 2232 #define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
AnnaBridge 172:65be27845400 2233 #define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
AnnaBridge 172:65be27845400 2234
AnnaBridge 172:65be27845400 2235 #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
AnnaBridge 172:65be27845400 2236 #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
AnnaBridge 172:65be27845400 2237 #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
AnnaBridge 172:65be27845400 2238 #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
AnnaBridge 172:65be27845400 2239 #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
AnnaBridge 172:65be27845400 2240 #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
AnnaBridge 172:65be27845400 2241 #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
AnnaBridge 172:65be27845400 2242 #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
AnnaBridge 172:65be27845400 2243
AnnaBridge 172:65be27845400 2244 #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
AnnaBridge 172:65be27845400 2245 #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
AnnaBridge 172:65be27845400 2246 #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
AnnaBridge 172:65be27845400 2247 #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
AnnaBridge 172:65be27845400 2248 #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
AnnaBridge 172:65be27845400 2249 #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
AnnaBridge 172:65be27845400 2250 #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
AnnaBridge 172:65be27845400 2251 #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
AnnaBridge 172:65be27845400 2252
AnnaBridge 172:65be27845400 2253 #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
AnnaBridge 172:65be27845400 2254 #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
AnnaBridge 172:65be27845400 2255
AnnaBridge 172:65be27845400 2256 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
AnnaBridge 172:65be27845400 2257 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
AnnaBridge 172:65be27845400 2258 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
AnnaBridge 172:65be27845400 2259 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
AnnaBridge 172:65be27845400 2260 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
AnnaBridge 172:65be27845400 2261 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
AnnaBridge 172:65be27845400 2262 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
AnnaBridge 172:65be27845400 2263 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
AnnaBridge 172:65be27845400 2264
AnnaBridge 172:65be27845400 2265 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
AnnaBridge 172:65be27845400 2266 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
AnnaBridge 172:65be27845400 2267 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
AnnaBridge 172:65be27845400 2268 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
AnnaBridge 172:65be27845400 2269 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
AnnaBridge 172:65be27845400 2270 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
AnnaBridge 172:65be27845400 2271 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
AnnaBridge 172:65be27845400 2272 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
AnnaBridge 172:65be27845400 2273
AnnaBridge 172:65be27845400 2274 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
AnnaBridge 172:65be27845400 2275 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
AnnaBridge 172:65be27845400 2276 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
AnnaBridge 172:65be27845400 2277 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
AnnaBridge 172:65be27845400 2278 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
AnnaBridge 172:65be27845400 2279 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
AnnaBridge 172:65be27845400 2280 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
AnnaBridge 172:65be27845400 2281 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
AnnaBridge 172:65be27845400 2282 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
AnnaBridge 172:65be27845400 2283 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
AnnaBridge 172:65be27845400 2284 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
AnnaBridge 172:65be27845400 2285 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
AnnaBridge 172:65be27845400 2286 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
AnnaBridge 172:65be27845400 2287 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
AnnaBridge 172:65be27845400 2288 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
AnnaBridge 172:65be27845400 2289 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
AnnaBridge 172:65be27845400 2290
AnnaBridge 172:65be27845400 2291 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
AnnaBridge 172:65be27845400 2292 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
AnnaBridge 172:65be27845400 2293 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
AnnaBridge 172:65be27845400 2294 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
AnnaBridge 172:65be27845400 2295 #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
AnnaBridge 172:65be27845400 2296 #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
AnnaBridge 172:65be27845400 2297 #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
AnnaBridge 172:65be27845400 2298 #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
AnnaBridge 172:65be27845400 2299
AnnaBridge 172:65be27845400 2300 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
AnnaBridge 172:65be27845400 2301 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
AnnaBridge 172:65be27845400 2302
AnnaBridge 172:65be27845400 2303 /*!< FMC Banks registers base address */
AnnaBridge 172:65be27845400 2304 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
AnnaBridge 172:65be27845400 2305 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
AnnaBridge 172:65be27845400 2306 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
AnnaBridge 172:65be27845400 2307 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
AnnaBridge 172:65be27845400 2308 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
AnnaBridge 172:65be27845400 2309
AnnaBridge 172:65be27845400 2310 /* Debug MCU registers base address */
AnnaBridge 172:65be27845400 2311 #define DBGMCU_BASE (0x5C001000UL)
AnnaBridge 172:65be27845400 2312
AnnaBridge 172:65be27845400 2313 #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
AnnaBridge 172:65be27845400 2314 #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
AnnaBridge 172:65be27845400 2315 #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
AnnaBridge 172:65be27845400 2316 #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
AnnaBridge 172:65be27845400 2317 #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
AnnaBridge 172:65be27845400 2318 #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
AnnaBridge 172:65be27845400 2319 #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
AnnaBridge 172:65be27845400 2320 #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
AnnaBridge 172:65be27845400 2321 #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
AnnaBridge 172:65be27845400 2322 #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
AnnaBridge 172:65be27845400 2323 #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
AnnaBridge 172:65be27845400 2324 #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
AnnaBridge 172:65be27845400 2325 #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
AnnaBridge 172:65be27845400 2326 #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
AnnaBridge 172:65be27845400 2327 #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
AnnaBridge 172:65be27845400 2328 #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
AnnaBridge 172:65be27845400 2329
AnnaBridge 172:65be27845400 2330 #define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
AnnaBridge 172:65be27845400 2331 #define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
AnnaBridge 172:65be27845400 2332 #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
AnnaBridge 172:65be27845400 2333 #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
AnnaBridge 172:65be27845400 2334 #define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
AnnaBridge 172:65be27845400 2335
AnnaBridge 172:65be27845400 2336 #define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
AnnaBridge 172:65be27845400 2337 #define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
AnnaBridge 172:65be27845400 2338 #define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
AnnaBridge 172:65be27845400 2339 #define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
AnnaBridge 172:65be27845400 2340 #define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
AnnaBridge 172:65be27845400 2341
AnnaBridge 172:65be27845400 2342 #define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
AnnaBridge 172:65be27845400 2343 #define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
AnnaBridge 172:65be27845400 2344
AnnaBridge 172:65be27845400 2345
AnnaBridge 172:65be27845400 2346 /**
AnnaBridge 172:65be27845400 2347 * @}
AnnaBridge 172:65be27845400 2348 */
AnnaBridge 172:65be27845400 2349
AnnaBridge 172:65be27845400 2350 /** @addtogroup Peripheral_declaration
AnnaBridge 172:65be27845400 2351 * @{
AnnaBridge 172:65be27845400 2352 */
AnnaBridge 172:65be27845400 2353 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 172:65be27845400 2354 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 172:65be27845400 2355 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 172:65be27845400 2356 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 172:65be27845400 2357 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 172:65be27845400 2358 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 172:65be27845400 2359 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
AnnaBridge 172:65be27845400 2360 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
AnnaBridge 172:65be27845400 2361 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
AnnaBridge 172:65be27845400 2362 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 172:65be27845400 2363 #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
AnnaBridge 172:65be27845400 2364
AnnaBridge 172:65be27845400 2365
AnnaBridge 172:65be27845400 2366 #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
AnnaBridge 172:65be27845400 2367 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 172:65be27845400 2368 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 172:65be27845400 2369 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
AnnaBridge 172:65be27845400 2370 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
AnnaBridge 172:65be27845400 2371 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
AnnaBridge 172:65be27845400 2372 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 172:65be27845400 2373 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 172:65be27845400 2374 #define USART6 ((USART_TypeDef *) USART6_BASE)
AnnaBridge 172:65be27845400 2375 #define UART7 ((USART_TypeDef *) UART7_BASE)
AnnaBridge 172:65be27845400 2376 #define UART8 ((USART_TypeDef *) UART8_BASE)
AnnaBridge 172:65be27845400 2377 #define CRS ((CRS_TypeDef *) CRS_BASE)
AnnaBridge 172:65be27845400 2378 #define UART4 ((USART_TypeDef *) UART4_BASE)
AnnaBridge 172:65be27845400 2379 #define UART5 ((USART_TypeDef *) UART5_BASE)
AnnaBridge 172:65be27845400 2380 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 172:65be27845400 2381 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 172:65be27845400 2382 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
AnnaBridge 172:65be27845400 2383 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
AnnaBridge 172:65be27845400 2384 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
AnnaBridge 172:65be27845400 2385 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
AnnaBridge 172:65be27845400 2386 #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
AnnaBridge 172:65be27845400 2387 #define CEC ((CEC_TypeDef *) CEC_BASE)
AnnaBridge 172:65be27845400 2388 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
AnnaBridge 172:65be27845400 2389 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 172:65be27845400 2390 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
AnnaBridge 172:65be27845400 2391 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
AnnaBridge 172:65be27845400 2392 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
AnnaBridge 172:65be27845400 2393 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
AnnaBridge 172:65be27845400 2394 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
AnnaBridge 172:65be27845400 2395 #define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
AnnaBridge 172:65be27845400 2396 #define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
AnnaBridge 172:65be27845400 2397
AnnaBridge 172:65be27845400 2398 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 172:65be27845400 2399 #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
AnnaBridge 172:65be27845400 2400 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
AnnaBridge 172:65be27845400 2401 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
AnnaBridge 172:65be27845400 2402 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
AnnaBridge 172:65be27845400 2403 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
AnnaBridge 172:65be27845400 2404 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
AnnaBridge 172:65be27845400 2405 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
AnnaBridge 172:65be27845400 2406
AnnaBridge 172:65be27845400 2407
AnnaBridge 172:65be27845400 2408 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 172:65be27845400 2409 #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
AnnaBridge 172:65be27845400 2410 #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
AnnaBridge 172:65be27845400 2411 #define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE)
AnnaBridge 172:65be27845400 2412 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 172:65be27845400 2413 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 172:65be27845400 2414 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
AnnaBridge 172:65be27845400 2415 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 172:65be27845400 2416 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
AnnaBridge 172:65be27845400 2417 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
AnnaBridge 172:65be27845400 2418 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
AnnaBridge 172:65be27845400 2419 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
AnnaBridge 172:65be27845400 2420 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
AnnaBridge 172:65be27845400 2421 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
AnnaBridge 172:65be27845400 2422 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
AnnaBridge 172:65be27845400 2423 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
AnnaBridge 172:65be27845400 2424 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
AnnaBridge 172:65be27845400 2425 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
AnnaBridge 172:65be27845400 2426 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
AnnaBridge 172:65be27845400 2427 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
AnnaBridge 172:65be27845400 2428 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
AnnaBridge 172:65be27845400 2429 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
AnnaBridge 172:65be27845400 2430 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
AnnaBridge 172:65be27845400 2431 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
AnnaBridge 172:65be27845400 2432 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
AnnaBridge 172:65be27845400 2433 #define SAI3 ((SAI_TypeDef *) SAI3_BASE)
AnnaBridge 172:65be27845400 2434 #define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
AnnaBridge 172:65be27845400 2435 #define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
AnnaBridge 172:65be27845400 2436 #define SAI4 ((SAI_TypeDef *) SAI4_BASE)
AnnaBridge 172:65be27845400 2437 #define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
AnnaBridge 172:65be27845400 2438 #define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
AnnaBridge 172:65be27845400 2439
AnnaBridge 172:65be27845400 2440 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
AnnaBridge 172:65be27845400 2441 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
AnnaBridge 172:65be27845400 2442 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
AnnaBridge 172:65be27845400 2443 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
AnnaBridge 172:65be27845400 2444 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
AnnaBridge 172:65be27845400 2445 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
AnnaBridge 172:65be27845400 2446 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
AnnaBridge 172:65be27845400 2447 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
AnnaBridge 172:65be27845400 2448 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
AnnaBridge 172:65be27845400 2449 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
AnnaBridge 172:65be27845400 2450 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
AnnaBridge 172:65be27845400 2451 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
AnnaBridge 172:65be27845400 2452 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
AnnaBridge 172:65be27845400 2453 #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
AnnaBridge 172:65be27845400 2454 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
AnnaBridge 172:65be27845400 2455 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 172:65be27845400 2456 #define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
AnnaBridge 172:65be27845400 2457 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 172:65be27845400 2458 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 172:65be27845400 2459
AnnaBridge 172:65be27845400 2460 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 172:65be27845400 2461 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 172:65be27845400 2462 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 172:65be27845400 2463 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 172:65be27845400 2464 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 172:65be27845400 2465 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 172:65be27845400 2466 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
AnnaBridge 172:65be27845400 2467 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 172:65be27845400 2468 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
AnnaBridge 172:65be27845400 2469 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
AnnaBridge 172:65be27845400 2470 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
AnnaBridge 172:65be27845400 2471
AnnaBridge 172:65be27845400 2472 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 172:65be27845400 2473 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
AnnaBridge 172:65be27845400 2474 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
AnnaBridge 172:65be27845400 2475 #define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
AnnaBridge 172:65be27845400 2476 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
AnnaBridge 172:65be27845400 2477
AnnaBridge 172:65be27845400 2478 #define RNG ((RNG_TypeDef *) RNG_BASE)
AnnaBridge 172:65be27845400 2479 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
AnnaBridge 172:65be27845400 2480 #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
AnnaBridge 172:65be27845400 2481
AnnaBridge 172:65be27845400 2482 #define BDMA ((BDMA_TypeDef *) BDMA_BASE)
AnnaBridge 172:65be27845400 2483 #define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
AnnaBridge 172:65be27845400 2484 #define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
AnnaBridge 172:65be27845400 2485 #define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
AnnaBridge 172:65be27845400 2486 #define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
AnnaBridge 172:65be27845400 2487 #define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
AnnaBridge 172:65be27845400 2488 #define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
AnnaBridge 172:65be27845400 2489 #define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
AnnaBridge 172:65be27845400 2490 #define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
AnnaBridge 172:65be27845400 2491
AnnaBridge 172:65be27845400 2492 #define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
AnnaBridge 172:65be27845400 2493 #define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
AnnaBridge 172:65be27845400 2494 #define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
AnnaBridge 172:65be27845400 2495 #define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
AnnaBridge 172:65be27845400 2496 #define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
AnnaBridge 172:65be27845400 2497 #define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
AnnaBridge 172:65be27845400 2498
AnnaBridge 172:65be27845400 2499 #define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
AnnaBridge 172:65be27845400 2500 #define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
AnnaBridge 172:65be27845400 2501 #define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
AnnaBridge 172:65be27845400 2502 #define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
AnnaBridge 172:65be27845400 2503 #define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
AnnaBridge 172:65be27845400 2504 #define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
AnnaBridge 172:65be27845400 2505
AnnaBridge 172:65be27845400 2506 #define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
AnnaBridge 172:65be27845400 2507 #define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
AnnaBridge 172:65be27845400 2508 #define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
AnnaBridge 172:65be27845400 2509
AnnaBridge 172:65be27845400 2510 #define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
AnnaBridge 172:65be27845400 2511 #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
AnnaBridge 172:65be27845400 2512 #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
AnnaBridge 172:65be27845400 2513 #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
AnnaBridge 172:65be27845400 2514 #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
AnnaBridge 172:65be27845400 2515 #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
AnnaBridge 172:65be27845400 2516 #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
AnnaBridge 172:65be27845400 2517 #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
AnnaBridge 172:65be27845400 2518 #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
AnnaBridge 172:65be27845400 2519
AnnaBridge 172:65be27845400 2520
AnnaBridge 172:65be27845400 2521 #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
AnnaBridge 172:65be27845400 2522 #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
AnnaBridge 172:65be27845400 2523 #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
AnnaBridge 172:65be27845400 2524 #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
AnnaBridge 172:65be27845400 2525 #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
AnnaBridge 172:65be27845400 2526 #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
AnnaBridge 172:65be27845400 2527 #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
AnnaBridge 172:65be27845400 2528 #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
AnnaBridge 172:65be27845400 2529
AnnaBridge 172:65be27845400 2530 #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
AnnaBridge 172:65be27845400 2531 #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
AnnaBridge 172:65be27845400 2532
AnnaBridge 172:65be27845400 2533 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 172:65be27845400 2534 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
AnnaBridge 172:65be27845400 2535 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
AnnaBridge 172:65be27845400 2536 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
AnnaBridge 172:65be27845400 2537 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
AnnaBridge 172:65be27845400 2538 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
AnnaBridge 172:65be27845400 2539 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
AnnaBridge 172:65be27845400 2540 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
AnnaBridge 172:65be27845400 2541 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
AnnaBridge 172:65be27845400 2542
AnnaBridge 172:65be27845400 2543 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 172:65be27845400 2544 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
AnnaBridge 172:65be27845400 2545 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
AnnaBridge 172:65be27845400 2546 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
AnnaBridge 172:65be27845400 2547 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
AnnaBridge 172:65be27845400 2548 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
AnnaBridge 172:65be27845400 2549 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
AnnaBridge 172:65be27845400 2550 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
AnnaBridge 172:65be27845400 2551 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
AnnaBridge 172:65be27845400 2552
AnnaBridge 172:65be27845400 2553
AnnaBridge 172:65be27845400 2554 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
AnnaBridge 172:65be27845400 2555 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
AnnaBridge 172:65be27845400 2556 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
AnnaBridge 172:65be27845400 2557 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
AnnaBridge 172:65be27845400 2558 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
AnnaBridge 172:65be27845400 2559 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
AnnaBridge 172:65be27845400 2560 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
AnnaBridge 172:65be27845400 2561 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
AnnaBridge 172:65be27845400 2562 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
AnnaBridge 172:65be27845400 2563 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
AnnaBridge 172:65be27845400 2564 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
AnnaBridge 172:65be27845400 2565 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
AnnaBridge 172:65be27845400 2566 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
AnnaBridge 172:65be27845400 2567 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
AnnaBridge 172:65be27845400 2568 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
AnnaBridge 172:65be27845400 2569 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
AnnaBridge 172:65be27845400 2570 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
AnnaBridge 172:65be27845400 2571
AnnaBridge 172:65be27845400 2572 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
AnnaBridge 172:65be27845400 2573 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
AnnaBridge 172:65be27845400 2574 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
AnnaBridge 172:65be27845400 2575 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
AnnaBridge 172:65be27845400 2576 #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
AnnaBridge 172:65be27845400 2577 #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
AnnaBridge 172:65be27845400 2578 #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
AnnaBridge 172:65be27845400 2579 #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
AnnaBridge 172:65be27845400 2580
AnnaBridge 172:65be27845400 2581 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
AnnaBridge 172:65be27845400 2582 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
AnnaBridge 172:65be27845400 2583
AnnaBridge 172:65be27845400 2584
AnnaBridge 172:65be27845400 2585 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
AnnaBridge 172:65be27845400 2586 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
AnnaBridge 172:65be27845400 2587 #define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
AnnaBridge 172:65be27845400 2588 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
AnnaBridge 172:65be27845400 2589 #define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
AnnaBridge 172:65be27845400 2590
AnnaBridge 172:65be27845400 2591
AnnaBridge 172:65be27845400 2592 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
AnnaBridge 172:65be27845400 2593 #define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
AnnaBridge 172:65be27845400 2594 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
AnnaBridge 172:65be27845400 2595 #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
AnnaBridge 172:65be27845400 2596
AnnaBridge 172:65be27845400 2597 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 172:65be27845400 2598
AnnaBridge 172:65be27845400 2599 #define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
AnnaBridge 172:65be27845400 2600 #define HSEM ((HSEM_TypeDef *) HSEM_BASE)
AnnaBridge 172:65be27845400 2601 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
AnnaBridge 172:65be27845400 2602
AnnaBridge 172:65be27845400 2603 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
AnnaBridge 172:65be27845400 2604 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
AnnaBridge 172:65be27845400 2605 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
AnnaBridge 172:65be27845400 2606
AnnaBridge 172:65be27845400 2607 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
AnnaBridge 172:65be27845400 2608
AnnaBridge 172:65be27845400 2609 #define ETH ((ETH_TypeDef *)ETH_BASE)
AnnaBridge 172:65be27845400 2610 #define MDMA ((MDMA_TypeDef *)MDMA_BASE)
AnnaBridge 172:65be27845400 2611 #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
AnnaBridge 172:65be27845400 2612 #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
AnnaBridge 172:65be27845400 2613 #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
AnnaBridge 172:65be27845400 2614 #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
AnnaBridge 172:65be27845400 2615 #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
AnnaBridge 172:65be27845400 2616 #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
AnnaBridge 172:65be27845400 2617 #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
AnnaBridge 172:65be27845400 2618 #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
AnnaBridge 172:65be27845400 2619 #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
AnnaBridge 172:65be27845400 2620 #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
AnnaBridge 172:65be27845400 2621 #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
AnnaBridge 172:65be27845400 2622 #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
AnnaBridge 172:65be27845400 2623 #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
AnnaBridge 172:65be27845400 2624 #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
AnnaBridge 172:65be27845400 2625 #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
AnnaBridge 172:65be27845400 2626 #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
AnnaBridge 172:65be27845400 2627
AnnaBridge 172:65be27845400 2628
AnnaBridge 172:65be27845400 2629 #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
AnnaBridge 172:65be27845400 2630 #define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
AnnaBridge 172:65be27845400 2631
AnnaBridge 172:65be27845400 2632 /* Legacy defines */
AnnaBridge 172:65be27845400 2633 #define USB_OTG_HS USB1_OTG_HS
AnnaBridge 172:65be27845400 2634 #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
AnnaBridge 172:65be27845400 2635 #define USB_OTG_FS USB2_OTG_FS
AnnaBridge 172:65be27845400 2636 #define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
AnnaBridge 172:65be27845400 2637
AnnaBridge 172:65be27845400 2638 /**
AnnaBridge 172:65be27845400 2639 * @}
AnnaBridge 172:65be27845400 2640 */
AnnaBridge 172:65be27845400 2641
AnnaBridge 172:65be27845400 2642 /** @addtogroup Exported_constants
AnnaBridge 172:65be27845400 2643 * @{
AnnaBridge 172:65be27845400 2644 */
AnnaBridge 172:65be27845400 2645
AnnaBridge 172:65be27845400 2646 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 172:65be27845400 2647 * @{
AnnaBridge 172:65be27845400 2648 */
AnnaBridge 172:65be27845400 2649
AnnaBridge 172:65be27845400 2650 /******************************************************************************/
AnnaBridge 172:65be27845400 2651 /* Peripheral Registers_Bits_Definition */
AnnaBridge 172:65be27845400 2652 /******************************************************************************/
AnnaBridge 172:65be27845400 2653
AnnaBridge 172:65be27845400 2654 /******************************************************************************/
AnnaBridge 172:65be27845400 2655 /* */
AnnaBridge 172:65be27845400 2656 /* Analog to Digital Converter */
AnnaBridge 172:65be27845400 2657 /* */
AnnaBridge 172:65be27845400 2658 /******************************************************************************/
AnnaBridge 172:65be27845400 2659 /******************** Bit definition for ADC_ISR register ********************/
AnnaBridge 172:65be27845400 2660 #define ADC_ISR_ADRDY_Pos (0U)
AnnaBridge 172:65be27845400 2661 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2662 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
AnnaBridge 172:65be27845400 2663 #define ADC_ISR_EOSMP_Pos (1U)
AnnaBridge 172:65be27845400 2664 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2665 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
AnnaBridge 172:65be27845400 2666 #define ADC_ISR_EOC_Pos (2U)
AnnaBridge 172:65be27845400 2667 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2668 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
AnnaBridge 172:65be27845400 2669 #define ADC_ISR_EOS_Pos (3U)
AnnaBridge 172:65be27845400 2670 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2671 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
AnnaBridge 172:65be27845400 2672 #define ADC_ISR_OVR_Pos (4U)
AnnaBridge 172:65be27845400 2673 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2674 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
AnnaBridge 172:65be27845400 2675 #define ADC_ISR_JEOC_Pos (5U)
AnnaBridge 172:65be27845400 2676 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2677 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
AnnaBridge 172:65be27845400 2678 #define ADC_ISR_JEOS_Pos (6U)
AnnaBridge 172:65be27845400 2679 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2680 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
AnnaBridge 172:65be27845400 2681 #define ADC_ISR_AWD1_Pos (7U)
AnnaBridge 172:65be27845400 2682 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2683 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
AnnaBridge 172:65be27845400 2684 #define ADC_ISR_AWD2_Pos (8U)
AnnaBridge 172:65be27845400 2685 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2686 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
AnnaBridge 172:65be27845400 2687 #define ADC_ISR_AWD3_Pos (9U)
AnnaBridge 172:65be27845400 2688 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2689 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
AnnaBridge 172:65be27845400 2690 #define ADC_ISR_JQOVF_Pos (10U)
AnnaBridge 172:65be27845400 2691 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2692 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
AnnaBridge 172:65be27845400 2693
AnnaBridge 172:65be27845400 2694 /******************** Bit definition for ADC_IER register ********************/
AnnaBridge 172:65be27845400 2695 #define ADC_IER_ADRDYIE_Pos (0U)
AnnaBridge 172:65be27845400 2696 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2697 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
AnnaBridge 172:65be27845400 2698 #define ADC_IER_EOSMPIE_Pos (1U)
AnnaBridge 172:65be27845400 2699 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2700 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
AnnaBridge 172:65be27845400 2701 #define ADC_IER_EOCIE_Pos (2U)
AnnaBridge 172:65be27845400 2702 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2703 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
AnnaBridge 172:65be27845400 2704 #define ADC_IER_EOSIE_Pos (3U)
AnnaBridge 172:65be27845400 2705 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2706 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
AnnaBridge 172:65be27845400 2707 #define ADC_IER_OVRIE_Pos (4U)
AnnaBridge 172:65be27845400 2708 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2709 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
AnnaBridge 172:65be27845400 2710 #define ADC_IER_JEOCIE_Pos (5U)
AnnaBridge 172:65be27845400 2711 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2712 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
AnnaBridge 172:65be27845400 2713 #define ADC_IER_JEOSIE_Pos (6U)
AnnaBridge 172:65be27845400 2714 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2715 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
AnnaBridge 172:65be27845400 2716 #define ADC_IER_AWD1IE_Pos (7U)
AnnaBridge 172:65be27845400 2717 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2718 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
AnnaBridge 172:65be27845400 2719 #define ADC_IER_AWD2IE_Pos (8U)
AnnaBridge 172:65be27845400 2720 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2721 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
AnnaBridge 172:65be27845400 2722 #define ADC_IER_AWD3IE_Pos (9U)
AnnaBridge 172:65be27845400 2723 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2724 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
AnnaBridge 172:65be27845400 2725 #define ADC_IER_JQOVFIE_Pos (10U)
AnnaBridge 172:65be27845400 2726 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2727 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
AnnaBridge 172:65be27845400 2728
AnnaBridge 172:65be27845400 2729 /******************** Bit definition for ADC_CR register ********************/
AnnaBridge 172:65be27845400 2730 #define ADC_CR_ADEN_Pos (0U)
AnnaBridge 172:65be27845400 2731 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2732 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
AnnaBridge 172:65be27845400 2733 #define ADC_CR_ADDIS_Pos (1U)
AnnaBridge 172:65be27845400 2734 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2735 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
AnnaBridge 172:65be27845400 2736 #define ADC_CR_ADSTART_Pos (2U)
AnnaBridge 172:65be27845400 2737 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2738 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
AnnaBridge 172:65be27845400 2739 #define ADC_CR_JADSTART_Pos (3U)
AnnaBridge 172:65be27845400 2740 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2741 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
AnnaBridge 172:65be27845400 2742 #define ADC_CR_ADSTP_Pos (4U)
AnnaBridge 172:65be27845400 2743 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2744 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
AnnaBridge 172:65be27845400 2745 #define ADC_CR_JADSTP_Pos (5U)
AnnaBridge 172:65be27845400 2746 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2747 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
AnnaBridge 172:65be27845400 2748 #define ADC_CR_BOOST_Pos (8U)
AnnaBridge 172:65be27845400 2749 #define ADC_CR_BOOST_Msk (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2750 #define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
AnnaBridge 172:65be27845400 2751 #define ADC_CR_ADCALLIN_Pos (16U)
AnnaBridge 172:65be27845400 2752 #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2753 #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
AnnaBridge 172:65be27845400 2754 #define ADC_CR_LINCALRDYW1_Pos (22U)
AnnaBridge 172:65be27845400 2755 #define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2756 #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
AnnaBridge 172:65be27845400 2757 #define ADC_CR_LINCALRDYW2_Pos (23U)
AnnaBridge 172:65be27845400 2758 #define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2759 #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
AnnaBridge 172:65be27845400 2760 #define ADC_CR_LINCALRDYW3_Pos (24U)
AnnaBridge 172:65be27845400 2761 #define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2762 #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
AnnaBridge 172:65be27845400 2763 #define ADC_CR_LINCALRDYW4_Pos (25U)
AnnaBridge 172:65be27845400 2764 #define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2765 #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
AnnaBridge 172:65be27845400 2766 #define ADC_CR_LINCALRDYW5_Pos (26U)
AnnaBridge 172:65be27845400 2767 #define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2768 #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
AnnaBridge 172:65be27845400 2769 #define ADC_CR_LINCALRDYW6_Pos (27U)
AnnaBridge 172:65be27845400 2770 #define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2771 #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
AnnaBridge 172:65be27845400 2772 #define ADC_CR_ADVREGEN_Pos (28U)
AnnaBridge 172:65be27845400 2773 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 2774 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
AnnaBridge 172:65be27845400 2775 #define ADC_CR_DEEPPWD_Pos (29U)
AnnaBridge 172:65be27845400 2776 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 2777 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
AnnaBridge 172:65be27845400 2778 #define ADC_CR_ADCALDIF_Pos (30U)
AnnaBridge 172:65be27845400 2779 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 2780 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
AnnaBridge 172:65be27845400 2781 #define ADC_CR_ADCAL_Pos (31U)
AnnaBridge 172:65be27845400 2782 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 2783 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
AnnaBridge 172:65be27845400 2784
AnnaBridge 172:65be27845400 2785 /******************** Bit definition for ADC_CFGR register ********************/
AnnaBridge 172:65be27845400 2786 #define ADC_CFGR_DMNGT_Pos (0U)
AnnaBridge 172:65be27845400 2787 #define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 2788 #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
AnnaBridge 172:65be27845400 2789 #define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2790 #define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2791
AnnaBridge 172:65be27845400 2792 #define ADC_CFGR_RES_Pos (2U)
AnnaBridge 172:65be27845400 2793 #define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
AnnaBridge 172:65be27845400 2794 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
AnnaBridge 172:65be27845400 2795 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2796 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2797 #define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2798
AnnaBridge 172:65be27845400 2799 #define ADC_CFGR_EXTSEL_Pos (5U)
AnnaBridge 172:65be27845400 2800 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
AnnaBridge 172:65be27845400 2801 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
AnnaBridge 172:65be27845400 2802 #define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2803 #define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2804 #define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2805 #define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2806 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2807
AnnaBridge 172:65be27845400 2808 #define ADC_CFGR_EXTEN_Pos (10U)
AnnaBridge 172:65be27845400 2809 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 2810 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
AnnaBridge 172:65be27845400 2811 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2812 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2813
AnnaBridge 172:65be27845400 2814 #define ADC_CFGR_OVRMOD_Pos (12U)
AnnaBridge 172:65be27845400 2815 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2816 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
AnnaBridge 172:65be27845400 2817 #define ADC_CFGR_CONT_Pos (13U)
AnnaBridge 172:65be27845400 2818 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2819 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
AnnaBridge 172:65be27845400 2820 #define ADC_CFGR_AUTDLY_Pos (14U)
AnnaBridge 172:65be27845400 2821 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2822 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
AnnaBridge 172:65be27845400 2823
AnnaBridge 172:65be27845400 2824 #define ADC_CFGR_DISCEN_Pos (16U)
AnnaBridge 172:65be27845400 2825 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2826 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
AnnaBridge 172:65be27845400 2827
AnnaBridge 172:65be27845400 2828 #define ADC_CFGR_DISCNUM_Pos (17U)
AnnaBridge 172:65be27845400 2829 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 2830 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
AnnaBridge 172:65be27845400 2831 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2832 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2833 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2834
AnnaBridge 172:65be27845400 2835 #define ADC_CFGR_JDISCEN_Pos (20U)
AnnaBridge 172:65be27845400 2836 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2837 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
AnnaBridge 172:65be27845400 2838 #define ADC_CFGR_JQM_Pos (21U)
AnnaBridge 172:65be27845400 2839 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2840 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
AnnaBridge 172:65be27845400 2841 #define ADC_CFGR_AWD1SGL_Pos (22U)
AnnaBridge 172:65be27845400 2842 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2843 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
AnnaBridge 172:65be27845400 2844 #define ADC_CFGR_AWD1EN_Pos (23U)
AnnaBridge 172:65be27845400 2845 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2846 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
AnnaBridge 172:65be27845400 2847 #define ADC_CFGR_JAWD1EN_Pos (24U)
AnnaBridge 172:65be27845400 2848 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2849 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
AnnaBridge 172:65be27845400 2850 #define ADC_CFGR_JAUTO_Pos (25U)
AnnaBridge 172:65be27845400 2851 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2852 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
AnnaBridge 172:65be27845400 2853
AnnaBridge 172:65be27845400 2854 #define ADC_CFGR_AWD1CH_Pos (26U)
AnnaBridge 172:65be27845400 2855 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
AnnaBridge 172:65be27845400 2856 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
AnnaBridge 172:65be27845400 2857 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2858 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2859 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 2860 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 2861 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 2862
AnnaBridge 172:65be27845400 2863 #define ADC_CFGR_JQDIS_Pos (31U)
AnnaBridge 172:65be27845400 2864 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 2865 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
AnnaBridge 172:65be27845400 2866
AnnaBridge 172:65be27845400 2867 /******************** Bit definition for ADC_CFGR2 register ********************/
AnnaBridge 172:65be27845400 2868 #define ADC_CFGR2_ROVSE_Pos (0U)
AnnaBridge 172:65be27845400 2869 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2870 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
AnnaBridge 172:65be27845400 2871 #define ADC_CFGR2_JOVSE_Pos (1U)
AnnaBridge 172:65be27845400 2872 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2873 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
AnnaBridge 172:65be27845400 2874
AnnaBridge 172:65be27845400 2875 #define ADC_CFGR2_OVSS_Pos (5U)
AnnaBridge 172:65be27845400 2876 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
AnnaBridge 172:65be27845400 2877 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
AnnaBridge 172:65be27845400 2878 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2879 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2880 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2881 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2882
AnnaBridge 172:65be27845400 2883 #define ADC_CFGR2_TROVS_Pos (9U)
AnnaBridge 172:65be27845400 2884 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2885 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
AnnaBridge 172:65be27845400 2886 #define ADC_CFGR2_ROVSM_Pos (10U)
AnnaBridge 172:65be27845400 2887 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2888 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
AnnaBridge 172:65be27845400 2889
AnnaBridge 172:65be27845400 2890 #define ADC_CFGR2_RSHIFT1_Pos (11U)
AnnaBridge 172:65be27845400 2891 #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2892 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
AnnaBridge 172:65be27845400 2893 #define ADC_CFGR2_RSHIFT2_Pos (12U)
AnnaBridge 172:65be27845400 2894 #define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2895 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
AnnaBridge 172:65be27845400 2896 #define ADC_CFGR2_RSHIFT3_Pos (13U)
AnnaBridge 172:65be27845400 2897 #define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2898 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
AnnaBridge 172:65be27845400 2899 #define ADC_CFGR2_RSHIFT4_Pos (14U)
AnnaBridge 172:65be27845400 2900 #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2901 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
AnnaBridge 172:65be27845400 2902
AnnaBridge 172:65be27845400 2903 #define ADC_CFGR2_OVSR_Pos (16U)
AnnaBridge 172:65be27845400 2904 #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
AnnaBridge 172:65be27845400 2905 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
AnnaBridge 172:65be27845400 2906 #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2907 #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2908 #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2909 #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2910 #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2911 #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2912 #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2913 #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2914 #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2915 #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2916
AnnaBridge 172:65be27845400 2917 #define ADC_CFGR2_LSHIFT_Pos (28U)
AnnaBridge 172:65be27845400 2918 #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 2919 #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
AnnaBridge 172:65be27845400 2920 #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 2921 #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 2922 #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 2923 #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 2924
AnnaBridge 172:65be27845400 2925 /******************** Bit definition for ADC_SMPR1 register ********************/
AnnaBridge 172:65be27845400 2926 #define ADC_SMPR1_SMP0_Pos (0U)
AnnaBridge 172:65be27845400 2927 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 2928 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
AnnaBridge 172:65be27845400 2929 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 2930 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 2931 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 2932
AnnaBridge 172:65be27845400 2933 #define ADC_SMPR1_SMP1_Pos (3U)
AnnaBridge 172:65be27845400 2934 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 2935 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
AnnaBridge 172:65be27845400 2936 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 2937 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 2938 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 2939
AnnaBridge 172:65be27845400 2940 #define ADC_SMPR1_SMP2_Pos (6U)
AnnaBridge 172:65be27845400 2941 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 172:65be27845400 2942 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
AnnaBridge 172:65be27845400 2943 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 2944 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 2945 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 2946
AnnaBridge 172:65be27845400 2947 #define ADC_SMPR1_SMP3_Pos (9U)
AnnaBridge 172:65be27845400 2948 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 172:65be27845400 2949 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
AnnaBridge 172:65be27845400 2950 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 2951 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 2952 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 2953
AnnaBridge 172:65be27845400 2954 #define ADC_SMPR1_SMP4_Pos (12U)
AnnaBridge 172:65be27845400 2955 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 2956 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
AnnaBridge 172:65be27845400 2957 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 2958 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 2959 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 2960
AnnaBridge 172:65be27845400 2961 #define ADC_SMPR1_SMP5_Pos (15U)
AnnaBridge 172:65be27845400 2962 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 172:65be27845400 2963 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
AnnaBridge 172:65be27845400 2964 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 2965 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 2966 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 2967
AnnaBridge 172:65be27845400 2968 #define ADC_SMPR1_SMP6_Pos (18U)
AnnaBridge 172:65be27845400 2969 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 172:65be27845400 2970 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
AnnaBridge 172:65be27845400 2971 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 2972 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 2973 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 2974
AnnaBridge 172:65be27845400 2975 #define ADC_SMPR1_SMP7_Pos (21U)
AnnaBridge 172:65be27845400 2976 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 172:65be27845400 2977 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
AnnaBridge 172:65be27845400 2978 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 2979 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 2980 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 2981
AnnaBridge 172:65be27845400 2982 #define ADC_SMPR1_SMP8_Pos (24U)
AnnaBridge 172:65be27845400 2983 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 2984 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
AnnaBridge 172:65be27845400 2985 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 2986 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 2987 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 2988
AnnaBridge 172:65be27845400 2989 #define ADC_SMPR1_SMP9_Pos (27U)
AnnaBridge 172:65be27845400 2990 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 172:65be27845400 2991 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
AnnaBridge 172:65be27845400 2992 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 2993 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 2994 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 2995
AnnaBridge 172:65be27845400 2996 /******************** Bit definition for ADC_SMPR2 register ********************/
AnnaBridge 172:65be27845400 2997 #define ADC_SMPR2_SMP10_Pos (0U)
AnnaBridge 172:65be27845400 2998 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 2999 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
AnnaBridge 172:65be27845400 3000 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3001 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3002 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3003
AnnaBridge 172:65be27845400 3004 #define ADC_SMPR2_SMP11_Pos (3U)
AnnaBridge 172:65be27845400 3005 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 3006 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
AnnaBridge 172:65be27845400 3007 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3008 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3009 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3010
AnnaBridge 172:65be27845400 3011 #define ADC_SMPR2_SMP12_Pos (6U)
AnnaBridge 172:65be27845400 3012 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 172:65be27845400 3013 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
AnnaBridge 172:65be27845400 3014 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3015 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3016 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3017
AnnaBridge 172:65be27845400 3018 #define ADC_SMPR2_SMP13_Pos (9U)
AnnaBridge 172:65be27845400 3019 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 172:65be27845400 3020 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
AnnaBridge 172:65be27845400 3021 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3022 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3023 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3024
AnnaBridge 172:65be27845400 3025 #define ADC_SMPR2_SMP14_Pos (12U)
AnnaBridge 172:65be27845400 3026 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 3027 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
AnnaBridge 172:65be27845400 3028 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3029 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3030 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3031
AnnaBridge 172:65be27845400 3032 #define ADC_SMPR2_SMP15_Pos (15U)
AnnaBridge 172:65be27845400 3033 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 172:65be27845400 3034 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
AnnaBridge 172:65be27845400 3035 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3036 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3037 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3038
AnnaBridge 172:65be27845400 3039 #define ADC_SMPR2_SMP16_Pos (18U)
AnnaBridge 172:65be27845400 3040 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 172:65be27845400 3041 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
AnnaBridge 172:65be27845400 3042 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3043 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3044 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3045
AnnaBridge 172:65be27845400 3046 #define ADC_SMPR2_SMP17_Pos (21U)
AnnaBridge 172:65be27845400 3047 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 172:65be27845400 3048 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
AnnaBridge 172:65be27845400 3049 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3050 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3051 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3052
AnnaBridge 172:65be27845400 3053 #define ADC_SMPR2_SMP18_Pos (24U)
AnnaBridge 172:65be27845400 3054 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 3055 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
AnnaBridge 172:65be27845400 3056 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3057 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3058 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3059
AnnaBridge 172:65be27845400 3060 #define ADC_SMPR2_SMP19_Pos (27U)
AnnaBridge 172:65be27845400 3061 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
AnnaBridge 172:65be27845400 3062 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
AnnaBridge 172:65be27845400 3063 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3064 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3065 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3066
AnnaBridge 172:65be27845400 3067 /******************** Bit definition for ADC_PCSEL register ********************/
AnnaBridge 172:65be27845400 3068 #define ADC_PCSEL_PCSEL_Pos (0U)
AnnaBridge 172:65be27845400 3069 #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
AnnaBridge 172:65be27845400 3070 #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
AnnaBridge 172:65be27845400 3071 #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3072 #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3073 #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3074 #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3075 #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3076 #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3077 #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3078 #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3079 #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3080 #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3081 #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3082 #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3083 #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3084 #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3085 #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3086 #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3087 #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3088 #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3089 #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3090 #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3091
AnnaBridge 172:65be27845400 3092 /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
AnnaBridge 172:65be27845400 3093 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 172:65be27845400 3094 #define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
AnnaBridge 172:65be27845400 3095 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
AnnaBridge 172:65be27845400 3096
AnnaBridge 172:65be27845400 3097 /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
AnnaBridge 172:65be27845400 3098 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 172:65be27845400 3099 #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
AnnaBridge 172:65be27845400 3100 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
AnnaBridge 172:65be27845400 3101
AnnaBridge 172:65be27845400 3102 /******************** Bit definition for ADC_SQR1 register ********************/
AnnaBridge 172:65be27845400 3103 #define ADC_SQR1_L_Pos (0U)
AnnaBridge 172:65be27845400 3104 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 3105 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
AnnaBridge 172:65be27845400 3106 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3107 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3108 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3109 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3110
AnnaBridge 172:65be27845400 3111 #define ADC_SQR1_SQ1_Pos (6U)
AnnaBridge 172:65be27845400 3112 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 3113 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
AnnaBridge 172:65be27845400 3114 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3115 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3116 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3117 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3118 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3119
AnnaBridge 172:65be27845400 3120 #define ADC_SQR1_SQ2_Pos (12U)
AnnaBridge 172:65be27845400 3121 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
AnnaBridge 172:65be27845400 3122 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
AnnaBridge 172:65be27845400 3123 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3124 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3125 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3126 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3127 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3128
AnnaBridge 172:65be27845400 3129 #define ADC_SQR1_SQ3_Pos (18U)
AnnaBridge 172:65be27845400 3130 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
AnnaBridge 172:65be27845400 3131 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
AnnaBridge 172:65be27845400 3132 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3133 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3134 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3135 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3136 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3137
AnnaBridge 172:65be27845400 3138 #define ADC_SQR1_SQ4_Pos (24U)
AnnaBridge 172:65be27845400 3139 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
AnnaBridge 172:65be27845400 3140 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
AnnaBridge 172:65be27845400 3141 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3142 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3143 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3144 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3145 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3146
AnnaBridge 172:65be27845400 3147 /******************** Bit definition for ADC_SQR2 register ********************/
AnnaBridge 172:65be27845400 3148 #define ADC_SQR2_SQ5_Pos (0U)
AnnaBridge 172:65be27845400 3149 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 3150 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
AnnaBridge 172:65be27845400 3151 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3152 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3153 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3154 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3155 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3156
AnnaBridge 172:65be27845400 3157 #define ADC_SQR2_SQ6_Pos (6U)
AnnaBridge 172:65be27845400 3158 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 3159 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
AnnaBridge 172:65be27845400 3160 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3161 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3162 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3163 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3164 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3165
AnnaBridge 172:65be27845400 3166 #define ADC_SQR2_SQ7_Pos (12U)
AnnaBridge 172:65be27845400 3167 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
AnnaBridge 172:65be27845400 3168 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
AnnaBridge 172:65be27845400 3169 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3170 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3171 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3172 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3173 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3174
AnnaBridge 172:65be27845400 3175 #define ADC_SQR2_SQ8_Pos (18U)
AnnaBridge 172:65be27845400 3176 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
AnnaBridge 172:65be27845400 3177 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
AnnaBridge 172:65be27845400 3178 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3179 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3180 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3181 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3182 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3183
AnnaBridge 172:65be27845400 3184 #define ADC_SQR2_SQ9_Pos (24U)
AnnaBridge 172:65be27845400 3185 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
AnnaBridge 172:65be27845400 3186 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
AnnaBridge 172:65be27845400 3187 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3188 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3189 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3190 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3191 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3192
AnnaBridge 172:65be27845400 3193 /******************** Bit definition for ADC_SQR3 register ********************/
AnnaBridge 172:65be27845400 3194 #define ADC_SQR3_SQ10_Pos (0U)
AnnaBridge 172:65be27845400 3195 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 3196 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
AnnaBridge 172:65be27845400 3197 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3198 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3199 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3200 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3201 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3202
AnnaBridge 172:65be27845400 3203 #define ADC_SQR3_SQ11_Pos (6U)
AnnaBridge 172:65be27845400 3204 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 3205 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
AnnaBridge 172:65be27845400 3206 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3207 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3208 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3209 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3210 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3211
AnnaBridge 172:65be27845400 3212 #define ADC_SQR3_SQ12_Pos (12U)
AnnaBridge 172:65be27845400 3213 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
AnnaBridge 172:65be27845400 3214 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
AnnaBridge 172:65be27845400 3215 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3216 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3217 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3218 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3219 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3220
AnnaBridge 172:65be27845400 3221 #define ADC_SQR3_SQ13_Pos (18U)
AnnaBridge 172:65be27845400 3222 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
AnnaBridge 172:65be27845400 3223 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
AnnaBridge 172:65be27845400 3224 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3225 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3226 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3227 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3228 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3229
AnnaBridge 172:65be27845400 3230 #define ADC_SQR3_SQ14_Pos (24U)
AnnaBridge 172:65be27845400 3231 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
AnnaBridge 172:65be27845400 3232 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
AnnaBridge 172:65be27845400 3233 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3234 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3235 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3236 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3237 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3238
AnnaBridge 172:65be27845400 3239 /******************** Bit definition for ADC_SQR4 register ********************/
AnnaBridge 172:65be27845400 3240 #define ADC_SQR4_SQ15_Pos (0U)
AnnaBridge 172:65be27845400 3241 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 3242 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
AnnaBridge 172:65be27845400 3243 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3244 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3245 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3246 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3247 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3248
AnnaBridge 172:65be27845400 3249 #define ADC_SQR4_SQ16_Pos (6U)
AnnaBridge 172:65be27845400 3250 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 3251 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
AnnaBridge 172:65be27845400 3252 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3253 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3254 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3255 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3256 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3257 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 172:65be27845400 3258 #define ADC_DR_RDATA_Pos (0U)
AnnaBridge 172:65be27845400 3259 #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 3260 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
AnnaBridge 172:65be27845400 3261
AnnaBridge 172:65be27845400 3262 /******************** Bit definition for ADC_JSQR register ********************/
AnnaBridge 172:65be27845400 3263 #define ADC_JSQR_JL_Pos (0U)
AnnaBridge 172:65be27845400 3264 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 3265 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
AnnaBridge 172:65be27845400 3266 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3267 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3268
AnnaBridge 172:65be27845400 3269 #define ADC_JSQR_JEXTSEL_Pos (2U)
AnnaBridge 172:65be27845400 3270 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
AnnaBridge 172:65be27845400 3271 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
AnnaBridge 172:65be27845400 3272 #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3273 #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3274 #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3275 #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3276 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3277
AnnaBridge 172:65be27845400 3278 #define ADC_JSQR_JEXTEN_Pos (7U)
AnnaBridge 172:65be27845400 3279 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
AnnaBridge 172:65be27845400 3280 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
AnnaBridge 172:65be27845400 3281 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3282 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3283
AnnaBridge 172:65be27845400 3284 #define ADC_JSQR_JSQ1_Pos (9U)
AnnaBridge 172:65be27845400 3285 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
AnnaBridge 172:65be27845400 3286 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
AnnaBridge 172:65be27845400 3287 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3288 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3289 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3290 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3291 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3292
AnnaBridge 172:65be27845400 3293 #define ADC_JSQR_JSQ2_Pos (15U)
AnnaBridge 172:65be27845400 3294 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
AnnaBridge 172:65be27845400 3295 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
AnnaBridge 172:65be27845400 3296 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3297 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3298 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3299 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3300 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3301
AnnaBridge 172:65be27845400 3302 #define ADC_JSQR_JSQ3_Pos (21U)
AnnaBridge 172:65be27845400 3303 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
AnnaBridge 172:65be27845400 3304 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
AnnaBridge 172:65be27845400 3305 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3306 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3307 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3308 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3309 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3310
AnnaBridge 172:65be27845400 3311 #define ADC_JSQR_JSQ4_Pos (27U)
AnnaBridge 172:65be27845400 3312 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
AnnaBridge 172:65be27845400 3313 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
AnnaBridge 172:65be27845400 3314 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3315 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3316 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3317 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3318 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3319
AnnaBridge 172:65be27845400 3320 /******************** Bit definition for ADC_OFR1 register ********************/
AnnaBridge 172:65be27845400 3321 #define ADC_OFR1_OFFSET1_Pos (0U)
AnnaBridge 172:65be27845400 3322 #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
AnnaBridge 172:65be27845400 3323 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
AnnaBridge 172:65be27845400 3324 #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3325 #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3326 #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3327 #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3328 #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3329 #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3330 #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3331 #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3332 #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3333 #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3334 #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3335 #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3336 #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3337 #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3338 #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3339 #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3340 #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3341 #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3342 #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3343 #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3344 #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3345 #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3346 #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3347 #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3348 #define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3349 #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3350
AnnaBridge 172:65be27845400 3351 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
AnnaBridge 172:65be27845400 3352 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 172:65be27845400 3353 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
AnnaBridge 172:65be27845400 3354 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3355 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3356 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3357 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3358 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3359
AnnaBridge 172:65be27845400 3360 #define ADC_OFR1_SSATE_Pos (31U)
AnnaBridge 172:65be27845400 3361 #define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3362 #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
AnnaBridge 172:65be27845400 3363
AnnaBridge 172:65be27845400 3364 /******************** Bit definition for ADC_OFR2 register ********************/
AnnaBridge 172:65be27845400 3365 #define ADC_OFR2_OFFSET2_Pos (0U)
AnnaBridge 172:65be27845400 3366 #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
AnnaBridge 172:65be27845400 3367 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
AnnaBridge 172:65be27845400 3368 #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3369 #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3370 #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3371 #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3372 #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3373 #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3374 #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3375 #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3376 #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3377 #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3378 #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3379 #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3380 #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3381 #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3382 #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3383 #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3384 #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3385 #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3386 #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3387 #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3388 #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3389 #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3390 #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3391 #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3392 #define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3393 #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3394
AnnaBridge 172:65be27845400 3395 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
AnnaBridge 172:65be27845400 3396 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 172:65be27845400 3397 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
AnnaBridge 172:65be27845400 3398 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3399 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3400 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3401 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3402 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3403
AnnaBridge 172:65be27845400 3404 #define ADC_OFR2_SSATE_Pos (31U)
AnnaBridge 172:65be27845400 3405 #define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3406 #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
AnnaBridge 172:65be27845400 3407
AnnaBridge 172:65be27845400 3408 /******************** Bit definition for ADC_OFR3 register ********************/
AnnaBridge 172:65be27845400 3409 #define ADC_OFR3_OFFSET3_Pos (0U)
AnnaBridge 172:65be27845400 3410 #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
AnnaBridge 172:65be27845400 3411 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
AnnaBridge 172:65be27845400 3412 #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3413 #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3414 #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3415 #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3416 #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3417 #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3418 #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3419 #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3420 #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3421 #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3422 #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3423 #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3424 #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3425 #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3426 #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3427 #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3428 #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3429 #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3430 #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3431 #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3432 #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3433 #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3434 #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3435 #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3436 #define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3437 #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3438
AnnaBridge 172:65be27845400 3439 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
AnnaBridge 172:65be27845400 3440 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 172:65be27845400 3441 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
AnnaBridge 172:65be27845400 3442 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3443 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3444 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3445 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3446 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3447
AnnaBridge 172:65be27845400 3448 #define ADC_OFR3_SSATE_Pos (31U)
AnnaBridge 172:65be27845400 3449 #define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3450 #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
AnnaBridge 172:65be27845400 3451
AnnaBridge 172:65be27845400 3452 /******************** Bit definition for ADC_OFR4 register ********************/
AnnaBridge 172:65be27845400 3453 #define ADC_OFR4_OFFSET4_Pos (0U)
AnnaBridge 172:65be27845400 3454 #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
AnnaBridge 172:65be27845400 3455 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
AnnaBridge 172:65be27845400 3456 #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3457 #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3458 #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3459 #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3460 #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3461 #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3462 #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3463 #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3464 #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3465 #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3466 #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3467 #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3468 #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3469 #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3470 #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3471 #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3472 #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3473 #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3474 #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3475 #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3476 #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3477 #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3478 #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3479 #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3480 #define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3481 #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3482
AnnaBridge 172:65be27845400 3483 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
AnnaBridge 172:65be27845400 3484 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
AnnaBridge 172:65be27845400 3485 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
AnnaBridge 172:65be27845400 3486 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3487 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3488 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3489 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3490 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3491
AnnaBridge 172:65be27845400 3492 #define ADC_OFR4_SSATE_Pos (31U)
AnnaBridge 172:65be27845400 3493 #define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3494 #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
AnnaBridge 172:65be27845400 3495
AnnaBridge 172:65be27845400 3496 /******************** Bit definition for ADC_JDR1 register ********************/
AnnaBridge 172:65be27845400 3497 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 3498 #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 3499 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
AnnaBridge 172:65be27845400 3500 #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3501 #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3502 #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3503 #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3504 #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3505 #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3506 #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3507 #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3508 #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3509 #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3510 #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3511 #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3512 #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3513 #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3514 #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3515 #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3516 #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3517 #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3518 #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3519 #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3520 #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3521 #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3522 #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3523 #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3524 #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3525 #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3526 #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3527 #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3528 #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3529 #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3530 #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3531 #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3532
AnnaBridge 172:65be27845400 3533 /******************** Bit definition for ADC_JDR2 register ********************/
AnnaBridge 172:65be27845400 3534 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 3535 #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 3536 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
AnnaBridge 172:65be27845400 3537 #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3538 #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3539 #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3540 #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3541 #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3542 #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3543 #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3544 #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3545 #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3546 #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3547 #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3548 #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3549 #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3550 #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3551 #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3552 #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3553 #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3554 #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3555 #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3556 #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3557 #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3558 #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3559 #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3560 #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3561 #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3562 #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3563 #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3564 #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3565 #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3566 #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3567 #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3568 #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3569
AnnaBridge 172:65be27845400 3570 /******************** Bit definition for ADC_JDR3 register ********************/
AnnaBridge 172:65be27845400 3571 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 3572 #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 3573 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
AnnaBridge 172:65be27845400 3574 #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3575 #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3576 #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3577 #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3578 #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3579 #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3580 #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3581 #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3582 #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3583 #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3584 #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3585 #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3586 #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3587 #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3588 #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3589 #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3590 #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3591 #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3592 #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3593 #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3594 #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3595 #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3596 #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3597 #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3598 #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3599 #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3600 #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3601 #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3602 #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3603 #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3604 #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3605 #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3606
AnnaBridge 172:65be27845400 3607 /******************** Bit definition for ADC_JDR4 register ********************/
AnnaBridge 172:65be27845400 3608 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 172:65be27845400 3609 #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 3610 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
AnnaBridge 172:65be27845400 3611 #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3612 #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3613 #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3614 #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3615 #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3616 #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3617 #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3618 #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3619 #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3620 #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3621 #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3622 #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3623 #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3624 #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3625 #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3626 #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3627 #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3628 #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3629 #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3630 #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3631 #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3632 #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3633 #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3634 #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3635 #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3636 #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3637 #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3638 #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3639 #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3640 #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3641 #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 3642 #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 3643
AnnaBridge 172:65be27845400 3644 /******************** Bit definition for ADC_AWD2CR register ********************/
AnnaBridge 172:65be27845400 3645 #define ADC_AWD2CR_AWD2CH_Pos (0U)
AnnaBridge 172:65be27845400 3646 #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
AnnaBridge 172:65be27845400 3647 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
AnnaBridge 172:65be27845400 3648 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3649 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3650 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3651 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3652 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3653 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3654 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3655 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3656 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3657 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3658 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3659 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3660 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3661 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3662 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3663 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3664 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3665 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3666 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3667 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3668
AnnaBridge 172:65be27845400 3669 /******************** Bit definition for ADC_AWD3CR register ********************/
AnnaBridge 172:65be27845400 3670 #define ADC_AWD3CR_AWD3CH_Pos (0U)
AnnaBridge 172:65be27845400 3671 #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
AnnaBridge 172:65be27845400 3672 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
AnnaBridge 172:65be27845400 3673 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3674 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3675 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3676 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3677 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3678 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3679 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3680 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3681 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3682 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3683 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3684 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3685 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3686 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3687 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3688 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3689 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3690 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3691 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3692 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3693
AnnaBridge 172:65be27845400 3694 /******************** Bit definition for ADC_DIFSEL register ********************/
AnnaBridge 172:65be27845400 3695 #define ADC_DIFSEL_DIFSEL_Pos (0U)
AnnaBridge 172:65be27845400 3696 #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
AnnaBridge 172:65be27845400 3697 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
AnnaBridge 172:65be27845400 3698 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3699 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3700 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3701 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3702 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3703 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3704 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3705 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3706 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3707 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3708 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3709 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3710 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3711 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3712 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3713 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3714 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3715 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3716 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3717 #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3718
AnnaBridge 172:65be27845400 3719 /******************** Bit definition for ADC_CALFACT register ********************/
AnnaBridge 172:65be27845400 3720 #define ADC_CALFACT_CALFACT_S_Pos (0U)
AnnaBridge 172:65be27845400 3721 #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 3722 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
AnnaBridge 172:65be27845400 3723 #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3724 #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3725 #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3726 #define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3727 #define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3728 #define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3729 #define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3730 #define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3731 #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3732 #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3733 #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3734 #define ADC_CALFACT_CALFACT_D_Pos (16U)
AnnaBridge 172:65be27845400 3735 #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
AnnaBridge 172:65be27845400 3736 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
AnnaBridge 172:65be27845400 3737 #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3738 #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3739 #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3740 #define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3741 #define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3742 #define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3743 #define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3744 #define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3745 #define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3746 #define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3747 #define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3748
AnnaBridge 172:65be27845400 3749 /******************** Bit definition for ADC_CALFACT2 register ********************/
AnnaBridge 172:65be27845400 3750 #define ADC_CALFACT2_LINCALFACT_Pos (0U)
AnnaBridge 172:65be27845400 3751 #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
AnnaBridge 172:65be27845400 3752 #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
AnnaBridge 172:65be27845400 3753 #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3754 #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3755 #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3756 #define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3757 #define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3758 #define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3759 #define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3760 #define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3761 #define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3762 #define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3763 #define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3764 #define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3765 #define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 3766 #define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 3767 #define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3768 #define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3769 #define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3770 #define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3771 #define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3772 #define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3773 #define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3774 #define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3775 #define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3776 #define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3777 #define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3778 #define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3779 #define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3780 #define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 3781 #define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 3782 #define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 3783
AnnaBridge 172:65be27845400 3784 /************************* ADC Common registers *****************************/
AnnaBridge 172:65be27845400 3785 /******************** Bit definition for ADC_CSR register ********************/
AnnaBridge 172:65be27845400 3786 #define ADC_CSR_ADRDY_MST_Pos (0U)
AnnaBridge 172:65be27845400 3787 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3788 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
AnnaBridge 172:65be27845400 3789 #define ADC_CSR_EOSMP_MST_Pos (1U)
AnnaBridge 172:65be27845400 3790 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3791 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
AnnaBridge 172:65be27845400 3792 #define ADC_CSR_EOC_MST_Pos (2U)
AnnaBridge 172:65be27845400 3793 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3794 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
AnnaBridge 172:65be27845400 3795 #define ADC_CSR_EOS_MST_Pos (3U)
AnnaBridge 172:65be27845400 3796 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3797 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
AnnaBridge 172:65be27845400 3798 #define ADC_CSR_OVR_MST_Pos (4U)
AnnaBridge 172:65be27845400 3799 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3800 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
AnnaBridge 172:65be27845400 3801 #define ADC_CSR_JEOC_MST_Pos (5U)
AnnaBridge 172:65be27845400 3802 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3803 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
AnnaBridge 172:65be27845400 3804 #define ADC_CSR_JEOS_MST_Pos (6U)
AnnaBridge 172:65be27845400 3805 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 3806 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
AnnaBridge 172:65be27845400 3807 #define ADC_CSR_AWD1_MST_Pos (7U)
AnnaBridge 172:65be27845400 3808 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 3809 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
AnnaBridge 172:65be27845400 3810 #define ADC_CSR_AWD2_MST_Pos (8U)
AnnaBridge 172:65be27845400 3811 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3812 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
AnnaBridge 172:65be27845400 3813 #define ADC_CSR_AWD3_MST_Pos (9U)
AnnaBridge 172:65be27845400 3814 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3815 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
AnnaBridge 172:65be27845400 3816 #define ADC_CSR_JQOVF_MST_Pos (10U)
AnnaBridge 172:65be27845400 3817 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3818 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
AnnaBridge 172:65be27845400 3819 #define ADC_CSR_ADRDY_SLV_Pos (16U)
AnnaBridge 172:65be27845400 3820 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3821 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
AnnaBridge 172:65be27845400 3822 #define ADC_CSR_EOSMP_SLV_Pos (17U)
AnnaBridge 172:65be27845400 3823 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3824 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
AnnaBridge 172:65be27845400 3825 #define ADC_CSR_EOC_SLV_Pos (18U)
AnnaBridge 172:65be27845400 3826 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3827 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
AnnaBridge 172:65be27845400 3828 #define ADC_CSR_EOS_SLV_Pos (19U)
AnnaBridge 172:65be27845400 3829 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3830 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
AnnaBridge 172:65be27845400 3831 #define ADC_CSR_OVR_SLV_Pos (20U)
AnnaBridge 172:65be27845400 3832 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3833 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
AnnaBridge 172:65be27845400 3834 #define ADC_CSR_JEOC_SLV_Pos (21U)
AnnaBridge 172:65be27845400 3835 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3836 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
AnnaBridge 172:65be27845400 3837 #define ADC_CSR_JEOS_SLV_Pos (22U)
AnnaBridge 172:65be27845400 3838 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3839 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
AnnaBridge 172:65be27845400 3840 #define ADC_CSR_AWD1_SLV_Pos (23U)
AnnaBridge 172:65be27845400 3841 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3842 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
AnnaBridge 172:65be27845400 3843 #define ADC_CSR_AWD2_SLV_Pos (24U)
AnnaBridge 172:65be27845400 3844 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3845 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
AnnaBridge 172:65be27845400 3846 #define ADC_CSR_AWD3_SLV_Pos (25U)
AnnaBridge 172:65be27845400 3847 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 3848 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
AnnaBridge 172:65be27845400 3849 #define ADC_CSR_JQOVF_SLV_Pos (26U)
AnnaBridge 172:65be27845400 3850 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 3851 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
AnnaBridge 172:65be27845400 3852
AnnaBridge 172:65be27845400 3853 /******************** Bit definition for ADC_CCR register ********************/
AnnaBridge 172:65be27845400 3854 #define ADC_CCR_DUAL_Pos (0U)
AnnaBridge 172:65be27845400 3855 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 3856 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
AnnaBridge 172:65be27845400 3857 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3858 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3859 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 3860 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3861 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3862
AnnaBridge 172:65be27845400 3863 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 172:65be27845400 3864 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 3865 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
AnnaBridge 172:65be27845400 3866 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 3867 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 3868 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 3869 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 3870
AnnaBridge 172:65be27845400 3871
AnnaBridge 172:65be27845400 3872 #define ADC_CCR_DAMDF_Pos (14U)
AnnaBridge 172:65be27845400 3873 #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 3874 #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
AnnaBridge 172:65be27845400 3875 #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 3876 #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 3877
AnnaBridge 172:65be27845400 3878 #define ADC_CCR_CKMODE_Pos (16U)
AnnaBridge 172:65be27845400 3879 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 3880 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
AnnaBridge 172:65be27845400 3881 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 3882 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 3883
AnnaBridge 172:65be27845400 3884 #define ADC_CCR_PRESC_Pos (18U)
AnnaBridge 172:65be27845400 3885 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
AnnaBridge 172:65be27845400 3886 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
AnnaBridge 172:65be27845400 3887 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 3888 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 3889 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 3890 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 3891
AnnaBridge 172:65be27845400 3892 #define ADC_CCR_VREFEN_Pos (22U)
AnnaBridge 172:65be27845400 3893 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 3894 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
AnnaBridge 172:65be27845400 3895 #define ADC_CCR_TSEN_Pos (23U)
AnnaBridge 172:65be27845400 3896 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3897 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
AnnaBridge 172:65be27845400 3898 #define ADC_CCR_VBATEN_Pos (24U)
AnnaBridge 172:65be27845400 3899 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 3900 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
AnnaBridge 172:65be27845400 3901
AnnaBridge 172:65be27845400 3902 /******************** Bit definition for ADC_CDR register *******************/
AnnaBridge 172:65be27845400 3903 #define ADC_CDR_RDATA_MST_Pos (0U)
AnnaBridge 172:65be27845400 3904 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 3905 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
AnnaBridge 172:65be27845400 3906
AnnaBridge 172:65be27845400 3907 #define ADC_CDR_RDATA_SLV_Pos (16U)
AnnaBridge 172:65be27845400 3908 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 3909 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
AnnaBridge 172:65be27845400 3910
AnnaBridge 172:65be27845400 3911 /******************** Bit definition for ADC_CDR2 register ******************/
AnnaBridge 172:65be27845400 3912 #define ADC_CDR2_RDATA_ALT_Pos (0U)
AnnaBridge 172:65be27845400 3913 #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 3914 #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
AnnaBridge 172:65be27845400 3915
AnnaBridge 172:65be27845400 3916 /******************************************************************************/
AnnaBridge 172:65be27845400 3917 /* */
AnnaBridge 172:65be27845400 3918 /* VREFBUF */
AnnaBridge 172:65be27845400 3919 /* */
AnnaBridge 172:65be27845400 3920 /******************************************************************************/
AnnaBridge 172:65be27845400 3921 /******************* Bit definition for VREFBUF_CSR register ****************/
AnnaBridge 172:65be27845400 3922 #define VREFBUF_CSR_ENVR_Pos (0U)
AnnaBridge 172:65be27845400 3923 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 3924 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
AnnaBridge 172:65be27845400 3925 #define VREFBUF_CSR_HIZ_Pos (1U)
AnnaBridge 172:65be27845400 3926 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 3927 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
AnnaBridge 172:65be27845400 3928 #define VREFBUF_CSR_VRR_Pos (3U)
AnnaBridge 172:65be27845400 3929 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 3930 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
AnnaBridge 172:65be27845400 3931 #define VREFBUF_CSR_VRS_Pos (4U)
AnnaBridge 172:65be27845400 3932 #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 3933 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
AnnaBridge 172:65be27845400 3934
AnnaBridge 172:65be27845400 3935 #define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
AnnaBridge 172:65be27845400 3936 #define VREFBUF_CSR_VRS_OUT2_Pos (4U)
AnnaBridge 172:65be27845400 3937 #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 3938 #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
AnnaBridge 172:65be27845400 3939 #define VREFBUF_CSR_VRS_OUT3_Pos (5U)
AnnaBridge 172:65be27845400 3940 #define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 3941 #define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
AnnaBridge 172:65be27845400 3942 #define VREFBUF_CSR_VRS_OUT4_Pos (4U)
AnnaBridge 172:65be27845400 3943 #define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 3944 #define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
AnnaBridge 172:65be27845400 3945
AnnaBridge 172:65be27845400 3946 /******************* Bit definition for VREFBUF_CCR register ****************/
AnnaBridge 172:65be27845400 3947 #define VREFBUF_CCR_TRIM_Pos (0U)
AnnaBridge 172:65be27845400 3948 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 3949 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
AnnaBridge 172:65be27845400 3950
AnnaBridge 172:65be27845400 3951 /******************************************************************************/
AnnaBridge 172:65be27845400 3952 /* */
AnnaBridge 172:65be27845400 3953 /* Flexible Datarate Controller Area Network */
AnnaBridge 172:65be27845400 3954 /* */
AnnaBridge 172:65be27845400 3955 /******************************************************************************/
AnnaBridge 172:65be27845400 3956 /*!<FDCAN control and status registers */
AnnaBridge 172:65be27845400 3957 /***************** Bit definition for FDCAN_CREL register *******************/
AnnaBridge 172:65be27845400 3958 #define FDCAN_CREL_DAY_Pos (0U)
AnnaBridge 172:65be27845400 3959 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 3960 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
AnnaBridge 172:65be27845400 3961 #define FDCAN_CREL_MON_Pos (8U)
AnnaBridge 172:65be27845400 3962 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 3963 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
AnnaBridge 172:65be27845400 3964 #define FDCAN_CREL_YEAR_Pos (16U)
AnnaBridge 172:65be27845400 3965 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 3966 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
AnnaBridge 172:65be27845400 3967 #define FDCAN_CREL_SUBSTEP_Pos (20U)
AnnaBridge 172:65be27845400 3968 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 3969 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
AnnaBridge 172:65be27845400 3970 #define FDCAN_CREL_STEP_Pos (24U)
AnnaBridge 172:65be27845400 3971 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 3972 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
AnnaBridge 172:65be27845400 3973 #define FDCAN_CREL_REL_Pos (28U)
AnnaBridge 172:65be27845400 3974 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 3975 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
AnnaBridge 172:65be27845400 3976
AnnaBridge 172:65be27845400 3977 /***************** Bit definition for FDCAN_ENDN register *******************/
AnnaBridge 172:65be27845400 3978 #define FDCAN_ENDN_ETV_Pos (0U)
AnnaBridge 172:65be27845400 3979 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 3980 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
AnnaBridge 172:65be27845400 3981
AnnaBridge 172:65be27845400 3982 /***************** Bit definition for FDCAN_DBTP register *******************/
AnnaBridge 172:65be27845400 3983 #define FDCAN_DBTP_DSJW_Pos (0U)
AnnaBridge 172:65be27845400 3984 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 3985 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
AnnaBridge 172:65be27845400 3986 #define FDCAN_DBTP_DTSEG2_Pos (4U)
AnnaBridge 172:65be27845400 3987 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 3988 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
AnnaBridge 172:65be27845400 3989 #define FDCAN_DBTP_DTSEG1_Pos (8U)
AnnaBridge 172:65be27845400 3990 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 3991 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
AnnaBridge 172:65be27845400 3992 #define FDCAN_DBTP_DBRP_Pos (16U)
AnnaBridge 172:65be27845400 3993 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 3994 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
AnnaBridge 172:65be27845400 3995 #define FDCAN_DBTP_TDC_Pos (23U)
AnnaBridge 172:65be27845400 3996 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 3997 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
AnnaBridge 172:65be27845400 3998
AnnaBridge 172:65be27845400 3999 /***************** Bit definition for FDCAN_TEST register *******************/
AnnaBridge 172:65be27845400 4000 #define FDCAN_TEST_LBCK_Pos (4U)
AnnaBridge 172:65be27845400 4001 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4002 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
AnnaBridge 172:65be27845400 4003 #define FDCAN_TEST_TX_Pos (5U)
AnnaBridge 172:65be27845400 4004 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 4005 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
AnnaBridge 172:65be27845400 4006 #define FDCAN_TEST_RX_Pos (7U)
AnnaBridge 172:65be27845400 4007 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4008 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
AnnaBridge 172:65be27845400 4009
AnnaBridge 172:65be27845400 4010 /***************** Bit definition for FDCAN_RWD register ********************/
AnnaBridge 172:65be27845400 4011 #define FDCAN_RWD_WDC_Pos (0U)
AnnaBridge 172:65be27845400 4012 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 4013 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
AnnaBridge 172:65be27845400 4014 #define FDCAN_RWD_WDV_Pos (8U)
AnnaBridge 172:65be27845400 4015 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 4016 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
AnnaBridge 172:65be27845400 4017
AnnaBridge 172:65be27845400 4018 /***************** Bit definition for FDCAN_CCCR register ********************/
AnnaBridge 172:65be27845400 4019 #define FDCAN_CCCR_INIT_Pos (0U)
AnnaBridge 172:65be27845400 4020 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4021 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
AnnaBridge 172:65be27845400 4022 #define FDCAN_CCCR_CCE_Pos (1U)
AnnaBridge 172:65be27845400 4023 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4024 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
AnnaBridge 172:65be27845400 4025 #define FDCAN_CCCR_ASM_Pos (2U)
AnnaBridge 172:65be27845400 4026 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4027 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
AnnaBridge 172:65be27845400 4028 #define FDCAN_CCCR_CSA_Pos (3U)
AnnaBridge 172:65be27845400 4029 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4030 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
AnnaBridge 172:65be27845400 4031 #define FDCAN_CCCR_CSR_Pos (4U)
AnnaBridge 172:65be27845400 4032 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4033 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
AnnaBridge 172:65be27845400 4034 #define FDCAN_CCCR_MON_Pos (5U)
AnnaBridge 172:65be27845400 4035 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4036 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
AnnaBridge 172:65be27845400 4037 #define FDCAN_CCCR_DAR_Pos (6U)
AnnaBridge 172:65be27845400 4038 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4039 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
AnnaBridge 172:65be27845400 4040 #define FDCAN_CCCR_TEST_Pos (7U)
AnnaBridge 172:65be27845400 4041 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4042 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
AnnaBridge 172:65be27845400 4043 #define FDCAN_CCCR_FDOE_Pos (8U)
AnnaBridge 172:65be27845400 4044 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4045 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
AnnaBridge 172:65be27845400 4046 #define FDCAN_CCCR_BRSE_Pos (9U)
AnnaBridge 172:65be27845400 4047 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4048 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
AnnaBridge 172:65be27845400 4049 #define FDCAN_CCCR_PXHD_Pos (12U)
AnnaBridge 172:65be27845400 4050 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4051 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
AnnaBridge 172:65be27845400 4052 #define FDCAN_CCCR_EFBI_Pos (13U)
AnnaBridge 172:65be27845400 4053 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4054 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
AnnaBridge 172:65be27845400 4055 #define FDCAN_CCCR_TXP_Pos (14U)
AnnaBridge 172:65be27845400 4056 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4057 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
AnnaBridge 172:65be27845400 4058 #define FDCAN_CCCR_NISO_Pos (15U)
AnnaBridge 172:65be27845400 4059 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4060 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
AnnaBridge 172:65be27845400 4061
AnnaBridge 172:65be27845400 4062 /***************** Bit definition for FDCAN_NBTP register ********************/
AnnaBridge 172:65be27845400 4063 #define FDCAN_NBTP_NTSEG2_Pos (0U)
AnnaBridge 172:65be27845400 4064 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 4065 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
AnnaBridge 172:65be27845400 4066 #define FDCAN_NBTP_NTSEG1_Pos (8U)
AnnaBridge 172:65be27845400 4067 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 4068 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
AnnaBridge 172:65be27845400 4069 #define FDCAN_NBTP_NBRP_Pos (16U)
AnnaBridge 172:65be27845400 4070 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
AnnaBridge 172:65be27845400 4071 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
AnnaBridge 172:65be27845400 4072 #define FDCAN_NBTP_NSJW_Pos (25U)
AnnaBridge 172:65be27845400 4073 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
AnnaBridge 172:65be27845400 4074 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
AnnaBridge 172:65be27845400 4075
AnnaBridge 172:65be27845400 4076 /***************** Bit definition for FDCAN_TSCC register ********************/
AnnaBridge 172:65be27845400 4077 #define FDCAN_TSCC_TSS_Pos (0U)
AnnaBridge 172:65be27845400 4078 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 4079 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
AnnaBridge 172:65be27845400 4080 #define FDCAN_TSCC_TCP_Pos (16U)
AnnaBridge 172:65be27845400 4081 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 4082 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
AnnaBridge 172:65be27845400 4083
AnnaBridge 172:65be27845400 4084 /***************** Bit definition for FDCAN_TSCV register ********************/
AnnaBridge 172:65be27845400 4085 #define FDCAN_TSCV_TSC_Pos (0U)
AnnaBridge 172:65be27845400 4086 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 4087 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
AnnaBridge 172:65be27845400 4088
AnnaBridge 172:65be27845400 4089 /***************** Bit definition for FDCAN_TOCC register ********************/
AnnaBridge 172:65be27845400 4090 #define FDCAN_TOCC_ETOC_Pos (0U)
AnnaBridge 172:65be27845400 4091 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4092 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
AnnaBridge 172:65be27845400 4093 #define FDCAN_TOCC_TOS_Pos (1U)
AnnaBridge 172:65be27845400 4094 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 4095 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
AnnaBridge 172:65be27845400 4096 #define FDCAN_TOCC_TOP_Pos (16U)
AnnaBridge 172:65be27845400 4097 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 4098 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
AnnaBridge 172:65be27845400 4099
AnnaBridge 172:65be27845400 4100 /***************** Bit definition for FDCAN_TOCV register ********************/
AnnaBridge 172:65be27845400 4101 #define FDCAN_TOCV_TOC_Pos (0U)
AnnaBridge 172:65be27845400 4102 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 4103 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
AnnaBridge 172:65be27845400 4104
AnnaBridge 172:65be27845400 4105 /***************** Bit definition for FDCAN_ECR register *********************/
AnnaBridge 172:65be27845400 4106 #define FDCAN_ECR_TEC_Pos (0U)
AnnaBridge 172:65be27845400 4107 #define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 4108 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
AnnaBridge 172:65be27845400 4109 #define FDCAN_ECR_REC_Pos (8U)
AnnaBridge 172:65be27845400 4110 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
AnnaBridge 172:65be27845400 4111 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
AnnaBridge 172:65be27845400 4112 #define FDCAN_ECR_RP_Pos (15U)
AnnaBridge 172:65be27845400 4113 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4114 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
AnnaBridge 172:65be27845400 4115 #define FDCAN_ECR_CEL_Pos (16U)
AnnaBridge 172:65be27845400 4116 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 4117 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
AnnaBridge 172:65be27845400 4118
AnnaBridge 172:65be27845400 4119 /***************** Bit definition for FDCAN_PSR register *********************/
AnnaBridge 172:65be27845400 4120 #define FDCAN_PSR_LEC_Pos (0U)
AnnaBridge 172:65be27845400 4121 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 4122 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
AnnaBridge 172:65be27845400 4123 #define FDCAN_PSR_ACT_Pos (3U)
AnnaBridge 172:65be27845400 4124 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 4125 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
AnnaBridge 172:65be27845400 4126 #define FDCAN_PSR_EP_Pos (5U)
AnnaBridge 172:65be27845400 4127 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4128 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
AnnaBridge 172:65be27845400 4129 #define FDCAN_PSR_EW_Pos (6U)
AnnaBridge 172:65be27845400 4130 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4131 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
AnnaBridge 172:65be27845400 4132 #define FDCAN_PSR_BO_Pos (7U)
AnnaBridge 172:65be27845400 4133 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4134 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
AnnaBridge 172:65be27845400 4135 #define FDCAN_PSR_DLEC_Pos (8U)
AnnaBridge 172:65be27845400 4136 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 4137 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
AnnaBridge 172:65be27845400 4138 #define FDCAN_PSR_RESI_Pos (11U)
AnnaBridge 172:65be27845400 4139 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4140 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
AnnaBridge 172:65be27845400 4141 #define FDCAN_PSR_RBRS_Pos (12U)
AnnaBridge 172:65be27845400 4142 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4143 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
AnnaBridge 172:65be27845400 4144 #define FDCAN_PSR_REDL_Pos (13U)
AnnaBridge 172:65be27845400 4145 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4146 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
AnnaBridge 172:65be27845400 4147 #define FDCAN_PSR_PXE_Pos (14U)
AnnaBridge 172:65be27845400 4148 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4149 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
AnnaBridge 172:65be27845400 4150 #define FDCAN_PSR_TDCV_Pos (16U)
AnnaBridge 172:65be27845400 4151 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 4152 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
AnnaBridge 172:65be27845400 4153
AnnaBridge 172:65be27845400 4154 /***************** Bit definition for FDCAN_TDCR register ********************/
AnnaBridge 172:65be27845400 4155 #define FDCAN_TDCR_TDCF_Pos (0U)
AnnaBridge 172:65be27845400 4156 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 4157 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
AnnaBridge 172:65be27845400 4158 #define FDCAN_TDCR_TDCO_Pos (8U)
AnnaBridge 172:65be27845400 4159 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
AnnaBridge 172:65be27845400 4160 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
AnnaBridge 172:65be27845400 4161
AnnaBridge 172:65be27845400 4162 /***************** Bit definition for FDCAN_IR register **********************/
AnnaBridge 172:65be27845400 4163 #define FDCAN_IR_RF0N_Pos (0U)
AnnaBridge 172:65be27845400 4164 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4165 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
AnnaBridge 172:65be27845400 4166 #define FDCAN_IR_RF0W_Pos (1U)
AnnaBridge 172:65be27845400 4167 #define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4168 #define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
AnnaBridge 172:65be27845400 4169 #define FDCAN_IR_RF0F_Pos (2U)
AnnaBridge 172:65be27845400 4170 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4171 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
AnnaBridge 172:65be27845400 4172 #define FDCAN_IR_RF0L_Pos (3U)
AnnaBridge 172:65be27845400 4173 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4174 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
AnnaBridge 172:65be27845400 4175 #define FDCAN_IR_RF1N_Pos (4U)
AnnaBridge 172:65be27845400 4176 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4177 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
AnnaBridge 172:65be27845400 4178 #define FDCAN_IR_RF1W_Pos (5U)
AnnaBridge 172:65be27845400 4179 #define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4180 #define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
AnnaBridge 172:65be27845400 4181 #define FDCAN_IR_RF1F_Pos (6U)
AnnaBridge 172:65be27845400 4182 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4183 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
AnnaBridge 172:65be27845400 4184 #define FDCAN_IR_RF1L_Pos (7U)
AnnaBridge 172:65be27845400 4185 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4186 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
AnnaBridge 172:65be27845400 4187 #define FDCAN_IR_HPM_Pos (8U)
AnnaBridge 172:65be27845400 4188 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4189 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
AnnaBridge 172:65be27845400 4190 #define FDCAN_IR_TC_Pos (9U)
AnnaBridge 172:65be27845400 4191 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4192 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
AnnaBridge 172:65be27845400 4193 #define FDCAN_IR_TCF_Pos (10U)
AnnaBridge 172:65be27845400 4194 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4195 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
AnnaBridge 172:65be27845400 4196 #define FDCAN_IR_TFE_Pos (11U)
AnnaBridge 172:65be27845400 4197 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4198 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
AnnaBridge 172:65be27845400 4199 #define FDCAN_IR_TEFN_Pos (12U)
AnnaBridge 172:65be27845400 4200 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4201 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
AnnaBridge 172:65be27845400 4202 #define FDCAN_IR_TEFW_Pos (13U)
AnnaBridge 172:65be27845400 4203 #define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4204 #define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
AnnaBridge 172:65be27845400 4205 #define FDCAN_IR_TEFF_Pos (14U)
AnnaBridge 172:65be27845400 4206 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4207 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
AnnaBridge 172:65be27845400 4208 #define FDCAN_IR_TEFL_Pos (15U)
AnnaBridge 172:65be27845400 4209 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4210 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
AnnaBridge 172:65be27845400 4211 #define FDCAN_IR_TSW_Pos (16U)
AnnaBridge 172:65be27845400 4212 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4213 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
AnnaBridge 172:65be27845400 4214 #define FDCAN_IR_MRAF_Pos (17U)
AnnaBridge 172:65be27845400 4215 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4216 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
AnnaBridge 172:65be27845400 4217 #define FDCAN_IR_TOO_Pos (18U)
AnnaBridge 172:65be27845400 4218 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4219 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
AnnaBridge 172:65be27845400 4220 #define FDCAN_IR_DRX_Pos (19U)
AnnaBridge 172:65be27845400 4221 #define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4222 #define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
AnnaBridge 172:65be27845400 4223 #define FDCAN_IR_ELO_Pos (22U)
AnnaBridge 172:65be27845400 4224 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4225 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
AnnaBridge 172:65be27845400 4226 #define FDCAN_IR_EP_Pos (23U)
AnnaBridge 172:65be27845400 4227 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4228 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
AnnaBridge 172:65be27845400 4229 #define FDCAN_IR_EW_Pos (24U)
AnnaBridge 172:65be27845400 4230 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4231 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
AnnaBridge 172:65be27845400 4232 #define FDCAN_IR_BO_Pos (25U)
AnnaBridge 172:65be27845400 4233 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4234 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
AnnaBridge 172:65be27845400 4235 #define FDCAN_IR_WDI_Pos (26U)
AnnaBridge 172:65be27845400 4236 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4237 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
AnnaBridge 172:65be27845400 4238 #define FDCAN_IR_PEA_Pos (27U)
AnnaBridge 172:65be27845400 4239 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4240 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
AnnaBridge 172:65be27845400 4241 #define FDCAN_IR_PED_Pos (28U)
AnnaBridge 172:65be27845400 4242 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4243 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
AnnaBridge 172:65be27845400 4244 #define FDCAN_IR_ARA_Pos (29U)
AnnaBridge 172:65be27845400 4245 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4246 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
AnnaBridge 172:65be27845400 4247
AnnaBridge 172:65be27845400 4248 /***************** Bit definition for FDCAN_IE register **********************/
AnnaBridge 172:65be27845400 4249 #define FDCAN_IE_RF0NE_Pos (0U)
AnnaBridge 172:65be27845400 4250 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4251 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
AnnaBridge 172:65be27845400 4252 #define FDCAN_IE_RF0WE_Pos (1U)
AnnaBridge 172:65be27845400 4253 #define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4254 #define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
AnnaBridge 172:65be27845400 4255 #define FDCAN_IE_RF0FE_Pos (2U)
AnnaBridge 172:65be27845400 4256 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4257 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
AnnaBridge 172:65be27845400 4258 #define FDCAN_IE_RF0LE_Pos (3U)
AnnaBridge 172:65be27845400 4259 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4260 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
AnnaBridge 172:65be27845400 4261 #define FDCAN_IE_RF1NE_Pos (4U)
AnnaBridge 172:65be27845400 4262 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4263 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
AnnaBridge 172:65be27845400 4264 #define FDCAN_IE_RF1WE_Pos (5U)
AnnaBridge 172:65be27845400 4265 #define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4266 #define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
AnnaBridge 172:65be27845400 4267 #define FDCAN_IE_RF1FE_Pos (6U)
AnnaBridge 172:65be27845400 4268 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4269 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
AnnaBridge 172:65be27845400 4270 #define FDCAN_IE_RF1LE_Pos (7U)
AnnaBridge 172:65be27845400 4271 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4272 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
AnnaBridge 172:65be27845400 4273 #define FDCAN_IE_HPME_Pos (8U)
AnnaBridge 172:65be27845400 4274 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4275 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
AnnaBridge 172:65be27845400 4276 #define FDCAN_IE_TCE_Pos (9U)
AnnaBridge 172:65be27845400 4277 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4278 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
AnnaBridge 172:65be27845400 4279 #define FDCAN_IE_TCFE_Pos (10U)
AnnaBridge 172:65be27845400 4280 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4281 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
AnnaBridge 172:65be27845400 4282 #define FDCAN_IE_TFEE_Pos (11U)
AnnaBridge 172:65be27845400 4283 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4284 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
AnnaBridge 172:65be27845400 4285 #define FDCAN_IE_TEFNE_Pos (12U)
AnnaBridge 172:65be27845400 4286 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4287 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
AnnaBridge 172:65be27845400 4288 #define FDCAN_IE_TEFWE_Pos (13U)
AnnaBridge 172:65be27845400 4289 #define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4290 #define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
AnnaBridge 172:65be27845400 4291 #define FDCAN_IE_TEFFE_Pos (14U)
AnnaBridge 172:65be27845400 4292 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4293 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
AnnaBridge 172:65be27845400 4294 #define FDCAN_IE_TEFLE_Pos (15U)
AnnaBridge 172:65be27845400 4295 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4296 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
AnnaBridge 172:65be27845400 4297 #define FDCAN_IE_TSWE_Pos (16U)
AnnaBridge 172:65be27845400 4298 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4299 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
AnnaBridge 172:65be27845400 4300 #define FDCAN_IE_MRAFE_Pos (17U)
AnnaBridge 172:65be27845400 4301 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4302 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
AnnaBridge 172:65be27845400 4303 #define FDCAN_IE_TOOE_Pos (18U)
AnnaBridge 172:65be27845400 4304 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4305 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
AnnaBridge 172:65be27845400 4306 #define FDCAN_IE_DRXE_Pos (19U)
AnnaBridge 172:65be27845400 4307 #define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4308 #define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
AnnaBridge 172:65be27845400 4309 #define FDCAN_IE_BECE_Pos (20U)
AnnaBridge 172:65be27845400 4310 #define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4311 #define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
AnnaBridge 172:65be27845400 4312 #define FDCAN_IE_BEUE_Pos (21U)
AnnaBridge 172:65be27845400 4313 #define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4314 #define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
AnnaBridge 172:65be27845400 4315 #define FDCAN_IE_ELOE_Pos (22U)
AnnaBridge 172:65be27845400 4316 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4317 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
AnnaBridge 172:65be27845400 4318 #define FDCAN_IE_EPE_Pos (23U)
AnnaBridge 172:65be27845400 4319 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4320 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
AnnaBridge 172:65be27845400 4321 #define FDCAN_IE_EWE_Pos (24U)
AnnaBridge 172:65be27845400 4322 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4323 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
AnnaBridge 172:65be27845400 4324 #define FDCAN_IE_BOE_Pos (25U)
AnnaBridge 172:65be27845400 4325 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4326 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
AnnaBridge 172:65be27845400 4327 #define FDCAN_IE_WDIE_Pos (26U)
AnnaBridge 172:65be27845400 4328 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4329 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
AnnaBridge 172:65be27845400 4330 #define FDCAN_IE_PEAE_Pos (27U)
AnnaBridge 172:65be27845400 4331 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4332 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
AnnaBridge 172:65be27845400 4333 #define FDCAN_IE_PEDE_Pos (28U)
AnnaBridge 172:65be27845400 4334 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4335 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
AnnaBridge 172:65be27845400 4336 #define FDCAN_IE_ARAE_Pos (29U)
AnnaBridge 172:65be27845400 4337 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4338 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
AnnaBridge 172:65be27845400 4339
AnnaBridge 172:65be27845400 4340 /***************** Bit definition for FDCAN_ILS register **********************/
AnnaBridge 172:65be27845400 4341 #define FDCAN_ILS_RF0NL_Pos (0U)
AnnaBridge 172:65be27845400 4342 #define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4343 #define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
AnnaBridge 172:65be27845400 4344 #define FDCAN_ILS_RF0WL_Pos (1U)
AnnaBridge 172:65be27845400 4345 #define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4346 #define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
AnnaBridge 172:65be27845400 4347 #define FDCAN_ILS_RF0FL_Pos (2U)
AnnaBridge 172:65be27845400 4348 #define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4349 #define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
AnnaBridge 172:65be27845400 4350 #define FDCAN_ILS_RF0LL_Pos (3U)
AnnaBridge 172:65be27845400 4351 #define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4352 #define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
AnnaBridge 172:65be27845400 4353 #define FDCAN_ILS_RF1NL_Pos (4U)
AnnaBridge 172:65be27845400 4354 #define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4355 #define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
AnnaBridge 172:65be27845400 4356 #define FDCAN_ILS_RF1WL_Pos (5U)
AnnaBridge 172:65be27845400 4357 #define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4358 #define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
AnnaBridge 172:65be27845400 4359 #define FDCAN_ILS_RF1FL_Pos (6U)
AnnaBridge 172:65be27845400 4360 #define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4361 #define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
AnnaBridge 172:65be27845400 4362 #define FDCAN_ILS_RF1LL_Pos (7U)
AnnaBridge 172:65be27845400 4363 #define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4364 #define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
AnnaBridge 172:65be27845400 4365 #define FDCAN_ILS_HPML_Pos (8U)
AnnaBridge 172:65be27845400 4366 #define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4367 #define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
AnnaBridge 172:65be27845400 4368 #define FDCAN_ILS_TCL_Pos (9U)
AnnaBridge 172:65be27845400 4369 #define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4370 #define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
AnnaBridge 172:65be27845400 4371 #define FDCAN_ILS_TCFL_Pos (10U)
AnnaBridge 172:65be27845400 4372 #define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4373 #define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
AnnaBridge 172:65be27845400 4374 #define FDCAN_ILS_TFEL_Pos (11U)
AnnaBridge 172:65be27845400 4375 #define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4376 #define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
AnnaBridge 172:65be27845400 4377 #define FDCAN_ILS_TEFNL_Pos (12U)
AnnaBridge 172:65be27845400 4378 #define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4379 #define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
AnnaBridge 172:65be27845400 4380 #define FDCAN_ILS_TEFWL_Pos (13U)
AnnaBridge 172:65be27845400 4381 #define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4382 #define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
AnnaBridge 172:65be27845400 4383 #define FDCAN_ILS_TEFFL_Pos (14U)
AnnaBridge 172:65be27845400 4384 #define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4385 #define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
AnnaBridge 172:65be27845400 4386 #define FDCAN_ILS_TEFLL_Pos (15U)
AnnaBridge 172:65be27845400 4387 #define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4388 #define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
AnnaBridge 172:65be27845400 4389 #define FDCAN_ILS_TSWL_Pos (16U)
AnnaBridge 172:65be27845400 4390 #define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4391 #define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
AnnaBridge 172:65be27845400 4392 #define FDCAN_ILS_MRAFE_Pos (17U)
AnnaBridge 172:65be27845400 4393 #define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4394 #define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
AnnaBridge 172:65be27845400 4395 #define FDCAN_ILS_TOOE_Pos (18U)
AnnaBridge 172:65be27845400 4396 #define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4397 #define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
AnnaBridge 172:65be27845400 4398 #define FDCAN_ILS_DRXE_Pos (19U)
AnnaBridge 172:65be27845400 4399 #define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4400 #define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
AnnaBridge 172:65be27845400 4401 #define FDCAN_ILS_BECE_Pos (20U)
AnnaBridge 172:65be27845400 4402 #define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4403 #define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
AnnaBridge 172:65be27845400 4404 #define FDCAN_ILS_BEUE_Pos (21U)
AnnaBridge 172:65be27845400 4405 #define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4406 #define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
AnnaBridge 172:65be27845400 4407 #define FDCAN_ILS_ELOE_Pos (22U)
AnnaBridge 172:65be27845400 4408 #define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4409 #define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
AnnaBridge 172:65be27845400 4410 #define FDCAN_ILS_EPE_Pos (23U)
AnnaBridge 172:65be27845400 4411 #define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4412 #define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
AnnaBridge 172:65be27845400 4413 #define FDCAN_ILS_EWE_Pos (24U)
AnnaBridge 172:65be27845400 4414 #define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4415 #define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
AnnaBridge 172:65be27845400 4416 #define FDCAN_ILS_BOE_Pos (25U)
AnnaBridge 172:65be27845400 4417 #define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4418 #define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
AnnaBridge 172:65be27845400 4419 #define FDCAN_ILS_WDIE_Pos (26U)
AnnaBridge 172:65be27845400 4420 #define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4421 #define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
AnnaBridge 172:65be27845400 4422 #define FDCAN_ILS_PEAE_Pos (27U)
AnnaBridge 172:65be27845400 4423 #define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4424 #define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
AnnaBridge 172:65be27845400 4425 #define FDCAN_ILS_PEDE_Pos (28U)
AnnaBridge 172:65be27845400 4426 #define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4427 #define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
AnnaBridge 172:65be27845400 4428 #define FDCAN_ILS_ARAE_Pos (29U)
AnnaBridge 172:65be27845400 4429 #define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4430 #define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
AnnaBridge 172:65be27845400 4431
AnnaBridge 172:65be27845400 4432 /***************** Bit definition for FDCAN_ILE register **********************/
AnnaBridge 172:65be27845400 4433 #define FDCAN_ILE_EINT0_Pos (0U)
AnnaBridge 172:65be27845400 4434 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4435 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
AnnaBridge 172:65be27845400 4436 #define FDCAN_ILE_EINT1_Pos (1U)
AnnaBridge 172:65be27845400 4437 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4438 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
AnnaBridge 172:65be27845400 4439
AnnaBridge 172:65be27845400 4440 /***************** Bit definition for FDCAN_GFC register **********************/
AnnaBridge 172:65be27845400 4441 #define FDCAN_GFC_RRFE_Pos (0U)
AnnaBridge 172:65be27845400 4442 #define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4443 #define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
AnnaBridge 172:65be27845400 4444 #define FDCAN_GFC_RRFS_Pos (1U)
AnnaBridge 172:65be27845400 4445 #define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4446 #define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
AnnaBridge 172:65be27845400 4447 #define FDCAN_GFC_ANFE_Pos (2U)
AnnaBridge 172:65be27845400 4448 #define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 4449 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
AnnaBridge 172:65be27845400 4450 #define FDCAN_GFC_ANFS_Pos (4U)
AnnaBridge 172:65be27845400 4451 #define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 4452 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
AnnaBridge 172:65be27845400 4453
AnnaBridge 172:65be27845400 4454 /***************** Bit definition for FDCAN_SIDFC register ********************/
AnnaBridge 172:65be27845400 4455 #define FDCAN_SIDFC_FLSSA_Pos (2U)
AnnaBridge 172:65be27845400 4456 #define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4457 #define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
AnnaBridge 172:65be27845400 4458 #define FDCAN_SIDFC_LSS_Pos (16U)
AnnaBridge 172:65be27845400 4459 #define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 4460 #define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
AnnaBridge 172:65be27845400 4461
AnnaBridge 172:65be27845400 4462 /***************** Bit definition for FDCAN_XIDFC register ********************/
AnnaBridge 172:65be27845400 4463 #define FDCAN_XIDFC_FLESA_Pos (2U)
AnnaBridge 172:65be27845400 4464 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4465 #define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
AnnaBridge 172:65be27845400 4466 #define FDCAN_XIDFC_LSE_Pos (16U)
AnnaBridge 172:65be27845400 4467 #define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 4468 #define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
AnnaBridge 172:65be27845400 4469
AnnaBridge 172:65be27845400 4470 /***************** Bit definition for FDCAN_XIDAM register ********************/
AnnaBridge 172:65be27845400 4471 #define FDCAN_XIDAM_EIDM_Pos (0U)
AnnaBridge 172:65be27845400 4472 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
AnnaBridge 172:65be27845400 4473 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
AnnaBridge 172:65be27845400 4474
AnnaBridge 172:65be27845400 4475 /***************** Bit definition for FDCAN_HPMS register *********************/
AnnaBridge 172:65be27845400 4476 #define FDCAN_HPMS_BIDX_Pos (0U)
AnnaBridge 172:65be27845400 4477 #define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 4478 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
AnnaBridge 172:65be27845400 4479 #define FDCAN_HPMS_MSI_Pos (6U)
AnnaBridge 172:65be27845400 4480 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 4481 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
AnnaBridge 172:65be27845400 4482 #define FDCAN_HPMS_FIDX_Pos (8U)
AnnaBridge 172:65be27845400 4483 #define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
AnnaBridge 172:65be27845400 4484 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
AnnaBridge 172:65be27845400 4485 #define FDCAN_HPMS_FLST_Pos (15U)
AnnaBridge 172:65be27845400 4486 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4487 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
AnnaBridge 172:65be27845400 4488
AnnaBridge 172:65be27845400 4489 /***************** Bit definition for FDCAN_NDAT1 register ********************/
AnnaBridge 172:65be27845400 4490 #define FDCAN_NDAT1_ND0_Pos (0U)
AnnaBridge 172:65be27845400 4491 #define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4492 #define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
AnnaBridge 172:65be27845400 4493 #define FDCAN_NDAT1_ND1_Pos (1U)
AnnaBridge 172:65be27845400 4494 #define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4495 #define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
AnnaBridge 172:65be27845400 4496 #define FDCAN_NDAT1_ND2_Pos (2U)
AnnaBridge 172:65be27845400 4497 #define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4498 #define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
AnnaBridge 172:65be27845400 4499 #define FDCAN_NDAT1_ND3_Pos (3U)
AnnaBridge 172:65be27845400 4500 #define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4501 #define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
AnnaBridge 172:65be27845400 4502 #define FDCAN_NDAT1_ND4_Pos (4U)
AnnaBridge 172:65be27845400 4503 #define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4504 #define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
AnnaBridge 172:65be27845400 4505 #define FDCAN_NDAT1_ND5_Pos (5U)
AnnaBridge 172:65be27845400 4506 #define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4507 #define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
AnnaBridge 172:65be27845400 4508 #define FDCAN_NDAT1_ND6_Pos (6U)
AnnaBridge 172:65be27845400 4509 #define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4510 #define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
AnnaBridge 172:65be27845400 4511 #define FDCAN_NDAT1_ND7_Pos (7U)
AnnaBridge 172:65be27845400 4512 #define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4513 #define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
AnnaBridge 172:65be27845400 4514 #define FDCAN_NDAT1_ND8_Pos (8U)
AnnaBridge 172:65be27845400 4515 #define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4516 #define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
AnnaBridge 172:65be27845400 4517 #define FDCAN_NDAT1_ND9_Pos (9U)
AnnaBridge 172:65be27845400 4518 #define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4519 #define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
AnnaBridge 172:65be27845400 4520 #define FDCAN_NDAT1_ND10_Pos (10U)
AnnaBridge 172:65be27845400 4521 #define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4522 #define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
AnnaBridge 172:65be27845400 4523 #define FDCAN_NDAT1_ND11_Pos (11U)
AnnaBridge 172:65be27845400 4524 #define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4525 #define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
AnnaBridge 172:65be27845400 4526 #define FDCAN_NDAT1_ND12_Pos (12U)
AnnaBridge 172:65be27845400 4527 #define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4528 #define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
AnnaBridge 172:65be27845400 4529 #define FDCAN_NDAT1_ND13_Pos (13U)
AnnaBridge 172:65be27845400 4530 #define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4531 #define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
AnnaBridge 172:65be27845400 4532 #define FDCAN_NDAT1_ND14_Pos (14U)
AnnaBridge 172:65be27845400 4533 #define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4534 #define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
AnnaBridge 172:65be27845400 4535 #define FDCAN_NDAT1_ND15_Pos (15U)
AnnaBridge 172:65be27845400 4536 #define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4537 #define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
AnnaBridge 172:65be27845400 4538 #define FDCAN_NDAT1_ND16_Pos (16U)
AnnaBridge 172:65be27845400 4539 #define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4540 #define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
AnnaBridge 172:65be27845400 4541 #define FDCAN_NDAT1_ND17_Pos (17U)
AnnaBridge 172:65be27845400 4542 #define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4543 #define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
AnnaBridge 172:65be27845400 4544 #define FDCAN_NDAT1_ND18_Pos (18U)
AnnaBridge 172:65be27845400 4545 #define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4546 #define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
AnnaBridge 172:65be27845400 4547 #define FDCAN_NDAT1_ND19_Pos (19U)
AnnaBridge 172:65be27845400 4548 #define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4549 #define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
AnnaBridge 172:65be27845400 4550 #define FDCAN_NDAT1_ND20_Pos (20U)
AnnaBridge 172:65be27845400 4551 #define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4552 #define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
AnnaBridge 172:65be27845400 4553 #define FDCAN_NDAT1_ND21_Pos (21U)
AnnaBridge 172:65be27845400 4554 #define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4555 #define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
AnnaBridge 172:65be27845400 4556 #define FDCAN_NDAT1_ND22_Pos (22U)
AnnaBridge 172:65be27845400 4557 #define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4558 #define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
AnnaBridge 172:65be27845400 4559 #define FDCAN_NDAT1_ND23_Pos (23U)
AnnaBridge 172:65be27845400 4560 #define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4561 #define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
AnnaBridge 172:65be27845400 4562 #define FDCAN_NDAT1_ND24_Pos (24U)
AnnaBridge 172:65be27845400 4563 #define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4564 #define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
AnnaBridge 172:65be27845400 4565 #define FDCAN_NDAT1_ND25_Pos (25U)
AnnaBridge 172:65be27845400 4566 #define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4567 #define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
AnnaBridge 172:65be27845400 4568 #define FDCAN_NDAT1_ND26_Pos (26U)
AnnaBridge 172:65be27845400 4569 #define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4570 #define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
AnnaBridge 172:65be27845400 4571 #define FDCAN_NDAT1_ND27_Pos (27U)
AnnaBridge 172:65be27845400 4572 #define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4573 #define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
AnnaBridge 172:65be27845400 4574 #define FDCAN_NDAT1_ND28_Pos (28U)
AnnaBridge 172:65be27845400 4575 #define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4576 #define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
AnnaBridge 172:65be27845400 4577 #define FDCAN_NDAT1_ND29_Pos (29U)
AnnaBridge 172:65be27845400 4578 #define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4579 #define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
AnnaBridge 172:65be27845400 4580 #define FDCAN_NDAT1_ND30_Pos (30U)
AnnaBridge 172:65be27845400 4581 #define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4582 #define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
AnnaBridge 172:65be27845400 4583 #define FDCAN_NDAT1_ND31_Pos (31U)
AnnaBridge 172:65be27845400 4584 #define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4585 #define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
AnnaBridge 172:65be27845400 4586
AnnaBridge 172:65be27845400 4587 /***************** Bit definition for FDCAN_NDAT2 register ********************/
AnnaBridge 172:65be27845400 4588 #define FDCAN_NDAT2_ND32_Pos (0U)
AnnaBridge 172:65be27845400 4589 #define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4590 #define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
AnnaBridge 172:65be27845400 4591 #define FDCAN_NDAT2_ND33_Pos (1U)
AnnaBridge 172:65be27845400 4592 #define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4593 #define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
AnnaBridge 172:65be27845400 4594 #define FDCAN_NDAT2_ND34_Pos (2U)
AnnaBridge 172:65be27845400 4595 #define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4596 #define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
AnnaBridge 172:65be27845400 4597 #define FDCAN_NDAT2_ND35_Pos (3U)
AnnaBridge 172:65be27845400 4598 #define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4599 #define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
AnnaBridge 172:65be27845400 4600 #define FDCAN_NDAT2_ND36_Pos (4U)
AnnaBridge 172:65be27845400 4601 #define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4602 #define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
AnnaBridge 172:65be27845400 4603 #define FDCAN_NDAT2_ND37_Pos (5U)
AnnaBridge 172:65be27845400 4604 #define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4605 #define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
AnnaBridge 172:65be27845400 4606 #define FDCAN_NDAT2_ND38_Pos (6U)
AnnaBridge 172:65be27845400 4607 #define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 4608 #define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
AnnaBridge 172:65be27845400 4609 #define FDCAN_NDAT2_ND39_Pos (7U)
AnnaBridge 172:65be27845400 4610 #define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 4611 #define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
AnnaBridge 172:65be27845400 4612 #define FDCAN_NDAT2_ND40_Pos (8U)
AnnaBridge 172:65be27845400 4613 #define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4614 #define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
AnnaBridge 172:65be27845400 4615 #define FDCAN_NDAT2_ND41_Pos (9U)
AnnaBridge 172:65be27845400 4616 #define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4617 #define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
AnnaBridge 172:65be27845400 4618 #define FDCAN_NDAT2_ND42_Pos (10U)
AnnaBridge 172:65be27845400 4619 #define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4620 #define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
AnnaBridge 172:65be27845400 4621 #define FDCAN_NDAT2_ND43_Pos (11U)
AnnaBridge 172:65be27845400 4622 #define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4623 #define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
AnnaBridge 172:65be27845400 4624 #define FDCAN_NDAT2_ND44_Pos (12U)
AnnaBridge 172:65be27845400 4625 #define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4626 #define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
AnnaBridge 172:65be27845400 4627 #define FDCAN_NDAT2_ND45_Pos (13U)
AnnaBridge 172:65be27845400 4628 #define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4629 #define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
AnnaBridge 172:65be27845400 4630 #define FDCAN_NDAT2_ND46_Pos (14U)
AnnaBridge 172:65be27845400 4631 #define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 4632 #define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
AnnaBridge 172:65be27845400 4633 #define FDCAN_NDAT2_ND47_Pos (15U)
AnnaBridge 172:65be27845400 4634 #define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4635 #define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
AnnaBridge 172:65be27845400 4636 #define FDCAN_NDAT2_ND48_Pos (16U)
AnnaBridge 172:65be27845400 4637 #define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 4638 #define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
AnnaBridge 172:65be27845400 4639 #define FDCAN_NDAT2_ND49_Pos (17U)
AnnaBridge 172:65be27845400 4640 #define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 4641 #define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
AnnaBridge 172:65be27845400 4642 #define FDCAN_NDAT2_ND50_Pos (18U)
AnnaBridge 172:65be27845400 4643 #define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 4644 #define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
AnnaBridge 172:65be27845400 4645 #define FDCAN_NDAT2_ND51_Pos (19U)
AnnaBridge 172:65be27845400 4646 #define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 4647 #define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
AnnaBridge 172:65be27845400 4648 #define FDCAN_NDAT2_ND52_Pos (20U)
AnnaBridge 172:65be27845400 4649 #define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 4650 #define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
AnnaBridge 172:65be27845400 4651 #define FDCAN_NDAT2_ND53_Pos (21U)
AnnaBridge 172:65be27845400 4652 #define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4653 #define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
AnnaBridge 172:65be27845400 4654 #define FDCAN_NDAT2_ND54_Pos (22U)
AnnaBridge 172:65be27845400 4655 #define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 4656 #define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
AnnaBridge 172:65be27845400 4657 #define FDCAN_NDAT2_ND55_Pos (23U)
AnnaBridge 172:65be27845400 4658 #define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 4659 #define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
AnnaBridge 172:65be27845400 4660 #define FDCAN_NDAT2_ND56_Pos (24U)
AnnaBridge 172:65be27845400 4661 #define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4662 #define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
AnnaBridge 172:65be27845400 4663 #define FDCAN_NDAT2_ND57_Pos (25U)
AnnaBridge 172:65be27845400 4664 #define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4665 #define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
AnnaBridge 172:65be27845400 4666 #define FDCAN_NDAT2_ND58_Pos (26U)
AnnaBridge 172:65be27845400 4667 #define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4668 #define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
AnnaBridge 172:65be27845400 4669 #define FDCAN_NDAT2_ND59_Pos (27U)
AnnaBridge 172:65be27845400 4670 #define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 4671 #define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
AnnaBridge 172:65be27845400 4672 #define FDCAN_NDAT2_ND60_Pos (28U)
AnnaBridge 172:65be27845400 4673 #define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 4674 #define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
AnnaBridge 172:65be27845400 4675 #define FDCAN_NDAT2_ND61_Pos (29U)
AnnaBridge 172:65be27845400 4676 #define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 4677 #define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
AnnaBridge 172:65be27845400 4678 #define FDCAN_NDAT2_ND62_Pos (30U)
AnnaBridge 172:65be27845400 4679 #define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4680 #define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
AnnaBridge 172:65be27845400 4681 #define FDCAN_NDAT2_ND63_Pos (31U)
AnnaBridge 172:65be27845400 4682 #define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4683 #define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
AnnaBridge 172:65be27845400 4684
AnnaBridge 172:65be27845400 4685 /***************** Bit definition for FDCAN_RXF0C register ********************/
AnnaBridge 172:65be27845400 4686 #define FDCAN_RXF0C_F0SA_Pos (2U)
AnnaBridge 172:65be27845400 4687 #define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4688 #define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
AnnaBridge 172:65be27845400 4689 #define FDCAN_RXF0C_F0S_Pos (16U)
AnnaBridge 172:65be27845400 4690 #define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 4691 #define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
AnnaBridge 172:65be27845400 4692 #define FDCAN_RXF0C_F0WM_Pos (24U)
AnnaBridge 172:65be27845400 4693 #define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
AnnaBridge 172:65be27845400 4694 #define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
AnnaBridge 172:65be27845400 4695 #define FDCAN_RXF0C_F0OM_Pos (31U)
AnnaBridge 172:65be27845400 4696 #define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4697 #define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
AnnaBridge 172:65be27845400 4698
AnnaBridge 172:65be27845400 4699 /***************** Bit definition for FDCAN_RXF0S register ********************/
AnnaBridge 172:65be27845400 4700 #define FDCAN_RXF0S_F0FL_Pos (0U)
AnnaBridge 172:65be27845400 4701 #define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 4702 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
AnnaBridge 172:65be27845400 4703 #define FDCAN_RXF0S_F0GI_Pos (8U)
AnnaBridge 172:65be27845400 4704 #define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
AnnaBridge 172:65be27845400 4705 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
AnnaBridge 172:65be27845400 4706 #define FDCAN_RXF0S_F0PI_Pos (16U)
AnnaBridge 172:65be27845400 4707 #define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
AnnaBridge 172:65be27845400 4708 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
AnnaBridge 172:65be27845400 4709 #define FDCAN_RXF0S_F0F_Pos (24U)
AnnaBridge 172:65be27845400 4710 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4711 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
AnnaBridge 172:65be27845400 4712 #define FDCAN_RXF0S_RF0L_Pos (25U)
AnnaBridge 172:65be27845400 4713 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4714 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
AnnaBridge 172:65be27845400 4715
AnnaBridge 172:65be27845400 4716 /***************** Bit definition for FDCAN_RXF0A register ********************/
AnnaBridge 172:65be27845400 4717 #define FDCAN_RXF0A_F0AI_Pos (0U)
AnnaBridge 172:65be27845400 4718 #define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 4719 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
AnnaBridge 172:65be27845400 4720
AnnaBridge 172:65be27845400 4721 /***************** Bit definition for FDCAN_RXBC register ********************/
AnnaBridge 172:65be27845400 4722 #define FDCAN_RXBC_RBSA_Pos (2U)
AnnaBridge 172:65be27845400 4723 #define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4724 #define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
AnnaBridge 172:65be27845400 4725
AnnaBridge 172:65be27845400 4726 /***************** Bit definition for FDCAN_RXF1C register ********************/
AnnaBridge 172:65be27845400 4727 #define FDCAN_RXF1C_F1SA_Pos (2U)
AnnaBridge 172:65be27845400 4728 #define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4729 #define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
AnnaBridge 172:65be27845400 4730 #define FDCAN_RXF1C_F1S_Pos (16U)
AnnaBridge 172:65be27845400 4731 #define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 4732 #define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
AnnaBridge 172:65be27845400 4733 #define FDCAN_RXF1C_F1WM_Pos (24U)
AnnaBridge 172:65be27845400 4734 #define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
AnnaBridge 172:65be27845400 4735 #define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
AnnaBridge 172:65be27845400 4736 #define FDCAN_RXF1C_F1OM_Pos (31U)
AnnaBridge 172:65be27845400 4737 #define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4738 #define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
AnnaBridge 172:65be27845400 4739
AnnaBridge 172:65be27845400 4740 /***************** Bit definition for FDCAN_RXF1S register ********************/
AnnaBridge 172:65be27845400 4741 #define FDCAN_RXF1S_F1FL_Pos (0U)
AnnaBridge 172:65be27845400 4742 #define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 4743 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
AnnaBridge 172:65be27845400 4744 #define FDCAN_RXF1S_F1GI_Pos (8U)
AnnaBridge 172:65be27845400 4745 #define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
AnnaBridge 172:65be27845400 4746 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
AnnaBridge 172:65be27845400 4747 #define FDCAN_RXF1S_F1PI_Pos (16U)
AnnaBridge 172:65be27845400 4748 #define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
AnnaBridge 172:65be27845400 4749 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
AnnaBridge 172:65be27845400 4750 #define FDCAN_RXF1S_F1F_Pos (24U)
AnnaBridge 172:65be27845400 4751 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4752 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
AnnaBridge 172:65be27845400 4753 #define FDCAN_RXF1S_RF1L_Pos (25U)
AnnaBridge 172:65be27845400 4754 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4755 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
AnnaBridge 172:65be27845400 4756
AnnaBridge 172:65be27845400 4757 /***************** Bit definition for FDCAN_RXF1A register ********************/
AnnaBridge 172:65be27845400 4758 #define FDCAN_RXF1A_F1AI_Pos (0U)
AnnaBridge 172:65be27845400 4759 #define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 4760 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
AnnaBridge 172:65be27845400 4761
AnnaBridge 172:65be27845400 4762 /***************** Bit definition for FDCAN_RXESC register ********************/
AnnaBridge 172:65be27845400 4763 #define FDCAN_RXESC_F0DS_Pos (0U)
AnnaBridge 172:65be27845400 4764 #define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 4765 #define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
AnnaBridge 172:65be27845400 4766 #define FDCAN_RXESC_F1DS_Pos (4U)
AnnaBridge 172:65be27845400 4767 #define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 4768 #define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
AnnaBridge 172:65be27845400 4769 #define FDCAN_RXESC_RBDS_Pos (8U)
AnnaBridge 172:65be27845400 4770 #define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 4771 #define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
AnnaBridge 172:65be27845400 4772
AnnaBridge 172:65be27845400 4773 /***************** Bit definition for FDCAN_TXBC register *********************/
AnnaBridge 172:65be27845400 4774 #define FDCAN_TXBC_TBSA_Pos (2U)
AnnaBridge 172:65be27845400 4775 #define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4776 #define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
AnnaBridge 172:65be27845400 4777 #define FDCAN_TXBC_NDTB_Pos (16U)
AnnaBridge 172:65be27845400 4778 #define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
AnnaBridge 172:65be27845400 4779 #define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
AnnaBridge 172:65be27845400 4780 #define FDCAN_TXBC_TFQS_Pos (24U)
AnnaBridge 172:65be27845400 4781 #define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 4782 #define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
AnnaBridge 172:65be27845400 4783 #define FDCAN_TXBC_TFQM_Pos (30U)
AnnaBridge 172:65be27845400 4784 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4785 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
AnnaBridge 172:65be27845400 4786
AnnaBridge 172:65be27845400 4787 /***************** Bit definition for FDCAN_TXFQS register *********************/
AnnaBridge 172:65be27845400 4788 #define FDCAN_TXFQS_TFFL_Pos (0U)
AnnaBridge 172:65be27845400 4789 #define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 4790 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
AnnaBridge 172:65be27845400 4791 #define FDCAN_TXFQS_TFGI_Pos (8U)
AnnaBridge 172:65be27845400 4792 #define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 4793 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
AnnaBridge 172:65be27845400 4794 #define FDCAN_TXFQS_TFQPI_Pos (16U)
AnnaBridge 172:65be27845400 4795 #define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 4796 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
AnnaBridge 172:65be27845400 4797 #define FDCAN_TXFQS_TFQF_Pos (21U)
AnnaBridge 172:65be27845400 4798 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 4799 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
AnnaBridge 172:65be27845400 4800
AnnaBridge 172:65be27845400 4801 /***************** Bit definition for FDCAN_TXESC register *********************/
AnnaBridge 172:65be27845400 4802 #define FDCAN_TXESC_TBDS_Pos (0U)
AnnaBridge 172:65be27845400 4803 #define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 4804 #define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
AnnaBridge 172:65be27845400 4805
AnnaBridge 172:65be27845400 4806 /***************** Bit definition for FDCAN_TXBRP register *********************/
AnnaBridge 172:65be27845400 4807 #define FDCAN_TXBRP_TRP_Pos (0U)
AnnaBridge 172:65be27845400 4808 #define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 4809 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
AnnaBridge 172:65be27845400 4810
AnnaBridge 172:65be27845400 4811 /***************** Bit definition for FDCAN_TXBAR register *********************/
AnnaBridge 172:65be27845400 4812 #define FDCAN_TXBAR_AR_Pos (0U)
AnnaBridge 172:65be27845400 4813 #define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 4814 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
AnnaBridge 172:65be27845400 4815
AnnaBridge 172:65be27845400 4816 /***************** Bit definition for FDCAN_TXBCR register *********************/
AnnaBridge 172:65be27845400 4817 #define FDCAN_TXBCR_CR_Pos (0U)
AnnaBridge 172:65be27845400 4818 #define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 4819 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
AnnaBridge 172:65be27845400 4820
AnnaBridge 172:65be27845400 4821 /***************** Bit definition for FDCAN_TXBTO register *********************/
AnnaBridge 172:65be27845400 4822 #define FDCAN_TXBTO_TO_Pos (0U)
AnnaBridge 172:65be27845400 4823 #define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 4824 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
AnnaBridge 172:65be27845400 4825
AnnaBridge 172:65be27845400 4826 /***************** Bit definition for FDCAN_TXBCF register *********************/
AnnaBridge 172:65be27845400 4827 #define FDCAN_TXBCF_CF_Pos (0U)
AnnaBridge 172:65be27845400 4828 #define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 4829 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
AnnaBridge 172:65be27845400 4830
AnnaBridge 172:65be27845400 4831 /***************** Bit definition for FDCAN_TXBTIE register ********************/
AnnaBridge 172:65be27845400 4832 #define FDCAN_TXBTIE_TIE_Pos (0U)
AnnaBridge 172:65be27845400 4833 #define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 4834 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
AnnaBridge 172:65be27845400 4835
AnnaBridge 172:65be27845400 4836 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
AnnaBridge 172:65be27845400 4837 #define FDCAN_TXBCIE_CFIE_Pos (0U)
AnnaBridge 172:65be27845400 4838 #define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 4839 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
AnnaBridge 172:65be27845400 4840
AnnaBridge 172:65be27845400 4841 /***************** Bit definition for FDCAN_TXEFC register *********************/
AnnaBridge 172:65be27845400 4842 #define FDCAN_TXEFC_EFSA_Pos (2U)
AnnaBridge 172:65be27845400 4843 #define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4844 #define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
AnnaBridge 172:65be27845400 4845 #define FDCAN_TXEFC_EFS_Pos (16U)
AnnaBridge 172:65be27845400 4846 #define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
AnnaBridge 172:65be27845400 4847 #define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
AnnaBridge 172:65be27845400 4848 #define FDCAN_TXEFC_EFWM_Pos (24U)
AnnaBridge 172:65be27845400 4849 #define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 4850 #define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
AnnaBridge 172:65be27845400 4851
AnnaBridge 172:65be27845400 4852 /***************** Bit definition for FDCAN_TXEFS register *********************/
AnnaBridge 172:65be27845400 4853 #define FDCAN_TXEFS_EFFL_Pos (0U)
AnnaBridge 172:65be27845400 4854 #define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 4855 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
AnnaBridge 172:65be27845400 4856 #define FDCAN_TXEFS_EFGI_Pos (8U)
AnnaBridge 172:65be27845400 4857 #define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 4858 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
AnnaBridge 172:65be27845400 4859 #define FDCAN_TXEFS_EFPI_Pos (16U)
AnnaBridge 172:65be27845400 4860 #define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 4861 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
AnnaBridge 172:65be27845400 4862 #define FDCAN_TXEFS_EFF_Pos (24U)
AnnaBridge 172:65be27845400 4863 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4864 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
AnnaBridge 172:65be27845400 4865 #define FDCAN_TXEFS_TEFL_Pos (25U)
AnnaBridge 172:65be27845400 4866 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4867 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
AnnaBridge 172:65be27845400 4868
AnnaBridge 172:65be27845400 4869 /***************** Bit definition for FDCAN_TXEFA register *********************/
AnnaBridge 172:65be27845400 4870 #define FDCAN_TXEFA_EFAI_Pos (0U)
AnnaBridge 172:65be27845400 4871 #define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 4872 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
AnnaBridge 172:65be27845400 4873
AnnaBridge 172:65be27845400 4874 /***************** Bit definition for FDCAN_TTTMC register *********************/
AnnaBridge 172:65be27845400 4875 #define FDCAN_TTTMC_TMSA_Pos (2U)
AnnaBridge 172:65be27845400 4876 #define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
AnnaBridge 172:65be27845400 4877 #define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
AnnaBridge 172:65be27845400 4878 #define FDCAN_TTTMC_TME_Pos (16U)
AnnaBridge 172:65be27845400 4879 #define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 4880 #define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
AnnaBridge 172:65be27845400 4881
AnnaBridge 172:65be27845400 4882 /***************** Bit definition for FDCAN_TTRMC register *********************/
AnnaBridge 172:65be27845400 4883 #define FDCAN_TTRMC_RID_Pos (0U)
AnnaBridge 172:65be27845400 4884 #define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
AnnaBridge 172:65be27845400 4885 #define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
AnnaBridge 172:65be27845400 4886 #define FDCAN_TTRMC_XTD_Pos (30U)
AnnaBridge 172:65be27845400 4887 #define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 4888 #define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
AnnaBridge 172:65be27845400 4889 #define FDCAN_TTRMC_RMPS_Pos (31U)
AnnaBridge 172:65be27845400 4890 #define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4891 #define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
AnnaBridge 172:65be27845400 4892
AnnaBridge 172:65be27845400 4893 /***************** Bit definition for FDCAN_TTOCF register *********************/
AnnaBridge 172:65be27845400 4894 #define FDCAN_TTOCF_OM_Pos (0U)
AnnaBridge 172:65be27845400 4895 #define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 4896 #define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
AnnaBridge 172:65be27845400 4897 #define FDCAN_TTOCF_GEN_Pos (3U)
AnnaBridge 172:65be27845400 4898 #define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 4899 #define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
AnnaBridge 172:65be27845400 4900 #define FDCAN_TTOCF_TM_Pos (4U)
AnnaBridge 172:65be27845400 4901 #define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 4902 #define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
AnnaBridge 172:65be27845400 4903 #define FDCAN_TTOCF_LDSDL_Pos (5U)
AnnaBridge 172:65be27845400 4904 #define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
AnnaBridge 172:65be27845400 4905 #define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
AnnaBridge 172:65be27845400 4906 #define FDCAN_TTOCF_IRTO_Pos (8U)
AnnaBridge 172:65be27845400 4907 #define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
AnnaBridge 172:65be27845400 4908 #define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
AnnaBridge 172:65be27845400 4909 #define FDCAN_TTOCF_EECS_Pos (15U)
AnnaBridge 172:65be27845400 4910 #define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4911 #define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
AnnaBridge 172:65be27845400 4912 #define FDCAN_TTOCF_AWL_Pos (16U)
AnnaBridge 172:65be27845400 4913 #define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 4914 #define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
AnnaBridge 172:65be27845400 4915 #define FDCAN_TTOCF_EGTF_Pos (24U)
AnnaBridge 172:65be27845400 4916 #define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 4917 #define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
AnnaBridge 172:65be27845400 4918 #define FDCAN_TTOCF_ECC_Pos (25U)
AnnaBridge 172:65be27845400 4919 #define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 4920 #define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
AnnaBridge 172:65be27845400 4921 #define FDCAN_TTOCF_EVTP_Pos (26U)
AnnaBridge 172:65be27845400 4922 #define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 4923 #define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
AnnaBridge 172:65be27845400 4924
AnnaBridge 172:65be27845400 4925 /***************** Bit definition for FDCAN_TTMLM register *********************/
AnnaBridge 172:65be27845400 4926 #define FDCAN_TTMLM_CCM_Pos (0U)
AnnaBridge 172:65be27845400 4927 #define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 4928 #define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
AnnaBridge 172:65be27845400 4929 #define FDCAN_TTMLM_CSS_Pos (6U)
AnnaBridge 172:65be27845400 4930 #define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 4931 #define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
AnnaBridge 172:65be27845400 4932 #define FDCAN_TTMLM_TXEW_Pos (8U)
AnnaBridge 172:65be27845400 4933 #define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 4934 #define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
AnnaBridge 172:65be27845400 4935 #define FDCAN_TTMLM_ENTT_Pos (16U)
AnnaBridge 172:65be27845400 4936 #define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 4937 #define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
AnnaBridge 172:65be27845400 4938
AnnaBridge 172:65be27845400 4939 /***************** Bit definition for FDCAN_TURCF register *********************/
AnnaBridge 172:65be27845400 4940 #define FDCAN_TURCF_NCL_Pos (0U)
AnnaBridge 172:65be27845400 4941 #define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 4942 #define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
AnnaBridge 172:65be27845400 4943 #define FDCAN_TURCF_DC_Pos (16U)
AnnaBridge 172:65be27845400 4944 #define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
AnnaBridge 172:65be27845400 4945 #define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
AnnaBridge 172:65be27845400 4946 #define FDCAN_TURCF_ELT_Pos (31U)
AnnaBridge 172:65be27845400 4947 #define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 4948 #define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
AnnaBridge 172:65be27845400 4949
AnnaBridge 172:65be27845400 4950 /***************** Bit definition for FDCAN_TTOCN register ********************/
AnnaBridge 172:65be27845400 4951 #define FDCAN_TTOCN_SGT_Pos (0U)
AnnaBridge 172:65be27845400 4952 #define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 4953 #define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
AnnaBridge 172:65be27845400 4954 #define FDCAN_TTOCN_ECS_Pos (1U)
AnnaBridge 172:65be27845400 4955 #define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 4956 #define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
AnnaBridge 172:65be27845400 4957 #define FDCAN_TTOCN_SWP_Pos (2U)
AnnaBridge 172:65be27845400 4958 #define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 4959 #define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
AnnaBridge 172:65be27845400 4960 #define FDCAN_TTOCN_SWS_Pos (3U)
AnnaBridge 172:65be27845400 4961 #define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 4962 #define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
AnnaBridge 172:65be27845400 4963 #define FDCAN_TTOCN_RTIE_Pos (5U)
AnnaBridge 172:65be27845400 4964 #define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 4965 #define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
AnnaBridge 172:65be27845400 4966 #define FDCAN_TTOCN_TMC_Pos (6U)
AnnaBridge 172:65be27845400 4967 #define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 4968 #define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
AnnaBridge 172:65be27845400 4969 #define FDCAN_TTOCN_TTIE_Pos (8U)
AnnaBridge 172:65be27845400 4970 #define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 4971 #define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
AnnaBridge 172:65be27845400 4972 #define FDCAN_TTOCN_GCS_Pos (9U)
AnnaBridge 172:65be27845400 4973 #define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 4974 #define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
AnnaBridge 172:65be27845400 4975 #define FDCAN_TTOCN_FGP_Pos (10U)
AnnaBridge 172:65be27845400 4976 #define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 4977 #define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
AnnaBridge 172:65be27845400 4978 #define FDCAN_TTOCN_TMG_Pos (11U)
AnnaBridge 172:65be27845400 4979 #define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 4980 #define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
AnnaBridge 172:65be27845400 4981 #define FDCAN_TTOCN_NIG_Pos (12U)
AnnaBridge 172:65be27845400 4982 #define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 4983 #define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
AnnaBridge 172:65be27845400 4984 #define FDCAN_TTOCN_ESCN_Pos (13U)
AnnaBridge 172:65be27845400 4985 #define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 4986 #define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
AnnaBridge 172:65be27845400 4987 #define FDCAN_TTOCN_LCKC_Pos (15U)
AnnaBridge 172:65be27845400 4988 #define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 4989 #define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
AnnaBridge 172:65be27845400 4990
AnnaBridge 172:65be27845400 4991 /***************** Bit definition for FDCAN_TTGTP register ********************/
AnnaBridge 172:65be27845400 4992 #define FDCAN_TTGTP_TP_Pos (0U)
AnnaBridge 172:65be27845400 4993 #define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 4994 #define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
AnnaBridge 172:65be27845400 4995 #define FDCAN_TTGTP_CTP_Pos (16U)
AnnaBridge 172:65be27845400 4996 #define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 4997 #define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
AnnaBridge 172:65be27845400 4998
AnnaBridge 172:65be27845400 4999 /***************** Bit definition for FDCAN_TTTMK register ********************/
AnnaBridge 172:65be27845400 5000 #define FDCAN_TTTMK_TM_Pos (0U)
AnnaBridge 172:65be27845400 5001 #define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 5002 #define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
AnnaBridge 172:65be27845400 5003 #define FDCAN_TTTMK_TICC_Pos (16U)
AnnaBridge 172:65be27845400 5004 #define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 5005 #define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
AnnaBridge 172:65be27845400 5006 #define FDCAN_TTTMK_LCKM_Pos (31U)
AnnaBridge 172:65be27845400 5007 #define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5008 #define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
AnnaBridge 172:65be27845400 5009
AnnaBridge 172:65be27845400 5010 /***************** Bit definition for FDCAN_TTIR register ********************/
AnnaBridge 172:65be27845400 5011 #define FDCAN_TTIR_SBC_Pos (0U)
AnnaBridge 172:65be27845400 5012 #define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5013 #define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
AnnaBridge 172:65be27845400 5014 #define FDCAN_TTIR_SMC_Pos (1U)
AnnaBridge 172:65be27845400 5015 #define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5016 #define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
AnnaBridge 172:65be27845400 5017 #define FDCAN_TTIR_CSM_Pos (2U)
AnnaBridge 172:65be27845400 5018 #define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5019 #define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
AnnaBridge 172:65be27845400 5020 #define FDCAN_TTIR_SOG_Pos (3U)
AnnaBridge 172:65be27845400 5021 #define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5022 #define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
AnnaBridge 172:65be27845400 5023 #define FDCAN_TTIR_RTMI_Pos (4U)
AnnaBridge 172:65be27845400 5024 #define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5025 #define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
AnnaBridge 172:65be27845400 5026 #define FDCAN_TTIR_TTMI_Pos (5U)
AnnaBridge 172:65be27845400 5027 #define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5028 #define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
AnnaBridge 172:65be27845400 5029 #define FDCAN_TTIR_SWE_Pos (6U)
AnnaBridge 172:65be27845400 5030 #define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5031 #define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
AnnaBridge 172:65be27845400 5032 #define FDCAN_TTIR_GTW_Pos (7U)
AnnaBridge 172:65be27845400 5033 #define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5034 #define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
AnnaBridge 172:65be27845400 5035 #define FDCAN_TTIR_GTD_Pos (8U)
AnnaBridge 172:65be27845400 5036 #define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5037 #define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
AnnaBridge 172:65be27845400 5038 #define FDCAN_TTIR_GTE_Pos (9U)
AnnaBridge 172:65be27845400 5039 #define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5040 #define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
AnnaBridge 172:65be27845400 5041 #define FDCAN_TTIR_TXU_Pos (10U)
AnnaBridge 172:65be27845400 5042 #define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5043 #define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
AnnaBridge 172:65be27845400 5044 #define FDCAN_TTIR_TXO_Pos (11U)
AnnaBridge 172:65be27845400 5045 #define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5046 #define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
AnnaBridge 172:65be27845400 5047 #define FDCAN_TTIR_SE1_Pos (12U)
AnnaBridge 172:65be27845400 5048 #define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5049 #define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
AnnaBridge 172:65be27845400 5050 #define FDCAN_TTIR_SE2_Pos (13U)
AnnaBridge 172:65be27845400 5051 #define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5052 #define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
AnnaBridge 172:65be27845400 5053 #define FDCAN_TTIR_ELC_Pos (14U)
AnnaBridge 172:65be27845400 5054 #define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5055 #define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
AnnaBridge 172:65be27845400 5056 #define FDCAN_TTIR_IWT_Pos (15U)
AnnaBridge 172:65be27845400 5057 #define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5058 #define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
AnnaBridge 172:65be27845400 5059 #define FDCAN_TTIR_WT_Pos (16U)
AnnaBridge 172:65be27845400 5060 #define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5061 #define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
AnnaBridge 172:65be27845400 5062 #define FDCAN_TTIR_AW_Pos (17U)
AnnaBridge 172:65be27845400 5063 #define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5064 #define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
AnnaBridge 172:65be27845400 5065 #define FDCAN_TTIR_CER_Pos (18U)
AnnaBridge 172:65be27845400 5066 #define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5067 #define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
AnnaBridge 172:65be27845400 5068
AnnaBridge 172:65be27845400 5069 /***************** Bit definition for FDCAN_TTIE register ********************/
AnnaBridge 172:65be27845400 5070 #define FDCAN_TTIE_SBCE_Pos (0U)
AnnaBridge 172:65be27845400 5071 #define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5072 #define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
AnnaBridge 172:65be27845400 5073 #define FDCAN_TTIE_SMCE_Pos (1U)
AnnaBridge 172:65be27845400 5074 #define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5075 #define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
AnnaBridge 172:65be27845400 5076 #define FDCAN_TTIE_CSME_Pos (2U)
AnnaBridge 172:65be27845400 5077 #define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5078 #define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
AnnaBridge 172:65be27845400 5079 #define FDCAN_TTIE_SOGE_Pos (3U)
AnnaBridge 172:65be27845400 5080 #define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5081 #define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
AnnaBridge 172:65be27845400 5082 #define FDCAN_TTIE_RTMIE_Pos (4U)
AnnaBridge 172:65be27845400 5083 #define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5084 #define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
AnnaBridge 172:65be27845400 5085 #define FDCAN_TTIE_TTMIE_Pos (5U)
AnnaBridge 172:65be27845400 5086 #define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5087 #define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
AnnaBridge 172:65be27845400 5088 #define FDCAN_TTIE_SWEE_Pos (6U)
AnnaBridge 172:65be27845400 5089 #define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5090 #define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
AnnaBridge 172:65be27845400 5091 #define FDCAN_TTIE_GTWE_Pos (7U)
AnnaBridge 172:65be27845400 5092 #define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5093 #define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
AnnaBridge 172:65be27845400 5094 #define FDCAN_TTIE_GTDE_Pos (8U)
AnnaBridge 172:65be27845400 5095 #define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5096 #define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
AnnaBridge 172:65be27845400 5097 #define FDCAN_TTIE_GTEE_Pos (9U)
AnnaBridge 172:65be27845400 5098 #define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5099 #define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
AnnaBridge 172:65be27845400 5100 #define FDCAN_TTIE_TXUE_Pos (10U)
AnnaBridge 172:65be27845400 5101 #define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5102 #define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
AnnaBridge 172:65be27845400 5103 #define FDCAN_TTIE_TXOE_Pos (11U)
AnnaBridge 172:65be27845400 5104 #define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5105 #define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
AnnaBridge 172:65be27845400 5106 #define FDCAN_TTIE_SE1E_Pos (12U)
AnnaBridge 172:65be27845400 5107 #define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5108 #define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
AnnaBridge 172:65be27845400 5109 #define FDCAN_TTIE_SE2E_Pos (13U)
AnnaBridge 172:65be27845400 5110 #define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5111 #define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
AnnaBridge 172:65be27845400 5112 #define FDCAN_TTIE_ELCE_Pos (14U)
AnnaBridge 172:65be27845400 5113 #define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5114 #define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
AnnaBridge 172:65be27845400 5115 #define FDCAN_TTIE_IWTE_Pos (15U)
AnnaBridge 172:65be27845400 5116 #define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5117 #define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
AnnaBridge 172:65be27845400 5118 #define FDCAN_TTIE_WTE_Pos (16U)
AnnaBridge 172:65be27845400 5119 #define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5120 #define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
AnnaBridge 172:65be27845400 5121 #define FDCAN_TTIE_AWE_Pos (17U)
AnnaBridge 172:65be27845400 5122 #define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5123 #define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
AnnaBridge 172:65be27845400 5124 #define FDCAN_TTIE_CERE_Pos (18U)
AnnaBridge 172:65be27845400 5125 #define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5126 #define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
AnnaBridge 172:65be27845400 5127
AnnaBridge 172:65be27845400 5128 /***************** Bit definition for FDCAN_TTILS register ********************/
AnnaBridge 172:65be27845400 5129 #define FDCAN_TTILS_SBCS_Pos (0U)
AnnaBridge 172:65be27845400 5130 #define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5131 #define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
AnnaBridge 172:65be27845400 5132 #define FDCAN_TTILS_SMCS_Pos (1U)
AnnaBridge 172:65be27845400 5133 #define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5134 #define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
AnnaBridge 172:65be27845400 5135 #define FDCAN_TTILS_CSMS_Pos (2U)
AnnaBridge 172:65be27845400 5136 #define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5137 #define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
AnnaBridge 172:65be27845400 5138 #define FDCAN_TTILS_SOGS_Pos (3U)
AnnaBridge 172:65be27845400 5139 #define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5140 #define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
AnnaBridge 172:65be27845400 5141 #define FDCAN_TTILS_RTMIS_Pos (4U)
AnnaBridge 172:65be27845400 5142 #define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5143 #define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
AnnaBridge 172:65be27845400 5144 #define FDCAN_TTILS_TTMIS_Pos (5U)
AnnaBridge 172:65be27845400 5145 #define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5146 #define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
AnnaBridge 172:65be27845400 5147 #define FDCAN_TTILS_SWES_Pos (6U)
AnnaBridge 172:65be27845400 5148 #define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5149 #define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
AnnaBridge 172:65be27845400 5150 #define FDCAN_TTILS_GTWS_Pos (7U)
AnnaBridge 172:65be27845400 5151 #define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5152 #define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
AnnaBridge 172:65be27845400 5153 #define FDCAN_TTILS_GTDS_Pos (8U)
AnnaBridge 172:65be27845400 5154 #define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5155 #define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
AnnaBridge 172:65be27845400 5156 #define FDCAN_TTILS_GTES_Pos (9U)
AnnaBridge 172:65be27845400 5157 #define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5158 #define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
AnnaBridge 172:65be27845400 5159 #define FDCAN_TTILS_TXUS_Pos (10U)
AnnaBridge 172:65be27845400 5160 #define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5161 #define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
AnnaBridge 172:65be27845400 5162 #define FDCAN_TTILS_TXOS_Pos (11U)
AnnaBridge 172:65be27845400 5163 #define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5164 #define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
AnnaBridge 172:65be27845400 5165 #define FDCAN_TTILS_SE1S_Pos (12U)
AnnaBridge 172:65be27845400 5166 #define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5167 #define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
AnnaBridge 172:65be27845400 5168 #define FDCAN_TTILS_SE2S_Pos (13U)
AnnaBridge 172:65be27845400 5169 #define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5170 #define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
AnnaBridge 172:65be27845400 5171 #define FDCAN_TTILS_ELCS_Pos (14U)
AnnaBridge 172:65be27845400 5172 #define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5173 #define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
AnnaBridge 172:65be27845400 5174 #define FDCAN_TTILS_IWTS_Pos (15U)
AnnaBridge 172:65be27845400 5175 #define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5176 #define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
AnnaBridge 172:65be27845400 5177 #define FDCAN_TTILS_WTS_Pos (16U)
AnnaBridge 172:65be27845400 5178 #define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5179 #define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
AnnaBridge 172:65be27845400 5180 #define FDCAN_TTILS_AWS_Pos (17U)
AnnaBridge 172:65be27845400 5181 #define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5182 #define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
AnnaBridge 172:65be27845400 5183 #define FDCAN_TTILS_CERS_Pos (18U)
AnnaBridge 172:65be27845400 5184 #define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5185 #define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
AnnaBridge 172:65be27845400 5186
AnnaBridge 172:65be27845400 5187 /***************** Bit definition for FDCAN_TTOST register ********************/
AnnaBridge 172:65be27845400 5188 #define FDCAN_TTOST_EL_Pos (0U)
AnnaBridge 172:65be27845400 5189 #define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 5190 #define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
AnnaBridge 172:65be27845400 5191 #define FDCAN_TTOST_MS_Pos (2U)
AnnaBridge 172:65be27845400 5192 #define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 5193 #define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
AnnaBridge 172:65be27845400 5194 #define FDCAN_TTOST_SYS_Pos (4U)
AnnaBridge 172:65be27845400 5195 #define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 5196 #define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
AnnaBridge 172:65be27845400 5197 #define FDCAN_TTOST_QGTP_Pos (6U)
AnnaBridge 172:65be27845400 5198 #define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5199 #define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
AnnaBridge 172:65be27845400 5200 #define FDCAN_TTOST_QCS_Pos (7U)
AnnaBridge 172:65be27845400 5201 #define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5202 #define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
AnnaBridge 172:65be27845400 5203 #define FDCAN_TTOST_RTO_Pos (8U)
AnnaBridge 172:65be27845400 5204 #define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 5205 #define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
AnnaBridge 172:65be27845400 5206 #define FDCAN_TTOST_WGTD_Pos (22U)
AnnaBridge 172:65be27845400 5207 #define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5208 #define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
AnnaBridge 172:65be27845400 5209 #define FDCAN_TTOST_GFI_Pos (23U)
AnnaBridge 172:65be27845400 5210 #define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5211 #define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
AnnaBridge 172:65be27845400 5212 #define FDCAN_TTOST_TMP_Pos (24U)
AnnaBridge 172:65be27845400 5213 #define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 5214 #define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
AnnaBridge 172:65be27845400 5215 #define FDCAN_TTOST_GSI_Pos (27U)
AnnaBridge 172:65be27845400 5216 #define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5217 #define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
AnnaBridge 172:65be27845400 5218 #define FDCAN_TTOST_WFE_Pos (28U)
AnnaBridge 172:65be27845400 5219 #define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5220 #define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
AnnaBridge 172:65be27845400 5221 #define FDCAN_TTOST_AWE_Pos (29U)
AnnaBridge 172:65be27845400 5222 #define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5223 #define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
AnnaBridge 172:65be27845400 5224 #define FDCAN_TTOST_WECS_Pos (30U)
AnnaBridge 172:65be27845400 5225 #define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5226 #define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
AnnaBridge 172:65be27845400 5227 #define FDCAN_TTOST_SPL_Pos (31U)
AnnaBridge 172:65be27845400 5228 #define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5229 #define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
AnnaBridge 172:65be27845400 5230
AnnaBridge 172:65be27845400 5231 /***************** Bit definition for FDCAN_TURNA register ********************/
AnnaBridge 172:65be27845400 5232 #define FDCAN_TURNA_NAV_Pos (0U)
AnnaBridge 172:65be27845400 5233 #define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
AnnaBridge 172:65be27845400 5234 #define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
AnnaBridge 172:65be27845400 5235
AnnaBridge 172:65be27845400 5236 /***************** Bit definition for FDCAN_TTLGT register ********************/
AnnaBridge 172:65be27845400 5237 #define FDCAN_TTLGT_LT_Pos (0U)
AnnaBridge 172:65be27845400 5238 #define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 5239 #define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
AnnaBridge 172:65be27845400 5240 #define FDCAN_TTLGT_GT_Pos (16U)
AnnaBridge 172:65be27845400 5241 #define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 5242 #define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
AnnaBridge 172:65be27845400 5243
AnnaBridge 172:65be27845400 5244 /***************** Bit definition for FDCAN_TTCTC register ********************/
AnnaBridge 172:65be27845400 5245 #define FDCAN_TTCTC_CT_Pos (0U)
AnnaBridge 172:65be27845400 5246 #define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 5247 #define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
AnnaBridge 172:65be27845400 5248 #define FDCAN_TTCTC_CC_Pos (16U)
AnnaBridge 172:65be27845400 5249 #define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
AnnaBridge 172:65be27845400 5250 #define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
AnnaBridge 172:65be27845400 5251
AnnaBridge 172:65be27845400 5252 /***************** Bit definition for FDCAN_TTCPT register ********************/
AnnaBridge 172:65be27845400 5253 #define FDCAN_TTCPT_CCV_Pos (0U)
AnnaBridge 172:65be27845400 5254 #define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 5255 #define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
AnnaBridge 172:65be27845400 5256 #define FDCAN_TTCPT_SWV_Pos (16U)
AnnaBridge 172:65be27845400 5257 #define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 5258 #define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
AnnaBridge 172:65be27845400 5259
AnnaBridge 172:65be27845400 5260 /***************** Bit definition for FDCAN_TTCSM register ********************/
AnnaBridge 172:65be27845400 5261 #define FDCAN_TTCSM_CSM_Pos (0U)
AnnaBridge 172:65be27845400 5262 #define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 5263 #define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
AnnaBridge 172:65be27845400 5264
AnnaBridge 172:65be27845400 5265 /***************** Bit definition for FDCAN_TTTS register *********************/
AnnaBridge 172:65be27845400 5266 #define FDCAN_TTTS_SWTSEL_Pos (0U)
AnnaBridge 172:65be27845400 5267 #define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 5268 #define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
AnnaBridge 172:65be27845400 5269 #define FDCAN_TTTS_EVTSEL_Pos (4U)
AnnaBridge 172:65be27845400 5270 #define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 5271 #define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
AnnaBridge 172:65be27845400 5272
AnnaBridge 172:65be27845400 5273 /********************************************************************************/
AnnaBridge 172:65be27845400 5274 /* */
AnnaBridge 172:65be27845400 5275 /* FDCANCCU (Clock Calibration unit) */
AnnaBridge 172:65be27845400 5276 /* */
AnnaBridge 172:65be27845400 5277 /********************************************************************************/
AnnaBridge 172:65be27845400 5278
AnnaBridge 172:65be27845400 5279 /***************** Bit definition for FDCANCCU_CREL register ******************/
AnnaBridge 172:65be27845400 5280 #define FDCANCCU_CREL_DAY_Pos (0U)
AnnaBridge 172:65be27845400 5281 #define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5282 #define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
AnnaBridge 172:65be27845400 5283 #define FDCANCCU_CREL_MON_Pos (8U)
AnnaBridge 172:65be27845400 5284 #define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 5285 #define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
AnnaBridge 172:65be27845400 5286 #define FDCANCCU_CREL_YEAR_Pos (16U)
AnnaBridge 172:65be27845400 5287 #define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 5288 #define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
AnnaBridge 172:65be27845400 5289 #define FDCANCCU_CREL_SUBSTEP_Pos (20U)
AnnaBridge 172:65be27845400 5290 #define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 5291 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
AnnaBridge 172:65be27845400 5292 #define FDCANCCU_CREL_STEP_Pos (24U)
AnnaBridge 172:65be27845400 5293 #define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 5294 #define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
AnnaBridge 172:65be27845400 5295 #define FDCANCCU_CREL_REL_Pos (28U)
AnnaBridge 172:65be27845400 5296 #define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 5297 #define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
AnnaBridge 172:65be27845400 5298
AnnaBridge 172:65be27845400 5299 /***************** Bit definition for FDCANCCU_CCFG register ******************/
AnnaBridge 172:65be27845400 5300 #define FDCANCCU_CCFG_TQBT_Pos (0U)
AnnaBridge 172:65be27845400 5301 #define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 5302 #define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
AnnaBridge 172:65be27845400 5303 #define FDCANCCU_CCFG_BCC_Pos (6U)
AnnaBridge 172:65be27845400 5304 #define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5305 #define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
AnnaBridge 172:65be27845400 5306 #define FDCANCCU_CCFG_CFL_Pos (7U)
AnnaBridge 172:65be27845400 5307 #define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5308 #define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
AnnaBridge 172:65be27845400 5309 #define FDCANCCU_CCFG_OCPM_Pos (8U)
AnnaBridge 172:65be27845400 5310 #define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 5311 #define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
AnnaBridge 172:65be27845400 5312 #define FDCANCCU_CCFG_CDIV_Pos (16U)
AnnaBridge 172:65be27845400 5313 #define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 5314 #define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
AnnaBridge 172:65be27845400 5315 #define FDCANCCU_CCFG_SWR_Pos (31U)
AnnaBridge 172:65be27845400 5316 #define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5317 #define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
AnnaBridge 172:65be27845400 5318
AnnaBridge 172:65be27845400 5319 /***************** Bit definition for FDCANCCU_CSTAT register *****************/
AnnaBridge 172:65be27845400 5320 #define FDCANCCU_CSTAT_OCPC_Pos (0U)
AnnaBridge 172:65be27845400 5321 #define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
AnnaBridge 172:65be27845400 5322 #define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
AnnaBridge 172:65be27845400 5323 #define FDCANCCU_CSTAT_TQC_Pos (18U)
AnnaBridge 172:65be27845400 5324 #define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
AnnaBridge 172:65be27845400 5325 #define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
AnnaBridge 172:65be27845400 5326 #define FDCANCCU_CSTAT_CALS_Pos (30U)
AnnaBridge 172:65be27845400 5327 #define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 5328 #define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
AnnaBridge 172:65be27845400 5329
AnnaBridge 172:65be27845400 5330 /****************** Bit definition for FDCANCCU_CWD register ******************/
AnnaBridge 172:65be27845400 5331 #define FDCANCCU_CWD_WDC_Pos (0U)
AnnaBridge 172:65be27845400 5332 #define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 5333 #define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
AnnaBridge 172:65be27845400 5334 #define FDCANCCU_CWD_WDV_Pos (16U)
AnnaBridge 172:65be27845400 5335 #define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 5336 #define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
AnnaBridge 172:65be27845400 5337
AnnaBridge 172:65be27845400 5338 /****************** Bit definition for FDCANCCU_IR register *******************/
AnnaBridge 172:65be27845400 5339 #define FDCANCCU_IR_CWE_Pos (0U)
AnnaBridge 172:65be27845400 5340 #define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5341 #define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
AnnaBridge 172:65be27845400 5342 #define FDCANCCU_IR_CSC_Pos (1U)
AnnaBridge 172:65be27845400 5343 #define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5344 #define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
AnnaBridge 172:65be27845400 5345
AnnaBridge 172:65be27845400 5346 /****************** Bit definition for FDCANCCU_IE register *******************/
AnnaBridge 172:65be27845400 5347 #define FDCANCCU_IE_CWEE_Pos (0U)
AnnaBridge 172:65be27845400 5348 #define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5349 #define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
AnnaBridge 172:65be27845400 5350 #define FDCANCCU_IE_CSCE_Pos (1U)
AnnaBridge 172:65be27845400 5351 #define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5352 #define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
AnnaBridge 172:65be27845400 5353
AnnaBridge 172:65be27845400 5354 /******************************************************************************/
AnnaBridge 172:65be27845400 5355 /* */
AnnaBridge 172:65be27845400 5356 /* HDMI-CEC (CEC) */
AnnaBridge 172:65be27845400 5357 /* */
AnnaBridge 172:65be27845400 5358 /******************************************************************************/
AnnaBridge 172:65be27845400 5359
AnnaBridge 172:65be27845400 5360 /******************* Bit definition for CEC_CR register *********************/
AnnaBridge 172:65be27845400 5361 #define CEC_CR_CECEN_Pos (0U)
AnnaBridge 172:65be27845400 5362 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5363 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
AnnaBridge 172:65be27845400 5364 #define CEC_CR_TXSOM_Pos (1U)
AnnaBridge 172:65be27845400 5365 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5366 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
AnnaBridge 172:65be27845400 5367 #define CEC_CR_TXEOM_Pos (2U)
AnnaBridge 172:65be27845400 5368 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5369 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
AnnaBridge 172:65be27845400 5370
AnnaBridge 172:65be27845400 5371 /******************* Bit definition for CEC_CFGR register *******************/
AnnaBridge 172:65be27845400 5372 #define CEC_CFGR_SFT_Pos (0U)
AnnaBridge 172:65be27845400 5373 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 5374 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
AnnaBridge 172:65be27845400 5375 #define CEC_CFGR_RXTOL_Pos (3U)
AnnaBridge 172:65be27845400 5376 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5377 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
AnnaBridge 172:65be27845400 5378 #define CEC_CFGR_BRESTP_Pos (4U)
AnnaBridge 172:65be27845400 5379 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5380 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
AnnaBridge 172:65be27845400 5381 #define CEC_CFGR_BREGEN_Pos (5U)
AnnaBridge 172:65be27845400 5382 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5383 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
AnnaBridge 172:65be27845400 5384 #define CEC_CFGR_LBPEGEN_Pos (6U)
AnnaBridge 172:65be27845400 5385 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5386 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
AnnaBridge 172:65be27845400 5387 #define CEC_CFGR_SFTOPT_Pos (8U)
AnnaBridge 172:65be27845400 5388 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5389 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
AnnaBridge 172:65be27845400 5390 #define CEC_CFGR_BRDNOGEN_Pos (7U)
AnnaBridge 172:65be27845400 5391 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5392 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
AnnaBridge 172:65be27845400 5393 #define CEC_CFGR_OAR_Pos (16U)
AnnaBridge 172:65be27845400 5394 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
AnnaBridge 172:65be27845400 5395 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
AnnaBridge 172:65be27845400 5396 #define CEC_CFGR_LSTN_Pos (31U)
AnnaBridge 172:65be27845400 5397 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5398 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
AnnaBridge 172:65be27845400 5399
AnnaBridge 172:65be27845400 5400 /******************* Bit definition for CEC_TXDR register *******************/
AnnaBridge 172:65be27845400 5401 #define CEC_TXDR_TXD_Pos (0U)
AnnaBridge 172:65be27845400 5402 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5403 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
AnnaBridge 172:65be27845400 5404
AnnaBridge 172:65be27845400 5405 /******************* Bit definition for CEC_RXDR register *******************/
AnnaBridge 172:65be27845400 5406 #define CEC_RXDR_RXD_Pos (0U)
AnnaBridge 172:65be27845400 5407 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5408 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
AnnaBridge 172:65be27845400 5409
AnnaBridge 172:65be27845400 5410 /******************* Bit definition for CEC_ISR register ********************/
AnnaBridge 172:65be27845400 5411 #define CEC_ISR_RXBR_Pos (0U)
AnnaBridge 172:65be27845400 5412 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5413 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
AnnaBridge 172:65be27845400 5414 #define CEC_ISR_RXEND_Pos (1U)
AnnaBridge 172:65be27845400 5415 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5416 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
AnnaBridge 172:65be27845400 5417 #define CEC_ISR_RXOVR_Pos (2U)
AnnaBridge 172:65be27845400 5418 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5419 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
AnnaBridge 172:65be27845400 5420 #define CEC_ISR_BRE_Pos (3U)
AnnaBridge 172:65be27845400 5421 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5422 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
AnnaBridge 172:65be27845400 5423 #define CEC_ISR_SBPE_Pos (4U)
AnnaBridge 172:65be27845400 5424 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5425 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
AnnaBridge 172:65be27845400 5426 #define CEC_ISR_LBPE_Pos (5U)
AnnaBridge 172:65be27845400 5427 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5428 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
AnnaBridge 172:65be27845400 5429 #define CEC_ISR_RXACKE_Pos (6U)
AnnaBridge 172:65be27845400 5430 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5431 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
AnnaBridge 172:65be27845400 5432 #define CEC_ISR_ARBLST_Pos (7U)
AnnaBridge 172:65be27845400 5433 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5434 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
AnnaBridge 172:65be27845400 5435 #define CEC_ISR_TXBR_Pos (8U)
AnnaBridge 172:65be27845400 5436 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5437 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
AnnaBridge 172:65be27845400 5438 #define CEC_ISR_TXEND_Pos (9U)
AnnaBridge 172:65be27845400 5439 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5440 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
AnnaBridge 172:65be27845400 5441 #define CEC_ISR_TXUDR_Pos (10U)
AnnaBridge 172:65be27845400 5442 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5443 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
AnnaBridge 172:65be27845400 5444 #define CEC_ISR_TXERR_Pos (11U)
AnnaBridge 172:65be27845400 5445 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5446 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
AnnaBridge 172:65be27845400 5447 #define CEC_ISR_TXACKE_Pos (12U)
AnnaBridge 172:65be27845400 5448 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5449 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
AnnaBridge 172:65be27845400 5450
AnnaBridge 172:65be27845400 5451 /******************* Bit definition for CEC_IER register ********************/
AnnaBridge 172:65be27845400 5452 #define CEC_IER_RXBRIE_Pos (0U)
AnnaBridge 172:65be27845400 5453 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5454 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
AnnaBridge 172:65be27845400 5455 #define CEC_IER_RXENDIE_Pos (1U)
AnnaBridge 172:65be27845400 5456 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5457 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
AnnaBridge 172:65be27845400 5458 #define CEC_IER_RXOVRIE_Pos (2U)
AnnaBridge 172:65be27845400 5459 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5460 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
AnnaBridge 172:65be27845400 5461 #define CEC_IER_BREIE_Pos (3U)
AnnaBridge 172:65be27845400 5462 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5463 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
AnnaBridge 172:65be27845400 5464 #define CEC_IER_SBPEIE_Pos (4U)
AnnaBridge 172:65be27845400 5465 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5466 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
AnnaBridge 172:65be27845400 5467 #define CEC_IER_LBPEIE_Pos (5U)
AnnaBridge 172:65be27845400 5468 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5469 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
AnnaBridge 172:65be27845400 5470 #define CEC_IER_RXACKEIE_Pos (6U)
AnnaBridge 172:65be27845400 5471 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5472 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
AnnaBridge 172:65be27845400 5473 #define CEC_IER_ARBLSTIE_Pos (7U)
AnnaBridge 172:65be27845400 5474 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5475 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
AnnaBridge 172:65be27845400 5476 #define CEC_IER_TXBRIE_Pos (8U)
AnnaBridge 172:65be27845400 5477 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5478 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
AnnaBridge 172:65be27845400 5479 #define CEC_IER_TXENDIE_Pos (9U)
AnnaBridge 172:65be27845400 5480 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5481 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
AnnaBridge 172:65be27845400 5482 #define CEC_IER_TXUDRIE_Pos (10U)
AnnaBridge 172:65be27845400 5483 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5484 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
AnnaBridge 172:65be27845400 5485 #define CEC_IER_TXERRIE_Pos (11U)
AnnaBridge 172:65be27845400 5486 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5487 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
AnnaBridge 172:65be27845400 5488 #define CEC_IER_TXACKEIE_Pos (12U)
AnnaBridge 172:65be27845400 5489 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5490 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
AnnaBridge 172:65be27845400 5491
AnnaBridge 172:65be27845400 5492 /******************************************************************************/
AnnaBridge 172:65be27845400 5493 /* */
AnnaBridge 172:65be27845400 5494 /* CRC calculation unit */
AnnaBridge 172:65be27845400 5495 /* */
AnnaBridge 172:65be27845400 5496 /******************************************************************************/
AnnaBridge 172:65be27845400 5497 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 172:65be27845400 5498 #define CRC_DR_DR_Pos (0U)
AnnaBridge 172:65be27845400 5499 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 5500 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 172:65be27845400 5501
AnnaBridge 172:65be27845400 5502 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 172:65be27845400 5503 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 172:65be27845400 5504 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 5505 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
AnnaBridge 172:65be27845400 5506
AnnaBridge 172:65be27845400 5507 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 172:65be27845400 5508 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 172:65be27845400 5509 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5510 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
AnnaBridge 172:65be27845400 5511 #define CRC_CR_POLYSIZE_Pos (3U)
AnnaBridge 172:65be27845400 5512 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 5513 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
AnnaBridge 172:65be27845400 5514 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5515 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5516 #define CRC_CR_REV_IN_Pos (5U)
AnnaBridge 172:65be27845400 5517 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 5518 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
AnnaBridge 172:65be27845400 5519 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5520 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5521 #define CRC_CR_REV_OUT_Pos (7U)
AnnaBridge 172:65be27845400 5522 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5523 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
AnnaBridge 172:65be27845400 5524
AnnaBridge 172:65be27845400 5525 /******************* Bit definition for CRC_INIT register *******************/
AnnaBridge 172:65be27845400 5526 #define CRC_INIT_INIT_Pos (0U)
AnnaBridge 172:65be27845400 5527 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 5528 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
AnnaBridge 172:65be27845400 5529
AnnaBridge 172:65be27845400 5530 /******************* Bit definition for CRC_POL register ********************/
AnnaBridge 172:65be27845400 5531 #define CRC_POL_POL_Pos (0U)
AnnaBridge 172:65be27845400 5532 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 5533 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
AnnaBridge 172:65be27845400 5534
AnnaBridge 172:65be27845400 5535 /******************************************************************************/
AnnaBridge 172:65be27845400 5536 /* */
AnnaBridge 172:65be27845400 5537 /* CRS Clock Recovery System */
AnnaBridge 172:65be27845400 5538 /******************************************************************************/
AnnaBridge 172:65be27845400 5539
AnnaBridge 172:65be27845400 5540 /******************* Bit definition for CRS_CR register *********************/
AnnaBridge 172:65be27845400 5541 #define CRS_CR_SYNCOKIE_Pos (0U)
AnnaBridge 172:65be27845400 5542 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5543 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
AnnaBridge 172:65be27845400 5544 #define CRS_CR_SYNCWARNIE_Pos (1U)
AnnaBridge 172:65be27845400 5545 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5546 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
AnnaBridge 172:65be27845400 5547 #define CRS_CR_ERRIE_Pos (2U)
AnnaBridge 172:65be27845400 5548 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5549 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
AnnaBridge 172:65be27845400 5550 #define CRS_CR_ESYNCIE_Pos (3U)
AnnaBridge 172:65be27845400 5551 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5552 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
AnnaBridge 172:65be27845400 5553 #define CRS_CR_CEN_Pos (5U)
AnnaBridge 172:65be27845400 5554 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5555 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
AnnaBridge 172:65be27845400 5556 #define CRS_CR_AUTOTRIMEN_Pos (6U)
AnnaBridge 172:65be27845400 5557 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5558 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
AnnaBridge 172:65be27845400 5559 #define CRS_CR_SWSYNC_Pos (7U)
AnnaBridge 172:65be27845400 5560 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5561 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
AnnaBridge 172:65be27845400 5562 #define CRS_CR_TRIM_Pos (8U)
AnnaBridge 172:65be27845400 5563 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
AnnaBridge 172:65be27845400 5564 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
AnnaBridge 172:65be27845400 5565
AnnaBridge 172:65be27845400 5566 /******************* Bit definition for CRS_CFGR register *********************/
AnnaBridge 172:65be27845400 5567 #define CRS_CFGR_RELOAD_Pos (0U)
AnnaBridge 172:65be27845400 5568 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 5569 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
AnnaBridge 172:65be27845400 5570 #define CRS_CFGR_FELIM_Pos (16U)
AnnaBridge 172:65be27845400 5571 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 5572 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
AnnaBridge 172:65be27845400 5573
AnnaBridge 172:65be27845400 5574 #define CRS_CFGR_SYNCDIV_Pos (24U)
AnnaBridge 172:65be27845400 5575 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 5576 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
AnnaBridge 172:65be27845400 5577 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5578 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5579 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5580
AnnaBridge 172:65be27845400 5581 #define CRS_CFGR_SYNCSRC_Pos (28U)
AnnaBridge 172:65be27845400 5582 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 5583 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
AnnaBridge 172:65be27845400 5584 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5585 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5586
AnnaBridge 172:65be27845400 5587 #define CRS_CFGR_SYNCPOL_Pos (31U)
AnnaBridge 172:65be27845400 5588 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5589 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
AnnaBridge 172:65be27845400 5590
AnnaBridge 172:65be27845400 5591 /******************* Bit definition for CRS_ISR register *********************/
AnnaBridge 172:65be27845400 5592 #define CRS_ISR_SYNCOKF_Pos (0U)
AnnaBridge 172:65be27845400 5593 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5594 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
AnnaBridge 172:65be27845400 5595 #define CRS_ISR_SYNCWARNF_Pos (1U)
AnnaBridge 172:65be27845400 5596 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5597 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
AnnaBridge 172:65be27845400 5598 #define CRS_ISR_ERRF_Pos (2U)
AnnaBridge 172:65be27845400 5599 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5600 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
AnnaBridge 172:65be27845400 5601 #define CRS_ISR_ESYNCF_Pos (3U)
AnnaBridge 172:65be27845400 5602 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5603 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
AnnaBridge 172:65be27845400 5604 #define CRS_ISR_SYNCERR_Pos (8U)
AnnaBridge 172:65be27845400 5605 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5606 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
AnnaBridge 172:65be27845400 5607 #define CRS_ISR_SYNCMISS_Pos (9U)
AnnaBridge 172:65be27845400 5608 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5609 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
AnnaBridge 172:65be27845400 5610 #define CRS_ISR_TRIMOVF_Pos (10U)
AnnaBridge 172:65be27845400 5611 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5612 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
AnnaBridge 172:65be27845400 5613 #define CRS_ISR_FEDIR_Pos (15U)
AnnaBridge 172:65be27845400 5614 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 5615 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
AnnaBridge 172:65be27845400 5616 #define CRS_ISR_FECAP_Pos (16U)
AnnaBridge 172:65be27845400 5617 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 5618 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
AnnaBridge 172:65be27845400 5619
AnnaBridge 172:65be27845400 5620 /******************* Bit definition for CRS_ICR register *********************/
AnnaBridge 172:65be27845400 5621 #define CRS_ICR_SYNCOKC_Pos (0U)
AnnaBridge 172:65be27845400 5622 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5623 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
AnnaBridge 172:65be27845400 5624 #define CRS_ICR_SYNCWARNC_Pos (1U)
AnnaBridge 172:65be27845400 5625 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5626 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
AnnaBridge 172:65be27845400 5627 #define CRS_ICR_ERRC_Pos (2U)
AnnaBridge 172:65be27845400 5628 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5629 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
AnnaBridge 172:65be27845400 5630 #define CRS_ICR_ESYNCC_Pos (3U)
AnnaBridge 172:65be27845400 5631 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5632 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
AnnaBridge 172:65be27845400 5633
AnnaBridge 172:65be27845400 5634 /******************************************************************************/
AnnaBridge 172:65be27845400 5635 /* */
AnnaBridge 172:65be27845400 5636 /* Digital to Analog Converter */
AnnaBridge 172:65be27845400 5637 /* */
AnnaBridge 172:65be27845400 5638 /******************************************************************************/
AnnaBridge 172:65be27845400 5639 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 172:65be27845400 5640 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 172:65be27845400 5641 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5642 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 172:65be27845400 5643 #define DAC_CR_TEN1_Pos (1U)
AnnaBridge 172:65be27845400 5644 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5645 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 172:65be27845400 5646
AnnaBridge 172:65be27845400 5647 #define DAC_CR_TSEL1_Pos (2U)
AnnaBridge 172:65be27845400 5648 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
AnnaBridge 172:65be27845400 5649 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 172:65be27845400 5650 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5651 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5652 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5653 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5654
AnnaBridge 172:65be27845400 5655
AnnaBridge 172:65be27845400 5656 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 172:65be27845400 5657 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 5658 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 172:65be27845400 5659 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5660 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5661
AnnaBridge 172:65be27845400 5662 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 172:65be27845400 5663 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 5664 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 172:65be27845400 5665 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 5666 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 5667 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 5668 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 5669
AnnaBridge 172:65be27845400 5670 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 172:65be27845400 5671 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5672 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 172:65be27845400 5673 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 172:65be27845400 5674 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5675 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
AnnaBridge 172:65be27845400 5676 #define DAC_CR_CEN1_Pos (14U)
AnnaBridge 172:65be27845400 5677 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5678 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
AnnaBridge 172:65be27845400 5679
AnnaBridge 172:65be27845400 5680 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 172:65be27845400 5681 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5682 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 172:65be27845400 5683 #define DAC_CR_TEN2_Pos (17U)
AnnaBridge 172:65be27845400 5684 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5685 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 172:65be27845400 5686
AnnaBridge 172:65be27845400 5687 #define DAC_CR_TSEL2_Pos (18U)
AnnaBridge 172:65be27845400 5688 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
AnnaBridge 172:65be27845400 5689 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 172:65be27845400 5690 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5691 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5692 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5693 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 5694
AnnaBridge 172:65be27845400 5695
AnnaBridge 172:65be27845400 5696 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 172:65be27845400 5697 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 5698 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 172:65be27845400 5699 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 5700 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 5701
AnnaBridge 172:65be27845400 5702 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 172:65be27845400 5703 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 5704 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 172:65be27845400 5705 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 5706 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 5707 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 5708 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 5709
AnnaBridge 172:65be27845400 5710 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 172:65be27845400 5711 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 5712 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 172:65be27845400 5713 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 172:65be27845400 5714 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5715 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
AnnaBridge 172:65be27845400 5716 #define DAC_CR_CEN2_Pos (30U)
AnnaBridge 172:65be27845400 5717 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5718 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
AnnaBridge 172:65be27845400 5719
AnnaBridge 172:65be27845400 5720 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 172:65be27845400 5721 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 172:65be27845400 5722 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5723 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 172:65be27845400 5724 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 172:65be27845400 5725 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5726 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 172:65be27845400 5727
AnnaBridge 172:65be27845400 5728 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 172:65be27845400 5729 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5730 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5731 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5732
AnnaBridge 172:65be27845400 5733 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 172:65be27845400 5734 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 172:65be27845400 5735 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 5736 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5737
AnnaBridge 172:65be27845400 5738 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 172:65be27845400 5739 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5740 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5741 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5742
AnnaBridge 172:65be27845400 5743 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 172:65be27845400 5744 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 172:65be27845400 5745 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5746 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5747
AnnaBridge 172:65be27845400 5748 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 172:65be27845400 5749 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 172:65be27845400 5750 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 5751 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5752
AnnaBridge 172:65be27845400 5753 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 172:65be27845400 5754 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 172:65be27845400 5755 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5756 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5757
AnnaBridge 172:65be27845400 5758 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 172:65be27845400 5759 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5760 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5761 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5762 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 172:65be27845400 5763 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 5764 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 172:65be27845400 5765
AnnaBridge 172:65be27845400 5766 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 172:65be27845400 5767 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 172:65be27845400 5768 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 5769 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5770 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 172:65be27845400 5771 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 172:65be27845400 5772 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 172:65be27845400 5773
AnnaBridge 172:65be27845400 5774 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 172:65be27845400 5775 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 172:65be27845400 5776 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5777 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5778 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 172:65be27845400 5779 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 5780 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 172:65be27845400 5781
AnnaBridge 172:65be27845400 5782 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 172:65be27845400 5783 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 172:65be27845400 5784 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5785 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 172:65be27845400 5786
AnnaBridge 172:65be27845400 5787 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 172:65be27845400 5788 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 172:65be27845400 5789 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 5790 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 172:65be27845400 5791
AnnaBridge 172:65be27845400 5792 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 172:65be27845400 5793 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 172:65be27845400 5794 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 5795 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 172:65be27845400 5796 #define DAC_SR_CAL_FLAG1_Pos (14U)
AnnaBridge 172:65be27845400 5797 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5798 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
AnnaBridge 172:65be27845400 5799 #define DAC_SR_BWST1_Pos (15U)
AnnaBridge 172:65be27845400 5800 #define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
AnnaBridge 172:65be27845400 5801 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
AnnaBridge 172:65be27845400 5802
AnnaBridge 172:65be27845400 5803 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 172:65be27845400 5804 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 5805 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 172:65be27845400 5806 #define DAC_SR_CAL_FLAG2_Pos (30U)
AnnaBridge 172:65be27845400 5807 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 5808 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
AnnaBridge 172:65be27845400 5809 #define DAC_SR_BWST2_Pos (31U)
AnnaBridge 172:65be27845400 5810 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 5811 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
AnnaBridge 172:65be27845400 5812
AnnaBridge 172:65be27845400 5813 /******************* Bit definition for DAC_CCR register ********************/
AnnaBridge 172:65be27845400 5814 #define DAC_CCR_OTRIM1_Pos (0U)
AnnaBridge 172:65be27845400 5815 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 5816 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
AnnaBridge 172:65be27845400 5817 #define DAC_CCR_OTRIM2_Pos (16U)
AnnaBridge 172:65be27845400 5818 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 5819 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
AnnaBridge 172:65be27845400 5820
AnnaBridge 172:65be27845400 5821 /******************* Bit definition for DAC_MCR register *******************/
AnnaBridge 172:65be27845400 5822 #define DAC_MCR_MODE1_Pos (0U)
AnnaBridge 172:65be27845400 5823 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 5824 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
AnnaBridge 172:65be27845400 5825 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5826 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5827 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5828
AnnaBridge 172:65be27845400 5829 #define DAC_MCR_MODE2_Pos (16U)
AnnaBridge 172:65be27845400 5830 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 5831 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
AnnaBridge 172:65be27845400 5832 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5833 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5834 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5835
AnnaBridge 172:65be27845400 5836 /****************** Bit definition for DAC_SHSR1 register ******************/
AnnaBridge 172:65be27845400 5837 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
AnnaBridge 172:65be27845400 5838 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 5839 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
AnnaBridge 172:65be27845400 5840
AnnaBridge 172:65be27845400 5841 /****************** Bit definition for DAC_SHSR2 register ******************/
AnnaBridge 172:65be27845400 5842 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
AnnaBridge 172:65be27845400 5843 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 5844 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
AnnaBridge 172:65be27845400 5845
AnnaBridge 172:65be27845400 5846 /****************** Bit definition for DAC_SHHR register ******************/
AnnaBridge 172:65be27845400 5847 #define DAC_SHHR_THOLD1_Pos (0U)
AnnaBridge 172:65be27845400 5848 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 5849 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
AnnaBridge 172:65be27845400 5850 #define DAC_SHHR_THOLD2_Pos (16U)
AnnaBridge 172:65be27845400 5851 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
AnnaBridge 172:65be27845400 5852 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
AnnaBridge 172:65be27845400 5853
AnnaBridge 172:65be27845400 5854 /****************** Bit definition for DAC_SHRR register ******************/
AnnaBridge 172:65be27845400 5855 #define DAC_SHRR_TREFRESH1_Pos (0U)
AnnaBridge 172:65be27845400 5856 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 5857 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
AnnaBridge 172:65be27845400 5858 #define DAC_SHRR_TREFRESH2_Pos (16U)
AnnaBridge 172:65be27845400 5859 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 5860 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
AnnaBridge 172:65be27845400 5861
AnnaBridge 172:65be27845400 5862 /******************************************************************************/
AnnaBridge 172:65be27845400 5863 /* */
AnnaBridge 172:65be27845400 5864 /* DCMI */
AnnaBridge 172:65be27845400 5865 /* */
AnnaBridge 172:65be27845400 5866 /******************************************************************************/
AnnaBridge 172:65be27845400 5867 /******************** Bits definition for DCMI_CR register ******************/
AnnaBridge 172:65be27845400 5868 #define DCMI_CR_CAPTURE_Pos (0U)
AnnaBridge 172:65be27845400 5869 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5870 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
AnnaBridge 172:65be27845400 5871 #define DCMI_CR_CM_Pos (1U)
AnnaBridge 172:65be27845400 5872 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5873 #define DCMI_CR_CM DCMI_CR_CM_Msk
AnnaBridge 172:65be27845400 5874 #define DCMI_CR_CROP_Pos (2U)
AnnaBridge 172:65be27845400 5875 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5876 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
AnnaBridge 172:65be27845400 5877 #define DCMI_CR_JPEG_Pos (3U)
AnnaBridge 172:65be27845400 5878 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5879 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
AnnaBridge 172:65be27845400 5880 #define DCMI_CR_ESS_Pos (4U)
AnnaBridge 172:65be27845400 5881 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5882 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
AnnaBridge 172:65be27845400 5883 #define DCMI_CR_PCKPOL_Pos (5U)
AnnaBridge 172:65be27845400 5884 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 5885 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
AnnaBridge 172:65be27845400 5886 #define DCMI_CR_HSPOL_Pos (6U)
AnnaBridge 172:65be27845400 5887 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 5888 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
AnnaBridge 172:65be27845400 5889 #define DCMI_CR_VSPOL_Pos (7U)
AnnaBridge 172:65be27845400 5890 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 5891 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
AnnaBridge 172:65be27845400 5892 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
AnnaBridge 172:65be27845400 5893 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
AnnaBridge 172:65be27845400 5894 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
AnnaBridge 172:65be27845400 5895 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
AnnaBridge 172:65be27845400 5896 #define DCMI_CR_CRE_Pos (12U)
AnnaBridge 172:65be27845400 5897 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 5898 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
AnnaBridge 172:65be27845400 5899 #define DCMI_CR_ENABLE_Pos (14U)
AnnaBridge 172:65be27845400 5900 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 5901 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
AnnaBridge 172:65be27845400 5902 #define DCMI_CR_BSM_Pos (16U)
AnnaBridge 172:65be27845400 5903 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 5904 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
AnnaBridge 172:65be27845400 5905 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 5906 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 5907 #define DCMI_CR_OEBS_Pos (18U)
AnnaBridge 172:65be27845400 5908 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 5909 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
AnnaBridge 172:65be27845400 5910 #define DCMI_CR_LSM_Pos (19U)
AnnaBridge 172:65be27845400 5911 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 5912 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
AnnaBridge 172:65be27845400 5913 #define DCMI_CR_OELS_Pos (20U)
AnnaBridge 172:65be27845400 5914 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 5915 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
AnnaBridge 172:65be27845400 5916
AnnaBridge 172:65be27845400 5917 /******************** Bits definition for DCMI_SR register ******************/
AnnaBridge 172:65be27845400 5918 #define DCMI_SR_HSYNC_Pos (0U)
AnnaBridge 172:65be27845400 5919 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5920 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
AnnaBridge 172:65be27845400 5921 #define DCMI_SR_VSYNC_Pos (1U)
AnnaBridge 172:65be27845400 5922 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5923 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
AnnaBridge 172:65be27845400 5924 #define DCMI_SR_FNE_Pos (2U)
AnnaBridge 172:65be27845400 5925 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5926 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
AnnaBridge 172:65be27845400 5927
AnnaBridge 172:65be27845400 5928 /******************** Bits definition for DCMI_RIS register ****************/
AnnaBridge 172:65be27845400 5929 #define DCMI_RIS_FRAME_RIS_Pos (0U)
AnnaBridge 172:65be27845400 5930 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5931 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
AnnaBridge 172:65be27845400 5932 #define DCMI_RIS_OVR_RIS_Pos (1U)
AnnaBridge 172:65be27845400 5933 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5934 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
AnnaBridge 172:65be27845400 5935 #define DCMI_RIS_ERR_RIS_Pos (2U)
AnnaBridge 172:65be27845400 5936 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5937 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
AnnaBridge 172:65be27845400 5938 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
AnnaBridge 172:65be27845400 5939 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5940 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
AnnaBridge 172:65be27845400 5941 #define DCMI_RIS_LINE_RIS_Pos (4U)
AnnaBridge 172:65be27845400 5942 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5943 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
AnnaBridge 172:65be27845400 5944
AnnaBridge 172:65be27845400 5945 /******************** Bits definition for DCMI_IER register *****************/
AnnaBridge 172:65be27845400 5946 #define DCMI_IER_FRAME_IE_Pos (0U)
AnnaBridge 172:65be27845400 5947 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5948 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
AnnaBridge 172:65be27845400 5949 #define DCMI_IER_OVR_IE_Pos (1U)
AnnaBridge 172:65be27845400 5950 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5951 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
AnnaBridge 172:65be27845400 5952 #define DCMI_IER_ERR_IE_Pos (2U)
AnnaBridge 172:65be27845400 5953 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5954 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
AnnaBridge 172:65be27845400 5955 #define DCMI_IER_VSYNC_IE_Pos (3U)
AnnaBridge 172:65be27845400 5956 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5957 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
AnnaBridge 172:65be27845400 5958 #define DCMI_IER_LINE_IE_Pos (4U)
AnnaBridge 172:65be27845400 5959 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5960 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
AnnaBridge 172:65be27845400 5961
AnnaBridge 172:65be27845400 5962
AnnaBridge 172:65be27845400 5963 /******************** Bits definition for DCMI_MIS register *****************/
AnnaBridge 172:65be27845400 5964 #define DCMI_MIS_FRAME_MIS_Pos (0U)
AnnaBridge 172:65be27845400 5965 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5966 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
AnnaBridge 172:65be27845400 5967 #define DCMI_MIS_OVR_MIS_Pos (1U)
AnnaBridge 172:65be27845400 5968 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5969 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
AnnaBridge 172:65be27845400 5970 #define DCMI_MIS_ERR_MIS_Pos (2U)
AnnaBridge 172:65be27845400 5971 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5972 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
AnnaBridge 172:65be27845400 5973 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
AnnaBridge 172:65be27845400 5974 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5975 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
AnnaBridge 172:65be27845400 5976 #define DCMI_MIS_LINE_MIS_Pos (4U)
AnnaBridge 172:65be27845400 5977 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5978 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
AnnaBridge 172:65be27845400 5979
AnnaBridge 172:65be27845400 5980
AnnaBridge 172:65be27845400 5981 /******************** Bits definition for DCMI_ICR register *****************/
AnnaBridge 172:65be27845400 5982 #define DCMI_ICR_FRAME_ISC_Pos (0U)
AnnaBridge 172:65be27845400 5983 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 5984 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
AnnaBridge 172:65be27845400 5985 #define DCMI_ICR_OVR_ISC_Pos (1U)
AnnaBridge 172:65be27845400 5986 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 5987 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
AnnaBridge 172:65be27845400 5988 #define DCMI_ICR_ERR_ISC_Pos (2U)
AnnaBridge 172:65be27845400 5989 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 5990 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
AnnaBridge 172:65be27845400 5991 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
AnnaBridge 172:65be27845400 5992 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 5993 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
AnnaBridge 172:65be27845400 5994 #define DCMI_ICR_LINE_ISC_Pos (4U)
AnnaBridge 172:65be27845400 5995 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 5996 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
AnnaBridge 172:65be27845400 5997
AnnaBridge 172:65be27845400 5998
AnnaBridge 172:65be27845400 5999 /******************** Bits definition for DCMI_ESCR register ******************/
AnnaBridge 172:65be27845400 6000 #define DCMI_ESCR_FSC_Pos (0U)
AnnaBridge 172:65be27845400 6001 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6002 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
AnnaBridge 172:65be27845400 6003 #define DCMI_ESCR_LSC_Pos (8U)
AnnaBridge 172:65be27845400 6004 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6005 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
AnnaBridge 172:65be27845400 6006 #define DCMI_ESCR_LEC_Pos (16U)
AnnaBridge 172:65be27845400 6007 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6008 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
AnnaBridge 172:65be27845400 6009 #define DCMI_ESCR_FEC_Pos (24U)
AnnaBridge 172:65be27845400 6010 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6011 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
AnnaBridge 172:65be27845400 6012
AnnaBridge 172:65be27845400 6013 /******************** Bits definition for DCMI_ESUR register ******************/
AnnaBridge 172:65be27845400 6014 #define DCMI_ESUR_FSU_Pos (0U)
AnnaBridge 172:65be27845400 6015 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6016 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
AnnaBridge 172:65be27845400 6017 #define DCMI_ESUR_LSU_Pos (8U)
AnnaBridge 172:65be27845400 6018 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6019 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
AnnaBridge 172:65be27845400 6020 #define DCMI_ESUR_LEU_Pos (16U)
AnnaBridge 172:65be27845400 6021 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6022 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
AnnaBridge 172:65be27845400 6023 #define DCMI_ESUR_FEU_Pos (24U)
AnnaBridge 172:65be27845400 6024 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6025 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
AnnaBridge 172:65be27845400 6026
AnnaBridge 172:65be27845400 6027 /******************** Bits definition for DCMI_CWSTRT register ******************/
AnnaBridge 172:65be27845400 6028 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
AnnaBridge 172:65be27845400 6029 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6030 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
AnnaBridge 172:65be27845400 6031 #define DCMI_CWSTRT_VST_Pos (16U)
AnnaBridge 172:65be27845400 6032 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
AnnaBridge 172:65be27845400 6033 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
AnnaBridge 172:65be27845400 6034
AnnaBridge 172:65be27845400 6035 /******************** Bits definition for DCMI_CWSIZE register ******************/
AnnaBridge 172:65be27845400 6036 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
AnnaBridge 172:65be27845400 6037 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6038 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
AnnaBridge 172:65be27845400 6039 #define DCMI_CWSIZE_VLINE_Pos (16U)
AnnaBridge 172:65be27845400 6040 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
AnnaBridge 172:65be27845400 6041 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
AnnaBridge 172:65be27845400 6042
AnnaBridge 172:65be27845400 6043 /******************** Bits definition for DCMI_DR register ******************/
AnnaBridge 172:65be27845400 6044 #define DCMI_DR_BYTE0_Pos (0U)
AnnaBridge 172:65be27845400 6045 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6046 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
AnnaBridge 172:65be27845400 6047 #define DCMI_DR_BYTE1_Pos (8U)
AnnaBridge 172:65be27845400 6048 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6049 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
AnnaBridge 172:65be27845400 6050 #define DCMI_DR_BYTE2_Pos (16U)
AnnaBridge 172:65be27845400 6051 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6052 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
AnnaBridge 172:65be27845400 6053 #define DCMI_DR_BYTE3_Pos (24U)
AnnaBridge 172:65be27845400 6054 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6055 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
AnnaBridge 172:65be27845400 6056
AnnaBridge 172:65be27845400 6057 /******************************************************************************/
AnnaBridge 172:65be27845400 6058 /* */
AnnaBridge 172:65be27845400 6059 /* Digital Filter for Sigma Delta Modulators */
AnnaBridge 172:65be27845400 6060 /* */
AnnaBridge 172:65be27845400 6061 /******************************************************************************/
AnnaBridge 172:65be27845400 6062
AnnaBridge 172:65be27845400 6063 /**************** DFSDM channel configuration registers ********************/
AnnaBridge 172:65be27845400 6064
AnnaBridge 172:65be27845400 6065 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
AnnaBridge 172:65be27845400 6066 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
AnnaBridge 172:65be27845400 6067 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 6068 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
AnnaBridge 172:65be27845400 6069 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
AnnaBridge 172:65be27845400 6070 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 6071 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
AnnaBridge 172:65be27845400 6072 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
AnnaBridge 172:65be27845400 6073 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6074 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
AnnaBridge 172:65be27845400 6075 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
AnnaBridge 172:65be27845400 6076 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 6077 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
AnnaBridge 172:65be27845400 6078 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 6079 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6080 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
AnnaBridge 172:65be27845400 6081 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 6082 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
AnnaBridge 172:65be27845400 6083 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6084 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6085 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
AnnaBridge 172:65be27845400 6086 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6087 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
AnnaBridge 172:65be27845400 6088 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
AnnaBridge 172:65be27845400 6089 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6090 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
AnnaBridge 172:65be27845400 6091 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
AnnaBridge 172:65be27845400 6092 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6093 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
AnnaBridge 172:65be27845400 6094 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
AnnaBridge 172:65be27845400 6095 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6096 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
AnnaBridge 172:65be27845400 6097 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
AnnaBridge 172:65be27845400 6098 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 6099 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
AnnaBridge 172:65be27845400 6100 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6101 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6102 #define DFSDM_CHCFGR1_SITP_Pos (0U)
AnnaBridge 172:65be27845400 6103 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 6104 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
AnnaBridge 172:65be27845400 6105 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6106 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6107
AnnaBridge 172:65be27845400 6108 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
AnnaBridge 172:65be27845400 6109 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
AnnaBridge 172:65be27845400 6110 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 6111 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
AnnaBridge 172:65be27845400 6112 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
AnnaBridge 172:65be27845400 6113 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
AnnaBridge 172:65be27845400 6114 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
AnnaBridge 172:65be27845400 6115
AnnaBridge 172:65be27845400 6116 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
AnnaBridge 172:65be27845400 6117 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
AnnaBridge 172:65be27845400 6118 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 6119 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
AnnaBridge 172:65be27845400 6120 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 6121 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6122 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
AnnaBridge 172:65be27845400 6123 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 6124 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
AnnaBridge 172:65be27845400 6125 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
AnnaBridge 172:65be27845400 6126 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 6127 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
AnnaBridge 172:65be27845400 6128 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
AnnaBridge 172:65be27845400 6129 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6130 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
AnnaBridge 172:65be27845400 6131
AnnaBridge 172:65be27845400 6132 /**************** Bit definition for DFSDM_CHWDATR register *******************/
AnnaBridge 172:65be27845400 6133 #define DFSDM_CHWDATR_WDATA_Pos (0U)
AnnaBridge 172:65be27845400 6134 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6135 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
AnnaBridge 172:65be27845400 6136
AnnaBridge 172:65be27845400 6137 /**************** Bit definition for DFSDM_CHDATINR register *****************/
AnnaBridge 172:65be27845400 6138 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
AnnaBridge 172:65be27845400 6139 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6140 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
AnnaBridge 172:65be27845400 6141 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
AnnaBridge 172:65be27845400 6142 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 6143 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
AnnaBridge 172:65be27845400 6144
AnnaBridge 172:65be27845400 6145 /************************ DFSDM module registers ****************************/
AnnaBridge 172:65be27845400 6146
AnnaBridge 172:65be27845400 6147 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
AnnaBridge 172:65be27845400 6148 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
AnnaBridge 172:65be27845400 6149 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 6150 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
AnnaBridge 172:65be27845400 6151 #define DFSDM_FLTCR1_FAST_Pos (29U)
AnnaBridge 172:65be27845400 6152 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 6153 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
AnnaBridge 172:65be27845400 6154 #define DFSDM_FLTCR1_RCH_Pos (24U)
AnnaBridge 172:65be27845400 6155 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 6156 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
AnnaBridge 172:65be27845400 6157 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
AnnaBridge 172:65be27845400 6158 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6159 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
AnnaBridge 172:65be27845400 6160 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
AnnaBridge 172:65be27845400 6161 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6162 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
AnnaBridge 172:65be27845400 6163 #define DFSDM_FLTCR1_RCONT_Pos (18U)
AnnaBridge 172:65be27845400 6164 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6165 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
AnnaBridge 172:65be27845400 6166 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
AnnaBridge 172:65be27845400 6167 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6168 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
AnnaBridge 172:65be27845400 6169 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
AnnaBridge 172:65be27845400 6170 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 6171 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
AnnaBridge 172:65be27845400 6172 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6173 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6174 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
AnnaBridge 172:65be27845400 6175 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 6176 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
AnnaBridge 172:65be27845400 6177 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6178 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6179 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6180 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6181 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6182
AnnaBridge 172:65be27845400 6183 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
AnnaBridge 172:65be27845400 6184 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6185 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
AnnaBridge 172:65be27845400 6186 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
AnnaBridge 172:65be27845400 6187 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6188 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
AnnaBridge 172:65be27845400 6189 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
AnnaBridge 172:65be27845400 6190 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6191 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
AnnaBridge 172:65be27845400 6192 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
AnnaBridge 172:65be27845400 6193 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6194 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
AnnaBridge 172:65be27845400 6195 #define DFSDM_FLTCR1_DFEN_Pos (0U)
AnnaBridge 172:65be27845400 6196 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6197 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
AnnaBridge 172:65be27845400 6198
AnnaBridge 172:65be27845400 6199 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
AnnaBridge 172:65be27845400 6200 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
AnnaBridge 172:65be27845400 6201 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6202 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
AnnaBridge 172:65be27845400 6203 #define DFSDM_FLTCR2_EXCH_Pos (8U)
AnnaBridge 172:65be27845400 6204 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6205 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
AnnaBridge 172:65be27845400 6206 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
AnnaBridge 172:65be27845400 6207 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6208 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
AnnaBridge 172:65be27845400 6209 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
AnnaBridge 172:65be27845400 6210 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6211 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
AnnaBridge 172:65be27845400 6212 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
AnnaBridge 172:65be27845400 6213 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6214 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
AnnaBridge 172:65be27845400 6215 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
AnnaBridge 172:65be27845400 6216 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6217 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
AnnaBridge 172:65be27845400 6218 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
AnnaBridge 172:65be27845400 6219 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6220 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
AnnaBridge 172:65be27845400 6221 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
AnnaBridge 172:65be27845400 6222 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6223 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
AnnaBridge 172:65be27845400 6224 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
AnnaBridge 172:65be27845400 6225 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6226 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
AnnaBridge 172:65be27845400 6227
AnnaBridge 172:65be27845400 6228 /******************** Bit definition for DFSDM_FLTISR register *******************/
AnnaBridge 172:65be27845400 6229 #define DFSDM_FLTISR_SCDF_Pos (24U)
AnnaBridge 172:65be27845400 6230 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6231 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
AnnaBridge 172:65be27845400 6232 #define DFSDM_FLTISR_CKABF_Pos (16U)
AnnaBridge 172:65be27845400 6233 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6234 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
AnnaBridge 172:65be27845400 6235 #define DFSDM_FLTISR_RCIP_Pos (14U)
AnnaBridge 172:65be27845400 6236 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6237 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
AnnaBridge 172:65be27845400 6238 #define DFSDM_FLTISR_JCIP_Pos (13U)
AnnaBridge 172:65be27845400 6239 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6240 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
AnnaBridge 172:65be27845400 6241 #define DFSDM_FLTISR_AWDF_Pos (4U)
AnnaBridge 172:65be27845400 6242 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6243 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
AnnaBridge 172:65be27845400 6244 #define DFSDM_FLTISR_ROVRF_Pos (3U)
AnnaBridge 172:65be27845400 6245 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6246 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
AnnaBridge 172:65be27845400 6247 #define DFSDM_FLTISR_JOVRF_Pos (2U)
AnnaBridge 172:65be27845400 6248 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6249 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
AnnaBridge 172:65be27845400 6250 #define DFSDM_FLTISR_REOCF_Pos (1U)
AnnaBridge 172:65be27845400 6251 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6252 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
AnnaBridge 172:65be27845400 6253 #define DFSDM_FLTISR_JEOCF_Pos (0U)
AnnaBridge 172:65be27845400 6254 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6255 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
AnnaBridge 172:65be27845400 6256
AnnaBridge 172:65be27845400 6257 /******************** Bit definition for DFSDM_FLTICR register *******************/
AnnaBridge 172:65be27845400 6258 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
AnnaBridge 172:65be27845400 6259 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 6260 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
AnnaBridge 172:65be27845400 6261 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
AnnaBridge 172:65be27845400 6262 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 6263 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
AnnaBridge 172:65be27845400 6264 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
AnnaBridge 172:65be27845400 6265 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6266 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
AnnaBridge 172:65be27845400 6267 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
AnnaBridge 172:65be27845400 6268 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6269 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
AnnaBridge 172:65be27845400 6270
AnnaBridge 172:65be27845400 6271 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
AnnaBridge 172:65be27845400 6272 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
AnnaBridge 172:65be27845400 6273 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6274 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
AnnaBridge 172:65be27845400 6275
AnnaBridge 172:65be27845400 6276 /******************** Bit definition for DFSDM_FLTFCR register *******************/
AnnaBridge 172:65be27845400 6277 #define DFSDM_FLTFCR_FORD_Pos (29U)
AnnaBridge 172:65be27845400 6278 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
AnnaBridge 172:65be27845400 6279 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
AnnaBridge 172:65be27845400 6280 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 6281 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 6282 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 6283 #define DFSDM_FLTFCR_FOSR_Pos (16U)
AnnaBridge 172:65be27845400 6284 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
AnnaBridge 172:65be27845400 6285 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
AnnaBridge 172:65be27845400 6286 #define DFSDM_FLTFCR_IOSR_Pos (0U)
AnnaBridge 172:65be27845400 6287 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6288 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
AnnaBridge 172:65be27845400 6289
AnnaBridge 172:65be27845400 6290 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
AnnaBridge 172:65be27845400 6291 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
AnnaBridge 172:65be27845400 6292 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 6293 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
AnnaBridge 172:65be27845400 6294 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
AnnaBridge 172:65be27845400 6295 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 6296 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
AnnaBridge 172:65be27845400 6297
AnnaBridge 172:65be27845400 6298 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
AnnaBridge 172:65be27845400 6299 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
AnnaBridge 172:65be27845400 6300 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 6301 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
AnnaBridge 172:65be27845400 6302 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
AnnaBridge 172:65be27845400 6303 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6304 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
AnnaBridge 172:65be27845400 6305 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
AnnaBridge 172:65be27845400 6306 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 6307 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
AnnaBridge 172:65be27845400 6308
AnnaBridge 172:65be27845400 6309 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
AnnaBridge 172:65be27845400 6310 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
AnnaBridge 172:65be27845400 6311 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 6312 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
AnnaBridge 172:65be27845400 6313 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
AnnaBridge 172:65be27845400 6314 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 6315 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
AnnaBridge 172:65be27845400 6316
AnnaBridge 172:65be27845400 6317 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
AnnaBridge 172:65be27845400 6318 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
AnnaBridge 172:65be27845400 6319 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 6320 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
AnnaBridge 172:65be27845400 6321 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
AnnaBridge 172:65be27845400 6322 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 6323 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
AnnaBridge 172:65be27845400 6324
AnnaBridge 172:65be27845400 6325 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
AnnaBridge 172:65be27845400 6326 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
AnnaBridge 172:65be27845400 6327 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6328 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
AnnaBridge 172:65be27845400 6329 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
AnnaBridge 172:65be27845400 6330 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6331 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
AnnaBridge 172:65be27845400 6332
AnnaBridge 172:65be27845400 6333 /****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
AnnaBridge 172:65be27845400 6334 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
AnnaBridge 172:65be27845400 6335 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 6336 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
AnnaBridge 172:65be27845400 6337 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
AnnaBridge 172:65be27845400 6338 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 6339 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
AnnaBridge 172:65be27845400 6340
AnnaBridge 172:65be27845400 6341 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
AnnaBridge 172:65be27845400 6342 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
AnnaBridge 172:65be27845400 6343 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 6344 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
AnnaBridge 172:65be27845400 6345 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
AnnaBridge 172:65be27845400 6346 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 6347 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
AnnaBridge 172:65be27845400 6348
AnnaBridge 172:65be27845400 6349 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
AnnaBridge 172:65be27845400 6350 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
AnnaBridge 172:65be27845400 6351 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 6352 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
AnnaBridge 172:65be27845400 6353 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
AnnaBridge 172:65be27845400 6354 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 6355 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
AnnaBridge 172:65be27845400 6356
AnnaBridge 172:65be27845400 6357 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
AnnaBridge 172:65be27845400 6358 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
AnnaBridge 172:65be27845400 6359 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
AnnaBridge 172:65be27845400 6360 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
AnnaBridge 172:65be27845400 6361
AnnaBridge 172:65be27845400 6362 /******************************************************************************/
AnnaBridge 172:65be27845400 6363 /* */
AnnaBridge 172:65be27845400 6364 /* BDMA Controller */
AnnaBridge 172:65be27845400 6365 /* */
AnnaBridge 172:65be27845400 6366 /******************************************************************************/
AnnaBridge 172:65be27845400 6367
AnnaBridge 172:65be27845400 6368 /******************* Bit definition for BDMA_ISR register ********************/
AnnaBridge 172:65be27845400 6369 #define BDMA_ISR_GIF0_Pos (0U)
AnnaBridge 172:65be27845400 6370 #define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6371 #define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
AnnaBridge 172:65be27845400 6372 #define BDMA_ISR_TCIF0_Pos (1U)
AnnaBridge 172:65be27845400 6373 #define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6374 #define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
AnnaBridge 172:65be27845400 6375 #define BDMA_ISR_HTIF0_Pos (2U)
AnnaBridge 172:65be27845400 6376 #define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6377 #define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
AnnaBridge 172:65be27845400 6378 #define BDMA_ISR_TEIF0_Pos (3U)
AnnaBridge 172:65be27845400 6379 #define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6380 #define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
AnnaBridge 172:65be27845400 6381 #define BDMA_ISR_GIF1_Pos (4U)
AnnaBridge 172:65be27845400 6382 #define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6383 #define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
AnnaBridge 172:65be27845400 6384 #define BDMA_ISR_TCIF1_Pos (5U)
AnnaBridge 172:65be27845400 6385 #define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6386 #define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
AnnaBridge 172:65be27845400 6387 #define BDMA_ISR_HTIF1_Pos (6U)
AnnaBridge 172:65be27845400 6388 #define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6389 #define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
AnnaBridge 172:65be27845400 6390 #define BDMA_ISR_TEIF1_Pos (7U)
AnnaBridge 172:65be27845400 6391 #define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6392 #define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
AnnaBridge 172:65be27845400 6393 #define BDMA_ISR_GIF2_Pos (8U)
AnnaBridge 172:65be27845400 6394 #define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6395 #define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
AnnaBridge 172:65be27845400 6396 #define BDMA_ISR_TCIF2_Pos (9U)
AnnaBridge 172:65be27845400 6397 #define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6398 #define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
AnnaBridge 172:65be27845400 6399 #define BDMA_ISR_HTIF2_Pos (10U)
AnnaBridge 172:65be27845400 6400 #define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6401 #define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
AnnaBridge 172:65be27845400 6402 #define BDMA_ISR_TEIF2_Pos (11U)
AnnaBridge 172:65be27845400 6403 #define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6404 #define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
AnnaBridge 172:65be27845400 6405 #define BDMA_ISR_GIF3_Pos (12U)
AnnaBridge 172:65be27845400 6406 #define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6407 #define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
AnnaBridge 172:65be27845400 6408 #define BDMA_ISR_TCIF3_Pos (13U)
AnnaBridge 172:65be27845400 6409 #define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6410 #define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
AnnaBridge 172:65be27845400 6411 #define BDMA_ISR_HTIF3_Pos (14U)
AnnaBridge 172:65be27845400 6412 #define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6413 #define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
AnnaBridge 172:65be27845400 6414 #define BDMA_ISR_TEIF3_Pos (15U)
AnnaBridge 172:65be27845400 6415 #define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 6416 #define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
AnnaBridge 172:65be27845400 6417 #define BDMA_ISR_GIF4_Pos (16U)
AnnaBridge 172:65be27845400 6418 #define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6419 #define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
AnnaBridge 172:65be27845400 6420 #define BDMA_ISR_TCIF4_Pos (17U)
AnnaBridge 172:65be27845400 6421 #define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6422 #define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
AnnaBridge 172:65be27845400 6423 #define BDMA_ISR_HTIF4_Pos (18U)
AnnaBridge 172:65be27845400 6424 #define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6425 #define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
AnnaBridge 172:65be27845400 6426 #define BDMA_ISR_TEIF4_Pos (19U)
AnnaBridge 172:65be27845400 6427 #define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6428 #define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
AnnaBridge 172:65be27845400 6429 #define BDMA_ISR_GIF5_Pos (20U)
AnnaBridge 172:65be27845400 6430 #define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6431 #define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
AnnaBridge 172:65be27845400 6432 #define BDMA_ISR_TCIF5_Pos (21U)
AnnaBridge 172:65be27845400 6433 #define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6434 #define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
AnnaBridge 172:65be27845400 6435 #define BDMA_ISR_HTIF5_Pos (22U)
AnnaBridge 172:65be27845400 6436 #define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6437 #define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
AnnaBridge 172:65be27845400 6438 #define BDMA_ISR_TEIF5_Pos (23U)
AnnaBridge 172:65be27845400 6439 #define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 6440 #define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
AnnaBridge 172:65be27845400 6441 #define BDMA_ISR_GIF6_Pos (24U)
AnnaBridge 172:65be27845400 6442 #define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6443 #define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
AnnaBridge 172:65be27845400 6444 #define BDMA_ISR_TCIF6_Pos (25U)
AnnaBridge 172:65be27845400 6445 #define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 6446 #define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
AnnaBridge 172:65be27845400 6447 #define BDMA_ISR_HTIF6_Pos (26U)
AnnaBridge 172:65be27845400 6448 #define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 6449 #define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
AnnaBridge 172:65be27845400 6450 #define BDMA_ISR_TEIF6_Pos (27U)
AnnaBridge 172:65be27845400 6451 #define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6452 #define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
AnnaBridge 172:65be27845400 6453 #define BDMA_ISR_GIF7_Pos (28U)
AnnaBridge 172:65be27845400 6454 #define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 6455 #define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
AnnaBridge 172:65be27845400 6456 #define BDMA_ISR_TCIF7_Pos (29U)
AnnaBridge 172:65be27845400 6457 #define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 6458 #define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
AnnaBridge 172:65be27845400 6459 #define BDMA_ISR_HTIF7_Pos (30U)
AnnaBridge 172:65be27845400 6460 #define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 6461 #define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
AnnaBridge 172:65be27845400 6462 #define BDMA_ISR_TEIF7_Pos (31U)
AnnaBridge 172:65be27845400 6463 #define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 6464 #define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
AnnaBridge 172:65be27845400 6465
AnnaBridge 172:65be27845400 6466 /******************* Bit definition for BDMA_IFCR register *******************/
AnnaBridge 172:65be27845400 6467 #define BDMA_IFCR_CGIF0_Pos (0U)
AnnaBridge 172:65be27845400 6468 #define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6469 #define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
AnnaBridge 172:65be27845400 6470 #define BDMA_IFCR_CTCIF0_Pos (1U)
AnnaBridge 172:65be27845400 6471 #define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6472 #define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
AnnaBridge 172:65be27845400 6473 #define BDMA_IFCR_CHTIF0_Pos (2U)
AnnaBridge 172:65be27845400 6474 #define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6475 #define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
AnnaBridge 172:65be27845400 6476 #define BDMA_IFCR_CTEIF0_Pos (3U)
AnnaBridge 172:65be27845400 6477 #define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6478 #define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
AnnaBridge 172:65be27845400 6479 #define BDMA_IFCR_CGIF1_Pos (4U)
AnnaBridge 172:65be27845400 6480 #define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6481 #define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
AnnaBridge 172:65be27845400 6482 #define BDMA_IFCR_CTCIF1_Pos (5U)
AnnaBridge 172:65be27845400 6483 #define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6484 #define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
AnnaBridge 172:65be27845400 6485 #define BDMA_IFCR_CHTIF1_Pos (6U)
AnnaBridge 172:65be27845400 6486 #define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6487 #define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
AnnaBridge 172:65be27845400 6488 #define BDMA_IFCR_CTEIF1_Pos (7U)
AnnaBridge 172:65be27845400 6489 #define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6490 #define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
AnnaBridge 172:65be27845400 6491 #define BDMA_IFCR_CGIF2_Pos (8U)
AnnaBridge 172:65be27845400 6492 #define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6493 #define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
AnnaBridge 172:65be27845400 6494 #define BDMA_IFCR_CTCIF2_Pos (9U)
AnnaBridge 172:65be27845400 6495 #define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6496 #define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
AnnaBridge 172:65be27845400 6497 #define BDMA_IFCR_CHTIF2_Pos (10U)
AnnaBridge 172:65be27845400 6498 #define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6499 #define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
AnnaBridge 172:65be27845400 6500 #define BDMA_IFCR_CTEIF2_Pos (11U)
AnnaBridge 172:65be27845400 6501 #define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6502 #define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
AnnaBridge 172:65be27845400 6503 #define BDMA_IFCR_CGIF3_Pos (12U)
AnnaBridge 172:65be27845400 6504 #define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6505 #define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
AnnaBridge 172:65be27845400 6506 #define BDMA_IFCR_CTCIF3_Pos (13U)
AnnaBridge 172:65be27845400 6507 #define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6508 #define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
AnnaBridge 172:65be27845400 6509 #define BDMA_IFCR_CHTIF3_Pos (14U)
AnnaBridge 172:65be27845400 6510 #define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6511 #define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
AnnaBridge 172:65be27845400 6512 #define BDMA_IFCR_CTEIF3_Pos (15U)
AnnaBridge 172:65be27845400 6513 #define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 6514 #define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
AnnaBridge 172:65be27845400 6515 #define BDMA_IFCR_CGIF4_Pos (16U)
AnnaBridge 172:65be27845400 6516 #define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6517 #define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
AnnaBridge 172:65be27845400 6518 #define BDMA_IFCR_CTCIF4_Pos (17U)
AnnaBridge 172:65be27845400 6519 #define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6520 #define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
AnnaBridge 172:65be27845400 6521 #define BDMA_IFCR_CHTIF4_Pos (18U)
AnnaBridge 172:65be27845400 6522 #define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6523 #define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
AnnaBridge 172:65be27845400 6524 #define BDMA_IFCR_CTEIF4_Pos (19U)
AnnaBridge 172:65be27845400 6525 #define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6526 #define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
AnnaBridge 172:65be27845400 6527 #define BDMA_IFCR_CGIF5_Pos (20U)
AnnaBridge 172:65be27845400 6528 #define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6529 #define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
AnnaBridge 172:65be27845400 6530 #define BDMA_IFCR_CTCIF5_Pos (21U)
AnnaBridge 172:65be27845400 6531 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6532 #define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
AnnaBridge 172:65be27845400 6533 #define BDMA_IFCR_CHTIF5_Pos (22U)
AnnaBridge 172:65be27845400 6534 #define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6535 #define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
AnnaBridge 172:65be27845400 6536 #define BDMA_IFCR_CTEIF5_Pos (23U)
AnnaBridge 172:65be27845400 6537 #define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 6538 #define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
AnnaBridge 172:65be27845400 6539 #define BDMA_IFCR_CGIF6_Pos (24U)
AnnaBridge 172:65be27845400 6540 #define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6541 #define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
AnnaBridge 172:65be27845400 6542 #define BDMA_IFCR_CTCIF6_Pos (25U)
AnnaBridge 172:65be27845400 6543 #define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 6544 #define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
AnnaBridge 172:65be27845400 6545 #define BDMA_IFCR_CHTIF6_Pos (26U)
AnnaBridge 172:65be27845400 6546 #define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 6547 #define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
AnnaBridge 172:65be27845400 6548 #define BDMA_IFCR_CTEIF6_Pos (27U)
AnnaBridge 172:65be27845400 6549 #define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6550 #define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
AnnaBridge 172:65be27845400 6551 #define BDMA_IFCR_CGIF7_Pos (28U)
AnnaBridge 172:65be27845400 6552 #define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 6553 #define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
AnnaBridge 172:65be27845400 6554 #define BDMA_IFCR_CTCIF7_Pos (29U)
AnnaBridge 172:65be27845400 6555 #define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 6556 #define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
AnnaBridge 172:65be27845400 6557 #define BDMA_IFCR_CHTIF7_Pos (30U)
AnnaBridge 172:65be27845400 6558 #define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 6559 #define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
AnnaBridge 172:65be27845400 6560 #define BDMA_IFCR_CTEIF7_Pos (31U)
AnnaBridge 172:65be27845400 6561 #define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 6562 #define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
AnnaBridge 172:65be27845400 6563
AnnaBridge 172:65be27845400 6564 /******************* Bit definition for BDMA_CCR register ********************/
AnnaBridge 172:65be27845400 6565 #define BDMA_CCR_EN_Pos (0U)
AnnaBridge 172:65be27845400 6566 #define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6567 #define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
AnnaBridge 172:65be27845400 6568 #define BDMA_CCR_TCIE_Pos (1U)
AnnaBridge 172:65be27845400 6569 #define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6570 #define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 172:65be27845400 6571 #define BDMA_CCR_HTIE_Pos (2U)
AnnaBridge 172:65be27845400 6572 #define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6573 #define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
AnnaBridge 172:65be27845400 6574 #define BDMA_CCR_TEIE_Pos (3U)
AnnaBridge 172:65be27845400 6575 #define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6576 #define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 172:65be27845400 6577 #define BDMA_CCR_DIR_Pos (4U)
AnnaBridge 172:65be27845400 6578 #define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6579 #define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
AnnaBridge 172:65be27845400 6580 #define BDMA_CCR_CIRC_Pos (5U)
AnnaBridge 172:65be27845400 6581 #define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6582 #define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
AnnaBridge 172:65be27845400 6583 #define BDMA_CCR_PINC_Pos (6U)
AnnaBridge 172:65be27845400 6584 #define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6585 #define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
AnnaBridge 172:65be27845400 6586 #define BDMA_CCR_MINC_Pos (7U)
AnnaBridge 172:65be27845400 6587 #define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6588 #define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
AnnaBridge 172:65be27845400 6589
AnnaBridge 172:65be27845400 6590 #define BDMA_CCR_PSIZE_Pos (8U)
AnnaBridge 172:65be27845400 6591 #define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 6592 #define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
AnnaBridge 172:65be27845400 6593 #define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6594 #define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6595
AnnaBridge 172:65be27845400 6596 #define BDMA_CCR_MSIZE_Pos (10U)
AnnaBridge 172:65be27845400 6597 #define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 6598 #define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
AnnaBridge 172:65be27845400 6599 #define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6600 #define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6601
AnnaBridge 172:65be27845400 6602 #define BDMA_CCR_PL_Pos (12U)
AnnaBridge 172:65be27845400 6603 #define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 6604 #define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
AnnaBridge 172:65be27845400 6605 #define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6606 #define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6607
AnnaBridge 172:65be27845400 6608 #define BDMA_CCR_MEM2MEM_Pos (14U)
AnnaBridge 172:65be27845400 6609 #define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6610 #define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
AnnaBridge 172:65be27845400 6611 #define BDMA_CCR_DBM_Pos (15U)
AnnaBridge 172:65be27845400 6612 #define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
AnnaBridge 172:65be27845400 6613 #define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
AnnaBridge 172:65be27845400 6614 #define BDMA_CCR_CT_Pos (16U)
AnnaBridge 172:65be27845400 6615 #define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6616 #define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
AnnaBridge 172:65be27845400 6617
AnnaBridge 172:65be27845400 6618 /****************** Bit definition for BDMA_CNDTR register *******************/
AnnaBridge 172:65be27845400 6619 #define BDMA_CNDTR_NDT_Pos (0U)
AnnaBridge 172:65be27845400 6620 #define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6621 #define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 172:65be27845400 6622
AnnaBridge 172:65be27845400 6623 /****************** Bit definition for BDMA_CPAR register ********************/
AnnaBridge 172:65be27845400 6624 #define BDMA_CPAR_PA_Pos (0U)
AnnaBridge 172:65be27845400 6625 #define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6626 #define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 172:65be27845400 6627
AnnaBridge 172:65be27845400 6628 /****************** Bit definition for BDMA_CM0AR register ********************/
AnnaBridge 172:65be27845400 6629 #define BDMA_CM0AR_MA_Pos (0U)
AnnaBridge 172:65be27845400 6630 #define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6631 #define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6632
AnnaBridge 172:65be27845400 6633 /****************** Bit definition for BDMA_CM1AR register ********************/
AnnaBridge 172:65be27845400 6634 #define BDMA_CM1AR_MA_Pos (0U)
AnnaBridge 172:65be27845400 6635 #define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6636 #define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
AnnaBridge 172:65be27845400 6637
AnnaBridge 172:65be27845400 6638 /******************************************************************************/
AnnaBridge 172:65be27845400 6639 /* */
AnnaBridge 172:65be27845400 6640 /* Ethernet MAC Registers bits definitions */
AnnaBridge 172:65be27845400 6641 /* */
AnnaBridge 172:65be27845400 6642 /******************************************************************************/
AnnaBridge 172:65be27845400 6643 /* Bit definition for Ethernet MAC Configuration Register register */
AnnaBridge 172:65be27845400 6644 #define ETH_MACCR_ARP_Pos (31U)
AnnaBridge 172:65be27845400 6645 #define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 6646 #define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
AnnaBridge 172:65be27845400 6647 #define ETH_MACCR_SARC_Pos (28U)
AnnaBridge 172:65be27845400 6648 #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 6649 #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
AnnaBridge 172:65be27845400 6650 #define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
AnnaBridge 172:65be27845400 6651 #define ETH_MACCR_SARC_INSADDR0_Pos (29U)
AnnaBridge 172:65be27845400 6652 #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 6653 #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
AnnaBridge 172:65be27845400 6654 #define ETH_MACCR_SARC_INSADDR1_Pos (29U)
AnnaBridge 172:65be27845400 6655 #define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
AnnaBridge 172:65be27845400 6656 #define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
AnnaBridge 172:65be27845400 6657 #define ETH_MACCR_SARC_REPADDR0_Pos (28U)
AnnaBridge 172:65be27845400 6658 #define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 6659 #define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
AnnaBridge 172:65be27845400 6660 #define ETH_MACCR_SARC_REPADDR1_Pos (28U)
AnnaBridge 172:65be27845400 6661 #define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 6662 #define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
AnnaBridge 172:65be27845400 6663 #define ETH_MACCR_IPC_Pos (27U)
AnnaBridge 172:65be27845400 6664 #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6665 #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
AnnaBridge 172:65be27845400 6666 #define ETH_MACCR_IPG_Pos (24U)
AnnaBridge 172:65be27845400 6667 #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 6668 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
AnnaBridge 172:65be27845400 6669 #define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
AnnaBridge 172:65be27845400 6670 #define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
AnnaBridge 172:65be27845400 6671 #define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
AnnaBridge 172:65be27845400 6672 #define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
AnnaBridge 172:65be27845400 6673 #define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
AnnaBridge 172:65be27845400 6674 #define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
AnnaBridge 172:65be27845400 6675 #define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
AnnaBridge 172:65be27845400 6676 #define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
AnnaBridge 172:65be27845400 6677 #define ETH_MACCR_GPSLCE_Pos (23U)
AnnaBridge 172:65be27845400 6678 #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 6679 #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
AnnaBridge 172:65be27845400 6680 #define ETH_MACCR_S2KP_Pos (22U)
AnnaBridge 172:65be27845400 6681 #define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6682 #define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
AnnaBridge 172:65be27845400 6683 #define ETH_MACCR_CST_Pos (21U)
AnnaBridge 172:65be27845400 6684 #define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6685 #define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
AnnaBridge 172:65be27845400 6686 #define ETH_MACCR_ACS_Pos (20U)
AnnaBridge 172:65be27845400 6687 #define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6688 #define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
AnnaBridge 172:65be27845400 6689 #define ETH_MACCR_WD_Pos (19U)
AnnaBridge 172:65be27845400 6690 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6691 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
AnnaBridge 172:65be27845400 6692 #define ETH_MACCR_JD_Pos (17U)
AnnaBridge 172:65be27845400 6693 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6694 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
AnnaBridge 172:65be27845400 6695 #define ETH_MACCR_JE_Pos (16U)
AnnaBridge 172:65be27845400 6696 #define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6697 #define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
AnnaBridge 172:65be27845400 6698 #define ETH_MACCR_FES_Pos (14U)
AnnaBridge 172:65be27845400 6699 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 6700 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
AnnaBridge 172:65be27845400 6701 #define ETH_MACCR_DM_Pos (13U)
AnnaBridge 172:65be27845400 6702 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 6703 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
AnnaBridge 172:65be27845400 6704 #define ETH_MACCR_LM_Pos (12U)
AnnaBridge 172:65be27845400 6705 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6706 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
AnnaBridge 172:65be27845400 6707 #define ETH_MACCR_ECRSFD_Pos (11U)
AnnaBridge 172:65be27845400 6708 #define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 6709 #define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
AnnaBridge 172:65be27845400 6710 #define ETH_MACCR_DO_Pos (10U)
AnnaBridge 172:65be27845400 6711 #define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6712 #define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
AnnaBridge 172:65be27845400 6713 #define ETH_MACCR_DCRS_Pos (9U)
AnnaBridge 172:65be27845400 6714 #define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6715 #define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
AnnaBridge 172:65be27845400 6716 #define ETH_MACCR_DR_Pos (8U)
AnnaBridge 172:65be27845400 6717 #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6718 #define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
AnnaBridge 172:65be27845400 6719 #define ETH_MACCR_BL_Pos (5U)
AnnaBridge 172:65be27845400 6720 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 6721 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
AnnaBridge 172:65be27845400 6722 #define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 6723 #define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6724 #define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6725 #define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 6726 #define ETH_MACCR_DC_Pos (4U)
AnnaBridge 172:65be27845400 6727 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6728 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
AnnaBridge 172:65be27845400 6729 #define ETH_MACCR_PRELEN_Pos (2U)
AnnaBridge 172:65be27845400 6730 #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 6731 #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
AnnaBridge 172:65be27845400 6732 #define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 6733 #define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6734 #define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6735 #define ETH_MACCR_TE_Pos (1U)
AnnaBridge 172:65be27845400 6736 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6737 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
AnnaBridge 172:65be27845400 6738 #define ETH_MACCR_RE_Pos (0U)
AnnaBridge 172:65be27845400 6739 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6740 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
AnnaBridge 172:65be27845400 6741
AnnaBridge 172:65be27845400 6742 /* Bit definition for Ethernet MAC Extended Configuration Register register */
AnnaBridge 172:65be27845400 6743 #define ETH_MACECR_EIPG_Pos (25U)
AnnaBridge 172:65be27845400 6744 #define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
AnnaBridge 172:65be27845400 6745 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
AnnaBridge 172:65be27845400 6746 #define ETH_MACECR_EIPGEN_Pos (24U)
AnnaBridge 172:65be27845400 6747 #define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6748 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
AnnaBridge 172:65be27845400 6749 #define ETH_MACECR_USP_Pos (18U)
AnnaBridge 172:65be27845400 6750 #define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6751 #define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
AnnaBridge 172:65be27845400 6752 #define ETH_MACECR_SPEN_Pos (17U)
AnnaBridge 172:65be27845400 6753 #define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6754 #define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
AnnaBridge 172:65be27845400 6755 #define ETH_MACECR_DCRCC_Pos (16U)
AnnaBridge 172:65be27845400 6756 #define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6757 #define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
AnnaBridge 172:65be27845400 6758 #define ETH_MACECR_GPSL_Pos (0U)
AnnaBridge 172:65be27845400 6759 #define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 6760 #define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
AnnaBridge 172:65be27845400 6761
AnnaBridge 172:65be27845400 6762 /* Bit definition for Ethernet MAC Packet Filter Register */
AnnaBridge 172:65be27845400 6763 #define ETH_MACPFR_RA_Pos (31U)
AnnaBridge 172:65be27845400 6764 #define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 6765 #define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
AnnaBridge 172:65be27845400 6766 #define ETH_MACPFR_DNTU_Pos (21U)
AnnaBridge 172:65be27845400 6767 #define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6768 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
AnnaBridge 172:65be27845400 6769 #define ETH_MACPFR_IPFE_Pos (20U)
AnnaBridge 172:65be27845400 6770 #define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6771 #define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
AnnaBridge 172:65be27845400 6772 #define ETH_MACPFR_VTFE_Pos (16U)
AnnaBridge 172:65be27845400 6773 #define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6774 #define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
AnnaBridge 172:65be27845400 6775 #define ETH_MACPFR_HPF_Pos (10U)
AnnaBridge 172:65be27845400 6776 #define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 6777 #define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
AnnaBridge 172:65be27845400 6778 #define ETH_MACPFR_SAF_Pos (9U)
AnnaBridge 172:65be27845400 6779 #define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 6780 #define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
AnnaBridge 172:65be27845400 6781 #define ETH_MACPFR_SAIF_Pos (8U)
AnnaBridge 172:65be27845400 6782 #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6783 #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
AnnaBridge 172:65be27845400 6784 #define ETH_MACPFR_PCF_Pos (6U)
AnnaBridge 172:65be27845400 6785 #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 6786 #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
AnnaBridge 172:65be27845400 6787 #define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
AnnaBridge 172:65be27845400 6788 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
AnnaBridge 172:65be27845400 6789 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 6790 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
AnnaBridge 172:65be27845400 6791 #define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
AnnaBridge 172:65be27845400 6792 #define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 6793 #define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
AnnaBridge 172:65be27845400 6794 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
AnnaBridge 172:65be27845400 6795 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 6796 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
AnnaBridge 172:65be27845400 6797 #define ETH_MACPFR_DBF_Pos (5U)
AnnaBridge 172:65be27845400 6798 #define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 6799 #define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
AnnaBridge 172:65be27845400 6800 #define ETH_MACPFR_PM_Pos (4U)
AnnaBridge 172:65be27845400 6801 #define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 6802 #define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
AnnaBridge 172:65be27845400 6803 #define ETH_MACPFR_DAIF_Pos (3U)
AnnaBridge 172:65be27845400 6804 #define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 6805 #define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
AnnaBridge 172:65be27845400 6806 #define ETH_MACPFR_HMC_Pos (2U)
AnnaBridge 172:65be27845400 6807 #define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 6808 #define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
AnnaBridge 172:65be27845400 6809 #define ETH_MACPFR_HUC_Pos (1U)
AnnaBridge 172:65be27845400 6810 #define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 6811 #define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
AnnaBridge 172:65be27845400 6812 #define ETH_MACPFR_PR_Pos (0U)
AnnaBridge 172:65be27845400 6813 #define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 6814 #define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
AnnaBridge 172:65be27845400 6815
AnnaBridge 172:65be27845400 6816 /* Bit definition for Ethernet MAC Watchdog Timeout Register */
AnnaBridge 172:65be27845400 6817 #define ETH_MACWTR_PWE_Pos (8U)
AnnaBridge 172:65be27845400 6818 #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 6819 #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
AnnaBridge 172:65be27845400 6820 #define ETH_MACWTR_WTO_Pos (0U)
AnnaBridge 172:65be27845400 6821 #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 6822 #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
AnnaBridge 172:65be27845400 6823 #define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
AnnaBridge 172:65be27845400 6824 #define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
AnnaBridge 172:65be27845400 6825 #define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
AnnaBridge 172:65be27845400 6826 #define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
AnnaBridge 172:65be27845400 6827 #define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
AnnaBridge 172:65be27845400 6828 #define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
AnnaBridge 172:65be27845400 6829 #define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
AnnaBridge 172:65be27845400 6830 #define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
AnnaBridge 172:65be27845400 6831 #define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
AnnaBridge 172:65be27845400 6832 #define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
AnnaBridge 172:65be27845400 6833 #define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
AnnaBridge 172:65be27845400 6834 #define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
AnnaBridge 172:65be27845400 6835 #define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
AnnaBridge 172:65be27845400 6836 #define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
AnnaBridge 172:65be27845400 6837 #define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
AnnaBridge 172:65be27845400 6838
AnnaBridge 172:65be27845400 6839 /* Bit definition for Ethernet MAC Hash Table High Register */
AnnaBridge 172:65be27845400 6840 #define ETH_MACHTHR_HTH_Pos (0U)
AnnaBridge 172:65be27845400 6841 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6842 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
AnnaBridge 172:65be27845400 6843
AnnaBridge 172:65be27845400 6844 /* Bit definition for Ethernet MAC Hash Table Low Register */
AnnaBridge 172:65be27845400 6845 #define ETH_MACHTLR_HTL_Pos (0U)
AnnaBridge 172:65be27845400 6846 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 6847 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
AnnaBridge 172:65be27845400 6848
AnnaBridge 172:65be27845400 6849 /* Bit definition for Ethernet MAC VLAN Tag Register */
AnnaBridge 172:65be27845400 6850 #define ETH_MACVTR_EIVLRXS_Pos (31U)
AnnaBridge 172:65be27845400 6851 #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 6852 #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
AnnaBridge 172:65be27845400 6853 #define ETH_MACVTR_EIVLS_Pos (28U)
AnnaBridge 172:65be27845400 6854 #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 6855 #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
AnnaBridge 172:65be27845400 6856 #define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
AnnaBridge 172:65be27845400 6857 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
AnnaBridge 172:65be27845400 6858 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 6859 #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
AnnaBridge 172:65be27845400 6860 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
AnnaBridge 172:65be27845400 6861 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 6862 #define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
AnnaBridge 172:65be27845400 6863 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
AnnaBridge 172:65be27845400 6864 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 6865 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
AnnaBridge 172:65be27845400 6866 #define ETH_MACVTR_ERIVLT_Pos (27U)
AnnaBridge 172:65be27845400 6867 #define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 6868 #define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
AnnaBridge 172:65be27845400 6869 #define ETH_MACVTR_EDVLP_Pos (26U)
AnnaBridge 172:65be27845400 6870 #define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 6871 #define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
AnnaBridge 172:65be27845400 6872 #define ETH_MACVTR_VTHM_Pos (25U)
AnnaBridge 172:65be27845400 6873 #define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 6874 #define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
AnnaBridge 172:65be27845400 6875 #define ETH_MACVTR_EVLRXS_Pos (24U)
AnnaBridge 172:65be27845400 6876 #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 6877 #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
AnnaBridge 172:65be27845400 6878 #define ETH_MACVTR_EVLS_Pos (21U)
AnnaBridge 172:65be27845400 6879 #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 6880 #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
AnnaBridge 172:65be27845400 6881 #define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
AnnaBridge 172:65be27845400 6882 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
AnnaBridge 172:65be27845400 6883 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 6884 #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
AnnaBridge 172:65be27845400 6885 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
AnnaBridge 172:65be27845400 6886 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 6887 #define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
AnnaBridge 172:65be27845400 6888 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
AnnaBridge 172:65be27845400 6889 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 6890 #define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
AnnaBridge 172:65be27845400 6891 #define ETH_MACVTR_DOVLTC_Pos (20U)
AnnaBridge 172:65be27845400 6892 #define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6893 #define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
AnnaBridge 172:65be27845400 6894 #define ETH_MACVTR_ERSVLM_Pos (19U)
AnnaBridge 172:65be27845400 6895 #define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6896 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
AnnaBridge 172:65be27845400 6897 #define ETH_MACVTR_ESVL_Pos (18U)
AnnaBridge 172:65be27845400 6898 #define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6899 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
AnnaBridge 172:65be27845400 6900 #define ETH_MACVTR_VTIM_Pos (17U)
AnnaBridge 172:65be27845400 6901 #define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6902 #define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
AnnaBridge 172:65be27845400 6903 #define ETH_MACVTR_ETV_Pos (16U)
AnnaBridge 172:65be27845400 6904 #define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6905 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
AnnaBridge 172:65be27845400 6906 #define ETH_MACVTR_VL_Pos (0U)
AnnaBridge 172:65be27845400 6907 #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6908 #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
AnnaBridge 172:65be27845400 6909 #define ETH_MACVTR_VL_UP_Pos (13U)
AnnaBridge 172:65be27845400 6910 #define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 6911 #define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
AnnaBridge 172:65be27845400 6912 #define ETH_MACVTR_VL_CFIDEI_Pos (12U)
AnnaBridge 172:65be27845400 6913 #define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6914 #define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
AnnaBridge 172:65be27845400 6915 #define ETH_MACVTR_VL_VID_Pos (0U)
AnnaBridge 172:65be27845400 6916 #define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 6917 #define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
AnnaBridge 172:65be27845400 6918
AnnaBridge 172:65be27845400 6919 /* Bit definition for Ethernet MAC VLAN Hash Table Register */
AnnaBridge 172:65be27845400 6920 #define ETH_MACVHTR_VLHT_Pos (0U)
AnnaBridge 172:65be27845400 6921 #define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6922 #define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
AnnaBridge 172:65be27845400 6923
AnnaBridge 172:65be27845400 6924 /* Bit definition for Ethernet MAC VLAN Incl Register */
AnnaBridge 172:65be27845400 6925 #define ETH_MACVIR_VLTI_Pos (20U)
AnnaBridge 172:65be27845400 6926 #define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6927 #define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
AnnaBridge 172:65be27845400 6928 #define ETH_MACVIR_CSVL_Pos (19U)
AnnaBridge 172:65be27845400 6929 #define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6930 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
AnnaBridge 172:65be27845400 6931 #define ETH_MACVIR_VLP_Pos (18U)
AnnaBridge 172:65be27845400 6932 #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6933 #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
AnnaBridge 172:65be27845400 6934 #define ETH_MACVIR_VLC_Pos (16U)
AnnaBridge 172:65be27845400 6935 #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6936 #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
AnnaBridge 172:65be27845400 6937 #define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
AnnaBridge 172:65be27845400 6938 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
AnnaBridge 172:65be27845400 6939 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6940 #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
AnnaBridge 172:65be27845400 6941 #define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
AnnaBridge 172:65be27845400 6942 #define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6943 #define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
AnnaBridge 172:65be27845400 6944 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
AnnaBridge 172:65be27845400 6945 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6946 #define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
AnnaBridge 172:65be27845400 6947 #define ETH_MACVIR_VLT_Pos (0U)
AnnaBridge 172:65be27845400 6948 #define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6949 #define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
AnnaBridge 172:65be27845400 6950 #define ETH_MACVIR_VLT_UP_Pos (13U)
AnnaBridge 172:65be27845400 6951 #define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 6952 #define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
AnnaBridge 172:65be27845400 6953 #define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
AnnaBridge 172:65be27845400 6954 #define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6955 #define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
AnnaBridge 172:65be27845400 6956 #define ETH_MACVIR_VLT_VID_Pos (0U)
AnnaBridge 172:65be27845400 6957 #define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 6958 #define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
AnnaBridge 172:65be27845400 6959
AnnaBridge 172:65be27845400 6960 /* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
AnnaBridge 172:65be27845400 6961 #define ETH_MACIVIR_VLTI_Pos (20U)
AnnaBridge 172:65be27845400 6962 #define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 6963 #define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
AnnaBridge 172:65be27845400 6964 #define ETH_MACIVIR_CSVL_Pos (19U)
AnnaBridge 172:65be27845400 6965 #define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 6966 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
AnnaBridge 172:65be27845400 6967 #define ETH_MACIVIR_VLP_Pos (18U)
AnnaBridge 172:65be27845400 6968 #define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 6969 #define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
AnnaBridge 172:65be27845400 6970 #define ETH_MACIVIR_VLC_Pos (16U)
AnnaBridge 172:65be27845400 6971 #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6972 #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
AnnaBridge 172:65be27845400 6973 #define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
AnnaBridge 172:65be27845400 6974 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
AnnaBridge 172:65be27845400 6975 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 6976 #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
AnnaBridge 172:65be27845400 6977 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
AnnaBridge 172:65be27845400 6978 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 6979 #define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
AnnaBridge 172:65be27845400 6980 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
AnnaBridge 172:65be27845400 6981 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 6982 #define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
AnnaBridge 172:65be27845400 6983 #define ETH_MACIVIR_VLT_Pos (0U)
AnnaBridge 172:65be27845400 6984 #define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 6985 #define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
AnnaBridge 172:65be27845400 6986 #define ETH_MACIVIR_VLT_UP_Pos (13U)
AnnaBridge 172:65be27845400 6987 #define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 6988 #define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
AnnaBridge 172:65be27845400 6989 #define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
AnnaBridge 172:65be27845400 6990 #define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 6991 #define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
AnnaBridge 172:65be27845400 6992 #define ETH_MACIVIR_VLT_VID_Pos (0U)
AnnaBridge 172:65be27845400 6993 #define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 6994 #define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
AnnaBridge 172:65be27845400 6995
AnnaBridge 172:65be27845400 6996 /* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
AnnaBridge 172:65be27845400 6997 #define ETH_MACTFCR_PT_Pos (16U)
AnnaBridge 172:65be27845400 6998 #define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 6999 #define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
AnnaBridge 172:65be27845400 7000 #define ETH_MACTFCR_DZPQ_Pos (7U)
AnnaBridge 172:65be27845400 7001 #define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7002 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
AnnaBridge 172:65be27845400 7003 #define ETH_MACTFCR_PLT_Pos (4U)
AnnaBridge 172:65be27845400 7004 #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 7005 #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
AnnaBridge 172:65be27845400 7006 #define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
AnnaBridge 172:65be27845400 7007 #define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
AnnaBridge 172:65be27845400 7008 #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7009 #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
AnnaBridge 172:65be27845400 7010 #define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
AnnaBridge 172:65be27845400 7011 #define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7012 #define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
AnnaBridge 172:65be27845400 7013 #define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
AnnaBridge 172:65be27845400 7014 #define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 7015 #define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
AnnaBridge 172:65be27845400 7016 #define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
AnnaBridge 172:65be27845400 7017 #define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7018 #define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
AnnaBridge 172:65be27845400 7019 #define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
AnnaBridge 172:65be27845400 7020 #define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
AnnaBridge 172:65be27845400 7021 #define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
AnnaBridge 172:65be27845400 7022 #define ETH_MACTFCR_TFE_Pos (1U)
AnnaBridge 172:65be27845400 7023 #define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7024 #define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
AnnaBridge 172:65be27845400 7025 #define ETH_MACTFCR_FCB_Pos (0U)
AnnaBridge 172:65be27845400 7026 #define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7027 #define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
AnnaBridge 172:65be27845400 7028
AnnaBridge 172:65be27845400 7029 /* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
AnnaBridge 172:65be27845400 7030 #define ETH_MACRFCR_UP_Pos (1U)
AnnaBridge 172:65be27845400 7031 #define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7032 #define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
AnnaBridge 172:65be27845400 7033 #define ETH_MACRFCR_RFE_Pos (0U)
AnnaBridge 172:65be27845400 7034 #define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7035 #define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
AnnaBridge 172:65be27845400 7036
AnnaBridge 172:65be27845400 7037 /* Bit definition for Ethernet MAC Interrupt Status Register */
AnnaBridge 172:65be27845400 7038 #define ETH_MACISR_RXSTSIS_Pos (14U)
AnnaBridge 172:65be27845400 7039 #define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7040 #define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
AnnaBridge 172:65be27845400 7041 #define ETH_MACISR_TXSTSIS_Pos (13U)
AnnaBridge 172:65be27845400 7042 #define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7043 #define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
AnnaBridge 172:65be27845400 7044 #define ETH_MACISR_TSIS_Pos (12U)
AnnaBridge 172:65be27845400 7045 #define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7046 #define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
AnnaBridge 172:65be27845400 7047 #define ETH_MACISR_MMCTXIS_Pos (10U)
AnnaBridge 172:65be27845400 7048 #define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7049 #define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
AnnaBridge 172:65be27845400 7050 #define ETH_MACISR_MMCRXIS_Pos (9U)
AnnaBridge 172:65be27845400 7051 #define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7052 #define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
AnnaBridge 172:65be27845400 7053 #define ETH_MACISR_MMCIS_Pos (8U)
AnnaBridge 172:65be27845400 7054 #define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7055 #define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
AnnaBridge 172:65be27845400 7056 #define ETH_MACISR_LPIIS_Pos (5U)
AnnaBridge 172:65be27845400 7057 #define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7058 #define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
AnnaBridge 172:65be27845400 7059 #define ETH_MACISR_PMTIS_Pos (4U)
AnnaBridge 172:65be27845400 7060 #define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7061 #define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
AnnaBridge 172:65be27845400 7062 #define ETH_MACISR_PHYIS_Pos (3U)
AnnaBridge 172:65be27845400 7063 #define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7064 #define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
AnnaBridge 172:65be27845400 7065
AnnaBridge 172:65be27845400 7066 /* Bit definition for Ethernet MAC Interrupt Enable Register */
AnnaBridge 172:65be27845400 7067 #define ETH_MACIER_RXSTSIE_Pos (14U)
AnnaBridge 172:65be27845400 7068 #define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7069 #define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
AnnaBridge 172:65be27845400 7070 #define ETH_MACIER_TXSTSIE_Pos (13U)
AnnaBridge 172:65be27845400 7071 #define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7072 #define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
AnnaBridge 172:65be27845400 7073 #define ETH_MACIER_TSIE_Pos (12U)
AnnaBridge 172:65be27845400 7074 #define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7075 #define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
AnnaBridge 172:65be27845400 7076 #define ETH_MACIER_LPIIE_Pos (5U)
AnnaBridge 172:65be27845400 7077 #define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7078 #define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
AnnaBridge 172:65be27845400 7079 #define ETH_MACIER_PMTIE_Pos (4U)
AnnaBridge 172:65be27845400 7080 #define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7081 #define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
AnnaBridge 172:65be27845400 7082 #define ETH_MACIER_PHYIE_Pos (3U)
AnnaBridge 172:65be27845400 7083 #define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7084 #define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
AnnaBridge 172:65be27845400 7085
AnnaBridge 172:65be27845400 7086 /* Bit definition for Ethernet MAC Rx Tx Status Register */
AnnaBridge 172:65be27845400 7087 #define ETH_MACRXTXSR_RWT_Pos (8U)
AnnaBridge 172:65be27845400 7088 #define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7089 #define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
AnnaBridge 172:65be27845400 7090 #define ETH_MACRXTXSR_EXCOL_Pos (5U)
AnnaBridge 172:65be27845400 7091 #define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7092 #define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
AnnaBridge 172:65be27845400 7093 #define ETH_MACRXTXSR_LCOL_Pos (4U)
AnnaBridge 172:65be27845400 7094 #define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7095 #define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
AnnaBridge 172:65be27845400 7096 #define ETH_MACRXTXSR_EXDEF_Pos (3U)
AnnaBridge 172:65be27845400 7097 #define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7098 #define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
AnnaBridge 172:65be27845400 7099 #define ETH_MACRXTXSR_LCARR_Pos (2U)
AnnaBridge 172:65be27845400 7100 #define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7101 #define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
AnnaBridge 172:65be27845400 7102 #define ETH_MACRXTXSR_NCARR_Pos (1U)
AnnaBridge 172:65be27845400 7103 #define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7104 #define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
AnnaBridge 172:65be27845400 7105 #define ETH_MACRXTXSR_TJT_Pos (0U)
AnnaBridge 172:65be27845400 7106 #define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7107 #define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
AnnaBridge 172:65be27845400 7108
AnnaBridge 172:65be27845400 7109 /* Bit definition for Ethernet MAC PMT Control Status Register */
AnnaBridge 172:65be27845400 7110 #define ETH_MACPCSR_RWKFILTRST_Pos (31U)
AnnaBridge 172:65be27845400 7111 #define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7112 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
AnnaBridge 172:65be27845400 7113 #define ETH_MACPCSR_RWKPTR_Pos (24U)
AnnaBridge 172:65be27845400 7114 #define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
AnnaBridge 172:65be27845400 7115 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
AnnaBridge 172:65be27845400 7116 #define ETH_MACPCSR_RWKPFE_Pos (10U)
AnnaBridge 172:65be27845400 7117 #define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7118 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
AnnaBridge 172:65be27845400 7119 #define ETH_MACPCSR_GLBLUCAST_Pos (9U)
AnnaBridge 172:65be27845400 7120 #define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7121 #define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
AnnaBridge 172:65be27845400 7122 #define ETH_MACPCSR_RWKPRCVD_Pos (6U)
AnnaBridge 172:65be27845400 7123 #define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7124 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
AnnaBridge 172:65be27845400 7125 #define ETH_MACPCSR_MGKPRCVD_Pos (5U)
AnnaBridge 172:65be27845400 7126 #define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7127 #define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
AnnaBridge 172:65be27845400 7128 #define ETH_MACPCSR_RWKPKTEN_Pos (2U)
AnnaBridge 172:65be27845400 7129 #define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7130 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
AnnaBridge 172:65be27845400 7131 #define ETH_MACPCSR_MGKPKTEN_Pos (1U)
AnnaBridge 172:65be27845400 7132 #define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7133 #define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
AnnaBridge 172:65be27845400 7134 #define ETH_MACPCSR_PWRDWN_Pos (0U)
AnnaBridge 172:65be27845400 7135 #define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7136 #define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
AnnaBridge 172:65be27845400 7137
AnnaBridge 172:65be27845400 7138 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
AnnaBridge 172:65be27845400 7139 #define ETH_MACRWUPFR_D_Pos (0U)
AnnaBridge 172:65be27845400 7140 #define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7141 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
AnnaBridge 172:65be27845400 7142
AnnaBridge 172:65be27845400 7143 /* Bit definition for Ethernet MAC LPI Control Status Register */
AnnaBridge 172:65be27845400 7144 #define ETH_MACLCSR_LPITCSE_Pos (21U)
AnnaBridge 172:65be27845400 7145 #define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7146 #define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
AnnaBridge 172:65be27845400 7147 #define ETH_MACLCSR_LPITE_Pos (20U)
AnnaBridge 172:65be27845400 7148 #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7149 #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
AnnaBridge 172:65be27845400 7150 #define ETH_MACLCSR_LPITXA_Pos (19U)
AnnaBridge 172:65be27845400 7151 #define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7152 #define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
AnnaBridge 172:65be27845400 7153 #define ETH_MACLCSR_PLS_Pos (17U)
AnnaBridge 172:65be27845400 7154 #define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7155 #define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
AnnaBridge 172:65be27845400 7156 #define ETH_MACLCSR_LPIEN_Pos (16U)
AnnaBridge 172:65be27845400 7157 #define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7158 #define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
AnnaBridge 172:65be27845400 7159 #define ETH_MACLCSR_RLPIST_Pos (9U)
AnnaBridge 172:65be27845400 7160 #define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7161 #define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
AnnaBridge 172:65be27845400 7162 #define ETH_MACLCSR_TLPIST_Pos (8U)
AnnaBridge 172:65be27845400 7163 #define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7164 #define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
AnnaBridge 172:65be27845400 7165 #define ETH_MACLCSR_RLPIEX_Pos (3U)
AnnaBridge 172:65be27845400 7166 #define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7167 #define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
AnnaBridge 172:65be27845400 7168 #define ETH_MACLCSR_RLPIEN_Pos (2U)
AnnaBridge 172:65be27845400 7169 #define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7170 #define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
AnnaBridge 172:65be27845400 7171 #define ETH_MACLCSR_TLPIEX_Pos (1U)
AnnaBridge 172:65be27845400 7172 #define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7173 #define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
AnnaBridge 172:65be27845400 7174 #define ETH_MACLCSR_TLPIEN_Pos (0U)
AnnaBridge 172:65be27845400 7175 #define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7176 #define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
AnnaBridge 172:65be27845400 7177
AnnaBridge 172:65be27845400 7178 /* Bit definition for Ethernet MAC LPI Timers Control Register */
AnnaBridge 172:65be27845400 7179 #define ETH_MACLTCR_LST_Pos (16U)
AnnaBridge 172:65be27845400 7180 #define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
AnnaBridge 172:65be27845400 7181 #define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
AnnaBridge 172:65be27845400 7182 #define ETH_MACLTCR_TWT_Pos (0U)
AnnaBridge 172:65be27845400 7183 #define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7184 #define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
AnnaBridge 172:65be27845400 7185
AnnaBridge 172:65be27845400 7186 /* Bit definition for Ethernet MAC LPI Entry Timer Register */
AnnaBridge 172:65be27845400 7187 #define ETH_MACLETR_LPIET_Pos (0U)
AnnaBridge 172:65be27845400 7188 #define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
AnnaBridge 172:65be27845400 7189 #define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
AnnaBridge 172:65be27845400 7190
AnnaBridge 172:65be27845400 7191 /* Bit definition for Ethernet MAC 1US Tic Counter Register */
AnnaBridge 172:65be27845400 7192 #define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
AnnaBridge 172:65be27845400 7193 #define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 7194 #define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
AnnaBridge 172:65be27845400 7195
AnnaBridge 172:65be27845400 7196 /* Bit definition for Ethernet MAC Version Register */
AnnaBridge 172:65be27845400 7197 #define ETH_MACVR_USERVER_Pos (8U)
AnnaBridge 172:65be27845400 7198 #define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7199 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
AnnaBridge 172:65be27845400 7200 #define ETH_MACVR_SNPSVER_Pos (0U)
AnnaBridge 172:65be27845400 7201 #define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 7202 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
AnnaBridge 172:65be27845400 7203
AnnaBridge 172:65be27845400 7204 /* Bit definition for Ethernet MAC Debug Register */
AnnaBridge 172:65be27845400 7205 #define ETH_MACDR_TFCSTS_Pos (17U)
AnnaBridge 172:65be27845400 7206 #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 7207 #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
AnnaBridge 172:65be27845400 7208 #define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
AnnaBridge 172:65be27845400 7209 #define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
AnnaBridge 172:65be27845400 7210 #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7211 #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
AnnaBridge 172:65be27845400 7212 #define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
AnnaBridge 172:65be27845400 7213 #define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7214 #define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
AnnaBridge 172:65be27845400 7215 #define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
AnnaBridge 172:65be27845400 7216 #define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 7217 #define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
AnnaBridge 172:65be27845400 7218 #define ETH_MACDR_TPESTS_Pos (16U)
AnnaBridge 172:65be27845400 7219 #define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7220 #define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
AnnaBridge 172:65be27845400 7221 #define ETH_MACDR_RFCFCSTS_Pos (1U)
AnnaBridge 172:65be27845400 7222 #define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 7223 #define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
AnnaBridge 172:65be27845400 7224 #define ETH_MACDR_RPESTS_Pos (0U)
AnnaBridge 172:65be27845400 7225 #define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7226 #define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
AnnaBridge 172:65be27845400 7227
AnnaBridge 172:65be27845400 7228 /* Bit definition for Ethernet MAC HW Feature0 Register */
AnnaBridge 172:65be27845400 7229 #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
AnnaBridge 172:65be27845400 7230 #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 7231 #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
AnnaBridge 172:65be27845400 7232 #define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
AnnaBridge 172:65be27845400 7233 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
AnnaBridge 172:65be27845400 7234 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 7235 #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
AnnaBridge 172:65be27845400 7236 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
AnnaBridge 172:65be27845400 7237 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 7238 #define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
AnnaBridge 172:65be27845400 7239 #define ETH_MACHWF0R_SAVLANINS_Pos (27U)
AnnaBridge 172:65be27845400 7240 #define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7241 #define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
AnnaBridge 172:65be27845400 7242 #define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
AnnaBridge 172:65be27845400 7243 #define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
AnnaBridge 172:65be27845400 7244 #define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
AnnaBridge 172:65be27845400 7245 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
AnnaBridge 172:65be27845400 7246 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 7247 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
AnnaBridge 172:65be27845400 7248 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
AnnaBridge 172:65be27845400 7249 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7250 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
AnnaBridge 172:65be27845400 7251 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
AnnaBridge 172:65be27845400 7252 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
AnnaBridge 172:65be27845400 7253 #define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
AnnaBridge 172:65be27845400 7254 #define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
AnnaBridge 172:65be27845400 7255 #define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7256 #define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
AnnaBridge 172:65be27845400 7257 #define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
AnnaBridge 172:65be27845400 7258 #define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 7259 #define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
AnnaBridge 172:65be27845400 7260 #define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
AnnaBridge 172:65be27845400 7261 #define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
AnnaBridge 172:65be27845400 7262 #define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
AnnaBridge 172:65be27845400 7263 #define ETH_MACHWF0R_RXCOESEL_Pos (16U)
AnnaBridge 172:65be27845400 7264 #define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7265 #define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
AnnaBridge 172:65be27845400 7266 #define ETH_MACHWF0R_TXCOESEL_Pos (14U)
AnnaBridge 172:65be27845400 7267 #define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7268 #define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
AnnaBridge 172:65be27845400 7269 #define ETH_MACHWF0R_EEESEL_Pos (13U)
AnnaBridge 172:65be27845400 7270 #define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7271 #define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
AnnaBridge 172:65be27845400 7272 #define ETH_MACHWF0R_TSSEL_Pos (12U)
AnnaBridge 172:65be27845400 7273 #define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7274 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
AnnaBridge 172:65be27845400 7275 #define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
AnnaBridge 172:65be27845400 7276 #define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7277 #define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
AnnaBridge 172:65be27845400 7278 #define ETH_MACHWF0R_MMCSEL_Pos (8U)
AnnaBridge 172:65be27845400 7279 #define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7280 #define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
AnnaBridge 172:65be27845400 7281 #define ETH_MACHWF0R_MGKSEL_Pos (7U)
AnnaBridge 172:65be27845400 7282 #define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7283 #define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
AnnaBridge 172:65be27845400 7284 #define ETH_MACHWF0R_RWKSEL_Pos (6U)
AnnaBridge 172:65be27845400 7285 #define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7286 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
AnnaBridge 172:65be27845400 7287 #define ETH_MACHWF0R_SMASEL_Pos (5U)
AnnaBridge 172:65be27845400 7288 #define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7289 #define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
AnnaBridge 172:65be27845400 7290 #define ETH_MACHWF0R_VLHASH_Pos (4U)
AnnaBridge 172:65be27845400 7291 #define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7292 #define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
AnnaBridge 172:65be27845400 7293 #define ETH_MACHWF0R_PCSSEL_Pos (3U)
AnnaBridge 172:65be27845400 7294 #define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7295 #define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
AnnaBridge 172:65be27845400 7296 #define ETH_MACHWF0R_HDSEL_Pos (2U)
AnnaBridge 172:65be27845400 7297 #define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7298 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
AnnaBridge 172:65be27845400 7299 #define ETH_MACHWF0R_GMIISEL_Pos (1U)
AnnaBridge 172:65be27845400 7300 #define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7301 #define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
AnnaBridge 172:65be27845400 7302 #define ETH_MACHWF0R_MIISEL_Pos (0U)
AnnaBridge 172:65be27845400 7303 #define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7304 #define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
AnnaBridge 172:65be27845400 7305
AnnaBridge 172:65be27845400 7306 /* Bit definition for Ethernet MAC HW Feature1 Register */
AnnaBridge 172:65be27845400 7307 #define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
AnnaBridge 172:65be27845400 7308 #define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
AnnaBridge 172:65be27845400 7309 #define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
AnnaBridge 172:65be27845400 7310 #define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
AnnaBridge 172:65be27845400 7311 #define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 7312 #define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
AnnaBridge 172:65be27845400 7313 #define ETH_MACHWF1R_AVSEL_Pos (20U)
AnnaBridge 172:65be27845400 7314 #define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7315 #define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
AnnaBridge 172:65be27845400 7316 #define ETH_MACHWF1R_DBGMEMA_Pos (19U)
AnnaBridge 172:65be27845400 7317 #define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7318 #define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
AnnaBridge 172:65be27845400 7319 #define ETH_MACHWF1R_TSOEN_Pos (18U)
AnnaBridge 172:65be27845400 7320 #define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7321 #define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
AnnaBridge 172:65be27845400 7322 #define ETH_MACHWF1R_SPHEN_Pos (17U)
AnnaBridge 172:65be27845400 7323 #define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7324 #define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
AnnaBridge 172:65be27845400 7325 #define ETH_MACHWF1R_DCBEN_Pos (16U)
AnnaBridge 172:65be27845400 7326 #define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7327 #define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
AnnaBridge 172:65be27845400 7328 #define ETH_MACHWF1R_ADDR64_Pos (14U)
AnnaBridge 172:65be27845400 7329 #define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 7330 #define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
AnnaBridge 172:65be27845400 7331 #define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 7332 #define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7333 #define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7334 #define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
AnnaBridge 172:65be27845400 7335 #define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7336 #define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
AnnaBridge 172:65be27845400 7337 #define ETH_MACHWF1R_PTOEN_Pos (12U)
AnnaBridge 172:65be27845400 7338 #define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7339 #define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
AnnaBridge 172:65be27845400 7340 #define ETH_MACHWF1R_OSTEN_Pos (11U)
AnnaBridge 172:65be27845400 7341 #define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7342 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
AnnaBridge 172:65be27845400 7343 #define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
AnnaBridge 172:65be27845400 7344 #define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 7345 #define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
AnnaBridge 172:65be27845400 7346 #define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
AnnaBridge 172:65be27845400 7347 #define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 7348 #define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
AnnaBridge 172:65be27845400 7349
AnnaBridge 172:65be27845400 7350 /* Bit definition for Ethernet MAC HW Feature2 Register */
AnnaBridge 172:65be27845400 7351 #define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
AnnaBridge 172:65be27845400 7352 #define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 7353 #define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
AnnaBridge 172:65be27845400 7354 #define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
AnnaBridge 172:65be27845400 7355 #define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 7356 #define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
AnnaBridge 172:65be27845400 7357 #define ETH_MACHWF2R_TXCHCNT_Pos (18U)
AnnaBridge 172:65be27845400 7358 #define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
AnnaBridge 172:65be27845400 7359 #define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
AnnaBridge 172:65be27845400 7360 #define ETH_MACHWF2R_RXCHCNT_Pos (13U)
AnnaBridge 172:65be27845400 7361 #define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 7362 #define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
AnnaBridge 172:65be27845400 7363 #define ETH_MACHWF2R_TXQCNT_Pos (6U)
AnnaBridge 172:65be27845400 7364 #define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
AnnaBridge 172:65be27845400 7365 #define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
AnnaBridge 172:65be27845400 7366 #define ETH_MACHWF2R_RXQCNT_Pos (0U)
AnnaBridge 172:65be27845400 7367 #define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7368 #define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
AnnaBridge 172:65be27845400 7369
AnnaBridge 172:65be27845400 7370 /* Bit definition for Ethernet MAC MDIO Address Register */
AnnaBridge 172:65be27845400 7371 #define ETH_MACMDIOAR_PSE_Pos (27U)
AnnaBridge 172:65be27845400 7372 #define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7373 #define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
AnnaBridge 172:65be27845400 7374 #define ETH_MACMDIOAR_BTB_Pos (26U)
AnnaBridge 172:65be27845400 7375 #define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7376 #define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
AnnaBridge 172:65be27845400 7377 #define ETH_MACMDIOAR_PA_Pos (21U)
AnnaBridge 172:65be27845400 7378 #define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
AnnaBridge 172:65be27845400 7379 #define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
AnnaBridge 172:65be27845400 7380 #define ETH_MACMDIOAR_RDA_Pos (16U)
AnnaBridge 172:65be27845400 7381 #define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 7382 #define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
AnnaBridge 172:65be27845400 7383 #define ETH_MACMDIOAR_NTC_Pos (12U)
AnnaBridge 172:65be27845400 7384 #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 7385 #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
AnnaBridge 172:65be27845400 7386 #define ETH_MACMDIOAR_CR_Pos (8U)
AnnaBridge 172:65be27845400 7387 #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 7388 #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
AnnaBridge 172:65be27845400 7389 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
AnnaBridge 172:65be27845400 7390 #define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
AnnaBridge 172:65be27845400 7391 #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7392 #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
AnnaBridge 172:65be27845400 7393 #define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
AnnaBridge 172:65be27845400 7394 #define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7395 #define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
AnnaBridge 172:65be27845400 7396 #define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
AnnaBridge 172:65be27845400 7397 #define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 7398 #define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
AnnaBridge 172:65be27845400 7399 #define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
AnnaBridge 172:65be27845400 7400 #define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7401 #define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
AnnaBridge 172:65be27845400 7402 #define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
AnnaBridge 172:65be27845400 7403 #define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
AnnaBridge 172:65be27845400 7404 #define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
AnnaBridge 172:65be27845400 7405 #define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
AnnaBridge 172:65be27845400 7406 #define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7407 #define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7408 #define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
AnnaBridge 172:65be27845400 7409 #define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
AnnaBridge 172:65be27845400 7410 #define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7411 #define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
AnnaBridge 172:65be27845400 7412 #define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
AnnaBridge 172:65be27845400 7413 #define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7414 #define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
AnnaBridge 172:65be27845400 7415 #define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
AnnaBridge 172:65be27845400 7416 #define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7417 #define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
AnnaBridge 172:65be27845400 7418 #define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 7419 #define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7420 #define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
AnnaBridge 172:65be27845400 7421 #define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
AnnaBridge 172:65be27845400 7422 #define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7423 #define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
AnnaBridge 172:65be27845400 7424 #define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
AnnaBridge 172:65be27845400 7425 #define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7426 #define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
AnnaBridge 172:65be27845400 7427 #define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 7428 #define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
AnnaBridge 172:65be27845400 7429 #define ETH_MACMDIOAR_SKAP_Pos (4U)
AnnaBridge 172:65be27845400 7430 #define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7431 #define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
AnnaBridge 172:65be27845400 7432 #define ETH_MACMDIOAR_MOC_Pos (2U)
AnnaBridge 172:65be27845400 7433 #define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 7434 #define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
AnnaBridge 172:65be27845400 7435 #define ETH_MACMDIOAR_MOC_WR_Pos (2U)
AnnaBridge 172:65be27845400 7436 #define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7437 #define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
AnnaBridge 172:65be27845400 7438 #define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
AnnaBridge 172:65be27845400 7439 #define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7440 #define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
AnnaBridge 172:65be27845400 7441 #define ETH_MACMDIOAR_MOC_RD_Pos (2U)
AnnaBridge 172:65be27845400 7442 #define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 7443 #define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
AnnaBridge 172:65be27845400 7444 #define ETH_MACMDIOAR_C45E_Pos (1U)
AnnaBridge 172:65be27845400 7445 #define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7446 #define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
AnnaBridge 172:65be27845400 7447 #define ETH_MACMDIOAR_MB_Pos (0U)
AnnaBridge 172:65be27845400 7448 #define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7449 #define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
AnnaBridge 172:65be27845400 7450
AnnaBridge 172:65be27845400 7451 /* Bit definition for Ethernet MAC MDIO Data Register */
AnnaBridge 172:65be27845400 7452 #define ETH_MACMDIODR_RA_Pos (16U)
AnnaBridge 172:65be27845400 7453 #define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 7454 #define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
AnnaBridge 172:65be27845400 7455 #define ETH_MACMDIODR_MD_Pos (0U)
AnnaBridge 172:65be27845400 7456 #define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7457 #define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
AnnaBridge 172:65be27845400 7458
AnnaBridge 172:65be27845400 7459 /* Bit definition for Ethernet ARP Address Register */
AnnaBridge 172:65be27845400 7460 #define ETH_MACARPAR_ARPPA_Pos (0U)
AnnaBridge 172:65be27845400 7461 #define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7462 #define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
AnnaBridge 172:65be27845400 7463
AnnaBridge 172:65be27845400 7464 /* Bit definition for Ethernet MAC Address 0 High Register */
AnnaBridge 172:65be27845400 7465 #define ETH_MACA0HR_AE_Pos (31U)
AnnaBridge 172:65be27845400 7466 #define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7467 #define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
AnnaBridge 172:65be27845400 7468 #define ETH_MACA0HR_ADDRHI_Pos (0U)
AnnaBridge 172:65be27845400 7469 #define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7470 #define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
AnnaBridge 172:65be27845400 7471
AnnaBridge 172:65be27845400 7472 /* Bit definition for Ethernet MAC Address 0 Low Register */
AnnaBridge 172:65be27845400 7473 #define ETH_MACA0LR_ADDRLO_Pos (0U)
AnnaBridge 172:65be27845400 7474 #define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7475 #define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
AnnaBridge 172:65be27845400 7476
AnnaBridge 172:65be27845400 7477 /* Bit definition for Ethernet MAC Address 1 High Register */
AnnaBridge 172:65be27845400 7478 #define ETH_MACA1HR_AE_Pos (31U)
AnnaBridge 172:65be27845400 7479 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7480 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
AnnaBridge 172:65be27845400 7481 #define ETH_MACA1HR_SA_Pos (30U)
AnnaBridge 172:65be27845400 7482 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 7483 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
AnnaBridge 172:65be27845400 7484 #define ETH_MACA1HR_MBC_Pos (24U)
AnnaBridge 172:65be27845400 7485 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 7486 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
AnnaBridge 172:65be27845400 7487 #define ETH_MACA1HR_ADDRHI_Pos (0U)
AnnaBridge 172:65be27845400 7488 #define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7489 #define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
AnnaBridge 172:65be27845400 7490
AnnaBridge 172:65be27845400 7491 /* Bit definition for Ethernet MAC Address 1 Low Register */
AnnaBridge 172:65be27845400 7492 #define ETH_MACA1LR_ADDRLO_Pos (0U)
AnnaBridge 172:65be27845400 7493 #define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7494 #define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
AnnaBridge 172:65be27845400 7495
AnnaBridge 172:65be27845400 7496 /* Bit definition for Ethernet MAC Address 2 High Register */
AnnaBridge 172:65be27845400 7497 #define ETH_MACA2HR_AE_Pos (31U)
AnnaBridge 172:65be27845400 7498 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7499 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
AnnaBridge 172:65be27845400 7500 #define ETH_MACA2HR_SA_Pos (30U)
AnnaBridge 172:65be27845400 7501 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 7502 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
AnnaBridge 172:65be27845400 7503 #define ETH_MACA2HR_MBC_Pos (24U)
AnnaBridge 172:65be27845400 7504 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 7505 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
AnnaBridge 172:65be27845400 7506 #define ETH_MACA2HR_ADDRHI_Pos (0U)
AnnaBridge 172:65be27845400 7507 #define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7508 #define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
AnnaBridge 172:65be27845400 7509
AnnaBridge 172:65be27845400 7510 /* Bit definition for Ethernet MAC Address 2 Low Register */
AnnaBridge 172:65be27845400 7511 #define ETH_MACA2LR_ADDRLO_Pos (0U)
AnnaBridge 172:65be27845400 7512 #define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7513 #define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
AnnaBridge 172:65be27845400 7514
AnnaBridge 172:65be27845400 7515 /* Bit definition for Ethernet MAC Address 3 High Register */
AnnaBridge 172:65be27845400 7516 #define ETH_MACA3HR_AE_Pos (31U)
AnnaBridge 172:65be27845400 7517 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7518 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
AnnaBridge 172:65be27845400 7519 #define ETH_MACA3HR_SA_Pos (30U)
AnnaBridge 172:65be27845400 7520 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 7521 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
AnnaBridge 172:65be27845400 7522 #define ETH_MACA3HR_MBC_Pos (24U)
AnnaBridge 172:65be27845400 7523 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 7524 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
AnnaBridge 172:65be27845400 7525 #define ETH_MACA3HR_ADDRHI_Pos (0U)
AnnaBridge 172:65be27845400 7526 #define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7527 #define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
AnnaBridge 172:65be27845400 7528
AnnaBridge 172:65be27845400 7529 /* Bit definition for Ethernet MAC Address 3 Low Register */
AnnaBridge 172:65be27845400 7530 #define ETH_MACA3LR_ADDRLO_Pos (0U)
AnnaBridge 172:65be27845400 7531 #define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7532 #define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
AnnaBridge 172:65be27845400 7533
AnnaBridge 172:65be27845400 7534 /* Bit definition for Ethernet MAC Address High Register */
AnnaBridge 172:65be27845400 7535 #define ETH_MACAHR_AE_Pos (31U)
AnnaBridge 172:65be27845400 7536 #define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7537 #define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
AnnaBridge 172:65be27845400 7538 #define ETH_MACAHR_SA_Pos (30U)
AnnaBridge 172:65be27845400 7539 #define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 7540 #define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
AnnaBridge 172:65be27845400 7541 #define ETH_MACAHR_MBC_Pos (24U)
AnnaBridge 172:65be27845400 7542 #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 172:65be27845400 7543 #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
AnnaBridge 172:65be27845400 7544 #define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 172:65be27845400 7545 #define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 172:65be27845400 7546 #define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 172:65be27845400 7547 #define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 172:65be27845400 7548 #define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 172:65be27845400 7549 #define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
AnnaBridge 172:65be27845400 7550 #define ETH_MACAHR_MACAH_Pos (0U)
AnnaBridge 172:65be27845400 7551 #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7552 #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
AnnaBridge 172:65be27845400 7553
AnnaBridge 172:65be27845400 7554 /* Bit definition for Ethernet MAC Address Low Register */
AnnaBridge 172:65be27845400 7555 #define ETH_MACALR_MACAL_Pos (0U)
AnnaBridge 172:65be27845400 7556 #define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7557 #define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
AnnaBridge 172:65be27845400 7558
AnnaBridge 172:65be27845400 7559 /* Bit definition for Ethernet MMC Control Register */
AnnaBridge 172:65be27845400 7560 #define ETH_MMCCR_UCDBC_Pos (8U)
AnnaBridge 172:65be27845400 7561 #define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7562 #define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
AnnaBridge 172:65be27845400 7563 #define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
AnnaBridge 172:65be27845400 7564 #define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7565 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
AnnaBridge 172:65be27845400 7566 #define ETH_MMCCR_CNTPRST_Pos (4U)
AnnaBridge 172:65be27845400 7567 #define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7568 #define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
AnnaBridge 172:65be27845400 7569 #define ETH_MMCCR_CNTFREEZ_Pos (3U)
AnnaBridge 172:65be27845400 7570 #define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7571 #define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
AnnaBridge 172:65be27845400 7572 #define ETH_MMCCR_RSTONRD_Pos (2U)
AnnaBridge 172:65be27845400 7573 #define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7574 #define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
AnnaBridge 172:65be27845400 7575 #define ETH_MMCCR_CNTSTOPRO_Pos (1U)
AnnaBridge 172:65be27845400 7576 #define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7577 #define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
AnnaBridge 172:65be27845400 7578 #define ETH_MMCCR_CNTRST_Pos (0U)
AnnaBridge 172:65be27845400 7579 #define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7580 #define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
AnnaBridge 172:65be27845400 7581
AnnaBridge 172:65be27845400 7582 /* Bit definition for Ethernet MMC Rx Interrupt Register */
AnnaBridge 172:65be27845400 7583 #define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
AnnaBridge 172:65be27845400 7584 #define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7585 #define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
AnnaBridge 172:65be27845400 7586 #define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
AnnaBridge 172:65be27845400 7587 #define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7588 #define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
AnnaBridge 172:65be27845400 7589 #define ETH_MMCRIR_RXUCGPIS_Pos (17U)
AnnaBridge 172:65be27845400 7590 #define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7591 #define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
AnnaBridge 172:65be27845400 7592 #define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
AnnaBridge 172:65be27845400 7593 #define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7594 #define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
AnnaBridge 172:65be27845400 7595 #define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
AnnaBridge 172:65be27845400 7596 #define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7597 #define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
AnnaBridge 172:65be27845400 7598
AnnaBridge 172:65be27845400 7599 /* Bit definition for Ethernet MMC Tx Interrupt Register */
AnnaBridge 172:65be27845400 7600 #define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
AnnaBridge 172:65be27845400 7601 #define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7602 #define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
AnnaBridge 172:65be27845400 7603 #define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
AnnaBridge 172:65be27845400 7604 #define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7605 #define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
AnnaBridge 172:65be27845400 7606 #define ETH_MMCTIR_TXGPKTIS_Pos (21U)
AnnaBridge 172:65be27845400 7607 #define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7608 #define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
AnnaBridge 172:65be27845400 7609 #define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
AnnaBridge 172:65be27845400 7610 #define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7611 #define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
AnnaBridge 172:65be27845400 7612 #define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
AnnaBridge 172:65be27845400 7613 #define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7614 #define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
AnnaBridge 172:65be27845400 7615
AnnaBridge 172:65be27845400 7616 /* Bit definition for Ethernet MMC Rx interrupt Mask register */
AnnaBridge 172:65be27845400 7617 #define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
AnnaBridge 172:65be27845400 7618 #define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7619 #define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
AnnaBridge 172:65be27845400 7620 #define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
AnnaBridge 172:65be27845400 7621 #define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7622 #define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
AnnaBridge 172:65be27845400 7623 #define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
AnnaBridge 172:65be27845400 7624 #define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 7625 #define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
AnnaBridge 172:65be27845400 7626 #define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
AnnaBridge 172:65be27845400 7627 #define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7628 #define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
AnnaBridge 172:65be27845400 7629 #define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
AnnaBridge 172:65be27845400 7630 #define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7631 #define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
AnnaBridge 172:65be27845400 7632
AnnaBridge 172:65be27845400 7633 /* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
AnnaBridge 172:65be27845400 7634 #define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
AnnaBridge 172:65be27845400 7635 #define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 7636 #define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
AnnaBridge 172:65be27845400 7637 #define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
AnnaBridge 172:65be27845400 7638 #define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 7639 #define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
AnnaBridge 172:65be27845400 7640 #define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
AnnaBridge 172:65be27845400 7641 #define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7642 #define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
AnnaBridge 172:65be27845400 7643 #define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
AnnaBridge 172:65be27845400 7644 #define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7645 #define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
AnnaBridge 172:65be27845400 7646 #define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
AnnaBridge 172:65be27845400 7647 #define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7648 #define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
AnnaBridge 172:65be27845400 7649
AnnaBridge 172:65be27845400 7650 /* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
AnnaBridge 172:65be27845400 7651 #define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
AnnaBridge 172:65be27845400 7652 #define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7653 #define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
AnnaBridge 172:65be27845400 7654
AnnaBridge 172:65be27845400 7655 /* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
AnnaBridge 172:65be27845400 7656 #define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
AnnaBridge 172:65be27845400 7657 #define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7658 #define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
AnnaBridge 172:65be27845400 7659
AnnaBridge 172:65be27845400 7660 /* Bit definition for Ethernet MMC Tx Packet Count Good Register */
AnnaBridge 172:65be27845400 7661 #define ETH_MMCTPCGR_TXPKTG_Pos (0U)
AnnaBridge 172:65be27845400 7662 #define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7663 #define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
AnnaBridge 172:65be27845400 7664
AnnaBridge 172:65be27845400 7665 /* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
AnnaBridge 172:65be27845400 7666 #define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
AnnaBridge 172:65be27845400 7667 #define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7668 #define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
AnnaBridge 172:65be27845400 7669
AnnaBridge 172:65be27845400 7670 /* Bit definition for Ethernet MMC Rx alignment error packets register */
AnnaBridge 172:65be27845400 7671 #define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
AnnaBridge 172:65be27845400 7672 #define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7673 #define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
AnnaBridge 172:65be27845400 7674
AnnaBridge 172:65be27845400 7675 /* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
AnnaBridge 172:65be27845400 7676 #define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
AnnaBridge 172:65be27845400 7677 #define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7678 #define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
AnnaBridge 172:65be27845400 7679
AnnaBridge 172:65be27845400 7680 /* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
AnnaBridge 172:65be27845400 7681 #define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
AnnaBridge 172:65be27845400 7682 #define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7683 #define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
AnnaBridge 172:65be27845400 7684
AnnaBridge 172:65be27845400 7685 /* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
AnnaBridge 172:65be27845400 7686 #define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
AnnaBridge 172:65be27845400 7687 #define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7688 #define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
AnnaBridge 172:65be27845400 7689
AnnaBridge 172:65be27845400 7690 /* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
AnnaBridge 172:65be27845400 7691 #define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
AnnaBridge 172:65be27845400 7692 #define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7693 #define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
AnnaBridge 172:65be27845400 7694
AnnaBridge 172:65be27845400 7695 /* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
AnnaBridge 172:65be27845400 7696 #define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
AnnaBridge 172:65be27845400 7697 #define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7698 #define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
AnnaBridge 172:65be27845400 7699
AnnaBridge 172:65be27845400 7700 /* Bit definition for Ethernet MAC L3 L4 Control Register */
AnnaBridge 172:65be27845400 7701 #define ETH_MACL3L4CR_L4DPIM_Pos (21U)
AnnaBridge 172:65be27845400 7702 #define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 7703 #define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
AnnaBridge 172:65be27845400 7704 #define ETH_MACL3L4CR_L4DPM_Pos (20U)
AnnaBridge 172:65be27845400 7705 #define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 7706 #define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
AnnaBridge 172:65be27845400 7707 #define ETH_MACL3L4CR_L4SPIM_Pos (19U)
AnnaBridge 172:65be27845400 7708 #define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7709 #define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
AnnaBridge 172:65be27845400 7710 #define ETH_MACL3L4CR_L4SPM_Pos (18U)
AnnaBridge 172:65be27845400 7711 #define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7712 #define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
AnnaBridge 172:65be27845400 7713 #define ETH_MACL3L4CR_L4PEN_Pos (16U)
AnnaBridge 172:65be27845400 7714 #define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 7715 #define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
AnnaBridge 172:65be27845400 7716 #define ETH_MACL3L4CR_L3HDBM_Pos (11U)
AnnaBridge 172:65be27845400 7717 #define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
AnnaBridge 172:65be27845400 7718 #define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
AnnaBridge 172:65be27845400 7719 #define ETH_MACL3L4CR_L3HSBM_Pos (6U)
AnnaBridge 172:65be27845400 7720 #define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 7721 #define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
AnnaBridge 172:65be27845400 7722 #define ETH_MACL3L4CR_L3DAIM_Pos (5U)
AnnaBridge 172:65be27845400 7723 #define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7724 #define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
AnnaBridge 172:65be27845400 7725 #define ETH_MACL3L4CR_L3DAM_Pos (4U)
AnnaBridge 172:65be27845400 7726 #define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7727 #define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
AnnaBridge 172:65be27845400 7728 #define ETH_MACL3L4CR_L3SAIM_Pos (3U)
AnnaBridge 172:65be27845400 7729 #define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7730 #define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
AnnaBridge 172:65be27845400 7731 #define ETH_MACL3L4CR_L3SAM_Pos (2U)
AnnaBridge 172:65be27845400 7732 #define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7733 #define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
AnnaBridge 172:65be27845400 7734 #define ETH_MACL3L4CR_L3PEN_Pos (0U)
AnnaBridge 172:65be27845400 7735 #define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7736 #define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
AnnaBridge 172:65be27845400 7737
AnnaBridge 172:65be27845400 7738 /* Bit definition for Ethernet MAC L4 Address Register */
AnnaBridge 172:65be27845400 7739 #define ETH_MACL4AR_L4DP_Pos (16U)
AnnaBridge 172:65be27845400 7740 #define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 7741 #define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
AnnaBridge 172:65be27845400 7742 #define ETH_MACL4AR_L4SP_Pos (0U)
AnnaBridge 172:65be27845400 7743 #define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 7744 #define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
AnnaBridge 172:65be27845400 7745
AnnaBridge 172:65be27845400 7746 /* Bit definition for Ethernet MAC L3 Address0 Register */
AnnaBridge 172:65be27845400 7747 #define ETH_MACL3A0R_L3A0_Pos (0U)
AnnaBridge 172:65be27845400 7748 #define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7749 #define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
AnnaBridge 172:65be27845400 7750
AnnaBridge 172:65be27845400 7751 /* Bit definition for Ethernet MAC L4 Address1 Register */
AnnaBridge 172:65be27845400 7752 #define ETH_MACL3A1R_L3A1_Pos (0U)
AnnaBridge 172:65be27845400 7753 #define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7754 #define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
AnnaBridge 172:65be27845400 7755
AnnaBridge 172:65be27845400 7756 /* Bit definition for Ethernet MAC L4 Address2 Register */
AnnaBridge 172:65be27845400 7757 #define ETH_MACL3A2R_L3A2_Pos (0U)
AnnaBridge 172:65be27845400 7758 #define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7759 #define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
AnnaBridge 172:65be27845400 7760
AnnaBridge 172:65be27845400 7761 /* Bit definition for Ethernet MAC L4 Address3 Register */
AnnaBridge 172:65be27845400 7762 #define ETH_MACL3A3R_L3A3_Pos (0U)
AnnaBridge 172:65be27845400 7763 #define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7764 #define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
AnnaBridge 172:65be27845400 7765
AnnaBridge 172:65be27845400 7766 /* Bit definition for Ethernet MAC Timestamp Control Register */
AnnaBridge 172:65be27845400 7767 #define ETH_MACTSCR_TXTSSTSM_Pos (24U)
AnnaBridge 172:65be27845400 7768 #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7769 #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
AnnaBridge 172:65be27845400 7770 #define ETH_MACTSCR_CSC_Pos (19U)
AnnaBridge 172:65be27845400 7771 #define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 7772 #define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
AnnaBridge 172:65be27845400 7773 #define ETH_MACTSCR_TSENMACADDR_Pos (18U)
AnnaBridge 172:65be27845400 7774 #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 7775 #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
AnnaBridge 172:65be27845400 7776 #define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
AnnaBridge 172:65be27845400 7777 #define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 7778 #define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
AnnaBridge 172:65be27845400 7779 #define ETH_MACTSCR_TSMSTRENA_Pos (15U)
AnnaBridge 172:65be27845400 7780 #define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7781 #define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
AnnaBridge 172:65be27845400 7782 #define ETH_MACTSCR_TSEVNTENA_Pos (14U)
AnnaBridge 172:65be27845400 7783 #define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 7784 #define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
AnnaBridge 172:65be27845400 7785 #define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
AnnaBridge 172:65be27845400 7786 #define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 7787 #define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
AnnaBridge 172:65be27845400 7788 #define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
AnnaBridge 172:65be27845400 7789 #define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 7790 #define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
AnnaBridge 172:65be27845400 7791 #define ETH_MACTSCR_TSIPENA_Pos (11U)
AnnaBridge 172:65be27845400 7792 #define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 7793 #define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
AnnaBridge 172:65be27845400 7794 #define ETH_MACTSCR_TSVER2ENA_Pos (10U)
AnnaBridge 172:65be27845400 7795 #define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 7796 #define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
AnnaBridge 172:65be27845400 7797 #define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
AnnaBridge 172:65be27845400 7798 #define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 7799 #define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
AnnaBridge 172:65be27845400 7800 #define ETH_MACTSCR_TSENALL_Pos (8U)
AnnaBridge 172:65be27845400 7801 #define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 7802 #define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
AnnaBridge 172:65be27845400 7803 #define ETH_MACTSCR_TSADDREG_Pos (5U)
AnnaBridge 172:65be27845400 7804 #define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7805 #define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
AnnaBridge 172:65be27845400 7806 #define ETH_MACTSCR_TSUPDT_Pos (3U)
AnnaBridge 172:65be27845400 7807 #define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7808 #define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
AnnaBridge 172:65be27845400 7809 #define ETH_MACTSCR_TSINIT_Pos (2U)
AnnaBridge 172:65be27845400 7810 #define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7811 #define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
AnnaBridge 172:65be27845400 7812 #define ETH_MACTSCR_TSCFUPDT_Pos (1U)
AnnaBridge 172:65be27845400 7813 #define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7814 #define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
AnnaBridge 172:65be27845400 7815 #define ETH_MACTSCR_TSENA_Pos (0U)
AnnaBridge 172:65be27845400 7816 #define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7817 #define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
AnnaBridge 172:65be27845400 7818
AnnaBridge 172:65be27845400 7819 /* Bit definition for Ethernet MAC Sub-second Increment Register */
AnnaBridge 172:65be27845400 7820 #define ETH_MACMACSSIR_SSINC_Pos (16U)
AnnaBridge 172:65be27845400 7821 #define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7822 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
AnnaBridge 172:65be27845400 7823 #define ETH_MACMACSSIR_SNSINC_Pos (8U)
AnnaBridge 172:65be27845400 7824 #define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 7825 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
AnnaBridge 172:65be27845400 7826
AnnaBridge 172:65be27845400 7827 /* Bit definition for Ethernet MAC System Time Seconds Register */
AnnaBridge 172:65be27845400 7828 #define ETH_MACSTSR_TSS_Pos (0U)
AnnaBridge 172:65be27845400 7829 #define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7830 #define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
AnnaBridge 172:65be27845400 7831
AnnaBridge 172:65be27845400 7832 /* Bit definition for Ethernet MAC System Time Nanoseconds Register */
AnnaBridge 172:65be27845400 7833 #define ETH_MACSTNR_TSSS_Pos (0U)
AnnaBridge 172:65be27845400 7834 #define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 172:65be27845400 7835 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
AnnaBridge 172:65be27845400 7836
AnnaBridge 172:65be27845400 7837 /* Bit definition for Ethernet MAC System Time Seconds Update Register */
AnnaBridge 172:65be27845400 7838 #define ETH_MACSTSUR_TSS_Pos (0U)
AnnaBridge 172:65be27845400 7839 #define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7840 #define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
AnnaBridge 172:65be27845400 7841
AnnaBridge 172:65be27845400 7842 /* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
AnnaBridge 172:65be27845400 7843 #define ETH_MACSTNUR_ADDSUB_Pos (31U)
AnnaBridge 172:65be27845400 7844 #define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7845 #define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
AnnaBridge 172:65be27845400 7846 #define ETH_MACSTNUR_TSSS_Pos (0U)
AnnaBridge 172:65be27845400 7847 #define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 172:65be27845400 7848 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
AnnaBridge 172:65be27845400 7849
AnnaBridge 172:65be27845400 7850 /* Bit definition for Ethernet MAC Timestamp Addend Register */
AnnaBridge 172:65be27845400 7851 #define ETH_MACTSAR_TSAR_Pos (0U)
AnnaBridge 172:65be27845400 7852 #define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7853 #define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
AnnaBridge 172:65be27845400 7854
AnnaBridge 172:65be27845400 7855 /* Bit definition for Ethernet MAC Timestamp Status Register */
AnnaBridge 172:65be27845400 7856 #define ETH_MACTSSR_ATSNS_Pos (25U)
AnnaBridge 172:65be27845400 7857 #define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
AnnaBridge 172:65be27845400 7858 #define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
AnnaBridge 172:65be27845400 7859 #define ETH_MACTSSR_ATSSTM_Pos (24U)
AnnaBridge 172:65be27845400 7860 #define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 7861 #define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
AnnaBridge 172:65be27845400 7862 #define ETH_MACTSSR_ATSSTN_Pos (16U)
AnnaBridge 172:65be27845400 7863 #define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 7864 #define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
AnnaBridge 172:65be27845400 7865 #define ETH_MACTSSR_TXTSSIS_Pos (15U)
AnnaBridge 172:65be27845400 7866 #define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 7867 #define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
AnnaBridge 172:65be27845400 7868 #define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
AnnaBridge 172:65be27845400 7869 #define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 7870 #define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
AnnaBridge 172:65be27845400 7871 #define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
AnnaBridge 172:65be27845400 7872 #define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7873 #define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
AnnaBridge 172:65be27845400 7874 #define ETH_MACTSSR_TSTARGT0_Pos (1U)
AnnaBridge 172:65be27845400 7875 #define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7876 #define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
AnnaBridge 172:65be27845400 7877 #define ETH_MACTSSR_TSSOVF_Pos (0U)
AnnaBridge 172:65be27845400 7878 #define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7879 #define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
AnnaBridge 172:65be27845400 7880
AnnaBridge 172:65be27845400 7881 /* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
AnnaBridge 172:65be27845400 7882 #define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
AnnaBridge 172:65be27845400 7883 #define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7884 #define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
AnnaBridge 172:65be27845400 7885 #define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
AnnaBridge 172:65be27845400 7886 #define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 172:65be27845400 7887 #define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
AnnaBridge 172:65be27845400 7888
AnnaBridge 172:65be27845400 7889 /* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
AnnaBridge 172:65be27845400 7890 #define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
AnnaBridge 172:65be27845400 7891 #define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7892 #define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
AnnaBridge 172:65be27845400 7893
AnnaBridge 172:65be27845400 7894 /* Bit definition for Ethernet MAC Auxiliary Control Register*/
AnnaBridge 172:65be27845400 7895 #define ETH_MACACR_ATSEN3_Pos (7U)
AnnaBridge 172:65be27845400 7896 #define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 7897 #define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
AnnaBridge 172:65be27845400 7898 #define ETH_MACACR_ATSEN2_Pos (6U)
AnnaBridge 172:65be27845400 7899 #define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7900 #define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
AnnaBridge 172:65be27845400 7901 #define ETH_MACACR_ATSEN1_Pos (5U)
AnnaBridge 172:65be27845400 7902 #define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7903 #define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
AnnaBridge 172:65be27845400 7904 #define ETH_MACACR_ATSEN0_Pos (4U)
AnnaBridge 172:65be27845400 7905 #define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7906 #define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
AnnaBridge 172:65be27845400 7907 #define ETH_MACACR_ATSFC_Pos (0U)
AnnaBridge 172:65be27845400 7908 #define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7909 #define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
AnnaBridge 172:65be27845400 7910
AnnaBridge 172:65be27845400 7911 /* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
AnnaBridge 172:65be27845400 7912 #define ETH_MACATSNR_AUXTSLO_Pos (0U)
AnnaBridge 172:65be27845400 7913 #define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 172:65be27845400 7914 #define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
AnnaBridge 172:65be27845400 7915
AnnaBridge 172:65be27845400 7916 /* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
AnnaBridge 172:65be27845400 7917 #define ETH_MACATSSR_AUXTSHI_Pos (0U)
AnnaBridge 172:65be27845400 7918 #define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7919 #define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
AnnaBridge 172:65be27845400 7920
AnnaBridge 172:65be27845400 7921 /* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
AnnaBridge 172:65be27845400 7922 #define ETH_MACTSIACR_OSTIAC_Pos (0U)
AnnaBridge 172:65be27845400 7923 #define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7924 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
AnnaBridge 172:65be27845400 7925
AnnaBridge 172:65be27845400 7926 /* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
AnnaBridge 172:65be27845400 7927 #define ETH_MACTSEACR_OSTEAC_Pos (0U)
AnnaBridge 172:65be27845400 7928 #define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7929 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
AnnaBridge 172:65be27845400 7930
AnnaBridge 172:65be27845400 7931 /* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
AnnaBridge 172:65be27845400 7932 #define ETH_MACTSICNR_TSIC_Pos (0U)
AnnaBridge 172:65be27845400 7933 #define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7934 #define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
AnnaBridge 172:65be27845400 7935
AnnaBridge 172:65be27845400 7936 /* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
AnnaBridge 172:65be27845400 7937 #define ETH_MACTSECNR_TSEC_Pos (0U)
AnnaBridge 172:65be27845400 7938 #define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7939 #define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
AnnaBridge 172:65be27845400 7940
AnnaBridge 172:65be27845400 7941 /* Bit definition for Ethernet MAC PPS Control Register */
AnnaBridge 172:65be27845400 7942 #define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
AnnaBridge 172:65be27845400 7943 #define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 7944 #define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
AnnaBridge 172:65be27845400 7945 #define ETH_MACPPSCR_PPSEN0_Pos (4U)
AnnaBridge 172:65be27845400 7946 #define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7947 #define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
AnnaBridge 172:65be27845400 7948 #define ETH_MACPPSCR_PPSCTRL_Pos (0U)
AnnaBridge 172:65be27845400 7949 #define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 7950 #define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
AnnaBridge 172:65be27845400 7951
AnnaBridge 172:65be27845400 7952 /* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
AnnaBridge 172:65be27845400 7953 #define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
AnnaBridge 172:65be27845400 7954 #define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7955 #define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
AnnaBridge 172:65be27845400 7956
AnnaBridge 172:65be27845400 7957 /* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
AnnaBridge 172:65be27845400 7958 #define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
AnnaBridge 172:65be27845400 7959 #define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 7960 #define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
AnnaBridge 172:65be27845400 7961 #define ETH_MACPPSTTNR_TTSL0_Pos (0U)
AnnaBridge 172:65be27845400 7962 #define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 172:65be27845400 7963 #define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
AnnaBridge 172:65be27845400 7964
AnnaBridge 172:65be27845400 7965 /* Bit definition for Ethernet MAC PPS Interval Register */
AnnaBridge 172:65be27845400 7966 #define ETH_MACPPSIR_PPSINT0_Pos (0U)
AnnaBridge 172:65be27845400 7967 #define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7968 #define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
AnnaBridge 172:65be27845400 7969
AnnaBridge 172:65be27845400 7970 /* Bit definition for Ethernet MAC PPS Width Register */
AnnaBridge 172:65be27845400 7971 #define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
AnnaBridge 172:65be27845400 7972 #define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 7973 #define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
AnnaBridge 172:65be27845400 7974
AnnaBridge 172:65be27845400 7975 /* Bit definition for Ethernet MAC PTP Offload Control Register */
AnnaBridge 172:65be27845400 7976 #define ETH_MACPOCR_DN_Pos (8U)
AnnaBridge 172:65be27845400 7977 #define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 7978 #define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
AnnaBridge 172:65be27845400 7979 #define ETH_MACPOCR_DRRDIS_Pos (6U)
AnnaBridge 172:65be27845400 7980 #define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 7981 #define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
AnnaBridge 172:65be27845400 7982 #define ETH_MACPOCR_APDREQTRIG_Pos (5U)
AnnaBridge 172:65be27845400 7983 #define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 7984 #define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
AnnaBridge 172:65be27845400 7985 #define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
AnnaBridge 172:65be27845400 7986 #define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 7987 #define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
AnnaBridge 172:65be27845400 7988 #define ETH_MACPOCR_APDREQEN_Pos (2U)
AnnaBridge 172:65be27845400 7989 #define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 7990 #define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
AnnaBridge 172:65be27845400 7991 #define ETH_MACPOCR_ASYNCEN_Pos (1U)
AnnaBridge 172:65be27845400 7992 #define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 7993 #define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
AnnaBridge 172:65be27845400 7994 #define ETH_MACPOCR_PTOEN_Pos (0U)
AnnaBridge 172:65be27845400 7995 #define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 7996 #define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
AnnaBridge 172:65be27845400 7997
AnnaBridge 172:65be27845400 7998 /* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
AnnaBridge 172:65be27845400 7999 #define ETH_MACSPI0R_SPI0_Pos (0U)
AnnaBridge 172:65be27845400 8000 #define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8001 #define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
AnnaBridge 172:65be27845400 8002
AnnaBridge 172:65be27845400 8003 /* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
AnnaBridge 172:65be27845400 8004 #define ETH_MACSPI1R_SPI1_Pos (0U)
AnnaBridge 172:65be27845400 8005 #define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8006 #define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
AnnaBridge 172:65be27845400 8007
AnnaBridge 172:65be27845400 8008 /* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
AnnaBridge 172:65be27845400 8009 #define ETH_MACSPI2R_SPI2_Pos (0U)
AnnaBridge 172:65be27845400 8010 #define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 8011 #define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
AnnaBridge 172:65be27845400 8012
AnnaBridge 172:65be27845400 8013 /* Bit definition for Ethernet MAC Log Message Interval Register */
AnnaBridge 172:65be27845400 8014 #define ETH_MACLMIR_LMPDRI_Pos (24U)
AnnaBridge 172:65be27845400 8015 #define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 8016 #define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
AnnaBridge 172:65be27845400 8017 #define ETH_MACLMIR_DRSYNCR_Pos (8U)
AnnaBridge 172:65be27845400 8018 #define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 8019 #define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
AnnaBridge 172:65be27845400 8020 #define ETH_MACLMIR_LSI_Pos (0U)
AnnaBridge 172:65be27845400 8021 #define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8022 #define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
AnnaBridge 172:65be27845400 8023
AnnaBridge 172:65be27845400 8024 /* Bit definition for Ethernet MTL Operation Mode Register */
AnnaBridge 172:65be27845400 8025 #define ETH_MTLOMR_CNTCLR_Pos (9U)
AnnaBridge 172:65be27845400 8026 #define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8027 #define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
AnnaBridge 172:65be27845400 8028 #define ETH_MTLOMR_CNTPRST_Pos (8U)
AnnaBridge 172:65be27845400 8029 #define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8030 #define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
AnnaBridge 172:65be27845400 8031 #define ETH_MTLOMR_DTXSTS_Pos (1U)
AnnaBridge 172:65be27845400 8032 #define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8033 #define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
AnnaBridge 172:65be27845400 8034
AnnaBridge 172:65be27845400 8035 /* Bit definition for Ethernet MTL Interrupt Status Register */
AnnaBridge 172:65be27845400 8036 #define ETH_MTLISR_MACIS_Pos (16U)
AnnaBridge 172:65be27845400 8037 #define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8038 #define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
AnnaBridge 172:65be27845400 8039 #define ETH_MTLISR_QIS_Pos (0U)
AnnaBridge 172:65be27845400 8040 #define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8041 #define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
AnnaBridge 172:65be27845400 8042
AnnaBridge 172:65be27845400 8043 /* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
AnnaBridge 172:65be27845400 8044 #define ETH_MTLTQOMR_TTC_Pos (4U)
AnnaBridge 172:65be27845400 8045 #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 8046 #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
AnnaBridge 172:65be27845400 8047 #define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
AnnaBridge 172:65be27845400 8048 #define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
AnnaBridge 172:65be27845400 8049 #define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
AnnaBridge 172:65be27845400 8050 #define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
AnnaBridge 172:65be27845400 8051 #define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
AnnaBridge 172:65be27845400 8052 #define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
AnnaBridge 172:65be27845400 8053 #define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
AnnaBridge 172:65be27845400 8054 #define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
AnnaBridge 172:65be27845400 8055 #define ETH_MTLTQOMR_TSF_Pos (1U)
AnnaBridge 172:65be27845400 8056 #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8057 #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
AnnaBridge 172:65be27845400 8058 #define ETH_MTLTQOMR_FTQ_Pos (0U)
AnnaBridge 172:65be27845400 8059 #define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8060 #define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
AnnaBridge 172:65be27845400 8061
AnnaBridge 172:65be27845400 8062 /* Bit definition for Ethernet MTL Tx Queue Underflow Register */
AnnaBridge 172:65be27845400 8063 #define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
AnnaBridge 172:65be27845400 8064 #define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8065 #define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
AnnaBridge 172:65be27845400 8066 #define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
AnnaBridge 172:65be27845400 8067 #define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 8068 #define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
AnnaBridge 172:65be27845400 8069
AnnaBridge 172:65be27845400 8070 /* Bit definition for Ethernet MTL Tx Queue Debug Register */
AnnaBridge 172:65be27845400 8071 #define ETH_MTLTQDR_STXSTSF_Pos (20U)
AnnaBridge 172:65be27845400 8072 #define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
AnnaBridge 172:65be27845400 8073 #define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
AnnaBridge 172:65be27845400 8074 #define ETH_MTLTQDR_PTXQ_Pos (16U)
AnnaBridge 172:65be27845400 8075 #define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 8076 #define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
AnnaBridge 172:65be27845400 8077 #define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
AnnaBridge 172:65be27845400 8078 #define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8079 #define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
AnnaBridge 172:65be27845400 8080 #define ETH_MTLTQDR_TXQSTS_Pos (4U)
AnnaBridge 172:65be27845400 8081 #define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8082 #define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
AnnaBridge 172:65be27845400 8083 #define ETH_MTLTQDR_TWCSTS_Pos (3U)
AnnaBridge 172:65be27845400 8084 #define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8085 #define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
AnnaBridge 172:65be27845400 8086 #define ETH_MTLTQDR_TRCSTS_Pos (1U)
AnnaBridge 172:65be27845400 8087 #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 8088 #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
AnnaBridge 172:65be27845400 8089 #define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
AnnaBridge 172:65be27845400 8090 #define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
AnnaBridge 172:65be27845400 8091 #define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
AnnaBridge 172:65be27845400 8092 #define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
AnnaBridge 172:65be27845400 8093 #define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
AnnaBridge 172:65be27845400 8094 #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8095 #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
AnnaBridge 172:65be27845400 8096
AnnaBridge 172:65be27845400 8097 /* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
AnnaBridge 172:65be27845400 8098 #define ETH_MTLQICSR_RXOIE_Pos (24U)
AnnaBridge 172:65be27845400 8099 #define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8100 #define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
AnnaBridge 172:65be27845400 8101 #define ETH_MTLQICSR_RXOVFIS_Pos (16U)
AnnaBridge 172:65be27845400 8102 #define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8103 #define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
AnnaBridge 172:65be27845400 8104 #define ETH_MTLQICSR_TXUIE_Pos (8U)
AnnaBridge 172:65be27845400 8105 #define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8106 #define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
AnnaBridge 172:65be27845400 8107 #define ETH_MTLQICSR_TXUNFIS_Pos (0U)
AnnaBridge 172:65be27845400 8108 #define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8109 #define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
AnnaBridge 172:65be27845400 8110
AnnaBridge 172:65be27845400 8111 /* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
AnnaBridge 172:65be27845400 8112 #define ETH_MTLRQOMR_RQS_Pos (20U)
AnnaBridge 172:65be27845400 8113 #define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
AnnaBridge 172:65be27845400 8114 #define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
AnnaBridge 172:65be27845400 8115 #define ETH_MTLRQOMR_RFD_Pos (14U)
AnnaBridge 172:65be27845400 8116 #define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
AnnaBridge 172:65be27845400 8117 #define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
AnnaBridge 172:65be27845400 8118 #define ETH_MTLRQOMR_RFA_Pos (8U)
AnnaBridge 172:65be27845400 8119 #define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 8120 #define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
AnnaBridge 172:65be27845400 8121 #define ETH_MTLRQOMR_EHFC_Pos (7U)
AnnaBridge 172:65be27845400 8122 #define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8123 #define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
AnnaBridge 172:65be27845400 8124 #define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
AnnaBridge 172:65be27845400 8125 #define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8126 #define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
AnnaBridge 172:65be27845400 8127 #define ETH_MTLRQOMR_RSF_Pos (5U)
AnnaBridge 172:65be27845400 8128 #define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8129 #define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
AnnaBridge 172:65be27845400 8130 #define ETH_MTLRQOMR_FEP_Pos (4U)
AnnaBridge 172:65be27845400 8131 #define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8132 #define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
AnnaBridge 172:65be27845400 8133 #define ETH_MTLRQOMR_FUP_Pos (3U)
AnnaBridge 172:65be27845400 8134 #define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8135 #define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
AnnaBridge 172:65be27845400 8136 #define ETH_MTLRQOMR_RTC_Pos (0U)
AnnaBridge 172:65be27845400 8137 #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 8138 #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
AnnaBridge 172:65be27845400 8139 #define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
AnnaBridge 172:65be27845400 8140 #define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
AnnaBridge 172:65be27845400 8141 #define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
AnnaBridge 172:65be27845400 8142 #define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
AnnaBridge 172:65be27845400 8143
AnnaBridge 172:65be27845400 8144 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
AnnaBridge 172:65be27845400 8145 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
AnnaBridge 172:65be27845400 8146 #define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8147 #define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
AnnaBridge 172:65be27845400 8148 #define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
AnnaBridge 172:65be27845400 8149 #define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
AnnaBridge 172:65be27845400 8150 #define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
AnnaBridge 172:65be27845400 8151 #define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
AnnaBridge 172:65be27845400 8152 #define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8153 #define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
AnnaBridge 172:65be27845400 8154 #define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
AnnaBridge 172:65be27845400 8155 #define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 8156 #define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
AnnaBridge 172:65be27845400 8157
AnnaBridge 172:65be27845400 8158 /* Bit definition for Ethernet MTL Rx Queue Debug Register */
AnnaBridge 172:65be27845400 8159 #define ETH_MTLRQDR_PRXQ_Pos (16U)
AnnaBridge 172:65be27845400 8160 #define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
AnnaBridge 172:65be27845400 8161 #define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
AnnaBridge 172:65be27845400 8162 #define ETH_MTLRQDR_RXQSTS_Pos (4U)
AnnaBridge 172:65be27845400 8163 #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8164 #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
AnnaBridge 172:65be27845400 8165 #define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
AnnaBridge 172:65be27845400 8166 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
AnnaBridge 172:65be27845400 8167 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8168 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
AnnaBridge 172:65be27845400 8169 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
AnnaBridge 172:65be27845400 8170 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8171 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
AnnaBridge 172:65be27845400 8172 #define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
AnnaBridge 172:65be27845400 8173 #define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 8174 #define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
AnnaBridge 172:65be27845400 8175 #define ETH_MTLRQDR_RRCSTS_Pos (1U)
AnnaBridge 172:65be27845400 8176 #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 8177 #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
AnnaBridge 172:65be27845400 8178 #define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
AnnaBridge 172:65be27845400 8179 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
AnnaBridge 172:65be27845400 8180 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8181 #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
AnnaBridge 172:65be27845400 8182 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
AnnaBridge 172:65be27845400 8183 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8184 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
AnnaBridge 172:65be27845400 8185 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
AnnaBridge 172:65be27845400 8186 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 8187 #define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
AnnaBridge 172:65be27845400 8188 #define ETH_MTLRQDR_RWCSTS_Pos (0U)
AnnaBridge 172:65be27845400 8189 #define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8190 #define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
AnnaBridge 172:65be27845400 8191
AnnaBridge 172:65be27845400 8192 /* Bit definition for Ethernet MTL Rx Queue Control Register */
AnnaBridge 172:65be27845400 8193 #define ETH_MTLRQCR_RQPA_Pos (3U)
AnnaBridge 172:65be27845400 8194 #define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8195 #define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
AnnaBridge 172:65be27845400 8196 #define ETH_MTLRQCR_RQW_Pos (0U)
AnnaBridge 172:65be27845400 8197 #define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 8198 #define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
AnnaBridge 172:65be27845400 8199
AnnaBridge 172:65be27845400 8200 /* Bit definition for Ethernet DMA Mode Register */
AnnaBridge 172:65be27845400 8201 #define ETH_DMAMR_INTM_Pos (16U)
AnnaBridge 172:65be27845400 8202 #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 8203 #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
AnnaBridge 172:65be27845400 8204 #define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 8205 #define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8206 #define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8207 #define ETH_DMAMR_PR_Pos (12U)
AnnaBridge 172:65be27845400 8208 #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 8209 #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
AnnaBridge 172:65be27845400 8210 #define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
AnnaBridge 172:65be27845400 8211 #define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
AnnaBridge 172:65be27845400 8212 #define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
AnnaBridge 172:65be27845400 8213 #define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
AnnaBridge 172:65be27845400 8214 #define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
AnnaBridge 172:65be27845400 8215 #define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
AnnaBridge 172:65be27845400 8216 #define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
AnnaBridge 172:65be27845400 8217 #define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
AnnaBridge 172:65be27845400 8218 #define ETH_DMAMR_TXPR_Pos (11U)
AnnaBridge 172:65be27845400 8219 #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8220 #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
AnnaBridge 172:65be27845400 8221 #define ETH_DMAMR_DA_Pos (1U)
AnnaBridge 172:65be27845400 8222 #define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8223 #define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
AnnaBridge 172:65be27845400 8224 #define ETH_DMAMR_SWR_Pos (0U)
AnnaBridge 172:65be27845400 8225 #define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8226 #define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
AnnaBridge 172:65be27845400 8227
AnnaBridge 172:65be27845400 8228 /* Bit definition for Ethernet DMA SysBus Mode Register */
AnnaBridge 172:65be27845400 8229 #define ETH_DMASBMR_RB_Pos (15U)
AnnaBridge 172:65be27845400 8230 #define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8231 #define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
AnnaBridge 172:65be27845400 8232 #define ETH_DMASBMR_MB_Pos (14U)
AnnaBridge 172:65be27845400 8233 #define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8234 #define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
AnnaBridge 172:65be27845400 8235 #define ETH_DMASBMR_AAL_Pos (12U)
AnnaBridge 172:65be27845400 8236 #define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8237 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
AnnaBridge 172:65be27845400 8238 #define ETH_DMASBMR_FB_Pos (0U)
AnnaBridge 172:65be27845400 8239 #define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8240 #define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
AnnaBridge 172:65be27845400 8241
AnnaBridge 172:65be27845400 8242 /* Bit definition for Ethernet DMA Interrupt Status Register */
AnnaBridge 172:65be27845400 8243 #define ETH_DMAISR_MACIS_Pos (17U)
AnnaBridge 172:65be27845400 8244 #define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8245 #define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
AnnaBridge 172:65be27845400 8246 #define ETH_DMAISR_MTLIS_Pos (16U)
AnnaBridge 172:65be27845400 8247 #define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8248 #define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
AnnaBridge 172:65be27845400 8249 #define ETH_DMAISR_DMACIS_Pos (0U)
AnnaBridge 172:65be27845400 8250 #define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8251 #define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
AnnaBridge 172:65be27845400 8252
AnnaBridge 172:65be27845400 8253 /* Bit definition for Ethernet DMA Debug Status Register */
AnnaBridge 172:65be27845400 8254 #define ETH_DMADSR_TPS_Pos (12U)
AnnaBridge 172:65be27845400 8255 #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 8256 #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
AnnaBridge 172:65be27845400 8257 #define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
AnnaBridge 172:65be27845400 8258 #define ETH_DMADSR_TPS_FETCHING_Pos (12U)
AnnaBridge 172:65be27845400 8259 #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8260 #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
AnnaBridge 172:65be27845400 8261 #define ETH_DMADSR_TPS_WAITING_Pos (13U)
AnnaBridge 172:65be27845400 8262 #define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8263 #define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
AnnaBridge 172:65be27845400 8264 #define ETH_DMADSR_TPS_READING_Pos (12U)
AnnaBridge 172:65be27845400 8265 #define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 8266 #define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
AnnaBridge 172:65be27845400 8267 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
AnnaBridge 172:65be27845400 8268 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8269 #define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
AnnaBridge 172:65be27845400 8270 #define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
AnnaBridge 172:65be27845400 8271 #define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 8272 #define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
AnnaBridge 172:65be27845400 8273 #define ETH_DMADSR_TPS_CLOSING_Pos (12U)
AnnaBridge 172:65be27845400 8274 #define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 8275 #define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
AnnaBridge 172:65be27845400 8276 #define ETH_DMADSR_RPS_Pos (8U)
AnnaBridge 172:65be27845400 8277 #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 8278 #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
AnnaBridge 172:65be27845400 8279 #define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
AnnaBridge 172:65be27845400 8280 #define ETH_DMADSR_RPS_FETCHING_Pos (12U)
AnnaBridge 172:65be27845400 8281 #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8282 #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
AnnaBridge 172:65be27845400 8283 #define ETH_DMADSR_RPS_WAITING_Pos (12U)
AnnaBridge 172:65be27845400 8284 #define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 8285 #define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
AnnaBridge 172:65be27845400 8286 #define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
AnnaBridge 172:65be27845400 8287 #define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8288 #define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
AnnaBridge 172:65be27845400 8289 #define ETH_DMADSR_RPS_CLOSING_Pos (12U)
AnnaBridge 172:65be27845400 8290 #define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
AnnaBridge 172:65be27845400 8291 #define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
AnnaBridge 172:65be27845400 8292 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
AnnaBridge 172:65be27845400 8293 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 8294 #define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
AnnaBridge 172:65be27845400 8295 #define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
AnnaBridge 172:65be27845400 8296 #define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 8297 #define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
AnnaBridge 172:65be27845400 8298
AnnaBridge 172:65be27845400 8299 /* Bit definition for Ethernet DMA Channel Control Register */
AnnaBridge 172:65be27845400 8300 #define ETH_DMACCR_DSL_Pos (18U)
AnnaBridge 172:65be27845400 8301 #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
AnnaBridge 172:65be27845400 8302 #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
AnnaBridge 172:65be27845400 8303 #define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
AnnaBridge 172:65be27845400 8304 #define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
AnnaBridge 172:65be27845400 8305 #define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
AnnaBridge 172:65be27845400 8306 #define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
AnnaBridge 172:65be27845400 8307 #define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
AnnaBridge 172:65be27845400 8308 #define ETH_DMACCR_MSS_Pos (0U)
AnnaBridge 172:65be27845400 8309 #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 8310 #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
AnnaBridge 172:65be27845400 8311
AnnaBridge 172:65be27845400 8312 /* Bit definition for Ethernet DMA Channel Tx Control Register */
AnnaBridge 172:65be27845400 8313 #define ETH_DMACTCR_TPBL_Pos (16U)
AnnaBridge 172:65be27845400 8314 #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
AnnaBridge 172:65be27845400 8315 #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
AnnaBridge 172:65be27845400 8316 #define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
AnnaBridge 172:65be27845400 8317 #define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
AnnaBridge 172:65be27845400 8318 #define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
AnnaBridge 172:65be27845400 8319 #define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
AnnaBridge 172:65be27845400 8320 #define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
AnnaBridge 172:65be27845400 8321 #define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
AnnaBridge 172:65be27845400 8322 #define ETH_DMACTCR_TSE_Pos (12U)
AnnaBridge 172:65be27845400 8323 #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8324 #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
AnnaBridge 172:65be27845400 8325 #define ETH_DMACTCR_OSP_Pos (4U)
AnnaBridge 172:65be27845400 8326 #define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8327 #define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
AnnaBridge 172:65be27845400 8328 #define ETH_DMACTCR_ST_Pos (0U)
AnnaBridge 172:65be27845400 8329 #define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8330 #define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
AnnaBridge 172:65be27845400 8331
AnnaBridge 172:65be27845400 8332 /* Bit definition for Ethernet DMA Channel Rx Control Register */
AnnaBridge 172:65be27845400 8333 #define ETH_DMACRCR_RPF_Pos (31U)
AnnaBridge 172:65be27845400 8334 #define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 8335 #define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
AnnaBridge 172:65be27845400 8336 #define ETH_DMACRCR_RPBL_Pos (16U)
AnnaBridge 172:65be27845400 8337 #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
AnnaBridge 172:65be27845400 8338 #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
AnnaBridge 172:65be27845400 8339 #define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
AnnaBridge 172:65be27845400 8340 #define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
AnnaBridge 172:65be27845400 8341 #define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
AnnaBridge 172:65be27845400 8342 #define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
AnnaBridge 172:65be27845400 8343 #define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
AnnaBridge 172:65be27845400 8344 #define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
AnnaBridge 172:65be27845400 8345 #define ETH_DMACRCR_RBSZ_Pos (1U)
AnnaBridge 172:65be27845400 8346 #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
AnnaBridge 172:65be27845400 8347 #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
AnnaBridge 172:65be27845400 8348 #define ETH_DMACRCR_SR_Pos (0U)
AnnaBridge 172:65be27845400 8349 #define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8350 #define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
AnnaBridge 172:65be27845400 8351
AnnaBridge 172:65be27845400 8352 /* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
AnnaBridge 172:65be27845400 8353 #define ETH_DMACTDLAR_TDESLA_Pos (2U)
AnnaBridge 172:65be27845400 8354 #define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
AnnaBridge 172:65be27845400 8355 #define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
AnnaBridge 172:65be27845400 8356
AnnaBridge 172:65be27845400 8357 /* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
AnnaBridge 172:65be27845400 8358 #define ETH_DMACRDLAR_RDESLA_Pos (2U)
AnnaBridge 172:65be27845400 8359 #define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
AnnaBridge 172:65be27845400 8360 #define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
AnnaBridge 172:65be27845400 8361
AnnaBridge 172:65be27845400 8362 /* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
AnnaBridge 172:65be27845400 8363 #define ETH_DMACTDTPR_TDT_Pos (2U)
AnnaBridge 172:65be27845400 8364 #define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
AnnaBridge 172:65be27845400 8365 #define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
AnnaBridge 172:65be27845400 8366
AnnaBridge 172:65be27845400 8367 /* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
AnnaBridge 172:65be27845400 8368 #define ETH_DMACRDTPR_RDT_Pos (2U)
AnnaBridge 172:65be27845400 8369 #define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
AnnaBridge 172:65be27845400 8370 #define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
AnnaBridge 172:65be27845400 8371
AnnaBridge 172:65be27845400 8372 /* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
AnnaBridge 172:65be27845400 8373 #define ETH_DMACTDRLR_TDRL_Pos (0U)
AnnaBridge 172:65be27845400 8374 #define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 8375 #define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
AnnaBridge 172:65be27845400 8376
AnnaBridge 172:65be27845400 8377 /* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
AnnaBridge 172:65be27845400 8378 #define ETH_DMACRDRLR_RDRL_Pos (0U)
AnnaBridge 172:65be27845400 8379 #define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 8380 #define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
AnnaBridge 172:65be27845400 8381
AnnaBridge 172:65be27845400 8382 /* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
AnnaBridge 172:65be27845400 8383 #define ETH_DMACIER_NIE_Pos (15U)
AnnaBridge 172:65be27845400 8384 #define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8385 #define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
AnnaBridge 172:65be27845400 8386 #define ETH_DMACIER_AIE_Pos (14U)
AnnaBridge 172:65be27845400 8387 #define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8388 #define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
AnnaBridge 172:65be27845400 8389 #define ETH_DMACIER_CDEE_Pos (13U)
AnnaBridge 172:65be27845400 8390 #define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8391 #define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
AnnaBridge 172:65be27845400 8392 #define ETH_DMACIER_FBEE_Pos (12U)
AnnaBridge 172:65be27845400 8393 #define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8394 #define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
AnnaBridge 172:65be27845400 8395 #define ETH_DMACIER_ERIE_Pos (11U)
AnnaBridge 172:65be27845400 8396 #define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8397 #define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
AnnaBridge 172:65be27845400 8398 #define ETH_DMACIER_ETIE_Pos (10U)
AnnaBridge 172:65be27845400 8399 #define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8400 #define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
AnnaBridge 172:65be27845400 8401 #define ETH_DMACIER_RWTE_Pos (9U)
AnnaBridge 172:65be27845400 8402 #define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8403 #define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
AnnaBridge 172:65be27845400 8404 #define ETH_DMACIER_RSE_Pos (8U)
AnnaBridge 172:65be27845400 8405 #define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8406 #define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
AnnaBridge 172:65be27845400 8407 #define ETH_DMACIER_RBUE_Pos (7U)
AnnaBridge 172:65be27845400 8408 #define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8409 #define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
AnnaBridge 172:65be27845400 8410 #define ETH_DMACIER_RIE_Pos (6U)
AnnaBridge 172:65be27845400 8411 #define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8412 #define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
AnnaBridge 172:65be27845400 8413 #define ETH_DMACIER_TBUE_Pos (2U)
AnnaBridge 172:65be27845400 8414 #define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8415 #define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
AnnaBridge 172:65be27845400 8416 #define ETH_DMACIER_TXSE_Pos (1U)
AnnaBridge 172:65be27845400 8417 #define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8418 #define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
AnnaBridge 172:65be27845400 8419 #define ETH_DMACIER_TIE_Pos (0U)
AnnaBridge 172:65be27845400 8420 #define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8421 #define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
AnnaBridge 172:65be27845400 8422
AnnaBridge 172:65be27845400 8423 /* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
AnnaBridge 172:65be27845400 8424 #define ETH_DMACRIWTR_RWT_Pos (0U)
AnnaBridge 172:65be27845400 8425 #define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8426 #define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
AnnaBridge 172:65be27845400 8427
AnnaBridge 172:65be27845400 8428 /* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
AnnaBridge 172:65be27845400 8429 #define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
AnnaBridge 172:65be27845400 8430 #define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8431 #define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
AnnaBridge 172:65be27845400 8432
AnnaBridge 172:65be27845400 8433 /* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
AnnaBridge 172:65be27845400 8434 #define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
AnnaBridge 172:65be27845400 8435 #define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8436 #define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
AnnaBridge 172:65be27845400 8437
AnnaBridge 172:65be27845400 8438 /* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
AnnaBridge 172:65be27845400 8439 #define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
AnnaBridge 172:65be27845400 8440 #define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8441 #define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
AnnaBridge 172:65be27845400 8442
AnnaBridge 172:65be27845400 8443 /* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
AnnaBridge 172:65be27845400 8444 #define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
AnnaBridge 172:65be27845400 8445 #define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8446 #define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
AnnaBridge 172:65be27845400 8447
AnnaBridge 172:65be27845400 8448 /* Bit definition for Ethernet DMA Channel Status Register */
AnnaBridge 172:65be27845400 8449 #define ETH_DMACSR_REB_Pos (19U)
AnnaBridge 172:65be27845400 8450 #define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
AnnaBridge 172:65be27845400 8451 #define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
AnnaBridge 172:65be27845400 8452 #define ETH_DMACSR_TEB_Pos (16U)
AnnaBridge 172:65be27845400 8453 #define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 8454 #define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
AnnaBridge 172:65be27845400 8455 #define ETH_DMACSR_NIS_Pos (15U)
AnnaBridge 172:65be27845400 8456 #define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8457 #define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
AnnaBridge 172:65be27845400 8458 #define ETH_DMACSR_AIS_Pos (14U)
AnnaBridge 172:65be27845400 8459 #define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8460 #define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
AnnaBridge 172:65be27845400 8461 #define ETH_DMACSR_CDE_Pos (13U)
AnnaBridge 172:65be27845400 8462 #define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8463 #define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
AnnaBridge 172:65be27845400 8464 #define ETH_DMACSR_FBE_Pos (12U)
AnnaBridge 172:65be27845400 8465 #define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8466 #define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
AnnaBridge 172:65be27845400 8467 #define ETH_DMACSR_ERI_Pos (11U)
AnnaBridge 172:65be27845400 8468 #define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8469 #define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
AnnaBridge 172:65be27845400 8470 #define ETH_DMACSR_ETI_Pos (10U)
AnnaBridge 172:65be27845400 8471 #define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8472 #define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
AnnaBridge 172:65be27845400 8473 #define ETH_DMACSR_RWT_Pos (9U)
AnnaBridge 172:65be27845400 8474 #define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8475 #define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
AnnaBridge 172:65be27845400 8476 #define ETH_DMACSR_RPS_Pos (8U)
AnnaBridge 172:65be27845400 8477 #define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8478 #define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
AnnaBridge 172:65be27845400 8479 #define ETH_DMACSR_RBU_Pos (7U)
AnnaBridge 172:65be27845400 8480 #define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8481 #define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
AnnaBridge 172:65be27845400 8482 #define ETH_DMACSR_RI_Pos (6U)
AnnaBridge 172:65be27845400 8483 #define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8484 #define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
AnnaBridge 172:65be27845400 8485 #define ETH_DMACSR_TBU_Pos (2U)
AnnaBridge 172:65be27845400 8486 #define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8487 #define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
AnnaBridge 172:65be27845400 8488 #define ETH_DMACSR_TPS_Pos (1U)
AnnaBridge 172:65be27845400 8489 #define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8490 #define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
AnnaBridge 172:65be27845400 8491 #define ETH_DMACSR_TI_Pos (0U)
AnnaBridge 172:65be27845400 8492 #define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8493 #define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
AnnaBridge 172:65be27845400 8494
AnnaBridge 172:65be27845400 8495 /* Bit definition for Ethernet DMA Channel missed frame count register */
AnnaBridge 172:65be27845400 8496 #define ETH_DMACMFCR_MFCO_Pos (15U)
AnnaBridge 172:65be27845400 8497 #define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8498 #define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
AnnaBridge 172:65be27845400 8499 #define ETH_DMACMFCR_MFC_Pos (0U)
AnnaBridge 172:65be27845400 8500 #define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 8501 #define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
AnnaBridge 172:65be27845400 8502
AnnaBridge 172:65be27845400 8503 /******************************************************************************/
AnnaBridge 172:65be27845400 8504 /* */
AnnaBridge 172:65be27845400 8505 /* DMA Controller */
AnnaBridge 172:65be27845400 8506 /* */
AnnaBridge 172:65be27845400 8507 /******************************************************************************/
AnnaBridge 172:65be27845400 8508 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 172:65be27845400 8509 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 172:65be27845400 8510 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 172:65be27845400 8511 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
AnnaBridge 172:65be27845400 8512 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8513 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8514 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 172:65be27845400 8515 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 8516 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
AnnaBridge 172:65be27845400 8517 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8518 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8519 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 172:65be27845400 8520 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8521 #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
AnnaBridge 172:65be27845400 8522 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 172:65be27845400 8523 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8524 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
AnnaBridge 172:65be27845400 8525 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 172:65be27845400 8526 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 8527 #define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
AnnaBridge 172:65be27845400 8528 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8529 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8530 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 172:65be27845400 8531 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8532 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
AnnaBridge 172:65be27845400 8533 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 172:65be27845400 8534 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 8535 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
AnnaBridge 172:65be27845400 8536 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8537 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8538 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 172:65be27845400 8539 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 8540 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
AnnaBridge 172:65be27845400 8541 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8542 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8543 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 172:65be27845400 8544 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8545 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
AnnaBridge 172:65be27845400 8546 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 172:65be27845400 8547 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8548 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
AnnaBridge 172:65be27845400 8549 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 172:65be27845400 8550 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8551 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
AnnaBridge 172:65be27845400 8552 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 172:65be27845400 8553 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 8554 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
AnnaBridge 172:65be27845400 8555 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8556 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8557 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 172:65be27845400 8558 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8559 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
AnnaBridge 172:65be27845400 8560 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 172:65be27845400 8561 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8562 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 172:65be27845400 8563 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 172:65be27845400 8564 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8565 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
AnnaBridge 172:65be27845400 8566 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 172:65be27845400 8567 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8568 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 172:65be27845400 8569 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 172:65be27845400 8570 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8571 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
AnnaBridge 172:65be27845400 8572 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 172:65be27845400 8573 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8574 #define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
AnnaBridge 172:65be27845400 8575
AnnaBridge 172:65be27845400 8576 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 172:65be27845400 8577 #define DMA_SxNDT_Pos (0U)
AnnaBridge 172:65be27845400 8578 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 8579 #define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
AnnaBridge 172:65be27845400 8580 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8581 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8582 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8583 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8584 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8585 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8586 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8587 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8588 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8589 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8590 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8591 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8592 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8593 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8594 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8595 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8596
AnnaBridge 172:65be27845400 8597 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 172:65be27845400 8598 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 172:65be27845400 8599 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8600 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
AnnaBridge 172:65be27845400 8601 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 172:65be27845400 8602 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 8603 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
AnnaBridge 172:65be27845400 8604 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8605 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8606 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8607 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 172:65be27845400 8608 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8609 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
AnnaBridge 172:65be27845400 8610 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 172:65be27845400 8611 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 8612 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
AnnaBridge 172:65be27845400 8613 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8614 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8615
AnnaBridge 172:65be27845400 8616 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 172:65be27845400 8617 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 172:65be27845400 8618 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8619 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8620 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 172:65be27845400 8621 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8622 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8623 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 172:65be27845400 8624 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8625 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8626 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 172:65be27845400 8627 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8628 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8629 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 172:65be27845400 8630 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8631 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8632 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 172:65be27845400 8633 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8634 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8635 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 172:65be27845400 8636 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8637 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8638 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 172:65be27845400 8639 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8640 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8641 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 172:65be27845400 8642 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8643 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8644 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 172:65be27845400 8645 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8646 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8647 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 172:65be27845400 8648 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8649 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8650 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 172:65be27845400 8651 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8652 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8653 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 172:65be27845400 8654 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8655 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8656 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 172:65be27845400 8657 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8658 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8659 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 172:65be27845400 8660 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8661 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8662 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 172:65be27845400 8663 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8664 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8665 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 172:65be27845400 8666 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8667 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8668 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 172:65be27845400 8669 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8670 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8671 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 172:65be27845400 8672 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8673 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8674 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 172:65be27845400 8675 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8676 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8677
AnnaBridge 172:65be27845400 8678 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 172:65be27845400 8679 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 172:65be27845400 8680 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8681 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8682 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 172:65be27845400 8683 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8684 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8685 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 172:65be27845400 8686 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8687 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8688 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 172:65be27845400 8689 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8690 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8691 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 172:65be27845400 8692 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8693 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8694 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 172:65be27845400 8695 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8696 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8697 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 172:65be27845400 8698 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8699 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8700 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 172:65be27845400 8701 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8702 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8703 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 172:65be27845400 8704 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8705 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8706 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 172:65be27845400 8707 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8708 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8709 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 172:65be27845400 8710 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8711 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8712 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 172:65be27845400 8713 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8714 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8715 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 172:65be27845400 8716 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8717 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8718 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 172:65be27845400 8719 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8720 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8721 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 172:65be27845400 8722 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8723 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8724 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 172:65be27845400 8725 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8726 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8727 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 172:65be27845400 8728 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8729 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
AnnaBridge 172:65be27845400 8730 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 172:65be27845400 8731 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8732 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
AnnaBridge 172:65be27845400 8733 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 172:65be27845400 8734 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8735 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8736 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 172:65be27845400 8737 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8738 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8739
AnnaBridge 172:65be27845400 8740 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 172:65be27845400 8741 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 172:65be27845400 8742 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8743 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8744 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 172:65be27845400 8745 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8746 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8747 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 172:65be27845400 8748 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8749 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8750 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 172:65be27845400 8751 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8752 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8753 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 172:65be27845400 8754 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8755 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8756 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 172:65be27845400 8757 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8758 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8759 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 172:65be27845400 8760 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8761 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8762 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 172:65be27845400 8763 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8764 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8765 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 172:65be27845400 8766 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8767 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8768 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 172:65be27845400 8769 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8770 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8771 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 172:65be27845400 8772 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8773 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8774 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 172:65be27845400 8775 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8776 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8777 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 172:65be27845400 8778 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8779 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8780 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 172:65be27845400 8781 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8782 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8783 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 172:65be27845400 8784 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8785 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8786 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 172:65be27845400 8787 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8788 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8789 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 172:65be27845400 8790 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8791 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8792 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 172:65be27845400 8793 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8794 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8795 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 172:65be27845400 8796 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8797 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8798 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 172:65be27845400 8799 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8800 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8801
AnnaBridge 172:65be27845400 8802 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 172:65be27845400 8803 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 172:65be27845400 8804 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8805 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8806 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 172:65be27845400 8807 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8808 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8809 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 172:65be27845400 8810 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8811 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8812 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 172:65be27845400 8813 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8814 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8815 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 172:65be27845400 8816 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8817 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8818 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 172:65be27845400 8819 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8820 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8821 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 172:65be27845400 8822 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8823 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8824 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 172:65be27845400 8825 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8826 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8827 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 172:65be27845400 8828 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8829 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8830 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 172:65be27845400 8831 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8832 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8833 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 172:65be27845400 8834 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8835 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8836 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 172:65be27845400 8837 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8838 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8839 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 172:65be27845400 8840 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8841 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8842 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 172:65be27845400 8843 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8844 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8845 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 172:65be27845400 8846 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8847 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8848 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 172:65be27845400 8849 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8850 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
AnnaBridge 172:65be27845400 8851 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 172:65be27845400 8852 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8853 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
AnnaBridge 172:65be27845400 8854 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 172:65be27845400 8855 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8856 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 8857 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 172:65be27845400 8858 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8859 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
AnnaBridge 172:65be27845400 8860 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 172:65be27845400 8861 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8862 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
AnnaBridge 172:65be27845400 8863
AnnaBridge 172:65be27845400 8864 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 172:65be27845400 8865 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 172:65be27845400 8866 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8867 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 172:65be27845400 8868
AnnaBridge 172:65be27845400 8869 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 172:65be27845400 8870 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 172:65be27845400 8871 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8872 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
AnnaBridge 172:65be27845400 8873
AnnaBridge 172:65be27845400 8874 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 172:65be27845400 8875 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 172:65be27845400 8876 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 8877 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
AnnaBridge 172:65be27845400 8878
AnnaBridge 172:65be27845400 8879 /******************************************************************************/
AnnaBridge 172:65be27845400 8880 /* */
AnnaBridge 172:65be27845400 8881 /* DMAMUX Controller */
AnnaBridge 172:65be27845400 8882 /* */
AnnaBridge 172:65be27845400 8883 /******************************************************************************/
AnnaBridge 172:65be27845400 8884 /******************** Bits definition for DMAMUX_CxCR register **************/
AnnaBridge 172:65be27845400 8885 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
AnnaBridge 172:65be27845400 8886 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 8887 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
AnnaBridge 172:65be27845400 8888 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8889 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8890 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8891 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8892 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8893 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8894 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8895 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8896 #define DMAMUX_CxCR_SOIE_Pos (8U)
AnnaBridge 172:65be27845400 8897 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8898 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
AnnaBridge 172:65be27845400 8899 #define DMAMUX_CxCR_EGE_Pos (9U)
AnnaBridge 172:65be27845400 8900 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8901 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
AnnaBridge 172:65be27845400 8902 #define DMAMUX_CxCR_SE_Pos (16U)
AnnaBridge 172:65be27845400 8903 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 8904 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
AnnaBridge 172:65be27845400 8905 #define DMAMUX_CxCR_SPOL_Pos (17U)
AnnaBridge 172:65be27845400 8906 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 8907 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
AnnaBridge 172:65be27845400 8908 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 8909 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 8910 #define DMAMUX_CxCR_NBREQ_Pos (19U)
AnnaBridge 172:65be27845400 8911 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
AnnaBridge 172:65be27845400 8912 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
AnnaBridge 172:65be27845400 8913 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 8914 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 8915 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 8916 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 8917 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 8918 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
AnnaBridge 172:65be27845400 8919 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
AnnaBridge 172:65be27845400 8920 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
AnnaBridge 172:65be27845400 8921 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 8922 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 8923 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 8924 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 8925 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 8926
AnnaBridge 172:65be27845400 8927 /******************** Bits definition for DMAMUX_CSR register **************/
AnnaBridge 172:65be27845400 8928 #define DMAMUX_CSR_SOF0_Pos (0U)
AnnaBridge 172:65be27845400 8929 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8930 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8931 #define DMAMUX_CSR_SOF1_Pos (1U)
AnnaBridge 172:65be27845400 8932 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8933 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8934 #define DMAMUX_CSR_SOF2_Pos (2U)
AnnaBridge 172:65be27845400 8935 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8936 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8937 #define DMAMUX_CSR_SOF3_Pos (3U)
AnnaBridge 172:65be27845400 8938 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8939 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8940 #define DMAMUX_CSR_SOF4_Pos (4U)
AnnaBridge 172:65be27845400 8941 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8942 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8943 #define DMAMUX_CSR_SOF5_Pos (5U)
AnnaBridge 172:65be27845400 8944 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8945 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8946 #define DMAMUX_CSR_SOF6_Pos (6U)
AnnaBridge 172:65be27845400 8947 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8948 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8949 #define DMAMUX_CSR_SOF7_Pos (7U)
AnnaBridge 172:65be27845400 8950 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 8951 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8952 #define DMAMUX_CSR_SOF8_Pos (8U)
AnnaBridge 172:65be27845400 8953 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 8954 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8955 #define DMAMUX_CSR_SOF9_Pos (9U)
AnnaBridge 172:65be27845400 8956 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 8957 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8958 #define DMAMUX_CSR_SOF10_Pos (10U)
AnnaBridge 172:65be27845400 8959 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 8960 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8961 #define DMAMUX_CSR_SOF11_Pos (11U)
AnnaBridge 172:65be27845400 8962 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 8963 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8964 #define DMAMUX_CSR_SOF12_Pos (12U)
AnnaBridge 172:65be27845400 8965 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 8966 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8967 #define DMAMUX_CSR_SOF13_Pos (13U)
AnnaBridge 172:65be27845400 8968 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 8969 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8970 #define DMAMUX_CSR_SOF14_Pos (14U)
AnnaBridge 172:65be27845400 8971 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 8972 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8973 #define DMAMUX_CSR_SOF15_Pos (15U)
AnnaBridge 172:65be27845400 8974 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 8975 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
AnnaBridge 172:65be27845400 8976
AnnaBridge 172:65be27845400 8977 /******************** Bits definition for DMAMUX_CFR register **************/
AnnaBridge 172:65be27845400 8978 #define DMAMUX_CFR_CSOF0_Pos (0U)
AnnaBridge 172:65be27845400 8979 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 8980 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 8981 #define DMAMUX_CFR_CSOF1_Pos (1U)
AnnaBridge 172:65be27845400 8982 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 8983 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 8984 #define DMAMUX_CFR_CSOF2_Pos (2U)
AnnaBridge 172:65be27845400 8985 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 8986 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 8987 #define DMAMUX_CFR_CSOF3_Pos (3U)
AnnaBridge 172:65be27845400 8988 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 8989 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 8990 #define DMAMUX_CFR_CSOF4_Pos (4U)
AnnaBridge 172:65be27845400 8991 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 8992 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 8993 #define DMAMUX_CFR_CSOF5_Pos (5U)
AnnaBridge 172:65be27845400 8994 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 8995 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 8996 #define DMAMUX_CFR_CSOF6_Pos (6U)
AnnaBridge 172:65be27845400 8997 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 8998 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 8999 #define DMAMUX_CFR_CSOF7_Pos (7U)
AnnaBridge 172:65be27845400 9000 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9001 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9002 #define DMAMUX_CFR_CSOF8_Pos (8U)
AnnaBridge 172:65be27845400 9003 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9004 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9005 #define DMAMUX_CFR_CSOF9_Pos (9U)
AnnaBridge 172:65be27845400 9006 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9007 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9008 #define DMAMUX_CFR_CSOF10_Pos (10U)
AnnaBridge 172:65be27845400 9009 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9010 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9011 #define DMAMUX_CFR_CSOF11_Pos (11U)
AnnaBridge 172:65be27845400 9012 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9013 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9014 #define DMAMUX_CFR_CSOF12_Pos (12U)
AnnaBridge 172:65be27845400 9015 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9016 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9017 #define DMAMUX_CFR_CSOF13_Pos (13U)
AnnaBridge 172:65be27845400 9018 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9019 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9020 #define DMAMUX_CFR_CSOF14_Pos (14U)
AnnaBridge 172:65be27845400 9021 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9022 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9023 #define DMAMUX_CFR_CSOF15_Pos (15U)
AnnaBridge 172:65be27845400 9024 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9025 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
AnnaBridge 172:65be27845400 9026
AnnaBridge 172:65be27845400 9027 /******************** Bits definition for DMAMUX_RGxCR register ************/
AnnaBridge 172:65be27845400 9028 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
AnnaBridge 172:65be27845400 9029 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 9030 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
AnnaBridge 172:65be27845400 9031 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9032 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9033 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9034 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9035 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9036 #define DMAMUX_RGxCR_OIE_Pos (8U)
AnnaBridge 172:65be27845400 9037 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9038 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
AnnaBridge 172:65be27845400 9039 #define DMAMUX_RGxCR_GE_Pos (16U)
AnnaBridge 172:65be27845400 9040 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9041 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
AnnaBridge 172:65be27845400 9042 #define DMAMUX_RGxCR_GPOL_Pos (17U)
AnnaBridge 172:65be27845400 9043 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 9044 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
AnnaBridge 172:65be27845400 9045 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9046 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9047 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
AnnaBridge 172:65be27845400 9048 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
AnnaBridge 172:65be27845400 9049 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
AnnaBridge 172:65be27845400 9050 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9051 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9052 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9053 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9054 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9055
AnnaBridge 172:65be27845400 9056 /******************** Bits definition for DMAMUX_RGSR register **************/
AnnaBridge 172:65be27845400 9057 #define DMAMUX_RGSR_OF0_Pos (0U)
AnnaBridge 172:65be27845400 9058 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9059 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9060 #define DMAMUX_RGSR_OF1_Pos (1U)
AnnaBridge 172:65be27845400 9061 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9062 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9063 #define DMAMUX_RGSR_OF2_Pos (2U)
AnnaBridge 172:65be27845400 9064 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9065 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9066 #define DMAMUX_RGSR_OF3_Pos (3U)
AnnaBridge 172:65be27845400 9067 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9068 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9069 #define DMAMUX_RGSR_OF4_Pos (4U)
AnnaBridge 172:65be27845400 9070 #define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9071 #define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9072 #define DMAMUX_RGSR_OF5_Pos (5U)
AnnaBridge 172:65be27845400 9073 #define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9074 #define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9075 #define DMAMUX_RGSR_OF6_Pos (6U)
AnnaBridge 172:65be27845400 9076 #define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9077 #define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9078 #define DMAMUX_RGSR_OF7_Pos (7U)
AnnaBridge 172:65be27845400 9079 #define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9080 #define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
AnnaBridge 172:65be27845400 9081
AnnaBridge 172:65be27845400 9082 /******************** Bits definition for DMAMUX_RGCFR register **************/
AnnaBridge 172:65be27845400 9083 #define DMAMUX_RGCFR_COF0_Pos (0U)
AnnaBridge 172:65be27845400 9084 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9085 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9086 #define DMAMUX_RGCFR_COF1_Pos (1U)
AnnaBridge 172:65be27845400 9087 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9088 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9089 #define DMAMUX_RGCFR_COF2_Pos (2U)
AnnaBridge 172:65be27845400 9090 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9091 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9092 #define DMAMUX_RGCFR_COF3_Pos (3U)
AnnaBridge 172:65be27845400 9093 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9094 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9095 #define DMAMUX_RGCFR_COF4_Pos (4U)
AnnaBridge 172:65be27845400 9096 #define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9097 #define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9098 #define DMAMUX_RGCFR_COF5_Pos (5U)
AnnaBridge 172:65be27845400 9099 #define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9100 #define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9101 #define DMAMUX_RGCFR_COF6_Pos (6U)
AnnaBridge 172:65be27845400 9102 #define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9103 #define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9104 #define DMAMUX_RGCFR_COF7_Pos (7U)
AnnaBridge 172:65be27845400 9105 #define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9106 #define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
AnnaBridge 172:65be27845400 9107
AnnaBridge 172:65be27845400 9108 /******************************************************************************/
AnnaBridge 172:65be27845400 9109 /* */
AnnaBridge 172:65be27845400 9110 /* AHB Master DMA2D Controller (DMA2D) */
AnnaBridge 172:65be27845400 9111 /* */
AnnaBridge 172:65be27845400 9112 /******************************************************************************/
AnnaBridge 172:65be27845400 9113
AnnaBridge 172:65be27845400 9114 /******************** Bit definition for DMA2D_CR register ******************/
AnnaBridge 172:65be27845400 9115
AnnaBridge 172:65be27845400 9116 #define DMA2D_CR_START_Pos (0U)
AnnaBridge 172:65be27845400 9117 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9118 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
AnnaBridge 172:65be27845400 9119 #define DMA2D_CR_SUSP_Pos (1U)
AnnaBridge 172:65be27845400 9120 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9121 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
AnnaBridge 172:65be27845400 9122 #define DMA2D_CR_ABORT_Pos (2U)
AnnaBridge 172:65be27845400 9123 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9124 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
AnnaBridge 172:65be27845400 9125 #define DMA2D_CR_TEIE_Pos (8U)
AnnaBridge 172:65be27845400 9126 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9127 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 172:65be27845400 9128 #define DMA2D_CR_TCIE_Pos (9U)
AnnaBridge 172:65be27845400 9129 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9130 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 172:65be27845400 9131 #define DMA2D_CR_TWIE_Pos (10U)
AnnaBridge 172:65be27845400 9132 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9133 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
AnnaBridge 172:65be27845400 9134 #define DMA2D_CR_CAEIE_Pos (11U)
AnnaBridge 172:65be27845400 9135 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9136 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
AnnaBridge 172:65be27845400 9137 #define DMA2D_CR_CTCIE_Pos (12U)
AnnaBridge 172:65be27845400 9138 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9139 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
AnnaBridge 172:65be27845400 9140 #define DMA2D_CR_CEIE_Pos (13U)
AnnaBridge 172:65be27845400 9141 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9142 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
AnnaBridge 172:65be27845400 9143 #define DMA2D_CR_MODE_Pos (16U)
AnnaBridge 172:65be27845400 9144 #define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9145 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
AnnaBridge 172:65be27845400 9146 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9147 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9148
AnnaBridge 172:65be27845400 9149 /******************** Bit definition for DMA2D_ISR register *****************/
AnnaBridge 172:65be27845400 9150
AnnaBridge 172:65be27845400 9151 #define DMA2D_ISR_TEIF_Pos (0U)
AnnaBridge 172:65be27845400 9152 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9153 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 9154 #define DMA2D_ISR_TCIF_Pos (1U)
AnnaBridge 172:65be27845400 9155 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9156 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 9157 #define DMA2D_ISR_TWIF_Pos (2U)
AnnaBridge 172:65be27845400 9158 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9159 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
AnnaBridge 172:65be27845400 9160 #define DMA2D_ISR_CAEIF_Pos (3U)
AnnaBridge 172:65be27845400 9161 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9162 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
AnnaBridge 172:65be27845400 9163 #define DMA2D_ISR_CTCIF_Pos (4U)
AnnaBridge 172:65be27845400 9164 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9165 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 9166 #define DMA2D_ISR_CEIF_Pos (5U)
AnnaBridge 172:65be27845400 9167 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9168 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
AnnaBridge 172:65be27845400 9169
AnnaBridge 172:65be27845400 9170 /******************** Bit definition for DMA2D_IFCR register ****************/
AnnaBridge 172:65be27845400 9171
AnnaBridge 172:65be27845400 9172 #define DMA2D_IFCR_CTEIF_Pos (0U)
AnnaBridge 172:65be27845400 9173 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9174 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 9175 #define DMA2D_IFCR_CTCIF_Pos (1U)
AnnaBridge 172:65be27845400 9176 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9177 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 9178 #define DMA2D_IFCR_CTWIF_Pos (2U)
AnnaBridge 172:65be27845400 9179 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9180 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 172:65be27845400 9181 #define DMA2D_IFCR_CAECIF_Pos (3U)
AnnaBridge 172:65be27845400 9182 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9183 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 172:65be27845400 9184 #define DMA2D_IFCR_CCTCIF_Pos (4U)
AnnaBridge 172:65be27845400 9185 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9186 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 172:65be27845400 9187 #define DMA2D_IFCR_CCEIF_Pos (5U)
AnnaBridge 172:65be27845400 9188 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9189 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
AnnaBridge 172:65be27845400 9190
AnnaBridge 172:65be27845400 9191 /******************** Bit definition for DMA2D_FGMAR register ***************/
AnnaBridge 172:65be27845400 9192
AnnaBridge 172:65be27845400 9193 #define DMA2D_FGMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 9194 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 9195 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
AnnaBridge 172:65be27845400 9196
AnnaBridge 172:65be27845400 9197 /******************** Bit definition for DMA2D_FGOR register ****************/
AnnaBridge 172:65be27845400 9198
AnnaBridge 172:65be27845400 9199 #define DMA2D_FGOR_LO_Pos (0U)
AnnaBridge 172:65be27845400 9200 #define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 9201 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
AnnaBridge 172:65be27845400 9202
AnnaBridge 172:65be27845400 9203 /******************** Bit definition for DMA2D_BGMAR register ***************/
AnnaBridge 172:65be27845400 9204
AnnaBridge 172:65be27845400 9205 #define DMA2D_BGMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 9206 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 9207 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
AnnaBridge 172:65be27845400 9208
AnnaBridge 172:65be27845400 9209 /******************** Bit definition for DMA2D_BGOR register ****************/
AnnaBridge 172:65be27845400 9210
AnnaBridge 172:65be27845400 9211 #define DMA2D_BGOR_LO_Pos (0U)
AnnaBridge 172:65be27845400 9212 #define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 9213 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
AnnaBridge 172:65be27845400 9214
AnnaBridge 172:65be27845400 9215 /******************** Bit definition for DMA2D_FGPFCCR register *************/
AnnaBridge 172:65be27845400 9216
AnnaBridge 172:65be27845400 9217 #define DMA2D_FGPFCCR_CM_Pos (0U)
AnnaBridge 172:65be27845400 9218 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 9219 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 172:65be27845400 9220 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9221 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9222 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9223 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9224 #define DMA2D_FGPFCCR_CCM_Pos (4U)
AnnaBridge 172:65be27845400 9225 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9226 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 172:65be27845400 9227 #define DMA2D_FGPFCCR_START_Pos (5U)
AnnaBridge 172:65be27845400 9228 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9229 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
AnnaBridge 172:65be27845400 9230 #define DMA2D_FGPFCCR_CS_Pos (8U)
AnnaBridge 172:65be27845400 9231 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 9232 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 172:65be27845400 9233 #define DMA2D_FGPFCCR_AM_Pos (16U)
AnnaBridge 172:65be27845400 9234 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9235 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 172:65be27845400 9236 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9237 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9238 #define DMA2D_FGPFCCR_CSS_Pos (18U)
AnnaBridge 172:65be27845400 9239 #define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9240 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
AnnaBridge 172:65be27845400 9241 #define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9242 #define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9243 #define DMA2D_FGPFCCR_AI_Pos (20U)
AnnaBridge 172:65be27845400 9244 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9245 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
AnnaBridge 172:65be27845400 9246 #define DMA2D_FGPFCCR_RBS_Pos (21U)
AnnaBridge 172:65be27845400 9247 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9248 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
AnnaBridge 172:65be27845400 9249 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
AnnaBridge 172:65be27845400 9250 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 9251 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
AnnaBridge 172:65be27845400 9252
AnnaBridge 172:65be27845400 9253 /******************** Bit definition for DMA2D_FGCOLR register **************/
AnnaBridge 172:65be27845400 9254
AnnaBridge 172:65be27845400 9255 #define DMA2D_FGCOLR_BLUE_Pos (0U)
AnnaBridge 172:65be27845400 9256 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 9257 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
AnnaBridge 172:65be27845400 9258 #define DMA2D_FGCOLR_GREEN_Pos (8U)
AnnaBridge 172:65be27845400 9259 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 9260 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
AnnaBridge 172:65be27845400 9261 #define DMA2D_FGCOLR_RED_Pos (16U)
AnnaBridge 172:65be27845400 9262 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 9263 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
AnnaBridge 172:65be27845400 9264
AnnaBridge 172:65be27845400 9265 /******************** Bit definition for DMA2D_BGPFCCR register *************/
AnnaBridge 172:65be27845400 9266
AnnaBridge 172:65be27845400 9267 #define DMA2D_BGPFCCR_CM_Pos (0U)
AnnaBridge 172:65be27845400 9268 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 9269 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 172:65be27845400 9270 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9271 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9272 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9273 #define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9274 #define DMA2D_BGPFCCR_CCM_Pos (4U)
AnnaBridge 172:65be27845400 9275 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9276 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 172:65be27845400 9277 #define DMA2D_BGPFCCR_START_Pos (5U)
AnnaBridge 172:65be27845400 9278 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9279 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
AnnaBridge 172:65be27845400 9280 #define DMA2D_BGPFCCR_CS_Pos (8U)
AnnaBridge 172:65be27845400 9281 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 9282 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 172:65be27845400 9283 #define DMA2D_BGPFCCR_AM_Pos (16U)
AnnaBridge 172:65be27845400 9284 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9285 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 172:65be27845400 9286 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9287 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9288 #define DMA2D_BGPFCCR_AI_Pos (20U)
AnnaBridge 172:65be27845400 9289 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9290 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
AnnaBridge 172:65be27845400 9291 #define DMA2D_BGPFCCR_RBS_Pos (21U)
AnnaBridge 172:65be27845400 9292 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9293 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
AnnaBridge 172:65be27845400 9294 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
AnnaBridge 172:65be27845400 9295 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 9296 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
AnnaBridge 172:65be27845400 9297
AnnaBridge 172:65be27845400 9298 /******************** Bit definition for DMA2D_BGCOLR register **************/
AnnaBridge 172:65be27845400 9299
AnnaBridge 172:65be27845400 9300 #define DMA2D_BGCOLR_BLUE_Pos (0U)
AnnaBridge 172:65be27845400 9301 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 9302 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
AnnaBridge 172:65be27845400 9303 #define DMA2D_BGCOLR_GREEN_Pos (8U)
AnnaBridge 172:65be27845400 9304 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 9305 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
AnnaBridge 172:65be27845400 9306 #define DMA2D_BGCOLR_RED_Pos (16U)
AnnaBridge 172:65be27845400 9307 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 9308 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
AnnaBridge 172:65be27845400 9309
AnnaBridge 172:65be27845400 9310 /******************** Bit definition for DMA2D_FGCMAR register **************/
AnnaBridge 172:65be27845400 9311
AnnaBridge 172:65be27845400 9312 #define DMA2D_FGCMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 9313 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 9314 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
AnnaBridge 172:65be27845400 9315
AnnaBridge 172:65be27845400 9316 /******************** Bit definition for DMA2D_BGCMAR register **************/
AnnaBridge 172:65be27845400 9317
AnnaBridge 172:65be27845400 9318 #define DMA2D_BGCMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 9319 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 9320 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
AnnaBridge 172:65be27845400 9321
AnnaBridge 172:65be27845400 9322 /******************** Bit definition for DMA2D_OPFCCR register **************/
AnnaBridge 172:65be27845400 9323
AnnaBridge 172:65be27845400 9324 #define DMA2D_OPFCCR_CM_Pos (0U)
AnnaBridge 172:65be27845400 9325 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 9326 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
AnnaBridge 172:65be27845400 9327 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9328 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9329 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9330 #define DMA2D_OPFCCR_AI_Pos (20U)
AnnaBridge 172:65be27845400 9331 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9332 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
AnnaBridge 172:65be27845400 9333 #define DMA2D_OPFCCR_RBS_Pos (21U)
AnnaBridge 172:65be27845400 9334 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9335 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
AnnaBridge 172:65be27845400 9336
AnnaBridge 172:65be27845400 9337 /******************** Bit definition for DMA2D_OCOLR register ***************/
AnnaBridge 172:65be27845400 9338
AnnaBridge 172:65be27845400 9339 /*!<Mode_ARGB8888/RGB888 */
AnnaBridge 172:65be27845400 9340
AnnaBridge 172:65be27845400 9341 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FFU) /*!< Output BLUE Value */
AnnaBridge 172:65be27845400 9342 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00U) /*!< Output GREEN Value */
AnnaBridge 172:65be27845400 9343 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000U) /*!< Output Red Value */
AnnaBridge 172:65be27845400 9344 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000U) /*!< Output Alpha Channel Value */
AnnaBridge 172:65be27845400 9345
AnnaBridge 172:65be27845400 9346 /*!<Mode_RGB565 */
AnnaBridge 172:65be27845400 9347 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
AnnaBridge 172:65be27845400 9348 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0U) /*!< Output GREEN Value */
AnnaBridge 172:65be27845400 9349 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800U) /*!< Output Red Value */
AnnaBridge 172:65be27845400 9350
AnnaBridge 172:65be27845400 9351 /*!<Mode_ARGB1555 */
AnnaBridge 172:65be27845400 9352 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001FU) /*!< Output BLUE Value */
AnnaBridge 172:65be27845400 9353 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0U) /*!< Output GREEN Value */
AnnaBridge 172:65be27845400 9354 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00U) /*!< Output Red Value */
AnnaBridge 172:65be27845400 9355 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000U) /*!< Output Alpha Channel Value */
AnnaBridge 172:65be27845400 9356
AnnaBridge 172:65be27845400 9357 /*!<Mode_ARGB4444 */
AnnaBridge 172:65be27845400 9358 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000FU) /*!< Output BLUE Value */
AnnaBridge 172:65be27845400 9359 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0U) /*!< Output GREEN Value */
AnnaBridge 172:65be27845400 9360 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00U) /*!< Output Red Value */
AnnaBridge 172:65be27845400 9361 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000U) /*!< Output Alpha Channel Value */
AnnaBridge 172:65be27845400 9362
AnnaBridge 172:65be27845400 9363 /******************** Bit definition for DMA2D_OMAR register ****************/
AnnaBridge 172:65be27845400 9364
AnnaBridge 172:65be27845400 9365 #define DMA2D_OMAR_MA_Pos (0U)
AnnaBridge 172:65be27845400 9366 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 9367 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
AnnaBridge 172:65be27845400 9368
AnnaBridge 172:65be27845400 9369 /******************** Bit definition for DMA2D_OOR register *****************/
AnnaBridge 172:65be27845400 9370
AnnaBridge 172:65be27845400 9371 #define DMA2D_OOR_LO_Pos (0U)
AnnaBridge 172:65be27845400 9372 #define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 172:65be27845400 9373 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
AnnaBridge 172:65be27845400 9374
AnnaBridge 172:65be27845400 9375 /******************** Bit definition for DMA2D_NLR register *****************/
AnnaBridge 172:65be27845400 9376
AnnaBridge 172:65be27845400 9377 #define DMA2D_NLR_NL_Pos (0U)
AnnaBridge 172:65be27845400 9378 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 9379 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
AnnaBridge 172:65be27845400 9380 #define DMA2D_NLR_PL_Pos (16U)
AnnaBridge 172:65be27845400 9381 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
AnnaBridge 172:65be27845400 9382 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
AnnaBridge 172:65be27845400 9383
AnnaBridge 172:65be27845400 9384 /******************** Bit definition for DMA2D_LWR register *****************/
AnnaBridge 172:65be27845400 9385
AnnaBridge 172:65be27845400 9386 #define DMA2D_LWR_LW_Pos (0U)
AnnaBridge 172:65be27845400 9387 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 9388 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
AnnaBridge 172:65be27845400 9389
AnnaBridge 172:65be27845400 9390 /******************** Bit definition for DMA2D_AMTCR register ***************/
AnnaBridge 172:65be27845400 9391
AnnaBridge 172:65be27845400 9392 #define DMA2D_AMTCR_EN_Pos (0U)
AnnaBridge 172:65be27845400 9393 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9394 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
AnnaBridge 172:65be27845400 9395 #define DMA2D_AMTCR_DT_Pos (8U)
AnnaBridge 172:65be27845400 9396 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 9397 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
AnnaBridge 172:65be27845400 9398
AnnaBridge 172:65be27845400 9399
AnnaBridge 172:65be27845400 9400 /******************** Bit definition for DMA2D_FGCLUT register **************/
AnnaBridge 172:65be27845400 9401
AnnaBridge 172:65be27845400 9402 /******************** Bit definition for DMA2D_BGCLUT register **************/
AnnaBridge 172:65be27845400 9403
AnnaBridge 172:65be27845400 9404
AnnaBridge 172:65be27845400 9405 /******************************************************************************/
AnnaBridge 172:65be27845400 9406 /* */
AnnaBridge 172:65be27845400 9407 /* External Interrupt/Event Controller */
AnnaBridge 172:65be27845400 9408 /* */
AnnaBridge 172:65be27845400 9409 /******************************************************************************/
AnnaBridge 172:65be27845400 9410 /****************** Bit definition for EXTI_RTSR1 register *******************/
AnnaBridge 172:65be27845400 9411 #define EXTI_RTSR1_TR_Pos (0U)
AnnaBridge 172:65be27845400 9412 #define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
AnnaBridge 172:65be27845400 9413 #define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
AnnaBridge 172:65be27845400 9414 #define EXTI_RTSR1_TR0_Pos (0U)
AnnaBridge 172:65be27845400 9415 #define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9416 #define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 172:65be27845400 9417 #define EXTI_RTSR1_TR1_Pos (1U)
AnnaBridge 172:65be27845400 9418 #define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9419 #define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 172:65be27845400 9420 #define EXTI_RTSR1_TR2_Pos (2U)
AnnaBridge 172:65be27845400 9421 #define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9422 #define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 172:65be27845400 9423 #define EXTI_RTSR1_TR3_Pos (3U)
AnnaBridge 172:65be27845400 9424 #define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9425 #define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 172:65be27845400 9426 #define EXTI_RTSR1_TR4_Pos (4U)
AnnaBridge 172:65be27845400 9427 #define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9428 #define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 172:65be27845400 9429 #define EXTI_RTSR1_TR5_Pos (5U)
AnnaBridge 172:65be27845400 9430 #define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9431 #define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 172:65be27845400 9432 #define EXTI_RTSR1_TR6_Pos (6U)
AnnaBridge 172:65be27845400 9433 #define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9434 #define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 172:65be27845400 9435 #define EXTI_RTSR1_TR7_Pos (7U)
AnnaBridge 172:65be27845400 9436 #define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9437 #define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 172:65be27845400 9438 #define EXTI_RTSR1_TR8_Pos (8U)
AnnaBridge 172:65be27845400 9439 #define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9440 #define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 172:65be27845400 9441 #define EXTI_RTSR1_TR9_Pos (9U)
AnnaBridge 172:65be27845400 9442 #define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9443 #define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 172:65be27845400 9444 #define EXTI_RTSR1_TR10_Pos (10U)
AnnaBridge 172:65be27845400 9445 #define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9446 #define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 172:65be27845400 9447 #define EXTI_RTSR1_TR11_Pos (11U)
AnnaBridge 172:65be27845400 9448 #define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9449 #define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 172:65be27845400 9450 #define EXTI_RTSR1_TR12_Pos (12U)
AnnaBridge 172:65be27845400 9451 #define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9452 #define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 172:65be27845400 9453 #define EXTI_RTSR1_TR13_Pos (13U)
AnnaBridge 172:65be27845400 9454 #define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9455 #define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 172:65be27845400 9456 #define EXTI_RTSR1_TR14_Pos (14U)
AnnaBridge 172:65be27845400 9457 #define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9458 #define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 172:65be27845400 9459 #define EXTI_RTSR1_TR15_Pos (15U)
AnnaBridge 172:65be27845400 9460 #define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9461 #define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 172:65be27845400 9462 #define EXTI_RTSR1_TR16_Pos (16U)
AnnaBridge 172:65be27845400 9463 #define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9464 #define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 172:65be27845400 9465 #define EXTI_RTSR1_TR17_Pos (17U)
AnnaBridge 172:65be27845400 9466 #define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9467 #define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 172:65be27845400 9468 #define EXTI_RTSR1_TR18_Pos (18U)
AnnaBridge 172:65be27845400 9469 #define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9470 #define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 172:65be27845400 9471 #define EXTI_RTSR1_TR19_Pos (19U)
AnnaBridge 172:65be27845400 9472 #define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9473 #define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 172:65be27845400 9474 #define EXTI_RTSR1_TR20_Pos (20U)
AnnaBridge 172:65be27845400 9475 #define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9476 #define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 172:65be27845400 9477 #define EXTI_RTSR1_TR21_Pos (21U)
AnnaBridge 172:65be27845400 9478 #define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9479 #define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 172:65be27845400 9480
AnnaBridge 172:65be27845400 9481 /****************** Bit definition for EXTI_FTSR1 register *******************/
AnnaBridge 172:65be27845400 9482 #define EXTI_FTSR1_TR_Pos (0U)
AnnaBridge 172:65be27845400 9483 #define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
AnnaBridge 172:65be27845400 9484 #define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
AnnaBridge 172:65be27845400 9485 #define EXTI_FTSR1_TR0_Pos (0U)
AnnaBridge 172:65be27845400 9486 #define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9487 #define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 172:65be27845400 9488 #define EXTI_FTSR1_TR1_Pos (1U)
AnnaBridge 172:65be27845400 9489 #define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9490 #define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 172:65be27845400 9491 #define EXTI_FTSR1_TR2_Pos (2U)
AnnaBridge 172:65be27845400 9492 #define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9493 #define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 172:65be27845400 9494 #define EXTI_FTSR1_TR3_Pos (3U)
AnnaBridge 172:65be27845400 9495 #define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9496 #define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 172:65be27845400 9497 #define EXTI_FTSR1_TR4_Pos (4U)
AnnaBridge 172:65be27845400 9498 #define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9499 #define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 172:65be27845400 9500 #define EXTI_FTSR1_TR5_Pos (5U)
AnnaBridge 172:65be27845400 9501 #define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9502 #define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 172:65be27845400 9503 #define EXTI_FTSR1_TR6_Pos (6U)
AnnaBridge 172:65be27845400 9504 #define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9505 #define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 172:65be27845400 9506 #define EXTI_FTSR1_TR7_Pos (7U)
AnnaBridge 172:65be27845400 9507 #define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9508 #define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 172:65be27845400 9509 #define EXTI_FTSR1_TR8_Pos (8U)
AnnaBridge 172:65be27845400 9510 #define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9511 #define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 172:65be27845400 9512 #define EXTI_FTSR1_TR9_Pos (9U)
AnnaBridge 172:65be27845400 9513 #define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9514 #define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 172:65be27845400 9515 #define EXTI_FTSR1_TR10_Pos (10U)
AnnaBridge 172:65be27845400 9516 #define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9517 #define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 172:65be27845400 9518 #define EXTI_FTSR1_TR11_Pos (11U)
AnnaBridge 172:65be27845400 9519 #define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9520 #define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 172:65be27845400 9521 #define EXTI_FTSR1_TR12_Pos (12U)
AnnaBridge 172:65be27845400 9522 #define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9523 #define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 172:65be27845400 9524 #define EXTI_FTSR1_TR13_Pos (13U)
AnnaBridge 172:65be27845400 9525 #define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9526 #define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 172:65be27845400 9527 #define EXTI_FTSR1_TR14_Pos (14U)
AnnaBridge 172:65be27845400 9528 #define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9529 #define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 172:65be27845400 9530 #define EXTI_FTSR1_TR15_Pos (15U)
AnnaBridge 172:65be27845400 9531 #define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9532 #define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 172:65be27845400 9533 #define EXTI_FTSR1_TR16_Pos (16U)
AnnaBridge 172:65be27845400 9534 #define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9535 #define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 172:65be27845400 9536 #define EXTI_FTSR1_TR17_Pos (17U)
AnnaBridge 172:65be27845400 9537 #define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9538 #define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 172:65be27845400 9539 #define EXTI_FTSR1_TR18_Pos (18U)
AnnaBridge 172:65be27845400 9540 #define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9541 #define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 172:65be27845400 9542 #define EXTI_FTSR1_TR19_Pos (19U)
AnnaBridge 172:65be27845400 9543 #define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9544 #define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 172:65be27845400 9545 #define EXTI_FTSR1_TR20_Pos (20U)
AnnaBridge 172:65be27845400 9546 #define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9547 #define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 172:65be27845400 9548 #define EXTI_FTSR1_TR21_Pos (21U)
AnnaBridge 172:65be27845400 9549 #define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9550 #define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 172:65be27845400 9551
AnnaBridge 172:65be27845400 9552 /****************** Bit definition for EXTI_SWIER1 register ******************/
AnnaBridge 172:65be27845400 9553 #define EXTI_SWIER1_SWIER0_Pos (0U)
AnnaBridge 172:65be27845400 9554 #define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9555 #define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 172:65be27845400 9556 #define EXTI_SWIER1_SWIER1_Pos (1U)
AnnaBridge 172:65be27845400 9557 #define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9558 #define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 172:65be27845400 9559 #define EXTI_SWIER1_SWIER2_Pos (2U)
AnnaBridge 172:65be27845400 9560 #define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9561 #define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 172:65be27845400 9562 #define EXTI_SWIER1_SWIER3_Pos (3U)
AnnaBridge 172:65be27845400 9563 #define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9564 #define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 172:65be27845400 9565 #define EXTI_SWIER1_SWIER4_Pos (4U)
AnnaBridge 172:65be27845400 9566 #define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9567 #define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 172:65be27845400 9568 #define EXTI_SWIER1_SWIER5_Pos (5U)
AnnaBridge 172:65be27845400 9569 #define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9570 #define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 172:65be27845400 9571 #define EXTI_SWIER1_SWIER6_Pos (6U)
AnnaBridge 172:65be27845400 9572 #define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9573 #define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 172:65be27845400 9574 #define EXTI_SWIER1_SWIER7_Pos (7U)
AnnaBridge 172:65be27845400 9575 #define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9576 #define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 172:65be27845400 9577 #define EXTI_SWIER1_SWIER8_Pos (8U)
AnnaBridge 172:65be27845400 9578 #define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9579 #define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 172:65be27845400 9580 #define EXTI_SWIER1_SWIER9_Pos (9U)
AnnaBridge 172:65be27845400 9581 #define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9582 #define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 172:65be27845400 9583 #define EXTI_SWIER1_SWIER10_Pos (10U)
AnnaBridge 172:65be27845400 9584 #define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9585 #define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 172:65be27845400 9586 #define EXTI_SWIER1_SWIER11_Pos (11U)
AnnaBridge 172:65be27845400 9587 #define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9588 #define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 172:65be27845400 9589 #define EXTI_SWIER1_SWIER12_Pos (12U)
AnnaBridge 172:65be27845400 9590 #define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9591 #define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 172:65be27845400 9592 #define EXTI_SWIER1_SWIER13_Pos (13U)
AnnaBridge 172:65be27845400 9593 #define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9594 #define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 172:65be27845400 9595 #define EXTI_SWIER1_SWIER14_Pos (14U)
AnnaBridge 172:65be27845400 9596 #define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9597 #define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 172:65be27845400 9598 #define EXTI_SWIER1_SWIER15_Pos (15U)
AnnaBridge 172:65be27845400 9599 #define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9600 #define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 172:65be27845400 9601 #define EXTI_SWIER1_SWIER16_Pos (16U)
AnnaBridge 172:65be27845400 9602 #define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9603 #define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 172:65be27845400 9604 #define EXTI_SWIER1_SWIER17_Pos (17U)
AnnaBridge 172:65be27845400 9605 #define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9606 #define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 172:65be27845400 9607 #define EXTI_SWIER1_SWIER18_Pos (18U)
AnnaBridge 172:65be27845400 9608 #define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9609 #define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 172:65be27845400 9610 #define EXTI_SWIER1_SWIER19_Pos (19U)
AnnaBridge 172:65be27845400 9611 #define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9612 #define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 172:65be27845400 9613 #define EXTI_SWIER1_SWIER20_Pos (20U)
AnnaBridge 172:65be27845400 9614 #define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9615 #define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 172:65be27845400 9616 #define EXTI_SWIER1_SWIER21_Pos (21U)
AnnaBridge 172:65be27845400 9617 #define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9618 #define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 172:65be27845400 9619
AnnaBridge 172:65be27845400 9620 /****************** Bit definition for EXTI_D3PMR1 register ******************/
AnnaBridge 172:65be27845400 9621 #define EXTI_D3PMR1_MR0_Pos (0U)
AnnaBridge 172:65be27845400 9622 #define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9623 #define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
AnnaBridge 172:65be27845400 9624 #define EXTI_D3PMR1_MR1_Pos (1U)
AnnaBridge 172:65be27845400 9625 #define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9626 #define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
AnnaBridge 172:65be27845400 9627 #define EXTI_D3PMR1_MR2_Pos (2U)
AnnaBridge 172:65be27845400 9628 #define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9629 #define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
AnnaBridge 172:65be27845400 9630 #define EXTI_D3PMR1_MR3_Pos (3U)
AnnaBridge 172:65be27845400 9631 #define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9632 #define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
AnnaBridge 172:65be27845400 9633 #define EXTI_D3PMR1_MR4_Pos (4U)
AnnaBridge 172:65be27845400 9634 #define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9635 #define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
AnnaBridge 172:65be27845400 9636 #define EXTI_D3PMR1_MR5_Pos (5U)
AnnaBridge 172:65be27845400 9637 #define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9638 #define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
AnnaBridge 172:65be27845400 9639 #define EXTI_D3PMR1_MR6_Pos (6U)
AnnaBridge 172:65be27845400 9640 #define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9641 #define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
AnnaBridge 172:65be27845400 9642 #define EXTI_D3PMR1_MR7_Pos (7U)
AnnaBridge 172:65be27845400 9643 #define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9644 #define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
AnnaBridge 172:65be27845400 9645 #define EXTI_D3PMR1_MR8_Pos (8U)
AnnaBridge 172:65be27845400 9646 #define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9647 #define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
AnnaBridge 172:65be27845400 9648 #define EXTI_D3PMR1_MR9_Pos (9U)
AnnaBridge 172:65be27845400 9649 #define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9650 #define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
AnnaBridge 172:65be27845400 9651 #define EXTI_D3PMR1_MR10_Pos (10U)
AnnaBridge 172:65be27845400 9652 #define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9653 #define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
AnnaBridge 172:65be27845400 9654 #define EXTI_D3PMR1_MR11_Pos (11U)
AnnaBridge 172:65be27845400 9655 #define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9656 #define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
AnnaBridge 172:65be27845400 9657 #define EXTI_D3PMR1_MR12_Pos (12U)
AnnaBridge 172:65be27845400 9658 #define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9659 #define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
AnnaBridge 172:65be27845400 9660 #define EXTI_D3PMR1_MR13_Pos (13U)
AnnaBridge 172:65be27845400 9661 #define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9662 #define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
AnnaBridge 172:65be27845400 9663 #define EXTI_D3PMR1_MR14_Pos (14U)
AnnaBridge 172:65be27845400 9664 #define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9665 #define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
AnnaBridge 172:65be27845400 9666 #define EXTI_D3PMR1_MR15_Pos (15U)
AnnaBridge 172:65be27845400 9667 #define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9668 #define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
AnnaBridge 172:65be27845400 9669 #define EXTI_D3PMR1_MR19_Pos (19U)
AnnaBridge 172:65be27845400 9670 #define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9671 #define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
AnnaBridge 172:65be27845400 9672 #define EXTI_D3PMR1_MR20_Pos (20U)
AnnaBridge 172:65be27845400 9673 #define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9674 #define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
AnnaBridge 172:65be27845400 9675 #define EXTI_D3PMR1_MR21_Pos (21U)
AnnaBridge 172:65be27845400 9676 #define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9677 #define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
AnnaBridge 172:65be27845400 9678 #define EXTI_D3PMR1_MR25_Pos (24U)
AnnaBridge 172:65be27845400 9679 #define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9680 #define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
AnnaBridge 172:65be27845400 9681
AnnaBridge 172:65be27845400 9682 /******************* Bit definition for EXTI_D3PCR1L register ****************/
AnnaBridge 172:65be27845400 9683 #define EXTI_D3PCR1L_PCS0_Pos (0U)
AnnaBridge 172:65be27845400 9684 #define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 9685 #define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
AnnaBridge 172:65be27845400 9686 #define EXTI_D3PCR1L_PCS1_Pos (2U)
AnnaBridge 172:65be27845400 9687 #define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9688 #define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
AnnaBridge 172:65be27845400 9689 #define EXTI_D3PCR1L_PCS2_Pos (4U)
AnnaBridge 172:65be27845400 9690 #define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 9691 #define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
AnnaBridge 172:65be27845400 9692 #define EXTI_D3PCR1L_PCS3_Pos (6U)
AnnaBridge 172:65be27845400 9693 #define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9694 #define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
AnnaBridge 172:65be27845400 9695 #define EXTI_D3PCR1L_PCS4_Pos (8U)
AnnaBridge 172:65be27845400 9696 #define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 9697 #define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
AnnaBridge 172:65be27845400 9698 #define EXTI_D3PCR1L_PCS5_Pos (10U)
AnnaBridge 172:65be27845400 9699 #define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 9700 #define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */
AnnaBridge 172:65be27845400 9701 #define EXTI_D3PCR1L_PCS6_Pos (12U)
AnnaBridge 172:65be27845400 9702 #define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 9703 #define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */
AnnaBridge 172:65be27845400 9704 #define EXTI_D3PCR1L_PCS7_Pos (14U)
AnnaBridge 172:65be27845400 9705 #define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 9706 #define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */
AnnaBridge 172:65be27845400 9707 #define EXTI_D3PCR1L_PCS8_Pos (16U)
AnnaBridge 172:65be27845400 9708 #define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 9709 #define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */
AnnaBridge 172:65be27845400 9710 #define EXTI_D3PCR1L_PCS9_Pos (18U)
AnnaBridge 172:65be27845400 9711 #define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9712 #define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */
AnnaBridge 172:65be27845400 9713 #define EXTI_D3PCR1L_PCS10_Pos (20U)
AnnaBridge 172:65be27845400 9714 #define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 9715 #define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/
AnnaBridge 172:65be27845400 9716 #define EXTI_D3PCR1L_PCS11_Pos (22U)
AnnaBridge 172:65be27845400 9717 #define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 9718 #define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/
AnnaBridge 172:65be27845400 9719 #define EXTI_D3PCR1L_PCS12_Pos (24U)
AnnaBridge 172:65be27845400 9720 #define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 9721 #define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/
AnnaBridge 172:65be27845400 9722 #define EXTI_D3PCR1L_PCS13_Pos (26U)
AnnaBridge 172:65be27845400 9723 #define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 9724 #define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/
AnnaBridge 172:65be27845400 9725 #define EXTI_D3PCR1L_PCS14_Pos (28U)
AnnaBridge 172:65be27845400 9726 #define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 9727 #define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/
AnnaBridge 172:65be27845400 9728 #define EXTI_D3PCR1L_PCS15_Pos (30U)
AnnaBridge 172:65be27845400 9729 #define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 9730 #define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/
AnnaBridge 172:65be27845400 9731
AnnaBridge 172:65be27845400 9732 /******************* Bit definition for EXTI_D3PCR1H register ****************/
AnnaBridge 172:65be27845400 9733 #define EXTI_D3PCR1H_PCS19_Pos (6U)
AnnaBridge 172:65be27845400 9734 #define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9735 #define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */
AnnaBridge 172:65be27845400 9736 #define EXTI_D3PCR1H_PCS20_Pos (8U)
AnnaBridge 172:65be27845400 9737 #define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 9738 #define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */
AnnaBridge 172:65be27845400 9739 #define EXTI_D3PCR1H_PCS21_Pos (10U)
AnnaBridge 172:65be27845400 9740 #define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 9741 #define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */
AnnaBridge 172:65be27845400 9742 #define EXTI_D3PCR1H_PCS25_Pos (18U)
AnnaBridge 172:65be27845400 9743 #define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9744 #define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */
AnnaBridge 172:65be27845400 9745
AnnaBridge 172:65be27845400 9746 /****************** Bit definition for EXTI_RTSR2 register *******************/
AnnaBridge 172:65be27845400 9747 #define EXTI_RTSR2_TR_Pos (17U)
AnnaBridge 172:65be27845400 9748 #define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */
AnnaBridge 172:65be27845400 9749 #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
AnnaBridge 172:65be27845400 9750 #define EXTI_RTSR2_TR49_Pos (17U)
AnnaBridge 172:65be27845400 9751 #define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9752 #define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
AnnaBridge 172:65be27845400 9753 #define EXTI_RTSR2_TR51_Pos (19U)
AnnaBridge 172:65be27845400 9754 #define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9755 #define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
AnnaBridge 172:65be27845400 9756
AnnaBridge 172:65be27845400 9757 /****************** Bit definition for EXTI_FTSR2 register *******************/
AnnaBridge 172:65be27845400 9758 #define EXTI_FTSR2_TR_Pos (17U)
AnnaBridge 172:65be27845400 9759 #define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */
AnnaBridge 172:65be27845400 9760 #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
AnnaBridge 172:65be27845400 9761 #define EXTI_FTSR2_TR49_Pos (17U)
AnnaBridge 172:65be27845400 9762 #define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9763 #define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
AnnaBridge 172:65be27845400 9764 #define EXTI_FTSR2_TR51_Pos (19U)
AnnaBridge 172:65be27845400 9765 #define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9766 #define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
AnnaBridge 172:65be27845400 9767
AnnaBridge 172:65be27845400 9768 /****************** Bit definition for EXTI_SWIER2 register ******************/
AnnaBridge 172:65be27845400 9769 #define EXTI_SWIER2_SWIER49_Pos (17U)
AnnaBridge 172:65be27845400 9770 #define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9771 #define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
AnnaBridge 172:65be27845400 9772 #define EXTI_SWIER2_SWIER51_Pos (19U)
AnnaBridge 172:65be27845400 9773 #define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9774 #define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
AnnaBridge 172:65be27845400 9775
AnnaBridge 172:65be27845400 9776 /****************** Bit definition for EXTI_D3PMR2 register ******************/
AnnaBridge 172:65be27845400 9777 #define EXTI_D3PMR2_MR34_Pos (2U)
AnnaBridge 172:65be27845400 9778 #define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9779 #define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
AnnaBridge 172:65be27845400 9780 #define EXTI_D3PMR2_MR35_Pos (3U)
AnnaBridge 172:65be27845400 9781 #define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9782 #define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
AnnaBridge 172:65be27845400 9783 #define EXTI_D3PMR2_MR41_Pos (9U)
AnnaBridge 172:65be27845400 9784 #define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9785 #define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
AnnaBridge 172:65be27845400 9786 #define EXTI_D3PMR2_MR48_Pos (16U)
AnnaBridge 172:65be27845400 9787 #define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9788 #define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
AnnaBridge 172:65be27845400 9789 #define EXTI_D3PMR2_MR49_Pos (17U)
AnnaBridge 172:65be27845400 9790 #define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9791 #define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
AnnaBridge 172:65be27845400 9792 #define EXTI_D3PMR2_MR50_Pos (18U)
AnnaBridge 172:65be27845400 9793 #define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9794 #define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
AnnaBridge 172:65be27845400 9795 #define EXTI_D3PMR2_MR51_Pos (19U)
AnnaBridge 172:65be27845400 9796 #define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9797 #define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
AnnaBridge 172:65be27845400 9798 #define EXTI_D3PMR2_MR52_Pos (20U)
AnnaBridge 172:65be27845400 9799 #define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9800 #define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk /*!< Pending Mask Event for line 52 */
AnnaBridge 172:65be27845400 9801 #define EXTI_D3PMR2_MR53_Pos (21U)
AnnaBridge 172:65be27845400 9802 #define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9803 #define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk /*!< Pending Mask Event for line 53 */
AnnaBridge 172:65be27845400 9804 /******************* Bit definition for EXTI_D3PCR2L register ****************/
AnnaBridge 172:65be27845400 9805 #define EXTI_D3PCR2L_PCS34_Pos (4U)
AnnaBridge 172:65be27845400 9806 #define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 9807 #define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */
AnnaBridge 172:65be27845400 9808 #define EXTI_D3PCR2L_PCS35_Pos (6U)
AnnaBridge 172:65be27845400 9809 #define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9810 #define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */
AnnaBridge 172:65be27845400 9811 #define EXTI_D3PCR2L_PCS41_Pos (18U)
AnnaBridge 172:65be27845400 9812 #define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 9813 #define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */
AnnaBridge 172:65be27845400 9814
AnnaBridge 172:65be27845400 9815
AnnaBridge 172:65be27845400 9816 /******************* Bit definition for EXTI_D3PCR2H register ****************/
AnnaBridge 172:65be27845400 9817 #define EXTI_D3PCR2H_PCS48_Pos (0U)
AnnaBridge 172:65be27845400 9818 #define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 9819 #define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */
AnnaBridge 172:65be27845400 9820 #define EXTI_D3PCR2H_PCS49_Pos (2U)
AnnaBridge 172:65be27845400 9821 #define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 9822 #define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */
AnnaBridge 172:65be27845400 9823 #define EXTI_D3PCR2H_PCS50_Pos (4U)
AnnaBridge 172:65be27845400 9824 #define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 9825 #define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */
AnnaBridge 172:65be27845400 9826 #define EXTI_D3PCR2H_PCS51_Pos (6U)
AnnaBridge 172:65be27845400 9827 #define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 9828 #define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */
AnnaBridge 172:65be27845400 9829 #define EXTI_D3PCR2H_PCS52_Pos (8U)
AnnaBridge 172:65be27845400 9830 #define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 9831 #define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk /*!< D3 Pending request clear input signal selection on line 52 */
AnnaBridge 172:65be27845400 9832 #define EXTI_D3PCR2H_PCS53_Pos (10U)
AnnaBridge 172:65be27845400 9833 #define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 9834 #define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk /*!< D3 Pending request clear input signal selection on line 53 */
AnnaBridge 172:65be27845400 9835 /****************** Bit definition for EXTI_RTSR3 register *******************/
AnnaBridge 172:65be27845400 9836 #define EXTI_RTSR3_TR_Pos (18U)
AnnaBridge 172:65be27845400 9837 #define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) /*!< 0x00740000 */
AnnaBridge 172:65be27845400 9838 #define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */
AnnaBridge 172:65be27845400 9839 #define EXTI_RTSR3_TR82_Pos (18U)
AnnaBridge 172:65be27845400 9840 #define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9841 #define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
AnnaBridge 172:65be27845400 9842 #define EXTI_RTSR3_TR84_Pos (20U)
AnnaBridge 172:65be27845400 9843 #define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9844 #define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk /*!< Rising trigger event configuration bit of line 84 */
AnnaBridge 172:65be27845400 9845 #define EXTI_RTSR3_TR85_Pos (21U)
AnnaBridge 172:65be27845400 9846 #define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9847 #define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
AnnaBridge 172:65be27845400 9848 #define EXTI_RTSR3_TR86_Pos (22U)
AnnaBridge 172:65be27845400 9849 #define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9850 #define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
AnnaBridge 172:65be27845400 9851
AnnaBridge 172:65be27845400 9852 /****************** Bit definition for EXTI_FTSR3 register *******************/
AnnaBridge 172:65be27845400 9853 #define EXTI_FTSR3_TR_Pos (18U)
AnnaBridge 172:65be27845400 9854 #define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) /*!< 0x00740000 */
AnnaBridge 172:65be27845400 9855 #define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */
AnnaBridge 172:65be27845400 9856 #define EXTI_FTSR3_TR82_Pos (18U)
AnnaBridge 172:65be27845400 9857 #define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9858 #define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
AnnaBridge 172:65be27845400 9859 #define EXTI_FTSR3_TR84_Pos (20U)
AnnaBridge 172:65be27845400 9860 #define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9861 #define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk /*!< Falling trigger event configuration bit of line 84 */
AnnaBridge 172:65be27845400 9862 #define EXTI_FTSR3_TR85_Pos (21U)
AnnaBridge 172:65be27845400 9863 #define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9864 #define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
AnnaBridge 172:65be27845400 9865 #define EXTI_FTSR3_TR86_Pos (22U)
AnnaBridge 172:65be27845400 9866 #define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9867 #define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
AnnaBridge 172:65be27845400 9868
AnnaBridge 172:65be27845400 9869 /****************** Bit definition for EXTI_SWIER3 register ******************/
AnnaBridge 172:65be27845400 9870 #define EXTI_SWIER3_SWI_Pos (18U)
AnnaBridge 172:65be27845400 9871 #define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) /*!< 0x00740000 */
AnnaBridge 172:65be27845400 9872 #define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */
AnnaBridge 172:65be27845400 9873 #define EXTI_SWIER3_SWIER82_Pos (18U)
AnnaBridge 172:65be27845400 9874 #define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9875 #define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
AnnaBridge 172:65be27845400 9876 #define EXTI_SWIER3_SWIER84_Pos (20U)
AnnaBridge 172:65be27845400 9877 #define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9878 #define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk /*!< Software Interrupt on line 84 */
AnnaBridge 172:65be27845400 9879 #define EXTI_SWIER3_SWIER85_Pos (21U)
AnnaBridge 172:65be27845400 9880 #define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9881 #define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
AnnaBridge 172:65be27845400 9882 #define EXTI_SWIER3_SWIER86_Pos (22U)
AnnaBridge 172:65be27845400 9883 #define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9884 #define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
AnnaBridge 172:65be27845400 9885
AnnaBridge 172:65be27845400 9886 /******************* Bit definition for EXTI_IMR1 register *******************/
AnnaBridge 172:65be27845400 9887 #define EXTI_IMR1_IM_Pos (0U)
AnnaBridge 172:65be27845400 9888 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 9889 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */
AnnaBridge 172:65be27845400 9890 #define EXTI_IMR1_IM0_Pos (0U)
AnnaBridge 172:65be27845400 9891 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9892 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 172:65be27845400 9893 #define EXTI_IMR1_IM1_Pos (1U)
AnnaBridge 172:65be27845400 9894 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9895 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 172:65be27845400 9896 #define EXTI_IMR1_IM2_Pos (2U)
AnnaBridge 172:65be27845400 9897 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9898 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 172:65be27845400 9899 #define EXTI_IMR1_IM3_Pos (3U)
AnnaBridge 172:65be27845400 9900 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 9901 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 172:65be27845400 9902 #define EXTI_IMR1_IM4_Pos (4U)
AnnaBridge 172:65be27845400 9903 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 9904 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 172:65be27845400 9905 #define EXTI_IMR1_IM5_Pos (5U)
AnnaBridge 172:65be27845400 9906 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 9907 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 172:65be27845400 9908 #define EXTI_IMR1_IM6_Pos (6U)
AnnaBridge 172:65be27845400 9909 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 9910 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 172:65be27845400 9911 #define EXTI_IMR1_IM7_Pos (7U)
AnnaBridge 172:65be27845400 9912 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 9913 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 172:65be27845400 9914 #define EXTI_IMR1_IM8_Pos (8U)
AnnaBridge 172:65be27845400 9915 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 9916 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 172:65be27845400 9917 #define EXTI_IMR1_IM9_Pos (9U)
AnnaBridge 172:65be27845400 9918 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 9919 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 172:65be27845400 9920 #define EXTI_IMR1_IM10_Pos (10U)
AnnaBridge 172:65be27845400 9921 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 9922 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 172:65be27845400 9923 #define EXTI_IMR1_IM11_Pos (11U)
AnnaBridge 172:65be27845400 9924 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 9925 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 172:65be27845400 9926 #define EXTI_IMR1_IM12_Pos (12U)
AnnaBridge 172:65be27845400 9927 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 9928 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 172:65be27845400 9929 #define EXTI_IMR1_IM13_Pos (13U)
AnnaBridge 172:65be27845400 9930 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 9931 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 172:65be27845400 9932 #define EXTI_IMR1_IM14_Pos (14U)
AnnaBridge 172:65be27845400 9933 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 9934 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 172:65be27845400 9935 #define EXTI_IMR1_IM15_Pos (15U)
AnnaBridge 172:65be27845400 9936 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 9937 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 172:65be27845400 9938 #define EXTI_IMR1_IM16_Pos (16U)
AnnaBridge 172:65be27845400 9939 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 9940 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 172:65be27845400 9941 #define EXTI_IMR1_IM17_Pos (17U)
AnnaBridge 172:65be27845400 9942 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 9943 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 172:65be27845400 9944 #define EXTI_IMR1_IM18_Pos (18U)
AnnaBridge 172:65be27845400 9945 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 9946 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 172:65be27845400 9947 #define EXTI_IMR1_IM19_Pos (19U)
AnnaBridge 172:65be27845400 9948 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 9949 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 172:65be27845400 9950 #define EXTI_IMR1_IM20_Pos (20U)
AnnaBridge 172:65be27845400 9951 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 9952 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 172:65be27845400 9953 #define EXTI_IMR1_IM21_Pos (21U)
AnnaBridge 172:65be27845400 9954 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 9955 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 172:65be27845400 9956 #define EXTI_IMR1_IM22_Pos (22U)
AnnaBridge 172:65be27845400 9957 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 9958 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 172:65be27845400 9959 #define EXTI_IMR1_IM23_Pos (23U)
AnnaBridge 172:65be27845400 9960 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 9961 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 172:65be27845400 9962 #define EXTI_IMR1_IM24_Pos (24U)
AnnaBridge 172:65be27845400 9963 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 9964 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
AnnaBridge 172:65be27845400 9965 #define EXTI_IMR1_IM25_Pos (25U)
AnnaBridge 172:65be27845400 9966 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 9967 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
AnnaBridge 172:65be27845400 9968 #define EXTI_IMR1_IM26_Pos (26U)
AnnaBridge 172:65be27845400 9969 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 9970 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
AnnaBridge 172:65be27845400 9971 #define EXTI_IMR1_IM27_Pos (27U)
AnnaBridge 172:65be27845400 9972 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 9973 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
AnnaBridge 172:65be27845400 9974 #define EXTI_IMR1_IM28_Pos (28U)
AnnaBridge 172:65be27845400 9975 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 9976 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
AnnaBridge 172:65be27845400 9977 #define EXTI_IMR1_IM29_Pos (29U)
AnnaBridge 172:65be27845400 9978 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 9979 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
AnnaBridge 172:65be27845400 9980 #define EXTI_IMR1_IM30_Pos (30U)
AnnaBridge 172:65be27845400 9981 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 9982 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
AnnaBridge 172:65be27845400 9983 #define EXTI_IMR1_IM31_Pos (31U)
AnnaBridge 172:65be27845400 9984 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 9985 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
AnnaBridge 172:65be27845400 9986
AnnaBridge 172:65be27845400 9987 /******************* Bit definition for EXTI_EMR1 register *******************/
AnnaBridge 172:65be27845400 9988 #define EXTI_EMR1_EM_Pos (0U)
AnnaBridge 172:65be27845400 9989 #define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 9990 #define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */
AnnaBridge 172:65be27845400 9991 #define EXTI_EMR1_EM0_Pos (0U)
AnnaBridge 172:65be27845400 9992 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 9993 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
AnnaBridge 172:65be27845400 9994 #define EXTI_EMR1_EM1_Pos (1U)
AnnaBridge 172:65be27845400 9995 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 9996 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
AnnaBridge 172:65be27845400 9997 #define EXTI_EMR1_EM2_Pos (2U)
AnnaBridge 172:65be27845400 9998 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 9999 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
AnnaBridge 172:65be27845400 10000 #define EXTI_EMR1_EM3_Pos (3U)
AnnaBridge 172:65be27845400 10001 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10002 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
AnnaBridge 172:65be27845400 10003 #define EXTI_EMR1_EM4_Pos (4U)
AnnaBridge 172:65be27845400 10004 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10005 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
AnnaBridge 172:65be27845400 10006 #define EXTI_EMR1_EM5_Pos (5U)
AnnaBridge 172:65be27845400 10007 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10008 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
AnnaBridge 172:65be27845400 10009 #define EXTI_EMR1_EM6_Pos (6U)
AnnaBridge 172:65be27845400 10010 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10011 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
AnnaBridge 172:65be27845400 10012 #define EXTI_EMR1_EM7_Pos (7U)
AnnaBridge 172:65be27845400 10013 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10014 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
AnnaBridge 172:65be27845400 10015 #define EXTI_EMR1_EM8_Pos (8U)
AnnaBridge 172:65be27845400 10016 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10017 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
AnnaBridge 172:65be27845400 10018 #define EXTI_EMR1_EM9_Pos (9U)
AnnaBridge 172:65be27845400 10019 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10020 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
AnnaBridge 172:65be27845400 10021 #define EXTI_EMR1_EM10_Pos (10U)
AnnaBridge 172:65be27845400 10022 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10023 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
AnnaBridge 172:65be27845400 10024 #define EXTI_EMR1_EM11_Pos (11U)
AnnaBridge 172:65be27845400 10025 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10026 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
AnnaBridge 172:65be27845400 10027 #define EXTI_EMR1_EM12_Pos (12U)
AnnaBridge 172:65be27845400 10028 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10029 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
AnnaBridge 172:65be27845400 10030 #define EXTI_EMR1_EM13_Pos (13U)
AnnaBridge 172:65be27845400 10031 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10032 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
AnnaBridge 172:65be27845400 10033 #define EXTI_EMR1_EM14_Pos (14U)
AnnaBridge 172:65be27845400 10034 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10035 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
AnnaBridge 172:65be27845400 10036 #define EXTI_EMR1_EM15_Pos (15U)
AnnaBridge 172:65be27845400 10037 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10038 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
AnnaBridge 172:65be27845400 10039 #define EXTI_EMR1_EM16_Pos (16U)
AnnaBridge 172:65be27845400 10040 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10041 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
AnnaBridge 172:65be27845400 10042 #define EXTI_EMR1_EM17_Pos (17U)
AnnaBridge 172:65be27845400 10043 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10044 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
AnnaBridge 172:65be27845400 10045 #define EXTI_EMR1_EM18_Pos (18U)
AnnaBridge 172:65be27845400 10046 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10047 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
AnnaBridge 172:65be27845400 10048 #define EXTI_EMR1_EM20_Pos (20U)
AnnaBridge 172:65be27845400 10049 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10050 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
AnnaBridge 172:65be27845400 10051 #define EXTI_EMR1_EM21_Pos (21U)
AnnaBridge 172:65be27845400 10052 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10053 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
AnnaBridge 172:65be27845400 10054 #define EXTI_EMR1_EM22_Pos (22U)
AnnaBridge 172:65be27845400 10055 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10056 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
AnnaBridge 172:65be27845400 10057 #define EXTI_EMR1_EM23_Pos (23U)
AnnaBridge 172:65be27845400 10058 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10059 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
AnnaBridge 172:65be27845400 10060 #define EXTI_EMR1_EM24_Pos (24U)
AnnaBridge 172:65be27845400 10061 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10062 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
AnnaBridge 172:65be27845400 10063 #define EXTI_EMR1_EM25_Pos (25U)
AnnaBridge 172:65be27845400 10064 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10065 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
AnnaBridge 172:65be27845400 10066 #define EXTI_EMR1_EM26_Pos (26U)
AnnaBridge 172:65be27845400 10067 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10068 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
AnnaBridge 172:65be27845400 10069 #define EXTI_EMR1_EM27_Pos (27U)
AnnaBridge 172:65be27845400 10070 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10071 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
AnnaBridge 172:65be27845400 10072 #define EXTI_EMR1_EM28_Pos (28U)
AnnaBridge 172:65be27845400 10073 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10074 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
AnnaBridge 172:65be27845400 10075 #define EXTI_EMR1_EM29_Pos (29U)
AnnaBridge 172:65be27845400 10076 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 10077 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
AnnaBridge 172:65be27845400 10078 #define EXTI_EMR1_EM30_Pos (30U)
AnnaBridge 172:65be27845400 10079 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10080 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
AnnaBridge 172:65be27845400 10081 #define EXTI_EMR1_EM31_Pos (31U)
AnnaBridge 172:65be27845400 10082 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10083 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
AnnaBridge 172:65be27845400 10084
AnnaBridge 172:65be27845400 10085 /******************* Bit definition for EXTI_PR1 register ********************/
AnnaBridge 172:65be27845400 10086 #define EXTI_PR1_PR_Pos (0U)
AnnaBridge 172:65be27845400 10087 #define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */
AnnaBridge 172:65be27845400 10088 #define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */
AnnaBridge 172:65be27845400 10089 #define EXTI_PR1_PR0_Pos (0U)
AnnaBridge 172:65be27845400 10090 #define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10091 #define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 172:65be27845400 10092 #define EXTI_PR1_PR1_Pos (1U)
AnnaBridge 172:65be27845400 10093 #define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10094 #define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 172:65be27845400 10095 #define EXTI_PR1_PR2_Pos (2U)
AnnaBridge 172:65be27845400 10096 #define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10097 #define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 172:65be27845400 10098 #define EXTI_PR1_PR3_Pos (3U)
AnnaBridge 172:65be27845400 10099 #define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10100 #define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 172:65be27845400 10101 #define EXTI_PR1_PR4_Pos (4U)
AnnaBridge 172:65be27845400 10102 #define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10103 #define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 172:65be27845400 10104 #define EXTI_PR1_PR5_Pos (5U)
AnnaBridge 172:65be27845400 10105 #define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10106 #define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 172:65be27845400 10107 #define EXTI_PR1_PR6_Pos (6U)
AnnaBridge 172:65be27845400 10108 #define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10109 #define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 172:65be27845400 10110 #define EXTI_PR1_PR7_Pos (7U)
AnnaBridge 172:65be27845400 10111 #define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10112 #define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 172:65be27845400 10113 #define EXTI_PR1_PR8_Pos (8U)
AnnaBridge 172:65be27845400 10114 #define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10115 #define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 172:65be27845400 10116 #define EXTI_PR1_PR9_Pos (9U)
AnnaBridge 172:65be27845400 10117 #define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10118 #define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 172:65be27845400 10119 #define EXTI_PR1_PR10_Pos (10U)
AnnaBridge 172:65be27845400 10120 #define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10121 #define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 172:65be27845400 10122 #define EXTI_PR1_PR11_Pos (11U)
AnnaBridge 172:65be27845400 10123 #define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10124 #define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 172:65be27845400 10125 #define EXTI_PR1_PR12_Pos (12U)
AnnaBridge 172:65be27845400 10126 #define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10127 #define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 172:65be27845400 10128 #define EXTI_PR1_PR13_Pos (13U)
AnnaBridge 172:65be27845400 10129 #define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10130 #define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 172:65be27845400 10131 #define EXTI_PR1_PR14_Pos (14U)
AnnaBridge 172:65be27845400 10132 #define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10133 #define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 172:65be27845400 10134 #define EXTI_PR1_PR15_Pos (15U)
AnnaBridge 172:65be27845400 10135 #define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10136 #define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 172:65be27845400 10137 #define EXTI_PR1_PR16_Pos (16U)
AnnaBridge 172:65be27845400 10138 #define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10139 #define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 172:65be27845400 10140 #define EXTI_PR1_PR17_Pos (17U)
AnnaBridge 172:65be27845400 10141 #define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10142 #define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 172:65be27845400 10143 #define EXTI_PR1_PR18_Pos (18U)
AnnaBridge 172:65be27845400 10144 #define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10145 #define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 172:65be27845400 10146 #define EXTI_PR1_PR19_Pos (19U)
AnnaBridge 172:65be27845400 10147 #define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10148 #define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 172:65be27845400 10149 #define EXTI_PR1_PR20_Pos (20U)
AnnaBridge 172:65be27845400 10150 #define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10151 #define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 172:65be27845400 10152 #define EXTI_PR1_PR21_Pos (21U)
AnnaBridge 172:65be27845400 10153 #define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10154 #define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 172:65be27845400 10155
AnnaBridge 172:65be27845400 10156 /******************* Bit definition for EXTI_IMR2 register *******************/
AnnaBridge 172:65be27845400 10157 #define EXTI_IMR2_IM_Pos (0U)
AnnaBridge 172:65be27845400 10158 #define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFFDFFF */
AnnaBridge 172:65be27845400 10159 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */
AnnaBridge 172:65be27845400 10160 #define EXTI_IMR2_IM32_Pos (0U)
AnnaBridge 172:65be27845400 10161 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10162 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
AnnaBridge 172:65be27845400 10163 #define EXTI_IMR2_IM33_Pos (1U)
AnnaBridge 172:65be27845400 10164 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10165 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
AnnaBridge 172:65be27845400 10166 #define EXTI_IMR2_IM34_Pos (2U)
AnnaBridge 172:65be27845400 10167 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10168 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
AnnaBridge 172:65be27845400 10169 #define EXTI_IMR2_IM35_Pos (3U)
AnnaBridge 172:65be27845400 10170 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10171 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
AnnaBridge 172:65be27845400 10172 #define EXTI_IMR2_IM36_Pos (4U)
AnnaBridge 172:65be27845400 10173 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10174 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
AnnaBridge 172:65be27845400 10175 #define EXTI_IMR2_IM37_Pos (5U)
AnnaBridge 172:65be27845400 10176 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10177 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
AnnaBridge 172:65be27845400 10178 #define EXTI_IMR2_IM38_Pos (6U)
AnnaBridge 172:65be27845400 10179 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10180 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
AnnaBridge 172:65be27845400 10181 #define EXTI_IMR2_IM39_Pos (7U)
AnnaBridge 172:65be27845400 10182 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10183 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
AnnaBridge 172:65be27845400 10184 #define EXTI_IMR2_IM40_Pos (8U)
AnnaBridge 172:65be27845400 10185 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10186 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
AnnaBridge 172:65be27845400 10187 #define EXTI_IMR2_IM41_Pos (9U)
AnnaBridge 172:65be27845400 10188 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10189 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
AnnaBridge 172:65be27845400 10190 #define EXTI_IMR2_IM42_Pos (10U)
AnnaBridge 172:65be27845400 10191 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10192 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
AnnaBridge 172:65be27845400 10193 #define EXTI_IMR2_IM43_Pos (11U)
AnnaBridge 172:65be27845400 10194 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10195 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
AnnaBridge 172:65be27845400 10196 #define EXTI_IMR2_IM44_Pos (12U)
AnnaBridge 172:65be27845400 10197 #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10198 #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
AnnaBridge 172:65be27845400 10199 #define EXTI_IMR2_IM46_Pos (14U)
AnnaBridge 172:65be27845400 10200 #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10201 #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
AnnaBridge 172:65be27845400 10202 #define EXTI_IMR2_IM47_Pos (15U)
AnnaBridge 172:65be27845400 10203 #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10204 #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
AnnaBridge 172:65be27845400 10205 #define EXTI_IMR2_IM48_Pos (16U)
AnnaBridge 172:65be27845400 10206 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10207 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
AnnaBridge 172:65be27845400 10208 #define EXTI_IMR2_IM49_Pos (17U)
AnnaBridge 172:65be27845400 10209 #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10210 #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
AnnaBridge 172:65be27845400 10211 #define EXTI_IMR2_IM50_Pos (18U)
AnnaBridge 172:65be27845400 10212 #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10213 #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
AnnaBridge 172:65be27845400 10214 #define EXTI_IMR2_IM51_Pos (19U)
AnnaBridge 172:65be27845400 10215 #define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10216 #define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
AnnaBridge 172:65be27845400 10217 #define EXTI_IMR2_IM52_Pos (20U)
AnnaBridge 172:65be27845400 10218 #define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10219 #define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
AnnaBridge 172:65be27845400 10220 #define EXTI_IMR2_IM53_Pos (21U)
AnnaBridge 172:65be27845400 10221 #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10222 #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
AnnaBridge 172:65be27845400 10223 #define EXTI_IMR2_IM54_Pos (22U)
AnnaBridge 172:65be27845400 10224 #define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10225 #define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
AnnaBridge 172:65be27845400 10226 #define EXTI_IMR2_IM55_Pos (23U)
AnnaBridge 172:65be27845400 10227 #define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10228 #define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
AnnaBridge 172:65be27845400 10229 #define EXTI_IMR2_IM56_Pos (24U)
AnnaBridge 172:65be27845400 10230 #define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10231 #define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
AnnaBridge 172:65be27845400 10232 #define EXTI_IMR2_IM57_Pos (25U)
AnnaBridge 172:65be27845400 10233 #define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10234 #define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
AnnaBridge 172:65be27845400 10235 #define EXTI_IMR2_IM58_Pos (26U)
AnnaBridge 172:65be27845400 10236 #define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10237 #define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
AnnaBridge 172:65be27845400 10238 #define EXTI_IMR2_IM59_Pos (27U)
AnnaBridge 172:65be27845400 10239 #define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10240 #define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
AnnaBridge 172:65be27845400 10241 #define EXTI_IMR2_IM60_Pos (28U)
AnnaBridge 172:65be27845400 10242 #define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10243 #define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
AnnaBridge 172:65be27845400 10244 #define EXTI_IMR2_IM61_Pos (29U)
AnnaBridge 172:65be27845400 10245 #define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 10246 #define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
AnnaBridge 172:65be27845400 10247 #define EXTI_IMR2_IM62_Pos (30U)
AnnaBridge 172:65be27845400 10248 #define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10249 #define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
AnnaBridge 172:65be27845400 10250 #define EXTI_IMR2_IM63_Pos (31U)
AnnaBridge 172:65be27845400 10251 #define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10252 #define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
AnnaBridge 172:65be27845400 10253
AnnaBridge 172:65be27845400 10254 /******************* Bit definition for EXTI_EMR2 register *******************/
AnnaBridge 172:65be27845400 10255 #define EXTI_EMR2_EM_Pos (0U)
AnnaBridge 172:65be27845400 10256 #define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFFDFFF */
AnnaBridge 172:65be27845400 10257 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */
AnnaBridge 172:65be27845400 10258 #define EXTI_EMR2_EM32_Pos (0U)
AnnaBridge 172:65be27845400 10259 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10260 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
AnnaBridge 172:65be27845400 10261 #define EXTI_EMR2_EM33_Pos (1U)
AnnaBridge 172:65be27845400 10262 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10263 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
AnnaBridge 172:65be27845400 10264 #define EXTI_EMR2_EM34_Pos (2U)
AnnaBridge 172:65be27845400 10265 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10266 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
AnnaBridge 172:65be27845400 10267 #define EXTI_EMR2_EM35_Pos (3U)
AnnaBridge 172:65be27845400 10268 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10269 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
AnnaBridge 172:65be27845400 10270 #define EXTI_EMR2_EM36_Pos (4U)
AnnaBridge 172:65be27845400 10271 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10272 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
AnnaBridge 172:65be27845400 10273 #define EXTI_EMR2_EM37_Pos (5U)
AnnaBridge 172:65be27845400 10274 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10275 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
AnnaBridge 172:65be27845400 10276 #define EXTI_EMR2_EM38_Pos (6U)
AnnaBridge 172:65be27845400 10277 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10278 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
AnnaBridge 172:65be27845400 10279 #define EXTI_EMR2_EM39_Pos (7U)
AnnaBridge 172:65be27845400 10280 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10281 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
AnnaBridge 172:65be27845400 10282 #define EXTI_EMR2_EM40_Pos (8U)
AnnaBridge 172:65be27845400 10283 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10284 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
AnnaBridge 172:65be27845400 10285 #define EXTI_EMR2_EM41_Pos (9U)
AnnaBridge 172:65be27845400 10286 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10287 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
AnnaBridge 172:65be27845400 10288 #define EXTI_EMR2_EM42_Pos (10U)
AnnaBridge 172:65be27845400 10289 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10290 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
AnnaBridge 172:65be27845400 10291 #define EXTI_EMR2_EM43_Pos (11U)
AnnaBridge 172:65be27845400 10292 #define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10293 #define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
AnnaBridge 172:65be27845400 10294 #define EXTI_EMR2_EM44_Pos (12U)
AnnaBridge 172:65be27845400 10295 #define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10296 #define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
AnnaBridge 172:65be27845400 10297 #define EXTI_EMR2_EM46_Pos (14U)
AnnaBridge 172:65be27845400 10298 #define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10299 #define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
AnnaBridge 172:65be27845400 10300 #define EXTI_EMR2_EM47_Pos (15U)
AnnaBridge 172:65be27845400 10301 #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10302 #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
AnnaBridge 172:65be27845400 10303 #define EXTI_EMR2_EM48_Pos (16U)
AnnaBridge 172:65be27845400 10304 #define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10305 #define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
AnnaBridge 172:65be27845400 10306 #define EXTI_EMR2_EM49_Pos (17U)
AnnaBridge 172:65be27845400 10307 #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10308 #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
AnnaBridge 172:65be27845400 10309 #define EXTI_EMR2_EM50_Pos (18U)
AnnaBridge 172:65be27845400 10310 #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10311 #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
AnnaBridge 172:65be27845400 10312 #define EXTI_EMR2_EM51_Pos (19U)
AnnaBridge 172:65be27845400 10313 #define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10314 #define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
AnnaBridge 172:65be27845400 10315 #define EXTI_EMR2_EM52_Pos (20U)
AnnaBridge 172:65be27845400 10316 #define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10317 #define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
AnnaBridge 172:65be27845400 10318 #define EXTI_EMR2_EM53_Pos (21U)
AnnaBridge 172:65be27845400 10319 #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10320 #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
AnnaBridge 172:65be27845400 10321 #define EXTI_EMR2_EM54_Pos (22U)
AnnaBridge 172:65be27845400 10322 #define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10323 #define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
AnnaBridge 172:65be27845400 10324 #define EXTI_EMR2_EM55_Pos (23U)
AnnaBridge 172:65be27845400 10325 #define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10326 #define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
AnnaBridge 172:65be27845400 10327 #define EXTI_EMR2_EM56_Pos (24U)
AnnaBridge 172:65be27845400 10328 #define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10329 #define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
AnnaBridge 172:65be27845400 10330 #define EXTI_EMR2_EM57_Pos (25U)
AnnaBridge 172:65be27845400 10331 #define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10332 #define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
AnnaBridge 172:65be27845400 10333 #define EXTI_EMR2_EM58_Pos (26U)
AnnaBridge 172:65be27845400 10334 #define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10335 #define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
AnnaBridge 172:65be27845400 10336 #define EXTI_EMR2_EM59_Pos (27U)
AnnaBridge 172:65be27845400 10337 #define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10338 #define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
AnnaBridge 172:65be27845400 10339 #define EXTI_EMR2_EM60_Pos (28U)
AnnaBridge 172:65be27845400 10340 #define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10341 #define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
AnnaBridge 172:65be27845400 10342 #define EXTI_EMR2_EM61_Pos (29U)
AnnaBridge 172:65be27845400 10343 #define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 10344 #define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
AnnaBridge 172:65be27845400 10345 #define EXTI_EMR2_EM62_Pos (30U)
AnnaBridge 172:65be27845400 10346 #define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10347 #define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
AnnaBridge 172:65be27845400 10348 #define EXTI_EMR2_EM63_Pos (31U)
AnnaBridge 172:65be27845400 10349 #define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10350 #define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
AnnaBridge 172:65be27845400 10351
AnnaBridge 172:65be27845400 10352 /******************* Bit definition for EXTI_PR2 register ********************/
AnnaBridge 172:65be27845400 10353 #define EXTI_PR2_PR_Pos (17U)
AnnaBridge 172:65be27845400 10354 #define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */
AnnaBridge 172:65be27845400 10355 #define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */
AnnaBridge 172:65be27845400 10356 #define EXTI_PR2_PR49_Pos (17U)
AnnaBridge 172:65be27845400 10357 #define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10358 #define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
AnnaBridge 172:65be27845400 10359 #define EXTI_PR2_PR51_Pos (19U)
AnnaBridge 172:65be27845400 10360 #define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10361 #define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
AnnaBridge 172:65be27845400 10362
AnnaBridge 172:65be27845400 10363 /******************* Bit definition for EXTI_IMR3 register *******************/
AnnaBridge 172:65be27845400 10364 #define EXTI_IMR3_IM_Pos (0U)
AnnaBridge 172:65be27845400 10365 #define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) /*!< 0x00F5FFFF */
AnnaBridge 172:65be27845400 10366 #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
AnnaBridge 172:65be27845400 10367 #define EXTI_IMR3_IM64_Pos (0U)
AnnaBridge 172:65be27845400 10368 #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10369 #define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
AnnaBridge 172:65be27845400 10370 #define EXTI_IMR3_IM65_Pos (1U)
AnnaBridge 172:65be27845400 10371 #define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10372 #define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
AnnaBridge 172:65be27845400 10373 #define EXTI_IMR3_IM66_Pos (2U)
AnnaBridge 172:65be27845400 10374 #define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10375 #define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
AnnaBridge 172:65be27845400 10376 #define EXTI_IMR3_IM67_Pos (3U)
AnnaBridge 172:65be27845400 10377 #define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10378 #define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
AnnaBridge 172:65be27845400 10379 #define EXTI_IMR3_IM68_Pos (4U)
AnnaBridge 172:65be27845400 10380 #define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10381 #define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
AnnaBridge 172:65be27845400 10382 #define EXTI_IMR3_IM69_Pos (5U)
AnnaBridge 172:65be27845400 10383 #define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10384 #define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
AnnaBridge 172:65be27845400 10385 #define EXTI_IMR3_IM70_Pos (6U)
AnnaBridge 172:65be27845400 10386 #define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10387 #define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
AnnaBridge 172:65be27845400 10388 #define EXTI_IMR3_IM71_Pos (7U)
AnnaBridge 172:65be27845400 10389 #define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10390 #define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
AnnaBridge 172:65be27845400 10391 #define EXTI_IMR3_IM72_Pos (8U)
AnnaBridge 172:65be27845400 10392 #define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10393 #define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
AnnaBridge 172:65be27845400 10394 #define EXTI_IMR3_IM73_Pos (9U)
AnnaBridge 172:65be27845400 10395 #define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10396 #define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
AnnaBridge 172:65be27845400 10397 #define EXTI_IMR3_IM74_Pos (10U)
AnnaBridge 172:65be27845400 10398 #define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10399 #define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
AnnaBridge 172:65be27845400 10400 #define EXTI_IMR3_IM75_Pos (11U)
AnnaBridge 172:65be27845400 10401 #define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10402 #define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
AnnaBridge 172:65be27845400 10403 #define EXTI_IMR3_IM76_Pos (12U)
AnnaBridge 172:65be27845400 10404 #define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10405 #define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
AnnaBridge 172:65be27845400 10406 #define EXTI_IMR3_IM77_Pos (13U)
AnnaBridge 172:65be27845400 10407 #define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10408 #define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
AnnaBridge 172:65be27845400 10409 #define EXTI_IMR3_IM78_Pos (14U)
AnnaBridge 172:65be27845400 10410 #define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10411 #define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
AnnaBridge 172:65be27845400 10412 #define EXTI_IMR3_IM79_Pos (15U)
AnnaBridge 172:65be27845400 10413 #define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10414 #define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
AnnaBridge 172:65be27845400 10415 #define EXTI_IMR3_IM80_Pos (16U)
AnnaBridge 172:65be27845400 10416 #define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10417 #define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
AnnaBridge 172:65be27845400 10418 #define EXTI_IMR3_IM82_Pos (18U)
AnnaBridge 172:65be27845400 10419 #define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10420 #define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
AnnaBridge 172:65be27845400 10421 #define EXTI_IMR3_IM84_Pos (20U)
AnnaBridge 172:65be27845400 10422 #define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10423 #define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
AnnaBridge 172:65be27845400 10424 #define EXTI_IMR3_IM85_Pos (21U)
AnnaBridge 172:65be27845400 10425 #define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10426 #define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
AnnaBridge 172:65be27845400 10427 #define EXTI_IMR3_IM86_Pos (22U)
AnnaBridge 172:65be27845400 10428 #define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10429 #define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
AnnaBridge 172:65be27845400 10430 #define EXTI_IMR3_IM87_Pos (23U)
AnnaBridge 172:65be27845400 10431 #define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10432 #define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
AnnaBridge 172:65be27845400 10433
AnnaBridge 172:65be27845400 10434
AnnaBridge 172:65be27845400 10435 /******************* Bit definition for EXTI_EMR3 register *******************/
AnnaBridge 172:65be27845400 10436 #define EXTI_EMR3_EM_Pos (0U)
AnnaBridge 172:65be27845400 10437 #define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) /*!< 0x00F5FFFF */
AnnaBridge 172:65be27845400 10438 #define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */
AnnaBridge 172:65be27845400 10439 #define EXTI_EMR3_EM64_Pos (0U)
AnnaBridge 172:65be27845400 10440 #define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10441 #define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
AnnaBridge 172:65be27845400 10442 #define EXTI_EMR3_EM65_Pos (1U)
AnnaBridge 172:65be27845400 10443 #define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10444 #define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
AnnaBridge 172:65be27845400 10445 #define EXTI_EMR3_EM66_Pos (2U)
AnnaBridge 172:65be27845400 10446 #define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10447 #define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
AnnaBridge 172:65be27845400 10448 #define EXTI_EMR3_EM67_Pos (3U)
AnnaBridge 172:65be27845400 10449 #define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10450 #define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
AnnaBridge 172:65be27845400 10451 #define EXTI_EMR3_EM68_Pos (4U)
AnnaBridge 172:65be27845400 10452 #define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10453 #define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
AnnaBridge 172:65be27845400 10454 #define EXTI_EMR3_EM69_Pos (5U)
AnnaBridge 172:65be27845400 10455 #define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10456 #define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
AnnaBridge 172:65be27845400 10457 #define EXTI_EMR3_EM70_Pos (6U)
AnnaBridge 172:65be27845400 10458 #define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10459 #define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
AnnaBridge 172:65be27845400 10460 #define EXTI_EMR3_EM71_Pos (7U)
AnnaBridge 172:65be27845400 10461 #define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10462 #define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
AnnaBridge 172:65be27845400 10463 #define EXTI_EMR3_EM72_Pos (8U)
AnnaBridge 172:65be27845400 10464 #define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10465 #define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
AnnaBridge 172:65be27845400 10466 #define EXTI_EMR3_EM73_Pos (9U)
AnnaBridge 172:65be27845400 10467 #define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10468 #define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
AnnaBridge 172:65be27845400 10469 #define EXTI_EMR3_EM74_Pos (10U)
AnnaBridge 172:65be27845400 10470 #define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10471 #define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
AnnaBridge 172:65be27845400 10472 #define EXTI_EMR3_EM75_Pos (11U)
AnnaBridge 172:65be27845400 10473 #define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10474 #define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
AnnaBridge 172:65be27845400 10475 #define EXTI_EMR3_EM76_Pos (12U)
AnnaBridge 172:65be27845400 10476 #define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10477 #define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
AnnaBridge 172:65be27845400 10478 #define EXTI_EMR3_EM77_Pos (13U)
AnnaBridge 172:65be27845400 10479 #define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10480 #define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
AnnaBridge 172:65be27845400 10481 #define EXTI_EMR3_EM78_Pos (14U)
AnnaBridge 172:65be27845400 10482 #define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10483 #define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
AnnaBridge 172:65be27845400 10484 #define EXTI_EMR3_EM79_Pos (15U)
AnnaBridge 172:65be27845400 10485 #define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10486 #define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
AnnaBridge 172:65be27845400 10487 #define EXTI_EMR3_EM80_Pos (16U)
AnnaBridge 172:65be27845400 10488 #define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10489 #define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
AnnaBridge 172:65be27845400 10490 #define EXTI_EMR3_EM81_Pos (17U)
AnnaBridge 172:65be27845400 10491 #define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10492 #define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
AnnaBridge 172:65be27845400 10493 #define EXTI_EMR3_EM82_Pos (18U)
AnnaBridge 172:65be27845400 10494 #define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10495 #define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
AnnaBridge 172:65be27845400 10496 #define EXTI_EMR3_EM84_Pos (20U)
AnnaBridge 172:65be27845400 10497 #define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10498 #define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
AnnaBridge 172:65be27845400 10499 #define EXTI_EMR3_EM85_Pos (21U)
AnnaBridge 172:65be27845400 10500 #define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10501 #define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
AnnaBridge 172:65be27845400 10502 #define EXTI_EMR3_EM86_Pos (22U)
AnnaBridge 172:65be27845400 10503 #define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10504 #define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
AnnaBridge 172:65be27845400 10505 #define EXTI_EMR3_EM87_Pos (23U)
AnnaBridge 172:65be27845400 10506 #define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10507 #define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
AnnaBridge 172:65be27845400 10508
AnnaBridge 172:65be27845400 10509 /******************* Bit definition for EXTI_PR3 register ********************/
AnnaBridge 172:65be27845400 10510 #define EXTI_PR3_PR_Pos (18U)
AnnaBridge 172:65be27845400 10511 #define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) /*!< 0x00740000 */
AnnaBridge 172:65be27845400 10512 #define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */
AnnaBridge 172:65be27845400 10513 #define EXTI_PR3_PR82_Pos (18U)
AnnaBridge 172:65be27845400 10514 #define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10515 #define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
AnnaBridge 172:65be27845400 10516 #define EXTI_PR3_PR84_Pos (20U)
AnnaBridge 172:65be27845400 10517 #define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10518 #define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk /*!< Pending bit for line 84 */
AnnaBridge 172:65be27845400 10519 #define EXTI_PR3_PR85_Pos (21U)
AnnaBridge 172:65be27845400 10520 #define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10521 #define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
AnnaBridge 172:65be27845400 10522 #define EXTI_PR3_PR86_Pos (22U)
AnnaBridge 172:65be27845400 10523 #define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10524 #define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk /*!< Pending bit for line 86 */
AnnaBridge 172:65be27845400 10525 /******************************************************************************/
AnnaBridge 172:65be27845400 10526 /* */
AnnaBridge 172:65be27845400 10527 /* FLASH */
AnnaBridge 172:65be27845400 10528 /* */
AnnaBridge 172:65be27845400 10529 /******************************************************************************/
AnnaBridge 172:65be27845400 10530 /*
AnnaBridge 172:65be27845400 10531 * @brief FLASH Total Sectors Number
AnnaBridge 172:65be27845400 10532 */
AnnaBridge 172:65be27845400 10533 #define FLASH_SECTOR_TOTAL 8U
AnnaBridge 172:65be27845400 10534 #define FLASH_NB_32BITWORD_IN_FLASHWORD 8U
AnnaBridge 172:65be27845400 10535
AnnaBridge 172:65be27845400 10536 /******************* Bits definition for FLASH_ACR register **********************/
AnnaBridge 172:65be27845400 10537 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 172:65be27845400 10538 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 10539 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 172:65be27845400 10540 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
AnnaBridge 172:65be27845400 10541 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
AnnaBridge 172:65be27845400 10542 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
AnnaBridge 172:65be27845400 10543 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
AnnaBridge 172:65be27845400 10544 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
AnnaBridge 172:65be27845400 10545 #define FLASH_ACR_LATENCY_5WS (0x00000005UL)
AnnaBridge 172:65be27845400 10546 #define FLASH_ACR_LATENCY_6WS (0x00000006UL)
AnnaBridge 172:65be27845400 10547 #define FLASH_ACR_LATENCY_7WS (0x00000007UL)
AnnaBridge 172:65be27845400 10548 #define FLASH_ACR_LATENCY_8WS (0x00000008UL)
AnnaBridge 172:65be27845400 10549 #define FLASH_ACR_LATENCY_9WS (0x00000009UL)
AnnaBridge 172:65be27845400 10550 #define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
AnnaBridge 172:65be27845400 10551 #define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
AnnaBridge 172:65be27845400 10552 #define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
AnnaBridge 172:65be27845400 10553 #define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
AnnaBridge 172:65be27845400 10554 #define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
AnnaBridge 172:65be27845400 10555 #define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
AnnaBridge 172:65be27845400 10556 #define FLASH_ACR_WRHIGHFREQ_Pos (4U)
AnnaBridge 172:65be27845400 10557 #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 10558 #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
AnnaBridge 172:65be27845400 10559 #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10560 #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10561
AnnaBridge 172:65be27845400 10562 /******************* Bits definition for FLASH_CR register ***********************/
AnnaBridge 172:65be27845400 10563 #define FLASH_CR_LOCK_Pos (0U)
AnnaBridge 172:65be27845400 10564 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10565 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
AnnaBridge 172:65be27845400 10566 #define FLASH_CR_PG_Pos (1U)
AnnaBridge 172:65be27845400 10567 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10568 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 172:65be27845400 10569 #define FLASH_CR_SER_Pos (2U)
AnnaBridge 172:65be27845400 10570 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10571 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 172:65be27845400 10572 #define FLASH_CR_BER_Pos (3U)
AnnaBridge 172:65be27845400 10573 #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10574 #define FLASH_CR_BER FLASH_CR_BER_Msk
AnnaBridge 172:65be27845400 10575 #define FLASH_CR_PSIZE_Pos (4U)
AnnaBridge 172:65be27845400 10576 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 10577 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 172:65be27845400 10578 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10579 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10580 #define FLASH_CR_FW_Pos (6U)
AnnaBridge 172:65be27845400 10581 #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10582 #define FLASH_CR_FW FLASH_CR_FW_Msk
AnnaBridge 172:65be27845400 10583 #define FLASH_CR_START_Pos (7U)
AnnaBridge 172:65be27845400 10584 #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10585 #define FLASH_CR_START FLASH_CR_START_Msk
AnnaBridge 172:65be27845400 10586 #define FLASH_CR_SNB_Pos (8U)
AnnaBridge 172:65be27845400 10587 #define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 10588 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 172:65be27845400 10589 #define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10590 #define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10591 #define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10592 #define FLASH_CR_CRC_EN_Pos (15U)
AnnaBridge 172:65be27845400 10593 #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10594 #define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
AnnaBridge 172:65be27845400 10595 #define FLASH_CR_EOPIE_Pos (16U)
AnnaBridge 172:65be27845400 10596 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10597 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 172:65be27845400 10598 #define FLASH_CR_WRPERRIE_Pos (17U)
AnnaBridge 172:65be27845400 10599 #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10600 #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
AnnaBridge 172:65be27845400 10601 #define FLASH_CR_PGSERRIE_Pos (18U)
AnnaBridge 172:65be27845400 10602 #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10603 #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
AnnaBridge 172:65be27845400 10604 #define FLASH_CR_STRBERRIE_Pos (19U)
AnnaBridge 172:65be27845400 10605 #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10606 #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
AnnaBridge 172:65be27845400 10607 #define FLASH_CR_INCERRIE_Pos (21U)
AnnaBridge 172:65be27845400 10608 #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10609 #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
AnnaBridge 172:65be27845400 10610 #define FLASH_CR_OPERRIE_Pos (22U)
AnnaBridge 172:65be27845400 10611 #define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10612 #define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
AnnaBridge 172:65be27845400 10613 #define FLASH_CR_RDPERRIE_Pos (23U)
AnnaBridge 172:65be27845400 10614 #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10615 #define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
AnnaBridge 172:65be27845400 10616 #define FLASH_CR_RDSERRIE_Pos (24U)
AnnaBridge 172:65be27845400 10617 #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10618 #define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
AnnaBridge 172:65be27845400 10619 #define FLASH_CR_SNECCERRIE_Pos (25U)
AnnaBridge 172:65be27845400 10620 #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10621 #define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
AnnaBridge 172:65be27845400 10622 #define FLASH_CR_DBECCERRIE_Pos (26U)
AnnaBridge 172:65be27845400 10623 #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10624 #define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
AnnaBridge 172:65be27845400 10625 #define FLASH_CR_CRCENDIE_Pos (27U)
AnnaBridge 172:65be27845400 10626 #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10627 #define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
AnnaBridge 172:65be27845400 10628 #define FLASH_CR_CRCRDERRIE_Pos (28U)
AnnaBridge 172:65be27845400 10629 #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10630 #define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
AnnaBridge 172:65be27845400 10631
AnnaBridge 172:65be27845400 10632 /******************* Bits definition for FLASH_SR register ***********************/
AnnaBridge 172:65be27845400 10633 #define FLASH_SR_BSY_Pos (0U)
AnnaBridge 172:65be27845400 10634 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10635 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
AnnaBridge 172:65be27845400 10636 #define FLASH_SR_WBNE_Pos (1U)
AnnaBridge 172:65be27845400 10637 #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10638 #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
AnnaBridge 172:65be27845400 10639 #define FLASH_SR_QW_Pos (2U)
AnnaBridge 172:65be27845400 10640 #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10641 #define FLASH_SR_QW FLASH_SR_QW_Msk
AnnaBridge 172:65be27845400 10642 #define FLASH_SR_CRC_BUSY_Pos (3U)
AnnaBridge 172:65be27845400 10643 #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10644 #define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
AnnaBridge 172:65be27845400 10645 #define FLASH_SR_EOP_Pos (16U)
AnnaBridge 172:65be27845400 10646 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10647 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 172:65be27845400 10648 #define FLASH_SR_WRPERR_Pos (17U)
AnnaBridge 172:65be27845400 10649 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10650 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 172:65be27845400 10651 #define FLASH_SR_PGSERR_Pos (18U)
AnnaBridge 172:65be27845400 10652 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10653 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 172:65be27845400 10654 #define FLASH_SR_STRBERR_Pos (19U)
AnnaBridge 172:65be27845400 10655 #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10656 #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
AnnaBridge 172:65be27845400 10657 #define FLASH_SR_INCERR_Pos (21U)
AnnaBridge 172:65be27845400 10658 #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10659 #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
AnnaBridge 172:65be27845400 10660 #define FLASH_SR_OPERR_Pos (22U)
AnnaBridge 172:65be27845400 10661 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10662 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
AnnaBridge 172:65be27845400 10663 #define FLASH_SR_RDPERR_Pos (23U)
AnnaBridge 172:65be27845400 10664 #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10665 #define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
AnnaBridge 172:65be27845400 10666 #define FLASH_SR_RDSERR_Pos (24U)
AnnaBridge 172:65be27845400 10667 #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10668 #define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
AnnaBridge 172:65be27845400 10669 #define FLASH_SR_SNECCERR_Pos (25U)
AnnaBridge 172:65be27845400 10670 #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10671 #define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
AnnaBridge 172:65be27845400 10672 #define FLASH_SR_DBECCERR_Pos (26U)
AnnaBridge 172:65be27845400 10673 #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10674 #define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
AnnaBridge 172:65be27845400 10675 #define FLASH_SR_CRCEND_Pos (27U)
AnnaBridge 172:65be27845400 10676 #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10677 #define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
AnnaBridge 172:65be27845400 10678 #define FLASH_SR_CRCRDERR_Pos (28U)
AnnaBridge 172:65be27845400 10679 #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10680 #define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
AnnaBridge 172:65be27845400 10681
AnnaBridge 172:65be27845400 10682 /******************* Bits definition for FLASH_CCR register *******************/
AnnaBridge 172:65be27845400 10683 #define FLASH_CCR_CLR_EOP_Pos (16U)
AnnaBridge 172:65be27845400 10684 #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10685 #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
AnnaBridge 172:65be27845400 10686 #define FLASH_CCR_CLR_WRPERR_Pos (17U)
AnnaBridge 172:65be27845400 10687 #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10688 #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
AnnaBridge 172:65be27845400 10689 #define FLASH_CCR_CLR_PGSERR_Pos (18U)
AnnaBridge 172:65be27845400 10690 #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10691 #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
AnnaBridge 172:65be27845400 10692 #define FLASH_CCR_CLR_STRBERR_Pos (19U)
AnnaBridge 172:65be27845400 10693 #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10694 #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
AnnaBridge 172:65be27845400 10695 #define FLASH_CCR_CLR_INCERR_Pos (21U)
AnnaBridge 172:65be27845400 10696 #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10697 #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
AnnaBridge 172:65be27845400 10698 #define FLASH_CCR_CLR_OPERR_Pos (22U)
AnnaBridge 172:65be27845400 10699 #define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10700 #define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
AnnaBridge 172:65be27845400 10701 #define FLASH_CCR_CLR_RDPERR_Pos (23U)
AnnaBridge 172:65be27845400 10702 #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10703 #define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
AnnaBridge 172:65be27845400 10704 #define FLASH_CCR_CLR_RDSERR_Pos (24U)
AnnaBridge 172:65be27845400 10705 #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10706 #define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
AnnaBridge 172:65be27845400 10707 #define FLASH_CCR_CLR_SNECCERR_Pos (25U)
AnnaBridge 172:65be27845400 10708 #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10709 #define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
AnnaBridge 172:65be27845400 10710 #define FLASH_CCR_CLR_DBECCERR_Pos (26U)
AnnaBridge 172:65be27845400 10711 #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 10712 #define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
AnnaBridge 172:65be27845400 10713 #define FLASH_CCR_CLR_CRCEND_Pos (27U)
AnnaBridge 172:65be27845400 10714 #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 10715 #define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
AnnaBridge 172:65be27845400 10716 #define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
AnnaBridge 172:65be27845400 10717 #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 10718 #define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
AnnaBridge 172:65be27845400 10719
AnnaBridge 172:65be27845400 10720 /******************* Bits definition for FLASH_OPTCR register *******************/
AnnaBridge 172:65be27845400 10721 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 172:65be27845400 10722 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10723 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 172:65be27845400 10724 #define FLASH_OPTCR_OPTSTART_Pos (1U)
AnnaBridge 172:65be27845400 10725 #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10726 #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
AnnaBridge 172:65be27845400 10727 #define FLASH_OPTCR_MER_Pos (4U)
AnnaBridge 172:65be27845400 10728 #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10729 #define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
AnnaBridge 172:65be27845400 10730 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
AnnaBridge 172:65be27845400 10731 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10732 #define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
AnnaBridge 172:65be27845400 10733 #define FLASH_OPTCR_SWAP_BANK_Pos (31U)
AnnaBridge 172:65be27845400 10734 #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10735 #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
AnnaBridge 172:65be27845400 10736
AnnaBridge 172:65be27845400 10737 /******************* Bits definition for FLASH_OPTSR register ***************/
AnnaBridge 172:65be27845400 10738 #define FLASH_OPTSR_OPT_BUSY_Pos (0U)
AnnaBridge 172:65be27845400 10739 #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10740 #define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
AnnaBridge 172:65be27845400 10741 #define FLASH_OPTSR_BOR_LEV_Pos (2U)
AnnaBridge 172:65be27845400 10742 #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 10743 #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
AnnaBridge 172:65be27845400 10744 #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10745 #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10746 #define FLASH_OPTSR_IWDG1_SW_Pos (4U)
AnnaBridge 172:65be27845400 10747 #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10748 #define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
AnnaBridge 172:65be27845400 10749 #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
AnnaBridge 172:65be27845400 10750 #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10751 #define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
AnnaBridge 172:65be27845400 10752 #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
AnnaBridge 172:65be27845400 10753 #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10754 #define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
AnnaBridge 172:65be27845400 10755 #define FLASH_OPTSR_RDP_Pos (8U)
AnnaBridge 172:65be27845400 10756 #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10757 #define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
AnnaBridge 172:65be27845400 10758 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
AnnaBridge 172:65be27845400 10759 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10760 #define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
AnnaBridge 172:65be27845400 10761 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
AnnaBridge 172:65be27845400 10762 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10763 #define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
AnnaBridge 172:65be27845400 10764 #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
AnnaBridge 172:65be27845400 10765 #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
AnnaBridge 172:65be27845400 10766 #define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
AnnaBridge 172:65be27845400 10767 #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10768 #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10769 #define FLASH_OPTSR_SECURITY_Pos (21U)
AnnaBridge 172:65be27845400 10770 #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10771 #define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
AnnaBridge 172:65be27845400 10772 #define FLASH_OPTSR_IO_HSLV_Pos (29U)
AnnaBridge 172:65be27845400 10773 #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 10774 #define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
AnnaBridge 172:65be27845400 10775 #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
AnnaBridge 172:65be27845400 10776 #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10777 #define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
AnnaBridge 172:65be27845400 10778 #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
AnnaBridge 172:65be27845400 10779 #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10780 #define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
AnnaBridge 172:65be27845400 10781
AnnaBridge 172:65be27845400 10782 /******************* Bits definition for FLASH_OPTCCR register *******************/
AnnaBridge 172:65be27845400 10783 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
AnnaBridge 172:65be27845400 10784 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 10785 #define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
AnnaBridge 172:65be27845400 10786
AnnaBridge 172:65be27845400 10787 /******************* Bits definition for FLASH_PRAR register *********************/
AnnaBridge 172:65be27845400 10788 #define FLASH_PRAR_PROT_AREA_START_Pos (0U)
AnnaBridge 172:65be27845400 10789 #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 10790 #define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
AnnaBridge 172:65be27845400 10791 #define FLASH_PRAR_PROT_AREA_END_Pos (16U)
AnnaBridge 172:65be27845400 10792 #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 10793 #define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
AnnaBridge 172:65be27845400 10794 #define FLASH_PRAR_DMEP_Pos (31U)
AnnaBridge 172:65be27845400 10795 #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10796 #define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
AnnaBridge 172:65be27845400 10797
AnnaBridge 172:65be27845400 10798 /******************* Bits definition for FLASH_SCAR register *********************/
AnnaBridge 172:65be27845400 10799 #define FLASH_SCAR_SEC_AREA_START_Pos (0U)
AnnaBridge 172:65be27845400 10800 #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 10801 #define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
AnnaBridge 172:65be27845400 10802 #define FLASH_SCAR_SEC_AREA_END_Pos (16U)
AnnaBridge 172:65be27845400 10803 #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 10804 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
AnnaBridge 172:65be27845400 10805 #define FLASH_SCAR_DMES_Pos (31U)
AnnaBridge 172:65be27845400 10806 #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10807 #define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
AnnaBridge 172:65be27845400 10808
AnnaBridge 172:65be27845400 10809 /******************* Bits definition for FLASH_WPSN register *********************/
AnnaBridge 172:65be27845400 10810 #define FLASH_WPSN_WRPSN_Pos (0U)
AnnaBridge 172:65be27845400 10811 #define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 10812 #define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
AnnaBridge 172:65be27845400 10813
AnnaBridge 172:65be27845400 10814 /******************* Bits definition for FLASH_BOOT_CUR register ****************/
AnnaBridge 172:65be27845400 10815 #define FLASH_BOOT_ADD0_Pos (0U)
AnnaBridge 172:65be27845400 10816 #define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 10817 #define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk
AnnaBridge 172:65be27845400 10818 #define FLASH_BOOT_ADD1_Pos (16U)
AnnaBridge 172:65be27845400 10819 #define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 10820 #define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk
AnnaBridge 172:65be27845400 10821
AnnaBridge 172:65be27845400 10822
AnnaBridge 172:65be27845400 10823 /******************* Bits definition for FLASH_CRCCR register ********************/
AnnaBridge 172:65be27845400 10824 #define FLASH_CRCCR_CRC_SECT_Pos (0U)
AnnaBridge 172:65be27845400 10825 #define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 10826 #define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
AnnaBridge 172:65be27845400 10827 #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
AnnaBridge 172:65be27845400 10828 #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10829 #define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
AnnaBridge 172:65be27845400 10830 #define FLASH_CRCCR_ADD_SECT_Pos (9U)
AnnaBridge 172:65be27845400 10831 #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10832 #define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
AnnaBridge 172:65be27845400 10833 #define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
AnnaBridge 172:65be27845400 10834 #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10835 #define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
AnnaBridge 172:65be27845400 10836 #define FLASH_CRCCR_START_CRC_Pos (16U)
AnnaBridge 172:65be27845400 10837 #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10838 #define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
AnnaBridge 172:65be27845400 10839 #define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
AnnaBridge 172:65be27845400 10840 #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10841 #define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
AnnaBridge 172:65be27845400 10842 #define FLASH_CRCCR_CRC_BURST_Pos (20U)
AnnaBridge 172:65be27845400 10843 #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 10844 #define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
AnnaBridge 172:65be27845400 10845 #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10846 #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10847 #define FLASH_CRCCR_ALL_BANK_Pos (22U)
AnnaBridge 172:65be27845400 10848 #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10849 #define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
AnnaBridge 172:65be27845400 10850
AnnaBridge 172:65be27845400 10851 /******************* Bits definition for FLASH_CRCSADD register ****************/
AnnaBridge 172:65be27845400 10852 #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
AnnaBridge 172:65be27845400 10853 #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 10854 #define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
AnnaBridge 172:65be27845400 10855
AnnaBridge 172:65be27845400 10856 /******************* Bits definition for FLASH_CRCEADD register ****************/
AnnaBridge 172:65be27845400 10857 #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
AnnaBridge 172:65be27845400 10858 #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 10859 #define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
AnnaBridge 172:65be27845400 10860
AnnaBridge 172:65be27845400 10861 /******************* Bits definition for FLASH_CRCDATA register ***************/
AnnaBridge 172:65be27845400 10862 #define FLASH_CRCDATA_CRC_DATA_Pos (0U)
AnnaBridge 172:65be27845400 10863 #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 10864 #define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
AnnaBridge 172:65be27845400 10865
AnnaBridge 172:65be27845400 10866 /******************* Bits definition for FLASH_ECC_FA register *******************/
AnnaBridge 172:65be27845400 10867 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
AnnaBridge 172:65be27845400 10868 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 10869 #define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
AnnaBridge 172:65be27845400 10870
AnnaBridge 172:65be27845400 10871 /******************************************************************************/
AnnaBridge 172:65be27845400 10872 /* */
AnnaBridge 172:65be27845400 10873 /* Flexible Memory Controller */
AnnaBridge 172:65be27845400 10874 /* */
AnnaBridge 172:65be27845400 10875 /******************************************************************************/
AnnaBridge 172:65be27845400 10876 /****************** Bit definition for FMC_BCR1 register *******************/
AnnaBridge 172:65be27845400 10877 #define FMC_BCR1_CCLKEN_Pos (20U)
AnnaBridge 172:65be27845400 10878 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10879 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
AnnaBridge 172:65be27845400 10880 #define FMC_BCR1_WFDIS_Pos (21U)
AnnaBridge 172:65be27845400 10881 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10882 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
AnnaBridge 172:65be27845400 10883
AnnaBridge 172:65be27845400 10884 #define FMC_BCR1_BMAP_Pos (24U)
AnnaBridge 172:65be27845400 10885 #define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 10886 #define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
AnnaBridge 172:65be27845400 10887 #define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10888 #define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10889
AnnaBridge 172:65be27845400 10890 #define FMC_BCR1_FMCEN_Pos (31U)
AnnaBridge 172:65be27845400 10891 #define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 10892 #define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
AnnaBridge 172:65be27845400 10893 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
AnnaBridge 172:65be27845400 10894 #define FMC_BCRx_MBKEN_Pos (0U)
AnnaBridge 172:65be27845400 10895 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10896 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 172:65be27845400 10897 #define FMC_BCRx_MUXEN_Pos (1U)
AnnaBridge 172:65be27845400 10898 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10899 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 172:65be27845400 10900
AnnaBridge 172:65be27845400 10901 #define FMC_BCRx_MTYP_Pos (2U)
AnnaBridge 172:65be27845400 10902 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 10903 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 172:65be27845400 10904 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10905 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10906
AnnaBridge 172:65be27845400 10907 #define FMC_BCRx_MWID_Pos (4U)
AnnaBridge 172:65be27845400 10908 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 10909 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 172:65be27845400 10910 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10911 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10912
AnnaBridge 172:65be27845400 10913 #define FMC_BCRx_FACCEN_Pos (6U)
AnnaBridge 172:65be27845400 10914 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10915 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 172:65be27845400 10916 #define FMC_BCRx_BURSTEN_Pos (8U)
AnnaBridge 172:65be27845400 10917 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10918 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 172:65be27845400 10919 #define FMC_BCRx_WAITPOL_Pos (9U)
AnnaBridge 172:65be27845400 10920 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10921 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 172:65be27845400 10922 #define FMC_BCRx_WAITCFG_Pos (11U)
AnnaBridge 172:65be27845400 10923 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10924 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 172:65be27845400 10925 #define FMC_BCRx_WREN_Pos (12U)
AnnaBridge 172:65be27845400 10926 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10927 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
AnnaBridge 172:65be27845400 10928 #define FMC_BCRx_WAITEN_Pos (13U)
AnnaBridge 172:65be27845400 10929 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10930 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 172:65be27845400 10931 #define FMC_BCRx_EXTMOD_Pos (14U)
AnnaBridge 172:65be27845400 10932 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10933 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 172:65be27845400 10934 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
AnnaBridge 172:65be27845400 10935 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10936 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 172:65be27845400 10937
AnnaBridge 172:65be27845400 10938 #define FMC_BCRx_CPSIZE_Pos (16U)
AnnaBridge 172:65be27845400 10939 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 10940 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
AnnaBridge 172:65be27845400 10941 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10942 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10943 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10944
AnnaBridge 172:65be27845400 10945 #define FMC_BCRx_CBURSTRW_Pos (19U)
AnnaBridge 172:65be27845400 10946 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10947 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 172:65be27845400 10948
AnnaBridge 172:65be27845400 10949 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
AnnaBridge 172:65be27845400 10950 #define FMC_BTRx_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 10951 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 10952 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 10953 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 10954 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 10955 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 10956 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 10957
AnnaBridge 172:65be27845400 10958 #define FMC_BTRx_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 10959 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 10960 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 10961 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 10962 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 10963 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 10964 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 10965
AnnaBridge 172:65be27845400 10966 #define FMC_BTRx_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 10967 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 10968 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 10969 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 10970 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 10971 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 10972 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 10973 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 10974 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 10975 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 10976 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 10977
AnnaBridge 172:65be27845400 10978 #define FMC_BTRx_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 10979 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 10980 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 172:65be27845400 10981 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 10982 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 10983 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 10984 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 10985
AnnaBridge 172:65be27845400 10986 #define FMC_BTRx_CLKDIV_Pos (20U)
AnnaBridge 172:65be27845400 10987 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 10988 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 172:65be27845400 10989 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 10990 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 10991 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 10992 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 10993
AnnaBridge 172:65be27845400 10994 #define FMC_BTRx_DATLAT_Pos (24U)
AnnaBridge 172:65be27845400 10995 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 10996 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 172:65be27845400 10997 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 10998 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 10999 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11000 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11001
AnnaBridge 172:65be27845400 11002 #define FMC_BTRx_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 11003 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 11004 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 11005 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11006 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11007
AnnaBridge 172:65be27845400 11008 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
AnnaBridge 172:65be27845400 11009 #define FMC_BWTRx_ADDSET_Pos (0U)
AnnaBridge 172:65be27845400 11010 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 11011 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 172:65be27845400 11012 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11013 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11014 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11015 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11016
AnnaBridge 172:65be27845400 11017 #define FMC_BWTRx_ADDHLD_Pos (4U)
AnnaBridge 172:65be27845400 11018 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 11019 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 172:65be27845400 11020 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11021 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11022 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11023 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11024
AnnaBridge 172:65be27845400 11025 #define FMC_BWTRx_DATAST_Pos (8U)
AnnaBridge 172:65be27845400 11026 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 11027 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 172:65be27845400 11028 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11029 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11030 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11031 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11032 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11033 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11034 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11035 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11036
AnnaBridge 172:65be27845400 11037 #define FMC_BWTRx_BUSTURN_Pos (16U)
AnnaBridge 172:65be27845400 11038 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 11039 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 172:65be27845400 11040 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11041 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11042 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11043 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11044
AnnaBridge 172:65be27845400 11045 #define FMC_BWTRx_ACCMOD_Pos (28U)
AnnaBridge 172:65be27845400 11046 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 11047 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 172:65be27845400 11048 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11049 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11050
AnnaBridge 172:65be27845400 11051 /****************** Bit definition for FMC_PCR register *******************/
AnnaBridge 172:65be27845400 11052 #define FMC_PCR_PWAITEN_Pos (1U)
AnnaBridge 172:65be27845400 11053 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11054 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 172:65be27845400 11055 #define FMC_PCR_PBKEN_Pos (2U)
AnnaBridge 172:65be27845400 11056 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11057 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
AnnaBridge 172:65be27845400 11058
AnnaBridge 172:65be27845400 11059 #define FMC_PCR_PWID_Pos (4U)
AnnaBridge 172:65be27845400 11060 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 11061 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 172:65be27845400 11062 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11063 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11064
AnnaBridge 172:65be27845400 11065 #define FMC_PCR_ECCEN_Pos (6U)
AnnaBridge 172:65be27845400 11066 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11067 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 172:65be27845400 11068
AnnaBridge 172:65be27845400 11069 #define FMC_PCR_TCLR_Pos (9U)
AnnaBridge 172:65be27845400 11070 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 172:65be27845400 11071 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 172:65be27845400 11072 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11073 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11074 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11075 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11076
AnnaBridge 172:65be27845400 11077 #define FMC_PCR_TAR_Pos (13U)
AnnaBridge 172:65be27845400 11078 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 11079 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 172:65be27845400 11080 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11081 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11082 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11083 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11084
AnnaBridge 172:65be27845400 11085 #define FMC_PCR_ECCPS_Pos (17U)
AnnaBridge 172:65be27845400 11086 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 11087 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
AnnaBridge 172:65be27845400 11088 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11089 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11090 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11091
AnnaBridge 172:65be27845400 11092 /******************* Bit definition for FMC_SR register *******************/
AnnaBridge 172:65be27845400 11093 #define FMC_SR_IRS_Pos (0U)
AnnaBridge 172:65be27845400 11094 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11095 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 172:65be27845400 11096 #define FMC_SR_ILS_Pos (1U)
AnnaBridge 172:65be27845400 11097 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11098 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 172:65be27845400 11099 #define FMC_SR_IFS_Pos (2U)
AnnaBridge 172:65be27845400 11100 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11101 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 172:65be27845400 11102 #define FMC_SR_IREN_Pos (3U)
AnnaBridge 172:65be27845400 11103 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11104 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 172:65be27845400 11105 #define FMC_SR_ILEN_Pos (4U)
AnnaBridge 172:65be27845400 11106 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11107 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 172:65be27845400 11108 #define FMC_SR_IFEN_Pos (5U)
AnnaBridge 172:65be27845400 11109 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11110 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 172:65be27845400 11111 #define FMC_SR_FEMPT_Pos (6U)
AnnaBridge 172:65be27845400 11112 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11113 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
AnnaBridge 172:65be27845400 11114
AnnaBridge 172:65be27845400 11115 /****************** Bit definition for FMC_PMEM register ******************/
AnnaBridge 172:65be27845400 11116 #define FMC_PMEM_MEMSET_Pos (0U)
AnnaBridge 172:65be27845400 11117 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 11118 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
AnnaBridge 172:65be27845400 11119 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11120 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11121 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11122 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11123 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11124 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11125 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11126 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11127
AnnaBridge 172:65be27845400 11128 #define FMC_PMEM_MEMWAIT_Pos (8U)
AnnaBridge 172:65be27845400 11129 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 11130 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
AnnaBridge 172:65be27845400 11131 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11132 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11133 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11134 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11135 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11136 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11137 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11138 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11139
AnnaBridge 172:65be27845400 11140 #define FMC_PMEM_MEMHOLD_Pos (16U)
AnnaBridge 172:65be27845400 11141 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 11142 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
AnnaBridge 172:65be27845400 11143 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11144 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11145 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11146 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11147 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11148 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11149 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11150 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11151
AnnaBridge 172:65be27845400 11152 #define FMC_PMEM_MEMHIZ_Pos (24U)
AnnaBridge 172:65be27845400 11153 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 11154 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
AnnaBridge 172:65be27845400 11155 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11156 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11157 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11158 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11159 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11160 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11161 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11162 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11163
AnnaBridge 172:65be27845400 11164 /****************** Bit definition for FMC_PATT register ******************/
AnnaBridge 172:65be27845400 11165 #define FMC_PATT_ATTSET_Pos (0U)
AnnaBridge 172:65be27845400 11166 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 11167 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
AnnaBridge 172:65be27845400 11168 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11169 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11170 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11171 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11172 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11173 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11174 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11175 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11176
AnnaBridge 172:65be27845400 11177 #define FMC_PATT_ATTWAIT_Pos (8U)
AnnaBridge 172:65be27845400 11178 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 11179 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
AnnaBridge 172:65be27845400 11180 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11181 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11182 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11183 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11184 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11185 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11186 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11187 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11188
AnnaBridge 172:65be27845400 11189 #define FMC_PATT_ATTHOLD_Pos (16U)
AnnaBridge 172:65be27845400 11190 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 11191 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
AnnaBridge 172:65be27845400 11192 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11193 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11194 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11195 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11196 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11197 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11198 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11199 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11200
AnnaBridge 172:65be27845400 11201 #define FMC_PATT_ATTHIZ_Pos (24U)
AnnaBridge 172:65be27845400 11202 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 11203 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
AnnaBridge 172:65be27845400 11204 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11205 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11206 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11207 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11208 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11209 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11210 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11211 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11212
AnnaBridge 172:65be27845400 11213 /****************** Bit definition for FMC_ECCR3 register ******************/
AnnaBridge 172:65be27845400 11214 #define FMC_ECCR3_ECC3_Pos (0U)
AnnaBridge 172:65be27845400 11215 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 11216 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
AnnaBridge 172:65be27845400 11217
AnnaBridge 172:65be27845400 11218 /****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
AnnaBridge 172:65be27845400 11219 #define FMC_SDCRx_NC_Pos (0U)
AnnaBridge 172:65be27845400 11220 #define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 11221 #define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 172:65be27845400 11222 #define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11223 #define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11224
AnnaBridge 172:65be27845400 11225 #define FMC_SDCRx_NR_Pos (2U)
AnnaBridge 172:65be27845400 11226 #define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 11227 #define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 172:65be27845400 11228 #define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11229 #define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11230
AnnaBridge 172:65be27845400 11231 #define FMC_SDCRx_MWID_Pos (4U)
AnnaBridge 172:65be27845400 11232 #define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 11233 #define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 172:65be27845400 11234 #define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11235 #define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11236
AnnaBridge 172:65be27845400 11237 #define FMC_SDCRx_NB_Pos (6U)
AnnaBridge 172:65be27845400 11238 #define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11239 #define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */
AnnaBridge 172:65be27845400 11240
AnnaBridge 172:65be27845400 11241 #define FMC_SDCRx_CAS_Pos (7U)
AnnaBridge 172:65be27845400 11242 #define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
AnnaBridge 172:65be27845400 11243 #define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 172:65be27845400 11244 #define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11245 #define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11246
AnnaBridge 172:65be27845400 11247 #define FMC_SDCRx_WP_Pos (9U)
AnnaBridge 172:65be27845400 11248 #define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11249 #define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */
AnnaBridge 172:65be27845400 11250
AnnaBridge 172:65be27845400 11251 #define FMC_SDCRx_SDCLK_Pos (10U)
AnnaBridge 172:65be27845400 11252 #define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 11253 #define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */
AnnaBridge 172:65be27845400 11254 #define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11255 #define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11256
AnnaBridge 172:65be27845400 11257 #define FMC_SDCRx_RBURST_Pos (12U)
AnnaBridge 172:65be27845400 11258 #define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11259 #define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */
AnnaBridge 172:65be27845400 11260
AnnaBridge 172:65be27845400 11261 #define FMC_SDCRx_RPIPE_Pos (13U)
AnnaBridge 172:65be27845400 11262 #define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 11263 #define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */
AnnaBridge 172:65be27845400 11264 #define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11265 #define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11266
AnnaBridge 172:65be27845400 11267 /****************** Bit definition for FMC_SDTRx(1,2) register ******************/
AnnaBridge 172:65be27845400 11268 #define FMC_SDTRx_TMRD_Pos (0U)
AnnaBridge 172:65be27845400 11269 #define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 11270 #define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 172:65be27845400 11271 #define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11272 #define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11273 #define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11274 #define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11275
AnnaBridge 172:65be27845400 11276 #define FMC_SDTRx_TXSR_Pos (4U)
AnnaBridge 172:65be27845400 11277 #define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 11278 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 172:65be27845400 11279 #define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11280 #define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11281 #define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11282 #define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11283
AnnaBridge 172:65be27845400 11284 #define FMC_SDTRx_TRAS_Pos (8U)
AnnaBridge 172:65be27845400 11285 #define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 11286 #define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 172:65be27845400 11287 #define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11288 #define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11289 #define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11290 #define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11291
AnnaBridge 172:65be27845400 11292 #define FMC_SDTRx_TRC_Pos (12U)
AnnaBridge 172:65be27845400 11293 #define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 11294 #define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 172:65be27845400 11295 #define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11296 #define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11297 #define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11298
AnnaBridge 172:65be27845400 11299 #define FMC_SDTRx_TWR_Pos (16U)
AnnaBridge 172:65be27845400 11300 #define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 11301 #define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 172:65be27845400 11302 #define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11303 #define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11304 #define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11305
AnnaBridge 172:65be27845400 11306 #define FMC_SDTRx_TRP_Pos (20U)
AnnaBridge 172:65be27845400 11307 #define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 11308 #define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 172:65be27845400 11309 #define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11310 #define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11311 #define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11312
AnnaBridge 172:65be27845400 11313 #define FMC_SDTRx_TRCD_Pos (24U)
AnnaBridge 172:65be27845400 11314 #define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 11315 #define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 172:65be27845400 11316 #define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11317 #define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11318 #define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11319
AnnaBridge 172:65be27845400 11320 /****************** Bit definition for FMC_SDCMR register ******************/
AnnaBridge 172:65be27845400 11321 #define FMC_SDCMR_MODE_Pos (0U)
AnnaBridge 172:65be27845400 11322 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 11323 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
AnnaBridge 172:65be27845400 11324 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11325 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11326 #define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 11327
AnnaBridge 172:65be27845400 11328 #define FMC_SDCMR_CTB2_Pos (3U)
AnnaBridge 172:65be27845400 11329 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11330 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
AnnaBridge 172:65be27845400 11331
AnnaBridge 172:65be27845400 11332 #define FMC_SDCMR_CTB1_Pos (4U)
AnnaBridge 172:65be27845400 11333 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11334 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
AnnaBridge 172:65be27845400 11335
AnnaBridge 172:65be27845400 11336 #define FMC_SDCMR_NRFS_Pos (5U)
AnnaBridge 172:65be27845400 11337 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
AnnaBridge 172:65be27845400 11338 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
AnnaBridge 172:65be27845400 11339 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11340 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11341 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11342 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11343
AnnaBridge 172:65be27845400 11344 #define FMC_SDCMR_MRD_Pos (9U)
AnnaBridge 172:65be27845400 11345 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
AnnaBridge 172:65be27845400 11346 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
AnnaBridge 172:65be27845400 11347
AnnaBridge 172:65be27845400 11348 /****************** Bit definition for FMC_SDRTR register ******************/
AnnaBridge 172:65be27845400 11349 #define FMC_SDRTR_CRE_Pos (0U)
AnnaBridge 172:65be27845400 11350 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11351 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
AnnaBridge 172:65be27845400 11352
AnnaBridge 172:65be27845400 11353 #define FMC_SDRTR_COUNT_Pos (1U)
AnnaBridge 172:65be27845400 11354 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
AnnaBridge 172:65be27845400 11355 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
AnnaBridge 172:65be27845400 11356
AnnaBridge 172:65be27845400 11357 #define FMC_SDRTR_REIE_Pos (14U)
AnnaBridge 172:65be27845400 11358 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11359 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
AnnaBridge 172:65be27845400 11360
AnnaBridge 172:65be27845400 11361 /****************** Bit definition for FMC_SDSR register ******************/
AnnaBridge 172:65be27845400 11362 #define FMC_SDSR_RE_Pos (0U)
AnnaBridge 172:65be27845400 11363 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11364 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
AnnaBridge 172:65be27845400 11365
AnnaBridge 172:65be27845400 11366 #define FMC_SDSR_MODES1_Pos (1U)
AnnaBridge 172:65be27845400 11367 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 11368 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
AnnaBridge 172:65be27845400 11369 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11370 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11371
AnnaBridge 172:65be27845400 11372 #define FMC_SDSR_MODES2_Pos (3U)
AnnaBridge 172:65be27845400 11373 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 11374 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
AnnaBridge 172:65be27845400 11375 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11376 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11377
AnnaBridge 172:65be27845400 11378 /******************************************************************************/
AnnaBridge 172:65be27845400 11379 /* */
AnnaBridge 172:65be27845400 11380 /* General Purpose I/O */
AnnaBridge 172:65be27845400 11381 /* */
AnnaBridge 172:65be27845400 11382 /******************************************************************************/
AnnaBridge 172:65be27845400 11383 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 172:65be27845400 11384 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 172:65be27845400 11385 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 11386 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 172:65be27845400 11387 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11388 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11389
AnnaBridge 172:65be27845400 11390 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 172:65be27845400 11391 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 11392 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 172:65be27845400 11393 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11394 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11395
AnnaBridge 172:65be27845400 11396 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 172:65be27845400 11397 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 11398 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 172:65be27845400 11399 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11400 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11401
AnnaBridge 172:65be27845400 11402 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 172:65be27845400 11403 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 11404 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 172:65be27845400 11405 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11406 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11407
AnnaBridge 172:65be27845400 11408 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 172:65be27845400 11409 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 11410 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 172:65be27845400 11411 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11412 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11413
AnnaBridge 172:65be27845400 11414 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 172:65be27845400 11415 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 11416 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 172:65be27845400 11417 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11418 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11419
AnnaBridge 172:65be27845400 11420 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 172:65be27845400 11421 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 11422 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 172:65be27845400 11423 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11424 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11425
AnnaBridge 172:65be27845400 11426 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 172:65be27845400 11427 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 11428 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 172:65be27845400 11429 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11430 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11431
AnnaBridge 172:65be27845400 11432 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 172:65be27845400 11433 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 11434 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 172:65be27845400 11435 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11436 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11437
AnnaBridge 172:65be27845400 11438 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 172:65be27845400 11439 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 11440 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 172:65be27845400 11441 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11442 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11443
AnnaBridge 172:65be27845400 11444 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 172:65be27845400 11445 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 11446 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 172:65be27845400 11447 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11448 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11449
AnnaBridge 172:65be27845400 11450 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 172:65be27845400 11451 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 11452 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 172:65be27845400 11453 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11454 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11455
AnnaBridge 172:65be27845400 11456 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 172:65be27845400 11457 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 11458 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 172:65be27845400 11459 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11460 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11461
AnnaBridge 172:65be27845400 11462 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 172:65be27845400 11463 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 11464 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 172:65be27845400 11465 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11466 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11467
AnnaBridge 172:65be27845400 11468 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 172:65be27845400 11469 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 11470 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 172:65be27845400 11471 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11472 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11473
AnnaBridge 172:65be27845400 11474 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 172:65be27845400 11475 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 11476 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 172:65be27845400 11477 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11478 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11479
AnnaBridge 172:65be27845400 11480 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 172:65be27845400 11481 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 172:65be27845400 11482 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11483 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 172:65be27845400 11484 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 172:65be27845400 11485 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11486 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 172:65be27845400 11487 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 172:65be27845400 11488 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11489 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 172:65be27845400 11490 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 172:65be27845400 11491 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11492 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 172:65be27845400 11493 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 172:65be27845400 11494 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11495 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 172:65be27845400 11496 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 172:65be27845400 11497 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11498 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 172:65be27845400 11499 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 172:65be27845400 11500 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11501 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 172:65be27845400 11502 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 172:65be27845400 11503 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11504 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 172:65be27845400 11505 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 172:65be27845400 11506 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11507 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 172:65be27845400 11508 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 172:65be27845400 11509 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11510 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 172:65be27845400 11511 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 172:65be27845400 11512 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11513 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 172:65be27845400 11514 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 172:65be27845400 11515 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11516 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 172:65be27845400 11517 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 172:65be27845400 11518 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11519 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 172:65be27845400 11520 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 172:65be27845400 11521 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11522 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 172:65be27845400 11523 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 172:65be27845400 11524 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11525 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 172:65be27845400 11526 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 172:65be27845400 11527 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11528 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 172:65be27845400 11529
AnnaBridge 172:65be27845400 11530 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 172:65be27845400 11531 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 172:65be27845400 11532 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 11533 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 172:65be27845400 11534 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11535 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11536
AnnaBridge 172:65be27845400 11537 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 172:65be27845400 11538 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 11539 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 172:65be27845400 11540 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11541 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11542
AnnaBridge 172:65be27845400 11543 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 172:65be27845400 11544 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 11545 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 172:65be27845400 11546 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11547 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11548
AnnaBridge 172:65be27845400 11549 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 172:65be27845400 11550 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 11551 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 172:65be27845400 11552 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11553 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11554
AnnaBridge 172:65be27845400 11555 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 172:65be27845400 11556 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 11557 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 172:65be27845400 11558 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11559 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11560
AnnaBridge 172:65be27845400 11561 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 172:65be27845400 11562 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 11563 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 172:65be27845400 11564 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11565 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11566
AnnaBridge 172:65be27845400 11567 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 172:65be27845400 11568 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 11569 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 172:65be27845400 11570 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11571 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11572
AnnaBridge 172:65be27845400 11573 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 172:65be27845400 11574 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 11575 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 172:65be27845400 11576 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11577 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11578
AnnaBridge 172:65be27845400 11579 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 172:65be27845400 11580 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 11581 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 172:65be27845400 11582 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11583 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11584
AnnaBridge 172:65be27845400 11585 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 172:65be27845400 11586 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 11587 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 172:65be27845400 11588 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11589 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11590
AnnaBridge 172:65be27845400 11591 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 172:65be27845400 11592 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 11593 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 172:65be27845400 11594 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11595 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11596
AnnaBridge 172:65be27845400 11597 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 172:65be27845400 11598 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 11599 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 172:65be27845400 11600 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11601 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11602
AnnaBridge 172:65be27845400 11603 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 172:65be27845400 11604 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 11605 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 172:65be27845400 11606 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11607 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11608
AnnaBridge 172:65be27845400 11609 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 172:65be27845400 11610 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 11611 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 172:65be27845400 11612 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11613 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11614
AnnaBridge 172:65be27845400 11615 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 172:65be27845400 11616 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 11617 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 172:65be27845400 11618 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11619 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11620
AnnaBridge 172:65be27845400 11621 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 172:65be27845400 11622 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 11623 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 172:65be27845400 11624 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11625 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11626
AnnaBridge 172:65be27845400 11627 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 172:65be27845400 11628 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 172:65be27845400 11629 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 11630 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 172:65be27845400 11631 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11632 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11633
AnnaBridge 172:65be27845400 11634 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 172:65be27845400 11635 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 11636 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 172:65be27845400 11637 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11638 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11639
AnnaBridge 172:65be27845400 11640 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 172:65be27845400 11641 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 11642 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 172:65be27845400 11643 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11644 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11645
AnnaBridge 172:65be27845400 11646 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 172:65be27845400 11647 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 11648 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 172:65be27845400 11649 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11650 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11651
AnnaBridge 172:65be27845400 11652 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 172:65be27845400 11653 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 11654 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 172:65be27845400 11655 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11656 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11657
AnnaBridge 172:65be27845400 11658 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 172:65be27845400 11659 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 11660 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 172:65be27845400 11661 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11662 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11663
AnnaBridge 172:65be27845400 11664 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 172:65be27845400 11665 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 11666 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 172:65be27845400 11667 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11668 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11669
AnnaBridge 172:65be27845400 11670 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 172:65be27845400 11671 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 11672 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 172:65be27845400 11673 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11674 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11675
AnnaBridge 172:65be27845400 11676 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 172:65be27845400 11677 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 11678 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 172:65be27845400 11679 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11680 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11681
AnnaBridge 172:65be27845400 11682 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 172:65be27845400 11683 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 11684 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 172:65be27845400 11685 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11686 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11687
AnnaBridge 172:65be27845400 11688 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 172:65be27845400 11689 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 11690 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 172:65be27845400 11691 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11692 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11693
AnnaBridge 172:65be27845400 11694 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 172:65be27845400 11695 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 11696 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 172:65be27845400 11697 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11698 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11699
AnnaBridge 172:65be27845400 11700 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 172:65be27845400 11701 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 11702 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 172:65be27845400 11703 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11704 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11705
AnnaBridge 172:65be27845400 11706 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 172:65be27845400 11707 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 11708 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 172:65be27845400 11709 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11710 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11711
AnnaBridge 172:65be27845400 11712 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 172:65be27845400 11713 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 11714 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 172:65be27845400 11715 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11716 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11717
AnnaBridge 172:65be27845400 11718 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 172:65be27845400 11719 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 11720 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 172:65be27845400 11721 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11722 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11723
AnnaBridge 172:65be27845400 11724 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 172:65be27845400 11725 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 172:65be27845400 11726 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11727 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 172:65be27845400 11728 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 172:65be27845400 11729 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11730 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 172:65be27845400 11731 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 172:65be27845400 11732 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11733 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 172:65be27845400 11734 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 172:65be27845400 11735 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11736 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 172:65be27845400 11737 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 172:65be27845400 11738 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11739 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 172:65be27845400 11740 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 172:65be27845400 11741 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11742 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 172:65be27845400 11743 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 172:65be27845400 11744 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11745 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 172:65be27845400 11746 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 172:65be27845400 11747 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11748 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 172:65be27845400 11749 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 172:65be27845400 11750 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11751 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 172:65be27845400 11752 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 172:65be27845400 11753 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11754 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 172:65be27845400 11755 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 172:65be27845400 11756 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11757 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 172:65be27845400 11758 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 172:65be27845400 11759 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11760 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 172:65be27845400 11761 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 172:65be27845400 11762 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11763 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 172:65be27845400 11764 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 172:65be27845400 11765 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11766 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 172:65be27845400 11767 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 172:65be27845400 11768 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11769 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 172:65be27845400 11770 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 172:65be27845400 11771 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11772 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 172:65be27845400 11773
AnnaBridge 172:65be27845400 11774 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 172:65be27845400 11775 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 172:65be27845400 11776 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11777 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 172:65be27845400 11778 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 172:65be27845400 11779 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11780 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 172:65be27845400 11781 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 172:65be27845400 11782 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11783 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 172:65be27845400 11784 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 172:65be27845400 11785 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11786 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 172:65be27845400 11787 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 172:65be27845400 11788 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11789 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 172:65be27845400 11790 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 172:65be27845400 11791 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11792 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 172:65be27845400 11793 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 172:65be27845400 11794 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11795 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 172:65be27845400 11796 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 172:65be27845400 11797 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11798 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 172:65be27845400 11799 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 172:65be27845400 11800 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11801 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 172:65be27845400 11802 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 172:65be27845400 11803 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11804 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 172:65be27845400 11805 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 172:65be27845400 11806 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11807 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 172:65be27845400 11808 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 172:65be27845400 11809 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11810 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 172:65be27845400 11811 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 172:65be27845400 11812 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11813 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 172:65be27845400 11814 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 172:65be27845400 11815 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11816 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 172:65be27845400 11817 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 172:65be27845400 11818 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11819 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 172:65be27845400 11820 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 172:65be27845400 11821 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11822 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 172:65be27845400 11823
AnnaBridge 172:65be27845400 11824 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 172:65be27845400 11825 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 172:65be27845400 11826 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11827 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 172:65be27845400 11828 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 172:65be27845400 11829 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11830 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 172:65be27845400 11831 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 172:65be27845400 11832 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11833 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 172:65be27845400 11834 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 172:65be27845400 11835 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11836 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 172:65be27845400 11837 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 172:65be27845400 11838 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11839 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 172:65be27845400 11840 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 172:65be27845400 11841 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11842 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 172:65be27845400 11843 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 172:65be27845400 11844 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11845 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 172:65be27845400 11846 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 172:65be27845400 11847 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11848 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 172:65be27845400 11849 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 172:65be27845400 11850 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11851 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 172:65be27845400 11852 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 172:65be27845400 11853 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11854 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 172:65be27845400 11855 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 172:65be27845400 11856 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11857 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 172:65be27845400 11858 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 172:65be27845400 11859 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11860 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 172:65be27845400 11861 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 172:65be27845400 11862 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11863 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 172:65be27845400 11864 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 172:65be27845400 11865 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11866 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 172:65be27845400 11867 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 172:65be27845400 11868 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11869 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 172:65be27845400 11870 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 172:65be27845400 11871 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11872 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 172:65be27845400 11873 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 172:65be27845400 11874 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11875 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 172:65be27845400 11876 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 172:65be27845400 11877 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 11878 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 172:65be27845400 11879 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 172:65be27845400 11880 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 11881 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 172:65be27845400 11882 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 172:65be27845400 11883 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 11884 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 172:65be27845400 11885 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 172:65be27845400 11886 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 11887 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 172:65be27845400 11888 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 172:65be27845400 11889 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 11890 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 172:65be27845400 11891 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 172:65be27845400 11892 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 11893 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 172:65be27845400 11894 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 172:65be27845400 11895 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 11896 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 172:65be27845400 11897 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 172:65be27845400 11898 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 11899 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 172:65be27845400 11900 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 172:65be27845400 11901 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 11902 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 172:65be27845400 11903 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 172:65be27845400 11904 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 11905 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 172:65be27845400 11906 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 172:65be27845400 11907 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 11908 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 172:65be27845400 11909 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 172:65be27845400 11910 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 11911 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 172:65be27845400 11912 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 172:65be27845400 11913 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 11914 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 172:65be27845400 11915 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 172:65be27845400 11916 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 11917 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 172:65be27845400 11918 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 172:65be27845400 11919 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 11920 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 172:65be27845400 11921
AnnaBridge 172:65be27845400 11922 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 172:65be27845400 11923 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 172:65be27845400 11924 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11925 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 172:65be27845400 11926 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 172:65be27845400 11927 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11928 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 172:65be27845400 11929 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 172:65be27845400 11930 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11931 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 172:65be27845400 11932 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 172:65be27845400 11933 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11934 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 172:65be27845400 11935 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 172:65be27845400 11936 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11937 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 172:65be27845400 11938 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 172:65be27845400 11939 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11940 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 172:65be27845400 11941 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 172:65be27845400 11942 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11943 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 172:65be27845400 11944 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 172:65be27845400 11945 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11946 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 172:65be27845400 11947 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 172:65be27845400 11948 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11949 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 172:65be27845400 11950 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 172:65be27845400 11951 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11952 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 172:65be27845400 11953 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 172:65be27845400 11954 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11955 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 172:65be27845400 11956 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 172:65be27845400 11957 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11958 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 172:65be27845400 11959 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 172:65be27845400 11960 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 11961 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 172:65be27845400 11962 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 172:65be27845400 11963 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 11964 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 172:65be27845400 11965 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 172:65be27845400 11966 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 11967 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 172:65be27845400 11968 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 172:65be27845400 11969 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 11970 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 172:65be27845400 11971 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 172:65be27845400 11972 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 11973 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 172:65be27845400 11974
AnnaBridge 172:65be27845400 11975 /****************** Bit definition for GPIO_AFRL register ********************/
AnnaBridge 172:65be27845400 11976 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 172:65be27845400 11977 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 11978 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 172:65be27845400 11979 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 11980 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 11981 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 11982 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 11983 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 172:65be27845400 11984 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 11985 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 172:65be27845400 11986 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 11987 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 11988 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 11989 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 11990 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 172:65be27845400 11991 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 11992 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 172:65be27845400 11993 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 11994 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 11995 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 11996 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 11997 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 172:65be27845400 11998 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 11999 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 172:65be27845400 12000 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12001 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12002 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12003 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12004 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 172:65be27845400 12005 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 12006 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 172:65be27845400 12007 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12008 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12009 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12010 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12011 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 172:65be27845400 12012 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 12013 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 172:65be27845400 12014 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12015 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12016 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12017 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12018 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 172:65be27845400 12019 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 12020 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 172:65be27845400 12021 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12022 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12023 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12024 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12025 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 172:65be27845400 12026 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 12027 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 172:65be27845400 12028 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12029 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12030 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12031 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12032
AnnaBridge 172:65be27845400 12033 /* Legacy defines */
AnnaBridge 172:65be27845400 12034 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 172:65be27845400 12035 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 172:65be27845400 12036 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 172:65be27845400 12037 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 172:65be27845400 12038 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 172:65be27845400 12039 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 172:65be27845400 12040 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 172:65be27845400 12041 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 172:65be27845400 12042
AnnaBridge 172:65be27845400 12043 /****************** Bit definition for GPIO_AFRH register ********************/
AnnaBridge 172:65be27845400 12044 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 172:65be27845400 12045 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 12046 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 172:65be27845400 12047 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12048 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12049 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12050 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12051 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 172:65be27845400 12052 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 12053 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 172:65be27845400 12054 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12055 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12056 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12057 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12058 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 172:65be27845400 12059 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12060 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 172:65be27845400 12061 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12062 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12063 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12064 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12065 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 172:65be27845400 12066 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 12067 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 172:65be27845400 12068 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12069 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12070 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12071 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12072 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 172:65be27845400 12073 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 12074 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 172:65be27845400 12075 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12076 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12077 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12078 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12079 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 172:65be27845400 12080 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 12081 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 172:65be27845400 12082 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12083 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12084 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12085 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12086 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 172:65be27845400 12087 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 12088 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 172:65be27845400 12089 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12090 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12091 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12092 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12093 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 172:65be27845400 12094 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 12095 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 172:65be27845400 12096 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12097 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12098 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12099 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12100
AnnaBridge 172:65be27845400 12101 /* Legacy defines */
AnnaBridge 172:65be27845400 12102 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 172:65be27845400 12103 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 172:65be27845400 12104 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 172:65be27845400 12105 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 172:65be27845400 12106 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 172:65be27845400 12107 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 172:65be27845400 12108 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 172:65be27845400 12109 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 172:65be27845400 12110
AnnaBridge 172:65be27845400 12111 /******************************************************************************/
AnnaBridge 172:65be27845400 12112 /* */
AnnaBridge 172:65be27845400 12113 /* HSEM HW Semaphore */
AnnaBridge 172:65be27845400 12114 /* */
AnnaBridge 172:65be27845400 12115 /******************************************************************************/
AnnaBridge 172:65be27845400 12116 /******************** Bit definition for HSEM_R register ********************/
AnnaBridge 172:65be27845400 12117 #define HSEM_R_PROCID_Pos (0U)
AnnaBridge 172:65be27845400 12118 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12119 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
AnnaBridge 172:65be27845400 12120 #define HSEM_R_COREID_Pos (8U)
AnnaBridge 172:65be27845400 12121 #define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 12122 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
AnnaBridge 172:65be27845400 12123 #define HSEM_R_LOCK_Pos (31U)
AnnaBridge 172:65be27845400 12124 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12125 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
AnnaBridge 172:65be27845400 12126
AnnaBridge 172:65be27845400 12127 /******************** Bit definition for HSEM_RLR register ******************/
AnnaBridge 172:65be27845400 12128 #define HSEM_RLR_PROCID_Pos (0U)
AnnaBridge 172:65be27845400 12129 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12130 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
AnnaBridge 172:65be27845400 12131 #define HSEM_RLR_COREID_Pos (8U)
AnnaBridge 172:65be27845400 12132 #define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 12133 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
AnnaBridge 172:65be27845400 12134 #define HSEM_RLR_LOCK_Pos (31U)
AnnaBridge 172:65be27845400 12135 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12136 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
AnnaBridge 172:65be27845400 12137
AnnaBridge 172:65be27845400 12138 /******************** Bit definition for HSEM_C1IER register *****************/
AnnaBridge 172:65be27845400 12139 #define HSEM_C1IER_ISE0_Pos (0U)
AnnaBridge 172:65be27845400 12140 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12141 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12142 #define HSEM_C1IER_ISE1_Pos (1U)
AnnaBridge 172:65be27845400 12143 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12144 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12145 #define HSEM_C1IER_ISE2_Pos (2U)
AnnaBridge 172:65be27845400 12146 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12147 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12148 #define HSEM_C1IER_ISE3_Pos (3U)
AnnaBridge 172:65be27845400 12149 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12150 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12151 #define HSEM_C1IER_ISE4_Pos (4U)
AnnaBridge 172:65be27845400 12152 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12153 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12154 #define HSEM_C1IER_ISE5_Pos (5U)
AnnaBridge 172:65be27845400 12155 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12156 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12157 #define HSEM_C1IER_ISE6_Pos (6U)
AnnaBridge 172:65be27845400 12158 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12159 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12160 #define HSEM_C1IER_ISE7_Pos (7U)
AnnaBridge 172:65be27845400 12161 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12162 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12163 #define HSEM_C1IER_ISE8_Pos (8U)
AnnaBridge 172:65be27845400 12164 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12165 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12166 #define HSEM_C1IER_ISE9_Pos (9U)
AnnaBridge 172:65be27845400 12167 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12168 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12169 #define HSEM_C1IER_ISE10_Pos (10U)
AnnaBridge 172:65be27845400 12170 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12171 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12172 #define HSEM_C1IER_ISE11_Pos (11U)
AnnaBridge 172:65be27845400 12173 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12174 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12175 #define HSEM_C1IER_ISE12_Pos (12U)
AnnaBridge 172:65be27845400 12176 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12177 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12178 #define HSEM_C1IER_ISE13_Pos (13U)
AnnaBridge 172:65be27845400 12179 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12180 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12181 #define HSEM_C1IER_ISE14_Pos (14U)
AnnaBridge 172:65be27845400 12182 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12183 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12184 #define HSEM_C1IER_ISE15_Pos (15U)
AnnaBridge 172:65be27845400 12185 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12186 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12187 #define HSEM_C1IER_ISE16_Pos (16U)
AnnaBridge 172:65be27845400 12188 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12189 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12190 #define HSEM_C1IER_ISE17_Pos (17U)
AnnaBridge 172:65be27845400 12191 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12192 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12193 #define HSEM_C1IER_ISE18_Pos (18U)
AnnaBridge 172:65be27845400 12194 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12195 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12196 #define HSEM_C1IER_ISE19_Pos (19U)
AnnaBridge 172:65be27845400 12197 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12198 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12199 #define HSEM_C1IER_ISE20_Pos (20U)
AnnaBridge 172:65be27845400 12200 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12201 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12202 #define HSEM_C1IER_ISE21_Pos (21U)
AnnaBridge 172:65be27845400 12203 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12204 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12205 #define HSEM_C1IER_ISE22_Pos (22U)
AnnaBridge 172:65be27845400 12206 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12207 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12208 #define HSEM_C1IER_ISE23_Pos (23U)
AnnaBridge 172:65be27845400 12209 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12210 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12211 #define HSEM_C1IER_ISE24_Pos (24U)
AnnaBridge 172:65be27845400 12212 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12213 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12214 #define HSEM_C1IER_ISE25_Pos (25U)
AnnaBridge 172:65be27845400 12215 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12216 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12217 #define HSEM_C1IER_ISE26_Pos (26U)
AnnaBridge 172:65be27845400 12218 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12219 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12220 #define HSEM_C1IER_ISE27_Pos (27U)
AnnaBridge 172:65be27845400 12221 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12222 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12223 #define HSEM_C1IER_ISE28_Pos (28U)
AnnaBridge 172:65be27845400 12224 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12225 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12226 #define HSEM_C1IER_ISE29_Pos (29U)
AnnaBridge 172:65be27845400 12227 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12228 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12229 #define HSEM_C1IER_ISE30_Pos (30U)
AnnaBridge 172:65be27845400 12230 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12231 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12232 #define HSEM_C1IER_ISE31_Pos (31U)
AnnaBridge 172:65be27845400 12233 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12234 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
AnnaBridge 172:65be27845400 12235
AnnaBridge 172:65be27845400 12236 /******************** Bit definition for HSEM_C1ICR register *****************/
AnnaBridge 172:65be27845400 12237 #define HSEM_C1ICR_ISC0_Pos (0U)
AnnaBridge 172:65be27845400 12238 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12239 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12240 #define HSEM_C1ICR_ISC1_Pos (1U)
AnnaBridge 172:65be27845400 12241 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12242 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12243 #define HSEM_C1ICR_ISC2_Pos (2U)
AnnaBridge 172:65be27845400 12244 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12245 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12246 #define HSEM_C1ICR_ISC3_Pos (3U)
AnnaBridge 172:65be27845400 12247 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12248 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12249 #define HSEM_C1ICR_ISC4_Pos (4U)
AnnaBridge 172:65be27845400 12250 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12251 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12252 #define HSEM_C1ICR_ISC5_Pos (5U)
AnnaBridge 172:65be27845400 12253 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12254 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12255 #define HSEM_C1ICR_ISC6_Pos (6U)
AnnaBridge 172:65be27845400 12256 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12257 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12258 #define HSEM_C1ICR_ISC7_Pos (7U)
AnnaBridge 172:65be27845400 12259 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12260 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12261 #define HSEM_C1ICR_ISC8_Pos (8U)
AnnaBridge 172:65be27845400 12262 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12263 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12264 #define HSEM_C1ICR_ISC9_Pos (9U)
AnnaBridge 172:65be27845400 12265 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12266 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12267 #define HSEM_C1ICR_ISC10_Pos (10U)
AnnaBridge 172:65be27845400 12268 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12269 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12270 #define HSEM_C1ICR_ISC11_Pos (11U)
AnnaBridge 172:65be27845400 12271 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12272 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12273 #define HSEM_C1ICR_ISC12_Pos (12U)
AnnaBridge 172:65be27845400 12274 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12275 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12276 #define HSEM_C1ICR_ISC13_Pos (13U)
AnnaBridge 172:65be27845400 12277 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12278 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12279 #define HSEM_C1ICR_ISC14_Pos (14U)
AnnaBridge 172:65be27845400 12280 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12281 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12282 #define HSEM_C1ICR_ISC15_Pos (15U)
AnnaBridge 172:65be27845400 12283 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12284 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12285 #define HSEM_C1ICR_ISC16_Pos (16U)
AnnaBridge 172:65be27845400 12286 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12287 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12288 #define HSEM_C1ICR_ISC17_Pos (17U)
AnnaBridge 172:65be27845400 12289 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12290 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12291 #define HSEM_C1ICR_ISC18_Pos (18U)
AnnaBridge 172:65be27845400 12292 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12293 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12294 #define HSEM_C1ICR_ISC19_Pos (19U)
AnnaBridge 172:65be27845400 12295 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12296 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12297 #define HSEM_C1ICR_ISC20_Pos (20U)
AnnaBridge 172:65be27845400 12298 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12299 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12300 #define HSEM_C1ICR_ISC21_Pos (21U)
AnnaBridge 172:65be27845400 12301 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12302 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12303 #define HSEM_C1ICR_ISC22_Pos (22U)
AnnaBridge 172:65be27845400 12304 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12305 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12306 #define HSEM_C1ICR_ISC23_Pos (23U)
AnnaBridge 172:65be27845400 12307 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12308 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12309 #define HSEM_C1ICR_ISC24_Pos (24U)
AnnaBridge 172:65be27845400 12310 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12311 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12312 #define HSEM_C1ICR_ISC25_Pos (25U)
AnnaBridge 172:65be27845400 12313 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12314 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12315 #define HSEM_C1ICR_ISC26_Pos (26U)
AnnaBridge 172:65be27845400 12316 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12317 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12318 #define HSEM_C1ICR_ISC27_Pos (27U)
AnnaBridge 172:65be27845400 12319 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12320 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12321 #define HSEM_C1ICR_ISC28_Pos (28U)
AnnaBridge 172:65be27845400 12322 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12323 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12324 #define HSEM_C1ICR_ISC29_Pos (29U)
AnnaBridge 172:65be27845400 12325 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12326 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12327 #define HSEM_C1ICR_ISC30_Pos (30U)
AnnaBridge 172:65be27845400 12328 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12329 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12330 #define HSEM_C1ICR_ISC31_Pos (31U)
AnnaBridge 172:65be27845400 12331 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12332 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
AnnaBridge 172:65be27845400 12333
AnnaBridge 172:65be27845400 12334 /******************** Bit definition for HSEM_C1ISR register *****************/
AnnaBridge 172:65be27845400 12335 #define HSEM_C1ISR_ISF0_Pos (0U)
AnnaBridge 172:65be27845400 12336 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12337 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12338 #define HSEM_C1ISR_ISF1_Pos (1U)
AnnaBridge 172:65be27845400 12339 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12340 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12341 #define HSEM_C1ISR_ISF2_Pos (2U)
AnnaBridge 172:65be27845400 12342 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12343 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12344 #define HSEM_C1ISR_ISF3_Pos (3U)
AnnaBridge 172:65be27845400 12345 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12346 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12347 #define HSEM_C1ISR_ISF4_Pos (4U)
AnnaBridge 172:65be27845400 12348 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12349 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12350 #define HSEM_C1ISR_ISF5_Pos (5U)
AnnaBridge 172:65be27845400 12351 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12352 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12353 #define HSEM_C1ISR_ISF6_Pos (6U)
AnnaBridge 172:65be27845400 12354 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12355 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12356 #define HSEM_C1ISR_ISF7_Pos (7U)
AnnaBridge 172:65be27845400 12357 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12358 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12359 #define HSEM_C1ISR_ISF8_Pos (8U)
AnnaBridge 172:65be27845400 12360 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12361 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12362 #define HSEM_C1ISR_ISF9_Pos (9U)
AnnaBridge 172:65be27845400 12363 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12364 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12365 #define HSEM_C1ISR_ISF10_Pos (10U)
AnnaBridge 172:65be27845400 12366 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12367 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12368 #define HSEM_C1ISR_ISF11_Pos (11U)
AnnaBridge 172:65be27845400 12369 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12370 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12371 #define HSEM_C1ISR_ISF12_Pos (12U)
AnnaBridge 172:65be27845400 12372 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12373 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12374 #define HSEM_C1ISR_ISF13_Pos (13U)
AnnaBridge 172:65be27845400 12375 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12376 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12377 #define HSEM_C1ISR_ISF14_Pos (14U)
AnnaBridge 172:65be27845400 12378 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12379 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12380 #define HSEM_C1ISR_ISF15_Pos (15U)
AnnaBridge 172:65be27845400 12381 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12382 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12383 #define HSEM_C1ISR_ISF16_Pos (16U)
AnnaBridge 172:65be27845400 12384 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12385 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12386 #define HSEM_C1ISR_ISF17_Pos (17U)
AnnaBridge 172:65be27845400 12387 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12388 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12389 #define HSEM_C1ISR_ISF18_Pos (18U)
AnnaBridge 172:65be27845400 12390 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12391 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12392 #define HSEM_C1ISR_ISF19_Pos (19U)
AnnaBridge 172:65be27845400 12393 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12394 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12395 #define HSEM_C1ISR_ISF20_Pos (20U)
AnnaBridge 172:65be27845400 12396 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12397 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12398 #define HSEM_C1ISR_ISF21_Pos (21U)
AnnaBridge 172:65be27845400 12399 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12400 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12401 #define HSEM_C1ISR_ISF22_Pos (22U)
AnnaBridge 172:65be27845400 12402 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12403 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12404 #define HSEM_C1ISR_ISF23_Pos (23U)
AnnaBridge 172:65be27845400 12405 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12406 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12407 #define HSEM_C1ISR_ISF24_Pos (24U)
AnnaBridge 172:65be27845400 12408 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12409 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12410 #define HSEM_C1ISR_ISF25_Pos (25U)
AnnaBridge 172:65be27845400 12411 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12412 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12413 #define HSEM_C1ISR_ISF26_Pos (26U)
AnnaBridge 172:65be27845400 12414 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12415 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12416 #define HSEM_C1ISR_ISF27_Pos (27U)
AnnaBridge 172:65be27845400 12417 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12418 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12419 #define HSEM_C1ISR_ISF28_Pos (28U)
AnnaBridge 172:65be27845400 12420 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12421 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12422 #define HSEM_C1ISR_ISF29_Pos (29U)
AnnaBridge 172:65be27845400 12423 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12424 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12425 #define HSEM_C1ISR_ISF30_Pos (30U)
AnnaBridge 172:65be27845400 12426 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12427 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12428 #define HSEM_C1ISR_ISF31_Pos (31U)
AnnaBridge 172:65be27845400 12429 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12430 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
AnnaBridge 172:65be27845400 12431
AnnaBridge 172:65be27845400 12432 /******************** Bit definition for HSEM_C1MISR register *****************/
AnnaBridge 172:65be27845400 12433 #define HSEM_C1MISR_MISF0_Pos (0U)
AnnaBridge 172:65be27845400 12434 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12435 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12436 #define HSEM_C1MISR_MISF1_Pos (1U)
AnnaBridge 172:65be27845400 12437 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12438 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12439 #define HSEM_C1MISR_MISF2_Pos (2U)
AnnaBridge 172:65be27845400 12440 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12441 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12442 #define HSEM_C1MISR_MISF3_Pos (3U)
AnnaBridge 172:65be27845400 12443 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12444 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12445 #define HSEM_C1MISR_MISF4_Pos (4U)
AnnaBridge 172:65be27845400 12446 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12447 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12448 #define HSEM_C1MISR_MISF5_Pos (5U)
AnnaBridge 172:65be27845400 12449 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12450 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12451 #define HSEM_C1MISR_MISF6_Pos (6U)
AnnaBridge 172:65be27845400 12452 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12453 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12454 #define HSEM_C1MISR_MISF7_Pos (7U)
AnnaBridge 172:65be27845400 12455 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12456 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12457 #define HSEM_C1MISR_MISF8_Pos (8U)
AnnaBridge 172:65be27845400 12458 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12459 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12460 #define HSEM_C1MISR_MISF9_Pos (9U)
AnnaBridge 172:65be27845400 12461 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12462 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12463 #define HSEM_C1MISR_MISF10_Pos (10U)
AnnaBridge 172:65be27845400 12464 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12465 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12466 #define HSEM_C1MISR_MISF11_Pos (11U)
AnnaBridge 172:65be27845400 12467 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12468 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12469 #define HSEM_C1MISR_MISF12_Pos (12U)
AnnaBridge 172:65be27845400 12470 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12471 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12472 #define HSEM_C1MISR_MISF13_Pos (13U)
AnnaBridge 172:65be27845400 12473 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12474 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12475 #define HSEM_C1MISR_MISF14_Pos (14U)
AnnaBridge 172:65be27845400 12476 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12477 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12478 #define HSEM_C1MISR_MISF15_Pos (15U)
AnnaBridge 172:65be27845400 12479 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12480 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12481 #define HSEM_C1MISR_MISF16_Pos (16U)
AnnaBridge 172:65be27845400 12482 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12483 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12484 #define HSEM_C1MISR_MISF17_Pos (17U)
AnnaBridge 172:65be27845400 12485 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12486 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12487 #define HSEM_C1MISR_MISF18_Pos (18U)
AnnaBridge 172:65be27845400 12488 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12489 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12490 #define HSEM_C1MISR_MISF19_Pos (19U)
AnnaBridge 172:65be27845400 12491 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12492 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12493 #define HSEM_C1MISR_MISF20_Pos (20U)
AnnaBridge 172:65be27845400 12494 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12495 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12496 #define HSEM_C1MISR_MISF21_Pos (21U)
AnnaBridge 172:65be27845400 12497 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12498 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12499 #define HSEM_C1MISR_MISF22_Pos (22U)
AnnaBridge 172:65be27845400 12500 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12501 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12502 #define HSEM_C1MISR_MISF23_Pos (23U)
AnnaBridge 172:65be27845400 12503 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12504 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12505 #define HSEM_C1MISR_MISF24_Pos (24U)
AnnaBridge 172:65be27845400 12506 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12507 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12508 #define HSEM_C1MISR_MISF25_Pos (25U)
AnnaBridge 172:65be27845400 12509 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12510 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12511 #define HSEM_C1MISR_MISF26_Pos (26U)
AnnaBridge 172:65be27845400 12512 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12513 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12514 #define HSEM_C1MISR_MISF27_Pos (27U)
AnnaBridge 172:65be27845400 12515 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 12516 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12517 #define HSEM_C1MISR_MISF28_Pos (28U)
AnnaBridge 172:65be27845400 12518 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 12519 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12520 #define HSEM_C1MISR_MISF29_Pos (29U)
AnnaBridge 172:65be27845400 12521 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 12522 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12523 #define HSEM_C1MISR_MISF30_Pos (30U)
AnnaBridge 172:65be27845400 12524 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 12525 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12526 #define HSEM_C1MISR_MISF31_Pos (31U)
AnnaBridge 172:65be27845400 12527 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12528 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
AnnaBridge 172:65be27845400 12529
AnnaBridge 172:65be27845400 12530 /******************** Bit definition for HSEM_CR register *****************/
AnnaBridge 172:65be27845400 12531 #define HSEM_CR_COREID_Pos (8U)
AnnaBridge 172:65be27845400 12532 #define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 12533 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
AnnaBridge 172:65be27845400 12534 #define HSEM_CR_KEY_Pos (16U)
AnnaBridge 172:65be27845400 12535 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 12536 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
AnnaBridge 172:65be27845400 12537
AnnaBridge 172:65be27845400 12538 /******************** Bit definition for HSEM_KEYR register *****************/
AnnaBridge 172:65be27845400 12539 #define HSEM_KEYR_KEY_Pos (16U)
AnnaBridge 172:65be27845400 12540 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 12541 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
AnnaBridge 172:65be27845400 12542
AnnaBridge 172:65be27845400 12543 /******************************************************************************/
AnnaBridge 172:65be27845400 12544 /* */
AnnaBridge 172:65be27845400 12545 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 172:65be27845400 12546 /* */
AnnaBridge 172:65be27845400 12547 /******************************************************************************/
AnnaBridge 172:65be27845400 12548 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 172:65be27845400 12549 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 172:65be27845400 12550 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12551 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 172:65be27845400 12552 #define I2C_CR1_TXIE_Pos (1U)
AnnaBridge 172:65be27845400 12553 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12554 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 172:65be27845400 12555 #define I2C_CR1_RXIE_Pos (2U)
AnnaBridge 172:65be27845400 12556 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12557 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 172:65be27845400 12558 #define I2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 172:65be27845400 12559 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12560 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 172:65be27845400 12561 #define I2C_CR1_NACKIE_Pos (4U)
AnnaBridge 172:65be27845400 12562 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12563 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 172:65be27845400 12564 #define I2C_CR1_STOPIE_Pos (5U)
AnnaBridge 172:65be27845400 12565 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12566 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 172:65be27845400 12567 #define I2C_CR1_TCIE_Pos (6U)
AnnaBridge 172:65be27845400 12568 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12569 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 172:65be27845400 12570 #define I2C_CR1_ERRIE_Pos (7U)
AnnaBridge 172:65be27845400 12571 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12572 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 172:65be27845400 12573 #define I2C_CR1_DNF_Pos (8U)
AnnaBridge 172:65be27845400 12574 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12575 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
AnnaBridge 172:65be27845400 12576 #define I2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 172:65be27845400 12577 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12578 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 172:65be27845400 12579 #define I2C_CR1_SWRST_Pos (13U)
AnnaBridge 172:65be27845400 12580 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12581 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
AnnaBridge 172:65be27845400 12582 #define I2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 172:65be27845400 12583 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12584 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 172:65be27845400 12585 #define I2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 172:65be27845400 12586 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12587 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 172:65be27845400 12588 #define I2C_CR1_SBC_Pos (16U)
AnnaBridge 172:65be27845400 12589 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12590 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 172:65be27845400 12591 #define I2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 172:65be27845400 12592 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 12593 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 172:65be27845400 12594 #define I2C_CR1_WUPEN_Pos (18U)
AnnaBridge 172:65be27845400 12595 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 12596 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
AnnaBridge 172:65be27845400 12597 #define I2C_CR1_GCEN_Pos (19U)
AnnaBridge 172:65be27845400 12598 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 12599 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 172:65be27845400 12600 #define I2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 172:65be27845400 12601 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 12602 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 172:65be27845400 12603 #define I2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 172:65be27845400 12604 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 12605 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 172:65be27845400 12606 #define I2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 172:65be27845400 12607 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 12608 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 172:65be27845400 12609 #define I2C_CR1_PECEN_Pos (23U)
AnnaBridge 172:65be27845400 12610 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 12611 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 172:65be27845400 12612
AnnaBridge 172:65be27845400 12613 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 172:65be27845400 12614 #define I2C_CR2_SADD_Pos (0U)
AnnaBridge 172:65be27845400 12615 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 12616 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 172:65be27845400 12617 #define I2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 172:65be27845400 12618 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12619 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 172:65be27845400 12620 #define I2C_CR2_ADD10_Pos (11U)
AnnaBridge 172:65be27845400 12621 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12622 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 172:65be27845400 12623 #define I2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 172:65be27845400 12624 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12625 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 172:65be27845400 12626 #define I2C_CR2_START_Pos (13U)
AnnaBridge 172:65be27845400 12627 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12628 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
AnnaBridge 172:65be27845400 12629 #define I2C_CR2_STOP_Pos (14U)
AnnaBridge 172:65be27845400 12630 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12631 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 172:65be27845400 12632 #define I2C_CR2_NACK_Pos (15U)
AnnaBridge 172:65be27845400 12633 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12634 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 172:65be27845400 12635 #define I2C_CR2_NBYTES_Pos (16U)
AnnaBridge 172:65be27845400 12636 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 12637 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 172:65be27845400 12638 #define I2C_CR2_RELOAD_Pos (24U)
AnnaBridge 172:65be27845400 12639 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 12640 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 172:65be27845400 12641 #define I2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 172:65be27845400 12642 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 12643 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 172:65be27845400 12644 #define I2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 172:65be27845400 12645 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 12646 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 172:65be27845400 12647
AnnaBridge 172:65be27845400 12648 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 172:65be27845400 12649 #define I2C_OAR1_OA1_Pos (0U)
AnnaBridge 172:65be27845400 12650 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 12651 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 172:65be27845400 12652 #define I2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 172:65be27845400 12653 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12654 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 172:65be27845400 12655 #define I2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 172:65be27845400 12656 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12657 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 172:65be27845400 12658
AnnaBridge 172:65be27845400 12659 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 172:65be27845400 12660 #define I2C_OAR2_OA2_Pos (1U)
AnnaBridge 172:65be27845400 12661 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 172:65be27845400 12662 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 172:65be27845400 12663 #define I2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 172:65be27845400 12664 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 12665 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 172:65be27845400 12666 #define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
AnnaBridge 172:65be27845400 12667 #define I2C_OAR2_OA2MASK01_Pos (8U)
AnnaBridge 172:65be27845400 12668 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12669 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
AnnaBridge 172:65be27845400 12670 #define I2C_OAR2_OA2MASK02_Pos (9U)
AnnaBridge 172:65be27845400 12671 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12672 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
AnnaBridge 172:65be27845400 12673 #define I2C_OAR2_OA2MASK03_Pos (8U)
AnnaBridge 172:65be27845400 12674 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 12675 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
AnnaBridge 172:65be27845400 12676 #define I2C_OAR2_OA2MASK04_Pos (10U)
AnnaBridge 172:65be27845400 12677 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12678 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
AnnaBridge 172:65be27845400 12679 #define I2C_OAR2_OA2MASK05_Pos (8U)
AnnaBridge 172:65be27845400 12680 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
AnnaBridge 172:65be27845400 12681 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
AnnaBridge 172:65be27845400 12682 #define I2C_OAR2_OA2MASK06_Pos (9U)
AnnaBridge 172:65be27845400 12683 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
AnnaBridge 172:65be27845400 12684 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
AnnaBridge 172:65be27845400 12685 #define I2C_OAR2_OA2MASK07_Pos (8U)
AnnaBridge 172:65be27845400 12686 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 12687 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
AnnaBridge 172:65be27845400 12688 #define I2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 172:65be27845400 12689 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12690 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 172:65be27845400 12691
AnnaBridge 172:65be27845400 12692 /******************* Bit definition for I2C_TIMINGR register *******************/
AnnaBridge 172:65be27845400 12693 #define I2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 172:65be27845400 12694 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12695 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 172:65be27845400 12696 #define I2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 172:65be27845400 12697 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 12698 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 172:65be27845400 12699 #define I2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 172:65be27845400 12700 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 12701 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 172:65be27845400 12702 #define I2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 172:65be27845400 12703 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 12704 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 172:65be27845400 12705 #define I2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 172:65be27845400 12706 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 12707 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 172:65be27845400 12708
AnnaBridge 172:65be27845400 12709 /******************* Bit definition for I2C_TIMEOUTR register *******************/
AnnaBridge 172:65be27845400 12710 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 172:65be27845400 12711 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 12712 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 172:65be27845400 12713 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 172:65be27845400 12714 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12715 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 172:65be27845400 12716 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 172:65be27845400 12717 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12718 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 172:65be27845400 12719 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 172:65be27845400 12720 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 12721 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
AnnaBridge 172:65be27845400 12722 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 172:65be27845400 12723 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 12724 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 172:65be27845400 12725
AnnaBridge 172:65be27845400 12726 /****************** Bit definition for I2C_ISR register *********************/
AnnaBridge 172:65be27845400 12727 #define I2C_ISR_TXE_Pos (0U)
AnnaBridge 172:65be27845400 12728 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12729 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 172:65be27845400 12730 #define I2C_ISR_TXIS_Pos (1U)
AnnaBridge 172:65be27845400 12731 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12732 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 172:65be27845400 12733 #define I2C_ISR_RXNE_Pos (2U)
AnnaBridge 172:65be27845400 12734 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12735 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 172:65be27845400 12736 #define I2C_ISR_ADDR_Pos (3U)
AnnaBridge 172:65be27845400 12737 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12738 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
AnnaBridge 172:65be27845400 12739 #define I2C_ISR_NACKF_Pos (4U)
AnnaBridge 172:65be27845400 12740 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12741 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 172:65be27845400 12742 #define I2C_ISR_STOPF_Pos (5U)
AnnaBridge 172:65be27845400 12743 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12744 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 172:65be27845400 12745 #define I2C_ISR_TC_Pos (6U)
AnnaBridge 172:65be27845400 12746 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12747 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 172:65be27845400 12748 #define I2C_ISR_TCR_Pos (7U)
AnnaBridge 172:65be27845400 12749 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12750 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 172:65be27845400 12751 #define I2C_ISR_BERR_Pos (8U)
AnnaBridge 172:65be27845400 12752 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12753 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 172:65be27845400 12754 #define I2C_ISR_ARLO_Pos (9U)
AnnaBridge 172:65be27845400 12755 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12756 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 172:65be27845400 12757 #define I2C_ISR_OVR_Pos (10U)
AnnaBridge 172:65be27845400 12758 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12759 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 172:65be27845400 12760 #define I2C_ISR_PECERR_Pos (11U)
AnnaBridge 172:65be27845400 12761 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12762 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 172:65be27845400 12763 #define I2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 172:65be27845400 12764 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12765 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 172:65be27845400 12766 #define I2C_ISR_ALERT_Pos (13U)
AnnaBridge 172:65be27845400 12767 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12768 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 172:65be27845400 12769 #define I2C_ISR_BUSY_Pos (15U)
AnnaBridge 172:65be27845400 12770 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12771 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 172:65be27845400 12772 #define I2C_ISR_DIR_Pos (16U)
AnnaBridge 172:65be27845400 12773 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 12774 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 172:65be27845400 12775 #define I2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 172:65be27845400 12776 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 172:65be27845400 12777 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 172:65be27845400 12778
AnnaBridge 172:65be27845400 12779 /****************** Bit definition for I2C_ICR register *********************/
AnnaBridge 172:65be27845400 12780 #define I2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 172:65be27845400 12781 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12782 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 172:65be27845400 12783 #define I2C_ICR_NACKCF_Pos (4U)
AnnaBridge 172:65be27845400 12784 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12785 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 172:65be27845400 12786 #define I2C_ICR_STOPCF_Pos (5U)
AnnaBridge 172:65be27845400 12787 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12788 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 172:65be27845400 12789 #define I2C_ICR_BERRCF_Pos (8U)
AnnaBridge 172:65be27845400 12790 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12791 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 172:65be27845400 12792 #define I2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 172:65be27845400 12793 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12794 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 172:65be27845400 12795 #define I2C_ICR_OVRCF_Pos (10U)
AnnaBridge 172:65be27845400 12796 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12797 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 172:65be27845400 12798 #define I2C_ICR_PECCF_Pos (11U)
AnnaBridge 172:65be27845400 12799 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12800 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 172:65be27845400 12801 #define I2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 172:65be27845400 12802 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12803 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 172:65be27845400 12804 #define I2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 172:65be27845400 12805 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12806 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 172:65be27845400 12807
AnnaBridge 172:65be27845400 12808 /****************** Bit definition for I2C_PECR register *********************/
AnnaBridge 172:65be27845400 12809 #define I2C_PECR_PEC_Pos (0U)
AnnaBridge 172:65be27845400 12810 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12811 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 172:65be27845400 12812
AnnaBridge 172:65be27845400 12813 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 172:65be27845400 12814 #define I2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 172:65be27845400 12815 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12816 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 172:65be27845400 12817
AnnaBridge 172:65be27845400 12818 /****************** Bit definition for I2C_TXDR register *********************/
AnnaBridge 172:65be27845400 12819 #define I2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 172:65be27845400 12820 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 12821 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 172:65be27845400 12822
AnnaBridge 172:65be27845400 12823 /******************************************************************************/
AnnaBridge 172:65be27845400 12824 /* */
AnnaBridge 172:65be27845400 12825 /* Independent WATCHDOG */
AnnaBridge 172:65be27845400 12826 /* */
AnnaBridge 172:65be27845400 12827 /******************************************************************************/
AnnaBridge 172:65be27845400 12828 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 172:65be27845400 12829 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 172:65be27845400 12830 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 12831 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
AnnaBridge 172:65be27845400 12832
AnnaBridge 172:65be27845400 12833 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 172:65be27845400 12834 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 172:65be27845400 12835 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 12836 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 172:65be27845400 12837 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12838 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12839 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12840
AnnaBridge 172:65be27845400 12841 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 172:65be27845400 12842 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 172:65be27845400 12843 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 12844 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
AnnaBridge 172:65be27845400 12845
AnnaBridge 172:65be27845400 12846 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 172:65be27845400 12847 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 172:65be27845400 12848 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12849 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
AnnaBridge 172:65be27845400 12850 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 172:65be27845400 12851 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12852 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
AnnaBridge 172:65be27845400 12853 #define IWDG_SR_WVU_Pos (2U)
AnnaBridge 172:65be27845400 12854 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12855 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
AnnaBridge 172:65be27845400 12856
AnnaBridge 172:65be27845400 12857 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 172:65be27845400 12858 #define IWDG_WINR_WIN_Pos (0U)
AnnaBridge 172:65be27845400 12859 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 12860 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
AnnaBridge 172:65be27845400 12861
AnnaBridge 172:65be27845400 12862 /******************************************************************************/
AnnaBridge 172:65be27845400 12863 /* */
AnnaBridge 172:65be27845400 12864 /* JPEG Encoder/Decoder */
AnnaBridge 172:65be27845400 12865 /* */
AnnaBridge 172:65be27845400 12866 /******************************************************************************/
AnnaBridge 172:65be27845400 12867 /******************** Bit definition for CONFR0 register ********************/
AnnaBridge 172:65be27845400 12868 #define JPEG_CONFR0_START_Pos (0U)
AnnaBridge 172:65be27845400 12869 #define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12870 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
AnnaBridge 172:65be27845400 12871
AnnaBridge 172:65be27845400 12872 /******************** Bit definition for CONFR1 register ********************/
AnnaBridge 172:65be27845400 12873 #define JPEG_CONFR1_NF_Pos (0U)
AnnaBridge 172:65be27845400 12874 #define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 12875 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
AnnaBridge 172:65be27845400 12876 #define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12877 #define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12878 #define JPEG_CONFR1_DE_Pos (3U)
AnnaBridge 172:65be27845400 12879 #define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12880 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
AnnaBridge 172:65be27845400 12881 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
AnnaBridge 172:65be27845400 12882 #define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 12883 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
AnnaBridge 172:65be27845400 12884 #define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12885 #define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12886 #define JPEG_CONFR1_NS_Pos (6U)
AnnaBridge 172:65be27845400 12887 #define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 12888 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
AnnaBridge 172:65be27845400 12889 #define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12890 #define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12891 #define JPEG_CONFR1_HDR_Pos (8U)
AnnaBridge 172:65be27845400 12892 #define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12893 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
AnnaBridge 172:65be27845400 12894 #define JPEG_CONFR1_YSIZE_Pos (16U)
AnnaBridge 172:65be27845400 12895 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 12896 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
AnnaBridge 172:65be27845400 12897
AnnaBridge 172:65be27845400 12898 /******************** Bit definition for CONFR2 register ********************/
AnnaBridge 172:65be27845400 12899 #define JPEG_CONFR2_NMCU_Pos (0U)
AnnaBridge 172:65be27845400 12900 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
AnnaBridge 172:65be27845400 12901 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
AnnaBridge 172:65be27845400 12902
AnnaBridge 172:65be27845400 12903 /******************** Bit definition for CONFR3 register ********************/
AnnaBridge 172:65be27845400 12904 #define JPEG_CONFR3_XSIZE_Pos (16U)
AnnaBridge 172:65be27845400 12905 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 12906 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
AnnaBridge 172:65be27845400 12907
AnnaBridge 172:65be27845400 12908 /******************** Bit definition for CONFR4 register ********************/
AnnaBridge 172:65be27845400 12909 #define JPEG_CONFR4_HD_Pos (0U)
AnnaBridge 172:65be27845400 12910 #define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12911 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 172:65be27845400 12912 #define JPEG_CONFR4_HA_Pos (1U)
AnnaBridge 172:65be27845400 12913 #define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12914 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 172:65be27845400 12915 #define JPEG_CONFR4_QT_Pos (2U)
AnnaBridge 172:65be27845400 12916 #define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 12917 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
AnnaBridge 172:65be27845400 12918 #define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12919 #define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12920 #define JPEG_CONFR4_NB_Pos (4U)
AnnaBridge 172:65be27845400 12921 #define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 12922 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 172:65be27845400 12923 #define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12924 #define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12925 #define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12926 #define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12927 #define JPEG_CONFR4_VSF_Pos (8U)
AnnaBridge 172:65be27845400 12928 #define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12929 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
AnnaBridge 172:65be27845400 12930 #define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12931 #define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12932 #define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12933 #define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12934 #define JPEG_CONFR4_HSF_Pos (12U)
AnnaBridge 172:65be27845400 12935 #define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 12936 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
AnnaBridge 172:65be27845400 12937 #define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12938 #define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12939 #define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12940 #define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12941
AnnaBridge 172:65be27845400 12942 /******************** Bit definition for CONFR5 register ********************/
AnnaBridge 172:65be27845400 12943 #define JPEG_CONFR5_HD_Pos (0U)
AnnaBridge 172:65be27845400 12944 #define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12945 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 172:65be27845400 12946 #define JPEG_CONFR5_HA_Pos (1U)
AnnaBridge 172:65be27845400 12947 #define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12948 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 172:65be27845400 12949 #define JPEG_CONFR5_QT_Pos (2U)
AnnaBridge 172:65be27845400 12950 #define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 12951 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
AnnaBridge 172:65be27845400 12952 #define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12953 #define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12954 #define JPEG_CONFR5_NB_Pos (4U)
AnnaBridge 172:65be27845400 12955 #define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 12956 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 172:65be27845400 12957 #define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12958 #define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12959 #define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12960 #define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12961 #define JPEG_CONFR5_VSF_Pos (8U)
AnnaBridge 172:65be27845400 12962 #define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12963 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
AnnaBridge 172:65be27845400 12964 #define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12965 #define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 12966 #define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 12967 #define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 12968 #define JPEG_CONFR5_HSF_Pos (12U)
AnnaBridge 172:65be27845400 12969 #define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 12970 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
AnnaBridge 172:65be27845400 12971 #define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 12972 #define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 12973 #define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 12974 #define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 12975
AnnaBridge 172:65be27845400 12976 /******************** Bit definition for CONFR6 register ********************/
AnnaBridge 172:65be27845400 12977 #define JPEG_CONFR6_HD_Pos (0U)
AnnaBridge 172:65be27845400 12978 #define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 12979 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 172:65be27845400 12980 #define JPEG_CONFR6_HA_Pos (1U)
AnnaBridge 172:65be27845400 12981 #define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 12982 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 172:65be27845400 12983 #define JPEG_CONFR6_QT_Pos (2U)
AnnaBridge 172:65be27845400 12984 #define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 12985 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
AnnaBridge 172:65be27845400 12986 #define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 12987 #define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 12988 #define JPEG_CONFR6_NB_Pos (4U)
AnnaBridge 172:65be27845400 12989 #define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 12990 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 172:65be27845400 12991 #define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 12992 #define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 12993 #define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 12994 #define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 12995 #define JPEG_CONFR6_VSF_Pos (8U)
AnnaBridge 172:65be27845400 12996 #define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 12997 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
AnnaBridge 172:65be27845400 12998 #define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 12999 #define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13000 #define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13001 #define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13002 #define JPEG_CONFR6_HSF_Pos (12U)
AnnaBridge 172:65be27845400 13003 #define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 13004 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
AnnaBridge 172:65be27845400 13005 #define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13006 #define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13007 #define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13008 #define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13009
AnnaBridge 172:65be27845400 13010 /******************** Bit definition for CONFR7 register ********************/
AnnaBridge 172:65be27845400 13011 #define JPEG_CONFR7_HD_Pos (0U)
AnnaBridge 172:65be27845400 13012 #define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13013 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
AnnaBridge 172:65be27845400 13014 #define JPEG_CONFR7_HA_Pos (1U)
AnnaBridge 172:65be27845400 13015 #define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13016 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
AnnaBridge 172:65be27845400 13017 #define JPEG_CONFR7_QT_Pos (2U)
AnnaBridge 172:65be27845400 13018 #define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 13019 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
AnnaBridge 172:65be27845400 13020 #define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13021 #define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13022 #define JPEG_CONFR7_NB_Pos (4U)
AnnaBridge 172:65be27845400 13023 #define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 13024 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
AnnaBridge 172:65be27845400 13025 #define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13026 #define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13027 #define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13028 #define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13029 #define JPEG_CONFR7_VSF_Pos (8U)
AnnaBridge 172:65be27845400 13030 #define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 13031 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
AnnaBridge 172:65be27845400 13032 #define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13033 #define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13034 #define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13035 #define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13036 #define JPEG_CONFR7_HSF_Pos (12U)
AnnaBridge 172:65be27845400 13037 #define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 13038 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
AnnaBridge 172:65be27845400 13039 #define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13040 #define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13041 #define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13042 #define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13043
AnnaBridge 172:65be27845400 13044 /******************** Bit definition for CR register ********************/
AnnaBridge 172:65be27845400 13045 #define JPEG_CR_JCEN_Pos (0U)
AnnaBridge 172:65be27845400 13046 #define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13047 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
AnnaBridge 172:65be27845400 13048 #define JPEG_CR_IFTIE_Pos (1U)
AnnaBridge 172:65be27845400 13049 #define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13050 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
AnnaBridge 172:65be27845400 13051 #define JPEG_CR_IFNFIE_Pos (2U)
AnnaBridge 172:65be27845400 13052 #define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13053 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
AnnaBridge 172:65be27845400 13054 #define JPEG_CR_OFTIE_Pos (3U)
AnnaBridge 172:65be27845400 13055 #define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13056 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
AnnaBridge 172:65be27845400 13057 #define JPEG_CR_OFNEIE_Pos (4U)
AnnaBridge 172:65be27845400 13058 #define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13059 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
AnnaBridge 172:65be27845400 13060 #define JPEG_CR_EOCIE_Pos (5U)
AnnaBridge 172:65be27845400 13061 #define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13062 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
AnnaBridge 172:65be27845400 13063 #define JPEG_CR_HPDIE_Pos (6U)
AnnaBridge 172:65be27845400 13064 #define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13065 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
AnnaBridge 172:65be27845400 13066 #define JPEG_CR_IFF_Pos (13U)
AnnaBridge 172:65be27845400 13067 #define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13068 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
AnnaBridge 172:65be27845400 13069 #define JPEG_CR_OFF_Pos (14U)
AnnaBridge 172:65be27845400 13070 #define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13071 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
AnnaBridge 172:65be27845400 13072
AnnaBridge 172:65be27845400 13073 /******************** Bit definition for SR register ********************/
AnnaBridge 172:65be27845400 13074 #define JPEG_SR_IFTF_Pos (1U)
AnnaBridge 172:65be27845400 13075 #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13076 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
AnnaBridge 172:65be27845400 13077 #define JPEG_SR_IFNFF_Pos (2U)
AnnaBridge 172:65be27845400 13078 #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13079 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
AnnaBridge 172:65be27845400 13080 #define JPEG_SR_OFTF_Pos (3U)
AnnaBridge 172:65be27845400 13081 #define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13082 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
AnnaBridge 172:65be27845400 13083 #define JPEG_SR_OFNEF_Pos (4U)
AnnaBridge 172:65be27845400 13084 #define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13085 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
AnnaBridge 172:65be27845400 13086 #define JPEG_SR_EOCF_Pos (5U)
AnnaBridge 172:65be27845400 13087 #define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13088 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
AnnaBridge 172:65be27845400 13089 #define JPEG_SR_HPDF_Pos (6U)
AnnaBridge 172:65be27845400 13090 #define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13091 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
AnnaBridge 172:65be27845400 13092 #define JPEG_SR_COF_Pos (7U)
AnnaBridge 172:65be27845400 13093 #define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13094 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
AnnaBridge 172:65be27845400 13095
AnnaBridge 172:65be27845400 13096 /******************** Bit definition for CFR register ********************/
AnnaBridge 172:65be27845400 13097 #define JPEG_CFR_CEOCF_Pos (4U)
AnnaBridge 172:65be27845400 13098 #define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13099 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
AnnaBridge 172:65be27845400 13100 #define JPEG_CFR_CHPDF_Pos (5U)
AnnaBridge 172:65be27845400 13101 #define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13102 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
AnnaBridge 172:65be27845400 13103
AnnaBridge 172:65be27845400 13104 /******************** Bit definition for DIR register ********************/
AnnaBridge 172:65be27845400 13105 #define JPEG_DIR_DATAIN_Pos (0U)
AnnaBridge 172:65be27845400 13106 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13107 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
AnnaBridge 172:65be27845400 13108
AnnaBridge 172:65be27845400 13109 /******************** Bit definition for DOR register ********************/
AnnaBridge 172:65be27845400 13110 #define JPEG_DOR_DATAOUT_Pos (0U)
AnnaBridge 172:65be27845400 13111 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13112 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
AnnaBridge 172:65be27845400 13113
AnnaBridge 172:65be27845400 13114 /******************************************************************************/
AnnaBridge 172:65be27845400 13115 /* */
AnnaBridge 172:65be27845400 13116 /* LCD-TFT Display Controller (LTDC) */
AnnaBridge 172:65be27845400 13117 /* */
AnnaBridge 172:65be27845400 13118 /******************************************************************************/
AnnaBridge 172:65be27845400 13119
AnnaBridge 172:65be27845400 13120 /******************** Bit definition for LTDC_SSCR register *****************/
AnnaBridge 172:65be27845400 13121
AnnaBridge 172:65be27845400 13122 #define LTDC_SSCR_VSH_Pos (0U)
AnnaBridge 172:65be27845400 13123 #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 13124 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
AnnaBridge 172:65be27845400 13125 #define LTDC_SSCR_HSW_Pos (16U)
AnnaBridge 172:65be27845400 13126 #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 13127 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
AnnaBridge 172:65be27845400 13128
AnnaBridge 172:65be27845400 13129 /******************** Bit definition for LTDC_BPCR register *****************/
AnnaBridge 172:65be27845400 13130
AnnaBridge 172:65be27845400 13131 #define LTDC_BPCR_AVBP_Pos (0U)
AnnaBridge 172:65be27845400 13132 #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 13133 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
AnnaBridge 172:65be27845400 13134 #define LTDC_BPCR_AHBP_Pos (16U)
AnnaBridge 172:65be27845400 13135 #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 13136 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
AnnaBridge 172:65be27845400 13137
AnnaBridge 172:65be27845400 13138 /******************** Bit definition for LTDC_AWCR register *****************/
AnnaBridge 172:65be27845400 13139
AnnaBridge 172:65be27845400 13140 #define LTDC_AWCR_AAH_Pos (0U)
AnnaBridge 172:65be27845400 13141 #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 13142 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
AnnaBridge 172:65be27845400 13143 #define LTDC_AWCR_AAW_Pos (16U)
AnnaBridge 172:65be27845400 13144 #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 13145 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
AnnaBridge 172:65be27845400 13146
AnnaBridge 172:65be27845400 13147 /******************** Bit definition for LTDC_TWCR register *****************/
AnnaBridge 172:65be27845400 13148
AnnaBridge 172:65be27845400 13149 #define LTDC_TWCR_TOTALH_Pos (0U)
AnnaBridge 172:65be27845400 13150 #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 13151 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
AnnaBridge 172:65be27845400 13152 #define LTDC_TWCR_TOTALW_Pos (16U)
AnnaBridge 172:65be27845400 13153 #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 13154 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
AnnaBridge 172:65be27845400 13155
AnnaBridge 172:65be27845400 13156 /******************** Bit definition for LTDC_GCR register ******************/
AnnaBridge 172:65be27845400 13157
AnnaBridge 172:65be27845400 13158 #define LTDC_GCR_LTDCEN_Pos (0U)
AnnaBridge 172:65be27845400 13159 #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13160 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
AnnaBridge 172:65be27845400 13161 #define LTDC_GCR_DBW_Pos (4U)
AnnaBridge 172:65be27845400 13162 #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 13163 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
AnnaBridge 172:65be27845400 13164 #define LTDC_GCR_DGW_Pos (8U)
AnnaBridge 172:65be27845400 13165 #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 13166 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
AnnaBridge 172:65be27845400 13167 #define LTDC_GCR_DRW_Pos (12U)
AnnaBridge 172:65be27845400 13168 #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 13169 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
AnnaBridge 172:65be27845400 13170 #define LTDC_GCR_DEN_Pos (16U)
AnnaBridge 172:65be27845400 13171 #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13172 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
AnnaBridge 172:65be27845400 13173 #define LTDC_GCR_PCPOL_Pos (28U)
AnnaBridge 172:65be27845400 13174 #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 13175 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
AnnaBridge 172:65be27845400 13176 #define LTDC_GCR_DEPOL_Pos (29U)
AnnaBridge 172:65be27845400 13177 #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 13178 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
AnnaBridge 172:65be27845400 13179 #define LTDC_GCR_VSPOL_Pos (30U)
AnnaBridge 172:65be27845400 13180 #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 13181 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
AnnaBridge 172:65be27845400 13182 #define LTDC_GCR_HSPOL_Pos (31U)
AnnaBridge 172:65be27845400 13183 #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 13184 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
AnnaBridge 172:65be27845400 13185
AnnaBridge 172:65be27845400 13186
AnnaBridge 172:65be27845400 13187 /******************** Bit definition for LTDC_SRCR register *****************/
AnnaBridge 172:65be27845400 13188
AnnaBridge 172:65be27845400 13189 #define LTDC_SRCR_IMR_Pos (0U)
AnnaBridge 172:65be27845400 13190 #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13191 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
AnnaBridge 172:65be27845400 13192 #define LTDC_SRCR_VBR_Pos (1U)
AnnaBridge 172:65be27845400 13193 #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13194 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
AnnaBridge 172:65be27845400 13195
AnnaBridge 172:65be27845400 13196 /******************** Bit definition for LTDC_BCCR register *****************/
AnnaBridge 172:65be27845400 13197
AnnaBridge 172:65be27845400 13198 #define LTDC_BCCR_BCBLUE_Pos (0U)
AnnaBridge 172:65be27845400 13199 #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 13200 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
AnnaBridge 172:65be27845400 13201 #define LTDC_BCCR_BCGREEN_Pos (8U)
AnnaBridge 172:65be27845400 13202 #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 13203 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
AnnaBridge 172:65be27845400 13204 #define LTDC_BCCR_BCRED_Pos (16U)
AnnaBridge 172:65be27845400 13205 #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 13206 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
AnnaBridge 172:65be27845400 13207
AnnaBridge 172:65be27845400 13208 /******************** Bit definition for LTDC_IER register ******************/
AnnaBridge 172:65be27845400 13209
AnnaBridge 172:65be27845400 13210 #define LTDC_IER_LIE_Pos (0U)
AnnaBridge 172:65be27845400 13211 #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13212 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
AnnaBridge 172:65be27845400 13213 #define LTDC_IER_FUIE_Pos (1U)
AnnaBridge 172:65be27845400 13214 #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13215 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
AnnaBridge 172:65be27845400 13216 #define LTDC_IER_TERRIE_Pos (2U)
AnnaBridge 172:65be27845400 13217 #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13218 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 172:65be27845400 13219 #define LTDC_IER_RRIE_Pos (3U)
AnnaBridge 172:65be27845400 13220 #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13221 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
AnnaBridge 172:65be27845400 13222
AnnaBridge 172:65be27845400 13223 /******************** Bit definition for LTDC_ISR register ******************/
AnnaBridge 172:65be27845400 13224
AnnaBridge 172:65be27845400 13225 #define LTDC_ISR_LIF_Pos (0U)
AnnaBridge 172:65be27845400 13226 #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13227 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
AnnaBridge 172:65be27845400 13228 #define LTDC_ISR_FUIF_Pos (1U)
AnnaBridge 172:65be27845400 13229 #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13230 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
AnnaBridge 172:65be27845400 13231 #define LTDC_ISR_TERRIF_Pos (2U)
AnnaBridge 172:65be27845400 13232 #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13233 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 13234 #define LTDC_ISR_RRIF_Pos (3U)
AnnaBridge 172:65be27845400 13235 #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13236 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
AnnaBridge 172:65be27845400 13237
AnnaBridge 172:65be27845400 13238 /******************** Bit definition for LTDC_ICR register ******************/
AnnaBridge 172:65be27845400 13239
AnnaBridge 172:65be27845400 13240 #define LTDC_ICR_CLIF_Pos (0U)
AnnaBridge 172:65be27845400 13241 #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13242 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
AnnaBridge 172:65be27845400 13243 #define LTDC_ICR_CFUIF_Pos (1U)
AnnaBridge 172:65be27845400 13244 #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13245 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
AnnaBridge 172:65be27845400 13246 #define LTDC_ICR_CTERRIF_Pos (2U)
AnnaBridge 172:65be27845400 13247 #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13248 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
AnnaBridge 172:65be27845400 13249 #define LTDC_ICR_CRRIF_Pos (3U)
AnnaBridge 172:65be27845400 13250 #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13251 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
AnnaBridge 172:65be27845400 13252
AnnaBridge 172:65be27845400 13253 /******************** Bit definition for LTDC_LIPCR register ****************/
AnnaBridge 172:65be27845400 13254
AnnaBridge 172:65be27845400 13255 #define LTDC_LIPCR_LIPOS_Pos (0U)
AnnaBridge 172:65be27845400 13256 #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 13257 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
AnnaBridge 172:65be27845400 13258
AnnaBridge 172:65be27845400 13259 /******************** Bit definition for LTDC_CPSR register *****************/
AnnaBridge 172:65be27845400 13260
AnnaBridge 172:65be27845400 13261 #define LTDC_CPSR_CYPOS_Pos (0U)
AnnaBridge 172:65be27845400 13262 #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 13263 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
AnnaBridge 172:65be27845400 13264 #define LTDC_CPSR_CXPOS_Pos (16U)
AnnaBridge 172:65be27845400 13265 #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 13266 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
AnnaBridge 172:65be27845400 13267
AnnaBridge 172:65be27845400 13268 /******************** Bit definition for LTDC_CDSR register *****************/
AnnaBridge 172:65be27845400 13269
AnnaBridge 172:65be27845400 13270 #define LTDC_CDSR_VDES_Pos (0U)
AnnaBridge 172:65be27845400 13271 #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13272 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
AnnaBridge 172:65be27845400 13273 #define LTDC_CDSR_HDES_Pos (1U)
AnnaBridge 172:65be27845400 13274 #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13275 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
AnnaBridge 172:65be27845400 13276 #define LTDC_CDSR_VSYNCS_Pos (2U)
AnnaBridge 172:65be27845400 13277 #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13278 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
AnnaBridge 172:65be27845400 13279 #define LTDC_CDSR_HSYNCS_Pos (3U)
AnnaBridge 172:65be27845400 13280 #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13281 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
AnnaBridge 172:65be27845400 13282
AnnaBridge 172:65be27845400 13283 /******************** Bit definition for LTDC_LxCR register *****************/
AnnaBridge 172:65be27845400 13284
AnnaBridge 172:65be27845400 13285 #define LTDC_LxCR_LEN_Pos (0U)
AnnaBridge 172:65be27845400 13286 #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13287 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
AnnaBridge 172:65be27845400 13288 #define LTDC_LxCR_COLKEN_Pos (1U)
AnnaBridge 172:65be27845400 13289 #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13290 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
AnnaBridge 172:65be27845400 13291 #define LTDC_LxCR_CLUTEN_Pos (4U)
AnnaBridge 172:65be27845400 13292 #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13293 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
AnnaBridge 172:65be27845400 13294
AnnaBridge 172:65be27845400 13295 /******************** Bit definition for LTDC_LxWHPCR register **************/
AnnaBridge 172:65be27845400 13296
AnnaBridge 172:65be27845400 13297 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
AnnaBridge 172:65be27845400 13298 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 13299 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
AnnaBridge 172:65be27845400 13300 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
AnnaBridge 172:65be27845400 13301 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 13302 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
AnnaBridge 172:65be27845400 13303
AnnaBridge 172:65be27845400 13304 /******************** Bit definition for LTDC_LxWVPCR register **************/
AnnaBridge 172:65be27845400 13305
AnnaBridge 172:65be27845400 13306 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
AnnaBridge 172:65be27845400 13307 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 13308 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
AnnaBridge 172:65be27845400 13309 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
AnnaBridge 172:65be27845400 13310 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 13311 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
AnnaBridge 172:65be27845400 13312
AnnaBridge 172:65be27845400 13313 /******************** Bit definition for LTDC_LxCKCR register ***************/
AnnaBridge 172:65be27845400 13314
AnnaBridge 172:65be27845400 13315 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
AnnaBridge 172:65be27845400 13316 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 13317 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
AnnaBridge 172:65be27845400 13318 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
AnnaBridge 172:65be27845400 13319 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 13320 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
AnnaBridge 172:65be27845400 13321 #define LTDC_LxCKCR_CKRED_Pos (16U)
AnnaBridge 172:65be27845400 13322 #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 13323 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
AnnaBridge 172:65be27845400 13324
AnnaBridge 172:65be27845400 13325 /******************** Bit definition for LTDC_LxPFCR register ***************/
AnnaBridge 172:65be27845400 13326
AnnaBridge 172:65be27845400 13327 #define LTDC_LxPFCR_PF_Pos (0U)
AnnaBridge 172:65be27845400 13328 #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 13329 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
AnnaBridge 172:65be27845400 13330
AnnaBridge 172:65be27845400 13331 /******************** Bit definition for LTDC_LxCACR register ***************/
AnnaBridge 172:65be27845400 13332
AnnaBridge 172:65be27845400 13333 #define LTDC_LxCACR_CONSTA_Pos (0U)
AnnaBridge 172:65be27845400 13334 #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 13335 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
AnnaBridge 172:65be27845400 13336
AnnaBridge 172:65be27845400 13337 /******************** Bit definition for LTDC_LxDCCR register ***************/
AnnaBridge 172:65be27845400 13338
AnnaBridge 172:65be27845400 13339 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
AnnaBridge 172:65be27845400 13340 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 13341 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
AnnaBridge 172:65be27845400 13342 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
AnnaBridge 172:65be27845400 13343 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 13344 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
AnnaBridge 172:65be27845400 13345 #define LTDC_LxDCCR_DCRED_Pos (16U)
AnnaBridge 172:65be27845400 13346 #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 13347 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
AnnaBridge 172:65be27845400 13348 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
AnnaBridge 172:65be27845400 13349 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 13350 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
AnnaBridge 172:65be27845400 13351
AnnaBridge 172:65be27845400 13352 /******************** Bit definition for LTDC_LxBFCR register ***************/
AnnaBridge 172:65be27845400 13353
AnnaBridge 172:65be27845400 13354 #define LTDC_LxBFCR_BF2_Pos (0U)
AnnaBridge 172:65be27845400 13355 #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 13356 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
AnnaBridge 172:65be27845400 13357 #define LTDC_LxBFCR_BF1_Pos (8U)
AnnaBridge 172:65be27845400 13358 #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 13359 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
AnnaBridge 172:65be27845400 13360
AnnaBridge 172:65be27845400 13361 /******************** Bit definition for LTDC_LxCFBAR register **************/
AnnaBridge 172:65be27845400 13362
AnnaBridge 172:65be27845400 13363 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
AnnaBridge 172:65be27845400 13364 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13365 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
AnnaBridge 172:65be27845400 13366
AnnaBridge 172:65be27845400 13367 /******************** Bit definition for LTDC_LxCFBLR register **************/
AnnaBridge 172:65be27845400 13368
AnnaBridge 172:65be27845400 13369 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
AnnaBridge 172:65be27845400 13370 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
AnnaBridge 172:65be27845400 13371 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
AnnaBridge 172:65be27845400 13372 #define LTDC_LxCFBLR_CFBP_Pos (16U)
AnnaBridge 172:65be27845400 13373 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
AnnaBridge 172:65be27845400 13374 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
AnnaBridge 172:65be27845400 13375
AnnaBridge 172:65be27845400 13376 /******************** Bit definition for LTDC_LxCFBLNR register *************/
AnnaBridge 172:65be27845400 13377
AnnaBridge 172:65be27845400 13378 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
AnnaBridge 172:65be27845400 13379 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 13380 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
AnnaBridge 172:65be27845400 13381
AnnaBridge 172:65be27845400 13382 /******************** Bit definition for LTDC_LxCLUTWR register *************/
AnnaBridge 172:65be27845400 13383
AnnaBridge 172:65be27845400 13384 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
AnnaBridge 172:65be27845400 13385 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 13386 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
AnnaBridge 172:65be27845400 13387 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
AnnaBridge 172:65be27845400 13388 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 13389 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
AnnaBridge 172:65be27845400 13390 #define LTDC_LxCLUTWR_RED_Pos (16U)
AnnaBridge 172:65be27845400 13391 #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 13392 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
AnnaBridge 172:65be27845400 13393 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
AnnaBridge 172:65be27845400 13394 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 13395 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
AnnaBridge 172:65be27845400 13396
AnnaBridge 172:65be27845400 13397 /******************************************************************************/
AnnaBridge 172:65be27845400 13398 /* */
AnnaBridge 172:65be27845400 13399 /* MDMA */
AnnaBridge 172:65be27845400 13400 /* */
AnnaBridge 172:65be27845400 13401 /******************************************************************************/
AnnaBridge 172:65be27845400 13402 /******************** Bit definition for MDMA_GISR0 register ****************/
AnnaBridge 172:65be27845400 13403 #define MDMA_GISR0_GIF0_Pos (0U)
AnnaBridge 172:65be27845400 13404 #define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13405 #define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
AnnaBridge 172:65be27845400 13406 #define MDMA_GISR0_GIF1_Pos (1U)
AnnaBridge 172:65be27845400 13407 #define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13408 #define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
AnnaBridge 172:65be27845400 13409 #define MDMA_GISR0_GIF2_Pos (2U)
AnnaBridge 172:65be27845400 13410 #define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13411 #define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
AnnaBridge 172:65be27845400 13412 #define MDMA_GISR0_GIF3_Pos (3U)
AnnaBridge 172:65be27845400 13413 #define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13414 #define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
AnnaBridge 172:65be27845400 13415 #define MDMA_GISR0_GIF4_Pos (4U)
AnnaBridge 172:65be27845400 13416 #define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13417 #define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
AnnaBridge 172:65be27845400 13418 #define MDMA_GISR0_GIF5_Pos (5U)
AnnaBridge 172:65be27845400 13419 #define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13420 #define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
AnnaBridge 172:65be27845400 13421 #define MDMA_GISR0_GIF6_Pos (6U)
AnnaBridge 172:65be27845400 13422 #define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13423 #define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
AnnaBridge 172:65be27845400 13424 #define MDMA_GISR0_GIF7_Pos (7U)
AnnaBridge 172:65be27845400 13425 #define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13426 #define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
AnnaBridge 172:65be27845400 13427 #define MDMA_GISR0_GIF8_Pos (8U)
AnnaBridge 172:65be27845400 13428 #define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13429 #define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
AnnaBridge 172:65be27845400 13430 #define MDMA_GISR0_GIF9_Pos (9U)
AnnaBridge 172:65be27845400 13431 #define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13432 #define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
AnnaBridge 172:65be27845400 13433 #define MDMA_GISR0_GIF10_Pos (10U)
AnnaBridge 172:65be27845400 13434 #define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13435 #define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
AnnaBridge 172:65be27845400 13436 #define MDMA_GISR0_GIF11_Pos (11U)
AnnaBridge 172:65be27845400 13437 #define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13438 #define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
AnnaBridge 172:65be27845400 13439 #define MDMA_GISR0_GIF12_Pos (12U)
AnnaBridge 172:65be27845400 13440 #define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13441 #define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
AnnaBridge 172:65be27845400 13442 #define MDMA_GISR0_GIF13_Pos (13U)
AnnaBridge 172:65be27845400 13443 #define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13444 #define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
AnnaBridge 172:65be27845400 13445 #define MDMA_GISR0_GIF14_Pos (14U)
AnnaBridge 172:65be27845400 13446 #define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13447 #define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
AnnaBridge 172:65be27845400 13448 #define MDMA_GISR0_GIF15_Pos (15U)
AnnaBridge 172:65be27845400 13449 #define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13450 #define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
AnnaBridge 172:65be27845400 13451
AnnaBridge 172:65be27845400 13452 /******************** Bit definition for MDMA_CxISR register ****************/
AnnaBridge 172:65be27845400 13453 #define MDMA_CISR_TEIF_Pos (0U)
AnnaBridge 172:65be27845400 13454 #define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13455 #define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
AnnaBridge 172:65be27845400 13456 #define MDMA_CISR_CTCIF_Pos (1U)
AnnaBridge 172:65be27845400 13457 #define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13458 #define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
AnnaBridge 172:65be27845400 13459 #define MDMA_CISR_BRTIF_Pos (2U)
AnnaBridge 172:65be27845400 13460 #define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13461 #define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
AnnaBridge 172:65be27845400 13462 #define MDMA_CISR_BTIF_Pos (3U)
AnnaBridge 172:65be27845400 13463 #define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13464 #define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
AnnaBridge 172:65be27845400 13465 #define MDMA_CISR_TCIF_Pos (4U)
AnnaBridge 172:65be27845400 13466 #define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13467 #define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
AnnaBridge 172:65be27845400 13468 #define MDMA_CISR_CRQA_Pos (16U)
AnnaBridge 172:65be27845400 13469 #define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13470 #define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
AnnaBridge 172:65be27845400 13471
AnnaBridge 172:65be27845400 13472 /******************** Bit definition for MDMA_CxIFCR register ****************/
AnnaBridge 172:65be27845400 13473 #define MDMA_CIFCR_CTEIF_Pos (0U)
AnnaBridge 172:65be27845400 13474 #define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13475 #define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
AnnaBridge 172:65be27845400 13476 #define MDMA_CIFCR_CCTCIF_Pos (1U)
AnnaBridge 172:65be27845400 13477 #define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13478 #define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
AnnaBridge 172:65be27845400 13479 #define MDMA_CIFCR_CBRTIF_Pos (2U)
AnnaBridge 172:65be27845400 13480 #define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13481 #define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
AnnaBridge 172:65be27845400 13482 #define MDMA_CIFCR_CBTIF_Pos (3U)
AnnaBridge 172:65be27845400 13483 #define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13484 #define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
AnnaBridge 172:65be27845400 13485 #define MDMA_CIFCR_CLTCIF_Pos (4U)
AnnaBridge 172:65be27845400 13486 #define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13487 #define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
AnnaBridge 172:65be27845400 13488
AnnaBridge 172:65be27845400 13489 /******************** Bit definition for MDMA_CxESR register ****************/
AnnaBridge 172:65be27845400 13490 #define MDMA_CESR_TEA_Pos (0U)
AnnaBridge 172:65be27845400 13491 #define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 13492 #define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
AnnaBridge 172:65be27845400 13493 #define MDMA_CESR_TED_Pos (7U)
AnnaBridge 172:65be27845400 13494 #define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13495 #define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
AnnaBridge 172:65be27845400 13496 #define MDMA_CESR_TELD_Pos (8U)
AnnaBridge 172:65be27845400 13497 #define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13498 #define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
AnnaBridge 172:65be27845400 13499 #define MDMA_CESR_TEMD_Pos (9U)
AnnaBridge 172:65be27845400 13500 #define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13501 #define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
AnnaBridge 172:65be27845400 13502 #define MDMA_CESR_ASE_Pos (10U)
AnnaBridge 172:65be27845400 13503 #define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13504 #define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
AnnaBridge 172:65be27845400 13505 #define MDMA_CESR_BSE_Pos (11U)
AnnaBridge 172:65be27845400 13506 #define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13507 #define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
AnnaBridge 172:65be27845400 13508
AnnaBridge 172:65be27845400 13509 /******************** Bit definition for MDMA_CxCR register ****************/
AnnaBridge 172:65be27845400 13510 #define MDMA_CCR_EN_Pos (0U)
AnnaBridge 172:65be27845400 13511 #define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13512 #define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
AnnaBridge 172:65be27845400 13513 #define MDMA_CCR_TEIE_Pos (1U)
AnnaBridge 172:65be27845400 13514 #define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13515 #define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 172:65be27845400 13516 #define MDMA_CCR_CTCIE_Pos (2U)
AnnaBridge 172:65be27845400 13517 #define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13518 #define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
AnnaBridge 172:65be27845400 13519 #define MDMA_CCR_BRTIE_Pos (3U)
AnnaBridge 172:65be27845400 13520 #define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13521 #define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
AnnaBridge 172:65be27845400 13522 #define MDMA_CCR_BTIE_Pos (4U)
AnnaBridge 172:65be27845400 13523 #define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13524 #define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
AnnaBridge 172:65be27845400 13525 #define MDMA_CCR_TCIE_Pos (5U)
AnnaBridge 172:65be27845400 13526 #define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13527 #define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
AnnaBridge 172:65be27845400 13528 #define MDMA_CCR_PL_Pos (6U)
AnnaBridge 172:65be27845400 13529 #define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 13530 #define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
AnnaBridge 172:65be27845400 13531 #define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13532 #define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13533 #define MDMA_CCR_BEX_Pos (12U)
AnnaBridge 172:65be27845400 13534 #define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13535 #define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
AnnaBridge 172:65be27845400 13536 #define MDMA_CCR_HEX_Pos (13U)
AnnaBridge 172:65be27845400 13537 #define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13538 #define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
AnnaBridge 172:65be27845400 13539 #define MDMA_CCR_WEX_Pos (14U)
AnnaBridge 172:65be27845400 13540 #define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13541 #define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
AnnaBridge 172:65be27845400 13542 #define MDMA_CCR_SWRQ_Pos (16U)
AnnaBridge 172:65be27845400 13543 #define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13544 #define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
AnnaBridge 172:65be27845400 13545
AnnaBridge 172:65be27845400 13546 /******************** Bit definition for MDMA_CxTCR register ****************/
AnnaBridge 172:65be27845400 13547 #define MDMA_CTCR_SINC_Pos (0U)
AnnaBridge 172:65be27845400 13548 #define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 13549 #define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
AnnaBridge 172:65be27845400 13550 #define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13551 #define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13552 #define MDMA_CTCR_DINC_Pos (2U)
AnnaBridge 172:65be27845400 13553 #define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 13554 #define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
AnnaBridge 172:65be27845400 13555 #define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13556 #define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13557 #define MDMA_CTCR_SSIZE_Pos (4U)
AnnaBridge 172:65be27845400 13558 #define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 13559 #define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
AnnaBridge 172:65be27845400 13560 #define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13561 #define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13562 #define MDMA_CTCR_DSIZE_Pos (6U)
AnnaBridge 172:65be27845400 13563 #define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 13564 #define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
AnnaBridge 172:65be27845400 13565 #define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13566 #define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13567 #define MDMA_CTCR_SINCOS_Pos (8U)
AnnaBridge 172:65be27845400 13568 #define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 13569 #define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
AnnaBridge 172:65be27845400 13570 #define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13571 #define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13572 #define MDMA_CTCR_DINCOS_Pos (10U)
AnnaBridge 172:65be27845400 13573 #define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 13574 #define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
AnnaBridge 172:65be27845400 13575 #define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 13576 #define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13577 #define MDMA_CTCR_SBURST_Pos (12U)
AnnaBridge 172:65be27845400 13578 #define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 13579 #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
AnnaBridge 172:65be27845400 13580 #define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13581 #define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13582 #define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13583 #define MDMA_CTCR_DBURST_Pos (15U)
AnnaBridge 172:65be27845400 13584 #define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
AnnaBridge 172:65be27845400 13585 #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
AnnaBridge 172:65be27845400 13586 #define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13587 #define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13588 #define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13589 #define MDMA_CTCR_TLEN_Pos (18U)
AnnaBridge 172:65be27845400 13590 #define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
AnnaBridge 172:65be27845400 13591 #define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
AnnaBridge 172:65be27845400 13592 #define MDMA_CTCR_PKE_Pos (25U)
AnnaBridge 172:65be27845400 13593 #define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 13594 #define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
AnnaBridge 172:65be27845400 13595 #define MDMA_CTCR_PAM_Pos (26U)
AnnaBridge 172:65be27845400 13596 #define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 13597 #define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
AnnaBridge 172:65be27845400 13598 #define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
AnnaBridge 172:65be27845400 13599 #define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
AnnaBridge 172:65be27845400 13600 #define MDMA_CTCR_TRGM_Pos (28U)
AnnaBridge 172:65be27845400 13601 #define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 13602 #define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
AnnaBridge 172:65be27845400 13603 #define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 13604 #define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 13605 #define MDMA_CTCR_SWRM_Pos (30U)
AnnaBridge 172:65be27845400 13606 #define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 13607 #define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
AnnaBridge 172:65be27845400 13608 #define MDMA_CTCR_BWM_Pos (31U)
AnnaBridge 172:65be27845400 13609 #define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 13610 #define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
AnnaBridge 172:65be27845400 13611
AnnaBridge 172:65be27845400 13612 /******************** Bit definition for MDMA_CxBNDTR register ****************/
AnnaBridge 172:65be27845400 13613 #define MDMA_CBNDTR_BNDT_Pos (0U)
AnnaBridge 172:65be27845400 13614 #define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
AnnaBridge 172:65be27845400 13615 #define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
AnnaBridge 172:65be27845400 13616 #define MDMA_CBNDTR_BRSUM_Pos (18U)
AnnaBridge 172:65be27845400 13617 #define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13618 #define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
AnnaBridge 172:65be27845400 13619 #define MDMA_CBNDTR_BRDUM_Pos (19U)
AnnaBridge 172:65be27845400 13620 #define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 13621 #define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
AnnaBridge 172:65be27845400 13622 #define MDMA_CBNDTR_BRC_Pos (20U)
AnnaBridge 172:65be27845400 13623 #define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
AnnaBridge 172:65be27845400 13624 #define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
AnnaBridge 172:65be27845400 13625
AnnaBridge 172:65be27845400 13626 /******************** Bit definition for MDMA_CxSAR register ****************/
AnnaBridge 172:65be27845400 13627 #define MDMA_CSAR_SAR_Pos (0U)
AnnaBridge 172:65be27845400 13628 #define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13629 #define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
AnnaBridge 172:65be27845400 13630
AnnaBridge 172:65be27845400 13631 /******************** Bit definition for MDMA_CxDAR register ****************/
AnnaBridge 172:65be27845400 13632 #define MDMA_CDAR_DAR_Pos (0U)
AnnaBridge 172:65be27845400 13633 #define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13634 #define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
AnnaBridge 172:65be27845400 13635
AnnaBridge 172:65be27845400 13636 /******************** Bit definition for MDMA_CxBRUR ************************/
AnnaBridge 172:65be27845400 13637 #define MDMA_CBRUR_SUV_Pos (0U)
AnnaBridge 172:65be27845400 13638 #define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 13639 #define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
AnnaBridge 172:65be27845400 13640 #define MDMA_CBRUR_DUV_Pos (16U)
AnnaBridge 172:65be27845400 13641 #define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 13642 #define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
AnnaBridge 172:65be27845400 13643
AnnaBridge 172:65be27845400 13644 /******************** Bit definition for MDMA_CxLAR *************************/
AnnaBridge 172:65be27845400 13645 #define MDMA_CLAR_LAR_Pos (0U)
AnnaBridge 172:65be27845400 13646 #define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13647 #define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
AnnaBridge 172:65be27845400 13648
AnnaBridge 172:65be27845400 13649 /******************** Bit definition for MDMA_CxTBR) ************************/
AnnaBridge 172:65be27845400 13650 #define MDMA_CTBR_TSEL_Pos (0U)
AnnaBridge 172:65be27845400 13651 #define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 13652 #define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
AnnaBridge 172:65be27845400 13653 #define MDMA_CTBR_SBUS_Pos (16U)
AnnaBridge 172:65be27845400 13654 #define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13655 #define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
AnnaBridge 172:65be27845400 13656 #define MDMA_CTBR_DBUS_Pos (17U)
AnnaBridge 172:65be27845400 13657 #define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13658 #define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
AnnaBridge 172:65be27845400 13659
AnnaBridge 172:65be27845400 13660 /******************** Bit definition for MDMA_CxMAR) ************************/
AnnaBridge 172:65be27845400 13661 #define MDMA_CMAR_MAR_Pos (0U)
AnnaBridge 172:65be27845400 13662 #define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13663 #define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
AnnaBridge 172:65be27845400 13664
AnnaBridge 172:65be27845400 13665 /******************** Bit definition for MDMA_CxMDR) ************************/
AnnaBridge 172:65be27845400 13666 #define MDMA_CMDR_MDR_Pos (0U)
AnnaBridge 172:65be27845400 13667 #define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 13668 #define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */
AnnaBridge 172:65be27845400 13669
AnnaBridge 172:65be27845400 13670 /******************************************************************************/
AnnaBridge 172:65be27845400 13671 /* */
AnnaBridge 172:65be27845400 13672 /* Operational Amplifier (OPAMP) */
AnnaBridge 172:65be27845400 13673 /* */
AnnaBridge 172:65be27845400 13674 /******************************************************************************/
AnnaBridge 172:65be27845400 13675 /********************* Bit definition for OPAMPx_CSR register ***************/
AnnaBridge 172:65be27845400 13676 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
AnnaBridge 172:65be27845400 13677 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13678 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
AnnaBridge 172:65be27845400 13679 #define OPAMP_CSR_FORCEVP_Pos (1U)
AnnaBridge 172:65be27845400 13680 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13681 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
AnnaBridge 172:65be27845400 13682
AnnaBridge 172:65be27845400 13683 #define OPAMP_CSR_VPSEL_Pos (2U)
AnnaBridge 172:65be27845400 13684 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 13685 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
AnnaBridge 172:65be27845400 13686 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13687 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13688
AnnaBridge 172:65be27845400 13689 #define OPAMP_CSR_VMSEL_Pos (5U)
AnnaBridge 172:65be27845400 13690 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 13691 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
AnnaBridge 172:65be27845400 13692 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13693 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13694
AnnaBridge 172:65be27845400 13695 #define OPAMP_CSR_OPAHSM_Pos (8U)
AnnaBridge 172:65be27845400 13696 #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13697 #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
AnnaBridge 172:65be27845400 13698 #define OPAMP_CSR_CALON_Pos (11U)
AnnaBridge 172:65be27845400 13699 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13700 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
AnnaBridge 172:65be27845400 13701
AnnaBridge 172:65be27845400 13702 #define OPAMP_CSR_CALSEL_Pos (12U)
AnnaBridge 172:65be27845400 13703 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 13704 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
AnnaBridge 172:65be27845400 13705 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13706 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13707
AnnaBridge 172:65be27845400 13708 #define OPAMP_CSR_PGGAIN_Pos (14U)
AnnaBridge 172:65be27845400 13709 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 13710 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
AnnaBridge 172:65be27845400 13711 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13712 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13713 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13714 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13715
AnnaBridge 172:65be27845400 13716 #define OPAMP_CSR_USERTRIM_Pos (18U)
AnnaBridge 172:65be27845400 13717 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13718 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
AnnaBridge 172:65be27845400 13719 #define OPAMP_CSR_TSTREF_Pos (29U)
AnnaBridge 172:65be27845400 13720 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 13721 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
AnnaBridge 172:65be27845400 13722 #define OPAMP_CSR_CALOUT_Pos (30U)
AnnaBridge 172:65be27845400 13723 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 13724 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
AnnaBridge 172:65be27845400 13725
AnnaBridge 172:65be27845400 13726 /********************* Bit definition for OPAMP1_CSR register ***************/
AnnaBridge 172:65be27845400 13727 #define OPAMP1_CSR_OPAEN_Pos (0U)
AnnaBridge 172:65be27845400 13728 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13729 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
AnnaBridge 172:65be27845400 13730 #define OPAMP1_CSR_FORCEVP_Pos (1U)
AnnaBridge 172:65be27845400 13731 #define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13732 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
AnnaBridge 172:65be27845400 13733
AnnaBridge 172:65be27845400 13734 #define OPAMP1_CSR_VPSEL_Pos (2U)
AnnaBridge 172:65be27845400 13735 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 13736 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
AnnaBridge 172:65be27845400 13737 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13738 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13739
AnnaBridge 172:65be27845400 13740 #define OPAMP1_CSR_VMSEL_Pos (5U)
AnnaBridge 172:65be27845400 13741 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 13742 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
AnnaBridge 172:65be27845400 13743 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13744 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13745
AnnaBridge 172:65be27845400 13746 #define OPAMP1_CSR_OPAHSM_Pos (8U)
AnnaBridge 172:65be27845400 13747 #define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13748 #define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
AnnaBridge 172:65be27845400 13749 #define OPAMP1_CSR_CALON_Pos (11U)
AnnaBridge 172:65be27845400 13750 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13751 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
AnnaBridge 172:65be27845400 13752
AnnaBridge 172:65be27845400 13753 #define OPAMP1_CSR_CALSEL_Pos (12U)
AnnaBridge 172:65be27845400 13754 #define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 13755 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
AnnaBridge 172:65be27845400 13756 #define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13757 #define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13758
AnnaBridge 172:65be27845400 13759 #define OPAMP1_CSR_PGGAIN_Pos (14U)
AnnaBridge 172:65be27845400 13760 #define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 13761 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
AnnaBridge 172:65be27845400 13762 #define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13763 #define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13764 #define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13765 #define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13766
AnnaBridge 172:65be27845400 13767 #define OPAMP1_CSR_USERTRIM_Pos (18U)
AnnaBridge 172:65be27845400 13768 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13769 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
AnnaBridge 172:65be27845400 13770 #define OPAMP1_CSR_TSTREF_Pos (29U)
AnnaBridge 172:65be27845400 13771 #define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 13772 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
AnnaBridge 172:65be27845400 13773 #define OPAMP1_CSR_CALOUT_Pos (30U)
AnnaBridge 172:65be27845400 13774 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 13775 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
AnnaBridge 172:65be27845400 13776
AnnaBridge 172:65be27845400 13777 /********************* Bit definition for OPAMP2_CSR register ***************/
AnnaBridge 172:65be27845400 13778 #define OPAMP2_CSR_OPAEN_Pos (0U)
AnnaBridge 172:65be27845400 13779 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13780 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
AnnaBridge 172:65be27845400 13781 #define OPAMP2_CSR_FORCEVP_Pos (1U)
AnnaBridge 172:65be27845400 13782 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 13783 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
AnnaBridge 172:65be27845400 13784
AnnaBridge 172:65be27845400 13785 #define OPAMP2_CSR_VPSEL_Pos (2U)
AnnaBridge 172:65be27845400 13786 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 13787 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
AnnaBridge 172:65be27845400 13788 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 13789 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 13790
AnnaBridge 172:65be27845400 13791 #define OPAMP2_CSR_VMSEL_Pos (5U)
AnnaBridge 172:65be27845400 13792 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 13793 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
AnnaBridge 172:65be27845400 13794 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13795 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13796
AnnaBridge 172:65be27845400 13797 #define OPAMP2_CSR_OPAHSM_Pos (8U)
AnnaBridge 172:65be27845400 13798 #define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13799 #define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
AnnaBridge 172:65be27845400 13800 #define OPAMP2_CSR_CALON_Pos (11U)
AnnaBridge 172:65be27845400 13801 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 13802 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
AnnaBridge 172:65be27845400 13803
AnnaBridge 172:65be27845400 13804 #define OPAMP2_CSR_CALSEL_Pos (12U)
AnnaBridge 172:65be27845400 13805 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 13806 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
AnnaBridge 172:65be27845400 13807 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 13808 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13809
AnnaBridge 172:65be27845400 13810 #define OPAMP2_CSR_PGGAIN_Pos (14U)
AnnaBridge 172:65be27845400 13811 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 13812 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
AnnaBridge 172:65be27845400 13813 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13814 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13815 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13816 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13817
AnnaBridge 172:65be27845400 13818 #define OPAMP2_CSR_USERTRIM_Pos (18U)
AnnaBridge 172:65be27845400 13819 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13820 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
AnnaBridge 172:65be27845400 13821 #define OPAMP2_CSR_TSTREF_Pos (29U)
AnnaBridge 172:65be27845400 13822 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 13823 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
AnnaBridge 172:65be27845400 13824 #define OPAMP2_CSR_CALOUT_Pos (30U)
AnnaBridge 172:65be27845400 13825 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 13826 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
AnnaBridge 172:65be27845400 13827
AnnaBridge 172:65be27845400 13828 /******************* Bit definition for OPAMP_OTR register ******************/
AnnaBridge 172:65be27845400 13829 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
AnnaBridge 172:65be27845400 13830 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 13831 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 172:65be27845400 13832 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
AnnaBridge 172:65be27845400 13833 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 13834 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 172:65be27845400 13835
AnnaBridge 172:65be27845400 13836 /******************* Bit definition for OPAMP1_OTR register ******************/
AnnaBridge 172:65be27845400 13837 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
AnnaBridge 172:65be27845400 13838 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 13839 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 172:65be27845400 13840 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
AnnaBridge 172:65be27845400 13841 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 13842 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 172:65be27845400 13843
AnnaBridge 172:65be27845400 13844 /******************* Bit definition for OPAMP2_OTR register ******************/
AnnaBridge 172:65be27845400 13845 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
AnnaBridge 172:65be27845400 13846 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 13847 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 172:65be27845400 13848 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
AnnaBridge 172:65be27845400 13849 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 13850 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 172:65be27845400 13851
AnnaBridge 172:65be27845400 13852 /******************* Bit definition for OPAMP_HSOTR register ****************/
AnnaBridge 172:65be27845400 13853 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
AnnaBridge 172:65be27845400 13854 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 13855 #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 172:65be27845400 13856 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
AnnaBridge 172:65be27845400 13857 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 13858 #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 172:65be27845400 13859
AnnaBridge 172:65be27845400 13860 /******************* Bit definition for OPAMP1_HSOTR register ****************/
AnnaBridge 172:65be27845400 13861 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
AnnaBridge 172:65be27845400 13862 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 13863 #define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 172:65be27845400 13864 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
AnnaBridge 172:65be27845400 13865 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 13866 #define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 172:65be27845400 13867
AnnaBridge 172:65be27845400 13868 /******************* Bit definition for OPAMP2_HSOTR register ****************/
AnnaBridge 172:65be27845400 13869 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
AnnaBridge 172:65be27845400 13870 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 13871 #define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
AnnaBridge 172:65be27845400 13872 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
AnnaBridge 172:65be27845400 13873 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 13874 #define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
AnnaBridge 172:65be27845400 13875
AnnaBridge 172:65be27845400 13876 /******************************************************************************/
AnnaBridge 172:65be27845400 13877 /* */
AnnaBridge 172:65be27845400 13878 /* Power Control */
AnnaBridge 172:65be27845400 13879 /* */
AnnaBridge 172:65be27845400 13880 /******************************************************************************/
AnnaBridge 172:65be27845400 13881
AnnaBridge 172:65be27845400 13882 /******************** Bit definition for PWR_CR1 register ********************/
AnnaBridge 172:65be27845400 13883 #define PWR_CR1_ALS_Pos (17U)
AnnaBridge 172:65be27845400 13884 #define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 13885 #define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
AnnaBridge 172:65be27845400 13886 #define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13887 #define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13888 #define PWR_CR1_AVDEN_Pos (16U)
AnnaBridge 172:65be27845400 13889 #define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13890 #define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
AnnaBridge 172:65be27845400 13891 #define PWR_CR1_SVOS_Pos (14U)
AnnaBridge 172:65be27845400 13892 #define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 13893 #define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */
AnnaBridge 172:65be27845400 13894 #define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13895 #define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13896 #define PWR_CR1_FLPS_Pos (9U)
AnnaBridge 172:65be27845400 13897 #define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 13898 #define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
AnnaBridge 172:65be27845400 13899 #define PWR_CR1_DBP_Pos (8U)
AnnaBridge 172:65be27845400 13900 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 13901 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
AnnaBridge 172:65be27845400 13902 #define PWR_CR1_PLS_Pos (5U)
AnnaBridge 172:65be27845400 13903 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 172:65be27845400 13904 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
AnnaBridge 172:65be27845400 13905 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13906 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13907 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13908 #define PWR_CR1_PVDEN_Pos (4U)
AnnaBridge 172:65be27845400 13909 #define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13910 #define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable. */
AnnaBridge 172:65be27845400 13911 #define PWR_CR1_LPDS_Pos (0U)
AnnaBridge 172:65be27845400 13912 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13913 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
AnnaBridge 172:65be27845400 13914
AnnaBridge 172:65be27845400 13915 /*!< PVD level configuration */
AnnaBridge 172:65be27845400 13916 #define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */
AnnaBridge 172:65be27845400 13917 #define PWR_CR1_PLS_LEV1_Pos (5U)
AnnaBridge 172:65be27845400 13918 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 13919 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
AnnaBridge 172:65be27845400 13920 #define PWR_CR1_PLS_LEV2_Pos (6U)
AnnaBridge 172:65be27845400 13921 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 13922 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
AnnaBridge 172:65be27845400 13923 #define PWR_CR1_PLS_LEV3_Pos (5U)
AnnaBridge 172:65be27845400 13924 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 13925 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
AnnaBridge 172:65be27845400 13926 #define PWR_CR1_PLS_LEV4_Pos (7U)
AnnaBridge 172:65be27845400 13927 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 13928 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
AnnaBridge 172:65be27845400 13929 #define PWR_CR1_PLS_LEV5_Pos (5U)
AnnaBridge 172:65be27845400 13930 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
AnnaBridge 172:65be27845400 13931 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
AnnaBridge 172:65be27845400 13932 #define PWR_CR1_PLS_LEV6_Pos (6U)
AnnaBridge 172:65be27845400 13933 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 13934 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
AnnaBridge 172:65be27845400 13935 #define PWR_CR1_PLS_LEV7_Pos (5U)
AnnaBridge 172:65be27845400 13936 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
AnnaBridge 172:65be27845400 13937 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
AnnaBridge 172:65be27845400 13938
AnnaBridge 172:65be27845400 13939 /*!< AVD level configuration */
AnnaBridge 172:65be27845400 13940 #define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */
AnnaBridge 172:65be27845400 13941 #define PWR_CR1_ALS_LEV1_Pos (17U)
AnnaBridge 172:65be27845400 13942 #define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 13943 #define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
AnnaBridge 172:65be27845400 13944 #define PWR_CR1_ALS_LEV2_Pos (18U)
AnnaBridge 172:65be27845400 13945 #define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 13946 #define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
AnnaBridge 172:65be27845400 13947 #define PWR_CR1_ALS_LEV3_Pos (17U)
AnnaBridge 172:65be27845400 13948 #define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 13949 #define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
AnnaBridge 172:65be27845400 13950
AnnaBridge 172:65be27845400 13951 /******************** Bit definition for PWR_CSR1 register ********************/
AnnaBridge 172:65be27845400 13952 #define PWR_CSR1_AVDO_Pos (16U)
AnnaBridge 172:65be27845400 13953 #define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13954 #define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
AnnaBridge 172:65be27845400 13955 #define PWR_CSR1_ACTVOS_Pos (14U)
AnnaBridge 172:65be27845400 13956 #define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 13957 #define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
AnnaBridge 172:65be27845400 13958 #define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 13959 #define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 13960 #define PWR_CSR1_ACTVOSRDY_Pos (13U)
AnnaBridge 172:65be27845400 13961 #define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 13962 #define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
AnnaBridge 172:65be27845400 13963 #define PWR_CSR1_PVDO_Pos (4U)
AnnaBridge 172:65be27845400 13964 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13965 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
AnnaBridge 172:65be27845400 13966
AnnaBridge 172:65be27845400 13967 /******************** Bit definition for PWR_CR2 register ********************/
AnnaBridge 172:65be27845400 13968 #define PWR_CR2_TEMPH_Pos (23U)
AnnaBridge 172:65be27845400 13969 #define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 13970 #define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
AnnaBridge 172:65be27845400 13971 #define PWR_CR2_TEMPL_Pos (22U)
AnnaBridge 172:65be27845400 13972 #define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 13973 #define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
AnnaBridge 172:65be27845400 13974 #define PWR_CR2_VBATH_Pos (21U)
AnnaBridge 172:65be27845400 13975 #define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 13976 #define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
AnnaBridge 172:65be27845400 13977 #define PWR_CR2_VBATL_Pos (20U)
AnnaBridge 172:65be27845400 13978 #define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 13979 #define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
AnnaBridge 172:65be27845400 13980 #define PWR_CR2_BRRDY_Pos (16U)
AnnaBridge 172:65be27845400 13981 #define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 13982 #define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
AnnaBridge 172:65be27845400 13983 #define PWR_CR2_MONEN_Pos (4U)
AnnaBridge 172:65be27845400 13984 #define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 13985 #define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
AnnaBridge 172:65be27845400 13986 #define PWR_CR2_BREN_Pos (0U)
AnnaBridge 172:65be27845400 13987 #define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 13988 #define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
AnnaBridge 172:65be27845400 13989
AnnaBridge 172:65be27845400 13990 /******************** Bit definition for PWR_CR3 register ********************/
AnnaBridge 172:65be27845400 13991 #define PWR_CR3_USB33RDY_Pos (26U)
AnnaBridge 172:65be27845400 13992 #define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 13993 #define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
AnnaBridge 172:65be27845400 13994 #define PWR_CR3_USBREGEN_Pos (25U)
AnnaBridge 172:65be27845400 13995 #define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 13996 #define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
AnnaBridge 172:65be27845400 13997 #define PWR_CR3_USB33DEN_Pos (24U)
AnnaBridge 172:65be27845400 13998 #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 13999 #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
AnnaBridge 172:65be27845400 14000 #define PWR_CR3_VBRS_Pos (9U)
AnnaBridge 172:65be27845400 14001 #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14002 #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
AnnaBridge 172:65be27845400 14003 #define PWR_CR3_VBE_Pos (8U)
AnnaBridge 172:65be27845400 14004 #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14005 #define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
AnnaBridge 172:65be27845400 14006 #define PWR_CR3_SCUEN_Pos (2U)
AnnaBridge 172:65be27845400 14007 #define PWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14008 #define PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk /*!< Supply configuration update enable */
AnnaBridge 172:65be27845400 14009 #define PWR_CR3_LDOEN_Pos (1U)
AnnaBridge 172:65be27845400 14010 #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14011 #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
AnnaBridge 172:65be27845400 14012 #define PWR_CR3_BYPASS_Pos (0U)
AnnaBridge 172:65be27845400 14013 #define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14014 #define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
AnnaBridge 172:65be27845400 14015
AnnaBridge 172:65be27845400 14016 /******************** Bit definition for PWR_CPUCR register ********************/
AnnaBridge 172:65be27845400 14017 #define PWR_CPUCR_RUN_D3_Pos (11U)
AnnaBridge 172:65be27845400 14018 #define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14019 #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
AnnaBridge 172:65be27845400 14020 #define PWR_CPUCR_CSSF_Pos (9U)
AnnaBridge 172:65be27845400 14021 #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14022 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
AnnaBridge 172:65be27845400 14023 #define PWR_CPUCR_SBF_D2_Pos (8U)
AnnaBridge 172:65be27845400 14024 #define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14025 #define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
AnnaBridge 172:65be27845400 14026 #define PWR_CPUCR_SBF_D1_Pos (7U)
AnnaBridge 172:65be27845400 14027 #define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14028 #define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
AnnaBridge 172:65be27845400 14029 #define PWR_CPUCR_SBF_Pos (6U)
AnnaBridge 172:65be27845400 14030 #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14031 #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
AnnaBridge 172:65be27845400 14032 #define PWR_CPUCR_STOPF_Pos (5U)
AnnaBridge 172:65be27845400 14033 #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14034 #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
AnnaBridge 172:65be27845400 14035 #define PWR_CPUCR_PDDS_D3_Pos (2U)
AnnaBridge 172:65be27845400 14036 #define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14037 #define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
AnnaBridge 172:65be27845400 14038 #define PWR_CPUCR_PDDS_D2_Pos (1U)
AnnaBridge 172:65be27845400 14039 #define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14040 #define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
AnnaBridge 172:65be27845400 14041 #define PWR_CPUCR_PDDS_D1_Pos (0U)
AnnaBridge 172:65be27845400 14042 #define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14043 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
AnnaBridge 172:65be27845400 14044
AnnaBridge 172:65be27845400 14045 /******************** Bit definition for PWR_D3CR register ********************/
AnnaBridge 172:65be27845400 14046 #define PWR_D3CR_VOS_Pos (14U)
AnnaBridge 172:65be27845400 14047 #define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 14048 #define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
AnnaBridge 172:65be27845400 14049 #define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14050 #define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14051 #define PWR_D3CR_VOSRDY_Pos (13U)
AnnaBridge 172:65be27845400 14052 #define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14053 #define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
AnnaBridge 172:65be27845400 14054
AnnaBridge 172:65be27845400 14055 /******************** Bit definition for PWR_WKUPCR register ********************/
AnnaBridge 172:65be27845400 14056 #define PWR_WKUPCR_WKUPC6_Pos (5U)
AnnaBridge 172:65be27845400 14057 #define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14058 #define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
AnnaBridge 172:65be27845400 14059 #define PWR_WKUPCR_WKUPC5_Pos (4U)
AnnaBridge 172:65be27845400 14060 #define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14061 #define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
AnnaBridge 172:65be27845400 14062 #define PWR_WKUPCR_WKUPC4_Pos (3U)
AnnaBridge 172:65be27845400 14063 #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14064 #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
AnnaBridge 172:65be27845400 14065 #define PWR_WKUPCR_WKUPC3_Pos (2U)
AnnaBridge 172:65be27845400 14066 #define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14067 #define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
AnnaBridge 172:65be27845400 14068 #define PWR_WKUPCR_WKUPC2_Pos (1U)
AnnaBridge 172:65be27845400 14069 #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14070 #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
AnnaBridge 172:65be27845400 14071 #define PWR_WKUPCR_WKUPC1_Pos (0U)
AnnaBridge 172:65be27845400 14072 #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14073 #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
AnnaBridge 172:65be27845400 14074
AnnaBridge 172:65be27845400 14075 /******************** Bit definition for PWR_WKUPFR register ********************/
AnnaBridge 172:65be27845400 14076 #define PWR_WKUPFR_WKUPF6_Pos (5U)
AnnaBridge 172:65be27845400 14077 #define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14078 #define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
AnnaBridge 172:65be27845400 14079 #define PWR_WKUPFR_WKUPF5_Pos (4U)
AnnaBridge 172:65be27845400 14080 #define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14081 #define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
AnnaBridge 172:65be27845400 14082 #define PWR_WKUPFR_WKUPF4_Pos (3U)
AnnaBridge 172:65be27845400 14083 #define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14084 #define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
AnnaBridge 172:65be27845400 14085 #define PWR_WKUPFR_WKUPF3_Pos (2U)
AnnaBridge 172:65be27845400 14086 #define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14087 #define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
AnnaBridge 172:65be27845400 14088 #define PWR_WKUPFR_WKUPF2_Pos (1U)
AnnaBridge 172:65be27845400 14089 #define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14090 #define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
AnnaBridge 172:65be27845400 14091 #define PWR_WKUPFR_WKUPF1_Pos (0U)
AnnaBridge 172:65be27845400 14092 #define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14093 #define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
AnnaBridge 172:65be27845400 14094
AnnaBridge 172:65be27845400 14095 /******************** Bit definition for PWR_WKUPEPR register ********************/
AnnaBridge 172:65be27845400 14096 #define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
AnnaBridge 172:65be27845400 14097 #define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 14098 #define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
AnnaBridge 172:65be27845400 14099 #define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 14100 #define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 14101 #define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
AnnaBridge 172:65be27845400 14102 #define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 14103 #define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
AnnaBridge 172:65be27845400 14104 #define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14105 #define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14106 #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
AnnaBridge 172:65be27845400 14107 #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 14108 #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
AnnaBridge 172:65be27845400 14109 #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14110 #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14111 #define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
AnnaBridge 172:65be27845400 14112 #define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 14113 #define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
AnnaBridge 172:65be27845400 14114 #define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14115 #define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14116 #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
AnnaBridge 172:65be27845400 14117 #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 14118 #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
AnnaBridge 172:65be27845400 14119 #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14120 #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 14121 #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
AnnaBridge 172:65be27845400 14122 #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 14123 #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
AnnaBridge 172:65be27845400 14124 #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14125 #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14126 #define PWR_WKUPEPR_WKUPP6_Pos (13U)
AnnaBridge 172:65be27845400 14127 #define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14128 #define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */
AnnaBridge 172:65be27845400 14129 #define PWR_WKUPEPR_WKUPP5_Pos (12U)
AnnaBridge 172:65be27845400 14130 #define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14131 #define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */
AnnaBridge 172:65be27845400 14132 #define PWR_WKUPEPR_WKUPP4_Pos (11U)
AnnaBridge 172:65be27845400 14133 #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14134 #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */
AnnaBridge 172:65be27845400 14135 #define PWR_WKUPEPR_WKUPP3_Pos (10U)
AnnaBridge 172:65be27845400 14136 #define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14137 #define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */
AnnaBridge 172:65be27845400 14138 #define PWR_WKUPEPR_WKUPP2_Pos (9U)
AnnaBridge 172:65be27845400 14139 #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14140 #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */
AnnaBridge 172:65be27845400 14141 #define PWR_WKUPEPR_WKUPP1_Pos (8U)
AnnaBridge 172:65be27845400 14142 #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14143 #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */
AnnaBridge 172:65be27845400 14144 #define PWR_WKUPEPR_WKUPEN6_Pos (5U)
AnnaBridge 172:65be27845400 14145 #define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14146 #define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */
AnnaBridge 172:65be27845400 14147 #define PWR_WKUPEPR_WKUPEN5_Pos (4U)
AnnaBridge 172:65be27845400 14148 #define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14149 #define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */
AnnaBridge 172:65be27845400 14150 #define PWR_WKUPEPR_WKUPEN4_Pos (3U)
AnnaBridge 172:65be27845400 14151 #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14152 #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */
AnnaBridge 172:65be27845400 14153 #define PWR_WKUPEPR_WKUPEN3_Pos (2U)
AnnaBridge 172:65be27845400 14154 #define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14155 #define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */
AnnaBridge 172:65be27845400 14156 #define PWR_WKUPEPR_WKUPEN2_Pos (1U)
AnnaBridge 172:65be27845400 14157 #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14158 #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */
AnnaBridge 172:65be27845400 14159 #define PWR_WKUPEPR_WKUPEN1_Pos (0U)
AnnaBridge 172:65be27845400 14160 #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14161 #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */
AnnaBridge 172:65be27845400 14162 #define PWR_WKUPEPR_WKUPEN_Pos (0U)
AnnaBridge 172:65be27845400 14163 #define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 14164 #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
AnnaBridge 172:65be27845400 14165
AnnaBridge 172:65be27845400 14166 /******************************************************************************/
AnnaBridge 172:65be27845400 14167 /* */
AnnaBridge 172:65be27845400 14168 /* Reset and Clock Control */
AnnaBridge 172:65be27845400 14169 /* */
AnnaBridge 172:65be27845400 14170 /******************************************************************************/
AnnaBridge 172:65be27845400 14171 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 172:65be27845400 14172 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 172:65be27845400 14173 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14174 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
AnnaBridge 172:65be27845400 14175 #define RCC_CR_HSIKERON_Pos (1U)
AnnaBridge 172:65be27845400 14176 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14177 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
AnnaBridge 172:65be27845400 14178 #define RCC_CR_HSIRDY_Pos (2U)
AnnaBridge 172:65be27845400 14179 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14180 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
AnnaBridge 172:65be27845400 14181 #define RCC_CR_HSIDIV_Pos (3U)
AnnaBridge 172:65be27845400 14182 #define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 14183 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
AnnaBridge 172:65be27845400 14184 #define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 14185 #define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14186 #define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14187 #define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 14188
AnnaBridge 172:65be27845400 14189 #define RCC_CR_HSIDIVF_Pos (5U)
AnnaBridge 172:65be27845400 14190 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14191 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
AnnaBridge 172:65be27845400 14192 #define RCC_CR_CSION_Pos (7U)
AnnaBridge 172:65be27845400 14193 #define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14194 #define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
AnnaBridge 172:65be27845400 14195 #define RCC_CR_CSIRDY_Pos (8U)
AnnaBridge 172:65be27845400 14196 #define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14197 #define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
AnnaBridge 172:65be27845400 14198 #define RCC_CR_CSIKERON_Pos (9U)
AnnaBridge 172:65be27845400 14199 #define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14200 #define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
AnnaBridge 172:65be27845400 14201 #define RCC_CR_HSI48ON_Pos (12U)
AnnaBridge 172:65be27845400 14202 #define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14203 #define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
AnnaBridge 172:65be27845400 14204 #define RCC_CR_HSI48RDY_Pos (13U)
AnnaBridge 172:65be27845400 14205 #define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14206 #define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
AnnaBridge 172:65be27845400 14207
AnnaBridge 172:65be27845400 14208 #define RCC_CR_D1CKRDY_Pos (14U)
AnnaBridge 172:65be27845400 14209 #define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14210 #define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk /*!< D1 domain clocks ready flag */
AnnaBridge 172:65be27845400 14211 #define RCC_CR_D2CKRDY_Pos (15U)
AnnaBridge 172:65be27845400 14212 #define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14213 #define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk /*!< D2 domain clocks ready flag */
AnnaBridge 172:65be27845400 14214
AnnaBridge 172:65be27845400 14215 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 172:65be27845400 14216 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14217 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
AnnaBridge 172:65be27845400 14218 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 172:65be27845400 14219 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14220 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
AnnaBridge 172:65be27845400 14221 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 172:65be27845400 14222 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14223 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
AnnaBridge 172:65be27845400 14224 #define RCC_CR_CSSHSEON_Pos (19U)
AnnaBridge 172:65be27845400 14225 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 14226 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
AnnaBridge 172:65be27845400 14227
AnnaBridge 172:65be27845400 14228
AnnaBridge 172:65be27845400 14229 #define RCC_CR_PLL1ON_Pos (24U)
AnnaBridge 172:65be27845400 14230 #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14231 #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
AnnaBridge 172:65be27845400 14232 #define RCC_CR_PLL1RDY_Pos (25U)
AnnaBridge 172:65be27845400 14233 #define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14234 #define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
AnnaBridge 172:65be27845400 14235 #define RCC_CR_PLL2ON_Pos (26U)
AnnaBridge 172:65be27845400 14236 #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 14237 #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
AnnaBridge 172:65be27845400 14238 #define RCC_CR_PLL2RDY_Pos (27U)
AnnaBridge 172:65be27845400 14239 #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 14240 #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
AnnaBridge 172:65be27845400 14241 #define RCC_CR_PLL3ON_Pos (28U)
AnnaBridge 172:65be27845400 14242 #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 14243 #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
AnnaBridge 172:65be27845400 14244 #define RCC_CR_PLL3RDY_Pos (29U)
AnnaBridge 172:65be27845400 14245 #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 14246 #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
AnnaBridge 172:65be27845400 14247
AnnaBridge 172:65be27845400 14248 /*Legacy */
AnnaBridge 172:65be27845400 14249 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 172:65be27845400 14250 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14251 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
AnnaBridge 172:65be27845400 14252 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 172:65be27845400 14253 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14254 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
AnnaBridge 172:65be27845400 14255
AnnaBridge 172:65be27845400 14256 /******************** Bit definition for RCC_ICSCR register ***************/
AnnaBridge 172:65be27845400 14257 /*!< HSICAL configuration */
AnnaBridge 172:65be27845400 14258 #define RCC_ICSCR_HSICAL_Pos (0U)
AnnaBridge 172:65be27845400 14259 #define RCC_ICSCR_HSICAL_Msk (0xFFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 14260 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[11:0] bits */
AnnaBridge 172:65be27845400 14261 #define RCC_ICSCR_HSICAL_0 (0x001UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14262 #define RCC_ICSCR_HSICAL_1 (0x002UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14263 #define RCC_ICSCR_HSICAL_2 (0x004UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14264 #define RCC_ICSCR_HSICAL_3 (0x008UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14265 #define RCC_ICSCR_HSICAL_4 (0x010UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14266 #define RCC_ICSCR_HSICAL_5 (0x020UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14267 #define RCC_ICSCR_HSICAL_6 (0x040UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14268 #define RCC_ICSCR_HSICAL_7 (0x080UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14269 #define RCC_ICSCR_HSICAL_8 (0x100UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14270 #define RCC_ICSCR_HSICAL_9 (0x200UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14271 #define RCC_ICSCR_HSICAL_10 (0x400UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14272 #define RCC_ICSCR_HSICAL_11 (0x800UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14273
AnnaBridge 172:65be27845400 14274 /*!< HSITRIM configuration */
AnnaBridge 172:65be27845400 14275 #define RCC_ICSCR_HSITRIM_Pos (12U)
AnnaBridge 172:65be27845400 14276 #define RCC_ICSCR_HSITRIM_Msk (0x3FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x0003F000 */
AnnaBridge 172:65be27845400 14277 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[5:0] bits */
AnnaBridge 172:65be27845400 14278 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14279 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14280 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14281 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14282 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14283 #define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14284
AnnaBridge 172:65be27845400 14285
AnnaBridge 172:65be27845400 14286 /*!< CSICAL configuration */
AnnaBridge 172:65be27845400 14287 #define RCC_ICSCR_CSICAL_Pos (18U)
AnnaBridge 172:65be27845400 14288 #define RCC_ICSCR_CSICAL_Msk (0xFFUL << RCC_ICSCR_CSICAL_Pos) /*!< 0x03FC0000 */
AnnaBridge 172:65be27845400 14289 #define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_Msk /*!< CSICAL[7:0] bits */
AnnaBridge 172:65be27845400 14290 #define RCC_ICSCR_CSICAL_0 (0x01UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14291 #define RCC_ICSCR_CSICAL_1 (0x02UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 14292 #define RCC_ICSCR_CSICAL_2 (0x04UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14293 #define RCC_ICSCR_CSICAL_3 (0x08UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14294 #define RCC_ICSCR_CSICAL_4 (0x10UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14295 #define RCC_ICSCR_CSICAL_5 (0x20UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14296 #define RCC_ICSCR_CSICAL_6 (0x40UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14297 #define RCC_ICSCR_CSICAL_7 (0x80UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14298
AnnaBridge 172:65be27845400 14299 /*!< CSITRIM configuration */
AnnaBridge 172:65be27845400 14300 #define RCC_ICSCR_CSITRIM_Pos (26U)
AnnaBridge 172:65be27845400 14301 #define RCC_ICSCR_CSITRIM_Msk (0x1FUL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x7C000000 */
AnnaBridge 172:65be27845400 14302 #define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_Msk /*!< CSITRIM[4:0] bits */
AnnaBridge 172:65be27845400 14303 #define RCC_ICSCR_CSITRIM_0 (0x01UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 14304 #define RCC_ICSCR_CSITRIM_1 (0x02UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 14305 #define RCC_ICSCR_CSITRIM_2 (0x04UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 14306 #define RCC_ICSCR_CSITRIM_3 (0x08UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 14307 #define RCC_ICSCR_CSITRIM_4 (0x10UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 14308
AnnaBridge 172:65be27845400 14309
AnnaBridge 172:65be27845400 14310
AnnaBridge 172:65be27845400 14311 /******************** Bit definition for RCC_CRRCR register *****************/
AnnaBridge 172:65be27845400 14312
AnnaBridge 172:65be27845400 14313 /*!< HSI48CAL configuration */
AnnaBridge 172:65be27845400 14314 #define RCC_CRRCR_HSI48CAL_Pos (0U)
AnnaBridge 172:65be27845400 14315 #define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 14316 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
AnnaBridge 172:65be27845400 14317 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14318 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14319 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14320 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14321 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14322 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14323 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14324 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14325 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14326 #define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14327
AnnaBridge 172:65be27845400 14328 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 172:65be27845400 14329 /*!< SW configuration */
AnnaBridge 172:65be27845400 14330 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 172:65be27845400 14331 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 14332 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
AnnaBridge 172:65be27845400 14333 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14334 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14335 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14336
AnnaBridge 172:65be27845400 14337 #define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */
AnnaBridge 172:65be27845400 14338 #define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */
AnnaBridge 172:65be27845400 14339 #define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */
AnnaBridge 172:65be27845400 14340 #define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */
AnnaBridge 172:65be27845400 14341
AnnaBridge 172:65be27845400 14342 /*!< SWS configuration */
AnnaBridge 172:65be27845400 14343 #define RCC_CFGR_SWS_Pos (3U)
AnnaBridge 172:65be27845400 14344 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 14345 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
AnnaBridge 172:65be27845400 14346 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14347 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14348 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14349
AnnaBridge 172:65be27845400 14350 #define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */
AnnaBridge 172:65be27845400 14351 #define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */
AnnaBridge 172:65be27845400 14352 #define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */
AnnaBridge 172:65be27845400 14353 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */
AnnaBridge 172:65be27845400 14354
AnnaBridge 172:65be27845400 14355 #define RCC_CFGR_STOPWUCK_Pos (6U)
AnnaBridge 172:65be27845400 14356 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14357 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
AnnaBridge 172:65be27845400 14358
AnnaBridge 172:65be27845400 14359 #define RCC_CFGR_STOPKERWUCK_Pos (7U)
AnnaBridge 172:65be27845400 14360 #define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14361 #define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */
AnnaBridge 172:65be27845400 14362
AnnaBridge 172:65be27845400 14363 /*!< RTCPRE configuration */
AnnaBridge 172:65be27845400 14364 #define RCC_CFGR_RTCPRE_Pos (8U)
AnnaBridge 172:65be27845400 14365 #define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
AnnaBridge 172:65be27845400 14366 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */
AnnaBridge 172:65be27845400 14367 #define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14368 #define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14369 #define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14370 #define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14371 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14372 #define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14373
AnnaBridge 172:65be27845400 14374 /*!< HRTIMSEL configuration */
AnnaBridge 172:65be27845400 14375 #define RCC_CFGR_HRTIMSEL_Pos (14U)
AnnaBridge 172:65be27845400 14376 #define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
AnnaBridge 172:65be27845400 14377 #define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14378
AnnaBridge 172:65be27845400 14379 /*!< TIMPRE configuration */
AnnaBridge 172:65be27845400 14380 #define RCC_CFGR_TIMPRE_Pos (15U)
AnnaBridge 172:65be27845400 14381 #define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
AnnaBridge 172:65be27845400 14382 #define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14383
AnnaBridge 172:65be27845400 14384 /*!< MCO1 configuration */
AnnaBridge 172:65be27845400 14385 #define RCC_CFGR_MCO1_Pos (22U)
AnnaBridge 172:65be27845400 14386 #define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
AnnaBridge 172:65be27845400 14387 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */
AnnaBridge 172:65be27845400 14388 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14389 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14390 #define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14391
AnnaBridge 172:65be27845400 14392 #define RCC_CFGR_MCO1PRE_Pos (18U)
AnnaBridge 172:65be27845400 14393 #define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
AnnaBridge 172:65be27845400 14394 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */
AnnaBridge 172:65be27845400 14395 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14396 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 14397 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14398 #define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14399
AnnaBridge 172:65be27845400 14400 #define RCC_CFGR_MCO2PRE_Pos (25U)
AnnaBridge 172:65be27845400 14401 #define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
AnnaBridge 172:65be27845400 14402 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */
AnnaBridge 172:65be27845400 14403 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14404 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 14405 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 14406 #define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 14407
AnnaBridge 172:65be27845400 14408 #define RCC_CFGR_MCO2_Pos (29U)
AnnaBridge 172:65be27845400 14409 #define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
AnnaBridge 172:65be27845400 14410 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */
AnnaBridge 172:65be27845400 14411 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 14412 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 14413 #define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 14414
AnnaBridge 172:65be27845400 14415 /******************** Bit definition for RCC_D1CFGR register ******************/
AnnaBridge 172:65be27845400 14416 /*!< D1HPRE configuration */
AnnaBridge 172:65be27845400 14417 #define RCC_D1CFGR_HPRE_Pos (0U)
AnnaBridge 172:65be27845400 14418 #define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 14419 #define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
AnnaBridge 172:65be27845400 14420 #define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14421 #define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14422 #define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14423 #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14424
AnnaBridge 172:65be27845400 14425
AnnaBridge 172:65be27845400 14426 #define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
AnnaBridge 172:65be27845400 14427 #define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
AnnaBridge 172:65be27845400 14428 #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14429 #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
AnnaBridge 172:65be27845400 14430 #define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
AnnaBridge 172:65be27845400 14431 #define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
AnnaBridge 172:65be27845400 14432 #define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
AnnaBridge 172:65be27845400 14433 #define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
AnnaBridge 172:65be27845400 14434 #define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
AnnaBridge 172:65be27845400 14435 #define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
AnnaBridge 172:65be27845400 14436 #define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
AnnaBridge 172:65be27845400 14437 #define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
AnnaBridge 172:65be27845400 14438 #define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
AnnaBridge 172:65be27845400 14439 #define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
AnnaBridge 172:65be27845400 14440 #define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 14441 #define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
AnnaBridge 172:65be27845400 14442 #define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
AnnaBridge 172:65be27845400 14443 #define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
AnnaBridge 172:65be27845400 14444 #define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
AnnaBridge 172:65be27845400 14445 #define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
AnnaBridge 172:65be27845400 14446 #define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
AnnaBridge 172:65be27845400 14447 #define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
AnnaBridge 172:65be27845400 14448 #define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
AnnaBridge 172:65be27845400 14449 #define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 14450 #define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
AnnaBridge 172:65be27845400 14451
AnnaBridge 172:65be27845400 14452 /*!< D1PPRE configuration */
AnnaBridge 172:65be27845400 14453 #define RCC_D1CFGR_D1PPRE_Pos (4U)
AnnaBridge 172:65be27845400 14454 #define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14455 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits (APB3 prescaler) */
AnnaBridge 172:65be27845400 14456 #define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14457 #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14458 #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14459
AnnaBridge 172:65be27845400 14460 #define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
AnnaBridge 172:65be27845400 14461 #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
AnnaBridge 172:65be27845400 14462 #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14463 #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
AnnaBridge 172:65be27845400 14464 #define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
AnnaBridge 172:65be27845400 14465 #define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
AnnaBridge 172:65be27845400 14466 #define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
AnnaBridge 172:65be27845400 14467 #define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
AnnaBridge 172:65be27845400 14468 #define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 14469 #define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
AnnaBridge 172:65be27845400 14470 #define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
AnnaBridge 172:65be27845400 14471 #define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14472 #define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
AnnaBridge 172:65be27845400 14473
AnnaBridge 172:65be27845400 14474 #define RCC_D1CFGR_D1CPRE_Pos (8U)
AnnaBridge 172:65be27845400 14475 #define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 14476 #define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
AnnaBridge 172:65be27845400 14477 #define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14478 #define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14479 #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14480 #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14481
AnnaBridge 172:65be27845400 14482 #define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
AnnaBridge 172:65be27845400 14483 #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
AnnaBridge 172:65be27845400 14484 #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14485 #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
AnnaBridge 172:65be27845400 14486 #define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
AnnaBridge 172:65be27845400 14487 #define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
AnnaBridge 172:65be27845400 14488 #define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
AnnaBridge 172:65be27845400 14489 #define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
AnnaBridge 172:65be27845400 14490 #define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
AnnaBridge 172:65be27845400 14491 #define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
AnnaBridge 172:65be27845400 14492 #define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
AnnaBridge 172:65be27845400 14493 #define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
AnnaBridge 172:65be27845400 14494 #define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
AnnaBridge 172:65be27845400 14495 #define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
AnnaBridge 172:65be27845400 14496 #define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 14497 #define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
AnnaBridge 172:65be27845400 14498 #define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
AnnaBridge 172:65be27845400 14499 #define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
AnnaBridge 172:65be27845400 14500 #define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
AnnaBridge 172:65be27845400 14501 #define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
AnnaBridge 172:65be27845400 14502 #define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
AnnaBridge 172:65be27845400 14503 #define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
AnnaBridge 172:65be27845400 14504 #define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
AnnaBridge 172:65be27845400 14505 #define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 14506 #define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
AnnaBridge 172:65be27845400 14507
AnnaBridge 172:65be27845400 14508 /******************** Bit definition for RCC_D2CFGR register ******************/
AnnaBridge 172:65be27845400 14509 /*!< D2PPRE1 configuration */
AnnaBridge 172:65be27845400 14510 #define RCC_D2CFGR_D2PPRE1_Pos (4U)
AnnaBridge 172:65be27845400 14511 #define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14512 #define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 172:65be27845400 14513 #define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14514 #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14515 #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14516
AnnaBridge 172:65be27845400 14517 #define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
AnnaBridge 172:65be27845400 14518 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
AnnaBridge 172:65be27845400 14519 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14520 #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
AnnaBridge 172:65be27845400 14521 #define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
AnnaBridge 172:65be27845400 14522 #define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
AnnaBridge 172:65be27845400 14523 #define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
AnnaBridge 172:65be27845400 14524 #define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
AnnaBridge 172:65be27845400 14525 #define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 14526 #define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
AnnaBridge 172:65be27845400 14527 #define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
AnnaBridge 172:65be27845400 14528 #define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14529 #define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
AnnaBridge 172:65be27845400 14530
AnnaBridge 172:65be27845400 14531 /*!< D2PPRE2 configuration */
AnnaBridge 172:65be27845400 14532 #define RCC_D2CFGR_D2PPRE2_Pos (8U)
AnnaBridge 172:65be27845400 14533 #define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 14534 #define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 172:65be27845400 14535 #define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14536 #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14537 #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14538
AnnaBridge 172:65be27845400 14539 #define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
AnnaBridge 172:65be27845400 14540 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
AnnaBridge 172:65be27845400 14541 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14542 #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
AnnaBridge 172:65be27845400 14543 #define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
AnnaBridge 172:65be27845400 14544 #define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
AnnaBridge 172:65be27845400 14545 #define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
AnnaBridge 172:65be27845400 14546 #define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
AnnaBridge 172:65be27845400 14547 #define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
AnnaBridge 172:65be27845400 14548 #define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
AnnaBridge 172:65be27845400 14549 #define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
AnnaBridge 172:65be27845400 14550 #define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 14551 #define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
AnnaBridge 172:65be27845400 14552
AnnaBridge 172:65be27845400 14553 /******************** Bit definition for RCC_D3CFGR register ******************/
AnnaBridge 172:65be27845400 14554 /*!< D3PPRE configuration */
AnnaBridge 172:65be27845400 14555 #define RCC_D3CFGR_D3PPRE_Pos (4U)
AnnaBridge 172:65be27845400 14556 #define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14557 #define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
AnnaBridge 172:65be27845400 14558 #define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14559 #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14560 #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14561
AnnaBridge 172:65be27845400 14562 #define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
AnnaBridge 172:65be27845400 14563 #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
AnnaBridge 172:65be27845400 14564 #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14565 #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
AnnaBridge 172:65be27845400 14566 #define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
AnnaBridge 172:65be27845400 14567 #define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
AnnaBridge 172:65be27845400 14568 #define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
AnnaBridge 172:65be27845400 14569 #define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
AnnaBridge 172:65be27845400 14570 #define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 14571 #define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
AnnaBridge 172:65be27845400 14572 #define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
AnnaBridge 172:65be27845400 14573 #define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 14574 #define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
AnnaBridge 172:65be27845400 14575
AnnaBridge 172:65be27845400 14576 /******************** Bit definition for RCC_PLLCKSELR register *************/
AnnaBridge 172:65be27845400 14577
AnnaBridge 172:65be27845400 14578 #define RCC_PLLCKSELR_PLLSRC_Pos (0U)
AnnaBridge 172:65be27845400 14579 #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 14580 #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
AnnaBridge 172:65be27845400 14581
AnnaBridge 172:65be27845400 14582 #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
AnnaBridge 172:65be27845400 14583 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
AnnaBridge 172:65be27845400 14584 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14585 #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
AnnaBridge 172:65be27845400 14586 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
AnnaBridge 172:65be27845400 14587 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14588 #define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
AnnaBridge 172:65be27845400 14589 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
AnnaBridge 172:65be27845400 14590 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 14591 #define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
AnnaBridge 172:65be27845400 14592
AnnaBridge 172:65be27845400 14593 #define RCC_PLLCKSELR_DIVM1_Pos (4U)
AnnaBridge 172:65be27845400 14594 #define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
AnnaBridge 172:65be27845400 14595 #define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
AnnaBridge 172:65be27845400 14596 #define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14597 #define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14598 #define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14599 #define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14600 #define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14601 #define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14602
AnnaBridge 172:65be27845400 14603 #define RCC_PLLCKSELR_DIVM2_Pos (12U)
AnnaBridge 172:65be27845400 14604 #define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
AnnaBridge 172:65be27845400 14605 #define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
AnnaBridge 172:65be27845400 14606 #define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14607 #define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14608 #define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14609 #define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14610 #define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14611 #define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14612
AnnaBridge 172:65be27845400 14613 #define RCC_PLLCKSELR_DIVM3_Pos (20U)
AnnaBridge 172:65be27845400 14614 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
AnnaBridge 172:65be27845400 14615 #define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
AnnaBridge 172:65be27845400 14616 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14617 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14618 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14619 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14620 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14621 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14622
AnnaBridge 172:65be27845400 14623 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 172:65be27845400 14624
AnnaBridge 172:65be27845400 14625 #define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
AnnaBridge 172:65be27845400 14626 #define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14627 #define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
AnnaBridge 172:65be27845400 14628 #define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
AnnaBridge 172:65be27845400 14629 #define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14630 #define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
AnnaBridge 172:65be27845400 14631 #define RCC_PLLCFGR_PLL1RGE_Pos (2U)
AnnaBridge 172:65be27845400 14632 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 14633 #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
AnnaBridge 172:65be27845400 14634 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 14635 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14636 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14637 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 14638
AnnaBridge 172:65be27845400 14639 #define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
AnnaBridge 172:65be27845400 14640 #define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14641 #define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
AnnaBridge 172:65be27845400 14642 #define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
AnnaBridge 172:65be27845400 14643 #define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14644 #define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
AnnaBridge 172:65be27845400 14645 #define RCC_PLLCFGR_PLL2RGE_Pos (6U)
AnnaBridge 172:65be27845400 14646 #define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 14647 #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
AnnaBridge 172:65be27845400 14648 #define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 14649 #define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14650 #define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14651 #define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 14652
AnnaBridge 172:65be27845400 14653 #define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
AnnaBridge 172:65be27845400 14654 #define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14655 #define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
AnnaBridge 172:65be27845400 14656 #define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
AnnaBridge 172:65be27845400 14657 #define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14658 #define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
AnnaBridge 172:65be27845400 14659 #define RCC_PLLCFGR_PLL3RGE_Pos (10U)
AnnaBridge 172:65be27845400 14660 #define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 14661 #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
AnnaBridge 172:65be27845400 14662 #define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
AnnaBridge 172:65be27845400 14663 #define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14664 #define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14665 #define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 14666
AnnaBridge 172:65be27845400 14667 #define RCC_PLLCFGR_DIVP1EN_Pos (16U)
AnnaBridge 172:65be27845400 14668 #define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14669 #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
AnnaBridge 172:65be27845400 14670 #define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
AnnaBridge 172:65be27845400 14671 #define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14672 #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
AnnaBridge 172:65be27845400 14673 #define RCC_PLLCFGR_DIVR1EN_Pos (18U)
AnnaBridge 172:65be27845400 14674 #define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14675 #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
AnnaBridge 172:65be27845400 14676
AnnaBridge 172:65be27845400 14677 #define RCC_PLLCFGR_DIVP2EN_Pos (19U)
AnnaBridge 172:65be27845400 14678 #define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 14679 #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
AnnaBridge 172:65be27845400 14680 #define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
AnnaBridge 172:65be27845400 14681 #define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14682 #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
AnnaBridge 172:65be27845400 14683 #define RCC_PLLCFGR_DIVR2EN_Pos (21U)
AnnaBridge 172:65be27845400 14684 #define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14685 #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
AnnaBridge 172:65be27845400 14686
AnnaBridge 172:65be27845400 14687 #define RCC_PLLCFGR_DIVP3EN_Pos (22U)
AnnaBridge 172:65be27845400 14688 #define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14689 #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
AnnaBridge 172:65be27845400 14690 #define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
AnnaBridge 172:65be27845400 14691 #define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14692 #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
AnnaBridge 172:65be27845400 14693 #define RCC_PLLCFGR_DIVR3EN_Pos (24U)
AnnaBridge 172:65be27845400 14694 #define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14695 #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
AnnaBridge 172:65be27845400 14696
AnnaBridge 172:65be27845400 14697
AnnaBridge 172:65be27845400 14698 /******************** Bit definition for RCC_PLL1DIVR register ***************/
AnnaBridge 172:65be27845400 14699 #define RCC_PLL1DIVR_N1_Pos (0U)
AnnaBridge 172:65be27845400 14700 #define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 14701 #define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
AnnaBridge 172:65be27845400 14702 #define RCC_PLL1DIVR_P1_Pos (9U)
AnnaBridge 172:65be27845400 14703 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
AnnaBridge 172:65be27845400 14704 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
AnnaBridge 172:65be27845400 14705 #define RCC_PLL1DIVR_Q1_Pos (16U)
AnnaBridge 172:65be27845400 14706 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 14707 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
AnnaBridge 172:65be27845400 14708 #define RCC_PLL1DIVR_R1_Pos (24U)
AnnaBridge 172:65be27845400 14709 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
AnnaBridge 172:65be27845400 14710 #define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
AnnaBridge 172:65be27845400 14711
AnnaBridge 172:65be27845400 14712 /******************** Bit definition for RCC_PLL1FRACR register ***************/
AnnaBridge 172:65be27845400 14713 #define RCC_PLL1FRACR_FRACN1_Pos (3U)
AnnaBridge 172:65be27845400 14714 #define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
AnnaBridge 172:65be27845400 14715 #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
AnnaBridge 172:65be27845400 14716
AnnaBridge 172:65be27845400 14717 /******************** Bit definition for RCC_PLL2DIVR register ***************/
AnnaBridge 172:65be27845400 14718 #define RCC_PLL2DIVR_N2_Pos (0U)
AnnaBridge 172:65be27845400 14719 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 14720 #define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
AnnaBridge 172:65be27845400 14721 #define RCC_PLL2DIVR_P2_Pos (9U)
AnnaBridge 172:65be27845400 14722 #define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
AnnaBridge 172:65be27845400 14723 #define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
AnnaBridge 172:65be27845400 14724 #define RCC_PLL2DIVR_Q2_Pos (16U)
AnnaBridge 172:65be27845400 14725 #define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 14726 #define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
AnnaBridge 172:65be27845400 14727 #define RCC_PLL2DIVR_R2_Pos (24U)
AnnaBridge 172:65be27845400 14728 #define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
AnnaBridge 172:65be27845400 14729 #define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
AnnaBridge 172:65be27845400 14730
AnnaBridge 172:65be27845400 14731 /******************** Bit definition for RCC_PLL2FRACR register ***************/
AnnaBridge 172:65be27845400 14732 #define RCC_PLL2FRACR_FRACN2_Pos (3U)
AnnaBridge 172:65be27845400 14733 #define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
AnnaBridge 172:65be27845400 14734 #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
AnnaBridge 172:65be27845400 14735
AnnaBridge 172:65be27845400 14736 /******************** Bit definition for RCC_PLL3DIVR register ***************/
AnnaBridge 172:65be27845400 14737 #define RCC_PLL3DIVR_N3_Pos (0U)
AnnaBridge 172:65be27845400 14738 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 14739 #define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
AnnaBridge 172:65be27845400 14740 #define RCC_PLL3DIVR_P3_Pos (9U)
AnnaBridge 172:65be27845400 14741 #define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
AnnaBridge 172:65be27845400 14742 #define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
AnnaBridge 172:65be27845400 14743 #define RCC_PLL3DIVR_Q3_Pos (16U)
AnnaBridge 172:65be27845400 14744 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 14745 #define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
AnnaBridge 172:65be27845400 14746 #define RCC_PLL3DIVR_R3_Pos (24U)
AnnaBridge 172:65be27845400 14747 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
AnnaBridge 172:65be27845400 14748 #define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
AnnaBridge 172:65be27845400 14749
AnnaBridge 172:65be27845400 14750 /******************** Bit definition for RCC_PLL3FRACR register ***************/
AnnaBridge 172:65be27845400 14751 #define RCC_PLL3FRACR_FRACN3_Pos (3U)
AnnaBridge 172:65be27845400 14752 #define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
AnnaBridge 172:65be27845400 14753 #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
AnnaBridge 172:65be27845400 14754
AnnaBridge 172:65be27845400 14755 /******************** Bit definition for RCC_D1CCIPR register ***************/
AnnaBridge 172:65be27845400 14756 #define RCC_D1CCIPR_FMCSEL_Pos (0U)
AnnaBridge 172:65be27845400 14757 #define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 14758 #define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
AnnaBridge 172:65be27845400 14759 #define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14760 #define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14761 #define RCC_D1CCIPR_QSPISEL_Pos (4U)
AnnaBridge 172:65be27845400 14762 #define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 14763 #define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
AnnaBridge 172:65be27845400 14764 #define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14765 #define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14766 #define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
AnnaBridge 172:65be27845400 14767 #define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14768 #define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
AnnaBridge 172:65be27845400 14769 #define RCC_D1CCIPR_CKPERSEL_Pos (28U)
AnnaBridge 172:65be27845400 14770 #define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 14771 #define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
AnnaBridge 172:65be27845400 14772 #define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 14773 #define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 14774
AnnaBridge 172:65be27845400 14775 /******************** Bit definition for RCC_D2CCIP1R register ***************/
AnnaBridge 172:65be27845400 14776 #define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
AnnaBridge 172:65be27845400 14777 #define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 14778 #define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
AnnaBridge 172:65be27845400 14779 #define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14780 #define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14781 #define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14782
AnnaBridge 172:65be27845400 14783 #define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
AnnaBridge 172:65be27845400 14784 #define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
AnnaBridge 172:65be27845400 14785 #define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
AnnaBridge 172:65be27845400 14786 #define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14787 #define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14788 #define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14789
AnnaBridge 172:65be27845400 14790 #define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
AnnaBridge 172:65be27845400 14791 #define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 14792 #define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
AnnaBridge 172:65be27845400 14793 #define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14794 #define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14795 #define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14796
AnnaBridge 172:65be27845400 14797 #define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
AnnaBridge 172:65be27845400 14798 #define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 14799 #define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
AnnaBridge 172:65be27845400 14800 #define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14801 #define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14802 #define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 14803
AnnaBridge 172:65be27845400 14804 #define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
AnnaBridge 172:65be27845400 14805 #define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 14806 #define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
AnnaBridge 172:65be27845400 14807 #define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14808 #define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14809
AnnaBridge 172:65be27845400 14810 #define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
AnnaBridge 172:65be27845400 14811 #define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14812 #define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
AnnaBridge 172:65be27845400 14813
AnnaBridge 172:65be27845400 14814 #define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
AnnaBridge 172:65be27845400 14815 #define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 14816 #define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
AnnaBridge 172:65be27845400 14817 #define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 14818 #define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 14819
AnnaBridge 172:65be27845400 14820 #define RCC_D2CCIP1R_SWPSEL_Pos (31U)
AnnaBridge 172:65be27845400 14821 #define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 14822 #define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
AnnaBridge 172:65be27845400 14823
AnnaBridge 172:65be27845400 14824 /******************** Bit definition for RCC_D2CCIP2R register ***************/
AnnaBridge 172:65be27845400 14825 #define RCC_D2CCIP2R_USART16SEL_Pos (3U)
AnnaBridge 172:65be27845400 14826 #define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
AnnaBridge 172:65be27845400 14827 #define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
AnnaBridge 172:65be27845400 14828 #define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14829 #define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14830 #define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14831
AnnaBridge 172:65be27845400 14832 #define RCC_D2CCIP2R_USART28SEL_Pos (0U)
AnnaBridge 172:65be27845400 14833 #define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 14834 #define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
AnnaBridge 172:65be27845400 14835 #define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14836 #define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14837 #define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14838
AnnaBridge 172:65be27845400 14839 #define RCC_D2CCIP2R_RNGSEL_Pos (8U)
AnnaBridge 172:65be27845400 14840 #define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 14841 #define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
AnnaBridge 172:65be27845400 14842 #define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14843 #define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14844
AnnaBridge 172:65be27845400 14845 #define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
AnnaBridge 172:65be27845400 14846 #define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 14847 #define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
AnnaBridge 172:65be27845400 14848 #define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14849 #define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14850
AnnaBridge 172:65be27845400 14851 #define RCC_D2CCIP2R_USBSEL_Pos (20U)
AnnaBridge 172:65be27845400 14852 #define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 14853 #define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
AnnaBridge 172:65be27845400 14854 #define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 14855 #define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14856
AnnaBridge 172:65be27845400 14857 #define RCC_D2CCIP2R_CECSEL_Pos (22U)
AnnaBridge 172:65be27845400 14858 #define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
AnnaBridge 172:65be27845400 14859 #define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
AnnaBridge 172:65be27845400 14860 #define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14861 #define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14862
AnnaBridge 172:65be27845400 14863 #define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
AnnaBridge 172:65be27845400 14864 #define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 14865 #define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
AnnaBridge 172:65be27845400 14866 #define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 14867 #define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 14868 #define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 14869
AnnaBridge 172:65be27845400 14870 /******************** Bit definition for RCC_D3CCIPR register ***************/
AnnaBridge 172:65be27845400 14871 #define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
AnnaBridge 172:65be27845400 14872 #define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 14873 #define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
AnnaBridge 172:65be27845400 14874 #define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14875 #define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14876 #define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14877
AnnaBridge 172:65be27845400 14878 #define RCC_D3CCIPR_I2C4SEL_Pos (8U)
AnnaBridge 172:65be27845400 14879 #define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 14880 #define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
AnnaBridge 172:65be27845400 14881 #define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14882 #define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14883
AnnaBridge 172:65be27845400 14884 #define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
AnnaBridge 172:65be27845400 14885 #define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
AnnaBridge 172:65be27845400 14886 #define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
AnnaBridge 172:65be27845400 14887 #define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14888 #define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 14889 #define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 14890
AnnaBridge 172:65be27845400 14891 #define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
AnnaBridge 172:65be27845400 14892 #define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 14893 #define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
AnnaBridge 172:65be27845400 14894 #define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 14895 #define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 14896 #define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 14897
AnnaBridge 172:65be27845400 14898 #define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
AnnaBridge 172:65be27845400 14899 #define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
AnnaBridge 172:65be27845400 14900 #define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
AnnaBridge 172:65be27845400 14901 #define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 14902 #define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 14903 #define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 14904
AnnaBridge 172:65be27845400 14905 #define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
AnnaBridge 172:65be27845400 14906 #define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 14907 #define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
AnnaBridge 172:65be27845400 14908 #define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 14909 #define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 14910 #define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 14911
AnnaBridge 172:65be27845400 14912 #define RCC_D3CCIPR_ADCSEL_Pos (16U)
AnnaBridge 172:65be27845400 14913 #define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 14914 #define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
AnnaBridge 172:65be27845400 14915 #define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 14916 #define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 14917
AnnaBridge 172:65be27845400 14918 #define RCC_D3CCIPR_SPI6SEL_Pos (28U)
AnnaBridge 172:65be27845400 14919 #define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 14920 #define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
AnnaBridge 172:65be27845400 14921 #define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 14922 #define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 14923 #define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 14924 /******************** Bit definition for RCC_CIER register ******************/
AnnaBridge 172:65be27845400 14925 #define RCC_CIER_LSIRDYIE_Pos (0U)
AnnaBridge 172:65be27845400 14926 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14927 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
AnnaBridge 172:65be27845400 14928 #define RCC_CIER_LSERDYIE_Pos (1U)
AnnaBridge 172:65be27845400 14929 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14930 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
AnnaBridge 172:65be27845400 14931 #define RCC_CIER_HSIRDYIE_Pos (2U)
AnnaBridge 172:65be27845400 14932 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14933 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
AnnaBridge 172:65be27845400 14934 #define RCC_CIER_HSERDYIE_Pos (3U)
AnnaBridge 172:65be27845400 14935 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14936 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
AnnaBridge 172:65be27845400 14937 #define RCC_CIER_CSIRDYIE_Pos (4U)
AnnaBridge 172:65be27845400 14938 #define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14939 #define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
AnnaBridge 172:65be27845400 14940 #define RCC_CIER_HSI48RDYIE_Pos (5U)
AnnaBridge 172:65be27845400 14941 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14942 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
AnnaBridge 172:65be27845400 14943 #define RCC_CIER_PLL1RDYIE_Pos (6U)
AnnaBridge 172:65be27845400 14944 #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14945 #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
AnnaBridge 172:65be27845400 14946 #define RCC_CIER_PLL2RDYIE_Pos (7U)
AnnaBridge 172:65be27845400 14947 #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14948 #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
AnnaBridge 172:65be27845400 14949 #define RCC_CIER_PLL3RDYIE_Pos (8U)
AnnaBridge 172:65be27845400 14950 #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14951 #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
AnnaBridge 172:65be27845400 14952 #define RCC_CIER_LSECSSIE_Pos (9U)
AnnaBridge 172:65be27845400 14953 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14954 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
AnnaBridge 172:65be27845400 14955
AnnaBridge 172:65be27845400 14956 /******************** Bit definition for RCC_CIFR register ******************/
AnnaBridge 172:65be27845400 14957 #define RCC_CIFR_LSIRDYF_Pos (0U)
AnnaBridge 172:65be27845400 14958 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14959 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
AnnaBridge 172:65be27845400 14960 #define RCC_CIFR_LSERDYF_Pos (1U)
AnnaBridge 172:65be27845400 14961 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14962 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
AnnaBridge 172:65be27845400 14963 #define RCC_CIFR_HSIRDYF_Pos (2U)
AnnaBridge 172:65be27845400 14964 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 14965 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
AnnaBridge 172:65be27845400 14966 #define RCC_CIFR_HSERDYF_Pos (3U)
AnnaBridge 172:65be27845400 14967 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 14968 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
AnnaBridge 172:65be27845400 14969 #define RCC_CIFR_CSIRDYF_Pos (4U)
AnnaBridge 172:65be27845400 14970 #define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 14971 #define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
AnnaBridge 172:65be27845400 14972 #define RCC_CIFR_HSI48RDYF_Pos (5U)
AnnaBridge 172:65be27845400 14973 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 14974 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
AnnaBridge 172:65be27845400 14975 #define RCC_CIFR_PLLRDYF_Pos (6U)
AnnaBridge 172:65be27845400 14976 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 14977 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
AnnaBridge 172:65be27845400 14978 #define RCC_CIFR_PLL2RDYF_Pos (7U)
AnnaBridge 172:65be27845400 14979 #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 14980 #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
AnnaBridge 172:65be27845400 14981 #define RCC_CIFR_PLL3RDYF_Pos (8U)
AnnaBridge 172:65be27845400 14982 #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 14983 #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
AnnaBridge 172:65be27845400 14984 #define RCC_CIFR_LSECSSF_Pos (9U)
AnnaBridge 172:65be27845400 14985 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 14986 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
AnnaBridge 172:65be27845400 14987 #define RCC_CIFR_HSECSSF_Pos (10U)
AnnaBridge 172:65be27845400 14988 #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 14989 #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
AnnaBridge 172:65be27845400 14990
AnnaBridge 172:65be27845400 14991 /******************** Bit definition for RCC_CICR register ******************/
AnnaBridge 172:65be27845400 14992 #define RCC_CICR_LSIRDYC_Pos (0U)
AnnaBridge 172:65be27845400 14993 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 14994 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
AnnaBridge 172:65be27845400 14995 #define RCC_CICR_LSERDYC_Pos (1U)
AnnaBridge 172:65be27845400 14996 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 14997 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
AnnaBridge 172:65be27845400 14998 #define RCC_CICR_HSIRDYC_Pos (2U)
AnnaBridge 172:65be27845400 14999 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15000 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
AnnaBridge 172:65be27845400 15001 #define RCC_CICR_HSERDYC_Pos (3U)
AnnaBridge 172:65be27845400 15002 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15003 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
AnnaBridge 172:65be27845400 15004 #define RCC_CICR_CSIRDYC_Pos (4U)
AnnaBridge 172:65be27845400 15005 #define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15006 #define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
AnnaBridge 172:65be27845400 15007 #define RCC_CICR_HSI48RDYC_Pos (5U)
AnnaBridge 172:65be27845400 15008 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15009 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
AnnaBridge 172:65be27845400 15010 #define RCC_CICR_PLLRDYC_Pos (6U)
AnnaBridge 172:65be27845400 15011 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15012 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
AnnaBridge 172:65be27845400 15013 #define RCC_CICR_PLL2RDYC_Pos (7U)
AnnaBridge 172:65be27845400 15014 #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15015 #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
AnnaBridge 172:65be27845400 15016 #define RCC_CICR_PLL3RDYC_Pos (8U)
AnnaBridge 172:65be27845400 15017 #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15018 #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
AnnaBridge 172:65be27845400 15019 #define RCC_CICR_LSECSSC_Pos (9U)
AnnaBridge 172:65be27845400 15020 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15021 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
AnnaBridge 172:65be27845400 15022 #define RCC_CICR_HSECSSC_Pos (10U)
AnnaBridge 172:65be27845400 15023 #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15024 #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
AnnaBridge 172:65be27845400 15025
AnnaBridge 172:65be27845400 15026 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 172:65be27845400 15027 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 172:65be27845400 15028 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15029 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 172:65be27845400 15030 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 172:65be27845400 15031 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15032 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 172:65be27845400 15033 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 172:65be27845400 15034 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15035 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 172:65be27845400 15036
AnnaBridge 172:65be27845400 15037 #define RCC_BDCR_LSEDRV_Pos (3U)
AnnaBridge 172:65be27845400 15038 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 15039 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
AnnaBridge 172:65be27845400 15040 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15041 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15042
AnnaBridge 172:65be27845400 15043 #define RCC_BDCR_LSECSSON_Pos (5U)
AnnaBridge 172:65be27845400 15044 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15045 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
AnnaBridge 172:65be27845400 15046 #define RCC_BDCR_LSECSSD_Pos (6U)
AnnaBridge 172:65be27845400 15047 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15048 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
AnnaBridge 172:65be27845400 15049
AnnaBridge 172:65be27845400 15050 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 172:65be27845400 15051 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 15052 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 172:65be27845400 15053 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15054 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15055
AnnaBridge 172:65be27845400 15056 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 172:65be27845400 15057 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15058 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 172:65be27845400 15059 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 172:65be27845400 15060 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15061 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
AnnaBridge 172:65be27845400 15062 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 172:65be27845400 15063 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 172:65be27845400 15064 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15065 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 172:65be27845400 15066 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 172:65be27845400 15067 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15068 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 172:65be27845400 15069
AnnaBridge 172:65be27845400 15070
AnnaBridge 172:65be27845400 15071 /******************** Bit definition for RCC_AHB3ENR register **************/
AnnaBridge 172:65be27845400 15072 #define RCC_AHB3ENR_MDMAEN_Pos (0U)
AnnaBridge 172:65be27845400 15073 #define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15074 #define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
AnnaBridge 172:65be27845400 15075 #define RCC_AHB3ENR_DMA2DEN_Pos (4U)
AnnaBridge 172:65be27845400 15076 #define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15077 #define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
AnnaBridge 172:65be27845400 15078 #define RCC_AHB3ENR_JPGDECEN_Pos (5U)
AnnaBridge 172:65be27845400 15079 #define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15080 #define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
AnnaBridge 172:65be27845400 15081 #define RCC_AHB3ENR_FMCEN_Pos (12U)
AnnaBridge 172:65be27845400 15082 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15083 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
AnnaBridge 172:65be27845400 15084 #define RCC_AHB3ENR_QSPIEN_Pos (14U)
AnnaBridge 172:65be27845400 15085 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15086 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
AnnaBridge 172:65be27845400 15087 #define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
AnnaBridge 172:65be27845400 15088 #define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15089 #define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
AnnaBridge 172:65be27845400 15090
AnnaBridge 172:65be27845400 15091 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 172:65be27845400 15092 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
AnnaBridge 172:65be27845400 15093 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15094 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 172:65be27845400 15095 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
AnnaBridge 172:65be27845400 15096 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15097 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 172:65be27845400 15098 #define RCC_AHB1ENR_ADC12EN_Pos (5U)
AnnaBridge 172:65be27845400 15099 #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15100 #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
AnnaBridge 172:65be27845400 15101 #define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
AnnaBridge 172:65be27845400 15102 #define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15103 #define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
AnnaBridge 172:65be27845400 15104 #define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
AnnaBridge 172:65be27845400 15105 #define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15106 #define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
AnnaBridge 172:65be27845400 15107 #define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
AnnaBridge 172:65be27845400 15108 #define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15109 #define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
AnnaBridge 172:65be27845400 15110 #define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
AnnaBridge 172:65be27845400 15111 #define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15112 #define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
AnnaBridge 172:65be27845400 15113 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
AnnaBridge 172:65be27845400 15114 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 15115 #define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
AnnaBridge 172:65be27845400 15116 #define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
AnnaBridge 172:65be27845400 15117 #define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15118 #define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
AnnaBridge 172:65be27845400 15119
AnnaBridge 172:65be27845400 15120 /* Legacy define */
AnnaBridge 172:65be27845400 15121 #define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
AnnaBridge 172:65be27845400 15122 #define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
AnnaBridge 172:65be27845400 15123 #define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
AnnaBridge 172:65be27845400 15124
AnnaBridge 172:65be27845400 15125 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 172:65be27845400 15126 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
AnnaBridge 172:65be27845400 15127 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15128 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
AnnaBridge 172:65be27845400 15129 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
AnnaBridge 172:65be27845400 15130 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15131 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
AnnaBridge 172:65be27845400 15132 #define RCC_AHB2ENR_HASHEN_Pos (5U)
AnnaBridge 172:65be27845400 15133 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15134 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
AnnaBridge 172:65be27845400 15135 #define RCC_AHB2ENR_RNGEN_Pos (6U)
AnnaBridge 172:65be27845400 15136 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15137 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
AnnaBridge 172:65be27845400 15138 #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
AnnaBridge 172:65be27845400 15139 #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15140 #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
AnnaBridge 172:65be27845400 15141 #define RCC_AHB2ENR_D2SRAM1EN_Pos (29U)
AnnaBridge 172:65be27845400 15142 #define RCC_AHB2ENR_D2SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM1EN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15143 #define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_D2SRAM1EN_Msk
AnnaBridge 172:65be27845400 15144 #define RCC_AHB2ENR_D2SRAM2EN_Pos (30U)
AnnaBridge 172:65be27845400 15145 #define RCC_AHB2ENR_D2SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM2EN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15146 #define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_D2SRAM2EN_Msk
AnnaBridge 172:65be27845400 15147 #define RCC_AHB2ENR_D2SRAM3EN_Pos (31U)
AnnaBridge 172:65be27845400 15148 #define RCC_AHB2ENR_D2SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_D2SRAM3EN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15149 #define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_D2SRAM3EN_Msk
AnnaBridge 172:65be27845400 15150
AnnaBridge 172:65be27845400 15151
AnnaBridge 172:65be27845400 15152 /******************** Bit definition for RCC_AHB4ENR register ******************/
AnnaBridge 172:65be27845400 15153 #define RCC_AHB4ENR_GPIOAEN_Pos (0U)
AnnaBridge 172:65be27845400 15154 #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15155 #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
AnnaBridge 172:65be27845400 15156 #define RCC_AHB4ENR_GPIOBEN_Pos (1U)
AnnaBridge 172:65be27845400 15157 #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15158 #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
AnnaBridge 172:65be27845400 15159 #define RCC_AHB4ENR_GPIOCEN_Pos (2U)
AnnaBridge 172:65be27845400 15160 #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15161 #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
AnnaBridge 172:65be27845400 15162 #define RCC_AHB4ENR_GPIODEN_Pos (3U)
AnnaBridge 172:65be27845400 15163 #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15164 #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
AnnaBridge 172:65be27845400 15165 #define RCC_AHB4ENR_GPIOEEN_Pos (4U)
AnnaBridge 172:65be27845400 15166 #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15167 #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
AnnaBridge 172:65be27845400 15168 #define RCC_AHB4ENR_GPIOFEN_Pos (5U)
AnnaBridge 172:65be27845400 15169 #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15170 #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
AnnaBridge 172:65be27845400 15171 #define RCC_AHB4ENR_GPIOGEN_Pos (6U)
AnnaBridge 172:65be27845400 15172 #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15173 #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
AnnaBridge 172:65be27845400 15174 #define RCC_AHB4ENR_GPIOHEN_Pos (7U)
AnnaBridge 172:65be27845400 15175 #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15176 #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
AnnaBridge 172:65be27845400 15177 #define RCC_AHB4ENR_GPIOIEN_Pos (8U)
AnnaBridge 172:65be27845400 15178 #define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15179 #define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
AnnaBridge 172:65be27845400 15180 #define RCC_AHB4ENR_GPIOJEN_Pos (9U)
AnnaBridge 172:65be27845400 15181 #define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15182 #define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
AnnaBridge 172:65be27845400 15183 #define RCC_AHB4ENR_GPIOKEN_Pos (10U)
AnnaBridge 172:65be27845400 15184 #define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15185 #define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
AnnaBridge 172:65be27845400 15186 #define RCC_AHB4ENR_CRCEN_Pos (19U)
AnnaBridge 172:65be27845400 15187 #define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15188 #define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
AnnaBridge 172:65be27845400 15189 #define RCC_AHB4ENR_BDMAEN_Pos (21U)
AnnaBridge 172:65be27845400 15190 #define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15191 #define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
AnnaBridge 172:65be27845400 15192 #define RCC_AHB4ENR_ADC3EN_Pos (24U)
AnnaBridge 172:65be27845400 15193 #define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15194 #define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
AnnaBridge 172:65be27845400 15195 #define RCC_AHB4ENR_HSEMEN_Pos (25U)
AnnaBridge 172:65be27845400 15196 #define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15197 #define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
AnnaBridge 172:65be27845400 15198 #define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
AnnaBridge 172:65be27845400 15199 #define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15200 #define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
AnnaBridge 172:65be27845400 15201 #define RCC_AHB4ENR_D3SRAM1EN_Pos (29U)
AnnaBridge 172:65be27845400 15202 #define RCC_AHB4ENR_D3SRAM1EN_Msk (0x1UL << RCC_AHB4ENR_D3SRAM1EN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15203 #define RCC_AHB4ENR_D3SRAM1EN RCC_AHB4ENR_D3SRAM1EN_Msk
AnnaBridge 172:65be27845400 15204
AnnaBridge 172:65be27845400 15205 /******************** Bit definition for RCC_APB3ENR register ******************/
AnnaBridge 172:65be27845400 15206
AnnaBridge 172:65be27845400 15207 #define RCC_APB3ENR_LTDCEN_Pos (3U)
AnnaBridge 172:65be27845400 15208 #define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15209 #define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
AnnaBridge 172:65be27845400 15210 #define RCC_APB3ENR_WWDG1EN_Pos (6U)
AnnaBridge 172:65be27845400 15211 #define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15212 #define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
AnnaBridge 172:65be27845400 15213
AnnaBridge 172:65be27845400 15214 /******************** Bit definition for RCC_APB1LENR register ******************/
AnnaBridge 172:65be27845400 15215
AnnaBridge 172:65be27845400 15216 #define RCC_APB1LENR_TIM2EN_Pos (0U)
AnnaBridge 172:65be27845400 15217 #define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15218 #define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
AnnaBridge 172:65be27845400 15219 #define RCC_APB1LENR_TIM3EN_Pos (1U)
AnnaBridge 172:65be27845400 15220 #define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15221 #define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
AnnaBridge 172:65be27845400 15222 #define RCC_APB1LENR_TIM4EN_Pos (2U)
AnnaBridge 172:65be27845400 15223 #define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15224 #define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
AnnaBridge 172:65be27845400 15225 #define RCC_APB1LENR_TIM5EN_Pos (3U)
AnnaBridge 172:65be27845400 15226 #define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15227 #define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
AnnaBridge 172:65be27845400 15228 #define RCC_APB1LENR_TIM6EN_Pos (4U)
AnnaBridge 172:65be27845400 15229 #define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15230 #define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
AnnaBridge 172:65be27845400 15231 #define RCC_APB1LENR_TIM7EN_Pos (5U)
AnnaBridge 172:65be27845400 15232 #define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15233 #define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
AnnaBridge 172:65be27845400 15234 #define RCC_APB1LENR_TIM12EN_Pos (6U)
AnnaBridge 172:65be27845400 15235 #define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15236 #define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
AnnaBridge 172:65be27845400 15237 #define RCC_APB1LENR_TIM13EN_Pos (7U)
AnnaBridge 172:65be27845400 15238 #define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15239 #define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
AnnaBridge 172:65be27845400 15240 #define RCC_APB1LENR_TIM14EN_Pos (8U)
AnnaBridge 172:65be27845400 15241 #define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15242 #define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
AnnaBridge 172:65be27845400 15243 #define RCC_APB1LENR_LPTIM1EN_Pos (9U)
AnnaBridge 172:65be27845400 15244 #define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15245 #define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
AnnaBridge 172:65be27845400 15246
AnnaBridge 172:65be27845400 15247
AnnaBridge 172:65be27845400 15248 #define RCC_APB1LENR_SPI2EN_Pos (14U)
AnnaBridge 172:65be27845400 15249 #define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15250 #define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
AnnaBridge 172:65be27845400 15251 #define RCC_APB1LENR_SPI3EN_Pos (15U)
AnnaBridge 172:65be27845400 15252 #define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15253 #define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
AnnaBridge 172:65be27845400 15254 #define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
AnnaBridge 172:65be27845400 15255 #define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15256 #define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
AnnaBridge 172:65be27845400 15257 #define RCC_APB1LENR_USART2EN_Pos (17U)
AnnaBridge 172:65be27845400 15258 #define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15259 #define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
AnnaBridge 172:65be27845400 15260 #define RCC_APB1LENR_USART3EN_Pos (18U)
AnnaBridge 172:65be27845400 15261 #define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15262 #define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
AnnaBridge 172:65be27845400 15263 #define RCC_APB1LENR_UART4EN_Pos (19U)
AnnaBridge 172:65be27845400 15264 #define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15265 #define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
AnnaBridge 172:65be27845400 15266 #define RCC_APB1LENR_UART5EN_Pos (20U)
AnnaBridge 172:65be27845400 15267 #define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15268 #define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
AnnaBridge 172:65be27845400 15269 #define RCC_APB1LENR_I2C1EN_Pos (21U)
AnnaBridge 172:65be27845400 15270 #define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15271 #define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
AnnaBridge 172:65be27845400 15272 #define RCC_APB1LENR_I2C2EN_Pos (22U)
AnnaBridge 172:65be27845400 15273 #define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 15274 #define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
AnnaBridge 172:65be27845400 15275 #define RCC_APB1LENR_I2C3EN_Pos (23U)
AnnaBridge 172:65be27845400 15276 #define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15277 #define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
AnnaBridge 172:65be27845400 15278 #define RCC_APB1LENR_CECEN_Pos (27U)
AnnaBridge 172:65be27845400 15279 #define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15280 #define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
AnnaBridge 172:65be27845400 15281 #define RCC_APB1LENR_DAC12EN_Pos (29U)
AnnaBridge 172:65be27845400 15282 #define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15283 #define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
AnnaBridge 172:65be27845400 15284 #define RCC_APB1LENR_UART7EN_Pos (30U)
AnnaBridge 172:65be27845400 15285 #define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15286 #define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
AnnaBridge 172:65be27845400 15287 #define RCC_APB1LENR_UART8EN_Pos (31U)
AnnaBridge 172:65be27845400 15288 #define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15289 #define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
AnnaBridge 172:65be27845400 15290
AnnaBridge 172:65be27845400 15291 /******************** Bit definition for RCC_APB1HENR register ******************/
AnnaBridge 172:65be27845400 15292 #define RCC_APB1HENR_CRSEN_Pos (1U)
AnnaBridge 172:65be27845400 15293 #define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15294 #define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
AnnaBridge 172:65be27845400 15295 #define RCC_APB1HENR_SWPMIEN_Pos (2U)
AnnaBridge 172:65be27845400 15296 #define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15297 #define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
AnnaBridge 172:65be27845400 15298 #define RCC_APB1HENR_OPAMPEN_Pos (4U)
AnnaBridge 172:65be27845400 15299 #define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15300 #define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
AnnaBridge 172:65be27845400 15301 #define RCC_APB1HENR_MDIOSEN_Pos (5U)
AnnaBridge 172:65be27845400 15302 #define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15303 #define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
AnnaBridge 172:65be27845400 15304 #define RCC_APB1HENR_FDCANEN_Pos (8U)
AnnaBridge 172:65be27845400 15305 #define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15306 #define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
AnnaBridge 172:65be27845400 15307
AnnaBridge 172:65be27845400 15308 /******************** Bit definition for RCC_APB2ENR register ******************/
AnnaBridge 172:65be27845400 15309 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 172:65be27845400 15310 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15311 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 172:65be27845400 15312 #define RCC_APB2ENR_TIM8EN_Pos (1U)
AnnaBridge 172:65be27845400 15313 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15314 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
AnnaBridge 172:65be27845400 15315 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 172:65be27845400 15316 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15317 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 172:65be27845400 15318 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 172:65be27845400 15319 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15320 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 172:65be27845400 15321 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 172:65be27845400 15322 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15323 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 172:65be27845400 15324 #define RCC_APB2ENR_SPI4EN_Pos (13U)
AnnaBridge 172:65be27845400 15325 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 15326 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
AnnaBridge 172:65be27845400 15327 #define RCC_APB2ENR_TIM15EN_Pos (16U)
AnnaBridge 172:65be27845400 15328 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15329 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
AnnaBridge 172:65be27845400 15330 #define RCC_APB2ENR_TIM16EN_Pos (17U)
AnnaBridge 172:65be27845400 15331 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15332 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
AnnaBridge 172:65be27845400 15333 #define RCC_APB2ENR_TIM17EN_Pos (18U)
AnnaBridge 172:65be27845400 15334 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15335 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
AnnaBridge 172:65be27845400 15336 #define RCC_APB2ENR_SPI5EN_Pos (20U)
AnnaBridge 172:65be27845400 15337 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15338 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
AnnaBridge 172:65be27845400 15339 #define RCC_APB2ENR_SAI1EN_Pos (22U)
AnnaBridge 172:65be27845400 15340 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 15341 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
AnnaBridge 172:65be27845400 15342 #define RCC_APB2ENR_SAI2EN_Pos (23U)
AnnaBridge 172:65be27845400 15343 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15344 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
AnnaBridge 172:65be27845400 15345 #define RCC_APB2ENR_SAI3EN_Pos (24U)
AnnaBridge 172:65be27845400 15346 #define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15347 #define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
AnnaBridge 172:65be27845400 15348 #define RCC_APB2ENR_DFSDM1EN_Pos (28U)
AnnaBridge 172:65be27845400 15349 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15350 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
AnnaBridge 172:65be27845400 15351 #define RCC_APB2ENR_HRTIMEN_Pos (29U)
AnnaBridge 172:65be27845400 15352 #define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15353 #define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
AnnaBridge 172:65be27845400 15354
AnnaBridge 172:65be27845400 15355 /******************** Bit definition for RCC_APB4ENR register ******************/
AnnaBridge 172:65be27845400 15356 #define RCC_APB4ENR_SYSCFGEN_Pos (1U)
AnnaBridge 172:65be27845400 15357 #define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15358 #define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
AnnaBridge 172:65be27845400 15359 #define RCC_APB4ENR_LPUART1EN_Pos (3U)
AnnaBridge 172:65be27845400 15360 #define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15361 #define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
AnnaBridge 172:65be27845400 15362 #define RCC_APB4ENR_SPI6EN_Pos (5U)
AnnaBridge 172:65be27845400 15363 #define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15364 #define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
AnnaBridge 172:65be27845400 15365 #define RCC_APB4ENR_I2C4EN_Pos (7U)
AnnaBridge 172:65be27845400 15366 #define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15367 #define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
AnnaBridge 172:65be27845400 15368 #define RCC_APB4ENR_LPTIM2EN_Pos (9U)
AnnaBridge 172:65be27845400 15369 #define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15370 #define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
AnnaBridge 172:65be27845400 15371 #define RCC_APB4ENR_LPTIM3EN_Pos (10U)
AnnaBridge 172:65be27845400 15372 #define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15373 #define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
AnnaBridge 172:65be27845400 15374 #define RCC_APB4ENR_LPTIM4EN_Pos (11U)
AnnaBridge 172:65be27845400 15375 #define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15376 #define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
AnnaBridge 172:65be27845400 15377 #define RCC_APB4ENR_LPTIM5EN_Pos (12U)
AnnaBridge 172:65be27845400 15378 #define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15379 #define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
AnnaBridge 172:65be27845400 15380 #define RCC_APB4ENR_COMP12EN_Pos (14U)
AnnaBridge 172:65be27845400 15381 #define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15382 #define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
AnnaBridge 172:65be27845400 15383 #define RCC_APB4ENR_VREFEN_Pos (15U)
AnnaBridge 172:65be27845400 15384 #define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15385 #define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
AnnaBridge 172:65be27845400 15386 #define RCC_APB4ENR_RTCAPBEN_Pos (16U)
AnnaBridge 172:65be27845400 15387 #define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15388 #define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
AnnaBridge 172:65be27845400 15389 #define RCC_APB4ENR_SAI4EN_Pos (21U)
AnnaBridge 172:65be27845400 15390 #define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15391 #define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
AnnaBridge 172:65be27845400 15392
AnnaBridge 172:65be27845400 15393
AnnaBridge 172:65be27845400 15394 /******************** Bit definition for RCC_AHB3RSTR register ***************/
AnnaBridge 172:65be27845400 15395 #define RCC_AHB3RSTR_MDMARST_Pos (0U)
AnnaBridge 172:65be27845400 15396 #define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15397 #define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
AnnaBridge 172:65be27845400 15398 #define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
AnnaBridge 172:65be27845400 15399 #define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15400 #define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
AnnaBridge 172:65be27845400 15401 #define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
AnnaBridge 172:65be27845400 15402 #define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15403 #define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
AnnaBridge 172:65be27845400 15404 #define RCC_AHB3RSTR_FMCRST_Pos (12U)
AnnaBridge 172:65be27845400 15405 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15406 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
AnnaBridge 172:65be27845400 15407 #define RCC_AHB3RSTR_QSPIRST_Pos (14U)
AnnaBridge 172:65be27845400 15408 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15409 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
AnnaBridge 172:65be27845400 15410 #define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
AnnaBridge 172:65be27845400 15411 #define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15412 #define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
AnnaBridge 172:65be27845400 15413
AnnaBridge 172:65be27845400 15414
AnnaBridge 172:65be27845400 15415 /******************** Bit definition for RCC_AHB1RSTR register ***************/
AnnaBridge 172:65be27845400 15416 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
AnnaBridge 172:65be27845400 15417 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15418 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 172:65be27845400 15419 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
AnnaBridge 172:65be27845400 15420 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15421 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 172:65be27845400 15422 #define RCC_AHB1RSTR_ADC12RST_Pos (5U)
AnnaBridge 172:65be27845400 15423 #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15424 #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
AnnaBridge 172:65be27845400 15425 #define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
AnnaBridge 172:65be27845400 15426 #define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15427 #define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
AnnaBridge 172:65be27845400 15428 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
AnnaBridge 172:65be27845400 15429 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15430 #define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
AnnaBridge 172:65be27845400 15431 #define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
AnnaBridge 172:65be27845400 15432 #define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15433 #define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
AnnaBridge 172:65be27845400 15434
AnnaBridge 172:65be27845400 15435 /* Legacy define */
AnnaBridge 172:65be27845400 15436 #define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
AnnaBridge 172:65be27845400 15437 #define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
AnnaBridge 172:65be27845400 15438 #define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
AnnaBridge 172:65be27845400 15439
AnnaBridge 172:65be27845400 15440 /******************** Bit definition for RCC_AHB2RSTR register ***************/
AnnaBridge 172:65be27845400 15441 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
AnnaBridge 172:65be27845400 15442 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15443 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
AnnaBridge 172:65be27845400 15444 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
AnnaBridge 172:65be27845400 15445 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15446 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
AnnaBridge 172:65be27845400 15447 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
AnnaBridge 172:65be27845400 15448 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15449 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
AnnaBridge 172:65be27845400 15450 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
AnnaBridge 172:65be27845400 15451 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15452 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
AnnaBridge 172:65be27845400 15453 #define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
AnnaBridge 172:65be27845400 15454 #define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15455 #define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
AnnaBridge 172:65be27845400 15456
AnnaBridge 172:65be27845400 15457 /******************** Bit definition for RCC_AHB4RSTR register ******************/
AnnaBridge 172:65be27845400 15458 #define RCC_AHB4RSTR_GPIOARST_Pos (0U)
AnnaBridge 172:65be27845400 15459 #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15460 #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
AnnaBridge 172:65be27845400 15461 #define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
AnnaBridge 172:65be27845400 15462 #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15463 #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
AnnaBridge 172:65be27845400 15464 #define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
AnnaBridge 172:65be27845400 15465 #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15466 #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
AnnaBridge 172:65be27845400 15467 #define RCC_AHB4RSTR_GPIODRST_Pos (3U)
AnnaBridge 172:65be27845400 15468 #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15469 #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
AnnaBridge 172:65be27845400 15470 #define RCC_AHB4RSTR_GPIOERST_Pos (4U)
AnnaBridge 172:65be27845400 15471 #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15472 #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
AnnaBridge 172:65be27845400 15473 #define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
AnnaBridge 172:65be27845400 15474 #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15475 #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
AnnaBridge 172:65be27845400 15476 #define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
AnnaBridge 172:65be27845400 15477 #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15478 #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
AnnaBridge 172:65be27845400 15479 #define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
AnnaBridge 172:65be27845400 15480 #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15481 #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
AnnaBridge 172:65be27845400 15482 #define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
AnnaBridge 172:65be27845400 15483 #define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15484 #define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
AnnaBridge 172:65be27845400 15485 #define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
AnnaBridge 172:65be27845400 15486 #define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15487 #define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
AnnaBridge 172:65be27845400 15488 #define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
AnnaBridge 172:65be27845400 15489 #define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15490 #define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
AnnaBridge 172:65be27845400 15491 #define RCC_AHB4RSTR_CRCRST_Pos (19U)
AnnaBridge 172:65be27845400 15492 #define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15493 #define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
AnnaBridge 172:65be27845400 15494 #define RCC_AHB4RSTR_BDMARST_Pos (21U)
AnnaBridge 172:65be27845400 15495 #define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15496 #define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
AnnaBridge 172:65be27845400 15497 #define RCC_AHB4RSTR_ADC3RST_Pos (24U)
AnnaBridge 172:65be27845400 15498 #define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15499 #define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
AnnaBridge 172:65be27845400 15500 #define RCC_AHB4RSTR_HSEMRST_Pos (25U)
AnnaBridge 172:65be27845400 15501 #define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15502 #define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
AnnaBridge 172:65be27845400 15503
AnnaBridge 172:65be27845400 15504
AnnaBridge 172:65be27845400 15505 /******************** Bit definition for RCC_APB3RSTR register ******************/
AnnaBridge 172:65be27845400 15506
AnnaBridge 172:65be27845400 15507 #define RCC_APB3RSTR_LTDCRST_Pos (3U)
AnnaBridge 172:65be27845400 15508 #define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15509 #define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
AnnaBridge 172:65be27845400 15510
AnnaBridge 172:65be27845400 15511 /******************** Bit definition for RCC_APB1LRSTR register ******************/
AnnaBridge 172:65be27845400 15512
AnnaBridge 172:65be27845400 15513 #define RCC_APB1LRSTR_TIM2RST_Pos (0U)
AnnaBridge 172:65be27845400 15514 #define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15515 #define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
AnnaBridge 172:65be27845400 15516 #define RCC_APB1LRSTR_TIM3RST_Pos (1U)
AnnaBridge 172:65be27845400 15517 #define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15518 #define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
AnnaBridge 172:65be27845400 15519 #define RCC_APB1LRSTR_TIM4RST_Pos (2U)
AnnaBridge 172:65be27845400 15520 #define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15521 #define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
AnnaBridge 172:65be27845400 15522 #define RCC_APB1LRSTR_TIM5RST_Pos (3U)
AnnaBridge 172:65be27845400 15523 #define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15524 #define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
AnnaBridge 172:65be27845400 15525 #define RCC_APB1LRSTR_TIM6RST_Pos (4U)
AnnaBridge 172:65be27845400 15526 #define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15527 #define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
AnnaBridge 172:65be27845400 15528 #define RCC_APB1LRSTR_TIM7RST_Pos (5U)
AnnaBridge 172:65be27845400 15529 #define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15530 #define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
AnnaBridge 172:65be27845400 15531 #define RCC_APB1LRSTR_TIM12RST_Pos (6U)
AnnaBridge 172:65be27845400 15532 #define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15533 #define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
AnnaBridge 172:65be27845400 15534 #define RCC_APB1LRSTR_TIM13RST_Pos (7U)
AnnaBridge 172:65be27845400 15535 #define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15536 #define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
AnnaBridge 172:65be27845400 15537 #define RCC_APB1LRSTR_TIM14RST_Pos (8U)
AnnaBridge 172:65be27845400 15538 #define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15539 #define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
AnnaBridge 172:65be27845400 15540 #define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
AnnaBridge 172:65be27845400 15541 #define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15542 #define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
AnnaBridge 172:65be27845400 15543 #define RCC_APB1LRSTR_SPI2RST_Pos (14U)
AnnaBridge 172:65be27845400 15544 #define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15545 #define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
AnnaBridge 172:65be27845400 15546 #define RCC_APB1LRSTR_SPI3RST_Pos (15U)
AnnaBridge 172:65be27845400 15547 #define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15548 #define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
AnnaBridge 172:65be27845400 15549 #define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
AnnaBridge 172:65be27845400 15550 #define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15551 #define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
AnnaBridge 172:65be27845400 15552 #define RCC_APB1LRSTR_USART2RST_Pos (17U)
AnnaBridge 172:65be27845400 15553 #define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15554 #define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
AnnaBridge 172:65be27845400 15555 #define RCC_APB1LRSTR_USART3RST_Pos (18U)
AnnaBridge 172:65be27845400 15556 #define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15557 #define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
AnnaBridge 172:65be27845400 15558 #define RCC_APB1LRSTR_UART4RST_Pos (19U)
AnnaBridge 172:65be27845400 15559 #define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15560 #define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
AnnaBridge 172:65be27845400 15561 #define RCC_APB1LRSTR_UART5RST_Pos (20U)
AnnaBridge 172:65be27845400 15562 #define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15563 #define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
AnnaBridge 172:65be27845400 15564 #define RCC_APB1LRSTR_I2C1RST_Pos (21U)
AnnaBridge 172:65be27845400 15565 #define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15566 #define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
AnnaBridge 172:65be27845400 15567 #define RCC_APB1LRSTR_I2C2RST_Pos (22U)
AnnaBridge 172:65be27845400 15568 #define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 15569 #define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
AnnaBridge 172:65be27845400 15570 #define RCC_APB1LRSTR_I2C3RST_Pos (23U)
AnnaBridge 172:65be27845400 15571 #define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15572 #define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
AnnaBridge 172:65be27845400 15573 #define RCC_APB1LRSTR_CECRST_Pos (27U)
AnnaBridge 172:65be27845400 15574 #define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15575 #define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
AnnaBridge 172:65be27845400 15576 #define RCC_APB1LRSTR_DAC12RST_Pos (29U)
AnnaBridge 172:65be27845400 15577 #define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15578 #define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
AnnaBridge 172:65be27845400 15579 #define RCC_APB1LRSTR_UART7RST_Pos (30U)
AnnaBridge 172:65be27845400 15580 #define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15581 #define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
AnnaBridge 172:65be27845400 15582 #define RCC_APB1LRSTR_UART8RST_Pos (31U)
AnnaBridge 172:65be27845400 15583 #define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15584 #define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
AnnaBridge 172:65be27845400 15585
AnnaBridge 172:65be27845400 15586 /******************** Bit definition for RCC_APB1HRSTR register ******************/
AnnaBridge 172:65be27845400 15587 #define RCC_APB1HRSTR_CRSRST_Pos (1U)
AnnaBridge 172:65be27845400 15588 #define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15589 #define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
AnnaBridge 172:65be27845400 15590 #define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
AnnaBridge 172:65be27845400 15591 #define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15592 #define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
AnnaBridge 172:65be27845400 15593 #define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
AnnaBridge 172:65be27845400 15594 #define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15595 #define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
AnnaBridge 172:65be27845400 15596 #define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
AnnaBridge 172:65be27845400 15597 #define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15598 #define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
AnnaBridge 172:65be27845400 15599 #define RCC_APB1HRSTR_FDCANRST_Pos (8U)
AnnaBridge 172:65be27845400 15600 #define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15601 #define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
AnnaBridge 172:65be27845400 15602
AnnaBridge 172:65be27845400 15603 /******************** Bit definition for RCC_APB2RSTR register ******************/
AnnaBridge 172:65be27845400 15604 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 172:65be27845400 15605 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15606 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 172:65be27845400 15607 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
AnnaBridge 172:65be27845400 15608 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15609 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
AnnaBridge 172:65be27845400 15610 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 172:65be27845400 15611 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15612 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 172:65be27845400 15613 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 172:65be27845400 15614 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15615 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 172:65be27845400 15616 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 172:65be27845400 15617 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15618 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 172:65be27845400 15619 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
AnnaBridge 172:65be27845400 15620 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 15621 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
AnnaBridge 172:65be27845400 15622 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
AnnaBridge 172:65be27845400 15623 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15624 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
AnnaBridge 172:65be27845400 15625 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
AnnaBridge 172:65be27845400 15626 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15627 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
AnnaBridge 172:65be27845400 15628 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
AnnaBridge 172:65be27845400 15629 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15630 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
AnnaBridge 172:65be27845400 15631 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
AnnaBridge 172:65be27845400 15632 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15633 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
AnnaBridge 172:65be27845400 15634 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
AnnaBridge 172:65be27845400 15635 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 15636 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
AnnaBridge 172:65be27845400 15637 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
AnnaBridge 172:65be27845400 15638 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15639 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
AnnaBridge 172:65be27845400 15640 #define RCC_APB2RSTR_SAI3RST_Pos (24U)
AnnaBridge 172:65be27845400 15641 #define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15642 #define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
AnnaBridge 172:65be27845400 15643 #define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
AnnaBridge 172:65be27845400 15644 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15645 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
AnnaBridge 172:65be27845400 15646 #define RCC_APB2RSTR_HRTIMRST_Pos (29U)
AnnaBridge 172:65be27845400 15647 #define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15648 #define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
AnnaBridge 172:65be27845400 15649
AnnaBridge 172:65be27845400 15650 /******************** Bit definition for RCC_APB4RSTR register ******************/
AnnaBridge 172:65be27845400 15651 #define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
AnnaBridge 172:65be27845400 15652 #define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15653 #define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
AnnaBridge 172:65be27845400 15654 #define RCC_APB4RSTR_LPUART1RST_Pos (3U)
AnnaBridge 172:65be27845400 15655 #define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15656 #define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
AnnaBridge 172:65be27845400 15657 #define RCC_APB4RSTR_SPI6RST_Pos (5U)
AnnaBridge 172:65be27845400 15658 #define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15659 #define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
AnnaBridge 172:65be27845400 15660 #define RCC_APB4RSTR_I2C4RST_Pos (7U)
AnnaBridge 172:65be27845400 15661 #define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15662 #define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
AnnaBridge 172:65be27845400 15663 #define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
AnnaBridge 172:65be27845400 15664 #define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15665 #define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
AnnaBridge 172:65be27845400 15666 #define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
AnnaBridge 172:65be27845400 15667 #define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15668 #define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
AnnaBridge 172:65be27845400 15669 #define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
AnnaBridge 172:65be27845400 15670 #define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15671 #define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
AnnaBridge 172:65be27845400 15672 #define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
AnnaBridge 172:65be27845400 15673 #define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15674 #define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
AnnaBridge 172:65be27845400 15675 #define RCC_APB4RSTR_COMP12RST_Pos (14U)
AnnaBridge 172:65be27845400 15676 #define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15677 #define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
AnnaBridge 172:65be27845400 15678 #define RCC_APB4RSTR_VREFRST_Pos (15U)
AnnaBridge 172:65be27845400 15679 #define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15680 #define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
AnnaBridge 172:65be27845400 15681 #define RCC_APB4RSTR_SAI4RST_Pos (21U)
AnnaBridge 172:65be27845400 15682 #define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15683 #define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
AnnaBridge 172:65be27845400 15684
AnnaBridge 172:65be27845400 15685
AnnaBridge 172:65be27845400 15686 /******************** Bit definition for RCC_GCR register ********************/
AnnaBridge 172:65be27845400 15687 #define RCC_GCR_WW1RSC_Pos (0U)
AnnaBridge 172:65be27845400 15688 #define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15689 #define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
AnnaBridge 172:65be27845400 15690
AnnaBridge 172:65be27845400 15691 /******************** Bit definition for RCC_D3AMR register ********************/
AnnaBridge 172:65be27845400 15692 #define RCC_D3AMR_BDMAAMEN_Pos (0U)
AnnaBridge 172:65be27845400 15693 #define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15694 #define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
AnnaBridge 172:65be27845400 15695 #define RCC_D3AMR_LPUART1AMEN_Pos (3U)
AnnaBridge 172:65be27845400 15696 #define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15697 #define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
AnnaBridge 172:65be27845400 15698 #define RCC_D3AMR_SPI6AMEN_Pos (5U)
AnnaBridge 172:65be27845400 15699 #define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15700 #define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
AnnaBridge 172:65be27845400 15701 #define RCC_D3AMR_I2C4AMEN_Pos (7U)
AnnaBridge 172:65be27845400 15702 #define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15703 #define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
AnnaBridge 172:65be27845400 15704 #define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
AnnaBridge 172:65be27845400 15705 #define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15706 #define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
AnnaBridge 172:65be27845400 15707 #define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
AnnaBridge 172:65be27845400 15708 #define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15709 #define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
AnnaBridge 172:65be27845400 15710 #define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
AnnaBridge 172:65be27845400 15711 #define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 15712 #define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
AnnaBridge 172:65be27845400 15713 #define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
AnnaBridge 172:65be27845400 15714 #define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15715 #define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
AnnaBridge 172:65be27845400 15716 #define RCC_D3AMR_COMP12AMEN_Pos (14U)
AnnaBridge 172:65be27845400 15717 #define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15718 #define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
AnnaBridge 172:65be27845400 15719 #define RCC_D3AMR_VREFAMEN_Pos (15U)
AnnaBridge 172:65be27845400 15720 #define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15721 #define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
AnnaBridge 172:65be27845400 15722 #define RCC_D3AMR_RTCAMEN_Pos (16U)
AnnaBridge 172:65be27845400 15723 #define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15724 #define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
AnnaBridge 172:65be27845400 15725 #define RCC_D3AMR_CRCAMEN_Pos (19U)
AnnaBridge 172:65be27845400 15726 #define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15727 #define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
AnnaBridge 172:65be27845400 15728 #define RCC_D3AMR_SAI4AMEN_Pos (21U)
AnnaBridge 172:65be27845400 15729 #define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15730 #define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
AnnaBridge 172:65be27845400 15731 #define RCC_D3AMR_ADC3AMEN_Pos (24U)
AnnaBridge 172:65be27845400 15732 #define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15733 #define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
AnnaBridge 172:65be27845400 15734
AnnaBridge 172:65be27845400 15735
AnnaBridge 172:65be27845400 15736 #define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
AnnaBridge 172:65be27845400 15737 #define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15738 #define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
AnnaBridge 172:65be27845400 15739 #define RCC_D3AMR_SRAM4AMEN_Pos (29U)
AnnaBridge 172:65be27845400 15740 #define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15741 #define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
AnnaBridge 172:65be27845400 15742 /******************** Bit definition for RCC_AHB3LPENR register **************/
AnnaBridge 172:65be27845400 15743 #define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
AnnaBridge 172:65be27845400 15744 #define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15745 #define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
AnnaBridge 172:65be27845400 15746 #define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
AnnaBridge 172:65be27845400 15747 #define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15748 #define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
AnnaBridge 172:65be27845400 15749 #define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
AnnaBridge 172:65be27845400 15750 #define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15751 #define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
AnnaBridge 172:65be27845400 15752 #define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
AnnaBridge 172:65be27845400 15753 #define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15754 #define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
AnnaBridge 172:65be27845400 15755 #define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
AnnaBridge 172:65be27845400 15756 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 15757 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
AnnaBridge 172:65be27845400 15758 #define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
AnnaBridge 172:65be27845400 15759 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15760 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
AnnaBridge 172:65be27845400 15761 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
AnnaBridge 172:65be27845400 15762 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15763 #define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
AnnaBridge 172:65be27845400 15764 #define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
AnnaBridge 172:65be27845400 15765 #define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15766 #define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
AnnaBridge 172:65be27845400 15767 #define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
AnnaBridge 172:65be27845400 15768 #define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15769 #define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
AnnaBridge 172:65be27845400 15770 #define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
AnnaBridge 172:65be27845400 15771 #define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15772 #define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
AnnaBridge 172:65be27845400 15773 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
AnnaBridge 172:65be27845400 15774 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15775 #define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
AnnaBridge 172:65be27845400 15776
AnnaBridge 172:65be27845400 15777
AnnaBridge 172:65be27845400 15778 /******************** Bit definition for RCC_AHB1LPENR register ***************/
AnnaBridge 172:65be27845400 15779 #define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
AnnaBridge 172:65be27845400 15780 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15781 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 172:65be27845400 15782 #define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
AnnaBridge 172:65be27845400 15783 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15784 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 172:65be27845400 15785 #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
AnnaBridge 172:65be27845400 15786 #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15787 #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
AnnaBridge 172:65be27845400 15788 #define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
AnnaBridge 172:65be27845400 15789 #define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15790 #define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
AnnaBridge 172:65be27845400 15791 #define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
AnnaBridge 172:65be27845400 15792 #define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15793 #define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
AnnaBridge 172:65be27845400 15794 #define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
AnnaBridge 172:65be27845400 15795 #define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15796 #define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
AnnaBridge 172:65be27845400 15797 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
AnnaBridge 172:65be27845400 15798 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 15799 #define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
AnnaBridge 172:65be27845400 15800 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
AnnaBridge 172:65be27845400 15801 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 15802 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
AnnaBridge 172:65be27845400 15803 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
AnnaBridge 172:65be27845400 15804 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15805 #define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
AnnaBridge 172:65be27845400 15806
AnnaBridge 172:65be27845400 15807 /* Legacy define */
AnnaBridge 172:65be27845400 15808 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
AnnaBridge 172:65be27845400 15809 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
AnnaBridge 172:65be27845400 15810 #define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
AnnaBridge 172:65be27845400 15811
AnnaBridge 172:65be27845400 15812
AnnaBridge 172:65be27845400 15813 /******************** Bit definition for RCC_AHB2LPENR register ***************/
AnnaBridge 172:65be27845400 15814 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
AnnaBridge 172:65be27845400 15815 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15816 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
AnnaBridge 172:65be27845400 15817 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
AnnaBridge 172:65be27845400 15818 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15819 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
AnnaBridge 172:65be27845400 15820 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
AnnaBridge 172:65be27845400 15821 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15822 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
AnnaBridge 172:65be27845400 15823 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
AnnaBridge 172:65be27845400 15824 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15825 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
AnnaBridge 172:65be27845400 15826 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
AnnaBridge 172:65be27845400 15827 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15828 #define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
AnnaBridge 172:65be27845400 15829 #define RCC_AHB2LPENR_D2SRAM1LPEN_Pos (30U)
AnnaBridge 172:65be27845400 15830 #define RCC_AHB2LPENR_D2SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM1LPEN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15831 #define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_D2SRAM1LPEN_Msk
AnnaBridge 172:65be27845400 15832 #define RCC_AHB2LPENR_D2SRAM2LPEN_Pos (30U)
AnnaBridge 172:65be27845400 15833 #define RCC_AHB2LPENR_D2SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM2LPEN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15834 #define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_D2SRAM2LPEN_Msk
AnnaBridge 172:65be27845400 15835 #define RCC_AHB2LPENR_D2SRAM3LPEN_Pos (31U)
AnnaBridge 172:65be27845400 15836 #define RCC_AHB2LPENR_D2SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_D2SRAM3LPEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15837 #define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_D2SRAM3LPEN_Msk
AnnaBridge 172:65be27845400 15838
AnnaBridge 172:65be27845400 15839
AnnaBridge 172:65be27845400 15840 /******************** Bit definition for RCC_AHB4LPENR register ******************/
AnnaBridge 172:65be27845400 15841 #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 172:65be27845400 15842 #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15843 #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
AnnaBridge 172:65be27845400 15844 #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 172:65be27845400 15845 #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15846 #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
AnnaBridge 172:65be27845400 15847 #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 172:65be27845400 15848 #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15849 #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
AnnaBridge 172:65be27845400 15850 #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 172:65be27845400 15851 #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15852 #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
AnnaBridge 172:65be27845400 15853 #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 172:65be27845400 15854 #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15855 #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
AnnaBridge 172:65be27845400 15856 #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
AnnaBridge 172:65be27845400 15857 #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15858 #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
AnnaBridge 172:65be27845400 15859 #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
AnnaBridge 172:65be27845400 15860 #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15861 #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
AnnaBridge 172:65be27845400 15862 #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 172:65be27845400 15863 #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15864 #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
AnnaBridge 172:65be27845400 15865 #define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
AnnaBridge 172:65be27845400 15866 #define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15867 #define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
AnnaBridge 172:65be27845400 15868 #define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
AnnaBridge 172:65be27845400 15869 #define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15870 #define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
AnnaBridge 172:65be27845400 15871 #define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
AnnaBridge 172:65be27845400 15872 #define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 15873 #define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
AnnaBridge 172:65be27845400 15874 #define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
AnnaBridge 172:65be27845400 15875 #define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15876 #define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
AnnaBridge 172:65be27845400 15877 #define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
AnnaBridge 172:65be27845400 15878 #define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15879 #define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
AnnaBridge 172:65be27845400 15880 #define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
AnnaBridge 172:65be27845400 15881 #define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 15882 #define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
AnnaBridge 172:65be27845400 15883 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
AnnaBridge 172:65be27845400 15884 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 15885 #define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
AnnaBridge 172:65be27845400 15886 #define RCC_AHB4LPENR_D3SRAM1LPEN_Pos (29U)
AnnaBridge 172:65be27845400 15887 #define RCC_AHB4LPENR_D3SRAM1LPEN_Msk (0x1UL << RCC_AHB4LPENR_D3SRAM1LPEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15888 #define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_D3SRAM1LPEN_Msk
AnnaBridge 172:65be27845400 15889
AnnaBridge 172:65be27845400 15890 /******************** Bit definition for RCC_APB3LPENR register ******************/
AnnaBridge 172:65be27845400 15891
AnnaBridge 172:65be27845400 15892 #define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
AnnaBridge 172:65be27845400 15893 #define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15894 #define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
AnnaBridge 172:65be27845400 15895 #define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
AnnaBridge 172:65be27845400 15896 #define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15897 #define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
AnnaBridge 172:65be27845400 15898
AnnaBridge 172:65be27845400 15899 /******************** Bit definition for RCC_APB1LLPENR register ******************/
AnnaBridge 172:65be27845400 15900
AnnaBridge 172:65be27845400 15901 #define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
AnnaBridge 172:65be27845400 15902 #define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15903 #define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
AnnaBridge 172:65be27845400 15904 #define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
AnnaBridge 172:65be27845400 15905 #define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15906 #define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
AnnaBridge 172:65be27845400 15907 #define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
AnnaBridge 172:65be27845400 15908 #define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15909 #define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
AnnaBridge 172:65be27845400 15910 #define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
AnnaBridge 172:65be27845400 15911 #define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 15912 #define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
AnnaBridge 172:65be27845400 15913 #define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
AnnaBridge 172:65be27845400 15914 #define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15915 #define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
AnnaBridge 172:65be27845400 15916 #define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
AnnaBridge 172:65be27845400 15917 #define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15918 #define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
AnnaBridge 172:65be27845400 15919 #define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
AnnaBridge 172:65be27845400 15920 #define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 15921 #define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
AnnaBridge 172:65be27845400 15922 #define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
AnnaBridge 172:65be27845400 15923 #define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 15924 #define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
AnnaBridge 172:65be27845400 15925 #define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
AnnaBridge 172:65be27845400 15926 #define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15927 #define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
AnnaBridge 172:65be27845400 15928 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
AnnaBridge 172:65be27845400 15929 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 15930 #define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
AnnaBridge 172:65be27845400 15931
AnnaBridge 172:65be27845400 15932
AnnaBridge 172:65be27845400 15933 #define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
AnnaBridge 172:65be27845400 15934 #define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 15935 #define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
AnnaBridge 172:65be27845400 15936 #define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
AnnaBridge 172:65be27845400 15937 #define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 15938 #define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
AnnaBridge 172:65be27845400 15939 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
AnnaBridge 172:65be27845400 15940 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 15941 #define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
AnnaBridge 172:65be27845400 15942 #define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
AnnaBridge 172:65be27845400 15943 #define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 15944 #define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
AnnaBridge 172:65be27845400 15945 #define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
AnnaBridge 172:65be27845400 15946 #define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 15947 #define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
AnnaBridge 172:65be27845400 15948 #define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
AnnaBridge 172:65be27845400 15949 #define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 15950 #define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
AnnaBridge 172:65be27845400 15951 #define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
AnnaBridge 172:65be27845400 15952 #define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 15953 #define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
AnnaBridge 172:65be27845400 15954 #define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
AnnaBridge 172:65be27845400 15955 #define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 15956 #define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
AnnaBridge 172:65be27845400 15957 #define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
AnnaBridge 172:65be27845400 15958 #define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 15959 #define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
AnnaBridge 172:65be27845400 15960 #define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
AnnaBridge 172:65be27845400 15961 #define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 15962 #define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
AnnaBridge 172:65be27845400 15963 #define RCC_APB1LLPENR_CECLPEN_Pos (27U)
AnnaBridge 172:65be27845400 15964 #define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 15965 #define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
AnnaBridge 172:65be27845400 15966 #define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
AnnaBridge 172:65be27845400 15967 #define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 15968 #define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
AnnaBridge 172:65be27845400 15969 #define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
AnnaBridge 172:65be27845400 15970 #define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 15971 #define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
AnnaBridge 172:65be27845400 15972 #define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
AnnaBridge 172:65be27845400 15973 #define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 15974 #define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
AnnaBridge 172:65be27845400 15975
AnnaBridge 172:65be27845400 15976 /******************** Bit definition for RCC_APB1HLPENR register ******************/
AnnaBridge 172:65be27845400 15977 #define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
AnnaBridge 172:65be27845400 15978 #define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15979 #define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
AnnaBridge 172:65be27845400 15980 #define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
AnnaBridge 172:65be27845400 15981 #define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 15982 #define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
AnnaBridge 172:65be27845400 15983 #define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
AnnaBridge 172:65be27845400 15984 #define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 15985 #define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
AnnaBridge 172:65be27845400 15986 #define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
AnnaBridge 172:65be27845400 15987 #define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 15988 #define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
AnnaBridge 172:65be27845400 15989 #define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
AnnaBridge 172:65be27845400 15990 #define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 15991 #define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
AnnaBridge 172:65be27845400 15992
AnnaBridge 172:65be27845400 15993 /******************** Bit definition for RCC_APB2LPENR register ******************/
AnnaBridge 172:65be27845400 15994 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 172:65be27845400 15995 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 15996 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 172:65be27845400 15997 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
AnnaBridge 172:65be27845400 15998 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 15999 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
AnnaBridge 172:65be27845400 16000 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 172:65be27845400 16001 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16002 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 172:65be27845400 16003 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 172:65be27845400 16004 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16005 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 172:65be27845400 16006 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 172:65be27845400 16007 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16008 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 172:65be27845400 16009 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
AnnaBridge 172:65be27845400 16010 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16011 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
AnnaBridge 172:65be27845400 16012 #define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
AnnaBridge 172:65be27845400 16013 #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16014 #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
AnnaBridge 172:65be27845400 16015 #define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
AnnaBridge 172:65be27845400 16016 #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16017 #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
AnnaBridge 172:65be27845400 16018 #define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
AnnaBridge 172:65be27845400 16019 #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16020 #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
AnnaBridge 172:65be27845400 16021 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
AnnaBridge 172:65be27845400 16022 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16023 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
AnnaBridge 172:65be27845400 16024 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
AnnaBridge 172:65be27845400 16025 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16026 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
AnnaBridge 172:65be27845400 16027 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
AnnaBridge 172:65be27845400 16028 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16029 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
AnnaBridge 172:65be27845400 16030 #define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
AnnaBridge 172:65be27845400 16031 #define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16032 #define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
AnnaBridge 172:65be27845400 16033 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
AnnaBridge 172:65be27845400 16034 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16035 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
AnnaBridge 172:65be27845400 16036 #define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
AnnaBridge 172:65be27845400 16037 #define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16038 #define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
AnnaBridge 172:65be27845400 16039
AnnaBridge 172:65be27845400 16040 /******************** Bit definition for RCC_APB4LPENR register ******************/
AnnaBridge 172:65be27845400 16041 #define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
AnnaBridge 172:65be27845400 16042 #define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16043 #define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
AnnaBridge 172:65be27845400 16044 #define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
AnnaBridge 172:65be27845400 16045 #define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16046 #define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
AnnaBridge 172:65be27845400 16047 #define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
AnnaBridge 172:65be27845400 16048 #define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16049 #define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
AnnaBridge 172:65be27845400 16050 #define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
AnnaBridge 172:65be27845400 16051 #define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16052 #define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
AnnaBridge 172:65be27845400 16053 #define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
AnnaBridge 172:65be27845400 16054 #define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16055 #define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
AnnaBridge 172:65be27845400 16056 #define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
AnnaBridge 172:65be27845400 16057 #define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16058 #define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
AnnaBridge 172:65be27845400 16059 #define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
AnnaBridge 172:65be27845400 16060 #define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16061 #define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
AnnaBridge 172:65be27845400 16062 #define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
AnnaBridge 172:65be27845400 16063 #define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16064 #define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
AnnaBridge 172:65be27845400 16065 #define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
AnnaBridge 172:65be27845400 16066 #define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16067 #define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
AnnaBridge 172:65be27845400 16068 #define RCC_APB4LPENR_VREFLPEN_Pos (15U)
AnnaBridge 172:65be27845400 16069 #define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16070 #define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
AnnaBridge 172:65be27845400 16071 #define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
AnnaBridge 172:65be27845400 16072 #define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16073 #define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
AnnaBridge 172:65be27845400 16074 #define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
AnnaBridge 172:65be27845400 16075 #define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16076 #define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
AnnaBridge 172:65be27845400 16077
AnnaBridge 172:65be27845400 16078
AnnaBridge 172:65be27845400 16079 /******************** Bit definition for RCC_RSR register *******************/
AnnaBridge 172:65be27845400 16080 #define RCC_RSR_RMVF_Pos (16U)
AnnaBridge 172:65be27845400 16081 #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16082 #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
AnnaBridge 172:65be27845400 16083 #define RCC_RSR_CPURSTF_Pos (17U)
AnnaBridge 172:65be27845400 16084 #define RCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16085 #define RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk
AnnaBridge 172:65be27845400 16086 #define RCC_RSR_D1RSTF_Pos (19U)
AnnaBridge 172:65be27845400 16087 #define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16088 #define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
AnnaBridge 172:65be27845400 16089 #define RCC_RSR_D2RSTF_Pos (20U)
AnnaBridge 172:65be27845400 16090 #define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16091 #define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
AnnaBridge 172:65be27845400 16092 #define RCC_RSR_BORRSTF_Pos (21U)
AnnaBridge 172:65be27845400 16093 #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16094 #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
AnnaBridge 172:65be27845400 16095 #define RCC_RSR_PINRSTF_Pos (22U)
AnnaBridge 172:65be27845400 16096 #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16097 #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
AnnaBridge 172:65be27845400 16098 #define RCC_RSR_PORRSTF_Pos (23U)
AnnaBridge 172:65be27845400 16099 #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16100 #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
AnnaBridge 172:65be27845400 16101 #define RCC_RSR_SFTRSTF_Pos (24U)
AnnaBridge 172:65be27845400 16102 #define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16103 #define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
AnnaBridge 172:65be27845400 16104 #define RCC_RSR_IWDG1RSTF_Pos (26U)
AnnaBridge 172:65be27845400 16105 #define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16106 #define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
AnnaBridge 172:65be27845400 16107 #define RCC_RSR_WWDG1RSTF_Pos (28U)
AnnaBridge 172:65be27845400 16108 #define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16109 #define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
AnnaBridge 172:65be27845400 16110
AnnaBridge 172:65be27845400 16111 #define RCC_RSR_LPWRRSTF_Pos (30U)
AnnaBridge 172:65be27845400 16112 #define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16113 #define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
AnnaBridge 172:65be27845400 16114
AnnaBridge 172:65be27845400 16115
AnnaBridge 172:65be27845400 16116 /******************************************************************************/
AnnaBridge 172:65be27845400 16117 /* */
AnnaBridge 172:65be27845400 16118 /* RNG */
AnnaBridge 172:65be27845400 16119 /* */
AnnaBridge 172:65be27845400 16120 /******************************************************************************/
AnnaBridge 172:65be27845400 16121 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 172:65be27845400 16122 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 172:65be27845400 16123 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16124 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 172:65be27845400 16125 #define RNG_CR_IE_Pos (3U)
AnnaBridge 172:65be27845400 16126 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16127 #define RNG_CR_IE RNG_CR_IE_Msk
AnnaBridge 172:65be27845400 16128 #define RNG_CR_CED_Pos (5U)
AnnaBridge 172:65be27845400 16129 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16130 #define RNG_CR_CED RNG_CR_CED_Msk
AnnaBridge 172:65be27845400 16131
AnnaBridge 172:65be27845400 16132 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 172:65be27845400 16133 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 172:65be27845400 16134 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16135 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 172:65be27845400 16136 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 172:65be27845400 16137 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16138 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 172:65be27845400 16139 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 172:65be27845400 16140 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16141 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 172:65be27845400 16142 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 172:65be27845400 16143 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16144 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 172:65be27845400 16145 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 172:65be27845400 16146 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16147 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
AnnaBridge 172:65be27845400 16148
AnnaBridge 172:65be27845400 16149 /******************************************************************************/
AnnaBridge 172:65be27845400 16150 /* */
AnnaBridge 172:65be27845400 16151 /* Real-Time Clock (RTC) */
AnnaBridge 172:65be27845400 16152 /* */
AnnaBridge 172:65be27845400 16153 /******************************************************************************/
AnnaBridge 172:65be27845400 16154 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 172:65be27845400 16155 #define RTC_TR_PM_Pos (22U)
AnnaBridge 172:65be27845400 16156 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16157 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 172:65be27845400 16158 #define RTC_TR_HT_Pos (20U)
AnnaBridge 172:65be27845400 16159 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 16160 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 172:65be27845400 16161 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16162 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16163 #define RTC_TR_HU_Pos (16U)
AnnaBridge 172:65be27845400 16164 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 16165 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 172:65be27845400 16166 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16167 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16168 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16169 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16170 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 16171 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 16172 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 172:65be27845400 16173 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16174 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16175 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16176 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 16177 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 16178 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 172:65be27845400 16179 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16180 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16181 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16182 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16183 #define RTC_TR_ST_Pos (4U)
AnnaBridge 172:65be27845400 16184 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 16185 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 172:65be27845400 16186 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16187 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16188 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16189 #define RTC_TR_SU_Pos (0U)
AnnaBridge 172:65be27845400 16190 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16191 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 172:65be27845400 16192 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16193 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16194 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16195 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16196
AnnaBridge 172:65be27845400 16197 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 172:65be27845400 16198 #define RTC_DR_YT_Pos (20U)
AnnaBridge 172:65be27845400 16199 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 16200 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 172:65be27845400 16201 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16202 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16203 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16204 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16205 #define RTC_DR_YU_Pos (16U)
AnnaBridge 172:65be27845400 16206 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 16207 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 172:65be27845400 16208 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16209 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16210 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16211 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16212 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 172:65be27845400 16213 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 16214 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 172:65be27845400 16215 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16216 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16217 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16218 #define RTC_DR_MT_Pos (12U)
AnnaBridge 172:65be27845400 16219 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16220 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 172:65be27845400 16221 #define RTC_DR_MU_Pos (8U)
AnnaBridge 172:65be27845400 16222 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 16223 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 172:65be27845400 16224 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16225 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16226 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16227 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16228 #define RTC_DR_DT_Pos (4U)
AnnaBridge 172:65be27845400 16229 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 16230 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 172:65be27845400 16231 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16232 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16233 #define RTC_DR_DU_Pos (0U)
AnnaBridge 172:65be27845400 16234 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16235 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 172:65be27845400 16236 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16237 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16238 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16239 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16240
AnnaBridge 172:65be27845400 16241 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 172:65be27845400 16242 #define RTC_CR_ITSE_Pos (24U)
AnnaBridge 172:65be27845400 16243 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16244 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
AnnaBridge 172:65be27845400 16245 #define RTC_CR_COE_Pos (23U)
AnnaBridge 172:65be27845400 16246 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16247 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 172:65be27845400 16248 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 172:65be27845400 16249 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 16250 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 172:65be27845400 16251 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16252 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16253 #define RTC_CR_POL_Pos (20U)
AnnaBridge 172:65be27845400 16254 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16255 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 172:65be27845400 16256 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 172:65be27845400 16257 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16258 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 172:65be27845400 16259 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 172:65be27845400 16260 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16261 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 172:65be27845400 16262 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 172:65be27845400 16263 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16264 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 172:65be27845400 16265 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 172:65be27845400 16266 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16267 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 172:65be27845400 16268 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 172:65be27845400 16269 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16270 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 172:65be27845400 16271 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 172:65be27845400 16272 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16273 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 172:65be27845400 16274 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 172:65be27845400 16275 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16276 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 172:65be27845400 16277 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 172:65be27845400 16278 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16279 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 172:65be27845400 16280 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 172:65be27845400 16281 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16282 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 172:65be27845400 16283 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 172:65be27845400 16284 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16285 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 172:65be27845400 16286 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 172:65be27845400 16287 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16288 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 172:65be27845400 16289 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 172:65be27845400 16290 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16291 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 172:65be27845400 16292 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 172:65be27845400 16293 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16294 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 172:65be27845400 16295 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 172:65be27845400 16296 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16297 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 172:65be27845400 16298 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 172:65be27845400 16299 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16300 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 172:65be27845400 16301 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 172:65be27845400 16302 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16303 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 172:65be27845400 16304 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 172:65be27845400 16305 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 16306 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 172:65be27845400 16307 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16308 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16309 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16310
AnnaBridge 172:65be27845400 16311 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 172:65be27845400 16312 #define RTC_ISR_ITSF_Pos (17U)
AnnaBridge 172:65be27845400 16313 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16314 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
AnnaBridge 172:65be27845400 16315 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 172:65be27845400 16316 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16317 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 172:65be27845400 16318 #define RTC_ISR_TAMP3F_Pos (15U)
AnnaBridge 172:65be27845400 16319 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16320 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
AnnaBridge 172:65be27845400 16321 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 172:65be27845400 16322 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16323 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 172:65be27845400 16324 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 172:65be27845400 16325 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16326 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 172:65be27845400 16327 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 172:65be27845400 16328 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16329 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 172:65be27845400 16330 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 172:65be27845400 16331 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16332 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 172:65be27845400 16333 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 172:65be27845400 16334 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16335 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 172:65be27845400 16336 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 172:65be27845400 16337 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16338 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 172:65be27845400 16339 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 172:65be27845400 16340 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16341 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 172:65be27845400 16342 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 172:65be27845400 16343 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16344 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 172:65be27845400 16345 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 172:65be27845400 16346 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16347 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 172:65be27845400 16348 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 172:65be27845400 16349 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16350 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 172:65be27845400 16351 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 172:65be27845400 16352 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16353 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 172:65be27845400 16354 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 172:65be27845400 16355 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16356 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 172:65be27845400 16357 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 172:65be27845400 16358 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16359 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 172:65be27845400 16360 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 172:65be27845400 16361 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16362 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 172:65be27845400 16363 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 172:65be27845400 16364 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16365 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 172:65be27845400 16366
AnnaBridge 172:65be27845400 16367 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 172:65be27845400 16368 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 172:65be27845400 16369 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 172:65be27845400 16370 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 172:65be27845400 16371 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 172:65be27845400 16372 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 16373 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 172:65be27845400 16374
AnnaBridge 172:65be27845400 16375 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 172:65be27845400 16376 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 172:65be27845400 16377 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16378 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 172:65be27845400 16379
AnnaBridge 172:65be27845400 16380 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 172:65be27845400 16381 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 172:65be27845400 16382 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16383 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 172:65be27845400 16384 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 172:65be27845400 16385 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16386 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 172:65be27845400 16387 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 172:65be27845400 16388 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 16389 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 172:65be27845400 16390 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16391 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16392 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 172:65be27845400 16393 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 16394 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 172:65be27845400 16395 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16396 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16397 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16398 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16399 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 172:65be27845400 16400 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16401 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 172:65be27845400 16402 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 172:65be27845400 16403 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16404 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 172:65be27845400 16405 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 172:65be27845400 16406 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 16407 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 172:65be27845400 16408 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16409 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16410 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 172:65be27845400 16411 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 16412 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 172:65be27845400 16413 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16414 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16415 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16416 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16417 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 172:65be27845400 16418 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16419 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 172:65be27845400 16420 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 16421 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 16422 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 172:65be27845400 16423 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16424 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16425 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16426 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 16427 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 16428 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 172:65be27845400 16429 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16430 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16431 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16432 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16433 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 172:65be27845400 16434 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16435 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 172:65be27845400 16436 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 172:65be27845400 16437 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 16438 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 172:65be27845400 16439 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16440 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16441 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16442 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 172:65be27845400 16443 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16444 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 172:65be27845400 16445 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16446 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16447 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16448 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16449
AnnaBridge 172:65be27845400 16450 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 172:65be27845400 16451 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 172:65be27845400 16452 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16453 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 172:65be27845400 16454 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 172:65be27845400 16455 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 16456 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 172:65be27845400 16457 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 172:65be27845400 16458 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 16459 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 172:65be27845400 16460 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 16461 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 16462 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 172:65be27845400 16463 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 16464 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 172:65be27845400 16465 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16466 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16467 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16468 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16469 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 172:65be27845400 16470 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16471 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 172:65be27845400 16472 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 172:65be27845400 16473 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16474 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 172:65be27845400 16475 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 172:65be27845400 16476 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 16477 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 172:65be27845400 16478 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16479 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16480 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 172:65be27845400 16481 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 16482 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 172:65be27845400 16483 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16484 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16485 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16486 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16487 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 172:65be27845400 16488 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16489 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 172:65be27845400 16490 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 16491 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 16492 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 172:65be27845400 16493 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16494 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16495 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16496 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 16497 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 16498 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 172:65be27845400 16499 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16500 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16501 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16502 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16503 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 172:65be27845400 16504 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16505 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 172:65be27845400 16506 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 172:65be27845400 16507 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 16508 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 172:65be27845400 16509 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16510 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16511 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16512 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 172:65be27845400 16513 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16514 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 172:65be27845400 16515 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16516 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16517 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16518 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16519
AnnaBridge 172:65be27845400 16520 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 172:65be27845400 16521 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 172:65be27845400 16522 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 16523 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 172:65be27845400 16524
AnnaBridge 172:65be27845400 16525 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 172:65be27845400 16526 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 16527 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16528 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 172:65be27845400 16529
AnnaBridge 172:65be27845400 16530 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 172:65be27845400 16531 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 172:65be27845400 16532 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 16533 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 172:65be27845400 16534 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 172:65be27845400 16535 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 16536 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 172:65be27845400 16537
AnnaBridge 172:65be27845400 16538 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 172:65be27845400 16539 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 172:65be27845400 16540 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16541 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 172:65be27845400 16542 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 172:65be27845400 16543 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 16544 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 172:65be27845400 16545 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16546 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16547 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 172:65be27845400 16548 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 16549 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 172:65be27845400 16550 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16551 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16552 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16553 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16554 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 172:65be27845400 16555 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 16556 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 172:65be27845400 16557 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16558 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16559 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16560 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 172:65be27845400 16561 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 16562 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 172:65be27845400 16563 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16564 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16565 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16566 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16567 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 172:65be27845400 16568 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 16569 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 172:65be27845400 16570 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16571 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16572 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16573 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 172:65be27845400 16574 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16575 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 172:65be27845400 16576 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16577 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16578 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16579 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16580
AnnaBridge 172:65be27845400 16581 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 172:65be27845400 16582 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 172:65be27845400 16583 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 16584 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 172:65be27845400 16585 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16586 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16587 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16588 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 172:65be27845400 16589 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16590 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 172:65be27845400 16591 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 172:65be27845400 16592 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 16593 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 172:65be27845400 16594 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16595 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16596 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16597 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16598 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 172:65be27845400 16599 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 16600 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 172:65be27845400 16601 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16602 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16603 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 172:65be27845400 16604 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 16605 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 172:65be27845400 16606 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16607 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16608 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16609 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16610
AnnaBridge 172:65be27845400 16611 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 172:65be27845400 16612 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 16613 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 16614 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 172:65be27845400 16615
AnnaBridge 172:65be27845400 16616 /******************** Bits definition for RTC_CALR register *****************/
AnnaBridge 172:65be27845400 16617 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 172:65be27845400 16618 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16619 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 172:65be27845400 16620 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 172:65be27845400 16621 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16622 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 172:65be27845400 16623 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 172:65be27845400 16624 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16625 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 172:65be27845400 16626 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 172:65be27845400 16627 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 16628 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 172:65be27845400 16629 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16630 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16631 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16632 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16633 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16634 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16635 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16636 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16637 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16638
AnnaBridge 172:65be27845400 16639 /******************** Bits definition for RTC_TAMPCR register ***************/
AnnaBridge 172:65be27845400 16640 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
AnnaBridge 172:65be27845400 16641 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16642 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
AnnaBridge 172:65be27845400 16643 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
AnnaBridge 172:65be27845400 16644 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 16645 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
AnnaBridge 172:65be27845400 16646 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
AnnaBridge 172:65be27845400 16647 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 16648 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
AnnaBridge 172:65be27845400 16649 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
AnnaBridge 172:65be27845400 16650 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16651 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
AnnaBridge 172:65be27845400 16652 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
AnnaBridge 172:65be27845400 16653 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16654 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
AnnaBridge 172:65be27845400 16655 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
AnnaBridge 172:65be27845400 16656 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 16657 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
AnnaBridge 172:65be27845400 16658 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
AnnaBridge 172:65be27845400 16659 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 16660 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
AnnaBridge 172:65be27845400 16661 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
AnnaBridge 172:65be27845400 16662 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 16663 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
AnnaBridge 172:65be27845400 16664 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
AnnaBridge 172:65be27845400 16665 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 16666 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
AnnaBridge 172:65be27845400 16667 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
AnnaBridge 172:65be27845400 16668 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 16669 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
AnnaBridge 172:65be27845400 16670 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
AnnaBridge 172:65be27845400 16671 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 16672 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
AnnaBridge 172:65be27845400 16673 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 16674 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16675 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
AnnaBridge 172:65be27845400 16676 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 16677 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
AnnaBridge 172:65be27845400 16678 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16679 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 16680 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
AnnaBridge 172:65be27845400 16681 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 16682 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
AnnaBridge 172:65be27845400 16683 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16684 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16685 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16686 #define RTC_TAMPCR_TAMPTS_Pos (7U)
AnnaBridge 172:65be27845400 16687 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16688 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
AnnaBridge 172:65be27845400 16689 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
AnnaBridge 172:65be27845400 16690 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16691 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
AnnaBridge 172:65be27845400 16692 #define RTC_TAMPCR_TAMP3E_Pos (5U)
AnnaBridge 172:65be27845400 16693 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16694 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
AnnaBridge 172:65be27845400 16695 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
AnnaBridge 172:65be27845400 16696 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16697 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
AnnaBridge 172:65be27845400 16698 #define RTC_TAMPCR_TAMP2E_Pos (3U)
AnnaBridge 172:65be27845400 16699 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16700 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
AnnaBridge 172:65be27845400 16701 #define RTC_TAMPCR_TAMPIE_Pos (2U)
AnnaBridge 172:65be27845400 16702 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16703 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
AnnaBridge 172:65be27845400 16704 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
AnnaBridge 172:65be27845400 16705 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16706 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
AnnaBridge 172:65be27845400 16707 #define RTC_TAMPCR_TAMP1E_Pos (0U)
AnnaBridge 172:65be27845400 16708 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16709 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
AnnaBridge 172:65be27845400 16710
AnnaBridge 172:65be27845400 16711 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 172:65be27845400 16712 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 172:65be27845400 16713 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 16714 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 172:65be27845400 16715 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16716 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16717 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16718 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16719 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 16720 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 16721 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 172:65be27845400 16722
AnnaBridge 172:65be27845400 16723 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 172:65be27845400 16724 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 172:65be27845400 16725 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 16726 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 172:65be27845400 16727 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 16728 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 16729 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 16730 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 16731 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 172:65be27845400 16732 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 172:65be27845400 16733 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 172:65be27845400 16734
AnnaBridge 172:65be27845400 16735 /******************** Bits definition for RTC_OR register *******************/
AnnaBridge 172:65be27845400 16736 #define RTC_OR_OUT_RMP_Pos (1U)
AnnaBridge 172:65be27845400 16737 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16738 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
AnnaBridge 172:65be27845400 16739 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
AnnaBridge 172:65be27845400 16740 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16741 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
AnnaBridge 172:65be27845400 16742
AnnaBridge 172:65be27845400 16743 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 172:65be27845400 16744 #define RTC_BKP0R_Pos (0U)
AnnaBridge 172:65be27845400 16745 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16746 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 172:65be27845400 16747
AnnaBridge 172:65be27845400 16748 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 172:65be27845400 16749 #define RTC_BKP1R_Pos (0U)
AnnaBridge 172:65be27845400 16750 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16751 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 172:65be27845400 16752
AnnaBridge 172:65be27845400 16753 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 172:65be27845400 16754 #define RTC_BKP2R_Pos (0U)
AnnaBridge 172:65be27845400 16755 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16756 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 172:65be27845400 16757
AnnaBridge 172:65be27845400 16758 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 172:65be27845400 16759 #define RTC_BKP3R_Pos (0U)
AnnaBridge 172:65be27845400 16760 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16761 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 172:65be27845400 16762
AnnaBridge 172:65be27845400 16763 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 172:65be27845400 16764 #define RTC_BKP4R_Pos (0U)
AnnaBridge 172:65be27845400 16765 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16766 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 172:65be27845400 16767
AnnaBridge 172:65be27845400 16768 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 172:65be27845400 16769 #define RTC_BKP5R_Pos (0U)
AnnaBridge 172:65be27845400 16770 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16771 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 172:65be27845400 16772
AnnaBridge 172:65be27845400 16773 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 172:65be27845400 16774 #define RTC_BKP6R_Pos (0U)
AnnaBridge 172:65be27845400 16775 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16776 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 172:65be27845400 16777
AnnaBridge 172:65be27845400 16778 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 172:65be27845400 16779 #define RTC_BKP7R_Pos (0U)
AnnaBridge 172:65be27845400 16780 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16781 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 172:65be27845400 16782
AnnaBridge 172:65be27845400 16783 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 172:65be27845400 16784 #define RTC_BKP8R_Pos (0U)
AnnaBridge 172:65be27845400 16785 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16786 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 172:65be27845400 16787
AnnaBridge 172:65be27845400 16788 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 172:65be27845400 16789 #define RTC_BKP9R_Pos (0U)
AnnaBridge 172:65be27845400 16790 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16791 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 172:65be27845400 16792
AnnaBridge 172:65be27845400 16793 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 172:65be27845400 16794 #define RTC_BKP10R_Pos (0U)
AnnaBridge 172:65be27845400 16795 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16796 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 172:65be27845400 16797
AnnaBridge 172:65be27845400 16798 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 172:65be27845400 16799 #define RTC_BKP11R_Pos (0U)
AnnaBridge 172:65be27845400 16800 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16801 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 172:65be27845400 16802
AnnaBridge 172:65be27845400 16803 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 172:65be27845400 16804 #define RTC_BKP12R_Pos (0U)
AnnaBridge 172:65be27845400 16805 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16806 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 172:65be27845400 16807
AnnaBridge 172:65be27845400 16808 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 172:65be27845400 16809 #define RTC_BKP13R_Pos (0U)
AnnaBridge 172:65be27845400 16810 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16811 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 172:65be27845400 16812
AnnaBridge 172:65be27845400 16813 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 172:65be27845400 16814 #define RTC_BKP14R_Pos (0U)
AnnaBridge 172:65be27845400 16815 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16816 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 172:65be27845400 16817
AnnaBridge 172:65be27845400 16818 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 172:65be27845400 16819 #define RTC_BKP15R_Pos (0U)
AnnaBridge 172:65be27845400 16820 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16821 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 172:65be27845400 16822
AnnaBridge 172:65be27845400 16823 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 172:65be27845400 16824 #define RTC_BKP16R_Pos (0U)
AnnaBridge 172:65be27845400 16825 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16826 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 172:65be27845400 16827
AnnaBridge 172:65be27845400 16828 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 172:65be27845400 16829 #define RTC_BKP17R_Pos (0U)
AnnaBridge 172:65be27845400 16830 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16831 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 172:65be27845400 16832
AnnaBridge 172:65be27845400 16833 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 172:65be27845400 16834 #define RTC_BKP18R_Pos (0U)
AnnaBridge 172:65be27845400 16835 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16836 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 172:65be27845400 16837
AnnaBridge 172:65be27845400 16838 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 172:65be27845400 16839 #define RTC_BKP19R_Pos (0U)
AnnaBridge 172:65be27845400 16840 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16841 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 172:65be27845400 16842
AnnaBridge 172:65be27845400 16843 /******************** Bits definition for RTC_BKP20R register ***************/
AnnaBridge 172:65be27845400 16844 #define RTC_BKP20R_Pos (0U)
AnnaBridge 172:65be27845400 16845 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16846 #define RTC_BKP20R RTC_BKP20R_Msk
AnnaBridge 172:65be27845400 16847
AnnaBridge 172:65be27845400 16848 /******************** Bits definition for RTC_BKP21R register ***************/
AnnaBridge 172:65be27845400 16849 #define RTC_BKP21R_Pos (0U)
AnnaBridge 172:65be27845400 16850 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16851 #define RTC_BKP21R RTC_BKP21R_Msk
AnnaBridge 172:65be27845400 16852
AnnaBridge 172:65be27845400 16853 /******************** Bits definition for RTC_BKP22R register ***************/
AnnaBridge 172:65be27845400 16854 #define RTC_BKP22R_Pos (0U)
AnnaBridge 172:65be27845400 16855 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16856 #define RTC_BKP22R RTC_BKP22R_Msk
AnnaBridge 172:65be27845400 16857
AnnaBridge 172:65be27845400 16858 /******************** Bits definition for RTC_BKP23R register ***************/
AnnaBridge 172:65be27845400 16859 #define RTC_BKP23R_Pos (0U)
AnnaBridge 172:65be27845400 16860 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16861 #define RTC_BKP23R RTC_BKP23R_Msk
AnnaBridge 172:65be27845400 16862
AnnaBridge 172:65be27845400 16863 /******************** Bits definition for RTC_BKP24R register ***************/
AnnaBridge 172:65be27845400 16864 #define RTC_BKP24R_Pos (0U)
AnnaBridge 172:65be27845400 16865 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16866 #define RTC_BKP24R RTC_BKP24R_Msk
AnnaBridge 172:65be27845400 16867
AnnaBridge 172:65be27845400 16868 /******************** Bits definition for RTC_BKP25R register ***************/
AnnaBridge 172:65be27845400 16869 #define RTC_BKP25R_Pos (0U)
AnnaBridge 172:65be27845400 16870 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16871 #define RTC_BKP25R RTC_BKP25R_Msk
AnnaBridge 172:65be27845400 16872
AnnaBridge 172:65be27845400 16873 /******************** Bits definition for RTC_BKP26R register ***************/
AnnaBridge 172:65be27845400 16874 #define RTC_BKP26R_Pos (0U)
AnnaBridge 172:65be27845400 16875 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16876 #define RTC_BKP26R RTC_BKP26R_Msk
AnnaBridge 172:65be27845400 16877
AnnaBridge 172:65be27845400 16878 /******************** Bits definition for RTC_BKP27R register ***************/
AnnaBridge 172:65be27845400 16879 #define RTC_BKP27R_Pos (0U)
AnnaBridge 172:65be27845400 16880 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16881 #define RTC_BKP27R RTC_BKP27R_Msk
AnnaBridge 172:65be27845400 16882
AnnaBridge 172:65be27845400 16883 /******************** Bits definition for RTC_BKP28R register ***************/
AnnaBridge 172:65be27845400 16884 #define RTC_BKP28R_Pos (0U)
AnnaBridge 172:65be27845400 16885 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16886 #define RTC_BKP28R RTC_BKP28R_Msk
AnnaBridge 172:65be27845400 16887
AnnaBridge 172:65be27845400 16888 /******************** Bits definition for RTC_BKP29R register ***************/
AnnaBridge 172:65be27845400 16889 #define RTC_BKP29R_Pos (0U)
AnnaBridge 172:65be27845400 16890 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16891 #define RTC_BKP29R RTC_BKP29R_Msk
AnnaBridge 172:65be27845400 16892
AnnaBridge 172:65be27845400 16893 /******************** Bits definition for RTC_BKP30R register ***************/
AnnaBridge 172:65be27845400 16894 #define RTC_BKP30R_Pos (0U)
AnnaBridge 172:65be27845400 16895 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16896 #define RTC_BKP30R RTC_BKP30R_Msk
AnnaBridge 172:65be27845400 16897
AnnaBridge 172:65be27845400 16898 /******************** Bits definition for RTC_BKP31R register ***************/
AnnaBridge 172:65be27845400 16899 #define RTC_BKP31R_Pos (0U)
AnnaBridge 172:65be27845400 16900 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 16901 #define RTC_BKP31R RTC_BKP31R_Msk
AnnaBridge 172:65be27845400 16902
AnnaBridge 172:65be27845400 16903 /******************** Number of backup registers ******************************/
AnnaBridge 172:65be27845400 16904 #define RTC_BKP_NUMBER_Pos (5U)
AnnaBridge 172:65be27845400 16905 #define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16906 #define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
AnnaBridge 172:65be27845400 16907
AnnaBridge 172:65be27845400 16908 /******************************************************************************/
AnnaBridge 172:65be27845400 16909 /* */
AnnaBridge 172:65be27845400 16910 /* SPDIF-RX Interface */
AnnaBridge 172:65be27845400 16911 /* */
AnnaBridge 172:65be27845400 16912 /******************************************************************************/
AnnaBridge 172:65be27845400 16913 /******************** Bit definition for SPDIF_CR register ******************/
AnnaBridge 172:65be27845400 16914 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
AnnaBridge 172:65be27845400 16915 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 16916 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
AnnaBridge 172:65be27845400 16917 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
AnnaBridge 172:65be27845400 16918 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16919 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
AnnaBridge 172:65be27845400 16920 #define SPDIFRX_CR_RXSTEO_Pos (3U)
AnnaBridge 172:65be27845400 16921 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16922 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
AnnaBridge 172:65be27845400 16923 #define SPDIFRX_CR_DRFMT_Pos (4U)
AnnaBridge 172:65be27845400 16924 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 16925 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
AnnaBridge 172:65be27845400 16926 #define SPDIFRX_CR_PMSK_Pos (6U)
AnnaBridge 172:65be27845400 16927 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16928 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
AnnaBridge 172:65be27845400 16929 #define SPDIFRX_CR_VMSK_Pos (7U)
AnnaBridge 172:65be27845400 16930 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 16931 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
AnnaBridge 172:65be27845400 16932 #define SPDIFRX_CR_CUMSK_Pos (8U)
AnnaBridge 172:65be27845400 16933 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 16934 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
AnnaBridge 172:65be27845400 16935 #define SPDIFRX_CR_PTMSK_Pos (9U)
AnnaBridge 172:65be27845400 16936 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 16937 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
AnnaBridge 172:65be27845400 16938 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
AnnaBridge 172:65be27845400 16939 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 16940 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
AnnaBridge 172:65be27845400 16941 #define SPDIFRX_CR_CHSEL_Pos (11U)
AnnaBridge 172:65be27845400 16942 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 16943 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
AnnaBridge 172:65be27845400 16944 #define SPDIFRX_CR_NBTR_Pos (12U)
AnnaBridge 172:65be27845400 16945 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 16946 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
AnnaBridge 172:65be27845400 16947 #define SPDIFRX_CR_WFA_Pos (14U)
AnnaBridge 172:65be27845400 16948 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 16949 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
AnnaBridge 172:65be27845400 16950 #define SPDIFRX_CR_INSEL_Pos (16U)
AnnaBridge 172:65be27845400 16951 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 16952 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
AnnaBridge 172:65be27845400 16953 #define SPDIFRX_CR_CKSEN_Pos (20U)
AnnaBridge 172:65be27845400 16954 #define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 16955 #define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
AnnaBridge 172:65be27845400 16956 #define SPDIFRX_CR_CKSBKPEN_Pos (21U)
AnnaBridge 172:65be27845400 16957 #define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 16958 #define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
AnnaBridge 172:65be27845400 16959
AnnaBridge 172:65be27845400 16960 /******************* Bit definition for SPDIFRX_IMR register *******************/
AnnaBridge 172:65be27845400 16961 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
AnnaBridge 172:65be27845400 16962 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16963 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
AnnaBridge 172:65be27845400 16964 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
AnnaBridge 172:65be27845400 16965 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16966 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
AnnaBridge 172:65be27845400 16967 #define SPDIFRX_IMR_PERRIE_Pos (2U)
AnnaBridge 172:65be27845400 16968 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16969 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
AnnaBridge 172:65be27845400 16970 #define SPDIFRX_IMR_OVRIE_Pos (3U)
AnnaBridge 172:65be27845400 16971 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16972 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
AnnaBridge 172:65be27845400 16973 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
AnnaBridge 172:65be27845400 16974 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16975 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
AnnaBridge 172:65be27845400 16976 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
AnnaBridge 172:65be27845400 16977 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 16978 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
AnnaBridge 172:65be27845400 16979 #define SPDIFRX_IMR_IFEIE_Pos (6U)
AnnaBridge 172:65be27845400 16980 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 16981 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
AnnaBridge 172:65be27845400 16982
AnnaBridge 172:65be27845400 16983 /******************* Bit definition for SPDIFRX_SR register *******************/
AnnaBridge 172:65be27845400 16984 #define SPDIFRX_SR_RXNE_Pos (0U)
AnnaBridge 172:65be27845400 16985 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 16986 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
AnnaBridge 172:65be27845400 16987 #define SPDIFRX_SR_CSRNE_Pos (1U)
AnnaBridge 172:65be27845400 16988 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 16989 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
AnnaBridge 172:65be27845400 16990 #define SPDIFRX_SR_PERR_Pos (2U)
AnnaBridge 172:65be27845400 16991 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 16992 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
AnnaBridge 172:65be27845400 16993 #define SPDIFRX_SR_OVR_Pos (3U)
AnnaBridge 172:65be27845400 16994 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 16995 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
AnnaBridge 172:65be27845400 16996 #define SPDIFRX_SR_SBD_Pos (4U)
AnnaBridge 172:65be27845400 16997 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 16998 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
AnnaBridge 172:65be27845400 16999 #define SPDIFRX_SR_SYNCD_Pos (5U)
AnnaBridge 172:65be27845400 17000 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17001 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
AnnaBridge 172:65be27845400 17002 #define SPDIFRX_SR_FERR_Pos (6U)
AnnaBridge 172:65be27845400 17003 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17004 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
AnnaBridge 172:65be27845400 17005 #define SPDIFRX_SR_SERR_Pos (7U)
AnnaBridge 172:65be27845400 17006 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17007 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
AnnaBridge 172:65be27845400 17008 #define SPDIFRX_SR_TERR_Pos (8U)
AnnaBridge 172:65be27845400 17009 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17010 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
AnnaBridge 172:65be27845400 17011 #define SPDIFRX_SR_WIDTH5_Pos (16U)
AnnaBridge 172:65be27845400 17012 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
AnnaBridge 172:65be27845400 17013 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
AnnaBridge 172:65be27845400 17014
AnnaBridge 172:65be27845400 17015 /******************* Bit definition for SPDIFRX_IFCR register *******************/
AnnaBridge 172:65be27845400 17016 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
AnnaBridge 172:65be27845400 17017 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17018 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
AnnaBridge 172:65be27845400 17019 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
AnnaBridge 172:65be27845400 17020 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17021 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
AnnaBridge 172:65be27845400 17022 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
AnnaBridge 172:65be27845400 17023 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17024 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
AnnaBridge 172:65be27845400 17025 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
AnnaBridge 172:65be27845400 17026 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17027 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
AnnaBridge 172:65be27845400 17028
AnnaBridge 172:65be27845400 17029 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
AnnaBridge 172:65be27845400 17030 #define SPDIFRX_DR0_DR_Pos (0U)
AnnaBridge 172:65be27845400 17031 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
AnnaBridge 172:65be27845400 17032 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
AnnaBridge 172:65be27845400 17033 #define SPDIFRX_DR0_PE_Pos (24U)
AnnaBridge 172:65be27845400 17034 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17035 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
AnnaBridge 172:65be27845400 17036 #define SPDIFRX_DR0_V_Pos (25U)
AnnaBridge 172:65be27845400 17037 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 17038 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
AnnaBridge 172:65be27845400 17039 #define SPDIFRX_DR0_U_Pos (26U)
AnnaBridge 172:65be27845400 17040 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 17041 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
AnnaBridge 172:65be27845400 17042 #define SPDIFRX_DR0_C_Pos (27U)
AnnaBridge 172:65be27845400 17043 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 17044 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
AnnaBridge 172:65be27845400 17045 #define SPDIFRX_DR0_PT_Pos (28U)
AnnaBridge 172:65be27845400 17046 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
AnnaBridge 172:65be27845400 17047 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
AnnaBridge 172:65be27845400 17048
AnnaBridge 172:65be27845400 17049 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
AnnaBridge 172:65be27845400 17050 #define SPDIFRX_DR1_DR_Pos (8U)
AnnaBridge 172:65be27845400 17051 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
AnnaBridge 172:65be27845400 17052 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
AnnaBridge 172:65be27845400 17053 #define SPDIFRX_DR1_PT_Pos (4U)
AnnaBridge 172:65be27845400 17054 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 17055 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
AnnaBridge 172:65be27845400 17056 #define SPDIFRX_DR1_C_Pos (3U)
AnnaBridge 172:65be27845400 17057 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17058 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
AnnaBridge 172:65be27845400 17059 #define SPDIFRX_DR1_U_Pos (2U)
AnnaBridge 172:65be27845400 17060 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17061 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
AnnaBridge 172:65be27845400 17062 #define SPDIFRX_DR1_V_Pos (1U)
AnnaBridge 172:65be27845400 17063 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17064 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
AnnaBridge 172:65be27845400 17065 #define SPDIFRX_DR1_PE_Pos (0U)
AnnaBridge 172:65be27845400 17066 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17067 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
AnnaBridge 172:65be27845400 17068
AnnaBridge 172:65be27845400 17069 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
AnnaBridge 172:65be27845400 17070 #define SPDIFRX_DR1_DRNL1_Pos (16U)
AnnaBridge 172:65be27845400 17071 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 17072 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
AnnaBridge 172:65be27845400 17073 #define SPDIFRX_DR1_DRNL2_Pos (0U)
AnnaBridge 172:65be27845400 17074 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 17075 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
AnnaBridge 172:65be27845400 17076
AnnaBridge 172:65be27845400 17077 /******************* Bit definition for SPDIFRX_CSR register *******************/
AnnaBridge 172:65be27845400 17078 #define SPDIFRX_CSR_USR_Pos (0U)
AnnaBridge 172:65be27845400 17079 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 17080 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
AnnaBridge 172:65be27845400 17081 #define SPDIFRX_CSR_CS_Pos (16U)
AnnaBridge 172:65be27845400 17082 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 17083 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
AnnaBridge 172:65be27845400 17084 #define SPDIFRX_CSR_SOB_Pos (24U)
AnnaBridge 172:65be27845400 17085 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17086 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
AnnaBridge 172:65be27845400 17087
AnnaBridge 172:65be27845400 17088 /******************* Bit definition for SPDIFRX_DIR register *******************/
AnnaBridge 172:65be27845400 17089 #define SPDIFRX_DIR_THI_Pos (0U)
AnnaBridge 172:65be27845400 17090 #define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
AnnaBridge 172:65be27845400 17091 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
AnnaBridge 172:65be27845400 17092 #define SPDIFRX_DIR_TLO_Pos (16U)
AnnaBridge 172:65be27845400 17093 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
AnnaBridge 172:65be27845400 17094 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
AnnaBridge 172:65be27845400 17095
AnnaBridge 172:65be27845400 17096 /******************* Bit definition for SPDIFRX_VERR register *******************/
AnnaBridge 172:65be27845400 17097 #define SPDIFRX_VERR_MINREV_Pos (0U)
AnnaBridge 172:65be27845400 17098 #define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 17099 #define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
AnnaBridge 172:65be27845400 17100 #define SPDIFRX_VERR_MAJREV_Pos (4U)
AnnaBridge 172:65be27845400 17101 #define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 17102 #define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
AnnaBridge 172:65be27845400 17103
AnnaBridge 172:65be27845400 17104 /******************* Bit definition for SPDIFRX_IDR register *******************/
AnnaBridge 172:65be27845400 17105 #define SPDIFRX_IDR_ID_Pos (0U)
AnnaBridge 172:65be27845400 17106 #define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17107 #define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
AnnaBridge 172:65be27845400 17108
AnnaBridge 172:65be27845400 17109 /******************* Bit definition for SPDIFRX_SIDR register *******************/
AnnaBridge 172:65be27845400 17110 #define SPDIFRX_SIDR_SID_Pos (0U)
AnnaBridge 172:65be27845400 17111 #define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17112 #define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
AnnaBridge 172:65be27845400 17113
AnnaBridge 172:65be27845400 17114 /******************************************************************************/
AnnaBridge 172:65be27845400 17115 /* */
AnnaBridge 172:65be27845400 17116 /* Serial Audio Interface */
AnnaBridge 172:65be27845400 17117 /* */
AnnaBridge 172:65be27845400 17118 /******************************************************************************/
AnnaBridge 172:65be27845400 17119 /******************************* SAI VERSION ********************************/
AnnaBridge 172:65be27845400 17120 #define SAI_VER_V2_X
AnnaBridge 172:65be27845400 17121
AnnaBridge 172:65be27845400 17122 /******************** Bit definition for SAI_GCR register *******************/
AnnaBridge 172:65be27845400 17123 #define SAI_GCR_SYNCIN_Pos (0U)
AnnaBridge 172:65be27845400 17124 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 17125 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
AnnaBridge 172:65be27845400 17126 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17127 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17128
AnnaBridge 172:65be27845400 17129 #define SAI_GCR_SYNCOUT_Pos (4U)
AnnaBridge 172:65be27845400 17130 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 17131 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
AnnaBridge 172:65be27845400 17132 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17133 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17134
AnnaBridge 172:65be27845400 17135 /******************* Bit definition for SAI_xCR1 register *******************/
AnnaBridge 172:65be27845400 17136 #define SAI_xCR1_MODE_Pos (0U)
AnnaBridge 172:65be27845400 17137 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 17138 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
AnnaBridge 172:65be27845400 17139 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17140 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17141
AnnaBridge 172:65be27845400 17142 #define SAI_xCR1_PRTCFG_Pos (2U)
AnnaBridge 172:65be27845400 17143 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 17144 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
AnnaBridge 172:65be27845400 17145 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17146 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17147
AnnaBridge 172:65be27845400 17148 #define SAI_xCR1_DS_Pos (5U)
AnnaBridge 172:65be27845400 17149 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
AnnaBridge 172:65be27845400 17150 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
AnnaBridge 172:65be27845400 17151 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17152 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17153 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17154
AnnaBridge 172:65be27845400 17155 #define SAI_xCR1_LSBFIRST_Pos (8U)
AnnaBridge 172:65be27845400 17156 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17157 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
AnnaBridge 172:65be27845400 17158 #define SAI_xCR1_CKSTR_Pos (9U)
AnnaBridge 172:65be27845400 17159 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17160 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
AnnaBridge 172:65be27845400 17161
AnnaBridge 172:65be27845400 17162 #define SAI_xCR1_SYNCEN_Pos (10U)
AnnaBridge 172:65be27845400 17163 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 17164 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
AnnaBridge 172:65be27845400 17165 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17166 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17167
AnnaBridge 172:65be27845400 17168 #define SAI_xCR1_MONO_Pos (12U)
AnnaBridge 172:65be27845400 17169 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17170 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
AnnaBridge 172:65be27845400 17171 #define SAI_xCR1_OUTDRIV_Pos (13U)
AnnaBridge 172:65be27845400 17172 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17173 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
AnnaBridge 172:65be27845400 17174 #define SAI_xCR1_SAIEN_Pos (16U)
AnnaBridge 172:65be27845400 17175 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17176 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
AnnaBridge 172:65be27845400 17177 #define SAI_xCR1_DMAEN_Pos (17U)
AnnaBridge 172:65be27845400 17178 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17179 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
AnnaBridge 172:65be27845400 17180 #define SAI_xCR1_NOMCK_Pos (19U)
AnnaBridge 172:65be27845400 17181 #define SAI_xCR1_NOMCK_Msk (0x1UL << SAI_xCR1_NOMCK_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 17182 #define SAI_xCR1_NOMCK SAI_xCR1_NOMCK_Msk /*!<No Divider Configuration */
AnnaBridge 172:65be27845400 17183
AnnaBridge 172:65be27845400 17184 #define SAI_xCR1_MCKDIV_Pos (20U)
AnnaBridge 172:65be27845400 17185 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
AnnaBridge 172:65be27845400 17186 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
AnnaBridge 172:65be27845400 17187 #define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 17188 #define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 17189 #define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 17190 #define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 17191 #define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17192 #define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 17193
AnnaBridge 172:65be27845400 17194 #define SAI_xCR1_MCKEN_Pos (27U)
AnnaBridge 172:65be27845400 17195 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 17196 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
AnnaBridge 172:65be27845400 17197
AnnaBridge 172:65be27845400 17198 #define SAI_xCR1_OSR_Pos (26U)
AnnaBridge 172:65be27845400 17199 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 17200 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
AnnaBridge 172:65be27845400 17201
AnnaBridge 172:65be27845400 17202 /******************* Bit definition for SAI_xCR2 register *******************/
AnnaBridge 172:65be27845400 17203 #define SAI_xCR2_FTH_Pos (0U)
AnnaBridge 172:65be27845400 17204 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 17205 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
AnnaBridge 172:65be27845400 17206 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17207 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17208 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17209
AnnaBridge 172:65be27845400 17210 #define SAI_xCR2_FFLUSH_Pos (3U)
AnnaBridge 172:65be27845400 17211 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17212 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
AnnaBridge 172:65be27845400 17213 #define SAI_xCR2_TRIS_Pos (4U)
AnnaBridge 172:65be27845400 17214 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17215 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
AnnaBridge 172:65be27845400 17216 #define SAI_xCR2_MUTE_Pos (5U)
AnnaBridge 172:65be27845400 17217 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17218 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
AnnaBridge 172:65be27845400 17219 #define SAI_xCR2_MUTEVAL_Pos (6U)
AnnaBridge 172:65be27845400 17220 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17221 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
AnnaBridge 172:65be27845400 17222
AnnaBridge 172:65be27845400 17223 #define SAI_xCR2_MUTECNT_Pos (7U)
AnnaBridge 172:65be27845400 17224 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
AnnaBridge 172:65be27845400 17225 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
AnnaBridge 172:65be27845400 17226 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17227 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17228 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17229 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17230 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17231 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17232
AnnaBridge 172:65be27845400 17233 #define SAI_xCR2_CPL_Pos (13U)
AnnaBridge 172:65be27845400 17234 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17235 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
AnnaBridge 172:65be27845400 17236
AnnaBridge 172:65be27845400 17237 #define SAI_xCR2_COMP_Pos (14U)
AnnaBridge 172:65be27845400 17238 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 17239 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
AnnaBridge 172:65be27845400 17240 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17241 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 17242
AnnaBridge 172:65be27845400 17243 /****************** Bit definition for SAI_xFRCR register *******************/
AnnaBridge 172:65be27845400 17244 #define SAI_xFRCR_FRL_Pos (0U)
AnnaBridge 172:65be27845400 17245 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 17246 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
AnnaBridge 172:65be27845400 17247 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17248 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17249 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17250 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17251 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17252 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17253 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17254 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17255
AnnaBridge 172:65be27845400 17256 #define SAI_xFRCR_FSALL_Pos (8U)
AnnaBridge 172:65be27845400 17257 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
AnnaBridge 172:65be27845400 17258 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
AnnaBridge 172:65be27845400 17259 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17260 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17261 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17262 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17263 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17264 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17265 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17266
AnnaBridge 172:65be27845400 17267 #define SAI_xFRCR_FSDEF_Pos (16U)
AnnaBridge 172:65be27845400 17268 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17269 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
AnnaBridge 172:65be27845400 17270 #define SAI_xFRCR_FSPOL_Pos (17U)
AnnaBridge 172:65be27845400 17271 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17272 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
AnnaBridge 172:65be27845400 17273 #define SAI_xFRCR_FSOFF_Pos (18U)
AnnaBridge 172:65be27845400 17274 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 17275 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
AnnaBridge 172:65be27845400 17276
AnnaBridge 172:65be27845400 17277 /* Legacy define */
AnnaBridge 172:65be27845400 17278 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
AnnaBridge 172:65be27845400 17279
AnnaBridge 172:65be27845400 17280 /****************** Bit definition for SAI_xSLOTR register *******************/
AnnaBridge 172:65be27845400 17281 #define SAI_xSLOTR_FBOFF_Pos (0U)
AnnaBridge 172:65be27845400 17282 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 17283 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
AnnaBridge 172:65be27845400 17284 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17285 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17286 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17287 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17288 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17289
AnnaBridge 172:65be27845400 17290 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
AnnaBridge 172:65be27845400 17291 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 17292 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
AnnaBridge 172:65be27845400 17293 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17294 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17295
AnnaBridge 172:65be27845400 17296 #define SAI_xSLOTR_NBSLOT_Pos (8U)
AnnaBridge 172:65be27845400 17297 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 17298 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
AnnaBridge 172:65be27845400 17299 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17300 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17301 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17302 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17303
AnnaBridge 172:65be27845400 17304 #define SAI_xSLOTR_SLOTEN_Pos (16U)
AnnaBridge 172:65be27845400 17305 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 17306 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
AnnaBridge 172:65be27845400 17307
AnnaBridge 172:65be27845400 17308 /******************* Bit definition for SAI_xIMR register *******************/
AnnaBridge 172:65be27845400 17309 #define SAI_xIMR_OVRUDRIE_Pos (0U)
AnnaBridge 172:65be27845400 17310 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17311 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
AnnaBridge 172:65be27845400 17312 #define SAI_xIMR_MUTEDETIE_Pos (1U)
AnnaBridge 172:65be27845400 17313 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17314 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
AnnaBridge 172:65be27845400 17315 #define SAI_xIMR_WCKCFGIE_Pos (2U)
AnnaBridge 172:65be27845400 17316 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17317 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
AnnaBridge 172:65be27845400 17318 #define SAI_xIMR_FREQIE_Pos (3U)
AnnaBridge 172:65be27845400 17319 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17320 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
AnnaBridge 172:65be27845400 17321 #define SAI_xIMR_CNRDYIE_Pos (4U)
AnnaBridge 172:65be27845400 17322 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17323 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
AnnaBridge 172:65be27845400 17324 #define SAI_xIMR_AFSDETIE_Pos (5U)
AnnaBridge 172:65be27845400 17325 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17326 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
AnnaBridge 172:65be27845400 17327 #define SAI_xIMR_LFSDETIE_Pos (6U)
AnnaBridge 172:65be27845400 17328 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17329 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
AnnaBridge 172:65be27845400 17330
AnnaBridge 172:65be27845400 17331 /******************** Bit definition for SAI_xSR register *******************/
AnnaBridge 172:65be27845400 17332 #define SAI_xSR_OVRUDR_Pos (0U)
AnnaBridge 172:65be27845400 17333 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17334 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
AnnaBridge 172:65be27845400 17335 #define SAI_xSR_MUTEDET_Pos (1U)
AnnaBridge 172:65be27845400 17336 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17337 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
AnnaBridge 172:65be27845400 17338 #define SAI_xSR_WCKCFG_Pos (2U)
AnnaBridge 172:65be27845400 17339 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17340 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
AnnaBridge 172:65be27845400 17341 #define SAI_xSR_FREQ_Pos (3U)
AnnaBridge 172:65be27845400 17342 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17343 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
AnnaBridge 172:65be27845400 17344 #define SAI_xSR_CNRDY_Pos (4U)
AnnaBridge 172:65be27845400 17345 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17346 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
AnnaBridge 172:65be27845400 17347 #define SAI_xSR_AFSDET_Pos (5U)
AnnaBridge 172:65be27845400 17348 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17349 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
AnnaBridge 172:65be27845400 17350 #define SAI_xSR_LFSDET_Pos (6U)
AnnaBridge 172:65be27845400 17351 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17352 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
AnnaBridge 172:65be27845400 17353
AnnaBridge 172:65be27845400 17354 #define SAI_xSR_FLVL_Pos (16U)
AnnaBridge 172:65be27845400 17355 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 17356 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
AnnaBridge 172:65be27845400 17357 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17358 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17359 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 17360
AnnaBridge 172:65be27845400 17361 /****************** Bit definition for SAI_xCLRFR register ******************/
AnnaBridge 172:65be27845400 17362 #define SAI_xCLRFR_COVRUDR_Pos (0U)
AnnaBridge 172:65be27845400 17363 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17364 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
AnnaBridge 172:65be27845400 17365 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
AnnaBridge 172:65be27845400 17366 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17367 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
AnnaBridge 172:65be27845400 17368 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
AnnaBridge 172:65be27845400 17369 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17370 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
AnnaBridge 172:65be27845400 17371 #define SAI_xCLRFR_CFREQ_Pos (3U)
AnnaBridge 172:65be27845400 17372 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17373 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
AnnaBridge 172:65be27845400 17374 #define SAI_xCLRFR_CCNRDY_Pos (4U)
AnnaBridge 172:65be27845400 17375 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17376 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
AnnaBridge 172:65be27845400 17377 #define SAI_xCLRFR_CAFSDET_Pos (5U)
AnnaBridge 172:65be27845400 17378 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17379 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
AnnaBridge 172:65be27845400 17380 #define SAI_xCLRFR_CLFSDET_Pos (6U)
AnnaBridge 172:65be27845400 17381 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17382 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
AnnaBridge 172:65be27845400 17383
AnnaBridge 172:65be27845400 17384 /****************** Bit definition for SAI_xDR register *********************/
AnnaBridge 172:65be27845400 17385 #define SAI_xDR_DATA_Pos (0U)
AnnaBridge 172:65be27845400 17386 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17387 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
AnnaBridge 172:65be27845400 17388
AnnaBridge 172:65be27845400 17389 /******************* Bit definition for SAI_PDMCR register ******************/
AnnaBridge 172:65be27845400 17390 #define SAI_PDMCR_PDMEN_Pos (0U)
AnnaBridge 172:65be27845400 17391 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17392 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
AnnaBridge 172:65be27845400 17393
AnnaBridge 172:65be27845400 17394 #define SAI_PDMCR_MICNBR_Pos (4U)
AnnaBridge 172:65be27845400 17395 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 17396 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
AnnaBridge 172:65be27845400 17397 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17398 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17399
AnnaBridge 172:65be27845400 17400 #define SAI_PDMCR_CKEN1_Pos (8U)
AnnaBridge 172:65be27845400 17401 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17402 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
AnnaBridge 172:65be27845400 17403 #define SAI_PDMCR_CKEN2_Pos (9U)
AnnaBridge 172:65be27845400 17404 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17405 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
AnnaBridge 172:65be27845400 17406 #define SAI_PDMCR_CKEN3_Pos (10U)
AnnaBridge 172:65be27845400 17407 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17408 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
AnnaBridge 172:65be27845400 17409 #define SAI_PDMCR_CKEN4_Pos (11U)
AnnaBridge 172:65be27845400 17410 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17411 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
AnnaBridge 172:65be27845400 17412
AnnaBridge 172:65be27845400 17413 /****************** Bit definition for SAI_PDMDLY register ******************/
AnnaBridge 172:65be27845400 17414 #define SAI_PDMDLY_DLYM1L_Pos (0U)
AnnaBridge 172:65be27845400 17415 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 17416 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
AnnaBridge 172:65be27845400 17417 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17418 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17419 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17420
AnnaBridge 172:65be27845400 17421 #define SAI_PDMDLY_DLYM1R_Pos (4U)
AnnaBridge 172:65be27845400 17422 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 17423 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
AnnaBridge 172:65be27845400 17424 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17425 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17426 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17427
AnnaBridge 172:65be27845400 17428 #define SAI_PDMDLY_DLYM2L_Pos (8U)
AnnaBridge 172:65be27845400 17429 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 17430 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
AnnaBridge 172:65be27845400 17431 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17432 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17433 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17434
AnnaBridge 172:65be27845400 17435 #define SAI_PDMDLY_DLYM2R_Pos (12U)
AnnaBridge 172:65be27845400 17436 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 17437 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
AnnaBridge 172:65be27845400 17438 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17439 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17440 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17441
AnnaBridge 172:65be27845400 17442 #define SAI_PDMDLY_DLYM3L_Pos (16U)
AnnaBridge 172:65be27845400 17443 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 17444 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
AnnaBridge 172:65be27845400 17445 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17446 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17447 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 17448
AnnaBridge 172:65be27845400 17449 #define SAI_PDMDLY_DLYM3R_Pos (20U)
AnnaBridge 172:65be27845400 17450 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
AnnaBridge 172:65be27845400 17451 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
AnnaBridge 172:65be27845400 17452 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 17453 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 17454 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 17455
AnnaBridge 172:65be27845400 17456 #define SAI_PDMDLY_DLYM4L_Pos (24U)
AnnaBridge 172:65be27845400 17457 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
AnnaBridge 172:65be27845400 17458 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
AnnaBridge 172:65be27845400 17459 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17460 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 17461 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 17462
AnnaBridge 172:65be27845400 17463 #define SAI_PDMDLY_DLYM4R_Pos (28U)
AnnaBridge 172:65be27845400 17464 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 17465 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
AnnaBridge 172:65be27845400 17466 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 17467 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 17468 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 17469
AnnaBridge 172:65be27845400 17470 /******************************************************************************/
AnnaBridge 172:65be27845400 17471 /* */
AnnaBridge 172:65be27845400 17472 /* SDMMC Interface */
AnnaBridge 172:65be27845400 17473 /* */
AnnaBridge 172:65be27845400 17474 /******************************************************************************/
AnnaBridge 172:65be27845400 17475 /****************** Bit definition for SDMMC_POWER register ******************/
AnnaBridge 172:65be27845400 17476 #define SDMMC_POWER_PWRCTRL_Pos (0U)
AnnaBridge 172:65be27845400 17477 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 17478 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 172:65be27845400 17479 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17480 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17481 #define SDMMC_POWER_VSWITCH_Pos (2U)
AnnaBridge 172:65be27845400 17482 #define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17483 #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
AnnaBridge 172:65be27845400 17484 #define SDMMC_POWER_VSWITCHEN_Pos (3U)
AnnaBridge 172:65be27845400 17485 #define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17486 #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
AnnaBridge 172:65be27845400 17487 #define SDMMC_POWER_DIRPOL_Pos (4U)
AnnaBridge 172:65be27845400 17488 #define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17489 #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
AnnaBridge 172:65be27845400 17490
AnnaBridge 172:65be27845400 17491 /****************** Bit definition for SDMMC_CLKCR register ******************/
AnnaBridge 172:65be27845400 17492 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 172:65be27845400 17493 #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
AnnaBridge 172:65be27845400 17494 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 172:65be27845400 17495 #define SDMMC_CLKCR_PWRSAV_Pos (12U)
AnnaBridge 172:65be27845400 17496 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17497 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 172:65be27845400 17498
AnnaBridge 172:65be27845400 17499 #define SDMMC_CLKCR_WIDBUS_Pos (14U)
AnnaBridge 172:65be27845400 17500 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 17501 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 172:65be27845400 17502 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17503 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 17504
AnnaBridge 172:65be27845400 17505 #define SDMMC_CLKCR_NEGEDGE_Pos (16U)
AnnaBridge 172:65be27845400 17506 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17507 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
AnnaBridge 172:65be27845400 17508 #define SDMMC_CLKCR_HWFC_EN_Pos (17U)
AnnaBridge 172:65be27845400 17509 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17510 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
AnnaBridge 172:65be27845400 17511 #define SDMMC_CLKCR_DDR_Pos (18U)
AnnaBridge 172:65be27845400 17512 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 17513 #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
AnnaBridge 172:65be27845400 17514 #define SDMMC_CLKCR_BUSSPEED_Pos (19U)
AnnaBridge 172:65be27845400 17515 #define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 17516 #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
AnnaBridge 172:65be27845400 17517 #define SDMMC_CLKCR_SELCLKRX_Pos (20U)
AnnaBridge 172:65be27845400 17518 #define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 17519 #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
AnnaBridge 172:65be27845400 17520 #define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 17521 #define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 17522
AnnaBridge 172:65be27845400 17523 /******************* Bit definition for SDMMC_ARG register *******************/
AnnaBridge 172:65be27845400 17524 #define SDMMC_ARG_CMDARG_Pos (0U)
AnnaBridge 172:65be27845400 17525 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17526 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
AnnaBridge 172:65be27845400 17527
AnnaBridge 172:65be27845400 17528 /******************* Bit definition for SDMMC_CMD register *******************/
AnnaBridge 172:65be27845400 17529 #define SDMMC_CMD_CMDINDEX_Pos (0U)
AnnaBridge 172:65be27845400 17530 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 17531 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 172:65be27845400 17532 #define SDMMC_CMD_CMDTRANS_Pos (6U)
AnnaBridge 172:65be27845400 17533 #define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17534 #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
AnnaBridge 172:65be27845400 17535 #define SDMMC_CMD_CMDSTOP_Pos (7U)
AnnaBridge 172:65be27845400 17536 #define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17537 #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
AnnaBridge 172:65be27845400 17538
AnnaBridge 172:65be27845400 17539 #define SDMMC_CMD_WAITRESP_Pos (8U)
AnnaBridge 172:65be27845400 17540 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 17541 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 172:65be27845400 17542 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17543 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17544
AnnaBridge 172:65be27845400 17545 #define SDMMC_CMD_WAITINT_Pos (10U)
AnnaBridge 172:65be27845400 17546 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17547 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 172:65be27845400 17548 #define SDMMC_CMD_WAITPEND_Pos (11U)
AnnaBridge 172:65be27845400 17549 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17550 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 172:65be27845400 17551 #define SDMMC_CMD_CPSMEN_Pos (12U)
AnnaBridge 172:65be27845400 17552 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17553 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 172:65be27845400 17554 #define SDMMC_CMD_DTHOLD_Pos (13U)
AnnaBridge 172:65be27845400 17555 #define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17556 #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
AnnaBridge 172:65be27845400 17557 #define SDMMC_CMD_BOOTMODE_Pos (14U)
AnnaBridge 172:65be27845400 17558 #define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17559 #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
AnnaBridge 172:65be27845400 17560 #define SDMMC_CMD_BOOTEN_Pos (15U)
AnnaBridge 172:65be27845400 17561 #define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 17562 #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
AnnaBridge 172:65be27845400 17563 #define SDMMC_CMD_CMDSUSPEND_Pos (16U)
AnnaBridge 172:65be27845400 17564 #define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17565 #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
AnnaBridge 172:65be27845400 17566
AnnaBridge 172:65be27845400 17567 /***************** Bit definition for SDMMC_RESPCMD register *****************/
AnnaBridge 172:65be27845400 17568 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 172:65be27845400 17569 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 172:65be27845400 17570 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
AnnaBridge 172:65be27845400 17571
AnnaBridge 172:65be27845400 17572 /****************** Bit definition for SDMMC_RESP0 register ******************/
AnnaBridge 172:65be27845400 17573 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 172:65be27845400 17574 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17575 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 17576
AnnaBridge 172:65be27845400 17577 /****************** Bit definition for SDMMC_RESP1 register ******************/
AnnaBridge 172:65be27845400 17578 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 172:65be27845400 17579 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17580 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 17581
AnnaBridge 172:65be27845400 17582 /****************** Bit definition for SDMMC_RESP2 register ******************/
AnnaBridge 172:65be27845400 17583 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 172:65be27845400 17584 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17585 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 17586
AnnaBridge 172:65be27845400 17587 /****************** Bit definition for SDMMC_RESP3 register ******************/
AnnaBridge 172:65be27845400 17588 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 172:65be27845400 17589 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17590 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 17591
AnnaBridge 172:65be27845400 17592 /****************** Bit definition for SDMMC_RESP4 register ******************/
AnnaBridge 172:65be27845400 17593 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 172:65be27845400 17594 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17595 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
AnnaBridge 172:65be27845400 17596
AnnaBridge 172:65be27845400 17597 /****************** Bit definition for SDMMC_DTIMER register *****************/
AnnaBridge 172:65be27845400 17598 #define SDMMC_DTIMER_DATATIME_Pos (0U)
AnnaBridge 172:65be27845400 17599 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17600 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
AnnaBridge 172:65be27845400 17601
AnnaBridge 172:65be27845400 17602 /****************** Bit definition for SDMMC_DLEN register *******************/
AnnaBridge 172:65be27845400 17603 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 172:65be27845400 17604 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 172:65be27845400 17605 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
AnnaBridge 172:65be27845400 17606
AnnaBridge 172:65be27845400 17607 /****************** Bit definition for SDMMC_DCTRL register ******************/
AnnaBridge 172:65be27845400 17608 #define SDMMC_DCTRL_DTEN_Pos (0U)
AnnaBridge 172:65be27845400 17609 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17610 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 172:65be27845400 17611 #define SDMMC_DCTRL_DTDIR_Pos (1U)
AnnaBridge 172:65be27845400 17612 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17613 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 172:65be27845400 17614 #define SDMMC_DCTRL_DTMODE_Pos (2U)
AnnaBridge 172:65be27845400 17615 #define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 17616 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
AnnaBridge 172:65be27845400 17617 #define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17618 #define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17619
AnnaBridge 172:65be27845400 17620 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 172:65be27845400 17621 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 17622 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 172:65be27845400 17623 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17624 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17625 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17626 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17627
AnnaBridge 172:65be27845400 17628 #define SDMMC_DCTRL_RWSTART_Pos (8U)
AnnaBridge 172:65be27845400 17629 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17630 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 172:65be27845400 17631 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 172:65be27845400 17632 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17633 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 172:65be27845400 17634 #define SDMMC_DCTRL_RWMOD_Pos (10U)
AnnaBridge 172:65be27845400 17635 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17636 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 172:65be27845400 17637 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 172:65be27845400 17638 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17639 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
AnnaBridge 172:65be27845400 17640 #define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
AnnaBridge 172:65be27845400 17641 #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17642 #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
AnnaBridge 172:65be27845400 17643 #define SDMMC_DCTRL_FIFORST_Pos (13U)
AnnaBridge 172:65be27845400 17644 #define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17645 #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
AnnaBridge 172:65be27845400 17646
AnnaBridge 172:65be27845400 17647 /****************** Bit definition for SDMMC_DCOUNT register *****************/
AnnaBridge 172:65be27845400 17648 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 172:65be27845400 17649 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 172:65be27845400 17650 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
AnnaBridge 172:65be27845400 17651
AnnaBridge 172:65be27845400 17652 /****************** Bit definition for SDMMC_STA register ********************/
AnnaBridge 172:65be27845400 17653 #define SDMMC_STA_CCRCFAIL_Pos (0U)
AnnaBridge 172:65be27845400 17654 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17655 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 172:65be27845400 17656 #define SDMMC_STA_DCRCFAIL_Pos (1U)
AnnaBridge 172:65be27845400 17657 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17658 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 172:65be27845400 17659 #define SDMMC_STA_CTIMEOUT_Pos (2U)
AnnaBridge 172:65be27845400 17660 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17661 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 172:65be27845400 17662 #define SDMMC_STA_DTIMEOUT_Pos (3U)
AnnaBridge 172:65be27845400 17663 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17664 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 172:65be27845400 17665 #define SDMMC_STA_TXUNDERR_Pos (4U)
AnnaBridge 172:65be27845400 17666 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17667 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 172:65be27845400 17668 #define SDMMC_STA_RXOVERR_Pos (5U)
AnnaBridge 172:65be27845400 17669 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17670 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 172:65be27845400 17671 #define SDMMC_STA_CMDREND_Pos (6U)
AnnaBridge 172:65be27845400 17672 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17673 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 172:65be27845400 17674 #define SDMMC_STA_CMDSENT_Pos (7U)
AnnaBridge 172:65be27845400 17675 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17676 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 172:65be27845400 17677 #define SDMMC_STA_DATAEND_Pos (8U)
AnnaBridge 172:65be27845400 17678 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17679 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 172:65be27845400 17680 #define SDMMC_STA_DHOLD_Pos (9U)
AnnaBridge 172:65be27845400 17681 #define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17682 #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
AnnaBridge 172:65be27845400 17683 #define SDMMC_STA_DBCKEND_Pos (10U)
AnnaBridge 172:65be27845400 17684 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17685 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 172:65be27845400 17686 #define SDMMC_STA_DABORT_Pos (11U)
AnnaBridge 172:65be27845400 17687 #define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17688 #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
AnnaBridge 172:65be27845400 17689 #define SDMMC_STA_DPSMACT_Pos (12U)
AnnaBridge 172:65be27845400 17690 #define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17691 #define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
AnnaBridge 172:65be27845400 17692 #define SDMMC_STA_CPSMACT_Pos (13U)
AnnaBridge 172:65be27845400 17693 #define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17694 #define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
AnnaBridge 172:65be27845400 17695 #define SDMMC_STA_TXFIFOHE_Pos (14U)
AnnaBridge 172:65be27845400 17696 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17697 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 172:65be27845400 17698 #define SDMMC_STA_RXFIFOHF_Pos (15U)
AnnaBridge 172:65be27845400 17699 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 17700 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 172:65be27845400 17701 #define SDMMC_STA_TXFIFOF_Pos (16U)
AnnaBridge 172:65be27845400 17702 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17703 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 172:65be27845400 17704 #define SDMMC_STA_RXFIFOF_Pos (17U)
AnnaBridge 172:65be27845400 17705 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17706 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 172:65be27845400 17707 #define SDMMC_STA_TXFIFOE_Pos (18U)
AnnaBridge 172:65be27845400 17708 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 17709 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 172:65be27845400 17710 #define SDMMC_STA_RXFIFOE_Pos (19U)
AnnaBridge 172:65be27845400 17711 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 17712 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 172:65be27845400 17713 #define SDMMC_STA_BUSYD0_Pos (20U)
AnnaBridge 172:65be27845400 17714 #define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 17715 #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
AnnaBridge 172:65be27845400 17716 #define SDMMC_STA_BUSYD0END_Pos (21U)
AnnaBridge 172:65be27845400 17717 #define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 17718 #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
AnnaBridge 172:65be27845400 17719 #define SDMMC_STA_SDIOIT_Pos (22U)
AnnaBridge 172:65be27845400 17720 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 17721 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
AnnaBridge 172:65be27845400 17722 #define SDMMC_STA_ACKFAIL_Pos (23U)
AnnaBridge 172:65be27845400 17723 #define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 17724 #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
AnnaBridge 172:65be27845400 17725 #define SDMMC_STA_ACKTIMEOUT_Pos (24U)
AnnaBridge 172:65be27845400 17726 #define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17727 #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
AnnaBridge 172:65be27845400 17728 #define SDMMC_STA_VSWEND_Pos (25U)
AnnaBridge 172:65be27845400 17729 #define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 17730 #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
AnnaBridge 172:65be27845400 17731 #define SDMMC_STA_CKSTOP_Pos (26U)
AnnaBridge 172:65be27845400 17732 #define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 17733 #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
AnnaBridge 172:65be27845400 17734 #define SDMMC_STA_IDMATE_Pos (27U)
AnnaBridge 172:65be27845400 17735 #define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 17736 #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
AnnaBridge 172:65be27845400 17737 #define SDMMC_STA_IDMABTC_Pos (28U)
AnnaBridge 172:65be27845400 17738 #define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 17739 #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
AnnaBridge 172:65be27845400 17740
AnnaBridge 172:65be27845400 17741 /******************* Bit definition for SDMMC_ICR register *******************/
AnnaBridge 172:65be27845400 17742 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 172:65be27845400 17743 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17744 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 172:65be27845400 17745 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 172:65be27845400 17746 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17747 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 172:65be27845400 17748 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 172:65be27845400 17749 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17750 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 172:65be27845400 17751 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 172:65be27845400 17752 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17753 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 172:65be27845400 17754 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 172:65be27845400 17755 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17756 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 172:65be27845400 17757 #define SDMMC_ICR_RXOVERRC_Pos (5U)
AnnaBridge 172:65be27845400 17758 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17759 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 172:65be27845400 17760 #define SDMMC_ICR_CMDRENDC_Pos (6U)
AnnaBridge 172:65be27845400 17761 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17762 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 172:65be27845400 17763 #define SDMMC_ICR_CMDSENTC_Pos (7U)
AnnaBridge 172:65be27845400 17764 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17765 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 172:65be27845400 17766 #define SDMMC_ICR_DATAENDC_Pos (8U)
AnnaBridge 172:65be27845400 17767 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17768 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 172:65be27845400 17769 #define SDMMC_ICR_DHOLDC_Pos (9U)
AnnaBridge 172:65be27845400 17770 #define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17771 #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
AnnaBridge 172:65be27845400 17772 #define SDMMC_ICR_DBCKENDC_Pos (10U)
AnnaBridge 172:65be27845400 17773 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17774 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 172:65be27845400 17775 #define SDMMC_ICR_DABORTC_Pos (11U)
AnnaBridge 172:65be27845400 17776 #define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17777 #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
AnnaBridge 172:65be27845400 17778 #define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
AnnaBridge 172:65be27845400 17779 #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 17780 #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
AnnaBridge 172:65be27845400 17781 #define SDMMC_ICR_SDIOITC_Pos (22U)
AnnaBridge 172:65be27845400 17782 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 17783 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
AnnaBridge 172:65be27845400 17784 #define SDMMC_ICR_ACKFAILC_Pos (23U)
AnnaBridge 172:65be27845400 17785 #define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 17786 #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
AnnaBridge 172:65be27845400 17787 #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
AnnaBridge 172:65be27845400 17788 #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17789 #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
AnnaBridge 172:65be27845400 17790 #define SDMMC_ICR_VSWENDC_Pos (25U)
AnnaBridge 172:65be27845400 17791 #define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 17792 #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
AnnaBridge 172:65be27845400 17793 #define SDMMC_ICR_CKSTOPC_Pos (26U)
AnnaBridge 172:65be27845400 17794 #define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 17795 #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
AnnaBridge 172:65be27845400 17796 #define SDMMC_ICR_IDMATEC_Pos (27U)
AnnaBridge 172:65be27845400 17797 #define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 17798 #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
AnnaBridge 172:65be27845400 17799 #define SDMMC_ICR_IDMABTCC_Pos (28U)
AnnaBridge 172:65be27845400 17800 #define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 17801 #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
AnnaBridge 172:65be27845400 17802
AnnaBridge 172:65be27845400 17803 /****************** Bit definition for SDMMC_MASK register *******************/
AnnaBridge 172:65be27845400 17804 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 172:65be27845400 17805 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17806 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 172:65be27845400 17807 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 172:65be27845400 17808 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17809 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 172:65be27845400 17810 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 172:65be27845400 17811 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17812 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 172:65be27845400 17813 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 172:65be27845400 17814 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17815 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 172:65be27845400 17816 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 172:65be27845400 17817 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 17818 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 172:65be27845400 17819 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 172:65be27845400 17820 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 17821 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 172:65be27845400 17822 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 172:65be27845400 17823 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 17824 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 172:65be27845400 17825 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 172:65be27845400 17826 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 17827 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 172:65be27845400 17828 #define SDMMC_MASK_DATAENDIE_Pos (8U)
AnnaBridge 172:65be27845400 17829 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17830 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 172:65be27845400 17831 #define SDMMC_MASK_DHOLDIE_Pos (9U)
AnnaBridge 172:65be27845400 17832 #define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17833 #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
AnnaBridge 172:65be27845400 17834 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 172:65be27845400 17835 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17836 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 172:65be27845400 17837 #define SDMMC_MASK_DABORTIE_Pos (11U)
AnnaBridge 172:65be27845400 17838 #define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17839 #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
AnnaBridge 172:65be27845400 17840
AnnaBridge 172:65be27845400 17841 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 172:65be27845400 17842 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17843 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 172:65be27845400 17844 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 172:65be27845400 17845 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 17846 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 172:65be27845400 17847
AnnaBridge 172:65be27845400 17848 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 172:65be27845400 17849 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17850 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 172:65be27845400 17851 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 172:65be27845400 17852 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 17853 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 172:65be27845400 17854
AnnaBridge 172:65be27845400 17855 #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
AnnaBridge 172:65be27845400 17856 #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 17857 #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
AnnaBridge 172:65be27845400 17858 #define SDMMC_MASK_SDIOITIE_Pos (22U)
AnnaBridge 172:65be27845400 17859 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 17860 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
AnnaBridge 172:65be27845400 17861 #define SDMMC_MASK_ACKFAILIE_Pos (23U)
AnnaBridge 172:65be27845400 17862 #define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 17863 #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
AnnaBridge 172:65be27845400 17864 #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
AnnaBridge 172:65be27845400 17865 #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17866 #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
AnnaBridge 172:65be27845400 17867 #define SDMMC_MASK_VSWENDIE_Pos (25U)
AnnaBridge 172:65be27845400 17868 #define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 17869 #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
AnnaBridge 172:65be27845400 17870 #define SDMMC_MASK_CKSTOPIE_Pos (26U)
AnnaBridge 172:65be27845400 17871 #define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 17872 #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
AnnaBridge 172:65be27845400 17873 #define SDMMC_MASK_IDMABTCIE_Pos (28U)
AnnaBridge 172:65be27845400 17874 #define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 17875 #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
AnnaBridge 172:65be27845400 17876
AnnaBridge 172:65be27845400 17877 /***************** Bit definition for SDMMC_ACKTIME register *****************/
AnnaBridge 172:65be27845400 17878 #define SDMMC_ACKTIME_ACKTIME_Pos (0U)
AnnaBridge 172:65be27845400 17879 #define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
AnnaBridge 172:65be27845400 17880 #define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
AnnaBridge 172:65be27845400 17881
AnnaBridge 172:65be27845400 17882 /****************** Bit definition for SDMMC_FIFO register *******************/
AnnaBridge 172:65be27845400 17883 #define SDMMC_FIFO_FIFODATA_Pos (0U)
AnnaBridge 172:65be27845400 17884 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 17885 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
AnnaBridge 172:65be27845400 17886
AnnaBridge 172:65be27845400 17887 /****************** Bit definition for SDMMC_IDMACTRL register ****************/
AnnaBridge 172:65be27845400 17888 #define SDMMC_IDMA_IDMAEN_Pos (0U)
AnnaBridge 172:65be27845400 17889 #define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17890 #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
AnnaBridge 172:65be27845400 17891 #define SDMMC_IDMA_IDMABMODE_Pos (1U)
AnnaBridge 172:65be27845400 17892 #define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17893 #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
AnnaBridge 172:65be27845400 17894 #define SDMMC_IDMA_IDMABACT_Pos (2U)
AnnaBridge 172:65be27845400 17895 #define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 17896 #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
AnnaBridge 172:65be27845400 17897
AnnaBridge 172:65be27845400 17898 /***************** Bit definition for SDMMC_IDMABSIZE register ***************/
AnnaBridge 172:65be27845400 17899 #define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
AnnaBridge 172:65be27845400 17900 #define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
AnnaBridge 172:65be27845400 17901 #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
AnnaBridge 172:65be27845400 17902
AnnaBridge 172:65be27845400 17903 /***************** Bit definition for SDMMC_IDMABASE0 register ***************/
AnnaBridge 172:65be27845400 17904 #define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
AnnaBridge 172:65be27845400 17905
AnnaBridge 172:65be27845400 17906 /***************** Bit definition for SDMMC_IDMABASE1 register ***************/
AnnaBridge 172:65be27845400 17907 #define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
AnnaBridge 172:65be27845400 17908
AnnaBridge 172:65be27845400 17909 /******************************************************************************/
AnnaBridge 172:65be27845400 17910 /* */
AnnaBridge 172:65be27845400 17911 /* Delay Block Interface (DLYB) */
AnnaBridge 172:65be27845400 17912 /* */
AnnaBridge 172:65be27845400 17913 /******************************************************************************/
AnnaBridge 172:65be27845400 17914 /******************* Bit definition for DLYB_CR register ********************/
AnnaBridge 172:65be27845400 17915 #define DLYB_CR_DEN_Pos (0U)
AnnaBridge 172:65be27845400 17916 #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17917 #define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
AnnaBridge 172:65be27845400 17918 #define DLYB_CR_SEN_Pos (1U)
AnnaBridge 172:65be27845400 17919 #define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17920 #define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
AnnaBridge 172:65be27845400 17921
AnnaBridge 172:65be27845400 17922
AnnaBridge 172:65be27845400 17923 /******************* Bit definition for DLYB_CFGR register ********************/
AnnaBridge 172:65be27845400 17924 #define DLYB_CFGR_SEL_Pos (0U)
AnnaBridge 172:65be27845400 17925 #define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 17926 #define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
AnnaBridge 172:65be27845400 17927 #define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17928 #define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 17929 #define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 17930 #define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 17931
AnnaBridge 172:65be27845400 17932 #define DLYB_CFGR_UNIT_Pos (8U)
AnnaBridge 172:65be27845400 17933 #define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
AnnaBridge 172:65be27845400 17934 #define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
AnnaBridge 172:65be27845400 17935 #define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17936 #define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17937 #define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17938 #define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17939 #define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17940 #define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17941 #define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17942
AnnaBridge 172:65be27845400 17943 #define DLYB_CFGR_LNG_Pos (16U)
AnnaBridge 172:65be27845400 17944 #define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 17945 #define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
AnnaBridge 172:65be27845400 17946 #define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17947 #define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 17948 #define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 17949 #define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 17950 #define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 17951 #define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 17952 #define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 17953 #define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 17954 #define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 17955 #define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 17956 #define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 17957 #define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 17958
AnnaBridge 172:65be27845400 17959 #define DLYB_CFGR_LNGF_Pos (31U)
AnnaBridge 172:65be27845400 17960 #define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 17961 #define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
AnnaBridge 172:65be27845400 17962
AnnaBridge 172:65be27845400 17963 /******************************************************************************/
AnnaBridge 172:65be27845400 17964 /* */
AnnaBridge 172:65be27845400 17965 /* Serial Peripheral Interface (SPI/I2S) */
AnnaBridge 172:65be27845400 17966 /* */
AnnaBridge 172:65be27845400 17967 /******************************************************************************/
AnnaBridge 172:65be27845400 17968 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 172:65be27845400 17969 #define SPI_CR1_SPE_Pos (0U)
AnnaBridge 172:65be27845400 17970 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 17971 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
AnnaBridge 172:65be27845400 17972 #define SPI_CR1_MASRX_Pos (8U)
AnnaBridge 172:65be27845400 17973 #define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 17974 #define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
AnnaBridge 172:65be27845400 17975 #define SPI_CR1_CSTART_Pos (9U)
AnnaBridge 172:65be27845400 17976 #define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 17977 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
AnnaBridge 172:65be27845400 17978 #define SPI_CR1_CSUSP_Pos (10U)
AnnaBridge 172:65be27845400 17979 #define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 17980 #define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
AnnaBridge 172:65be27845400 17981 #define SPI_CR1_HDDIR_Pos (11U)
AnnaBridge 172:65be27845400 17982 #define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 17983 #define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
AnnaBridge 172:65be27845400 17984 #define SPI_CR1_SSI_Pos (12U)
AnnaBridge 172:65be27845400 17985 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 17986 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
AnnaBridge 172:65be27845400 17987 #define SPI_CR1_CRC33_17_Pos (13U)
AnnaBridge 172:65be27845400 17988 #define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 17989 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
AnnaBridge 172:65be27845400 17990 #define SPI_CR1_RCRCINI_Pos (14U)
AnnaBridge 172:65be27845400 17991 #define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 17992 #define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
AnnaBridge 172:65be27845400 17993 #define SPI_CR1_TCRCINI_Pos (15U)
AnnaBridge 172:65be27845400 17994 #define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 17995 #define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
AnnaBridge 172:65be27845400 17996 #define SPI_CR1_IOLOCK_Pos (16U)
AnnaBridge 172:65be27845400 17997 #define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 17998 #define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
AnnaBridge 172:65be27845400 17999
AnnaBridge 172:65be27845400 18000 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 172:65be27845400 18001 #define SPI_CR2_TSER_Pos (16U)
AnnaBridge 172:65be27845400 18002 #define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 18003 #define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
AnnaBridge 172:65be27845400 18004 #define SPI_CR2_TSIZE_Pos (0U)
AnnaBridge 172:65be27845400 18005 #define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 18006 #define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
AnnaBridge 172:65be27845400 18007
AnnaBridge 172:65be27845400 18008 /******************* Bit definition for SPI_CFG1 register ********************/
AnnaBridge 172:65be27845400 18009 #define SPI_CFG1_DSIZE_Pos (0U)
AnnaBridge 172:65be27845400 18010 #define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 18011 #define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
AnnaBridge 172:65be27845400 18012 #define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18013 #define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18014 #define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18015 #define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18016 #define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18017
AnnaBridge 172:65be27845400 18018 #define SPI_CFG1_FTHLV_Pos (5U)
AnnaBridge 172:65be27845400 18019 #define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
AnnaBridge 172:65be27845400 18020 #define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
AnnaBridge 172:65be27845400 18021 #define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18022 #define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18023 #define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18024 #define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18025
AnnaBridge 172:65be27845400 18026 #define SPI_CFG1_UDRCFG_Pos (9U)
AnnaBridge 172:65be27845400 18027 #define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
AnnaBridge 172:65be27845400 18028 #define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
AnnaBridge 172:65be27845400 18029 #define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18030 #define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18031
AnnaBridge 172:65be27845400 18032
AnnaBridge 172:65be27845400 18033 #define SPI_CFG1_UDRDET_Pos (11U)
AnnaBridge 172:65be27845400 18034 #define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 18035 #define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
AnnaBridge 172:65be27845400 18036 #define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 18037 #define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 18038
AnnaBridge 172:65be27845400 18039 #define SPI_CFG1_RXDMAEN_Pos (14U)
AnnaBridge 172:65be27845400 18040 #define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 18041 #define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
AnnaBridge 172:65be27845400 18042 #define SPI_CFG1_TXDMAEN_Pos (15U)
AnnaBridge 172:65be27845400 18043 #define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 18044 #define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
AnnaBridge 172:65be27845400 18045
AnnaBridge 172:65be27845400 18046 #define SPI_CFG1_CRCSIZE_Pos (16U)
AnnaBridge 172:65be27845400 18047 #define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 18048 #define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
AnnaBridge 172:65be27845400 18049 #define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 18050 #define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 18051 #define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 18052 #define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 18053 #define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 18054
AnnaBridge 172:65be27845400 18055 #define SPI_CFG1_CRCEN_Pos (22U)
AnnaBridge 172:65be27845400 18056 #define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 18057 #define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
AnnaBridge 172:65be27845400 18058
AnnaBridge 172:65be27845400 18059 #define SPI_CFG1_MBR_Pos (28U)
AnnaBridge 172:65be27845400 18060 #define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
AnnaBridge 172:65be27845400 18061 #define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
AnnaBridge 172:65be27845400 18062 #define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 18063 #define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 18064 #define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 18065
AnnaBridge 172:65be27845400 18066 /******************* Bit definition for SPI_CFG2 register ********************/
AnnaBridge 172:65be27845400 18067 #define SPI_CFG2_MSSI_Pos (0U)
AnnaBridge 172:65be27845400 18068 #define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18069 #define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
AnnaBridge 172:65be27845400 18070 #define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18071 #define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18072 #define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18073 #define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18074
AnnaBridge 172:65be27845400 18075 #define SPI_CFG2_MIDI_Pos (4U)
AnnaBridge 172:65be27845400 18076 #define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 18077 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
AnnaBridge 172:65be27845400 18078 #define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18079 #define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18080 #define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18081 #define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18082
AnnaBridge 172:65be27845400 18083 #define SPI_CFG2_IOSWP_Pos (15U)
AnnaBridge 172:65be27845400 18084 #define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 18085 #define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
AnnaBridge 172:65be27845400 18086
AnnaBridge 172:65be27845400 18087 #define SPI_CFG2_COMM_Pos (17U)
AnnaBridge 172:65be27845400 18088 #define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 18089 #define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
AnnaBridge 172:65be27845400 18090 #define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 18091 #define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 18092
AnnaBridge 172:65be27845400 18093 #define SPI_CFG2_SP_Pos (19U)
AnnaBridge 172:65be27845400 18094 #define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
AnnaBridge 172:65be27845400 18095 #define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
AnnaBridge 172:65be27845400 18096 #define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 18097 #define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 18098 #define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 18099
AnnaBridge 172:65be27845400 18100 #define SPI_CFG2_MASTER_Pos (22U)
AnnaBridge 172:65be27845400 18101 #define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 18102 #define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
AnnaBridge 172:65be27845400 18103 #define SPI_CFG2_LSBFRST_Pos (23U)
AnnaBridge 172:65be27845400 18104 #define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 18105 #define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
AnnaBridge 172:65be27845400 18106 #define SPI_CFG2_CPHA_Pos (24U)
AnnaBridge 172:65be27845400 18107 #define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 18108 #define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 172:65be27845400 18109 #define SPI_CFG2_CPOL_Pos (25U)
AnnaBridge 172:65be27845400 18110 #define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 18111 #define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 172:65be27845400 18112 #define SPI_CFG2_SSM_Pos (26U)
AnnaBridge 172:65be27845400 18113 #define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 18114 #define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
AnnaBridge 172:65be27845400 18115
AnnaBridge 172:65be27845400 18116 #define SPI_CFG2_SSIOP_Pos (28U)
AnnaBridge 172:65be27845400 18117 #define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 18118 #define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
AnnaBridge 172:65be27845400 18119 #define SPI_CFG2_SSOE_Pos (29U)
AnnaBridge 172:65be27845400 18120 #define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 18121 #define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
AnnaBridge 172:65be27845400 18122 #define SPI_CFG2_SSOM_Pos (30U)
AnnaBridge 172:65be27845400 18123 #define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 18124 #define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
AnnaBridge 172:65be27845400 18125
AnnaBridge 172:65be27845400 18126 #define SPI_CFG2_AFCNTR_Pos (31U)
AnnaBridge 172:65be27845400 18127 #define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 18128 #define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
AnnaBridge 172:65be27845400 18129
AnnaBridge 172:65be27845400 18130 /******************* Bit definition for SPI_IER register ********************/
AnnaBridge 172:65be27845400 18131 #define SPI_IER_RXPIE_Pos (0U)
AnnaBridge 172:65be27845400 18132 #define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18133 #define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
AnnaBridge 172:65be27845400 18134 #define SPI_IER_TXPIE_Pos (1U)
AnnaBridge 172:65be27845400 18135 #define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18136 #define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
AnnaBridge 172:65be27845400 18137 #define SPI_IER_DXPIE_Pos (2U)
AnnaBridge 172:65be27845400 18138 #define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18139 #define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
AnnaBridge 172:65be27845400 18140 #define SPI_IER_EOTIE_Pos (3U)
AnnaBridge 172:65be27845400 18141 #define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18142 #define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
AnnaBridge 172:65be27845400 18143 #define SPI_IER_TXTFIE_Pos (4U)
AnnaBridge 172:65be27845400 18144 #define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18145 #define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
AnnaBridge 172:65be27845400 18146 #define SPI_IER_UDRIE_Pos (5U)
AnnaBridge 172:65be27845400 18147 #define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18148 #define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
AnnaBridge 172:65be27845400 18149 #define SPI_IER_OVRIE_Pos (6U)
AnnaBridge 172:65be27845400 18150 #define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18151 #define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
AnnaBridge 172:65be27845400 18152 #define SPI_IER_CRCEIE_Pos (7U)
AnnaBridge 172:65be27845400 18153 #define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18154 #define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
AnnaBridge 172:65be27845400 18155 #define SPI_IER_TIFREIE_Pos (8U)
AnnaBridge 172:65be27845400 18156 #define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18157 #define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
AnnaBridge 172:65be27845400 18158 #define SPI_IER_MODFIE_Pos (9U)
AnnaBridge 172:65be27845400 18159 #define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18160 #define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
AnnaBridge 172:65be27845400 18161 #define SPI_IER_TSERFIE_Pos (10U)
AnnaBridge 172:65be27845400 18162 #define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18163 #define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
AnnaBridge 172:65be27845400 18164
AnnaBridge 172:65be27845400 18165 /******************* Bit definition for SPI_SR register ********************/
AnnaBridge 172:65be27845400 18166 #define SPI_SR_RXP_Pos (0U)
AnnaBridge 172:65be27845400 18167 #define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18168 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
AnnaBridge 172:65be27845400 18169 #define SPI_SR_TXP_Pos (1U)
AnnaBridge 172:65be27845400 18170 #define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18171 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
AnnaBridge 172:65be27845400 18172 #define SPI_SR_DXP_Pos (2U)
AnnaBridge 172:65be27845400 18173 #define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18174 #define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
AnnaBridge 172:65be27845400 18175 #define SPI_SR_EOT_Pos (3U)
AnnaBridge 172:65be27845400 18176 #define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18177 #define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
AnnaBridge 172:65be27845400 18178 #define SPI_SR_TXTF_Pos (4U)
AnnaBridge 172:65be27845400 18179 #define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18180 #define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
AnnaBridge 172:65be27845400 18181 #define SPI_SR_UDR_Pos (5U)
AnnaBridge 172:65be27845400 18182 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18183 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
AnnaBridge 172:65be27845400 18184 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 172:65be27845400 18185 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18186 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
AnnaBridge 172:65be27845400 18187 #define SPI_SR_CRCE_Pos (7U)
AnnaBridge 172:65be27845400 18188 #define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18189 #define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
AnnaBridge 172:65be27845400 18190 #define SPI_SR_TIFRE_Pos (8U)
AnnaBridge 172:65be27845400 18191 #define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18192 #define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
AnnaBridge 172:65be27845400 18193 #define SPI_SR_MODF_Pos (9U)
AnnaBridge 172:65be27845400 18194 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18195 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
AnnaBridge 172:65be27845400 18196 #define SPI_SR_TSERF_Pos (10U)
AnnaBridge 172:65be27845400 18197 #define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18198 #define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
AnnaBridge 172:65be27845400 18199 #define SPI_SR_SUSP_Pos (11U)
AnnaBridge 172:65be27845400 18200 #define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 18201 #define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
AnnaBridge 172:65be27845400 18202 #define SPI_SR_TXC_Pos (12U)
AnnaBridge 172:65be27845400 18203 #define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 18204 #define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
AnnaBridge 172:65be27845400 18205 #define SPI_SR_RXPLVL_Pos (13U)
AnnaBridge 172:65be27845400 18206 #define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 18207 #define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
AnnaBridge 172:65be27845400 18208 #define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 18209 #define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 18210 #define SPI_SR_RXWNE_Pos (15U)
AnnaBridge 172:65be27845400 18211 #define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 18212 #define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
AnnaBridge 172:65be27845400 18213 #define SPI_SR_CTSIZE_Pos (16U)
AnnaBridge 172:65be27845400 18214 #define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 18215 #define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
AnnaBridge 172:65be27845400 18216
AnnaBridge 172:65be27845400 18217 /******************* Bit definition for SPI_IFCR register ********************/
AnnaBridge 172:65be27845400 18218 #define SPI_IFCR_EOTC_Pos (3U)
AnnaBridge 172:65be27845400 18219 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18220 #define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
AnnaBridge 172:65be27845400 18221 #define SPI_IFCR_TXTFC_Pos (4U)
AnnaBridge 172:65be27845400 18222 #define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18223 #define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
AnnaBridge 172:65be27845400 18224 #define SPI_IFCR_UDRC_Pos (5U)
AnnaBridge 172:65be27845400 18225 #define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18226 #define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
AnnaBridge 172:65be27845400 18227 #define SPI_IFCR_OVRC_Pos (6U)
AnnaBridge 172:65be27845400 18228 #define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18229 #define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
AnnaBridge 172:65be27845400 18230 #define SPI_IFCR_CRCEC_Pos (7U)
AnnaBridge 172:65be27845400 18231 #define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18232 #define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
AnnaBridge 172:65be27845400 18233 #define SPI_IFCR_TIFREC_Pos (8U)
AnnaBridge 172:65be27845400 18234 #define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18235 #define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
AnnaBridge 172:65be27845400 18236 #define SPI_IFCR_MODFC_Pos (9U)
AnnaBridge 172:65be27845400 18237 #define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18238 #define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
AnnaBridge 172:65be27845400 18239 #define SPI_IFCR_TSERFC_Pos (10U)
AnnaBridge 172:65be27845400 18240 #define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18241 #define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
AnnaBridge 172:65be27845400 18242 #define SPI_IFCR_SUSPC_Pos (11U)
AnnaBridge 172:65be27845400 18243 #define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 18244 #define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
AnnaBridge 172:65be27845400 18245
AnnaBridge 172:65be27845400 18246 /******************* Bit definition for SPI_TXDR register ********************/
AnnaBridge 172:65be27845400 18247 #define SPI_TXDR_TXDR_Pos (0U)
AnnaBridge 172:65be27845400 18248 #define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18249 #define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
AnnaBridge 172:65be27845400 18250
AnnaBridge 172:65be27845400 18251 /******************* Bit definition for SPI_RXDR register ********************/
AnnaBridge 172:65be27845400 18252 #define SPI_RXDR_RXDR_Pos (0U)
AnnaBridge 172:65be27845400 18253 #define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18254 #define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
AnnaBridge 172:65be27845400 18255
AnnaBridge 172:65be27845400 18256 /******************* Bit definition for SPI_CRCPOLY register ********************/
AnnaBridge 172:65be27845400 18257 #define SPI_CRCPOLY_CRCPOLY_Pos (0U)
AnnaBridge 172:65be27845400 18258 #define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18259 #define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
AnnaBridge 172:65be27845400 18260
AnnaBridge 172:65be27845400 18261 /******************* Bit definition for SPI_TXCRC register ********************/
AnnaBridge 172:65be27845400 18262 #define SPI_TXCRC_TXCRC_Pos (0U)
AnnaBridge 172:65be27845400 18263 #define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18264 #define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
AnnaBridge 172:65be27845400 18265
AnnaBridge 172:65be27845400 18266 /******************* Bit definition for SPI_RXCRC register ********************/
AnnaBridge 172:65be27845400 18267 #define SPI_TXCRC_RXCRC_Pos (0U)
AnnaBridge 172:65be27845400 18268 #define SPI_TXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18269 #define SPI_TXCRC_RXCRC SPI_TXCRC_RXCRC_Msk /* CRCRegister for receiver */
AnnaBridge 172:65be27845400 18270
AnnaBridge 172:65be27845400 18271 /******************* Bit definition for SPI_UDRDR register ********************/
AnnaBridge 172:65be27845400 18272 #define SPI_UDRDR_UDRDR_Pos (0U)
AnnaBridge 172:65be27845400 18273 #define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18274 #define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
AnnaBridge 172:65be27845400 18275
AnnaBridge 172:65be27845400 18276 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 172:65be27845400 18277 #define SPI_I2SCFGR_I2SMOD_Pos (0U)
AnnaBridge 172:65be27845400 18278 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18279 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 172:65be27845400 18280 #define SPI_I2SCFGR_I2SCFG_Pos (1U)
AnnaBridge 172:65be27845400 18281 #define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
AnnaBridge 172:65be27845400 18282 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
AnnaBridge 172:65be27845400 18283 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18284 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18285 #define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18286 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 172:65be27845400 18287 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 18288 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
AnnaBridge 172:65be27845400 18289 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18290 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18291 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 172:65be27845400 18292 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18293 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 172:65be27845400 18294 #define SPI_I2SCFGR_DATLEN_Pos (8U)
AnnaBridge 172:65be27845400 18295 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 18296 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
AnnaBridge 172:65be27845400 18297 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18298 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18299 #define SPI_I2SCFGR_CHLEN_Pos (10U)
AnnaBridge 172:65be27845400 18300 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18301 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 172:65be27845400 18302 #define SPI_I2SCFGR_CKPOL_Pos (11U)
AnnaBridge 172:65be27845400 18303 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 18304 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
AnnaBridge 172:65be27845400 18305 #define SPI_I2SCFGR_FIXCH_Pos (12U)
AnnaBridge 172:65be27845400 18306 #define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 18307 #define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
AnnaBridge 172:65be27845400 18308 #define SPI_I2SCFGR_WSINV_Pos (13U)
AnnaBridge 172:65be27845400 18309 #define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 18310 #define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
AnnaBridge 172:65be27845400 18311 #define SPI_I2SCFGR_DATFMT_Pos (14U)
AnnaBridge 172:65be27845400 18312 #define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 18313 #define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
AnnaBridge 172:65be27845400 18314 #define SPI_I2SCFGR_I2SDIV_Pos (16U)
AnnaBridge 172:65be27845400 18315 #define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 18316 #define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 172:65be27845400 18317 #define SPI_I2SCFGR_ODD_Pos (24U)
AnnaBridge 172:65be27845400 18318 #define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 18319 #define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 172:65be27845400 18320 #define SPI_I2SCFGR_MCKOE_Pos (25U)
AnnaBridge 172:65be27845400 18321 #define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 18322 #define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 172:65be27845400 18323
AnnaBridge 172:65be27845400 18324
AnnaBridge 172:65be27845400 18325 /******************************************************************************/
AnnaBridge 172:65be27845400 18326 /* */
AnnaBridge 172:65be27845400 18327 /* QUADSPI */
AnnaBridge 172:65be27845400 18328 /* */
AnnaBridge 172:65be27845400 18329 /******************************************************************************/
AnnaBridge 172:65be27845400 18330 /***************** Bit definition for QUADSPI_CR register *******************/
AnnaBridge 172:65be27845400 18331 #define QUADSPI_CR_EN_Pos (0U)
AnnaBridge 172:65be27845400 18332 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18333 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
AnnaBridge 172:65be27845400 18334 #define QUADSPI_CR_ABORT_Pos (1U)
AnnaBridge 172:65be27845400 18335 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18336 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
AnnaBridge 172:65be27845400 18337 #define QUADSPI_CR_DMAEN_Pos (2U)
AnnaBridge 172:65be27845400 18338 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18339 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
AnnaBridge 172:65be27845400 18340 #define QUADSPI_CR_TCEN_Pos (3U)
AnnaBridge 172:65be27845400 18341 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18342 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
AnnaBridge 172:65be27845400 18343 #define QUADSPI_CR_SSHIFT_Pos (4U)
AnnaBridge 172:65be27845400 18344 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18345 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
AnnaBridge 172:65be27845400 18346 #define QUADSPI_CR_DFM_Pos (6U)
AnnaBridge 172:65be27845400 18347 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18348 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
AnnaBridge 172:65be27845400 18349 #define QUADSPI_CR_FSEL_Pos (7U)
AnnaBridge 172:65be27845400 18350 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18351 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
AnnaBridge 172:65be27845400 18352 #define QUADSPI_CR_FTHRES_Pos (8U)
AnnaBridge 172:65be27845400 18353 #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 18354 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
AnnaBridge 172:65be27845400 18355 #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18356 #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18357 #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18358 #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 18359 #define QUADSPI_CR_TEIE_Pos (16U)
AnnaBridge 172:65be27845400 18360 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 18361 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 172:65be27845400 18362 #define QUADSPI_CR_TCIE_Pos (17U)
AnnaBridge 172:65be27845400 18363 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 18364 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 172:65be27845400 18365 #define QUADSPI_CR_FTIE_Pos (18U)
AnnaBridge 172:65be27845400 18366 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 18367 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
AnnaBridge 172:65be27845400 18368 #define QUADSPI_CR_SMIE_Pos (19U)
AnnaBridge 172:65be27845400 18369 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 18370 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
AnnaBridge 172:65be27845400 18371 #define QUADSPI_CR_TOIE_Pos (20U)
AnnaBridge 172:65be27845400 18372 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 18373 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
AnnaBridge 172:65be27845400 18374 #define QUADSPI_CR_APMS_Pos (22U)
AnnaBridge 172:65be27845400 18375 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 18376 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
AnnaBridge 172:65be27845400 18377 #define QUADSPI_CR_PMM_Pos (23U)
AnnaBridge 172:65be27845400 18378 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 18379 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
AnnaBridge 172:65be27845400 18380 #define QUADSPI_CR_PRESCALER_Pos (24U)
AnnaBridge 172:65be27845400 18381 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 18382 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
AnnaBridge 172:65be27845400 18383 #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 18384 #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 18385 #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 18386 #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 18387 #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 18388 #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 18389 #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 18390 #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 18391
AnnaBridge 172:65be27845400 18392 /***************** Bit definition for QUADSPI_DCR register ******************/
AnnaBridge 172:65be27845400 18393 #define QUADSPI_DCR_CKMODE_Pos (0U)
AnnaBridge 172:65be27845400 18394 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18395 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
AnnaBridge 172:65be27845400 18396 #define QUADSPI_DCR_CSHT_Pos (8U)
AnnaBridge 172:65be27845400 18397 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
AnnaBridge 172:65be27845400 18398 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
AnnaBridge 172:65be27845400 18399 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18400 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18401 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18402 #define QUADSPI_DCR_FSIZE_Pos (16U)
AnnaBridge 172:65be27845400 18403 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 18404 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
AnnaBridge 172:65be27845400 18405 #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 18406 #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 18407 #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 18408 #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 18409 #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 18410
AnnaBridge 172:65be27845400 18411 /****************** Bit definition for QUADSPI_SR register *******************/
AnnaBridge 172:65be27845400 18412 #define QUADSPI_SR_TEF_Pos (0U)
AnnaBridge 172:65be27845400 18413 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18414 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
AnnaBridge 172:65be27845400 18415 #define QUADSPI_SR_TCF_Pos (1U)
AnnaBridge 172:65be27845400 18416 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18417 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
AnnaBridge 172:65be27845400 18418 #define QUADSPI_SR_FTF_Pos (2U)
AnnaBridge 172:65be27845400 18419 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18420 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 172:65be27845400 18421 #define QUADSPI_SR_SMF_Pos (3U)
AnnaBridge 172:65be27845400 18422 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18423 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
AnnaBridge 172:65be27845400 18424 #define QUADSPI_SR_TOF_Pos (4U)
AnnaBridge 172:65be27845400 18425 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18426 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
AnnaBridge 172:65be27845400 18427 #define QUADSPI_SR_BUSY_Pos (5U)
AnnaBridge 172:65be27845400 18428 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18429 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
AnnaBridge 172:65be27845400 18430 #define QUADSPI_SR_FLEVEL_Pos (8U)
AnnaBridge 172:65be27845400 18431 #define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 18432 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
AnnaBridge 172:65be27845400 18433 #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18434 #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18435 #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18436 #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 18437 #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 18438 #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 18439 #define QUADSPI_SR_FLEVEL_6 (0x30UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 18440
AnnaBridge 172:65be27845400 18441 /****************** Bit definition for QUADSPI_FCR register ******************/
AnnaBridge 172:65be27845400 18442 #define QUADSPI_FCR_CTEF_Pos (0U)
AnnaBridge 172:65be27845400 18443 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18444 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
AnnaBridge 172:65be27845400 18445 #define QUADSPI_FCR_CTCF_Pos (1U)
AnnaBridge 172:65be27845400 18446 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18447 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
AnnaBridge 172:65be27845400 18448 #define QUADSPI_FCR_CSMF_Pos (3U)
AnnaBridge 172:65be27845400 18449 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18450 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
AnnaBridge 172:65be27845400 18451 #define QUADSPI_FCR_CTOF_Pos (4U)
AnnaBridge 172:65be27845400 18452 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18453 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
AnnaBridge 172:65be27845400 18454
AnnaBridge 172:65be27845400 18455 /****************** Bit definition for QUADSPI_DLR register ******************/
AnnaBridge 172:65be27845400 18456 #define QUADSPI_DLR_DL_Pos (0U)
AnnaBridge 172:65be27845400 18457 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18458 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
AnnaBridge 172:65be27845400 18459
AnnaBridge 172:65be27845400 18460 /****************** Bit definition for QUADSPI_CCR register ******************/
AnnaBridge 172:65be27845400 18461 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
AnnaBridge 172:65be27845400 18462 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 18463 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
AnnaBridge 172:65be27845400 18464 #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18465 #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18466 #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18467 #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18468 #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18469 #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18470 #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18471 #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18472 #define QUADSPI_CCR_IMODE_Pos (8U)
AnnaBridge 172:65be27845400 18473 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 18474 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
AnnaBridge 172:65be27845400 18475 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18476 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18477 #define QUADSPI_CCR_ADMODE_Pos (10U)
AnnaBridge 172:65be27845400 18478 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 18479 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
AnnaBridge 172:65be27845400 18480 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 18481 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 18482 #define QUADSPI_CCR_ADSIZE_Pos (12U)
AnnaBridge 172:65be27845400 18483 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 18484 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
AnnaBridge 172:65be27845400 18485 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 18486 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 18487 #define QUADSPI_CCR_ABMODE_Pos (14U)
AnnaBridge 172:65be27845400 18488 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 18489 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
AnnaBridge 172:65be27845400 18490 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 18491 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 18492 #define QUADSPI_CCR_ABSIZE_Pos (16U)
AnnaBridge 172:65be27845400 18493 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
AnnaBridge 172:65be27845400 18494 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
AnnaBridge 172:65be27845400 18495 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 18496 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 18497 #define QUADSPI_CCR_DCYC_Pos (18U)
AnnaBridge 172:65be27845400 18498 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
AnnaBridge 172:65be27845400 18499 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
AnnaBridge 172:65be27845400 18500 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 18501 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 18502 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 18503 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 18504 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 18505 #define QUADSPI_CCR_DMODE_Pos (24U)
AnnaBridge 172:65be27845400 18506 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 18507 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
AnnaBridge 172:65be27845400 18508 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 18509 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 18510 #define QUADSPI_CCR_FMODE_Pos (26U)
AnnaBridge 172:65be27845400 18511 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
AnnaBridge 172:65be27845400 18512 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
AnnaBridge 172:65be27845400 18513 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 18514 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 18515 #define QUADSPI_CCR_SIOO_Pos (28U)
AnnaBridge 172:65be27845400 18516 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 18517 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
AnnaBridge 172:65be27845400 18518 #define QUADSPI_CCR_DHHC_Pos (30U)
AnnaBridge 172:65be27845400 18519 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 18520 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
AnnaBridge 172:65be27845400 18521 #define QUADSPI_CCR_DDRM_Pos (31U)
AnnaBridge 172:65be27845400 18522 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 18523 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
AnnaBridge 172:65be27845400 18524
AnnaBridge 172:65be27845400 18525 /****************** Bit definition for QUADSPI_AR register *******************/
AnnaBridge 172:65be27845400 18526 #define QUADSPI_AR_ADDRESS_Pos (0U)
AnnaBridge 172:65be27845400 18527 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18528 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
AnnaBridge 172:65be27845400 18529
AnnaBridge 172:65be27845400 18530 /****************** Bit definition for QUADSPI_ABR register ******************/
AnnaBridge 172:65be27845400 18531 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
AnnaBridge 172:65be27845400 18532 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18533 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
AnnaBridge 172:65be27845400 18534
AnnaBridge 172:65be27845400 18535 /****************** Bit definition for QUADSPI_DR register *******************/
AnnaBridge 172:65be27845400 18536 #define QUADSPI_DR_DATA_Pos (0U)
AnnaBridge 172:65be27845400 18537 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18538 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
AnnaBridge 172:65be27845400 18539
AnnaBridge 172:65be27845400 18540 /****************** Bit definition for QUADSPI_PSMKR register ****************/
AnnaBridge 172:65be27845400 18541 #define QUADSPI_PSMKR_MASK_Pos (0U)
AnnaBridge 172:65be27845400 18542 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18543 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
AnnaBridge 172:65be27845400 18544
AnnaBridge 172:65be27845400 18545 /****************** Bit definition for QUADSPI_PSMAR register ****************/
AnnaBridge 172:65be27845400 18546 #define QUADSPI_PSMAR_MATCH_Pos (0U)
AnnaBridge 172:65be27845400 18547 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 18548 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
AnnaBridge 172:65be27845400 18549
AnnaBridge 172:65be27845400 18550 /****************** Bit definition for QUADSPI_PIR register *****************/
AnnaBridge 172:65be27845400 18551 #define QUADSPI_PIR_INTERVAL_Pos (0U)
AnnaBridge 172:65be27845400 18552 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 18553 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
AnnaBridge 172:65be27845400 18554
AnnaBridge 172:65be27845400 18555 /****************** Bit definition for QUADSPI_LPTR register *****************/
AnnaBridge 172:65be27845400 18556 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
AnnaBridge 172:65be27845400 18557 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 18558 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
AnnaBridge 172:65be27845400 18559
AnnaBridge 172:65be27845400 18560 /******************************************************************************/
AnnaBridge 172:65be27845400 18561 /* */
AnnaBridge 172:65be27845400 18562 /* SYSCFG */
AnnaBridge 172:65be27845400 18563 /* */
AnnaBridge 172:65be27845400 18564 /******************************************************************************/
AnnaBridge 172:65be27845400 18565
AnnaBridge 172:65be27845400 18566 /****************** Bit definition for SYSCFG_PMCR register ******************/
AnnaBridge 172:65be27845400 18567 #define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
AnnaBridge 172:65be27845400 18568 #define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18569 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
AnnaBridge 172:65be27845400 18570 #define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
AnnaBridge 172:65be27845400 18571 #define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18572 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
AnnaBridge 172:65be27845400 18573 #define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
AnnaBridge 172:65be27845400 18574 #define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 18575 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
AnnaBridge 172:65be27845400 18576 #define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
AnnaBridge 172:65be27845400 18577 #define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 18578 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
AnnaBridge 172:65be27845400 18579 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
AnnaBridge 172:65be27845400 18580 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 18581 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
AnnaBridge 172:65be27845400 18582 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
AnnaBridge 172:65be27845400 18583 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 18584 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
AnnaBridge 172:65be27845400 18585 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
AnnaBridge 172:65be27845400 18586 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 18587 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
AnnaBridge 172:65be27845400 18588 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
AnnaBridge 172:65be27845400 18589 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 18590 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
AnnaBridge 172:65be27845400 18591 #define SYSCFG_PMCR_BOOSTEN_Pos (8U)
AnnaBridge 172:65be27845400 18592 #define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18593 #define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
AnnaBridge 172:65be27845400 18594 #define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
AnnaBridge 172:65be27845400 18595 #define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 18596 #define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk /*!< Analog switch supply source selection : VDD/VDDA */
AnnaBridge 172:65be27845400 18597
AnnaBridge 172:65be27845400 18598 #define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
AnnaBridge 172:65be27845400 18599 #define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00E00000 */
AnnaBridge 172:65be27845400 18600 #define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk /*!< Ethernet PHY Interface Selection */
AnnaBridge 172:65be27845400 18601 #define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 18602 #define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 18603 #define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 18604 #define SYSCFG_PMCR_PA0SO_Pos (24U)
AnnaBridge 172:65be27845400 18605 #define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 18606 #define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
AnnaBridge 172:65be27845400 18607 #define SYSCFG_PMCR_PA1SO_Pos (25U)
AnnaBridge 172:65be27845400 18608 #define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 18609 #define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
AnnaBridge 172:65be27845400 18610 #define SYSCFG_PMCR_PC2SO_Pos (26U)
AnnaBridge 172:65be27845400 18611 #define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 18612 #define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
AnnaBridge 172:65be27845400 18613 #define SYSCFG_PMCR_PC3SO_Pos (27U)
AnnaBridge 172:65be27845400 18614 #define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 18615 #define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
AnnaBridge 172:65be27845400 18616
AnnaBridge 172:65be27845400 18617 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 172:65be27845400 18618 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 172:65be27845400 18619 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18620 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 172:65be27845400 18621 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 172:65be27845400 18622 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 18623 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 172:65be27845400 18624 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 172:65be27845400 18625 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 18626 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 172:65be27845400 18627 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 172:65be27845400 18628 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 18629 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 172:65be27845400 18630 /**
AnnaBridge 172:65be27845400 18631 * @brief EXTI0 configuration
AnnaBridge 172:65be27845400 18632 */
AnnaBridge 172:65be27845400 18633 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
AnnaBridge 172:65be27845400 18634 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
AnnaBridge 172:65be27845400 18635 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
AnnaBridge 172:65be27845400 18636 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
AnnaBridge 172:65be27845400 18637 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
AnnaBridge 172:65be27845400 18638 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
AnnaBridge 172:65be27845400 18639 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
AnnaBridge 172:65be27845400 18640 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
AnnaBridge 172:65be27845400 18641 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
AnnaBridge 172:65be27845400 18642 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
AnnaBridge 172:65be27845400 18643 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
AnnaBridge 172:65be27845400 18644
AnnaBridge 172:65be27845400 18645 /**
AnnaBridge 172:65be27845400 18646 * @brief EXTI1 configuration
AnnaBridge 172:65be27845400 18647 */
AnnaBridge 172:65be27845400 18648 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
AnnaBridge 172:65be27845400 18649 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
AnnaBridge 172:65be27845400 18650 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
AnnaBridge 172:65be27845400 18651 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
AnnaBridge 172:65be27845400 18652 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
AnnaBridge 172:65be27845400 18653 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
AnnaBridge 172:65be27845400 18654 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
AnnaBridge 172:65be27845400 18655 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
AnnaBridge 172:65be27845400 18656 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
AnnaBridge 172:65be27845400 18657 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
AnnaBridge 172:65be27845400 18658 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
AnnaBridge 172:65be27845400 18659 /**
AnnaBridge 172:65be27845400 18660 * @brief EXTI2 configuration
AnnaBridge 172:65be27845400 18661 */
AnnaBridge 172:65be27845400 18662 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
AnnaBridge 172:65be27845400 18663 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
AnnaBridge 172:65be27845400 18664 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
AnnaBridge 172:65be27845400 18665 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
AnnaBridge 172:65be27845400 18666 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
AnnaBridge 172:65be27845400 18667 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
AnnaBridge 172:65be27845400 18668 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
AnnaBridge 172:65be27845400 18669 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
AnnaBridge 172:65be27845400 18670 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
AnnaBridge 172:65be27845400 18671 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
AnnaBridge 172:65be27845400 18672 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
AnnaBridge 172:65be27845400 18673
AnnaBridge 172:65be27845400 18674 /**
AnnaBridge 172:65be27845400 18675 * @brief EXTI3 configuration
AnnaBridge 172:65be27845400 18676 */
AnnaBridge 172:65be27845400 18677 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
AnnaBridge 172:65be27845400 18678 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
AnnaBridge 172:65be27845400 18679 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
AnnaBridge 172:65be27845400 18680 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
AnnaBridge 172:65be27845400 18681 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
AnnaBridge 172:65be27845400 18682 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
AnnaBridge 172:65be27845400 18683 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
AnnaBridge 172:65be27845400 18684 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
AnnaBridge 172:65be27845400 18685 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
AnnaBridge 172:65be27845400 18686 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
AnnaBridge 172:65be27845400 18687 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
AnnaBridge 172:65be27845400 18688
AnnaBridge 172:65be27845400 18689 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 172:65be27845400 18690 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 172:65be27845400 18691 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18692 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 172:65be27845400 18693 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 172:65be27845400 18694 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 18695 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 172:65be27845400 18696 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 172:65be27845400 18697 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 18698 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 172:65be27845400 18699 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 172:65be27845400 18700 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 18701 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 172:65be27845400 18702 /**
AnnaBridge 172:65be27845400 18703 * @brief EXTI4 configuration
AnnaBridge 172:65be27845400 18704 */
AnnaBridge 172:65be27845400 18705 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
AnnaBridge 172:65be27845400 18706 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
AnnaBridge 172:65be27845400 18707 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
AnnaBridge 172:65be27845400 18708 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
AnnaBridge 172:65be27845400 18709 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
AnnaBridge 172:65be27845400 18710 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
AnnaBridge 172:65be27845400 18711 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
AnnaBridge 172:65be27845400 18712 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
AnnaBridge 172:65be27845400 18713 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
AnnaBridge 172:65be27845400 18714 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
AnnaBridge 172:65be27845400 18715 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
AnnaBridge 172:65be27845400 18716 /**
AnnaBridge 172:65be27845400 18717 * @brief EXTI5 configuration
AnnaBridge 172:65be27845400 18718 */
AnnaBridge 172:65be27845400 18719 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
AnnaBridge 172:65be27845400 18720 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
AnnaBridge 172:65be27845400 18721 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
AnnaBridge 172:65be27845400 18722 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
AnnaBridge 172:65be27845400 18723 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
AnnaBridge 172:65be27845400 18724 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
AnnaBridge 172:65be27845400 18725 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
AnnaBridge 172:65be27845400 18726 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
AnnaBridge 172:65be27845400 18727 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
AnnaBridge 172:65be27845400 18728 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
AnnaBridge 172:65be27845400 18729 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
AnnaBridge 172:65be27845400 18730 /**
AnnaBridge 172:65be27845400 18731 * @brief EXTI6 configuration
AnnaBridge 172:65be27845400 18732 */
AnnaBridge 172:65be27845400 18733 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
AnnaBridge 172:65be27845400 18734 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
AnnaBridge 172:65be27845400 18735 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
AnnaBridge 172:65be27845400 18736 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
AnnaBridge 172:65be27845400 18737 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
AnnaBridge 172:65be27845400 18738 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
AnnaBridge 172:65be27845400 18739 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
AnnaBridge 172:65be27845400 18740 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
AnnaBridge 172:65be27845400 18741 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
AnnaBridge 172:65be27845400 18742 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
AnnaBridge 172:65be27845400 18743 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
AnnaBridge 172:65be27845400 18744
AnnaBridge 172:65be27845400 18745 /**
AnnaBridge 172:65be27845400 18746 * @brief EXTI7 configuration
AnnaBridge 172:65be27845400 18747 */
AnnaBridge 172:65be27845400 18748 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
AnnaBridge 172:65be27845400 18749 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
AnnaBridge 172:65be27845400 18750 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
AnnaBridge 172:65be27845400 18751 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
AnnaBridge 172:65be27845400 18752 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
AnnaBridge 172:65be27845400 18753 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
AnnaBridge 172:65be27845400 18754 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
AnnaBridge 172:65be27845400 18755 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
AnnaBridge 172:65be27845400 18756 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
AnnaBridge 172:65be27845400 18757 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
AnnaBridge 172:65be27845400 18758 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
AnnaBridge 172:65be27845400 18759
AnnaBridge 172:65be27845400 18760 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 172:65be27845400 18761 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 172:65be27845400 18762 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18763 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 172:65be27845400 18764 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 172:65be27845400 18765 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 18766 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 172:65be27845400 18767 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 172:65be27845400 18768 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 18769 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 172:65be27845400 18770 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 172:65be27845400 18771 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 18772 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 172:65be27845400 18773
AnnaBridge 172:65be27845400 18774 /**
AnnaBridge 172:65be27845400 18775 * @brief EXTI8 configuration
AnnaBridge 172:65be27845400 18776 */
AnnaBridge 172:65be27845400 18777 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
AnnaBridge 172:65be27845400 18778 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
AnnaBridge 172:65be27845400 18779 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
AnnaBridge 172:65be27845400 18780 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
AnnaBridge 172:65be27845400 18781 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
AnnaBridge 172:65be27845400 18782 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
AnnaBridge 172:65be27845400 18783 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
AnnaBridge 172:65be27845400 18784 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
AnnaBridge 172:65be27845400 18785 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
AnnaBridge 172:65be27845400 18786 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
AnnaBridge 172:65be27845400 18787
AnnaBridge 172:65be27845400 18788 /**
AnnaBridge 172:65be27845400 18789 * @brief EXTI9 configuration
AnnaBridge 172:65be27845400 18790 */
AnnaBridge 172:65be27845400 18791 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
AnnaBridge 172:65be27845400 18792 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
AnnaBridge 172:65be27845400 18793 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
AnnaBridge 172:65be27845400 18794 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
AnnaBridge 172:65be27845400 18795 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
AnnaBridge 172:65be27845400 18796 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
AnnaBridge 172:65be27845400 18797 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
AnnaBridge 172:65be27845400 18798 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
AnnaBridge 172:65be27845400 18799 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
AnnaBridge 172:65be27845400 18800 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
AnnaBridge 172:65be27845400 18801
AnnaBridge 172:65be27845400 18802 /**
AnnaBridge 172:65be27845400 18803 * @brief EXTI10 configuration
AnnaBridge 172:65be27845400 18804 */
AnnaBridge 172:65be27845400 18805 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
AnnaBridge 172:65be27845400 18806 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
AnnaBridge 172:65be27845400 18807 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
AnnaBridge 172:65be27845400 18808 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
AnnaBridge 172:65be27845400 18809 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
AnnaBridge 172:65be27845400 18810 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
AnnaBridge 172:65be27845400 18811 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
AnnaBridge 172:65be27845400 18812 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
AnnaBridge 172:65be27845400 18813 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
AnnaBridge 172:65be27845400 18814 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
AnnaBridge 172:65be27845400 18815
AnnaBridge 172:65be27845400 18816
AnnaBridge 172:65be27845400 18817 /**
AnnaBridge 172:65be27845400 18818 * @brief EXTI11 configuration
AnnaBridge 172:65be27845400 18819 */
AnnaBridge 172:65be27845400 18820 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
AnnaBridge 172:65be27845400 18821 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
AnnaBridge 172:65be27845400 18822 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
AnnaBridge 172:65be27845400 18823 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
AnnaBridge 172:65be27845400 18824 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
AnnaBridge 172:65be27845400 18825 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
AnnaBridge 172:65be27845400 18826 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
AnnaBridge 172:65be27845400 18827 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
AnnaBridge 172:65be27845400 18828 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
AnnaBridge 172:65be27845400 18829 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
AnnaBridge 172:65be27845400 18830
AnnaBridge 172:65be27845400 18831
AnnaBridge 172:65be27845400 18832 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 172:65be27845400 18833 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 172:65be27845400 18834 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18835 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 172:65be27845400 18836 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 172:65be27845400 18837 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 18838 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 172:65be27845400 18839 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 172:65be27845400 18840 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 18841 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 172:65be27845400 18842 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 172:65be27845400 18843 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 18844 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 172:65be27845400 18845 /**
AnnaBridge 172:65be27845400 18846 * @brief EXTI12 configuration
AnnaBridge 172:65be27845400 18847 */
AnnaBridge 172:65be27845400 18848 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
AnnaBridge 172:65be27845400 18849 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
AnnaBridge 172:65be27845400 18850 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
AnnaBridge 172:65be27845400 18851 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
AnnaBridge 172:65be27845400 18852 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
AnnaBridge 172:65be27845400 18853 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
AnnaBridge 172:65be27845400 18854 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
AnnaBridge 172:65be27845400 18855 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
AnnaBridge 172:65be27845400 18856 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
AnnaBridge 172:65be27845400 18857 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
AnnaBridge 172:65be27845400 18858 /**
AnnaBridge 172:65be27845400 18859 * @brief EXTI13 configuration
AnnaBridge 172:65be27845400 18860 */
AnnaBridge 172:65be27845400 18861 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
AnnaBridge 172:65be27845400 18862 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
AnnaBridge 172:65be27845400 18863 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
AnnaBridge 172:65be27845400 18864 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
AnnaBridge 172:65be27845400 18865 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
AnnaBridge 172:65be27845400 18866 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
AnnaBridge 172:65be27845400 18867 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
AnnaBridge 172:65be27845400 18868 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
AnnaBridge 172:65be27845400 18869 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
AnnaBridge 172:65be27845400 18870 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
AnnaBridge 172:65be27845400 18871 /**
AnnaBridge 172:65be27845400 18872 * @brief EXTI14 configuration
AnnaBridge 172:65be27845400 18873 */
AnnaBridge 172:65be27845400 18874 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
AnnaBridge 172:65be27845400 18875 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
AnnaBridge 172:65be27845400 18876 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
AnnaBridge 172:65be27845400 18877 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
AnnaBridge 172:65be27845400 18878 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
AnnaBridge 172:65be27845400 18879 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
AnnaBridge 172:65be27845400 18880 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
AnnaBridge 172:65be27845400 18881 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
AnnaBridge 172:65be27845400 18882 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
AnnaBridge 172:65be27845400 18883 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
AnnaBridge 172:65be27845400 18884 /**
AnnaBridge 172:65be27845400 18885 * @brief EXTI15 configuration
AnnaBridge 172:65be27845400 18886 */
AnnaBridge 172:65be27845400 18887 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
AnnaBridge 172:65be27845400 18888 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
AnnaBridge 172:65be27845400 18889 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
AnnaBridge 172:65be27845400 18890 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
AnnaBridge 172:65be27845400 18891 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
AnnaBridge 172:65be27845400 18892 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
AnnaBridge 172:65be27845400 18893 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
AnnaBridge 172:65be27845400 18894 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
AnnaBridge 172:65be27845400 18895 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
AnnaBridge 172:65be27845400 18896 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
AnnaBridge 172:65be27845400 18897
AnnaBridge 172:65be27845400 18898 /****************** Bit definition for SYSCFG_CCCSR register ******************/
AnnaBridge 172:65be27845400 18899 #define SYSCFG_CCCSR_EN_Pos (0U)
AnnaBridge 172:65be27845400 18900 #define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18901 #define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
AnnaBridge 172:65be27845400 18902 #define SYSCFG_CCCSR_CS_Pos (1U)
AnnaBridge 172:65be27845400 18903 #define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18904 #define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
AnnaBridge 172:65be27845400 18905 #define SYSCFG_CCCSR_READY_Pos (8U)
AnnaBridge 172:65be27845400 18906 #define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 18907 #define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
AnnaBridge 172:65be27845400 18908 #define SYSCFG_CCCSR_HSLV_Pos (16U)
AnnaBridge 172:65be27845400 18909 #define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 18910 #define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
AnnaBridge 172:65be27845400 18911
AnnaBridge 172:65be27845400 18912 /****************** Bit definition for SYSCFG_CCVR register *******************/
AnnaBridge 172:65be27845400 18913 #define SYSCFG_CCVR_NCV_Pos (0U)
AnnaBridge 172:65be27845400 18914 #define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18915 #define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
AnnaBridge 172:65be27845400 18916 #define SYSCFG_CCVR_PCV_Pos (4U)
AnnaBridge 172:65be27845400 18917 #define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 18918 #define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
AnnaBridge 172:65be27845400 18919
AnnaBridge 172:65be27845400 18920 /****************** Bit definition for SYSCFG_CCCR register *******************/
AnnaBridge 172:65be27845400 18921 #define SYSCFG_CCCR_NCC_Pos (0U)
AnnaBridge 172:65be27845400 18922 #define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18923 #define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
AnnaBridge 172:65be27845400 18924 #define SYSCFG_CCCR_PCC_Pos (4U)
AnnaBridge 172:65be27845400 18925 #define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 18926 #define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
AnnaBridge 172:65be27845400 18927
AnnaBridge 172:65be27845400 18928 /****************** Bit definition for SYSCFG_PKGR register *******************/
AnnaBridge 172:65be27845400 18929 #define SYSCFG_PKGR_PKG_Pos (0U)
AnnaBridge 172:65be27845400 18930 #define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 18931 #define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk /*!< Package type */
AnnaBridge 172:65be27845400 18932
AnnaBridge 172:65be27845400 18933 /****************** Bit definition for SYSCFG_UR0 register *******************/
AnnaBridge 172:65be27845400 18934 #define SYSCFG_UR0_BKS_Pos (0U)
AnnaBridge 172:65be27845400 18935 #define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18936 #define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk /*!< Bank Swap */
AnnaBridge 172:65be27845400 18937 #define SYSCFG_UR0_RDP_Pos (16U)
AnnaBridge 172:65be27845400 18938 #define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 18939 #define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk /*!< Readout protection */
AnnaBridge 172:65be27845400 18940
AnnaBridge 172:65be27845400 18941 /****************** Bit definition for SYSCFG_UR2 register *******************/
AnnaBridge 172:65be27845400 18942 #define SYSCFG_UR2_BORH_Pos (0U)
AnnaBridge 172:65be27845400 18943 #define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 18944 #define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk /*!< Brown Out Reset High level */
AnnaBridge 172:65be27845400 18945 #define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18946 #define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 18947 #define SYSCFG_UR2_BOOT_ADD0_Pos (16U)
AnnaBridge 172:65be27845400 18948 #define SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 18949 #define SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk /*!< Core Boot Address 0 */
AnnaBridge 172:65be27845400 18950 /****************** Bit definition for SYSCFG_UR3 register *******************/
AnnaBridge 172:65be27845400 18951 #define SYSCFG_UR3_BOOT_ADD1_Pos (0U)
AnnaBridge 172:65be27845400 18952 #define SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 18953 #define SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk /*!< Core Boot Address 1 */
AnnaBridge 172:65be27845400 18954
AnnaBridge 172:65be27845400 18955 /****************** Bit definition for SYSCFG_UR4 register *******************/
AnnaBridge 172:65be27845400 18956
AnnaBridge 172:65be27845400 18957 #define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
AnnaBridge 172:65be27845400 18958 #define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 18959 #define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk /*!< Mass Erase Protected Area Disabled for bank 1 */
AnnaBridge 172:65be27845400 18960
AnnaBridge 172:65be27845400 18961 /****************** Bit definition for SYSCFG_UR5 register *******************/
AnnaBridge 172:65be27845400 18962 #define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
AnnaBridge 172:65be27845400 18963 #define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18964 #define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk /*!< Mass erase secured area disabled for bank 1 */
AnnaBridge 172:65be27845400 18965 #define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
AnnaBridge 172:65be27845400 18966 #define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 18967 #define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk /*!< Write protection for flash bank 1 */
AnnaBridge 172:65be27845400 18968
AnnaBridge 172:65be27845400 18969 /****************** Bit definition for SYSCFG_UR6 register *******************/
AnnaBridge 172:65be27845400 18970 #define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
AnnaBridge 172:65be27845400 18971 #define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 18972 #define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk /*!< Protected area start address for bank 1 */
AnnaBridge 172:65be27845400 18973 #define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
AnnaBridge 172:65be27845400 18974 #define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 18975 #define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk /*!< Protected area end address for bank 1 */
AnnaBridge 172:65be27845400 18976
AnnaBridge 172:65be27845400 18977 /****************** Bit definition for SYSCFG_UR7 register *******************/
AnnaBridge 172:65be27845400 18978 #define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
AnnaBridge 172:65be27845400 18979 #define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 18980 #define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk /*!< Secured area start address for bank 1 */
AnnaBridge 172:65be27845400 18981 #define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
AnnaBridge 172:65be27845400 18982 #define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 18983 #define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk /*!< Secured area end address for bank 1 */
AnnaBridge 172:65be27845400 18984
AnnaBridge 172:65be27845400 18985 /****************** Bit definition for SYSCFG_UR8 register *******************/
AnnaBridge 172:65be27845400 18986 #define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
AnnaBridge 172:65be27845400 18987 #define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 18988 #define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk /*!< Mass erase Protected area disabled for bank 2 */
AnnaBridge 172:65be27845400 18989 #define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
AnnaBridge 172:65be27845400 18990 #define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 18991 #define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk /*!< Mass Erase Secured Area Disabled for bank 2 */
AnnaBridge 172:65be27845400 18992
AnnaBridge 172:65be27845400 18993 /****************** Bit definition for SYSCFG_UR9 register *******************/
AnnaBridge 172:65be27845400 18994 #define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
AnnaBridge 172:65be27845400 18995 #define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 18996 #define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk /*!< Write protection for flash bank 2 */
AnnaBridge 172:65be27845400 18997 #define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
AnnaBridge 172:65be27845400 18998 #define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 18999 #define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk /*!< Protected area start address for bank 2 */
AnnaBridge 172:65be27845400 19000
AnnaBridge 172:65be27845400 19001 /****************** Bit definition for SYSCFG_UR10 register *******************/
AnnaBridge 172:65be27845400 19002 #define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
AnnaBridge 172:65be27845400 19003 #define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 19004 #define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk /*!< Protected area end address for bank 2 */
AnnaBridge 172:65be27845400 19005 #define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
AnnaBridge 172:65be27845400 19006 #define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
AnnaBridge 172:65be27845400 19007 #define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk /*!< Secured area start address for bank 2 */
AnnaBridge 172:65be27845400 19008
AnnaBridge 172:65be27845400 19009 /****************** Bit definition for SYSCFG_UR11 register *******************/
AnnaBridge 172:65be27845400 19010 #define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
AnnaBridge 172:65be27845400 19011 #define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 19012 #define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk /*!< Secured area end address for bank 2 */
AnnaBridge 172:65be27845400 19013 #define SYSCFG_UR11_IWDG1M_Pos (16U)
AnnaBridge 172:65be27845400 19014 #define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19015 #define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk /*!< Independent Watchdog 1 mode (SW or HW) */
AnnaBridge 172:65be27845400 19016
AnnaBridge 172:65be27845400 19017 /****************** Bit definition for SYSCFG_UR12 register *******************/
AnnaBridge 172:65be27845400 19018
AnnaBridge 172:65be27845400 19019 #define SYSCFG_UR12_SECURE_Pos (16U)
AnnaBridge 172:65be27845400 19020 #define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19021 #define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk /*!< Secure mode status */
AnnaBridge 172:65be27845400 19022
AnnaBridge 172:65be27845400 19023 /****************** Bit definition for SYSCFG_UR13 register *******************/
AnnaBridge 172:65be27845400 19024 #define SYSCFG_UR13_SDRS_Pos (0U)
AnnaBridge 172:65be27845400 19025 #define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 19026 #define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk /*!< Secured DTCM RAM Size */
AnnaBridge 172:65be27845400 19027 #define SYSCFG_UR13_D1SBRST_Pos (16U)
AnnaBridge 172:65be27845400 19028 #define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19029 #define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk /*!< D1 Standby reset */
AnnaBridge 172:65be27845400 19030
AnnaBridge 172:65be27845400 19031 /****************** Bit definition for SYSCFG_UR14 register *******************/
AnnaBridge 172:65be27845400 19032 #define SYSCFG_UR14_D1STPRST_Pos (0U)
AnnaBridge 172:65be27845400 19033 #define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19034 #define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk /*!< D1 Stop Reset */
AnnaBridge 172:65be27845400 19035
AnnaBridge 172:65be27845400 19036 /****************** Bit definition for SYSCFG_UR15 register *******************/
AnnaBridge 172:65be27845400 19037 #define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
AnnaBridge 172:65be27845400 19038 #define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19039 #define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk /*!< Freeze independent watchdogs in Standby mode */
AnnaBridge 172:65be27845400 19040
AnnaBridge 172:65be27845400 19041 /****************** Bit definition for SYSCFG_UR16 register *******************/
AnnaBridge 172:65be27845400 19042 #define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
AnnaBridge 172:65be27845400 19043 #define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19044 #define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk /*!< Freeze independent watchdogs in Stop mode */
AnnaBridge 172:65be27845400 19045 #define SYSCFG_UR16_PKP_Pos (16U)
AnnaBridge 172:65be27845400 19046 #define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19047 #define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk /*!< Private key programmed */
AnnaBridge 172:65be27845400 19048
AnnaBridge 172:65be27845400 19049 /****************** Bit definition for SYSCFG_UR17 register *******************/
AnnaBridge 172:65be27845400 19050 #define SYSCFG_UR17_IOHSLV_Pos (0U)
AnnaBridge 172:65be27845400 19051 #define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19052 #define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk /*!< I/O high speed / low voltage */
AnnaBridge 172:65be27845400 19053
AnnaBridge 172:65be27845400 19054
AnnaBridge 172:65be27845400 19055 /******************************************************************************/
AnnaBridge 172:65be27845400 19056 /* */
AnnaBridge 172:65be27845400 19057 /* TIM */
AnnaBridge 172:65be27845400 19058 /* */
AnnaBridge 172:65be27845400 19059 /******************************************************************************/
AnnaBridge 172:65be27845400 19060 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
AnnaBridge 172:65be27845400 19061 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 172:65be27845400 19062 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 172:65be27845400 19063 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19064 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 172:65be27845400 19065 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 172:65be27845400 19066 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19067 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 172:65be27845400 19068 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 172:65be27845400 19069 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19070 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 172:65be27845400 19071 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 172:65be27845400 19072 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19073 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 172:65be27845400 19074 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 172:65be27845400 19075 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19076 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 172:65be27845400 19077
AnnaBridge 172:65be27845400 19078 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 172:65be27845400 19079 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 172:65be27845400 19080 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 172:65be27845400 19081 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19082 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19083
AnnaBridge 172:65be27845400 19084 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 172:65be27845400 19085 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19086 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 172:65be27845400 19087
AnnaBridge 172:65be27845400 19088 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 172:65be27845400 19089 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 19090 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 172:65be27845400 19091 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19092 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19093
AnnaBridge 172:65be27845400 19094 #define TIM_CR1_UIFREMAP_Pos (11U)
AnnaBridge 172:65be27845400 19095 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19096 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
AnnaBridge 172:65be27845400 19097
AnnaBridge 172:65be27845400 19098 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 172:65be27845400 19099 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 172:65be27845400 19100 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19101 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 172:65be27845400 19102 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 172:65be27845400 19103 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19104 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 172:65be27845400 19105 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 172:65be27845400 19106 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19107 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 172:65be27845400 19108
AnnaBridge 172:65be27845400 19109 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 172:65be27845400 19110 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 19111 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 172:65be27845400 19112 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19113 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19114 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19115
AnnaBridge 172:65be27845400 19116 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 172:65be27845400 19117 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19118 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 172:65be27845400 19119 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 172:65be27845400 19120 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19121 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 172:65be27845400 19122 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 172:65be27845400 19123 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19124 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 172:65be27845400 19125 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 172:65be27845400 19126 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19127 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 172:65be27845400 19128 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 172:65be27845400 19129 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19130 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 172:65be27845400 19131 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 172:65be27845400 19132 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19133 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 172:65be27845400 19134 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 172:65be27845400 19135 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19136 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 172:65be27845400 19137 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 172:65be27845400 19138 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19139 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 172:65be27845400 19140 #define TIM_CR2_OIS5_Pos (16U)
AnnaBridge 172:65be27845400 19141 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19142 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 172:65be27845400 19143 #define TIM_CR2_OIS6_Pos (17U)
AnnaBridge 172:65be27845400 19144 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19145 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 172:65be27845400 19146
AnnaBridge 172:65be27845400 19147 #define TIM_CR2_MMS2_Pos (20U)
AnnaBridge 172:65be27845400 19148 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 19149 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 172:65be27845400 19150 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 19151 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 19152 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 19153 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 19154
AnnaBridge 172:65be27845400 19155 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 172:65be27845400 19156 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 172:65be27845400 19157 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
AnnaBridge 172:65be27845400 19158 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 172:65be27845400 19159 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19160 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19161 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19162 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19163
AnnaBridge 172:65be27845400 19164 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 172:65be27845400 19165 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
AnnaBridge 172:65be27845400 19166 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
AnnaBridge 172:65be27845400 19167 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19168 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19169 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19170 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 19171 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 19172
AnnaBridge 172:65be27845400 19173 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 172:65be27845400 19174 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19175 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 172:65be27845400 19176
AnnaBridge 172:65be27845400 19177 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 172:65be27845400 19178 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 19179 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 172:65be27845400 19180 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19181 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19182 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19183 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19184
AnnaBridge 172:65be27845400 19185 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 172:65be27845400 19186 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 19187 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 172:65be27845400 19188 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19189 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19190
AnnaBridge 172:65be27845400 19191 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 172:65be27845400 19192 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19193 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 172:65be27845400 19194 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 172:65be27845400 19195 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19196 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 172:65be27845400 19197
AnnaBridge 172:65be27845400 19198 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 172:65be27845400 19199 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 172:65be27845400 19200 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19201 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 172:65be27845400 19202 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 172:65be27845400 19203 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19204 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 172:65be27845400 19205 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 172:65be27845400 19206 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19207 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 172:65be27845400 19208 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 172:65be27845400 19209 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19210 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 172:65be27845400 19211 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 172:65be27845400 19212 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19213 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 172:65be27845400 19214 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 172:65be27845400 19215 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19216 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 172:65be27845400 19217 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 172:65be27845400 19218 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19219 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 172:65be27845400 19220 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 172:65be27845400 19221 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19222 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 172:65be27845400 19223 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 172:65be27845400 19224 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19225 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 172:65be27845400 19226 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 172:65be27845400 19227 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19228 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 172:65be27845400 19229 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 172:65be27845400 19230 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19231 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 172:65be27845400 19232 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 172:65be27845400 19233 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19234 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 172:65be27845400 19235 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 172:65be27845400 19236 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19237 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 172:65be27845400 19238 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 172:65be27845400 19239 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19240 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 172:65be27845400 19241 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 172:65be27845400 19242 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19243 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 172:65be27845400 19244
AnnaBridge 172:65be27845400 19245 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 172:65be27845400 19246 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 172:65be27845400 19247 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19248 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 172:65be27845400 19249 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 172:65be27845400 19250 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19251 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 172:65be27845400 19252 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 172:65be27845400 19253 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19254 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 172:65be27845400 19255 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 172:65be27845400 19256 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19257 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 172:65be27845400 19258 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 172:65be27845400 19259 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19260 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 172:65be27845400 19261 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 172:65be27845400 19262 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19263 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 172:65be27845400 19264 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 172:65be27845400 19265 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19266 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 172:65be27845400 19267 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 172:65be27845400 19268 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19269 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 172:65be27845400 19270 #define TIM_SR_B2IF_Pos (8U)
AnnaBridge 172:65be27845400 19271 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19272 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
AnnaBridge 172:65be27845400 19273 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 172:65be27845400 19274 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19275 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 172:65be27845400 19276 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 172:65be27845400 19277 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19278 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 172:65be27845400 19279 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 172:65be27845400 19280 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19281 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 172:65be27845400 19282 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 172:65be27845400 19283 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19284 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 172:65be27845400 19285 #define TIM_SR_CC5IF_Pos (16U)
AnnaBridge 172:65be27845400 19286 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19287 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
AnnaBridge 172:65be27845400 19288 #define TIM_SR_CC6IF_Pos (17U)
AnnaBridge 172:65be27845400 19289 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19290 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
AnnaBridge 172:65be27845400 19291 #define TIM_SR_SBIF_Pos (13U)
AnnaBridge 172:65be27845400 19292 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19293 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
AnnaBridge 172:65be27845400 19294
AnnaBridge 172:65be27845400 19295 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 172:65be27845400 19296 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 172:65be27845400 19297 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19298 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 172:65be27845400 19299 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 172:65be27845400 19300 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19301 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 172:65be27845400 19302 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 172:65be27845400 19303 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19304 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 172:65be27845400 19305 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 172:65be27845400 19306 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19307 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 172:65be27845400 19308 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 172:65be27845400 19309 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19310 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 172:65be27845400 19311 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 172:65be27845400 19312 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19313 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 172:65be27845400 19314 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 172:65be27845400 19315 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19316 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 172:65be27845400 19317 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 172:65be27845400 19318 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19319 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 172:65be27845400 19320 #define TIM_EGR_B2G_Pos (8U)
AnnaBridge 172:65be27845400 19321 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19322 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
AnnaBridge 172:65be27845400 19323
AnnaBridge 172:65be27845400 19324
AnnaBridge 172:65be27845400 19325 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 172:65be27845400 19326 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 172:65be27845400 19327 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 19328 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 172:65be27845400 19329 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19330 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19331
AnnaBridge 172:65be27845400 19332 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 172:65be27845400 19333 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19334 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 172:65be27845400 19335 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 172:65be27845400 19336 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19337 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 172:65be27845400 19338
AnnaBridge 172:65be27845400 19339 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 172:65be27845400 19340 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
AnnaBridge 172:65be27845400 19341 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 172:65be27845400 19342 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19343 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19344 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19345 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19346
AnnaBridge 172:65be27845400 19347 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 172:65be27845400 19348 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19349 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 172:65be27845400 19350
AnnaBridge 172:65be27845400 19351 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 172:65be27845400 19352 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 19353 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 172:65be27845400 19354 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19355 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19356
AnnaBridge 172:65be27845400 19357 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 172:65be27845400 19358 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19359 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 172:65be27845400 19360 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 172:65be27845400 19361 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19362 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 172:65be27845400 19363
AnnaBridge 172:65be27845400 19364 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 172:65be27845400 19365 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
AnnaBridge 172:65be27845400 19366 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 172:65be27845400 19367 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19368 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19369 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19370 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 19371
AnnaBridge 172:65be27845400 19372 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 172:65be27845400 19373 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19374 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 172:65be27845400 19375
AnnaBridge 172:65be27845400 19376 /*----------------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 19377
AnnaBridge 172:65be27845400 19378 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 172:65be27845400 19379 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 19380 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 172:65be27845400 19381 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19382 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19383
AnnaBridge 172:65be27845400 19384 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 172:65be27845400 19385 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 19386 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 172:65be27845400 19387 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19388 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19389 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19390 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19391
AnnaBridge 172:65be27845400 19392 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 172:65be27845400 19393 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 19394 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 172:65be27845400 19395 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19396 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19397
AnnaBridge 172:65be27845400 19398 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 172:65be27845400 19399 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 19400 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 172:65be27845400 19401 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19402 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19403 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19404 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19405
AnnaBridge 172:65be27845400 19406 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 172:65be27845400 19407 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 172:65be27845400 19408 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 19409 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 172:65be27845400 19410 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19411 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19412
AnnaBridge 172:65be27845400 19413 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 172:65be27845400 19414 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19415 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 172:65be27845400 19416 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 172:65be27845400 19417 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19418 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 172:65be27845400 19419
AnnaBridge 172:65be27845400 19420 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 172:65be27845400 19421 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 19422 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 172:65be27845400 19423 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19424 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19425 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19426 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19427
AnnaBridge 172:65be27845400 19428 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 172:65be27845400 19429 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19430 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 172:65be27845400 19431
AnnaBridge 172:65be27845400 19432 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 172:65be27845400 19433 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 19434 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 172:65be27845400 19435 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19436 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19437
AnnaBridge 172:65be27845400 19438 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 172:65be27845400 19439 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19440 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 172:65be27845400 19441 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 172:65be27845400 19442 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19443 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 172:65be27845400 19444
AnnaBridge 172:65be27845400 19445 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 172:65be27845400 19446 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 19447 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 172:65be27845400 19448 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19449 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19450 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19451 #define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 19452
AnnaBridge 172:65be27845400 19453 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 172:65be27845400 19454 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19455 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 172:65be27845400 19456
AnnaBridge 172:65be27845400 19457 /*----------------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 19458
AnnaBridge 172:65be27845400 19459 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 172:65be27845400 19460 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 172:65be27845400 19461 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 172:65be27845400 19462 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19463 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19464
AnnaBridge 172:65be27845400 19465 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 172:65be27845400 19466 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 172:65be27845400 19467 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 172:65be27845400 19468 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19469 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19470 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19471 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19472
AnnaBridge 172:65be27845400 19473 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 172:65be27845400 19474 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 19475 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 172:65be27845400 19476 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19477 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19478
AnnaBridge 172:65be27845400 19479 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 172:65be27845400 19480 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 19481 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 172:65be27845400 19482 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19483 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19484 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19485 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19486
AnnaBridge 172:65be27845400 19487 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 172:65be27845400 19488 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 172:65be27845400 19489 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19490 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 172:65be27845400 19491 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 172:65be27845400 19492 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19493 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 172:65be27845400 19494 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 172:65be27845400 19495 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19496 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 172:65be27845400 19497 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 172:65be27845400 19498 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19499 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 172:65be27845400 19500 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 172:65be27845400 19501 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19502 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 172:65be27845400 19503 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 172:65be27845400 19504 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19505 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 172:65be27845400 19506 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 172:65be27845400 19507 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19508 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 172:65be27845400 19509 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 172:65be27845400 19510 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19511 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 172:65be27845400 19512 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 172:65be27845400 19513 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19514 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 172:65be27845400 19515 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 172:65be27845400 19516 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19517 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 172:65be27845400 19518 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 172:65be27845400 19519 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19520 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 172:65be27845400 19521 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 172:65be27845400 19522 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19523 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 172:65be27845400 19524 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 172:65be27845400 19525 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19526 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 172:65be27845400 19527 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 172:65be27845400 19528 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19529 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 172:65be27845400 19530 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 172:65be27845400 19531 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19532 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 172:65be27845400 19533 #define TIM_CCER_CC5E_Pos (16U)
AnnaBridge 172:65be27845400 19534 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19535 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
AnnaBridge 172:65be27845400 19536 #define TIM_CCER_CC5P_Pos (17U)
AnnaBridge 172:65be27845400 19537 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19538 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
AnnaBridge 172:65be27845400 19539 #define TIM_CCER_CC6E_Pos (20U)
AnnaBridge 172:65be27845400 19540 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 19541 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
AnnaBridge 172:65be27845400 19542 #define TIM_CCER_CC6P_Pos (21U)
AnnaBridge 172:65be27845400 19543 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 19544 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
AnnaBridge 172:65be27845400 19545 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 172:65be27845400 19546 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 172:65be27845400 19547 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 19548 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 172:65be27845400 19549 #define TIM_CNT_UIFCPY_Pos (31U)
AnnaBridge 172:65be27845400 19550 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 19551 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
AnnaBridge 172:65be27845400 19552 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 172:65be27845400 19553 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 172:65be27845400 19554 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 19555 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 172:65be27845400 19556
AnnaBridge 172:65be27845400 19557 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 172:65be27845400 19558 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 172:65be27845400 19559 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 19560 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 172:65be27845400 19561
AnnaBridge 172:65be27845400 19562 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 172:65be27845400 19563 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 172:65be27845400 19564 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 19565 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 172:65be27845400 19566
AnnaBridge 172:65be27845400 19567 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 172:65be27845400 19568 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 172:65be27845400 19569 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 19570 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 172:65be27845400 19571
AnnaBridge 172:65be27845400 19572 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 172:65be27845400 19573 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 172:65be27845400 19574 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 19575 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 172:65be27845400 19576
AnnaBridge 172:65be27845400 19577 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 172:65be27845400 19578 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 172:65be27845400 19579 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 19580 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 172:65be27845400 19581
AnnaBridge 172:65be27845400 19582 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 172:65be27845400 19583 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 172:65be27845400 19584 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 19585 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 172:65be27845400 19586
AnnaBridge 172:65be27845400 19587 /******************* Bit definition for TIM_CCR5 register *******************/
AnnaBridge 172:65be27845400 19588 #define TIM_CCR5_CCR5_Pos (0U)
AnnaBridge 172:65be27845400 19589 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 19590 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
AnnaBridge 172:65be27845400 19591 #define TIM_CCR5_GC5C1_Pos (29U)
AnnaBridge 172:65be27845400 19592 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 19593 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
AnnaBridge 172:65be27845400 19594 #define TIM_CCR5_GC5C2_Pos (30U)
AnnaBridge 172:65be27845400 19595 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 19596 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
AnnaBridge 172:65be27845400 19597 #define TIM_CCR5_GC5C3_Pos (31U)
AnnaBridge 172:65be27845400 19598 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 19599 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
AnnaBridge 172:65be27845400 19600
AnnaBridge 172:65be27845400 19601 /******************* Bit definition for TIM_CCR6 register *******************/
AnnaBridge 172:65be27845400 19602 #define TIM_CCR6_CCR6_Pos (0U)
AnnaBridge 172:65be27845400 19603 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 19604 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
AnnaBridge 172:65be27845400 19605
AnnaBridge 172:65be27845400 19606 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 172:65be27845400 19607 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 172:65be27845400 19608 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 19609 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 172:65be27845400 19610 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19611 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19612 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19613 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19614 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19615 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19616 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19617 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19618
AnnaBridge 172:65be27845400 19619 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 172:65be27845400 19620 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 19621 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 172:65be27845400 19622 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19623 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19624
AnnaBridge 172:65be27845400 19625 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 172:65be27845400 19626 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19627 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 172:65be27845400 19628 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 172:65be27845400 19629 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19630 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 172:65be27845400 19631 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 172:65be27845400 19632 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19633 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
AnnaBridge 172:65be27845400 19634 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 172:65be27845400 19635 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19636 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
AnnaBridge 172:65be27845400 19637 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 172:65be27845400 19638 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19639 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 172:65be27845400 19640 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 172:65be27845400 19641 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19642 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 172:65be27845400 19643
AnnaBridge 172:65be27845400 19644 #define TIM_BDTR_BKF_Pos (16U)
AnnaBridge 172:65be27845400 19645 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 19646 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
AnnaBridge 172:65be27845400 19647 #define TIM_BDTR_BK2F_Pos (20U)
AnnaBridge 172:65be27845400 19648 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
AnnaBridge 172:65be27845400 19649 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
AnnaBridge 172:65be27845400 19650
AnnaBridge 172:65be27845400 19651 #define TIM_BDTR_BK2E_Pos (24U)
AnnaBridge 172:65be27845400 19652 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 19653 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
AnnaBridge 172:65be27845400 19654 #define TIM_BDTR_BK2P_Pos (25U)
AnnaBridge 172:65be27845400 19655 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 19656 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
AnnaBridge 172:65be27845400 19657
AnnaBridge 172:65be27845400 19658 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 172:65be27845400 19659 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 172:65be27845400 19660 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 19661 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 172:65be27845400 19662 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19663 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19664 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19665 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19666 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19667
AnnaBridge 172:65be27845400 19668 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 172:65be27845400 19669 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 19670 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 172:65be27845400 19671 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19672 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19673 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19674 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19675 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19676
AnnaBridge 172:65be27845400 19677 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 172:65be27845400 19678 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 172:65be27845400 19679 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 19680 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 172:65be27845400 19681
AnnaBridge 172:65be27845400 19682 /****************** Bit definition for TIM_CCMR3 register *******************/
AnnaBridge 172:65be27845400 19683 #define TIM_CCMR3_OC5FE_Pos (2U)
AnnaBridge 172:65be27845400 19684 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19685 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
AnnaBridge 172:65be27845400 19686 #define TIM_CCMR3_OC5PE_Pos (3U)
AnnaBridge 172:65be27845400 19687 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19688 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
AnnaBridge 172:65be27845400 19689
AnnaBridge 172:65be27845400 19690 #define TIM_CCMR3_OC5M_Pos (4U)
AnnaBridge 172:65be27845400 19691 #define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 19692 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
AnnaBridge 172:65be27845400 19693 #define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19694 #define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19695 #define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19696 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19697
AnnaBridge 172:65be27845400 19698 #define TIM_CCMR3_OC5CE_Pos (7U)
AnnaBridge 172:65be27845400 19699 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 19700 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
AnnaBridge 172:65be27845400 19701
AnnaBridge 172:65be27845400 19702 #define TIM_CCMR3_OC6FE_Pos (10U)
AnnaBridge 172:65be27845400 19703 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19704 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 172:65be27845400 19705 #define TIM_CCMR3_OC6PE_Pos (11U)
AnnaBridge 172:65be27845400 19706 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19707 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 172:65be27845400 19708
AnnaBridge 172:65be27845400 19709 #define TIM_CCMR3_OC6M_Pos (12U)
AnnaBridge 172:65be27845400 19710 #define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
AnnaBridge 172:65be27845400 19711 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 172:65be27845400 19712 #define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 19713 #define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 19714 #define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19715 #define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 19716
AnnaBridge 172:65be27845400 19717 #define TIM_CCMR3_OC6CE_Pos (15U)
AnnaBridge 172:65be27845400 19718 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19719 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 172:65be27845400 19720 /******************* Bit definition for TIM1_AF1 register *********************/
AnnaBridge 172:65be27845400 19721 #define TIM1_AF1_BKINE_Pos (0U)
AnnaBridge 172:65be27845400 19722 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19723 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
AnnaBridge 172:65be27845400 19724 #define TIM1_AF1_BKCMP1E_Pos (1U)
AnnaBridge 172:65be27845400 19725 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19726 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
AnnaBridge 172:65be27845400 19727 #define TIM1_AF1_BKCMP2E_Pos (2U)
AnnaBridge 172:65be27845400 19728 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19729 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
AnnaBridge 172:65be27845400 19730 #define TIM1_AF1_BKDF1BK0E_Pos (8U)
AnnaBridge 172:65be27845400 19731 #define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19732 #define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
AnnaBridge 172:65be27845400 19733 #define TIM1_AF1_BKINP_Pos (9U)
AnnaBridge 172:65be27845400 19734 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19735 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
AnnaBridge 172:65be27845400 19736 #define TIM1_AF1_BKCMP1P_Pos (10U)
AnnaBridge 172:65be27845400 19737 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19738 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
AnnaBridge 172:65be27845400 19739 #define TIM1_AF1_BKCMP2P_Pos (11U)
AnnaBridge 172:65be27845400 19740 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19741 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
AnnaBridge 172:65be27845400 19742
AnnaBridge 172:65be27845400 19743 #define TIM1_AF1_ETRSEL_Pos (14U)
AnnaBridge 172:65be27845400 19744 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 19745 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
AnnaBridge 172:65be27845400 19746 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19747 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19748 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19749 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19750
AnnaBridge 172:65be27845400 19751 /******************* Bit definition for TIM1_AF2 register *********************/
AnnaBridge 172:65be27845400 19752 #define TIM1_AF2_BK2INE_Pos (0U)
AnnaBridge 172:65be27845400 19753 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19754 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
AnnaBridge 172:65be27845400 19755 #define TIM1_AF2_BK2CMP1E_Pos (1U)
AnnaBridge 172:65be27845400 19756 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19757 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
AnnaBridge 172:65be27845400 19758 #define TIM1_AF2_BK2CMP2E_Pos (2U)
AnnaBridge 172:65be27845400 19759 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19760 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
AnnaBridge 172:65be27845400 19761 #define TIM1_AF2_BK2DFBK1E_Pos (8U)
AnnaBridge 172:65be27845400 19762 #define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19763 #define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
AnnaBridge 172:65be27845400 19764 #define TIM1_AF2_BK2INP_Pos (9U)
AnnaBridge 172:65be27845400 19765 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19766 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
AnnaBridge 172:65be27845400 19767 #define TIM1_AF2_BK2CMP1P_Pos (10U)
AnnaBridge 172:65be27845400 19768 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19769 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
AnnaBridge 172:65be27845400 19770 #define TIM1_AF2_BK2CMP2P_Pos (11U)
AnnaBridge 172:65be27845400 19771 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19772 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
AnnaBridge 172:65be27845400 19773
AnnaBridge 172:65be27845400 19774 /******************* Bit definition for TIM_TISEL register *********************/
AnnaBridge 172:65be27845400 19775 #define TIM_TISEL_TI1SEL_Pos (0U)
AnnaBridge 172:65be27845400 19776 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 19777 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
AnnaBridge 172:65be27845400 19778 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19779 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19780 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19781 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19782
AnnaBridge 172:65be27845400 19783 #define TIM_TISEL_TI2SEL_Pos (8U)
AnnaBridge 172:65be27845400 19784 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 19785 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
AnnaBridge 172:65be27845400 19786 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19787 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19788 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19789 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19790
AnnaBridge 172:65be27845400 19791 #define TIM_TISEL_TI3SEL_Pos (16U)
AnnaBridge 172:65be27845400 19792 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
AnnaBridge 172:65be27845400 19793 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
AnnaBridge 172:65be27845400 19794 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19795 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19796 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 19797 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 19798
AnnaBridge 172:65be27845400 19799 #define TIM_TISEL_TI4SEL_Pos (24U)
AnnaBridge 172:65be27845400 19800 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 19801 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
AnnaBridge 172:65be27845400 19802 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 19803 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 19804 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 19805 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 19806
AnnaBridge 172:65be27845400 19807 /******************* Bit definition for TIM8_AF1 register *********************/
AnnaBridge 172:65be27845400 19808 #define TIM8_AF1_BKINE_Pos (0U)
AnnaBridge 172:65be27845400 19809 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19810 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
AnnaBridge 172:65be27845400 19811 #define TIM8_AF1_BKCMP1E_Pos (1U)
AnnaBridge 172:65be27845400 19812 #define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19813 #define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
AnnaBridge 172:65be27845400 19814 #define TIM8_AF1_BKCMP2E_Pos (2U)
AnnaBridge 172:65be27845400 19815 #define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19816 #define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
AnnaBridge 172:65be27845400 19817 #define TIM8_AF1_BKDFBK2E_Pos (8U)
AnnaBridge 172:65be27845400 19818 #define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19819 #define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
AnnaBridge 172:65be27845400 19820 #define TIM8_AF1_BKINP_Pos (9U)
AnnaBridge 172:65be27845400 19821 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19822 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
AnnaBridge 172:65be27845400 19823 #define TIM8_AF1_BKCMP1P_Pos (10U)
AnnaBridge 172:65be27845400 19824 #define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19825 #define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
AnnaBridge 172:65be27845400 19826 #define TIM8_AF1_BKCMP2P_Pos (11U)
AnnaBridge 172:65be27845400 19827 #define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19828 #define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
AnnaBridge 172:65be27845400 19829
AnnaBridge 172:65be27845400 19830 #define TIM8_AF1_ETRSEL_Pos (14U)
AnnaBridge 172:65be27845400 19831 #define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 19832 #define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
AnnaBridge 172:65be27845400 19833 #define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19834 #define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19835 #define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19836 #define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19837 /******************* Bit definition for TIM8_AF2 register *********************/
AnnaBridge 172:65be27845400 19838 #define TIM8_AF2_BK2INE_Pos (0U)
AnnaBridge 172:65be27845400 19839 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19840 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
AnnaBridge 172:65be27845400 19841 #define TIM8_AF2_BK2CMP1E_Pos (1U)
AnnaBridge 172:65be27845400 19842 #define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19843 #define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
AnnaBridge 172:65be27845400 19844 #define TIM8_AF2_BK2CMP2E_Pos (2U)
AnnaBridge 172:65be27845400 19845 #define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19846 #define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
AnnaBridge 172:65be27845400 19847 #define TIM8_AF2_BK2DFBK3E_Pos (8U)
AnnaBridge 172:65be27845400 19848 #define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19849 #define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
AnnaBridge 172:65be27845400 19850 #define TIM8_AF2_BK2INP_Pos (9U)
AnnaBridge 172:65be27845400 19851 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19852 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
AnnaBridge 172:65be27845400 19853 #define TIM8_AF2_BK2CMP1P_Pos (10U)
AnnaBridge 172:65be27845400 19854 #define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19855 #define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
AnnaBridge 172:65be27845400 19856 #define TIM8_AF2_BK2CMP2P_Pos (11U)
AnnaBridge 172:65be27845400 19857 #define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19858 #define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
AnnaBridge 172:65be27845400 19859
AnnaBridge 172:65be27845400 19860 /******************* Bit definition for TIM2_AF1 register *********************/
AnnaBridge 172:65be27845400 19861 #define TIM2_AF1_ETRSEL_Pos (14U)
AnnaBridge 172:65be27845400 19862 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 19863 #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
AnnaBridge 172:65be27845400 19864 #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19865 #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19866 #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19867 #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19868
AnnaBridge 172:65be27845400 19869 /******************* Bit definition for TIM3_AF1 register *********************/
AnnaBridge 172:65be27845400 19870 #define TIM3_AF1_ETRSEL_Pos (14U)
AnnaBridge 172:65be27845400 19871 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 19872 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
AnnaBridge 172:65be27845400 19873 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19874 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19875 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19876 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19877
AnnaBridge 172:65be27845400 19878 /******************* Bit definition for TIM5_AF1 register *********************/
AnnaBridge 172:65be27845400 19879 #define TIM5_AF1_ETRSEL_Pos (14U)
AnnaBridge 172:65be27845400 19880 #define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
AnnaBridge 172:65be27845400 19881 #define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
AnnaBridge 172:65be27845400 19882 #define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 19883 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 19884 #define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 19885 #define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 19886
AnnaBridge 172:65be27845400 19887 /******************* Bit definition for TIM15_AF1 register *********************/
AnnaBridge 172:65be27845400 19888 #define TIM15_AF1_BKINE_Pos (0U)
AnnaBridge 172:65be27845400 19889 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19890 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
AnnaBridge 172:65be27845400 19891 #define TIM15_AF1_BKCMP1E_Pos (1U)
AnnaBridge 172:65be27845400 19892 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19893 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
AnnaBridge 172:65be27845400 19894 #define TIM15_AF1_BKCMP2E_Pos (2U)
AnnaBridge 172:65be27845400 19895 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19896 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
AnnaBridge 172:65be27845400 19897 #define TIM15_AF1_BKDF1BK2E_Pos (8U)
AnnaBridge 172:65be27845400 19898 #define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19899 #define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
AnnaBridge 172:65be27845400 19900 #define TIM15_AF1_BKINP_Pos (9U)
AnnaBridge 172:65be27845400 19901 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19902 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
AnnaBridge 172:65be27845400 19903 #define TIM15_AF1_BKCMP1P_Pos (10U)
AnnaBridge 172:65be27845400 19904 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19905 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
AnnaBridge 172:65be27845400 19906 #define TIM15_AF1_BKCMP2P_Pos (11U)
AnnaBridge 172:65be27845400 19907 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19908 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
AnnaBridge 172:65be27845400 19909
AnnaBridge 172:65be27845400 19910 /******************* Bit definition for TIM16_ register *********************/
AnnaBridge 172:65be27845400 19911 #define TIM16_AF1_BKINE_Pos (0U)
AnnaBridge 172:65be27845400 19912 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19913 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
AnnaBridge 172:65be27845400 19914 #define TIM16_AF1_BKCMP1E_Pos (1U)
AnnaBridge 172:65be27845400 19915 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19916 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
AnnaBridge 172:65be27845400 19917 #define TIM16_AF1_BKCMP2E_Pos (2U)
AnnaBridge 172:65be27845400 19918 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19919 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
AnnaBridge 172:65be27845400 19920 #define TIM16_AF1_BKDF1BK2E_Pos (8U)
AnnaBridge 172:65be27845400 19921 #define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19922 #define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
AnnaBridge 172:65be27845400 19923 #define TIM16_AF1_BKINP_Pos (9U)
AnnaBridge 172:65be27845400 19924 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19925 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
AnnaBridge 172:65be27845400 19926 #define TIM16_AF1_BKCMP1P_Pos (10U)
AnnaBridge 172:65be27845400 19927 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19928 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
AnnaBridge 172:65be27845400 19929 #define TIM16_AF1_BKCMP2P_Pos (11U)
AnnaBridge 172:65be27845400 19930 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19931 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
AnnaBridge 172:65be27845400 19932
AnnaBridge 172:65be27845400 19933 /******************* Bit definition for TIM17_AF1 register *********************/
AnnaBridge 172:65be27845400 19934 #define TIM17_AF1_BKINE_Pos (0U)
AnnaBridge 172:65be27845400 19935 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19936 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
AnnaBridge 172:65be27845400 19937 #define TIM17_AF1_BKCMP1E_Pos (1U)
AnnaBridge 172:65be27845400 19938 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19939 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
AnnaBridge 172:65be27845400 19940 #define TIM17_AF1_BKCMP2E_Pos (2U)
AnnaBridge 172:65be27845400 19941 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19942 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
AnnaBridge 172:65be27845400 19943 #define TIM17_AF1_BKDF1BK2E_Pos (8U)
AnnaBridge 172:65be27845400 19944 #define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 19945 #define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
AnnaBridge 172:65be27845400 19946 #define TIM17_AF1_BKINP_Pos (9U)
AnnaBridge 172:65be27845400 19947 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 19948 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
AnnaBridge 172:65be27845400 19949 #define TIM17_AF1_BKCMP1P_Pos (10U)
AnnaBridge 172:65be27845400 19950 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 19951 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
AnnaBridge 172:65be27845400 19952 #define TIM17_AF1_BKCMP2P_Pos (11U)
AnnaBridge 172:65be27845400 19953 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 19954 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
AnnaBridge 172:65be27845400 19955
AnnaBridge 172:65be27845400 19956 /******************************************************************************/
AnnaBridge 172:65be27845400 19957 /* */
AnnaBridge 172:65be27845400 19958 /* Low Power Timer (LPTTIM) */
AnnaBridge 172:65be27845400 19959 /* */
AnnaBridge 172:65be27845400 19960 /******************************************************************************/
AnnaBridge 172:65be27845400 19961 /****************** Bit definition for LPTIM_ISR register *******************/
AnnaBridge 172:65be27845400 19962 #define LPTIM_ISR_CMPM_Pos (0U)
AnnaBridge 172:65be27845400 19963 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19964 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
AnnaBridge 172:65be27845400 19965 #define LPTIM_ISR_ARRM_Pos (1U)
AnnaBridge 172:65be27845400 19966 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19967 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
AnnaBridge 172:65be27845400 19968 #define LPTIM_ISR_EXTTRIG_Pos (2U)
AnnaBridge 172:65be27845400 19969 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19970 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
AnnaBridge 172:65be27845400 19971 #define LPTIM_ISR_CMPOK_Pos (3U)
AnnaBridge 172:65be27845400 19972 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19973 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
AnnaBridge 172:65be27845400 19974 #define LPTIM_ISR_ARROK_Pos (4U)
AnnaBridge 172:65be27845400 19975 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19976 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
AnnaBridge 172:65be27845400 19977 #define LPTIM_ISR_UP_Pos (5U)
AnnaBridge 172:65be27845400 19978 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 19979 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
AnnaBridge 172:65be27845400 19980 #define LPTIM_ISR_DOWN_Pos (6U)
AnnaBridge 172:65be27845400 19981 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 19982 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
AnnaBridge 172:65be27845400 19983
AnnaBridge 172:65be27845400 19984 /****************** Bit definition for LPTIM_ICR register *******************/
AnnaBridge 172:65be27845400 19985 #define LPTIM_ICR_CMPMCF_Pos (0U)
AnnaBridge 172:65be27845400 19986 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 19987 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
AnnaBridge 172:65be27845400 19988 #define LPTIM_ICR_ARRMCF_Pos (1U)
AnnaBridge 172:65be27845400 19989 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 19990 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
AnnaBridge 172:65be27845400 19991 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
AnnaBridge 172:65be27845400 19992 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 19993 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
AnnaBridge 172:65be27845400 19994 #define LPTIM_ICR_CMPOKCF_Pos (3U)
AnnaBridge 172:65be27845400 19995 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 19996 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
AnnaBridge 172:65be27845400 19997 #define LPTIM_ICR_ARROKCF_Pos (4U)
AnnaBridge 172:65be27845400 19998 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 19999 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
AnnaBridge 172:65be27845400 20000 #define LPTIM_ICR_UPCF_Pos (5U)
AnnaBridge 172:65be27845400 20001 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20002 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
AnnaBridge 172:65be27845400 20003 #define LPTIM_ICR_DOWNCF_Pos (6U)
AnnaBridge 172:65be27845400 20004 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20005 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
AnnaBridge 172:65be27845400 20006
AnnaBridge 172:65be27845400 20007 /****************** Bit definition for LPTIM_IER register ********************/
AnnaBridge 172:65be27845400 20008 #define LPTIM_IER_CMPMIE_Pos (0U)
AnnaBridge 172:65be27845400 20009 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20010 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
AnnaBridge 172:65be27845400 20011 #define LPTIM_IER_ARRMIE_Pos (1U)
AnnaBridge 172:65be27845400 20012 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20013 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
AnnaBridge 172:65be27845400 20014 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
AnnaBridge 172:65be27845400 20015 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20016 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
AnnaBridge 172:65be27845400 20017 #define LPTIM_IER_CMPOKIE_Pos (3U)
AnnaBridge 172:65be27845400 20018 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20019 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
AnnaBridge 172:65be27845400 20020 #define LPTIM_IER_ARROKIE_Pos (4U)
AnnaBridge 172:65be27845400 20021 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20022 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 172:65be27845400 20023 #define LPTIM_IER_UPIE_Pos (5U)
AnnaBridge 172:65be27845400 20024 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20025 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
AnnaBridge 172:65be27845400 20026 #define LPTIM_IER_DOWNIE_Pos (6U)
AnnaBridge 172:65be27845400 20027 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20028 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
AnnaBridge 172:65be27845400 20029
AnnaBridge 172:65be27845400 20030 /****************** Bit definition for LPTIM_CFGR register *******************/
AnnaBridge 172:65be27845400 20031 #define LPTIM_CFGR_CKSEL_Pos (0U)
AnnaBridge 172:65be27845400 20032 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20033 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
AnnaBridge 172:65be27845400 20034
AnnaBridge 172:65be27845400 20035 #define LPTIM_CFGR_CKPOL_Pos (1U)
AnnaBridge 172:65be27845400 20036 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 20037 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
AnnaBridge 172:65be27845400 20038 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20039 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20040
AnnaBridge 172:65be27845400 20041 #define LPTIM_CFGR_CKFLT_Pos (3U)
AnnaBridge 172:65be27845400 20042 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 20043 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
AnnaBridge 172:65be27845400 20044 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20045 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20046
AnnaBridge 172:65be27845400 20047 #define LPTIM_CFGR_TRGFLT_Pos (6U)
AnnaBridge 172:65be27845400 20048 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 20049 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
AnnaBridge 172:65be27845400 20050 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20051 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20052
AnnaBridge 172:65be27845400 20053 #define LPTIM_CFGR_PRESC_Pos (9U)
AnnaBridge 172:65be27845400 20054 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
AnnaBridge 172:65be27845400 20055 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
AnnaBridge 172:65be27845400 20056 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20057 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20058 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20059
AnnaBridge 172:65be27845400 20060 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
AnnaBridge 172:65be27845400 20061 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
AnnaBridge 172:65be27845400 20062 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
AnnaBridge 172:65be27845400 20063 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20064 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 20065 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 20066
AnnaBridge 172:65be27845400 20067 #define LPTIM_CFGR_TRIGEN_Pos (17U)
AnnaBridge 172:65be27845400 20068 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 20069 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
AnnaBridge 172:65be27845400 20070 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20071 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 20072
AnnaBridge 172:65be27845400 20073 #define LPTIM_CFGR_TIMOUT_Pos (19U)
AnnaBridge 172:65be27845400 20074 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 20075 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
AnnaBridge 172:65be27845400 20076 #define LPTIM_CFGR_WAVE_Pos (20U)
AnnaBridge 172:65be27845400 20077 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20078 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
AnnaBridge 172:65be27845400 20079 #define LPTIM_CFGR_WAVPOL_Pos (21U)
AnnaBridge 172:65be27845400 20080 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 20081 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
AnnaBridge 172:65be27845400 20082 #define LPTIM_CFGR_PRELOAD_Pos (22U)
AnnaBridge 172:65be27845400 20083 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 20084 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
AnnaBridge 172:65be27845400 20085 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
AnnaBridge 172:65be27845400 20086 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 20087 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
AnnaBridge 172:65be27845400 20088 #define LPTIM_CFGR_ENC_Pos (24U)
AnnaBridge 172:65be27845400 20089 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 20090 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
AnnaBridge 172:65be27845400 20091
AnnaBridge 172:65be27845400 20092 /****************** Bit definition for LPTIM_CR register ********************/
AnnaBridge 172:65be27845400 20093 #define LPTIM_CR_ENABLE_Pos (0U)
AnnaBridge 172:65be27845400 20094 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20095 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
AnnaBridge 172:65be27845400 20096 #define LPTIM_CR_SNGSTRT_Pos (1U)
AnnaBridge 172:65be27845400 20097 #define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
AnnaBridge 172:65be27845400 20098 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
AnnaBridge 172:65be27845400 20099 #define LPTIM_CR_CNTSTRT_Pos (2U)
AnnaBridge 172:65be27845400 20100 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20101 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
AnnaBridge 172:65be27845400 20102 #define LPTIM_CR_COUNTRST_Pos (3U)
AnnaBridge 172:65be27845400 20103 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20104 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
AnnaBridge 172:65be27845400 20105 #define LPTIM_CR_RSTARE_Pos (4U)
AnnaBridge 172:65be27845400 20106 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20107 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
AnnaBridge 172:65be27845400 20108
AnnaBridge 172:65be27845400 20109
AnnaBridge 172:65be27845400 20110 /****************** Bit definition for LPTIM_CMP register *******************/
AnnaBridge 172:65be27845400 20111 #define LPTIM_CMP_CMP_Pos (0U)
AnnaBridge 172:65be27845400 20112 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 20113 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
AnnaBridge 172:65be27845400 20114
AnnaBridge 172:65be27845400 20115 /****************** Bit definition for LPTIM_ARR register *******************/
AnnaBridge 172:65be27845400 20116 #define LPTIM_ARR_ARR_Pos (0U)
AnnaBridge 172:65be27845400 20117 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 20118 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
AnnaBridge 172:65be27845400 20119
AnnaBridge 172:65be27845400 20120 /****************** Bit definition for LPTIM_CNT register *******************/
AnnaBridge 172:65be27845400 20121 #define LPTIM_CNT_CNT_Pos (0U)
AnnaBridge 172:65be27845400 20122 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 20123 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
AnnaBridge 172:65be27845400 20124
AnnaBridge 172:65be27845400 20125 /****************** Bit definition for LPTIM_CFGR2 register *****************/
AnnaBridge 172:65be27845400 20126 #define LPTIM_CFGR2_IN1SEL_Pos (0U)
AnnaBridge 172:65be27845400 20127 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 20128 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
AnnaBridge 172:65be27845400 20129 #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20130 #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20131 #define LPTIM_CFGR2_IN2SEL_Pos (4U)
AnnaBridge 172:65be27845400 20132 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 20133 #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
AnnaBridge 172:65be27845400 20134 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20135 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20136
AnnaBridge 172:65be27845400 20137 /******************************************************************************/
AnnaBridge 172:65be27845400 20138 /* */
AnnaBridge 172:65be27845400 20139 /* Analog Comparators (COMP) */
AnnaBridge 172:65be27845400 20140 /* */
AnnaBridge 172:65be27845400 20141 /******************************************************************************/
AnnaBridge 172:65be27845400 20142
AnnaBridge 172:65be27845400 20143 /******************* Bit definition for COMP_SR register ********************/
AnnaBridge 172:65be27845400 20144 #define COMP_SR_C1VAL_Pos (0U)
AnnaBridge 172:65be27845400 20145 #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20146 #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
AnnaBridge 172:65be27845400 20147 #define COMP_SR_C2VAL_Pos (1U)
AnnaBridge 172:65be27845400 20148 #define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20149 #define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
AnnaBridge 172:65be27845400 20150 #define COMP_SR_C1IF_Pos (16U)
AnnaBridge 172:65be27845400 20151 #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 20152 #define COMP_SR_C1IF COMP_SR_C1IF_Msk
AnnaBridge 172:65be27845400 20153 #define COMP_SR_C2IF_Pos (17U)
AnnaBridge 172:65be27845400 20154 #define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20155 #define COMP_SR_C2IF COMP_SR_C2IF_Msk
AnnaBridge 172:65be27845400 20156 /******************* Bit definition for COMP_ICFR register ********************/
AnnaBridge 172:65be27845400 20157 #define COMP_ICFR_C1IF_Pos (16U)
AnnaBridge 172:65be27845400 20158 #define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 20159 #define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
AnnaBridge 172:65be27845400 20160 #define COMP_ICFR_C2IF_Pos (17U)
AnnaBridge 172:65be27845400 20161 #define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20162 #define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
AnnaBridge 172:65be27845400 20163 /******************* Bit definition for COMP_OR register ********************/
AnnaBridge 172:65be27845400 20164 #define COMP_OR_AFOPA6_Pos (0U)
AnnaBridge 172:65be27845400 20165 #define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20166 #define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
AnnaBridge 172:65be27845400 20167 #define COMP_OR_AFOPA8_Pos (1U)
AnnaBridge 172:65be27845400 20168 #define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20169 #define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
AnnaBridge 172:65be27845400 20170 #define COMP_OR_AFOPB12_Pos (2U)
AnnaBridge 172:65be27845400 20171 #define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20172 #define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
AnnaBridge 172:65be27845400 20173 #define COMP_OR_AFOPE6_Pos (3U)
AnnaBridge 172:65be27845400 20174 #define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20175 #define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
AnnaBridge 172:65be27845400 20176 #define COMP_OR_AFOPE15_Pos (4U)
AnnaBridge 172:65be27845400 20177 #define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20178 #define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
AnnaBridge 172:65be27845400 20179 #define COMP_OR_AFOPG2_Pos (5U)
AnnaBridge 172:65be27845400 20180 #define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20181 #define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
AnnaBridge 172:65be27845400 20182 #define COMP_OR_AFOPG3_Pos (6U)
AnnaBridge 172:65be27845400 20183 #define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20184 #define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
AnnaBridge 172:65be27845400 20185 #define COMP_OR_AFOPG4_Pos (7U)
AnnaBridge 172:65be27845400 20186 #define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20187 #define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
AnnaBridge 172:65be27845400 20188 #define COMP_OR_AFOPI1_Pos (8U)
AnnaBridge 172:65be27845400 20189 #define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20190 #define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
AnnaBridge 172:65be27845400 20191 #define COMP_OR_AFOPI4_Pos (9U)
AnnaBridge 172:65be27845400 20192 #define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20193 #define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
AnnaBridge 172:65be27845400 20194 #define COMP_OR_AFOPK2_Pos (10U)
AnnaBridge 172:65be27845400 20195 #define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20196 #define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
AnnaBridge 172:65be27845400 20197
AnnaBridge 172:65be27845400 20198 /*!< ****************** Bit definition for COMP_CFGRx register ********************/
AnnaBridge 172:65be27845400 20199 #define COMP_CFGRx_EN_Pos (0U)
AnnaBridge 172:65be27845400 20200 #define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20201 #define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
AnnaBridge 172:65be27845400 20202 #define COMP_CFGRx_BRGEN_Pos (1U)
AnnaBridge 172:65be27845400 20203 #define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20204 #define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
AnnaBridge 172:65be27845400 20205 #define COMP_CFGRx_SCALEN_Pos (2U)
AnnaBridge 172:65be27845400 20206 #define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20207 #define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
AnnaBridge 172:65be27845400 20208 #define COMP_CFGRx_POLARITY_Pos (3U)
AnnaBridge 172:65be27845400 20209 #define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20210 #define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
AnnaBridge 172:65be27845400 20211 #define COMP_CFGRx_WINMODE_Pos (4U)
AnnaBridge 172:65be27845400 20212 #define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20213 #define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
AnnaBridge 172:65be27845400 20214 #define COMP_CFGRx_ITEN_Pos (6U)
AnnaBridge 172:65be27845400 20215 #define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20216 #define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
AnnaBridge 172:65be27845400 20217 #define COMP_CFGRx_HYST_Pos (8U)
AnnaBridge 172:65be27845400 20218 #define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 20219 #define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
AnnaBridge 172:65be27845400 20220 #define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20221 #define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20222 #define COMP_CFGRx_PWRMODE_Pos (12U)
AnnaBridge 172:65be27845400 20223 #define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 20224 #define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
AnnaBridge 172:65be27845400 20225 #define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 20226 #define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20227 #define COMP_CFGRx_INMSEL_Pos (16U)
AnnaBridge 172:65be27845400 20228 #define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 20229 #define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
AnnaBridge 172:65be27845400 20230 #define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 20231 #define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20232 #define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 20233 #define COMP_CFGRx_INPSEL_Pos (20U)
AnnaBridge 172:65be27845400 20234 #define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20235 #define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
AnnaBridge 172:65be27845400 20236 #define COMP_CFGRx_BLANKING_Pos (24U)
AnnaBridge 172:65be27845400 20237 #define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 20238 #define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
AnnaBridge 172:65be27845400 20239 #define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 20240 #define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 20241 #define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 20242 #define COMP_CFGRx_LOCK_Pos (31U)
AnnaBridge 172:65be27845400 20243 #define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 20244 #define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
AnnaBridge 172:65be27845400 20245
AnnaBridge 172:65be27845400 20246
AnnaBridge 172:65be27845400 20247 /******************************************************************************/
AnnaBridge 172:65be27845400 20248 /* */
AnnaBridge 172:65be27845400 20249 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 172:65be27845400 20250 /* */
AnnaBridge 172:65be27845400 20251 /******************************************************************************/
AnnaBridge 172:65be27845400 20252 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 172:65be27845400 20253 #define USART_CR1_UE_Pos (0U)
AnnaBridge 172:65be27845400 20254 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20255 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
AnnaBridge 172:65be27845400 20256 #define USART_CR1_UESM_Pos (1U)
AnnaBridge 172:65be27845400 20257 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20258 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
AnnaBridge 172:65be27845400 20259 #define USART_CR1_RE_Pos (2U)
AnnaBridge 172:65be27845400 20260 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20261 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
AnnaBridge 172:65be27845400 20262 #define USART_CR1_TE_Pos (3U)
AnnaBridge 172:65be27845400 20263 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20264 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
AnnaBridge 172:65be27845400 20265 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 172:65be27845400 20266 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20267 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
AnnaBridge 172:65be27845400 20268 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
AnnaBridge 172:65be27845400 20269 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20270 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
AnnaBridge 172:65be27845400 20271 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 172:65be27845400 20272 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20273 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
AnnaBridge 172:65be27845400 20274 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
AnnaBridge 172:65be27845400 20275 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20276 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
AnnaBridge 172:65be27845400 20277 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 172:65be27845400 20278 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20279 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 172:65be27845400 20280 #define USART_CR1_PS_Pos (9U)
AnnaBridge 172:65be27845400 20281 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20282 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
AnnaBridge 172:65be27845400 20283 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 172:65be27845400 20284 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20285 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
AnnaBridge 172:65be27845400 20286 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 172:65be27845400 20287 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20288 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
AnnaBridge 172:65be27845400 20289 #define USART_CR1_M_Pos (12U)
AnnaBridge 172:65be27845400 20290 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
AnnaBridge 172:65be27845400 20291 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
AnnaBridge 172:65be27845400 20292 #define USART_CR1_M0_Pos (12U)
AnnaBridge 172:65be27845400 20293 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 20294 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
AnnaBridge 172:65be27845400 20295 #define USART_CR1_MME_Pos (13U)
AnnaBridge 172:65be27845400 20296 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20297 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
AnnaBridge 172:65be27845400 20298 #define USART_CR1_CMIE_Pos (14U)
AnnaBridge 172:65be27845400 20299 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 20300 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
AnnaBridge 172:65be27845400 20301 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 172:65be27845400 20302 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 20303 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
AnnaBridge 172:65be27845400 20304 #define USART_CR1_DEDT_Pos (16U)
AnnaBridge 172:65be27845400 20305 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
AnnaBridge 172:65be27845400 20306 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
AnnaBridge 172:65be27845400 20307 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 20308 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20309 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 20310 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 20311 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20312 #define USART_CR1_DEAT_Pos (21U)
AnnaBridge 172:65be27845400 20313 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
AnnaBridge 172:65be27845400 20314 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
AnnaBridge 172:65be27845400 20315 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 20316 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 20317 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 20318 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 20319 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 20320 #define USART_CR1_RTOIE_Pos (26U)
AnnaBridge 172:65be27845400 20321 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 20322 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
AnnaBridge 172:65be27845400 20323 #define USART_CR1_EOBIE_Pos (27U)
AnnaBridge 172:65be27845400 20324 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 20325 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
AnnaBridge 172:65be27845400 20326 #define USART_CR1_M1_Pos (28U)
AnnaBridge 172:65be27845400 20327 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 20328 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
AnnaBridge 172:65be27845400 20329 #define USART_CR1_FIFOEN_Pos (29U)
AnnaBridge 172:65be27845400 20330 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 20331 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
AnnaBridge 172:65be27845400 20332 #define USART_CR1_TXFEIE_Pos (30U)
AnnaBridge 172:65be27845400 20333 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 20334 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
AnnaBridge 172:65be27845400 20335 #define USART_CR1_RXFFIE_Pos (31U)
AnnaBridge 172:65be27845400 20336 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 20337 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
AnnaBridge 172:65be27845400 20338
AnnaBridge 172:65be27845400 20339 /* Legacy define */
AnnaBridge 172:65be27845400 20340 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
AnnaBridge 172:65be27845400 20341 #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
AnnaBridge 172:65be27845400 20342
AnnaBridge 172:65be27845400 20343 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 172:65be27845400 20344 #define USART_CR2_SLVEN_Pos (0U)
AnnaBridge 172:65be27845400 20345 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20346 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
AnnaBridge 172:65be27845400 20347 #define USART_CR2_DIS_NSS_Pos (3U)
AnnaBridge 172:65be27845400 20348 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20349 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
AnnaBridge 172:65be27845400 20350 #define USART_CR2_ADDM7_Pos (4U)
AnnaBridge 172:65be27845400 20351 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20352 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
AnnaBridge 172:65be27845400 20353 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 172:65be27845400 20354 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20355 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
AnnaBridge 172:65be27845400 20356 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 172:65be27845400 20357 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20358 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 172:65be27845400 20359 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 172:65be27845400 20360 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20361 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
AnnaBridge 172:65be27845400 20362 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 172:65be27845400 20363 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20364 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
AnnaBridge 172:65be27845400 20365 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 172:65be27845400 20366 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20367 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 172:65be27845400 20368 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 172:65be27845400 20369 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20370 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
AnnaBridge 172:65be27845400 20371 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 172:65be27845400 20372 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 20373 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 172:65be27845400 20374 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 20375 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20376 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 172:65be27845400 20377 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 20378 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
AnnaBridge 172:65be27845400 20379 #define USART_CR2_SWAP_Pos (15U)
AnnaBridge 172:65be27845400 20380 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 20381 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
AnnaBridge 172:65be27845400 20382 #define USART_CR2_RXINV_Pos (16U)
AnnaBridge 172:65be27845400 20383 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 20384 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
AnnaBridge 172:65be27845400 20385 #define USART_CR2_TXINV_Pos (17U)
AnnaBridge 172:65be27845400 20386 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20387 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
AnnaBridge 172:65be27845400 20388 #define USART_CR2_DATAINV_Pos (18U)
AnnaBridge 172:65be27845400 20389 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 20390 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
AnnaBridge 172:65be27845400 20391 #define USART_CR2_MSBFIRST_Pos (19U)
AnnaBridge 172:65be27845400 20392 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 20393 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
AnnaBridge 172:65be27845400 20394 #define USART_CR2_ABREN_Pos (20U)
AnnaBridge 172:65be27845400 20395 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20396 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
AnnaBridge 172:65be27845400 20397 #define USART_CR2_ABRMODE_Pos (21U)
AnnaBridge 172:65be27845400 20398 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 20399 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
AnnaBridge 172:65be27845400 20400 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 20401 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 20402 #define USART_CR2_RTOEN_Pos (23U)
AnnaBridge 172:65be27845400 20403 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 20404 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
AnnaBridge 172:65be27845400 20405 #define USART_CR2_ADD_Pos (24U)
AnnaBridge 172:65be27845400 20406 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 20407 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
AnnaBridge 172:65be27845400 20408
AnnaBridge 172:65be27845400 20409 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 172:65be27845400 20410 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 172:65be27845400 20411 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20412 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 172:65be27845400 20413 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 172:65be27845400 20414 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20415 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
AnnaBridge 172:65be27845400 20416 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 172:65be27845400 20417 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20418 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
AnnaBridge 172:65be27845400 20419 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 172:65be27845400 20420 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20421 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
AnnaBridge 172:65be27845400 20422 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 172:65be27845400 20423 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20424 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
AnnaBridge 172:65be27845400 20425 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 172:65be27845400 20426 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20427 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
AnnaBridge 172:65be27845400 20428 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 172:65be27845400 20429 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20430 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
AnnaBridge 172:65be27845400 20431 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 172:65be27845400 20432 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20433 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
AnnaBridge 172:65be27845400 20434 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 172:65be27845400 20435 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20436 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
AnnaBridge 172:65be27845400 20437 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 172:65be27845400 20438 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20439 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
AnnaBridge 172:65be27845400 20440 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 172:65be27845400 20441 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20442 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
AnnaBridge 172:65be27845400 20443 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 172:65be27845400 20444 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20445 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
AnnaBridge 172:65be27845400 20446 #define USART_CR3_OVRDIS_Pos (12U)
AnnaBridge 172:65be27845400 20447 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 20448 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
AnnaBridge 172:65be27845400 20449 #define USART_CR3_DDRE_Pos (13U)
AnnaBridge 172:65be27845400 20450 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20451 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
AnnaBridge 172:65be27845400 20452 #define USART_CR3_DEM_Pos (14U)
AnnaBridge 172:65be27845400 20453 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 20454 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
AnnaBridge 172:65be27845400 20455 #define USART_CR3_DEP_Pos (15U)
AnnaBridge 172:65be27845400 20456 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 20457 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
AnnaBridge 172:65be27845400 20458 #define USART_CR3_SCARCNT_Pos (17U)
AnnaBridge 172:65be27845400 20459 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
AnnaBridge 172:65be27845400 20460 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
AnnaBridge 172:65be27845400 20461 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20462 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 20463 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 20464 #define USART_CR3_WUS_Pos (20U)
AnnaBridge 172:65be27845400 20465 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 20466 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
AnnaBridge 172:65be27845400 20467 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20468 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 20469 #define USART_CR3_WUFIE_Pos (22U)
AnnaBridge 172:65be27845400 20470 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 20471 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
AnnaBridge 172:65be27845400 20472 #define USART_CR3_TXFTIE_Pos (23U)
AnnaBridge 172:65be27845400 20473 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 20474 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
AnnaBridge 172:65be27845400 20475 #define USART_CR3_TCBGTIE_Pos (24U)
AnnaBridge 172:65be27845400 20476 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 20477 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
AnnaBridge 172:65be27845400 20478 #define USART_CR3_RXFTCFG_Pos (25U)
AnnaBridge 172:65be27845400 20479 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
AnnaBridge 172:65be27845400 20480 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
AnnaBridge 172:65be27845400 20481 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 20482 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 20483 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 20484 #define USART_CR3_RXFTIE_Pos (28U)
AnnaBridge 172:65be27845400 20485 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 20486 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
AnnaBridge 172:65be27845400 20487 #define USART_CR3_TXFTCFG_Pos (29U)
AnnaBridge 172:65be27845400 20488 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
AnnaBridge 172:65be27845400 20489 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
AnnaBridge 172:65be27845400 20490 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 20491 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 20492 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 20493
AnnaBridge 172:65be27845400 20494 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 172:65be27845400 20495 #define USART_BRR_DIV_FRACTION_Pos (0U)
AnnaBridge 172:65be27845400 20496 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 20497 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
AnnaBridge 172:65be27845400 20498 #define USART_BRR_DIV_MANTISSA_Pos (4U)
AnnaBridge 172:65be27845400 20499 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
AnnaBridge 172:65be27845400 20500 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
AnnaBridge 172:65be27845400 20501
AnnaBridge 172:65be27845400 20502 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 172:65be27845400 20503 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 172:65be27845400 20504 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 20505 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 172:65be27845400 20506 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 172:65be27845400 20507 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 172:65be27845400 20508 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
AnnaBridge 172:65be27845400 20509
AnnaBridge 172:65be27845400 20510 /******************* Bit definition for USART_RTOR register *****************/
AnnaBridge 172:65be27845400 20511 #define USART_RTOR_RTO_Pos (0U)
AnnaBridge 172:65be27845400 20512 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
AnnaBridge 172:65be27845400 20513 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
AnnaBridge 172:65be27845400 20514 #define USART_RTOR_BLEN_Pos (24U)
AnnaBridge 172:65be27845400 20515 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 20516 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
AnnaBridge 172:65be27845400 20517
AnnaBridge 172:65be27845400 20518 /******************* Bit definition for USART_RQR register ******************/
AnnaBridge 172:65be27845400 20519 #define USART_RQR_ABRRQ_Pos (0U)
AnnaBridge 172:65be27845400 20520 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20521 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
AnnaBridge 172:65be27845400 20522 #define USART_RQR_SBKRQ_Pos (1U)
AnnaBridge 172:65be27845400 20523 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20524 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
AnnaBridge 172:65be27845400 20525 #define USART_RQR_MMRQ_Pos (2U)
AnnaBridge 172:65be27845400 20526 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20527 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
AnnaBridge 172:65be27845400 20528 #define USART_RQR_RXFRQ_Pos (3U)
AnnaBridge 172:65be27845400 20529 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20530 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
AnnaBridge 172:65be27845400 20531 #define USART_RQR_TXFRQ_Pos (4U)
AnnaBridge 172:65be27845400 20532 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20533 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
AnnaBridge 172:65be27845400 20534
AnnaBridge 172:65be27845400 20535 /******************* Bit definition for USART_ISR register ******************/
AnnaBridge 172:65be27845400 20536 #define USART_ISR_PE_Pos (0U)
AnnaBridge 172:65be27845400 20537 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20538 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
AnnaBridge 172:65be27845400 20539 #define USART_ISR_FE_Pos (1U)
AnnaBridge 172:65be27845400 20540 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20541 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
AnnaBridge 172:65be27845400 20542 #define USART_ISR_NE_Pos (2U)
AnnaBridge 172:65be27845400 20543 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20544 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
AnnaBridge 172:65be27845400 20545 #define USART_ISR_ORE_Pos (3U)
AnnaBridge 172:65be27845400 20546 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20547 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
AnnaBridge 172:65be27845400 20548 #define USART_ISR_IDLE_Pos (4U)
AnnaBridge 172:65be27845400 20549 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20550 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
AnnaBridge 172:65be27845400 20551 #define USART_ISR_RXNE_RXFNE_Pos (5U)
AnnaBridge 172:65be27845400 20552 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20553 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
AnnaBridge 172:65be27845400 20554 #define USART_ISR_TC_Pos (6U)
AnnaBridge 172:65be27845400 20555 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20556 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
AnnaBridge 172:65be27845400 20557 #define USART_ISR_TXE_TXFNF_Pos (7U)
AnnaBridge 172:65be27845400 20558 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20559 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
AnnaBridge 172:65be27845400 20560 #define USART_ISR_LBDF_Pos (8U)
AnnaBridge 172:65be27845400 20561 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20562 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
AnnaBridge 172:65be27845400 20563 #define USART_ISR_CTSIF_Pos (9U)
AnnaBridge 172:65be27845400 20564 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20565 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
AnnaBridge 172:65be27845400 20566 #define USART_ISR_CTS_Pos (10U)
AnnaBridge 172:65be27845400 20567 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20568 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
AnnaBridge 172:65be27845400 20569 #define USART_ISR_RTOF_Pos (11U)
AnnaBridge 172:65be27845400 20570 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20571 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
AnnaBridge 172:65be27845400 20572 #define USART_ISR_EOBF_Pos (12U)
AnnaBridge 172:65be27845400 20573 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 20574 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
AnnaBridge 172:65be27845400 20575 #define USART_ISR_UDR_Pos (13U)
AnnaBridge 172:65be27845400 20576 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20577 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
AnnaBridge 172:65be27845400 20578 #define USART_ISR_ABRE_Pos (14U)
AnnaBridge 172:65be27845400 20579 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 20580 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
AnnaBridge 172:65be27845400 20581 #define USART_ISR_ABRF_Pos (15U)
AnnaBridge 172:65be27845400 20582 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 20583 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
AnnaBridge 172:65be27845400 20584 #define USART_ISR_BUSY_Pos (16U)
AnnaBridge 172:65be27845400 20585 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 20586 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
AnnaBridge 172:65be27845400 20587 #define USART_ISR_CMF_Pos (17U)
AnnaBridge 172:65be27845400 20588 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20589 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
AnnaBridge 172:65be27845400 20590 #define USART_ISR_SBKF_Pos (18U)
AnnaBridge 172:65be27845400 20591 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 20592 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
AnnaBridge 172:65be27845400 20593 #define USART_ISR_RWU_Pos (19U)
AnnaBridge 172:65be27845400 20594 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 20595 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
AnnaBridge 172:65be27845400 20596 #define USART_ISR_WUF_Pos (20U)
AnnaBridge 172:65be27845400 20597 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20598 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
AnnaBridge 172:65be27845400 20599 #define USART_ISR_TEACK_Pos (21U)
AnnaBridge 172:65be27845400 20600 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 20601 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
AnnaBridge 172:65be27845400 20602 #define USART_ISR_REACK_Pos (22U)
AnnaBridge 172:65be27845400 20603 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 20604 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
AnnaBridge 172:65be27845400 20605 #define USART_ISR_TXFE_Pos (23U)
AnnaBridge 172:65be27845400 20606 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 20607 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
AnnaBridge 172:65be27845400 20608 #define USART_ISR_RXFF_Pos (24U)
AnnaBridge 172:65be27845400 20609 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 20610 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
AnnaBridge 172:65be27845400 20611 #define USART_ISR_TCBGT_Pos (25U)
AnnaBridge 172:65be27845400 20612 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 20613 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
AnnaBridge 172:65be27845400 20614 #define USART_ISR_RXFT_Pos (26U)
AnnaBridge 172:65be27845400 20615 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 20616 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
AnnaBridge 172:65be27845400 20617 #define USART_ISR_TXFT_Pos (27U)
AnnaBridge 172:65be27845400 20618 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 20619 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
AnnaBridge 172:65be27845400 20620
AnnaBridge 172:65be27845400 20621 /******************* Bit definition for USART_ICR register ******************/
AnnaBridge 172:65be27845400 20622 #define USART_ICR_PECF_Pos (0U)
AnnaBridge 172:65be27845400 20623 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20624 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
AnnaBridge 172:65be27845400 20625 #define USART_ICR_FECF_Pos (1U)
AnnaBridge 172:65be27845400 20626 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20627 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
AnnaBridge 172:65be27845400 20628 #define USART_ICR_NECF_Pos (2U)
AnnaBridge 172:65be27845400 20629 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20630 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
AnnaBridge 172:65be27845400 20631 #define USART_ICR_ORECF_Pos (3U)
AnnaBridge 172:65be27845400 20632 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20633 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
AnnaBridge 172:65be27845400 20634 #define USART_ICR_IDLECF_Pos (4U)
AnnaBridge 172:65be27845400 20635 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20636 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
AnnaBridge 172:65be27845400 20637 #define USART_ICR_TXFECF_Pos (5U)
AnnaBridge 172:65be27845400 20638 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20639 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
AnnaBridge 172:65be27845400 20640 #define USART_ICR_TCCF_Pos (6U)
AnnaBridge 172:65be27845400 20641 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20642 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
AnnaBridge 172:65be27845400 20643 #define USART_ICR_TCBGTCF_Pos (7U)
AnnaBridge 172:65be27845400 20644 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20645 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */
AnnaBridge 172:65be27845400 20646 #define USART_ICR_LBDCF_Pos (8U)
AnnaBridge 172:65be27845400 20647 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20648 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
AnnaBridge 172:65be27845400 20649 #define USART_ICR_CTSCF_Pos (9U)
AnnaBridge 172:65be27845400 20650 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20651 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
AnnaBridge 172:65be27845400 20652 #define USART_ICR_RTOCF_Pos (11U)
AnnaBridge 172:65be27845400 20653 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20654 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
AnnaBridge 172:65be27845400 20655 #define USART_ICR_EOBCF_Pos (12U)
AnnaBridge 172:65be27845400 20656 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 20657 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
AnnaBridge 172:65be27845400 20658 #define USART_ICR_UDRCF_Pos (13U)
AnnaBridge 172:65be27845400 20659 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20660 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
AnnaBridge 172:65be27845400 20661 #define USART_ICR_CMCF_Pos (17U)
AnnaBridge 172:65be27845400 20662 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20663 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
AnnaBridge 172:65be27845400 20664 #define USART_ICR_WUCF_Pos (20U)
AnnaBridge 172:65be27845400 20665 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20666 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
AnnaBridge 172:65be27845400 20667
AnnaBridge 172:65be27845400 20668 /******************* Bit definition for USART_RDR register ******************/
AnnaBridge 172:65be27845400 20669 #define USART_RDR_RDR_Pos (0U)
AnnaBridge 172:65be27845400 20670 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 20671 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
AnnaBridge 172:65be27845400 20672
AnnaBridge 172:65be27845400 20673 /******************* Bit definition for USART_TDR register ******************/
AnnaBridge 172:65be27845400 20674 #define USART_TDR_TDR_Pos (0U)
AnnaBridge 172:65be27845400 20675 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 20676 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
AnnaBridge 172:65be27845400 20677
AnnaBridge 172:65be27845400 20678 /******************* Bit definition for USART_PRESC register ******************/
AnnaBridge 172:65be27845400 20679 #define USART_PRESC_PRESCALER_Pos (0U)
AnnaBridge 172:65be27845400 20680 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 20681 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
AnnaBridge 172:65be27845400 20682 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20683 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20684 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20685 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20686
AnnaBridge 172:65be27845400 20687 /******************************************************************************/
AnnaBridge 172:65be27845400 20688 /* */
AnnaBridge 172:65be27845400 20689 /* Single Wire Protocol Master Interface (SWPMI) */
AnnaBridge 172:65be27845400 20690 /* */
AnnaBridge 172:65be27845400 20691 /******************************************************************************/
AnnaBridge 172:65be27845400 20692
AnnaBridge 172:65be27845400 20693 /******************* Bit definition for SWPMI_CR register ********************/
AnnaBridge 172:65be27845400 20694 #define SWPMI_CR_RXDMA_Pos (0U)
AnnaBridge 172:65be27845400 20695 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20696 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
AnnaBridge 172:65be27845400 20697 #define SWPMI_CR_TXDMA_Pos (1U)
AnnaBridge 172:65be27845400 20698 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20699 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
AnnaBridge 172:65be27845400 20700 #define SWPMI_CR_RXMODE_Pos (2U)
AnnaBridge 172:65be27845400 20701 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20702 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
AnnaBridge 172:65be27845400 20703 #define SWPMI_CR_TXMODE_Pos (3U)
AnnaBridge 172:65be27845400 20704 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20705 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
AnnaBridge 172:65be27845400 20706 #define SWPMI_CR_LPBK_Pos (4U)
AnnaBridge 172:65be27845400 20707 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20708 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
AnnaBridge 172:65be27845400 20709 #define SWPMI_CR_SWPACT_Pos (5U)
AnnaBridge 172:65be27845400 20710 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20711 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
AnnaBridge 172:65be27845400 20712 #define SWPMI_CR_DEACT_Pos (10U)
AnnaBridge 172:65be27845400 20713 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20714 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
AnnaBridge 172:65be27845400 20715 #define SWPMI_CR_SWPEN_Pos (11U)
AnnaBridge 172:65be27845400 20716 #define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20717 #define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */
AnnaBridge 172:65be27845400 20718
AnnaBridge 172:65be27845400 20719 /******************* Bit definition for SWPMI_BRR register ********************/
AnnaBridge 172:65be27845400 20720 #define SWPMI_BRR_BR_Pos (0U)
AnnaBridge 172:65be27845400 20721 #define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 20722 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */
AnnaBridge 172:65be27845400 20723
AnnaBridge 172:65be27845400 20724 /******************* Bit definition for SWPMI_ISR register ********************/
AnnaBridge 172:65be27845400 20725 #define SWPMI_ISR_RXBFF_Pos (0U)
AnnaBridge 172:65be27845400 20726 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20727 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
AnnaBridge 172:65be27845400 20728 #define SWPMI_ISR_TXBEF_Pos (1U)
AnnaBridge 172:65be27845400 20729 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20730 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
AnnaBridge 172:65be27845400 20731 #define SWPMI_ISR_RXBERF_Pos (2U)
AnnaBridge 172:65be27845400 20732 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20733 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
AnnaBridge 172:65be27845400 20734 #define SWPMI_ISR_RXOVRF_Pos (3U)
AnnaBridge 172:65be27845400 20735 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20736 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
AnnaBridge 172:65be27845400 20737 #define SWPMI_ISR_TXUNRF_Pos (4U)
AnnaBridge 172:65be27845400 20738 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20739 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
AnnaBridge 172:65be27845400 20740 #define SWPMI_ISR_RXNE_Pos (5U)
AnnaBridge 172:65be27845400 20741 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20742 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
AnnaBridge 172:65be27845400 20743 #define SWPMI_ISR_TXE_Pos (6U)
AnnaBridge 172:65be27845400 20744 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20745 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
AnnaBridge 172:65be27845400 20746 #define SWPMI_ISR_TCF_Pos (7U)
AnnaBridge 172:65be27845400 20747 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20748 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
AnnaBridge 172:65be27845400 20749 #define SWPMI_ISR_SRF_Pos (8U)
AnnaBridge 172:65be27845400 20750 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20751 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
AnnaBridge 172:65be27845400 20752 #define SWPMI_ISR_SUSP_Pos (9U)
AnnaBridge 172:65be27845400 20753 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20754 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
AnnaBridge 172:65be27845400 20755 #define SWPMI_ISR_DEACTF_Pos (10U)
AnnaBridge 172:65be27845400 20756 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 20757 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
AnnaBridge 172:65be27845400 20758 #define SWPMI_ISR_RDYF_Pos (11U)
AnnaBridge 172:65be27845400 20759 #define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20760 #define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */
AnnaBridge 172:65be27845400 20761
AnnaBridge 172:65be27845400 20762 /******************* Bit definition for SWPMI_ICR register ********************/
AnnaBridge 172:65be27845400 20763 #define SWPMI_ICR_CRXBFF_Pos (0U)
AnnaBridge 172:65be27845400 20764 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20765 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
AnnaBridge 172:65be27845400 20766 #define SWPMI_ICR_CTXBEF_Pos (1U)
AnnaBridge 172:65be27845400 20767 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20768 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
AnnaBridge 172:65be27845400 20769 #define SWPMI_ICR_CRXBERF_Pos (2U)
AnnaBridge 172:65be27845400 20770 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20771 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
AnnaBridge 172:65be27845400 20772 #define SWPMI_ICR_CRXOVRF_Pos (3U)
AnnaBridge 172:65be27845400 20773 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20774 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
AnnaBridge 172:65be27845400 20775 #define SWPMI_ICR_CTXUNRF_Pos (4U)
AnnaBridge 172:65be27845400 20776 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20777 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
AnnaBridge 172:65be27845400 20778 #define SWPMI_ICR_CTCF_Pos (7U)
AnnaBridge 172:65be27845400 20779 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20780 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
AnnaBridge 172:65be27845400 20781 #define SWPMI_ICR_CSRF_Pos (8U)
AnnaBridge 172:65be27845400 20782 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20783 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
AnnaBridge 172:65be27845400 20784 #define SWPMI_ICR_CRDYF_Pos (11U)
AnnaBridge 172:65be27845400 20785 #define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20786 #define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */
AnnaBridge 172:65be27845400 20787
AnnaBridge 172:65be27845400 20788 /******************* Bit definition for SWPMI_IER register ********************/
AnnaBridge 172:65be27845400 20789 #define SWPMI_IER_RXBFIE_Pos (0U)
AnnaBridge 172:65be27845400 20790 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20791 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
AnnaBridge 172:65be27845400 20792 #define SWPMI_IER_TXBEIE_Pos (1U)
AnnaBridge 172:65be27845400 20793 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20794 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
AnnaBridge 172:65be27845400 20795 #define SWPMI_IER_RXBERIE_Pos (2U)
AnnaBridge 172:65be27845400 20796 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20797 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
AnnaBridge 172:65be27845400 20798 #define SWPMI_IER_RXOVRIE_Pos (3U)
AnnaBridge 172:65be27845400 20799 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20800 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
AnnaBridge 172:65be27845400 20801 #define SWPMI_IER_TXUNRIE_Pos (4U)
AnnaBridge 172:65be27845400 20802 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20803 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
AnnaBridge 172:65be27845400 20804 #define SWPMI_IER_RIE_Pos (5U)
AnnaBridge 172:65be27845400 20805 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20806 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
AnnaBridge 172:65be27845400 20807 #define SWPMI_IER_TIE_Pos (6U)
AnnaBridge 172:65be27845400 20808 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20809 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
AnnaBridge 172:65be27845400 20810 #define SWPMI_IER_TCIE_Pos (7U)
AnnaBridge 172:65be27845400 20811 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20812 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
AnnaBridge 172:65be27845400 20813 #define SWPMI_IER_SRIE_Pos (8U)
AnnaBridge 172:65be27845400 20814 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20815 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
AnnaBridge 172:65be27845400 20816 #define SWPMI_IER_RDYIE_Pos (11U)
AnnaBridge 172:65be27845400 20817 #define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20818 #define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */
AnnaBridge 172:65be27845400 20819
AnnaBridge 172:65be27845400 20820 /******************* Bit definition for SWPMI_RFL register ********************/
AnnaBridge 172:65be27845400 20821 #define SWPMI_RFL_RFL_Pos (0U)
AnnaBridge 172:65be27845400 20822 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
AnnaBridge 172:65be27845400 20823 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
AnnaBridge 172:65be27845400 20824 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
AnnaBridge 172:65be27845400 20825
AnnaBridge 172:65be27845400 20826 /******************* Bit definition for SWPMI_TDR register ********************/
AnnaBridge 172:65be27845400 20827 #define SWPMI_TDR_TD_Pos (0U)
AnnaBridge 172:65be27845400 20828 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 20829 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
AnnaBridge 172:65be27845400 20830
AnnaBridge 172:65be27845400 20831 /******************* Bit definition for SWPMI_RDR register ********************/
AnnaBridge 172:65be27845400 20832 #define SWPMI_RDR_RD_Pos (0U)
AnnaBridge 172:65be27845400 20833 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 20834 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
AnnaBridge 172:65be27845400 20835
AnnaBridge 172:65be27845400 20836
AnnaBridge 172:65be27845400 20837 /******************* Bit definition for SWPMI_OR register ********************/
AnnaBridge 172:65be27845400 20838 #define SWPMI_OR_TBYP_Pos (0U)
AnnaBridge 172:65be27845400 20839 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20840 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
AnnaBridge 172:65be27845400 20841 #define SWPMI_OR_CLASS_Pos (1U)
AnnaBridge 172:65be27845400 20842 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20843 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */
AnnaBridge 172:65be27845400 20844
AnnaBridge 172:65be27845400 20845 /******************************************************************************/
AnnaBridge 172:65be27845400 20846 /* */
AnnaBridge 172:65be27845400 20847 /* Window WATCHDOG */
AnnaBridge 172:65be27845400 20848 /* */
AnnaBridge 172:65be27845400 20849 /******************************************************************************/
AnnaBridge 172:65be27845400 20850 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 172:65be27845400 20851 #define WWDG_CR_T_Pos (0U)
AnnaBridge 172:65be27845400 20852 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 20853 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 172:65be27845400 20854 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20855 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20856 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20857 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20858 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20859 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20860 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20861
AnnaBridge 172:65be27845400 20862 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 172:65be27845400 20863 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20864 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
AnnaBridge 172:65be27845400 20865
AnnaBridge 172:65be27845400 20866 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 172:65be27845400 20867 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 172:65be27845400 20868 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 20869 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 172:65be27845400 20870 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20871 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20872 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20873 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20874 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20875 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20876 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20877
AnnaBridge 172:65be27845400 20878 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 172:65be27845400 20879 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20880 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
AnnaBridge 172:65be27845400 20881
AnnaBridge 172:65be27845400 20882 #define WWDG_CFR_WDGTB_Pos (11U)
AnnaBridge 172:65be27845400 20883 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
AnnaBridge 172:65be27845400 20884 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
AnnaBridge 172:65be27845400 20885 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 20886 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 20887 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 20888
AnnaBridge 172:65be27845400 20889 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 172:65be27845400 20890 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 172:65be27845400 20891 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20892 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
AnnaBridge 172:65be27845400 20893
AnnaBridge 172:65be27845400 20894
AnnaBridge 172:65be27845400 20895 /******************************************************************************/
AnnaBridge 172:65be27845400 20896 /* */
AnnaBridge 172:65be27845400 20897 /* DBG */
AnnaBridge 172:65be27845400 20898 /* */
AnnaBridge 172:65be27845400 20899 /******************************************************************************/
AnnaBridge 172:65be27845400 20900
AnnaBridge 172:65be27845400 20901 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 172:65be27845400 20902 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 172:65be27845400 20903 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 20904 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 172:65be27845400 20905 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 172:65be27845400 20906 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 20907 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
AnnaBridge 172:65be27845400 20908
AnnaBridge 172:65be27845400 20909 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 172:65be27845400 20910 #define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
AnnaBridge 172:65be27845400 20911 #define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20912 #define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
AnnaBridge 172:65be27845400 20913 #define DBGMCU_CR_DBG_STOPD1_Pos (1U)
AnnaBridge 172:65be27845400 20914 #define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20915 #define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
AnnaBridge 172:65be27845400 20916 #define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
AnnaBridge 172:65be27845400 20917 #define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20918 #define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
AnnaBridge 172:65be27845400 20919 #define DBGMCU_CR_DBG_STOPD3_Pos (7U)
AnnaBridge 172:65be27845400 20920 #define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20921 #define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
AnnaBridge 172:65be27845400 20922 #define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
AnnaBridge 172:65be27845400 20923 #define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20924 #define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
AnnaBridge 172:65be27845400 20925 #define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
AnnaBridge 172:65be27845400 20926 #define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 20927 #define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
AnnaBridge 172:65be27845400 20928 #define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
AnnaBridge 172:65be27845400 20929 #define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 20930 #define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
AnnaBridge 172:65be27845400 20931 #define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
AnnaBridge 172:65be27845400 20932 #define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 20933 #define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
AnnaBridge 172:65be27845400 20934 #define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
AnnaBridge 172:65be27845400 20935 #define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 20936 #define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
AnnaBridge 172:65be27845400 20937
AnnaBridge 172:65be27845400 20938 /******************** Bit definition for APB3FZ1 register ************/
AnnaBridge 172:65be27845400 20939 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
AnnaBridge 172:65be27845400 20940 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20941 #define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
AnnaBridge 172:65be27845400 20942 /******************** Bit definition for APB1LFZ1 register ************/
AnnaBridge 172:65be27845400 20943 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
AnnaBridge 172:65be27845400 20944 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20945 #define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
AnnaBridge 172:65be27845400 20946 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
AnnaBridge 172:65be27845400 20947 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20948 #define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
AnnaBridge 172:65be27845400 20949 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
AnnaBridge 172:65be27845400 20950 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 20951 #define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
AnnaBridge 172:65be27845400 20952 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
AnnaBridge 172:65be27845400 20953 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 20954 #define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
AnnaBridge 172:65be27845400 20955 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
AnnaBridge 172:65be27845400 20956 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 20957 #define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
AnnaBridge 172:65be27845400 20958 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
AnnaBridge 172:65be27845400 20959 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 20960 #define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
AnnaBridge 172:65be27845400 20961 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
AnnaBridge 172:65be27845400 20962 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 20963 #define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
AnnaBridge 172:65be27845400 20964 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
AnnaBridge 172:65be27845400 20965 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 20966 #define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
AnnaBridge 172:65be27845400 20967 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
AnnaBridge 172:65be27845400 20968 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20969 #define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
AnnaBridge 172:65be27845400 20970 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
AnnaBridge 172:65be27845400 20971 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 20972 #define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
AnnaBridge 172:65be27845400 20973 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
AnnaBridge 172:65be27845400 20974 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 20975 #define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
AnnaBridge 172:65be27845400 20976 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
AnnaBridge 172:65be27845400 20977 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 20978 #define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
AnnaBridge 172:65be27845400 20979 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
AnnaBridge 172:65be27845400 20980 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 20981 #define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
AnnaBridge 172:65be27845400 20982
AnnaBridge 172:65be27845400 20983 /******************** Bit definition for APB1HFZ1 register ************/
AnnaBridge 172:65be27845400 20984 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
AnnaBridge 172:65be27845400 20985 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 20986 #define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
AnnaBridge 172:65be27845400 20987 /******************** Bit definition for APB2FZ1 register ************/
AnnaBridge 172:65be27845400 20988 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
AnnaBridge 172:65be27845400 20989 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 20990 #define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
AnnaBridge 172:65be27845400 20991 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
AnnaBridge 172:65be27845400 20992 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 20993 #define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
AnnaBridge 172:65be27845400 20994 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
AnnaBridge 172:65be27845400 20995 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 20996 #define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
AnnaBridge 172:65be27845400 20997 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
AnnaBridge 172:65be27845400 20998 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 20999 #define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
AnnaBridge 172:65be27845400 21000 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
AnnaBridge 172:65be27845400 21001 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21002 #define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
AnnaBridge 172:65be27845400 21003 #define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
AnnaBridge 172:65be27845400 21004 #define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 21005 #define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
AnnaBridge 172:65be27845400 21006
AnnaBridge 172:65be27845400 21007 /******************** Bit definition for APB4FZ1 register ************/
AnnaBridge 172:65be27845400 21008 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
AnnaBridge 172:65be27845400 21009 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21010 #define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
AnnaBridge 172:65be27845400 21011 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
AnnaBridge 172:65be27845400 21012 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21013 #define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
AnnaBridge 172:65be27845400 21014 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
AnnaBridge 172:65be27845400 21015 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21016 #define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
AnnaBridge 172:65be27845400 21017 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
AnnaBridge 172:65be27845400 21018 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21019 #define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
AnnaBridge 172:65be27845400 21020 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
AnnaBridge 172:65be27845400 21021 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21022 #define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
AnnaBridge 172:65be27845400 21023 #define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
AnnaBridge 172:65be27845400 21024 #define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21025 #define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
AnnaBridge 172:65be27845400 21026 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
AnnaBridge 172:65be27845400 21027 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21028 #define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
AnnaBridge 172:65be27845400 21029 /******************************************************************************/
AnnaBridge 172:65be27845400 21030 /* */
AnnaBridge 172:65be27845400 21031 /* High Resolution Timer (HRTIM) */
AnnaBridge 172:65be27845400 21032 /* */
AnnaBridge 172:65be27845400 21033 /******************************************************************************/
AnnaBridge 172:65be27845400 21034 /******************** Master Timer control register ***************************/
AnnaBridge 172:65be27845400 21035 #define HRTIM_MCR_CK_PSC_Pos (0U)
AnnaBridge 172:65be27845400 21036 #define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 21037 #define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
AnnaBridge 172:65be27845400 21038 #define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21039 #define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21040 #define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21041
AnnaBridge 172:65be27845400 21042 #define HRTIM_MCR_CONT_Pos (3U)
AnnaBridge 172:65be27845400 21043 #define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21044 #define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
AnnaBridge 172:65be27845400 21045 #define HRTIM_MCR_RETRIG_Pos (4U)
AnnaBridge 172:65be27845400 21046 #define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21047 #define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
AnnaBridge 172:65be27845400 21048 #define HRTIM_MCR_HALF_Pos (5U)
AnnaBridge 172:65be27845400 21049 #define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21050 #define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
AnnaBridge 172:65be27845400 21051
AnnaBridge 172:65be27845400 21052 #define HRTIM_MCR_SYNC_IN_Pos (8U)
AnnaBridge 172:65be27845400 21053 #define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
AnnaBridge 172:65be27845400 21054 #define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
AnnaBridge 172:65be27845400 21055 #define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21056 #define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21057 #define HRTIM_MCR_SYNCRSTM_Pos (10U)
AnnaBridge 172:65be27845400 21058 #define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21059 #define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
AnnaBridge 172:65be27845400 21060 #define HRTIM_MCR_SYNCSTRTM_Pos (11U)
AnnaBridge 172:65be27845400 21061 #define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21062 #define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
AnnaBridge 172:65be27845400 21063 #define HRTIM_MCR_SYNC_OUT_Pos (12U)
AnnaBridge 172:65be27845400 21064 #define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 21065 #define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
AnnaBridge 172:65be27845400 21066 #define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21067 #define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21068 #define HRTIM_MCR_SYNC_SRC_Pos (14U)
AnnaBridge 172:65be27845400 21069 #define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 21070 #define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
AnnaBridge 172:65be27845400 21071 #define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21072 #define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 21073
AnnaBridge 172:65be27845400 21074 #define HRTIM_MCR_MCEN_Pos (16U)
AnnaBridge 172:65be27845400 21075 #define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21076 #define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
AnnaBridge 172:65be27845400 21077 #define HRTIM_MCR_TACEN_Pos (17U)
AnnaBridge 172:65be27845400 21078 #define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21079 #define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
AnnaBridge 172:65be27845400 21080 #define HRTIM_MCR_TBCEN_Pos (18U)
AnnaBridge 172:65be27845400 21081 #define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21082 #define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
AnnaBridge 172:65be27845400 21083 #define HRTIM_MCR_TCCEN_Pos (19U)
AnnaBridge 172:65be27845400 21084 #define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21085 #define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
AnnaBridge 172:65be27845400 21086 #define HRTIM_MCR_TDCEN_Pos (20U)
AnnaBridge 172:65be27845400 21087 #define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21088 #define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
AnnaBridge 172:65be27845400 21089 #define HRTIM_MCR_TECEN_Pos (21U)
AnnaBridge 172:65be27845400 21090 #define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21091 #define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
AnnaBridge 172:65be27845400 21092
AnnaBridge 172:65be27845400 21093 #define HRTIM_MCR_DACSYNC_Pos (25U)
AnnaBridge 172:65be27845400 21094 #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
AnnaBridge 172:65be27845400 21095 #define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
AnnaBridge 172:65be27845400 21096 #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 21097 #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 21098
AnnaBridge 172:65be27845400 21099 #define HRTIM_MCR_PREEN_Pos (27U)
AnnaBridge 172:65be27845400 21100 #define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 21101 #define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
AnnaBridge 172:65be27845400 21102 #define HRTIM_MCR_MREPU_Pos (29U)
AnnaBridge 172:65be27845400 21103 #define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 21104 #define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
AnnaBridge 172:65be27845400 21105
AnnaBridge 172:65be27845400 21106 #define HRTIM_MCR_BRSTDMA_Pos (30U)
AnnaBridge 172:65be27845400 21107 #define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 21108 #define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
AnnaBridge 172:65be27845400 21109 #define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 21110 #define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 21111
AnnaBridge 172:65be27845400 21112 /******************** Master Timer Interrupt status register ******************/
AnnaBridge 172:65be27845400 21113 #define HRTIM_MISR_MCMP1_Pos (0U)
AnnaBridge 172:65be27845400 21114 #define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21115 #define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
AnnaBridge 172:65be27845400 21116 #define HRTIM_MISR_MCMP2_Pos (1U)
AnnaBridge 172:65be27845400 21117 #define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21118 #define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
AnnaBridge 172:65be27845400 21119 #define HRTIM_MISR_MCMP3_Pos (2U)
AnnaBridge 172:65be27845400 21120 #define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21121 #define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
AnnaBridge 172:65be27845400 21122 #define HRTIM_MISR_MCMP4_Pos (3U)
AnnaBridge 172:65be27845400 21123 #define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21124 #define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
AnnaBridge 172:65be27845400 21125 #define HRTIM_MISR_MREP_Pos (4U)
AnnaBridge 172:65be27845400 21126 #define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21127 #define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
AnnaBridge 172:65be27845400 21128 #define HRTIM_MISR_SYNC_Pos (5U)
AnnaBridge 172:65be27845400 21129 #define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21130 #define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
AnnaBridge 172:65be27845400 21131 #define HRTIM_MISR_MUPD_Pos (6U)
AnnaBridge 172:65be27845400 21132 #define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21133 #define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
AnnaBridge 172:65be27845400 21134
AnnaBridge 172:65be27845400 21135 /******************** Master Timer Interrupt clear register *******************/
AnnaBridge 172:65be27845400 21136 #define HRTIM_MICR_MCMP1_Pos (0U)
AnnaBridge 172:65be27845400 21137 #define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21138 #define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
AnnaBridge 172:65be27845400 21139 #define HRTIM_MICR_MCMP2_Pos (1U)
AnnaBridge 172:65be27845400 21140 #define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21141 #define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
AnnaBridge 172:65be27845400 21142 #define HRTIM_MICR_MCMP3_Pos (2U)
AnnaBridge 172:65be27845400 21143 #define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21144 #define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
AnnaBridge 172:65be27845400 21145 #define HRTIM_MICR_MCMP4_Pos (3U)
AnnaBridge 172:65be27845400 21146 #define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21147 #define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
AnnaBridge 172:65be27845400 21148 #define HRTIM_MICR_MREP_Pos (4U)
AnnaBridge 172:65be27845400 21149 #define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21150 #define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
AnnaBridge 172:65be27845400 21151 #define HRTIM_MICR_SYNC_Pos (5U)
AnnaBridge 172:65be27845400 21152 #define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21153 #define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
AnnaBridge 172:65be27845400 21154 #define HRTIM_MICR_MUPD_Pos (6U)
AnnaBridge 172:65be27845400 21155 #define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21156 #define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
AnnaBridge 172:65be27845400 21157
AnnaBridge 172:65be27845400 21158 /******************** Master Timer DMA/Interrupt enable register **************/
AnnaBridge 172:65be27845400 21159 #define HRTIM_MDIER_MCMP1IE_Pos (0U)
AnnaBridge 172:65be27845400 21160 #define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21161 #define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
AnnaBridge 172:65be27845400 21162 #define HRTIM_MDIER_MCMP2IE_Pos (1U)
AnnaBridge 172:65be27845400 21163 #define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21164 #define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
AnnaBridge 172:65be27845400 21165 #define HRTIM_MDIER_MCMP3IE_Pos (2U)
AnnaBridge 172:65be27845400 21166 #define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21167 #define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
AnnaBridge 172:65be27845400 21168 #define HRTIM_MDIER_MCMP4IE_Pos (3U)
AnnaBridge 172:65be27845400 21169 #define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21170 #define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
AnnaBridge 172:65be27845400 21171 #define HRTIM_MDIER_MREPIE_Pos (4U)
AnnaBridge 172:65be27845400 21172 #define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21173 #define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
AnnaBridge 172:65be27845400 21174 #define HRTIM_MDIER_SYNCIE_Pos (5U)
AnnaBridge 172:65be27845400 21175 #define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21176 #define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
AnnaBridge 172:65be27845400 21177 #define HRTIM_MDIER_MUPDIE_Pos (6U)
AnnaBridge 172:65be27845400 21178 #define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21179 #define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
AnnaBridge 172:65be27845400 21180
AnnaBridge 172:65be27845400 21181 #define HRTIM_MDIER_MCMP1DE_Pos (16U)
AnnaBridge 172:65be27845400 21182 #define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21183 #define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
AnnaBridge 172:65be27845400 21184 #define HRTIM_MDIER_MCMP2DE_Pos (17U)
AnnaBridge 172:65be27845400 21185 #define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21186 #define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
AnnaBridge 172:65be27845400 21187 #define HRTIM_MDIER_MCMP3DE_Pos (18U)
AnnaBridge 172:65be27845400 21188 #define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21189 #define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
AnnaBridge 172:65be27845400 21190 #define HRTIM_MDIER_MCMP4DE_Pos (19U)
AnnaBridge 172:65be27845400 21191 #define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21192 #define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
AnnaBridge 172:65be27845400 21193 #define HRTIM_MDIER_MREPDE_Pos (20U)
AnnaBridge 172:65be27845400 21194 #define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21195 #define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
AnnaBridge 172:65be27845400 21196 #define HRTIM_MDIER_SYNCDE_Pos (21U)
AnnaBridge 172:65be27845400 21197 #define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21198 #define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
AnnaBridge 172:65be27845400 21199 #define HRTIM_MDIER_MUPDDE_Pos (22U)
AnnaBridge 172:65be27845400 21200 #define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21201 #define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
AnnaBridge 172:65be27845400 21202
AnnaBridge 172:65be27845400 21203 /******************* Bit definition for HRTIM_MCNTR register ****************/
AnnaBridge 172:65be27845400 21204 #define HRTIM_MCNTR_MCNTR_Pos (0U)
AnnaBridge 172:65be27845400 21205 #define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21206 #define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
AnnaBridge 172:65be27845400 21207
AnnaBridge 172:65be27845400 21208 /******************* Bit definition for HRTIM_MPER register *****************/
AnnaBridge 172:65be27845400 21209 #define HRTIM_MPER_MPER_Pos (0U)
AnnaBridge 172:65be27845400 21210 #define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21211 #define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
AnnaBridge 172:65be27845400 21212
AnnaBridge 172:65be27845400 21213 /******************* Bit definition for HRTIM_MREP register *****************/
AnnaBridge 172:65be27845400 21214 #define HRTIM_MREP_MREP_Pos (0U)
AnnaBridge 172:65be27845400 21215 #define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 21216 #define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
AnnaBridge 172:65be27845400 21217
AnnaBridge 172:65be27845400 21218 /******************* Bit definition for HRTIM_MCMP1R register *****************/
AnnaBridge 172:65be27845400 21219 #define HRTIM_MCMP1R_MCMP1R_Pos (0U)
AnnaBridge 172:65be27845400 21220 #define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21221 #define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
AnnaBridge 172:65be27845400 21222
AnnaBridge 172:65be27845400 21223 /******************* Bit definition for HRTIM_MCMP2R register *****************/
AnnaBridge 172:65be27845400 21224 #define HRTIM_MCMP1R_MCMP2R_Pos (0U)
AnnaBridge 172:65be27845400 21225 #define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21226 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk /*!<Compare Value */
AnnaBridge 172:65be27845400 21227
AnnaBridge 172:65be27845400 21228 /******************* Bit definition for HRTIM_MCMP3R register *****************/
AnnaBridge 172:65be27845400 21229 #define HRTIM_MCMP1R_MCMP3R_Pos (0U)
AnnaBridge 172:65be27845400 21230 #define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21231 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk /*!<Compare Value */
AnnaBridge 172:65be27845400 21232
AnnaBridge 172:65be27845400 21233 /******************* Bit definition for HRTIM_MCMP4R register *****************/
AnnaBridge 172:65be27845400 21234 #define HRTIM_MCMP1R_MCMP4R_Pos (0U)
AnnaBridge 172:65be27845400 21235 #define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21236 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk /*!<Compare Value */
AnnaBridge 172:65be27845400 21237
AnnaBridge 172:65be27845400 21238 /******************** Slave control register **********************************/
AnnaBridge 172:65be27845400 21239 #define HRTIM_TIMCR_CK_PSC_Pos (0U)
AnnaBridge 172:65be27845400 21240 #define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 21241 #define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
AnnaBridge 172:65be27845400 21242 #define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21243 #define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21244 #define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21245
AnnaBridge 172:65be27845400 21246 #define HRTIM_TIMCR_CONT_Pos (3U)
AnnaBridge 172:65be27845400 21247 #define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21248 #define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
AnnaBridge 172:65be27845400 21249 #define HRTIM_TIMCR_RETRIG_Pos (4U)
AnnaBridge 172:65be27845400 21250 #define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21251 #define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
AnnaBridge 172:65be27845400 21252 #define HRTIM_TIMCR_HALF_Pos (5U)
AnnaBridge 172:65be27845400 21253 #define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21254 #define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
AnnaBridge 172:65be27845400 21255 #define HRTIM_TIMCR_PSHPLL_Pos (6U)
AnnaBridge 172:65be27845400 21256 #define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21257 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
AnnaBridge 172:65be27845400 21258
AnnaBridge 172:65be27845400 21259 #define HRTIM_TIMCR_SYNCRST_Pos (10U)
AnnaBridge 172:65be27845400 21260 #define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21261 #define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
AnnaBridge 172:65be27845400 21262 #define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
AnnaBridge 172:65be27845400 21263 #define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21264 #define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
AnnaBridge 172:65be27845400 21265
AnnaBridge 172:65be27845400 21266 #define HRTIM_TIMCR_DELCMP2_Pos (12U)
AnnaBridge 172:65be27845400 21267 #define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 21268 #define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
AnnaBridge 172:65be27845400 21269 #define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21270 #define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21271 #define HRTIM_TIMCR_DELCMP4_Pos (14U)
AnnaBridge 172:65be27845400 21272 #define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 21273 #define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
AnnaBridge 172:65be27845400 21274 #define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21275 #define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 21276
AnnaBridge 172:65be27845400 21277 #define HRTIM_TIMCR_TREPU_Pos (17U)
AnnaBridge 172:65be27845400 21278 #define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21279 #define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
AnnaBridge 172:65be27845400 21280 #define HRTIM_TIMCR_TRSTU_Pos (18U)
AnnaBridge 172:65be27845400 21281 #define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21282 #define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
AnnaBridge 172:65be27845400 21283 #define HRTIM_TIMCR_TAU_Pos (19U)
AnnaBridge 172:65be27845400 21284 #define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21285 #define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
AnnaBridge 172:65be27845400 21286 #define HRTIM_TIMCR_TBU_Pos (20U)
AnnaBridge 172:65be27845400 21287 #define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21288 #define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
AnnaBridge 172:65be27845400 21289 #define HRTIM_TIMCR_TCU_Pos (21U)
AnnaBridge 172:65be27845400 21290 #define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21291 #define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
AnnaBridge 172:65be27845400 21292 #define HRTIM_TIMCR_TDU_Pos (22U)
AnnaBridge 172:65be27845400 21293 #define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21294 #define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
AnnaBridge 172:65be27845400 21295 #define HRTIM_TIMCR_TEU_Pos (23U)
AnnaBridge 172:65be27845400 21296 #define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 21297 #define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
AnnaBridge 172:65be27845400 21298 #define HRTIM_TIMCR_MSTU_Pos (24U)
AnnaBridge 172:65be27845400 21299 #define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 21300 #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
AnnaBridge 172:65be27845400 21301
AnnaBridge 172:65be27845400 21302 #define HRTIM_TIMCR_DACSYNC_Pos (25U)
AnnaBridge 172:65be27845400 21303 #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
AnnaBridge 172:65be27845400 21304 #define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
AnnaBridge 172:65be27845400 21305 #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 21306 #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 21307 #define HRTIM_TIMCR_PREEN_Pos (27U)
AnnaBridge 172:65be27845400 21308 #define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 21309 #define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
AnnaBridge 172:65be27845400 21310
AnnaBridge 172:65be27845400 21311 #define HRTIM_TIMCR_UPDGAT_Pos (28U)
AnnaBridge 172:65be27845400 21312 #define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
AnnaBridge 172:65be27845400 21313 #define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
AnnaBridge 172:65be27845400 21314 #define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 21315 #define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 21316 #define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 21317 #define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 21318
AnnaBridge 172:65be27845400 21319 /******************** Slave Interrupt status register **************************/
AnnaBridge 172:65be27845400 21320 #define HRTIM_TIMISR_CMP1_Pos (0U)
AnnaBridge 172:65be27845400 21321 #define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21322 #define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
AnnaBridge 172:65be27845400 21323 #define HRTIM_TIMISR_CMP2_Pos (1U)
AnnaBridge 172:65be27845400 21324 #define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21325 #define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
AnnaBridge 172:65be27845400 21326 #define HRTIM_TIMISR_CMP3_Pos (2U)
AnnaBridge 172:65be27845400 21327 #define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21328 #define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
AnnaBridge 172:65be27845400 21329 #define HRTIM_TIMISR_CMP4_Pos (3U)
AnnaBridge 172:65be27845400 21330 #define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21331 #define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
AnnaBridge 172:65be27845400 21332 #define HRTIM_TIMISR_REP_Pos (4U)
AnnaBridge 172:65be27845400 21333 #define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21334 #define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
AnnaBridge 172:65be27845400 21335 #define HRTIM_TIMISR_UPD_Pos (6U)
AnnaBridge 172:65be27845400 21336 #define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21337 #define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
AnnaBridge 172:65be27845400 21338 #define HRTIM_TIMISR_CPT1_Pos (7U)
AnnaBridge 172:65be27845400 21339 #define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21340 #define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
AnnaBridge 172:65be27845400 21341 #define HRTIM_TIMISR_CPT2_Pos (8U)
AnnaBridge 172:65be27845400 21342 #define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21343 #define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
AnnaBridge 172:65be27845400 21344 #define HRTIM_TIMISR_SET1_Pos (9U)
AnnaBridge 172:65be27845400 21345 #define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21346 #define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
AnnaBridge 172:65be27845400 21347 #define HRTIM_TIMISR_RST1_Pos (10U)
AnnaBridge 172:65be27845400 21348 #define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21349 #define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
AnnaBridge 172:65be27845400 21350 #define HRTIM_TIMISR_SET2_Pos (11U)
AnnaBridge 172:65be27845400 21351 #define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21352 #define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
AnnaBridge 172:65be27845400 21353 #define HRTIM_TIMISR_RST2_Pos (12U)
AnnaBridge 172:65be27845400 21354 #define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21355 #define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
AnnaBridge 172:65be27845400 21356 #define HRTIM_TIMISR_RST_Pos (13U)
AnnaBridge 172:65be27845400 21357 #define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21358 #define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
AnnaBridge 172:65be27845400 21359 #define HRTIM_TIMISR_DLYPRT_Pos (14U)
AnnaBridge 172:65be27845400 21360 #define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21361 #define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
AnnaBridge 172:65be27845400 21362 #define HRTIM_TIMISR_CPPSTAT_Pos (16U)
AnnaBridge 172:65be27845400 21363 #define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21364 #define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
AnnaBridge 172:65be27845400 21365 #define HRTIM_TIMISR_IPPSTAT_Pos (17U)
AnnaBridge 172:65be27845400 21366 #define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21367 #define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
AnnaBridge 172:65be27845400 21368 #define HRTIM_TIMISR_O1STAT_Pos (18U)
AnnaBridge 172:65be27845400 21369 #define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21370 #define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
AnnaBridge 172:65be27845400 21371 #define HRTIM_TIMISR_O2STAT_Pos (19U)
AnnaBridge 172:65be27845400 21372 #define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21373 #define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
AnnaBridge 172:65be27845400 21374 #define HRTIM_TIMISR_O1CPY_Pos (20U)
AnnaBridge 172:65be27845400 21375 #define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21376 #define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
AnnaBridge 172:65be27845400 21377 #define HRTIM_TIMISR_O2CPY_Pos (21U)
AnnaBridge 172:65be27845400 21378 #define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21379 #define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
AnnaBridge 172:65be27845400 21380
AnnaBridge 172:65be27845400 21381 /******************** Slave Interrupt clear register **************************/
AnnaBridge 172:65be27845400 21382 #define HRTIM_TIMICR_CMP1C_Pos (0U)
AnnaBridge 172:65be27845400 21383 #define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21384 #define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
AnnaBridge 172:65be27845400 21385 #define HRTIM_TIMICR_CMP2C_Pos (1U)
AnnaBridge 172:65be27845400 21386 #define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21387 #define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
AnnaBridge 172:65be27845400 21388 #define HRTIM_TIMICR_CMP3C_Pos (2U)
AnnaBridge 172:65be27845400 21389 #define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21390 #define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
AnnaBridge 172:65be27845400 21391 #define HRTIM_TIMICR_CMP4C_Pos (3U)
AnnaBridge 172:65be27845400 21392 #define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21393 #define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
AnnaBridge 172:65be27845400 21394 #define HRTIM_TIMICR_REPC_Pos (4U)
AnnaBridge 172:65be27845400 21395 #define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21396 #define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
AnnaBridge 172:65be27845400 21397 #define HRTIM_TIMICR_UPDC_Pos (6U)
AnnaBridge 172:65be27845400 21398 #define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21399 #define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
AnnaBridge 172:65be27845400 21400 #define HRTIM_TIMICR_CPT1C_Pos (7U)
AnnaBridge 172:65be27845400 21401 #define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21402 #define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
AnnaBridge 172:65be27845400 21403 #define HRTIM_TIMICR_CPT2C_Pos (8U)
AnnaBridge 172:65be27845400 21404 #define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21405 #define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
AnnaBridge 172:65be27845400 21406 #define HRTIM_TIMICR_SET1C_Pos (9U)
AnnaBridge 172:65be27845400 21407 #define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21408 #define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
AnnaBridge 172:65be27845400 21409 #define HRTIM_TIMICR_RST1C_Pos (10U)
AnnaBridge 172:65be27845400 21410 #define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21411 #define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
AnnaBridge 172:65be27845400 21412 #define HRTIM_TIMICR_SET2C_Pos (11U)
AnnaBridge 172:65be27845400 21413 #define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21414 #define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
AnnaBridge 172:65be27845400 21415 #define HRTIM_TIMICR_RST2C_Pos (12U)
AnnaBridge 172:65be27845400 21416 #define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21417 #define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
AnnaBridge 172:65be27845400 21418 #define HRTIM_TIMICR_RSTC_Pos (13U)
AnnaBridge 172:65be27845400 21419 #define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21420 #define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
AnnaBridge 172:65be27845400 21421 #define HRTIM_TIMICR_DLYPRTC_Pos (14U)
AnnaBridge 172:65be27845400 21422 #define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21423 #define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output 1 delay protection clear flag */
AnnaBridge 172:65be27845400 21424
AnnaBridge 172:65be27845400 21425 /******************** Slave DMA/Interrupt enable register *********************/
AnnaBridge 172:65be27845400 21426 #define HRTIM_TIMDIER_CMP1IE_Pos (0U)
AnnaBridge 172:65be27845400 21427 #define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21428 #define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
AnnaBridge 172:65be27845400 21429 #define HRTIM_TIMDIER_CMP2IE_Pos (1U)
AnnaBridge 172:65be27845400 21430 #define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21431 #define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
AnnaBridge 172:65be27845400 21432 #define HRTIM_TIMDIER_CMP3IE_Pos (2U)
AnnaBridge 172:65be27845400 21433 #define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21434 #define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
AnnaBridge 172:65be27845400 21435 #define HRTIM_TIMDIER_CMP4IE_Pos (3U)
AnnaBridge 172:65be27845400 21436 #define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21437 #define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
AnnaBridge 172:65be27845400 21438 #define HRTIM_TIMDIER_REPIE_Pos (4U)
AnnaBridge 172:65be27845400 21439 #define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21440 #define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
AnnaBridge 172:65be27845400 21441 #define HRTIM_TIMDIER_UPDIE_Pos (6U)
AnnaBridge 172:65be27845400 21442 #define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21443 #define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
AnnaBridge 172:65be27845400 21444 #define HRTIM_TIMDIER_CPT1IE_Pos (7U)
AnnaBridge 172:65be27845400 21445 #define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21446 #define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
AnnaBridge 172:65be27845400 21447 #define HRTIM_TIMDIER_CPT2IE_Pos (8U)
AnnaBridge 172:65be27845400 21448 #define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21449 #define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
AnnaBridge 172:65be27845400 21450 #define HRTIM_TIMDIER_SET1IE_Pos (9U)
AnnaBridge 172:65be27845400 21451 #define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21452 #define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
AnnaBridge 172:65be27845400 21453 #define HRTIM_TIMDIER_RST1IE_Pos (10U)
AnnaBridge 172:65be27845400 21454 #define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21455 #define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
AnnaBridge 172:65be27845400 21456 #define HRTIM_TIMDIER_SET2IE_Pos (11U)
AnnaBridge 172:65be27845400 21457 #define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21458 #define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
AnnaBridge 172:65be27845400 21459 #define HRTIM_TIMDIER_RST2IE_Pos (12U)
AnnaBridge 172:65be27845400 21460 #define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21461 #define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
AnnaBridge 172:65be27845400 21462 #define HRTIM_TIMDIER_RSTIE_Pos (13U)
AnnaBridge 172:65be27845400 21463 #define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21464 #define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
AnnaBridge 172:65be27845400 21465 #define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
AnnaBridge 172:65be27845400 21466 #define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21467 #define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
AnnaBridge 172:65be27845400 21468
AnnaBridge 172:65be27845400 21469 #define HRTIM_TIMDIER_CMP1DE_Pos (16U)
AnnaBridge 172:65be27845400 21470 #define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21471 #define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
AnnaBridge 172:65be27845400 21472 #define HRTIM_TIMDIER_CMP2DE_Pos (17U)
AnnaBridge 172:65be27845400 21473 #define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21474 #define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
AnnaBridge 172:65be27845400 21475 #define HRTIM_TIMDIER_CMP3DE_Pos (18U)
AnnaBridge 172:65be27845400 21476 #define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21477 #define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
AnnaBridge 172:65be27845400 21478 #define HRTIM_TIMDIER_CMP4DE_Pos (19U)
AnnaBridge 172:65be27845400 21479 #define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21480 #define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
AnnaBridge 172:65be27845400 21481 #define HRTIM_TIMDIER_REPDE_Pos (20U)
AnnaBridge 172:65be27845400 21482 #define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21483 #define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
AnnaBridge 172:65be27845400 21484 #define HRTIM_TIMDIER_UPDDE_Pos (22U)
AnnaBridge 172:65be27845400 21485 #define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21486 #define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
AnnaBridge 172:65be27845400 21487 #define HRTIM_TIMDIER_CPT1DE_Pos (23U)
AnnaBridge 172:65be27845400 21488 #define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 21489 #define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
AnnaBridge 172:65be27845400 21490 #define HRTIM_TIMDIER_CPT2DE_Pos (24U)
AnnaBridge 172:65be27845400 21491 #define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 21492 #define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
AnnaBridge 172:65be27845400 21493 #define HRTIM_TIMDIER_SET1DE_Pos (25U)
AnnaBridge 172:65be27845400 21494 #define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 21495 #define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
AnnaBridge 172:65be27845400 21496 #define HRTIM_TIMDIER_RST1DE_Pos (26U)
AnnaBridge 172:65be27845400 21497 #define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 21498 #define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
AnnaBridge 172:65be27845400 21499 #define HRTIM_TIMDIER_SET2DE_Pos (27U)
AnnaBridge 172:65be27845400 21500 #define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 21501 #define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
AnnaBridge 172:65be27845400 21502 #define HRTIM_TIMDIER_RST2DE_Pos (28U)
AnnaBridge 172:65be27845400 21503 #define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 21504 #define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
AnnaBridge 172:65be27845400 21505 #define HRTIM_TIMDIER_RSTDE_Pos (29U)
AnnaBridge 172:65be27845400 21506 #define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 21507 #define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
AnnaBridge 172:65be27845400 21508 #define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
AnnaBridge 172:65be27845400 21509 #define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 21510 #define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
AnnaBridge 172:65be27845400 21511
AnnaBridge 172:65be27845400 21512 /****************** Bit definition for HRTIM_CNTR register ****************/
AnnaBridge 172:65be27845400 21513 #define HRTIM_CNTR_CNTR_Pos (0U)
AnnaBridge 172:65be27845400 21514 #define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21515 #define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
AnnaBridge 172:65be27845400 21516
AnnaBridge 172:65be27845400 21517 /******************* Bit definition for HRTIM_PER register *****************/
AnnaBridge 172:65be27845400 21518 #define HRTIM_PER_PER_Pos (0U)
AnnaBridge 172:65be27845400 21519 #define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21520 #define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
AnnaBridge 172:65be27845400 21521
AnnaBridge 172:65be27845400 21522 /******************* Bit definition for HRTIM_REP register *****************/
AnnaBridge 172:65be27845400 21523 #define HRTIM_REP_REP_Pos (0U)
AnnaBridge 172:65be27845400 21524 #define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
AnnaBridge 172:65be27845400 21525 #define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
AnnaBridge 172:65be27845400 21526
AnnaBridge 172:65be27845400 21527 /******************* Bit definition for HRTIM_CMP1R register *****************/
AnnaBridge 172:65be27845400 21528 #define HRTIM_CMP1R_CMP1R_Pos (0U)
AnnaBridge 172:65be27845400 21529 #define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21530 #define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
AnnaBridge 172:65be27845400 21531
AnnaBridge 172:65be27845400 21532 /******************* Bit definition for HRTIM_CMP1CR register *****************/
AnnaBridge 172:65be27845400 21533 #define HRTIM_CMP1CR_CMP1CR_Pos (0U)
AnnaBridge 172:65be27845400 21534 #define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 21535 #define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
AnnaBridge 172:65be27845400 21536
AnnaBridge 172:65be27845400 21537 /******************* Bit definition for HRTIM_CMP2R register *****************/
AnnaBridge 172:65be27845400 21538 #define HRTIM_CMP2R_CMP2R_Pos (0U)
AnnaBridge 172:65be27845400 21539 #define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21540 #define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
AnnaBridge 172:65be27845400 21541
AnnaBridge 172:65be27845400 21542 /******************* Bit definition for HRTIM_CMP3R register *****************/
AnnaBridge 172:65be27845400 21543 #define HRTIM_CMP3R_CMP3R_Pos (0U)
AnnaBridge 172:65be27845400 21544 #define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21545 #define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
AnnaBridge 172:65be27845400 21546
AnnaBridge 172:65be27845400 21547 /******************* Bit definition for HRTIM_CMP4R register *****************/
AnnaBridge 172:65be27845400 21548 #define HRTIM_CMP4R_CMP4R_Pos (0U)
AnnaBridge 172:65be27845400 21549 #define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21550 #define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
AnnaBridge 172:65be27845400 21551
AnnaBridge 172:65be27845400 21552 /******************* Bit definition for HRTIM_CPT1R register ****************/
AnnaBridge 172:65be27845400 21553 #define HRTIM_CPT1R_CPT1R_Pos (0U)
AnnaBridge 172:65be27845400 21554 #define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21555 #define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
AnnaBridge 172:65be27845400 21556
AnnaBridge 172:65be27845400 21557 /******************* Bit definition for HRTIM_CPT2R register ****************/
AnnaBridge 172:65be27845400 21558 #define HRTIM_CPT2R_CPT2R_Pos (0U)
AnnaBridge 172:65be27845400 21559 #define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 21560 #define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
AnnaBridge 172:65be27845400 21561
AnnaBridge 172:65be27845400 21562 /******************** Bit definition for Slave Deadtime register **************/
AnnaBridge 172:65be27845400 21563 #define HRTIM_DTR_DTR_Pos (0U)
AnnaBridge 172:65be27845400 21564 #define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
AnnaBridge 172:65be27845400 21565 #define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
AnnaBridge 172:65be27845400 21566 #define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21567 #define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21568 #define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21569 #define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21570 #define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21571 #define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21572 #define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21573 #define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21574 #define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21575 #define HRTIM_DTR_SDTR_Pos (9U)
AnnaBridge 172:65be27845400 21576 #define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21577 #define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
AnnaBridge 172:65be27845400 21578 #define HRTIM_DTR_DTPRSC_Pos (10U)
AnnaBridge 172:65be27845400 21579 #define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
AnnaBridge 172:65be27845400 21580 #define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
AnnaBridge 172:65be27845400 21581 #define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21582 #define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21583 #define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21584 #define HRTIM_DTR_DTRSLK_Pos (14U)
AnnaBridge 172:65be27845400 21585 #define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21586 #define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
AnnaBridge 172:65be27845400 21587 #define HRTIM_DTR_DTRLK_Pos (15U)
AnnaBridge 172:65be27845400 21588 #define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 21589 #define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
AnnaBridge 172:65be27845400 21590 #define HRTIM_DTR_DTF_Pos (16U)
AnnaBridge 172:65be27845400 21591 #define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
AnnaBridge 172:65be27845400 21592 #define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
AnnaBridge 172:65be27845400 21593 #define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21594 #define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21595 #define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21596 #define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21597 #define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21598 #define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21599 #define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21600 #define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 21601 #define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 21602 #define HRTIM_DTR_SDTF_Pos (25U)
AnnaBridge 172:65be27845400 21603 #define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 21604 #define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
AnnaBridge 172:65be27845400 21605 #define HRTIM_DTR_DTFSLK_Pos (30U)
AnnaBridge 172:65be27845400 21606 #define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 21607 #define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
AnnaBridge 172:65be27845400 21608 #define HRTIM_DTR_DTFLK_Pos (31U)
AnnaBridge 172:65be27845400 21609 #define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 21610 #define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
AnnaBridge 172:65be27845400 21611
AnnaBridge 172:65be27845400 21612 /**** Bit definition for Slave Output 1 set register **************************/
AnnaBridge 172:65be27845400 21613 #define HRTIM_SET1R_SST_Pos (0U)
AnnaBridge 172:65be27845400 21614 #define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21615 #define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
AnnaBridge 172:65be27845400 21616 #define HRTIM_SET1R_RESYNC_Pos (1U)
AnnaBridge 172:65be27845400 21617 #define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21618 #define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 172:65be27845400 21619 #define HRTIM_SET1R_PER_Pos (2U)
AnnaBridge 172:65be27845400 21620 #define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21621 #define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
AnnaBridge 172:65be27845400 21622 #define HRTIM_SET1R_CMP1_Pos (3U)
AnnaBridge 172:65be27845400 21623 #define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21624 #define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 172:65be27845400 21625 #define HRTIM_SET1R_CMP2_Pos (4U)
AnnaBridge 172:65be27845400 21626 #define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21627 #define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 172:65be27845400 21628 #define HRTIM_SET1R_CMP3_Pos (5U)
AnnaBridge 172:65be27845400 21629 #define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21630 #define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 172:65be27845400 21631 #define HRTIM_SET1R_CMP4_Pos (6U)
AnnaBridge 172:65be27845400 21632 #define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21633 #define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 172:65be27845400 21634
AnnaBridge 172:65be27845400 21635 #define HRTIM_SET1R_MSTPER_Pos (7U)
AnnaBridge 172:65be27845400 21636 #define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21637 #define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
AnnaBridge 172:65be27845400 21638 #define HRTIM_SET1R_MSTCMP1_Pos (8U)
AnnaBridge 172:65be27845400 21639 #define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21640 #define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 172:65be27845400 21641 #define HRTIM_SET1R_MSTCMP2_Pos (9U)
AnnaBridge 172:65be27845400 21642 #define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21643 #define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 172:65be27845400 21644 #define HRTIM_SET1R_MSTCMP3_Pos (10U)
AnnaBridge 172:65be27845400 21645 #define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21646 #define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 172:65be27845400 21647 #define HRTIM_SET1R_MSTCMP4_Pos (11U)
AnnaBridge 172:65be27845400 21648 #define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21649 #define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 172:65be27845400 21650
AnnaBridge 172:65be27845400 21651 #define HRTIM_SET1R_TIMEVNT1_Pos (12U)
AnnaBridge 172:65be27845400 21652 #define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21653 #define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 172:65be27845400 21654 #define HRTIM_SET1R_TIMEVNT2_Pos (13U)
AnnaBridge 172:65be27845400 21655 #define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21656 #define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 172:65be27845400 21657 #define HRTIM_SET1R_TIMEVNT3_Pos (14U)
AnnaBridge 172:65be27845400 21658 #define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21659 #define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 172:65be27845400 21660 #define HRTIM_SET1R_TIMEVNT4_Pos (15U)
AnnaBridge 172:65be27845400 21661 #define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 21662 #define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 172:65be27845400 21663 #define HRTIM_SET1R_TIMEVNT5_Pos (16U)
AnnaBridge 172:65be27845400 21664 #define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21665 #define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 172:65be27845400 21666 #define HRTIM_SET1R_TIMEVNT6_Pos (17U)
AnnaBridge 172:65be27845400 21667 #define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21668 #define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 172:65be27845400 21669 #define HRTIM_SET1R_TIMEVNT7_Pos (18U)
AnnaBridge 172:65be27845400 21670 #define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21671 #define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 172:65be27845400 21672 #define HRTIM_SET1R_TIMEVNT8_Pos (19U)
AnnaBridge 172:65be27845400 21673 #define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21674 #define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 172:65be27845400 21675 #define HRTIM_SET1R_TIMEVNT9_Pos (20U)
AnnaBridge 172:65be27845400 21676 #define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21677 #define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 172:65be27845400 21678
AnnaBridge 172:65be27845400 21679 #define HRTIM_SET1R_EXTVNT1_Pos (21U)
AnnaBridge 172:65be27845400 21680 #define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21681 #define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 172:65be27845400 21682 #define HRTIM_SET1R_EXTVNT2_Pos (22U)
AnnaBridge 172:65be27845400 21683 #define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21684 #define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 172:65be27845400 21685 #define HRTIM_SET1R_EXTVNT3_Pos (23U)
AnnaBridge 172:65be27845400 21686 #define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 21687 #define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 172:65be27845400 21688 #define HRTIM_SET1R_EXTVNT4_Pos (24U)
AnnaBridge 172:65be27845400 21689 #define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 21690 #define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 172:65be27845400 21691 #define HRTIM_SET1R_EXTVNT5_Pos (25U)
AnnaBridge 172:65be27845400 21692 #define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 21693 #define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 172:65be27845400 21694 #define HRTIM_SET1R_EXTVNT6_Pos (26U)
AnnaBridge 172:65be27845400 21695 #define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 21696 #define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 172:65be27845400 21697 #define HRTIM_SET1R_EXTVNT7_Pos (27U)
AnnaBridge 172:65be27845400 21698 #define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 21699 #define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 172:65be27845400 21700 #define HRTIM_SET1R_EXTVNT8_Pos (28U)
AnnaBridge 172:65be27845400 21701 #define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 21702 #define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 172:65be27845400 21703 #define HRTIM_SET1R_EXTVNT9_Pos (29U)
AnnaBridge 172:65be27845400 21704 #define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 21705 #define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 172:65be27845400 21706 #define HRTIM_SET1R_EXTVNT10_Pos (30U)
AnnaBridge 172:65be27845400 21707 #define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 21708 #define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 172:65be27845400 21709
AnnaBridge 172:65be27845400 21710 #define HRTIM_SET1R_UPDATE_Pos (31U)
AnnaBridge 172:65be27845400 21711 #define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 21712 #define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 172:65be27845400 21713
AnnaBridge 172:65be27845400 21714 /**** Bit definition for Slave Output 1 reset register ************************/
AnnaBridge 172:65be27845400 21715 #define HRTIM_RST1R_SRT_Pos (0U)
AnnaBridge 172:65be27845400 21716 #define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21717 #define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
AnnaBridge 172:65be27845400 21718 #define HRTIM_RST1R_RESYNC_Pos (1U)
AnnaBridge 172:65be27845400 21719 #define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21720 #define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 172:65be27845400 21721 #define HRTIM_RST1R_PER_Pos (2U)
AnnaBridge 172:65be27845400 21722 #define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21723 #define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
AnnaBridge 172:65be27845400 21724 #define HRTIM_RST1R_CMP1_Pos (3U)
AnnaBridge 172:65be27845400 21725 #define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21726 #define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 172:65be27845400 21727 #define HRTIM_RST1R_CMP2_Pos (4U)
AnnaBridge 172:65be27845400 21728 #define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21729 #define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 172:65be27845400 21730 #define HRTIM_RST1R_CMP3_Pos (5U)
AnnaBridge 172:65be27845400 21731 #define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21732 #define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 172:65be27845400 21733 #define HRTIM_RST1R_CMP4_Pos (6U)
AnnaBridge 172:65be27845400 21734 #define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21735 #define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 172:65be27845400 21736
AnnaBridge 172:65be27845400 21737 #define HRTIM_RST1R_MSTPER_Pos (7U)
AnnaBridge 172:65be27845400 21738 #define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21739 #define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
AnnaBridge 172:65be27845400 21740 #define HRTIM_RST1R_MSTCMP1_Pos (8U)
AnnaBridge 172:65be27845400 21741 #define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21742 #define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 172:65be27845400 21743 #define HRTIM_RST1R_MSTCMP2_Pos (9U)
AnnaBridge 172:65be27845400 21744 #define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21745 #define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 172:65be27845400 21746 #define HRTIM_RST1R_MSTCMP3_Pos (10U)
AnnaBridge 172:65be27845400 21747 #define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21748 #define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 172:65be27845400 21749 #define HRTIM_RST1R_MSTCMP4_Pos (11U)
AnnaBridge 172:65be27845400 21750 #define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21751 #define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 172:65be27845400 21752
AnnaBridge 172:65be27845400 21753 #define HRTIM_RST1R_TIMEVNT1_Pos (12U)
AnnaBridge 172:65be27845400 21754 #define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21755 #define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 172:65be27845400 21756 #define HRTIM_RST1R_TIMEVNT2_Pos (13U)
AnnaBridge 172:65be27845400 21757 #define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21758 #define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 172:65be27845400 21759 #define HRTIM_RST1R_TIMEVNT3_Pos (14U)
AnnaBridge 172:65be27845400 21760 #define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21761 #define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 172:65be27845400 21762 #define HRTIM_RST1R_TIMEVNT4_Pos (15U)
AnnaBridge 172:65be27845400 21763 #define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 21764 #define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 172:65be27845400 21765 #define HRTIM_RST1R_TIMEVNT5_Pos (16U)
AnnaBridge 172:65be27845400 21766 #define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21767 #define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 172:65be27845400 21768 #define HRTIM_RST1R_TIMEVNT6_Pos (17U)
AnnaBridge 172:65be27845400 21769 #define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21770 #define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 172:65be27845400 21771 #define HRTIM_RST1R_TIMEVNT7_Pos (18U)
AnnaBridge 172:65be27845400 21772 #define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21773 #define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 172:65be27845400 21774 #define HRTIM_RST1R_TIMEVNT8_Pos (19U)
AnnaBridge 172:65be27845400 21775 #define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21776 #define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 172:65be27845400 21777 #define HRTIM_RST1R_TIMEVNT9_Pos (20U)
AnnaBridge 172:65be27845400 21778 #define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21779 #define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 172:65be27845400 21780
AnnaBridge 172:65be27845400 21781 #define HRTIM_RST1R_EXTVNT1_Pos (21U)
AnnaBridge 172:65be27845400 21782 #define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21783 #define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 172:65be27845400 21784 #define HRTIM_RST1R_EXTVNT2_Pos (22U)
AnnaBridge 172:65be27845400 21785 #define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21786 #define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 172:65be27845400 21787 #define HRTIM_RST1R_EXTVNT3_Pos (23U)
AnnaBridge 172:65be27845400 21788 #define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 21789 #define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 172:65be27845400 21790 #define HRTIM_RST1R_EXTVNT4_Pos (24U)
AnnaBridge 172:65be27845400 21791 #define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 21792 #define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 172:65be27845400 21793 #define HRTIM_RST1R_EXTVNT5_Pos (25U)
AnnaBridge 172:65be27845400 21794 #define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 21795 #define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 172:65be27845400 21796 #define HRTIM_RST1R_EXTVNT6_Pos (26U)
AnnaBridge 172:65be27845400 21797 #define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 21798 #define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 172:65be27845400 21799 #define HRTIM_RST1R_EXTVNT7_Pos (27U)
AnnaBridge 172:65be27845400 21800 #define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 21801 #define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 172:65be27845400 21802 #define HRTIM_RST1R_EXTVNT8_Pos (28U)
AnnaBridge 172:65be27845400 21803 #define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 21804 #define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 172:65be27845400 21805 #define HRTIM_RST1R_EXTVNT9_Pos (29U)
AnnaBridge 172:65be27845400 21806 #define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 21807 #define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 172:65be27845400 21808 #define HRTIM_RST1R_EXTVNT10_Pos (30U)
AnnaBridge 172:65be27845400 21809 #define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 21810 #define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 172:65be27845400 21811
AnnaBridge 172:65be27845400 21812 #define HRTIM_RST1R_UPDATE_Pos (31U)
AnnaBridge 172:65be27845400 21813 #define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 21814 #define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 172:65be27845400 21815
AnnaBridge 172:65be27845400 21816
AnnaBridge 172:65be27845400 21817 /**** Bit definition for Slave Output 2 set register **************************/
AnnaBridge 172:65be27845400 21818 #define HRTIM_SET2R_SST_Pos (0U)
AnnaBridge 172:65be27845400 21819 #define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21820 #define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
AnnaBridge 172:65be27845400 21821 #define HRTIM_SET2R_RESYNC_Pos (1U)
AnnaBridge 172:65be27845400 21822 #define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21823 #define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 172:65be27845400 21824 #define HRTIM_SET2R_PER_Pos (2U)
AnnaBridge 172:65be27845400 21825 #define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21826 #define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
AnnaBridge 172:65be27845400 21827 #define HRTIM_SET2R_CMP1_Pos (3U)
AnnaBridge 172:65be27845400 21828 #define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21829 #define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 172:65be27845400 21830 #define HRTIM_SET2R_CMP2_Pos (4U)
AnnaBridge 172:65be27845400 21831 #define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21832 #define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 172:65be27845400 21833 #define HRTIM_SET2R_CMP3_Pos (5U)
AnnaBridge 172:65be27845400 21834 #define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21835 #define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 172:65be27845400 21836 #define HRTIM_SET2R_CMP4_Pos (6U)
AnnaBridge 172:65be27845400 21837 #define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21838 #define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 172:65be27845400 21839
AnnaBridge 172:65be27845400 21840 #define HRTIM_SET2R_MSTPER_Pos (7U)
AnnaBridge 172:65be27845400 21841 #define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21842 #define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
AnnaBridge 172:65be27845400 21843 #define HRTIM_SET2R_MSTCMP1_Pos (8U)
AnnaBridge 172:65be27845400 21844 #define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21845 #define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 172:65be27845400 21846 #define HRTIM_SET2R_MSTCMP2_Pos (9U)
AnnaBridge 172:65be27845400 21847 #define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21848 #define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 172:65be27845400 21849 #define HRTIM_SET2R_MSTCMP3_Pos (10U)
AnnaBridge 172:65be27845400 21850 #define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21851 #define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 172:65be27845400 21852 #define HRTIM_SET2R_MSTCMP4_Pos (11U)
AnnaBridge 172:65be27845400 21853 #define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21854 #define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 172:65be27845400 21855
AnnaBridge 172:65be27845400 21856 #define HRTIM_SET2R_TIMEVNT1_Pos (12U)
AnnaBridge 172:65be27845400 21857 #define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21858 #define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 172:65be27845400 21859 #define HRTIM_SET2R_TIMEVNT2_Pos (13U)
AnnaBridge 172:65be27845400 21860 #define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21861 #define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 172:65be27845400 21862 #define HRTIM_SET2R_TIMEVNT3_Pos (14U)
AnnaBridge 172:65be27845400 21863 #define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21864 #define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 172:65be27845400 21865 #define HRTIM_SET2R_TIMEVNT4_Pos (15U)
AnnaBridge 172:65be27845400 21866 #define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 21867 #define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 172:65be27845400 21868 #define HRTIM_SET2R_TIMEVNT5_Pos (16U)
AnnaBridge 172:65be27845400 21869 #define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21870 #define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 172:65be27845400 21871 #define HRTIM_SET2R_TIMEVNT6_Pos (17U)
AnnaBridge 172:65be27845400 21872 #define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21873 #define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 172:65be27845400 21874 #define HRTIM_SET2R_TIMEVNT7_Pos (18U)
AnnaBridge 172:65be27845400 21875 #define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21876 #define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 172:65be27845400 21877 #define HRTIM_SET2R_TIMEVNT8_Pos (19U)
AnnaBridge 172:65be27845400 21878 #define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21879 #define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 172:65be27845400 21880 #define HRTIM_SET2R_TIMEVNT9_Pos (20U)
AnnaBridge 172:65be27845400 21881 #define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21882 #define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 172:65be27845400 21883
AnnaBridge 172:65be27845400 21884 #define HRTIM_SET2R_EXTVNT1_Pos (21U)
AnnaBridge 172:65be27845400 21885 #define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21886 #define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 172:65be27845400 21887 #define HRTIM_SET2R_EXTVNT2_Pos (22U)
AnnaBridge 172:65be27845400 21888 #define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21889 #define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 172:65be27845400 21890 #define HRTIM_SET2R_EXTVNT3_Pos (23U)
AnnaBridge 172:65be27845400 21891 #define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 21892 #define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 172:65be27845400 21893 #define HRTIM_SET2R_EXTVNT4_Pos (24U)
AnnaBridge 172:65be27845400 21894 #define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 21895 #define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 172:65be27845400 21896 #define HRTIM_SET2R_EXTVNT5_Pos (25U)
AnnaBridge 172:65be27845400 21897 #define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 21898 #define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 172:65be27845400 21899 #define HRTIM_SET2R_EXTVNT6_Pos (26U)
AnnaBridge 172:65be27845400 21900 #define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 21901 #define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 172:65be27845400 21902 #define HRTIM_SET2R_EXTVNT7_Pos (27U)
AnnaBridge 172:65be27845400 21903 #define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 21904 #define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 172:65be27845400 21905 #define HRTIM_SET2R_EXTVNT8_Pos (28U)
AnnaBridge 172:65be27845400 21906 #define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 21907 #define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 172:65be27845400 21908 #define HRTIM_SET2R_EXTVNT9_Pos (29U)
AnnaBridge 172:65be27845400 21909 #define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 21910 #define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 172:65be27845400 21911 #define HRTIM_SET2R_EXTVNT10_Pos (30U)
AnnaBridge 172:65be27845400 21912 #define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 21913 #define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 172:65be27845400 21914
AnnaBridge 172:65be27845400 21915 #define HRTIM_SET2R_UPDATE_Pos (31U)
AnnaBridge 172:65be27845400 21916 #define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 21917 #define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 172:65be27845400 21918
AnnaBridge 172:65be27845400 21919 /**** Bit definition for Slave Output 2 reset register ************************/
AnnaBridge 172:65be27845400 21920 #define HRTIM_RST2R_SRT_Pos (0U)
AnnaBridge 172:65be27845400 21921 #define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 21922 #define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
AnnaBridge 172:65be27845400 21923 #define HRTIM_RST2R_RESYNC_Pos (1U)
AnnaBridge 172:65be27845400 21924 #define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 21925 #define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
AnnaBridge 172:65be27845400 21926 #define HRTIM_RST2R_PER_Pos (2U)
AnnaBridge 172:65be27845400 21927 #define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 21928 #define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
AnnaBridge 172:65be27845400 21929 #define HRTIM_RST2R_CMP1_Pos (3U)
AnnaBridge 172:65be27845400 21930 #define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 21931 #define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 172:65be27845400 21932 #define HRTIM_RST2R_CMP2_Pos (4U)
AnnaBridge 172:65be27845400 21933 #define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 21934 #define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 172:65be27845400 21935 #define HRTIM_RST2R_CMP3_Pos (5U)
AnnaBridge 172:65be27845400 21936 #define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 21937 #define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
AnnaBridge 172:65be27845400 21938 #define HRTIM_RST2R_CMP4_Pos (6U)
AnnaBridge 172:65be27845400 21939 #define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 21940 #define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
AnnaBridge 172:65be27845400 21941
AnnaBridge 172:65be27845400 21942 #define HRTIM_RST2R_MSTPER_Pos (7U)
AnnaBridge 172:65be27845400 21943 #define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 21944 #define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
AnnaBridge 172:65be27845400 21945 #define HRTIM_RST2R_MSTCMP1_Pos (8U)
AnnaBridge 172:65be27845400 21946 #define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 21947 #define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 172:65be27845400 21948 #define HRTIM_RST2R_MSTCMP2_Pos (9U)
AnnaBridge 172:65be27845400 21949 #define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 21950 #define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 172:65be27845400 21951 #define HRTIM_RST2R_MSTCMP3_Pos (10U)
AnnaBridge 172:65be27845400 21952 #define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 21953 #define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 172:65be27845400 21954 #define HRTIM_RST2R_MSTCMP4_Pos (11U)
AnnaBridge 172:65be27845400 21955 #define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 21956 #define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 172:65be27845400 21957
AnnaBridge 172:65be27845400 21958 #define HRTIM_RST2R_TIMEVNT1_Pos (12U)
AnnaBridge 172:65be27845400 21959 #define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 21960 #define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
AnnaBridge 172:65be27845400 21961 #define HRTIM_RST2R_TIMEVNT2_Pos (13U)
AnnaBridge 172:65be27845400 21962 #define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 21963 #define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
AnnaBridge 172:65be27845400 21964 #define HRTIM_RST2R_TIMEVNT3_Pos (14U)
AnnaBridge 172:65be27845400 21965 #define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 21966 #define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
AnnaBridge 172:65be27845400 21967 #define HRTIM_RST2R_TIMEVNT4_Pos (15U)
AnnaBridge 172:65be27845400 21968 #define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 21969 #define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
AnnaBridge 172:65be27845400 21970 #define HRTIM_RST2R_TIMEVNT5_Pos (16U)
AnnaBridge 172:65be27845400 21971 #define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 21972 #define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
AnnaBridge 172:65be27845400 21973 #define HRTIM_RST2R_TIMEVNT6_Pos (17U)
AnnaBridge 172:65be27845400 21974 #define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 21975 #define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
AnnaBridge 172:65be27845400 21976 #define HRTIM_RST2R_TIMEVNT7_Pos (18U)
AnnaBridge 172:65be27845400 21977 #define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 21978 #define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
AnnaBridge 172:65be27845400 21979 #define HRTIM_RST2R_TIMEVNT8_Pos (19U)
AnnaBridge 172:65be27845400 21980 #define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 21981 #define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
AnnaBridge 172:65be27845400 21982 #define HRTIM_RST2R_TIMEVNT9_Pos (20U)
AnnaBridge 172:65be27845400 21983 #define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 21984 #define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
AnnaBridge 172:65be27845400 21985
AnnaBridge 172:65be27845400 21986 #define HRTIM_RST2R_EXTVNT1_Pos (21U)
AnnaBridge 172:65be27845400 21987 #define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 21988 #define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
AnnaBridge 172:65be27845400 21989 #define HRTIM_RST2R_EXTVNT2_Pos (22U)
AnnaBridge 172:65be27845400 21990 #define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 21991 #define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
AnnaBridge 172:65be27845400 21992 #define HRTIM_RST2R_EXTVNT3_Pos (23U)
AnnaBridge 172:65be27845400 21993 #define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 21994 #define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
AnnaBridge 172:65be27845400 21995 #define HRTIM_RST2R_EXTVNT4_Pos (24U)
AnnaBridge 172:65be27845400 21996 #define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 21997 #define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
AnnaBridge 172:65be27845400 21998 #define HRTIM_RST2R_EXTVNT5_Pos (25U)
AnnaBridge 172:65be27845400 21999 #define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22000 #define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
AnnaBridge 172:65be27845400 22001 #define HRTIM_RST2R_EXTVNT6_Pos (26U)
AnnaBridge 172:65be27845400 22002 #define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22003 #define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
AnnaBridge 172:65be27845400 22004 #define HRTIM_RST2R_EXTVNT7_Pos (27U)
AnnaBridge 172:65be27845400 22005 #define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 22006 #define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
AnnaBridge 172:65be27845400 22007 #define HRTIM_RST2R_EXTVNT8_Pos (28U)
AnnaBridge 172:65be27845400 22008 #define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 22009 #define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
AnnaBridge 172:65be27845400 22010 #define HRTIM_RST2R_EXTVNT9_Pos (29U)
AnnaBridge 172:65be27845400 22011 #define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 22012 #define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
AnnaBridge 172:65be27845400 22013 #define HRTIM_RST2R_EXTVNT10_Pos (30U)
AnnaBridge 172:65be27845400 22014 #define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 22015 #define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
AnnaBridge 172:65be27845400 22016
AnnaBridge 172:65be27845400 22017 #define HRTIM_RST2R_UPDATE_Pos (31U)
AnnaBridge 172:65be27845400 22018 #define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 22019 #define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
AnnaBridge 172:65be27845400 22020
AnnaBridge 172:65be27845400 22021 /**** Bit definition for Slave external event filtering register 1 ***********/
AnnaBridge 172:65be27845400 22022 #define HRTIM_EEFR1_EE1LTCH_Pos (0U)
AnnaBridge 172:65be27845400 22023 #define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22024 #define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
AnnaBridge 172:65be27845400 22025 #define HRTIM_EEFR1_EE1FLTR_Pos (1U)
AnnaBridge 172:65be27845400 22026 #define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
AnnaBridge 172:65be27845400 22027 #define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
AnnaBridge 172:65be27845400 22028 #define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22029 #define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22030 #define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22031 #define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22032
AnnaBridge 172:65be27845400 22033 #define HRTIM_EEFR1_EE2LTCH_Pos (6U)
AnnaBridge 172:65be27845400 22034 #define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22035 #define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
AnnaBridge 172:65be27845400 22036 #define HRTIM_EEFR1_EE2FLTR_Pos (7U)
AnnaBridge 172:65be27845400 22037 #define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
AnnaBridge 172:65be27845400 22038 #define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
AnnaBridge 172:65be27845400 22039 #define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22040 #define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22041 #define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22042 #define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22043
AnnaBridge 172:65be27845400 22044 #define HRTIM_EEFR1_EE3LTCH_Pos (12U)
AnnaBridge 172:65be27845400 22045 #define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22046 #define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
AnnaBridge 172:65be27845400 22047 #define HRTIM_EEFR1_EE3FLTR_Pos (13U)
AnnaBridge 172:65be27845400 22048 #define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 22049 #define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
AnnaBridge 172:65be27845400 22050 #define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22051 #define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 22052 #define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 22053 #define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22054
AnnaBridge 172:65be27845400 22055 #define HRTIM_EEFR1_EE4LTCH_Pos (18U)
AnnaBridge 172:65be27845400 22056 #define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22057 #define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
AnnaBridge 172:65be27845400 22058 #define HRTIM_EEFR1_EE4FLTR_Pos (19U)
AnnaBridge 172:65be27845400 22059 #define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
AnnaBridge 172:65be27845400 22060 #define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
AnnaBridge 172:65be27845400 22061 #define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22062 #define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22063 #define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22064 #define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22065
AnnaBridge 172:65be27845400 22066 #define HRTIM_EEFR1_EE5LTCH_Pos (24U)
AnnaBridge 172:65be27845400 22067 #define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 22068 #define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
AnnaBridge 172:65be27845400 22069 #define HRTIM_EEFR1_EE5FLTR_Pos (25U)
AnnaBridge 172:65be27845400 22070 #define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
AnnaBridge 172:65be27845400 22071 #define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
AnnaBridge 172:65be27845400 22072 #define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22073 #define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22074 #define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 22075 #define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 22076
AnnaBridge 172:65be27845400 22077 /**** Bit definition for Slave external event filtering register 2 ***********/
AnnaBridge 172:65be27845400 22078 #define HRTIM_EEFR2_EE6LTCH_Pos (0U)
AnnaBridge 172:65be27845400 22079 #define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22080 #define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
AnnaBridge 172:65be27845400 22081 #define HRTIM_EEFR2_EE6FLTR_Pos (1U)
AnnaBridge 172:65be27845400 22082 #define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
AnnaBridge 172:65be27845400 22083 #define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
AnnaBridge 172:65be27845400 22084 #define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22085 #define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22086 #define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22087 #define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22088
AnnaBridge 172:65be27845400 22089 #define HRTIM_EEFR2_EE7LTCH_Pos (6U)
AnnaBridge 172:65be27845400 22090 #define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22091 #define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
AnnaBridge 172:65be27845400 22092 #define HRTIM_EEFR2_EE7FLTR_Pos (7U)
AnnaBridge 172:65be27845400 22093 #define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
AnnaBridge 172:65be27845400 22094 #define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
AnnaBridge 172:65be27845400 22095 #define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22096 #define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22097 #define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22098 #define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22099
AnnaBridge 172:65be27845400 22100 #define HRTIM_EEFR2_EE8LTCH_Pos (12U)
AnnaBridge 172:65be27845400 22101 #define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22102 #define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
AnnaBridge 172:65be27845400 22103 #define HRTIM_EEFR2_EE8FLTR_Pos (13U)
AnnaBridge 172:65be27845400 22104 #define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 22105 #define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
AnnaBridge 172:65be27845400 22106 #define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22107 #define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 22108 #define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 22109 #define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22110
AnnaBridge 172:65be27845400 22111 #define HRTIM_EEFR2_EE9LTCH_Pos (18U)
AnnaBridge 172:65be27845400 22112 #define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22113 #define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
AnnaBridge 172:65be27845400 22114 #define HRTIM_EEFR2_EE9FLTR_Pos (19U)
AnnaBridge 172:65be27845400 22115 #define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
AnnaBridge 172:65be27845400 22116 #define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
AnnaBridge 172:65be27845400 22117 #define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22118 #define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22119 #define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22120 #define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22121
AnnaBridge 172:65be27845400 22122 #define HRTIM_EEFR2_EE10LTCH_Pos (24U)
AnnaBridge 172:65be27845400 22123 #define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 22124 #define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
AnnaBridge 172:65be27845400 22125 #define HRTIM_EEFR2_EE10FLTR_Pos (25U)
AnnaBridge 172:65be27845400 22126 #define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
AnnaBridge 172:65be27845400 22127 #define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
AnnaBridge 172:65be27845400 22128 #define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22129 #define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22130 #define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 22131 #define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 22132
AnnaBridge 172:65be27845400 22133 /**** Bit definition for Slave Timer reset register ***************************/
AnnaBridge 172:65be27845400 22134 #define HRTIM_RSTR_UPDATE_Pos (1U)
AnnaBridge 172:65be27845400 22135 #define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22136 #define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
AnnaBridge 172:65be27845400 22137 #define HRTIM_RSTR_CMP2_Pos (2U)
AnnaBridge 172:65be27845400 22138 #define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22139 #define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
AnnaBridge 172:65be27845400 22140 #define HRTIM_RSTR_CMP4_Pos (3U)
AnnaBridge 172:65be27845400 22141 #define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22142 #define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
AnnaBridge 172:65be27845400 22143
AnnaBridge 172:65be27845400 22144 #define HRTIM_RSTR_MSTPER_Pos (4U)
AnnaBridge 172:65be27845400 22145 #define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22146 #define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
AnnaBridge 172:65be27845400 22147 #define HRTIM_RSTR_MSTCMP1_Pos (5U)
AnnaBridge 172:65be27845400 22148 #define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22149 #define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
AnnaBridge 172:65be27845400 22150 #define HRTIM_RSTR_MSTCMP2_Pos (6U)
AnnaBridge 172:65be27845400 22151 #define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22152 #define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
AnnaBridge 172:65be27845400 22153 #define HRTIM_RSTR_MSTCMP3_Pos (7U)
AnnaBridge 172:65be27845400 22154 #define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22155 #define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
AnnaBridge 172:65be27845400 22156 #define HRTIM_RSTR_MSTCMP4_Pos (8U)
AnnaBridge 172:65be27845400 22157 #define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22158 #define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
AnnaBridge 172:65be27845400 22159
AnnaBridge 172:65be27845400 22160 #define HRTIM_RSTR_EXTEVNT1_Pos (9U)
AnnaBridge 172:65be27845400 22161 #define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22162 #define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
AnnaBridge 172:65be27845400 22163 #define HRTIM_RSTR_EXTEVNT2_Pos (10U)
AnnaBridge 172:65be27845400 22164 #define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22165 #define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
AnnaBridge 172:65be27845400 22166 #define HRTIM_RSTR_EXTEVNT3_Pos (11U)
AnnaBridge 172:65be27845400 22167 #define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 22168 #define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
AnnaBridge 172:65be27845400 22169 #define HRTIM_RSTR_EXTEVNT4_Pos (12U)
AnnaBridge 172:65be27845400 22170 #define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22171 #define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
AnnaBridge 172:65be27845400 22172 #define HRTIM_RSTR_EXTEVNT5_Pos (13U)
AnnaBridge 172:65be27845400 22173 #define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22174 #define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
AnnaBridge 172:65be27845400 22175 #define HRTIM_RSTR_EXTEVNT6_Pos (14U)
AnnaBridge 172:65be27845400 22176 #define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 22177 #define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
AnnaBridge 172:65be27845400 22178 #define HRTIM_RSTR_EXTEVNT7_Pos (15U)
AnnaBridge 172:65be27845400 22179 #define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 22180 #define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
AnnaBridge 172:65be27845400 22181 #define HRTIM_RSTR_EXTEVNT8_Pos (16U)
AnnaBridge 172:65be27845400 22182 #define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22183 #define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
AnnaBridge 172:65be27845400 22184 #define HRTIM_RSTR_EXTEVNT9_Pos (17U)
AnnaBridge 172:65be27845400 22185 #define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22186 #define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
AnnaBridge 172:65be27845400 22187 #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
AnnaBridge 172:65be27845400 22188 #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22189 #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
AnnaBridge 172:65be27845400 22190
AnnaBridge 172:65be27845400 22191 #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
AnnaBridge 172:65be27845400 22192 #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22193 #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 172:65be27845400 22194 #define HRTIM_RSTR_TIMBCMP2_Pos (20U)
AnnaBridge 172:65be27845400 22195 #define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22196 #define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 172:65be27845400 22197 #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
AnnaBridge 172:65be27845400 22198 #define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22199 #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
AnnaBridge 172:65be27845400 22200
AnnaBridge 172:65be27845400 22201 #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
AnnaBridge 172:65be27845400 22202 #define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22203 #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 172:65be27845400 22204 #define HRTIM_RSTR_TIMCCMP2_Pos (23U)
AnnaBridge 172:65be27845400 22205 #define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 22206 #define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 172:65be27845400 22207 #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
AnnaBridge 172:65be27845400 22208 #define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 22209 #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
AnnaBridge 172:65be27845400 22210
AnnaBridge 172:65be27845400 22211 #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
AnnaBridge 172:65be27845400 22212 #define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22213 #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 172:65be27845400 22214 #define HRTIM_RSTR_TIMDCMP2_Pos (26U)
AnnaBridge 172:65be27845400 22215 #define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22216 #define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 172:65be27845400 22217 #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
AnnaBridge 172:65be27845400 22218 #define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 22219 #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
AnnaBridge 172:65be27845400 22220
AnnaBridge 172:65be27845400 22221 #define HRTIM_RSTR_TIMECMP1_Pos (28U)
AnnaBridge 172:65be27845400 22222 #define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 22223 #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 172:65be27845400 22224 #define HRTIM_RSTR_TIMECMP2_Pos (29U)
AnnaBridge 172:65be27845400 22225 #define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 22226 #define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 172:65be27845400 22227 #define HRTIM_RSTR_TIMECMP4_Pos (30U)
AnnaBridge 172:65be27845400 22228 #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 22229 #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
AnnaBridge 172:65be27845400 22230
AnnaBridge 172:65be27845400 22231 /**** Bit definition for Slave Timer Chopper register *************************/
AnnaBridge 172:65be27845400 22232 #define HRTIM_CHPR_CARFRQ_Pos (0U)
AnnaBridge 172:65be27845400 22233 #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 22234 #define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
AnnaBridge 172:65be27845400 22235 #define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22236 #define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22237 #define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22238 #define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22239
AnnaBridge 172:65be27845400 22240 #define HRTIM_CHPR_CARDTY_Pos (4U)
AnnaBridge 172:65be27845400 22241 #define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 22242 #define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
AnnaBridge 172:65be27845400 22243 #define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22244 #define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22245 #define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22246
AnnaBridge 172:65be27845400 22247 #define HRTIM_CHPR_STRPW_Pos (7U)
AnnaBridge 172:65be27845400 22248 #define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
AnnaBridge 172:65be27845400 22249 #define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
AnnaBridge 172:65be27845400 22250 #define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22251 #define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22252 #define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22253 #define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22254
AnnaBridge 172:65be27845400 22255 /**** Bit definition for Slave Timer Capture 1 control register ***************/
AnnaBridge 172:65be27845400 22256 #define HRTIM_CPT1CR_SWCPT_Pos (0U)
AnnaBridge 172:65be27845400 22257 #define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22258 #define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
AnnaBridge 172:65be27845400 22259 #define HRTIM_CPT1CR_UPDCPT_Pos (1U)
AnnaBridge 172:65be27845400 22260 #define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22261 #define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
AnnaBridge 172:65be27845400 22262 #define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
AnnaBridge 172:65be27845400 22263 #define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22264 #define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
AnnaBridge 172:65be27845400 22265 #define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
AnnaBridge 172:65be27845400 22266 #define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22267 #define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
AnnaBridge 172:65be27845400 22268 #define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
AnnaBridge 172:65be27845400 22269 #define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22270 #define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
AnnaBridge 172:65be27845400 22271 #define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
AnnaBridge 172:65be27845400 22272 #define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22273 #define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
AnnaBridge 172:65be27845400 22274 #define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
AnnaBridge 172:65be27845400 22275 #define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22276 #define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
AnnaBridge 172:65be27845400 22277 #define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
AnnaBridge 172:65be27845400 22278 #define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22279 #define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
AnnaBridge 172:65be27845400 22280 #define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
AnnaBridge 172:65be27845400 22281 #define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22282 #define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
AnnaBridge 172:65be27845400 22283 #define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
AnnaBridge 172:65be27845400 22284 #define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22285 #define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
AnnaBridge 172:65be27845400 22286 #define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
AnnaBridge 172:65be27845400 22287 #define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22288 #define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
AnnaBridge 172:65be27845400 22289 #define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
AnnaBridge 172:65be27845400 22290 #define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 22291 #define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
AnnaBridge 172:65be27845400 22292
AnnaBridge 172:65be27845400 22293 #define HRTIM_CPT1CR_TA1SET_Pos (12U)
AnnaBridge 172:65be27845400 22294 #define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22295 #define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
AnnaBridge 172:65be27845400 22296 #define HRTIM_CPT1CR_TA1RST_Pos (13U)
AnnaBridge 172:65be27845400 22297 #define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22298 #define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
AnnaBridge 172:65be27845400 22299 #define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
AnnaBridge 172:65be27845400 22300 #define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 22301 #define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 172:65be27845400 22302 #define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
AnnaBridge 172:65be27845400 22303 #define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 22304 #define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 172:65be27845400 22305
AnnaBridge 172:65be27845400 22306 #define HRTIM_CPT1CR_TB1SET_Pos (16U)
AnnaBridge 172:65be27845400 22307 #define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22308 #define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
AnnaBridge 172:65be27845400 22309 #define HRTIM_CPT1CR_TB1RST_Pos (17U)
AnnaBridge 172:65be27845400 22310 #define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22311 #define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
AnnaBridge 172:65be27845400 22312 #define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
AnnaBridge 172:65be27845400 22313 #define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22314 #define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 172:65be27845400 22315 #define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
AnnaBridge 172:65be27845400 22316 #define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22317 #define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 172:65be27845400 22318
AnnaBridge 172:65be27845400 22319 #define HRTIM_CPT1CR_TC1SET_Pos (20U)
AnnaBridge 172:65be27845400 22320 #define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22321 #define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
AnnaBridge 172:65be27845400 22322 #define HRTIM_CPT1CR_TC1RST_Pos (21U)
AnnaBridge 172:65be27845400 22323 #define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22324 #define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
AnnaBridge 172:65be27845400 22325 #define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
AnnaBridge 172:65be27845400 22326 #define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22327 #define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 172:65be27845400 22328 #define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
AnnaBridge 172:65be27845400 22329 #define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 22330 #define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 172:65be27845400 22331
AnnaBridge 172:65be27845400 22332 #define HRTIM_CPT1CR_TD1SET_Pos (24U)
AnnaBridge 172:65be27845400 22333 #define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 22334 #define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
AnnaBridge 172:65be27845400 22335 #define HRTIM_CPT1CR_TD1RST_Pos (25U)
AnnaBridge 172:65be27845400 22336 #define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22337 #define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
AnnaBridge 172:65be27845400 22338 #define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
AnnaBridge 172:65be27845400 22339 #define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22340 #define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 172:65be27845400 22341 #define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
AnnaBridge 172:65be27845400 22342 #define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 22343 #define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 172:65be27845400 22344
AnnaBridge 172:65be27845400 22345 #define HRTIM_CPT1CR_TE1SET_Pos (28U)
AnnaBridge 172:65be27845400 22346 #define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 22347 #define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
AnnaBridge 172:65be27845400 22348 #define HRTIM_CPT1CR_TE1RST_Pos (29U)
AnnaBridge 172:65be27845400 22349 #define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 22350 #define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
AnnaBridge 172:65be27845400 22351 #define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
AnnaBridge 172:65be27845400 22352 #define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 22353 #define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 172:65be27845400 22354 #define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
AnnaBridge 172:65be27845400 22355 #define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 22356 #define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 172:65be27845400 22357
AnnaBridge 172:65be27845400 22358 /**** Bit definition for Slave Timer Capture 2 control register ***************/
AnnaBridge 172:65be27845400 22359 #define HRTIM_CPT2CR_SWCPT_Pos (0U)
AnnaBridge 172:65be27845400 22360 #define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22361 #define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
AnnaBridge 172:65be27845400 22362 #define HRTIM_CPT2CR_UPDCPT_Pos (1U)
AnnaBridge 172:65be27845400 22363 #define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22364 #define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
AnnaBridge 172:65be27845400 22365 #define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
AnnaBridge 172:65be27845400 22366 #define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22367 #define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
AnnaBridge 172:65be27845400 22368 #define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
AnnaBridge 172:65be27845400 22369 #define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22370 #define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
AnnaBridge 172:65be27845400 22371 #define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
AnnaBridge 172:65be27845400 22372 #define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22373 #define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
AnnaBridge 172:65be27845400 22374 #define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
AnnaBridge 172:65be27845400 22375 #define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22376 #define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
AnnaBridge 172:65be27845400 22377 #define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
AnnaBridge 172:65be27845400 22378 #define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22379 #define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
AnnaBridge 172:65be27845400 22380 #define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
AnnaBridge 172:65be27845400 22381 #define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22382 #define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
AnnaBridge 172:65be27845400 22383 #define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
AnnaBridge 172:65be27845400 22384 #define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22385 #define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
AnnaBridge 172:65be27845400 22386 #define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
AnnaBridge 172:65be27845400 22387 #define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22388 #define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
AnnaBridge 172:65be27845400 22389 #define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
AnnaBridge 172:65be27845400 22390 #define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22391 #define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
AnnaBridge 172:65be27845400 22392 #define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
AnnaBridge 172:65be27845400 22393 #define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 22394 #define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
AnnaBridge 172:65be27845400 22395
AnnaBridge 172:65be27845400 22396 #define HRTIM_CPT2CR_TA1SET_Pos (12U)
AnnaBridge 172:65be27845400 22397 #define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22398 #define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
AnnaBridge 172:65be27845400 22399 #define HRTIM_CPT2CR_TA1RST_Pos (13U)
AnnaBridge 172:65be27845400 22400 #define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22401 #define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
AnnaBridge 172:65be27845400 22402 #define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
AnnaBridge 172:65be27845400 22403 #define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 22404 #define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 172:65be27845400 22405 #define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
AnnaBridge 172:65be27845400 22406 #define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 22407 #define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 172:65be27845400 22408
AnnaBridge 172:65be27845400 22409 #define HRTIM_CPT2CR_TB1SET_Pos (16U)
AnnaBridge 172:65be27845400 22410 #define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22411 #define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
AnnaBridge 172:65be27845400 22412 #define HRTIM_CPT2CR_TB1RST_Pos (17U)
AnnaBridge 172:65be27845400 22413 #define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22414 #define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
AnnaBridge 172:65be27845400 22415 #define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
AnnaBridge 172:65be27845400 22416 #define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22417 #define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 172:65be27845400 22418 #define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
AnnaBridge 172:65be27845400 22419 #define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22420 #define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 172:65be27845400 22421
AnnaBridge 172:65be27845400 22422 #define HRTIM_CPT2CR_TC1SET_Pos (20U)
AnnaBridge 172:65be27845400 22423 #define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22424 #define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
AnnaBridge 172:65be27845400 22425 #define HRTIM_CPT2CR_TC1RST_Pos (21U)
AnnaBridge 172:65be27845400 22426 #define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22427 #define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
AnnaBridge 172:65be27845400 22428 #define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
AnnaBridge 172:65be27845400 22429 #define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22430 #define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 172:65be27845400 22431 #define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
AnnaBridge 172:65be27845400 22432 #define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 22433 #define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 172:65be27845400 22434
AnnaBridge 172:65be27845400 22435 #define HRTIM_CPT2CR_TD1SET_Pos (24U)
AnnaBridge 172:65be27845400 22436 #define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 22437 #define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
AnnaBridge 172:65be27845400 22438 #define HRTIM_CPT2CR_TD1RST_Pos (25U)
AnnaBridge 172:65be27845400 22439 #define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22440 #define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
AnnaBridge 172:65be27845400 22441 #define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
AnnaBridge 172:65be27845400 22442 #define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22443 #define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 172:65be27845400 22444 #define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
AnnaBridge 172:65be27845400 22445 #define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 22446 #define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 172:65be27845400 22447
AnnaBridge 172:65be27845400 22448 #define HRTIM_CPT2CR_TE1SET_Pos (28U)
AnnaBridge 172:65be27845400 22449 #define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 22450 #define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
AnnaBridge 172:65be27845400 22451 #define HRTIM_CPT2CR_TE1RST_Pos (29U)
AnnaBridge 172:65be27845400 22452 #define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 22453 #define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
AnnaBridge 172:65be27845400 22454 #define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
AnnaBridge 172:65be27845400 22455 #define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 22456 #define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 172:65be27845400 22457 #define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
AnnaBridge 172:65be27845400 22458 #define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 22459 #define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 172:65be27845400 22460
AnnaBridge 172:65be27845400 22461 /**** Bit definition for Slave Timer Output register **************************/
AnnaBridge 172:65be27845400 22462 #define HRTIM_OUTR_POL1_Pos (1U)
AnnaBridge 172:65be27845400 22463 #define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22464 #define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
AnnaBridge 172:65be27845400 22465 #define HRTIM_OUTR_IDLM1_Pos (2U)
AnnaBridge 172:65be27845400 22466 #define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22467 #define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
AnnaBridge 172:65be27845400 22468 #define HRTIM_OUTR_IDLES1_Pos (3U)
AnnaBridge 172:65be27845400 22469 #define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22470 #define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
AnnaBridge 172:65be27845400 22471 #define HRTIM_OUTR_FAULT1_Pos (4U)
AnnaBridge 172:65be27845400 22472 #define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
AnnaBridge 172:65be27845400 22473 #define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
AnnaBridge 172:65be27845400 22474 #define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22475 #define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22476 #define HRTIM_OUTR_CHP1_Pos (6U)
AnnaBridge 172:65be27845400 22477 #define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22478 #define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
AnnaBridge 172:65be27845400 22479 #define HRTIM_OUTR_DIDL1_Pos (7U)
AnnaBridge 172:65be27845400 22480 #define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22481 #define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
AnnaBridge 172:65be27845400 22482
AnnaBridge 172:65be27845400 22483 #define HRTIM_OUTR_DTEN_Pos (8U)
AnnaBridge 172:65be27845400 22484 #define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22485 #define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
AnnaBridge 172:65be27845400 22486 #define HRTIM_OUTR_DLYPRTEN_Pos (9U)
AnnaBridge 172:65be27845400 22487 #define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22488 #define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
AnnaBridge 172:65be27845400 22489 #define HRTIM_OUTR_DLYPRT_Pos (10U)
AnnaBridge 172:65be27845400 22490 #define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
AnnaBridge 172:65be27845400 22491 #define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
AnnaBridge 172:65be27845400 22492 #define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22493 #define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 22494 #define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22495
AnnaBridge 172:65be27845400 22496 #define HRTIM_OUTR_POL2_Pos (17U)
AnnaBridge 172:65be27845400 22497 #define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22498 #define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
AnnaBridge 172:65be27845400 22499 #define HRTIM_OUTR_IDLM2_Pos (18U)
AnnaBridge 172:65be27845400 22500 #define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22501 #define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
AnnaBridge 172:65be27845400 22502 #define HRTIM_OUTR_IDLES2_Pos (19U)
AnnaBridge 172:65be27845400 22503 #define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22504 #define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
AnnaBridge 172:65be27845400 22505 #define HRTIM_OUTR_FAULT2_Pos (20U)
AnnaBridge 172:65be27845400 22506 #define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 22507 #define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
AnnaBridge 172:65be27845400 22508 #define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22509 #define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22510 #define HRTIM_OUTR_CHP2_Pos (22U)
AnnaBridge 172:65be27845400 22511 #define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22512 #define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
AnnaBridge 172:65be27845400 22513 #define HRTIM_OUTR_DIDL2_Pos (23U)
AnnaBridge 172:65be27845400 22514 #define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 22515 #define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
AnnaBridge 172:65be27845400 22516
AnnaBridge 172:65be27845400 22517 /**** Bit definition for Slave Timer Fault register ***************************/
AnnaBridge 172:65be27845400 22518 #define HRTIM_FLTR_FLT1EN_Pos (0U)
AnnaBridge 172:65be27845400 22519 #define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22520 #define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
AnnaBridge 172:65be27845400 22521 #define HRTIM_FLTR_FLT2EN_Pos (1U)
AnnaBridge 172:65be27845400 22522 #define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22523 #define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
AnnaBridge 172:65be27845400 22524 #define HRTIM_FLTR_FLT3EN_Pos (2U)
AnnaBridge 172:65be27845400 22525 #define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22526 #define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
AnnaBridge 172:65be27845400 22527 #define HRTIM_FLTR_FLT4EN_Pos (3U)
AnnaBridge 172:65be27845400 22528 #define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22529 #define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
AnnaBridge 172:65be27845400 22530 #define HRTIM_FLTR_FLT5EN_Pos (4U)
AnnaBridge 172:65be27845400 22531 #define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22532 #define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
AnnaBridge 172:65be27845400 22533 #define HRTIM_FLTR_FLTLCK_Pos (31U)
AnnaBridge 172:65be27845400 22534 #define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 22535 #define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
AnnaBridge 172:65be27845400 22536
AnnaBridge 172:65be27845400 22537 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
AnnaBridge 172:65be27845400 22538 #define HRTIM_CR1_MUDIS_Pos (0U)
AnnaBridge 172:65be27845400 22539 #define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22540 #define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
AnnaBridge 172:65be27845400 22541 #define HRTIM_CR1_TAUDIS_Pos (1U)
AnnaBridge 172:65be27845400 22542 #define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22543 #define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
AnnaBridge 172:65be27845400 22544 #define HRTIM_CR1_TBUDIS_Pos (2U)
AnnaBridge 172:65be27845400 22545 #define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22546 #define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
AnnaBridge 172:65be27845400 22547 #define HRTIM_CR1_TCUDIS_Pos (3U)
AnnaBridge 172:65be27845400 22548 #define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22549 #define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
AnnaBridge 172:65be27845400 22550 #define HRTIM_CR1_TDUDIS_Pos (4U)
AnnaBridge 172:65be27845400 22551 #define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22552 #define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
AnnaBridge 172:65be27845400 22553 #define HRTIM_CR1_TEUDIS_Pos (5U)
AnnaBridge 172:65be27845400 22554 #define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22555 #define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
AnnaBridge 172:65be27845400 22556 #define HRTIM_CR1_ADC1USRC_Pos (16U)
AnnaBridge 172:65be27845400 22557 #define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
AnnaBridge 172:65be27845400 22558 #define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
AnnaBridge 172:65be27845400 22559 #define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22560 #define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22561 #define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22562 #define HRTIM_CR1_ADC2USRC_Pos (19U)
AnnaBridge 172:65be27845400 22563 #define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
AnnaBridge 172:65be27845400 22564 #define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
AnnaBridge 172:65be27845400 22565 #define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22566 #define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22567 #define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22568 #define HRTIM_CR1_ADC3USRC_Pos (22U)
AnnaBridge 172:65be27845400 22569 #define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
AnnaBridge 172:65be27845400 22570 #define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
AnnaBridge 172:65be27845400 22571 #define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22572 #define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 22573 #define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 22574 #define HRTIM_CR1_ADC4USRC_Pos (25U)
AnnaBridge 172:65be27845400 22575 #define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
AnnaBridge 172:65be27845400 22576 #define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
AnnaBridge 172:65be27845400 22577 #define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22578 #define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22579 #define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
AnnaBridge 172:65be27845400 22580
AnnaBridge 172:65be27845400 22581 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
AnnaBridge 172:65be27845400 22582 #define HRTIM_CR2_MSWU_Pos (0U)
AnnaBridge 172:65be27845400 22583 #define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22584 #define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
AnnaBridge 172:65be27845400 22585 #define HRTIM_CR2_TASWU_Pos (1U)
AnnaBridge 172:65be27845400 22586 #define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22587 #define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
AnnaBridge 172:65be27845400 22588 #define HRTIM_CR2_TBSWU_Pos (2U)
AnnaBridge 172:65be27845400 22589 #define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22590 #define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
AnnaBridge 172:65be27845400 22591 #define HRTIM_CR2_TCSWU_Pos (3U)
AnnaBridge 172:65be27845400 22592 #define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22593 #define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
AnnaBridge 172:65be27845400 22594 #define HRTIM_CR2_TDSWU_Pos (4U)
AnnaBridge 172:65be27845400 22595 #define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22596 #define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
AnnaBridge 172:65be27845400 22597 #define HRTIM_CR2_TESWU_Pos (5U)
AnnaBridge 172:65be27845400 22598 #define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22599 #define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
AnnaBridge 172:65be27845400 22600 #define HRTIM_CR2_MRST_Pos (8U)
AnnaBridge 172:65be27845400 22601 #define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22602 #define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
AnnaBridge 172:65be27845400 22603 #define HRTIM_CR2_TARST_Pos (9U)
AnnaBridge 172:65be27845400 22604 #define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22605 #define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
AnnaBridge 172:65be27845400 22606 #define HRTIM_CR2_TBRST_Pos (10U)
AnnaBridge 172:65be27845400 22607 #define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22608 #define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
AnnaBridge 172:65be27845400 22609 #define HRTIM_CR2_TCRST_Pos (11U)
AnnaBridge 172:65be27845400 22610 #define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 22611 #define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
AnnaBridge 172:65be27845400 22612 #define HRTIM_CR2_TDRST_Pos (12U)
AnnaBridge 172:65be27845400 22613 #define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22614 #define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
AnnaBridge 172:65be27845400 22615 #define HRTIM_CR2_TERST_Pos (13U)
AnnaBridge 172:65be27845400 22616 #define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22617 #define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
AnnaBridge 172:65be27845400 22618
AnnaBridge 172:65be27845400 22619 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
AnnaBridge 172:65be27845400 22620 #define HRTIM_ISR_FLT1_Pos (0U)
AnnaBridge 172:65be27845400 22621 #define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22622 #define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
AnnaBridge 172:65be27845400 22623 #define HRTIM_ISR_FLT2_Pos (1U)
AnnaBridge 172:65be27845400 22624 #define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22625 #define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
AnnaBridge 172:65be27845400 22626 #define HRTIM_ISR_FLT3_Pos (2U)
AnnaBridge 172:65be27845400 22627 #define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22628 #define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
AnnaBridge 172:65be27845400 22629 #define HRTIM_ISR_FLT4_Pos (3U)
AnnaBridge 172:65be27845400 22630 #define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22631 #define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
AnnaBridge 172:65be27845400 22632 #define HRTIM_ISR_FLT5_Pos (4U)
AnnaBridge 172:65be27845400 22633 #define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22634 #define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
AnnaBridge 172:65be27845400 22635 #define HRTIM_ISR_SYSFLT_Pos (5U)
AnnaBridge 172:65be27845400 22636 #define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22637 #define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
AnnaBridge 172:65be27845400 22638 #define HRTIM_ISR_BMPER_Pos (17U)
AnnaBridge 172:65be27845400 22639 #define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22640 #define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
AnnaBridge 172:65be27845400 22641
AnnaBridge 172:65be27845400 22642 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
AnnaBridge 172:65be27845400 22643 #define HRTIM_ICR_FLT1C_Pos (0U)
AnnaBridge 172:65be27845400 22644 #define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22645 #define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
AnnaBridge 172:65be27845400 22646 #define HRTIM_ICR_FLT2C_Pos (1U)
AnnaBridge 172:65be27845400 22647 #define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22648 #define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
AnnaBridge 172:65be27845400 22649 #define HRTIM_ICR_FLT3C_Pos (2U)
AnnaBridge 172:65be27845400 22650 #define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22651 #define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
AnnaBridge 172:65be27845400 22652 #define HRTIM_ICR_FLT4C_Pos (3U)
AnnaBridge 172:65be27845400 22653 #define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22654 #define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
AnnaBridge 172:65be27845400 22655 #define HRTIM_ICR_FLT5C_Pos (4U)
AnnaBridge 172:65be27845400 22656 #define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22657 #define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
AnnaBridge 172:65be27845400 22658 #define HRTIM_ICR_SYSFLTC_Pos (5U)
AnnaBridge 172:65be27845400 22659 #define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22660 #define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
AnnaBridge 172:65be27845400 22661 #define HRTIM_ICR_BMPERC_Pos (17U)
AnnaBridge 172:65be27845400 22662 #define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22663 #define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
AnnaBridge 172:65be27845400 22664
AnnaBridge 172:65be27845400 22665 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
AnnaBridge 172:65be27845400 22666 #define HRTIM_IER_FLT1_Pos (0U)
AnnaBridge 172:65be27845400 22667 #define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22668 #define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
AnnaBridge 172:65be27845400 22669 #define HRTIM_IER_FLT2_Pos (1U)
AnnaBridge 172:65be27845400 22670 #define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22671 #define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
AnnaBridge 172:65be27845400 22672 #define HRTIM_IER_FLT3_Pos (2U)
AnnaBridge 172:65be27845400 22673 #define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22674 #define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
AnnaBridge 172:65be27845400 22675 #define HRTIM_IER_FLT4_Pos (3U)
AnnaBridge 172:65be27845400 22676 #define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22677 #define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
AnnaBridge 172:65be27845400 22678 #define HRTIM_IER_FLT5_Pos (4U)
AnnaBridge 172:65be27845400 22679 #define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22680 #define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
AnnaBridge 172:65be27845400 22681 #define HRTIM_IER_SYSFLT_Pos (5U)
AnnaBridge 172:65be27845400 22682 #define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22683 #define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
AnnaBridge 172:65be27845400 22684 #define HRTIM_IER_BMPER_Pos (17U)
AnnaBridge 172:65be27845400 22685 #define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22686 #define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
AnnaBridge 172:65be27845400 22687
AnnaBridge 172:65be27845400 22688 /**** Bit definition for Common HRTIM Timer output enable register ************/
AnnaBridge 172:65be27845400 22689 #define HRTIM_OENR_TA1OEN_Pos (0U)
AnnaBridge 172:65be27845400 22690 #define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22691 #define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
AnnaBridge 172:65be27845400 22692 #define HRTIM_OENR_TA2OEN_Pos (1U)
AnnaBridge 172:65be27845400 22693 #define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22694 #define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
AnnaBridge 172:65be27845400 22695 #define HRTIM_OENR_TB1OEN_Pos (2U)
AnnaBridge 172:65be27845400 22696 #define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22697 #define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
AnnaBridge 172:65be27845400 22698 #define HRTIM_OENR_TB2OEN_Pos (3U)
AnnaBridge 172:65be27845400 22699 #define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22700 #define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
AnnaBridge 172:65be27845400 22701 #define HRTIM_OENR_TC1OEN_Pos (4U)
AnnaBridge 172:65be27845400 22702 #define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22703 #define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
AnnaBridge 172:65be27845400 22704 #define HRTIM_OENR_TC2OEN_Pos (5U)
AnnaBridge 172:65be27845400 22705 #define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22706 #define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
AnnaBridge 172:65be27845400 22707 #define HRTIM_OENR_TD1OEN_Pos (6U)
AnnaBridge 172:65be27845400 22708 #define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22709 #define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
AnnaBridge 172:65be27845400 22710 #define HRTIM_OENR_TD2OEN_Pos (7U)
AnnaBridge 172:65be27845400 22711 #define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22712 #define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
AnnaBridge 172:65be27845400 22713 #define HRTIM_OENR_TE1OEN_Pos (8U)
AnnaBridge 172:65be27845400 22714 #define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22715 #define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
AnnaBridge 172:65be27845400 22716 #define HRTIM_OENR_TE2OEN_Pos (9U)
AnnaBridge 172:65be27845400 22717 #define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22718 #define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
AnnaBridge 172:65be27845400 22719
AnnaBridge 172:65be27845400 22720 /**** Bit definition for Common HRTIM Timer output disable register ***********/
AnnaBridge 172:65be27845400 22721 #define HRTIM_ODISR_TA1ODIS_Pos (0U)
AnnaBridge 172:65be27845400 22722 #define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22723 #define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
AnnaBridge 172:65be27845400 22724 #define HRTIM_ODISR_TA2ODIS_Pos (1U)
AnnaBridge 172:65be27845400 22725 #define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22726 #define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
AnnaBridge 172:65be27845400 22727 #define HRTIM_ODISR_TB1ODIS_Pos (2U)
AnnaBridge 172:65be27845400 22728 #define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22729 #define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
AnnaBridge 172:65be27845400 22730 #define HRTIM_ODISR_TB2ODIS_Pos (3U)
AnnaBridge 172:65be27845400 22731 #define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22732 #define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
AnnaBridge 172:65be27845400 22733 #define HRTIM_ODISR_TC1ODIS_Pos (4U)
AnnaBridge 172:65be27845400 22734 #define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22735 #define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
AnnaBridge 172:65be27845400 22736 #define HRTIM_ODISR_TC2ODIS_Pos (5U)
AnnaBridge 172:65be27845400 22737 #define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22738 #define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
AnnaBridge 172:65be27845400 22739 #define HRTIM_ODISR_TD1ODIS_Pos (6U)
AnnaBridge 172:65be27845400 22740 #define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22741 #define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
AnnaBridge 172:65be27845400 22742 #define HRTIM_ODISR_TD2ODIS_Pos (7U)
AnnaBridge 172:65be27845400 22743 #define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22744 #define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
AnnaBridge 172:65be27845400 22745 #define HRTIM_ODISR_TE1ODIS_Pos (8U)
AnnaBridge 172:65be27845400 22746 #define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22747 #define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
AnnaBridge 172:65be27845400 22748 #define HRTIM_ODISR_TE2ODIS_Pos (9U)
AnnaBridge 172:65be27845400 22749 #define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22750 #define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
AnnaBridge 172:65be27845400 22751
AnnaBridge 172:65be27845400 22752 /**** Bit definition for Common HRTIM Timer output disable status register *****/
AnnaBridge 172:65be27845400 22753 #define HRTIM_ODSR_TA1ODS_Pos (0U)
AnnaBridge 172:65be27845400 22754 #define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22755 #define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
AnnaBridge 172:65be27845400 22756 #define HRTIM_ODSR_TA2ODS_Pos (1U)
AnnaBridge 172:65be27845400 22757 #define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22758 #define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
AnnaBridge 172:65be27845400 22759 #define HRTIM_ODSR_TB1ODS_Pos (2U)
AnnaBridge 172:65be27845400 22760 #define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22761 #define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
AnnaBridge 172:65be27845400 22762 #define HRTIM_ODSR_TB2ODS_Pos (3U)
AnnaBridge 172:65be27845400 22763 #define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22764 #define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
AnnaBridge 172:65be27845400 22765 #define HRTIM_ODSR_TC1ODS_Pos (4U)
AnnaBridge 172:65be27845400 22766 #define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22767 #define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
AnnaBridge 172:65be27845400 22768 #define HRTIM_ODSR_TC2ODS_Pos (5U)
AnnaBridge 172:65be27845400 22769 #define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22770 #define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
AnnaBridge 172:65be27845400 22771 #define HRTIM_ODSR_TD1ODS_Pos (6U)
AnnaBridge 172:65be27845400 22772 #define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22773 #define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
AnnaBridge 172:65be27845400 22774 #define HRTIM_ODSR_TD2ODS_Pos (7U)
AnnaBridge 172:65be27845400 22775 #define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22776 #define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
AnnaBridge 172:65be27845400 22777 #define HRTIM_ODSR_TE1ODS_Pos (8U)
AnnaBridge 172:65be27845400 22778 #define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22779 #define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
AnnaBridge 172:65be27845400 22780 #define HRTIM_ODSR_TE2ODS_Pos (9U)
AnnaBridge 172:65be27845400 22781 #define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22782 #define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
AnnaBridge 172:65be27845400 22783
AnnaBridge 172:65be27845400 22784 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
AnnaBridge 172:65be27845400 22785 #define HRTIM_BMCR_BME_Pos (0U)
AnnaBridge 172:65be27845400 22786 #define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22787 #define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
AnnaBridge 172:65be27845400 22788 #define HRTIM_BMCR_BMOM_Pos (1U)
AnnaBridge 172:65be27845400 22789 #define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22790 #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
AnnaBridge 172:65be27845400 22791 #define HRTIM_BMCR_BMCLK_Pos (2U)
AnnaBridge 172:65be27845400 22792 #define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
AnnaBridge 172:65be27845400 22793 #define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
AnnaBridge 172:65be27845400 22794 #define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22795 #define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22796 #define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22797 #define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22798 #define HRTIM_BMCR_BMPRSC_Pos (6U)
AnnaBridge 172:65be27845400 22799 #define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
AnnaBridge 172:65be27845400 22800 #define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
AnnaBridge 172:65be27845400 22801 #define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22802 #define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22803 #define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22804 #define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22805 #define HRTIM_BMCR_BMPREN_Pos (10U)
AnnaBridge 172:65be27845400 22806 #define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22807 #define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
AnnaBridge 172:65be27845400 22808 #define HRTIM_BMCR_MTBM_Pos (16U)
AnnaBridge 172:65be27845400 22809 #define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22810 #define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
AnnaBridge 172:65be27845400 22811 #define HRTIM_BMCR_TABM_Pos (17U)
AnnaBridge 172:65be27845400 22812 #define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22813 #define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
AnnaBridge 172:65be27845400 22814 #define HRTIM_BMCR_TBBM_Pos (18U)
AnnaBridge 172:65be27845400 22815 #define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22816 #define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
AnnaBridge 172:65be27845400 22817 #define HRTIM_BMCR_TCBM_Pos (19U)
AnnaBridge 172:65be27845400 22818 #define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22819 #define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
AnnaBridge 172:65be27845400 22820 #define HRTIM_BMCR_TDBM_Pos (20U)
AnnaBridge 172:65be27845400 22821 #define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22822 #define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
AnnaBridge 172:65be27845400 22823 #define HRTIM_BMCR_TEBM_Pos (21U)
AnnaBridge 172:65be27845400 22824 #define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22825 #define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
AnnaBridge 172:65be27845400 22826 #define HRTIM_BMCR_BMSTAT_Pos (31U)
AnnaBridge 172:65be27845400 22827 #define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 22828 #define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
AnnaBridge 172:65be27845400 22829
AnnaBridge 172:65be27845400 22830 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
AnnaBridge 172:65be27845400 22831 #define HRTIM_BMTRGR_SW_Pos (0U)
AnnaBridge 172:65be27845400 22832 #define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22833 #define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
AnnaBridge 172:65be27845400 22834 #define HRTIM_BMTRGR_MSTRST_Pos (1U)
AnnaBridge 172:65be27845400 22835 #define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22836 #define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
AnnaBridge 172:65be27845400 22837 #define HRTIM_BMTRGR_MSTREP_Pos (2U)
AnnaBridge 172:65be27845400 22838 #define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22839 #define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
AnnaBridge 172:65be27845400 22840 #define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
AnnaBridge 172:65be27845400 22841 #define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22842 #define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
AnnaBridge 172:65be27845400 22843 #define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
AnnaBridge 172:65be27845400 22844 #define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22845 #define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
AnnaBridge 172:65be27845400 22846 #define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
AnnaBridge 172:65be27845400 22847 #define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22848 #define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
AnnaBridge 172:65be27845400 22849 #define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
AnnaBridge 172:65be27845400 22850 #define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22851 #define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
AnnaBridge 172:65be27845400 22852 #define HRTIM_BMTRGR_TARST_Pos (7U)
AnnaBridge 172:65be27845400 22853 #define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22854 #define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
AnnaBridge 172:65be27845400 22855 #define HRTIM_BMTRGR_TAREP_Pos (8U)
AnnaBridge 172:65be27845400 22856 #define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22857 #define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
AnnaBridge 172:65be27845400 22858 #define HRTIM_BMTRGR_TACMP1_Pos (9U)
AnnaBridge 172:65be27845400 22859 #define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22860 #define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
AnnaBridge 172:65be27845400 22861 #define HRTIM_BMTRGR_TACMP2_Pos (10U)
AnnaBridge 172:65be27845400 22862 #define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22863 #define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
AnnaBridge 172:65be27845400 22864 #define HRTIM_BMTRGR_TBRST_Pos (11U)
AnnaBridge 172:65be27845400 22865 #define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 22866 #define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
AnnaBridge 172:65be27845400 22867 #define HRTIM_BMTRGR_TBREP_Pos (12U)
AnnaBridge 172:65be27845400 22868 #define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22869 #define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
AnnaBridge 172:65be27845400 22870 #define HRTIM_BMTRGR_TBCMP1_Pos (13U)
AnnaBridge 172:65be27845400 22871 #define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22872 #define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
AnnaBridge 172:65be27845400 22873 #define HRTIM_BMTRGR_TBCMP2_Pos (14U)
AnnaBridge 172:65be27845400 22874 #define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 22875 #define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
AnnaBridge 172:65be27845400 22876 #define HRTIM_BMTRGR_TCRST_Pos (15U)
AnnaBridge 172:65be27845400 22877 #define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 22878 #define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
AnnaBridge 172:65be27845400 22879 #define HRTIM_BMTRGR_TCREP_Pos (16U)
AnnaBridge 172:65be27845400 22880 #define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22881 #define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
AnnaBridge 172:65be27845400 22882 #define HRTIM_BMTRGR_TCCMP1_Pos (17U)
AnnaBridge 172:65be27845400 22883 #define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22884 #define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
AnnaBridge 172:65be27845400 22885 #define HRTIM_BMTRGR_TCCMP2_Pos (18U)
AnnaBridge 172:65be27845400 22886 #define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22887 #define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
AnnaBridge 172:65be27845400 22888 #define HRTIM_BMTRGR_TDRST_Pos (19U)
AnnaBridge 172:65be27845400 22889 #define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22890 #define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
AnnaBridge 172:65be27845400 22891 #define HRTIM_BMTRGR_TDREP_Pos (20U)
AnnaBridge 172:65be27845400 22892 #define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22893 #define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
AnnaBridge 172:65be27845400 22894 #define HRTIM_BMTRGR_TDCMP1_Pos (21U)
AnnaBridge 172:65be27845400 22895 #define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 22896 #define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
AnnaBridge 172:65be27845400 22897 #define HRTIM_BMTRGR_TDCMP2_Pos (22U)
AnnaBridge 172:65be27845400 22898 #define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 22899 #define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
AnnaBridge 172:65be27845400 22900 #define HRTIM_BMTRGR_TERST_Pos (23U)
AnnaBridge 172:65be27845400 22901 #define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 22902 #define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
AnnaBridge 172:65be27845400 22903 #define HRTIM_BMTRGR_TEREP_Pos (24U)
AnnaBridge 172:65be27845400 22904 #define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 22905 #define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
AnnaBridge 172:65be27845400 22906 #define HRTIM_BMTRGR_TECMP1_Pos (25U)
AnnaBridge 172:65be27845400 22907 #define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 22908 #define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
AnnaBridge 172:65be27845400 22909 #define HRTIM_BMTRGR_TECMP2_Pos (26U)
AnnaBridge 172:65be27845400 22910 #define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 22911 #define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
AnnaBridge 172:65be27845400 22912 #define HRTIM_BMTRGR_TAEEV7_Pos (27U)
AnnaBridge 172:65be27845400 22913 #define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 22914 #define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
AnnaBridge 172:65be27845400 22915 #define HRTIM_BMTRGR_TDEEV8_Pos (28U)
AnnaBridge 172:65be27845400 22916 #define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 22917 #define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
AnnaBridge 172:65be27845400 22918 #define HRTIM_BMTRGR_EEV7_Pos (29U)
AnnaBridge 172:65be27845400 22919 #define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 22920 #define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
AnnaBridge 172:65be27845400 22921 #define HRTIM_BMTRGR_EEV8_Pos (30U)
AnnaBridge 172:65be27845400 22922 #define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 22923 #define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
AnnaBridge 172:65be27845400 22924 #define HRTIM_BMTRGR_OCHPEV_Pos (31U)
AnnaBridge 172:65be27845400 22925 #define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 22926 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
AnnaBridge 172:65be27845400 22927
AnnaBridge 172:65be27845400 22928 /******************* Bit definition for HRTIM_BMCMPR register ***************/
AnnaBridge 172:65be27845400 22929 #define HRTIM_BMCMPR_BMCMPR_Pos (0U)
AnnaBridge 172:65be27845400 22930 #define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 22931 #define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
AnnaBridge 172:65be27845400 22932
AnnaBridge 172:65be27845400 22933 /******************* Bit definition for HRTIM_BMPER register ****************/
AnnaBridge 172:65be27845400 22934 #define HRTIM_BMPER_BMPER_Pos (0U)
AnnaBridge 172:65be27845400 22935 #define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 22936 #define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
AnnaBridge 172:65be27845400 22937
AnnaBridge 172:65be27845400 22938 /******************* Bit definition for HRTIM_EECR1 register ****************/
AnnaBridge 172:65be27845400 22939 #define HRTIM_EECR1_EE1SRC_Pos (0U)
AnnaBridge 172:65be27845400 22940 #define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 22941 #define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
AnnaBridge 172:65be27845400 22942 #define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 22943 #define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 22944 #define HRTIM_EECR1_EE1POL_Pos (2U)
AnnaBridge 172:65be27845400 22945 #define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 22946 #define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
AnnaBridge 172:65be27845400 22947 #define HRTIM_EECR1_EE1SNS_Pos (3U)
AnnaBridge 172:65be27845400 22948 #define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 22949 #define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
AnnaBridge 172:65be27845400 22950 #define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 22951 #define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 22952 #define HRTIM_EECR1_EE1FAST_Pos (5U)
AnnaBridge 172:65be27845400 22953 #define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 22954 #define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
AnnaBridge 172:65be27845400 22955
AnnaBridge 172:65be27845400 22956 #define HRTIM_EECR1_EE2SRC_Pos (6U)
AnnaBridge 172:65be27845400 22957 #define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 22958 #define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
AnnaBridge 172:65be27845400 22959 #define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 22960 #define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 22961 #define HRTIM_EECR1_EE2POL_Pos (8U)
AnnaBridge 172:65be27845400 22962 #define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 22963 #define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
AnnaBridge 172:65be27845400 22964 #define HRTIM_EECR1_EE2SNS_Pos (9U)
AnnaBridge 172:65be27845400 22965 #define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
AnnaBridge 172:65be27845400 22966 #define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
AnnaBridge 172:65be27845400 22967 #define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 22968 #define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 22969 #define HRTIM_EECR1_EE2FAST_Pos (11U)
AnnaBridge 172:65be27845400 22970 #define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 22971 #define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
AnnaBridge 172:65be27845400 22972
AnnaBridge 172:65be27845400 22973 #define HRTIM_EECR1_EE3SRC_Pos (12U)
AnnaBridge 172:65be27845400 22974 #define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 22975 #define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
AnnaBridge 172:65be27845400 22976 #define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 22977 #define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 22978 #define HRTIM_EECR1_EE3POL_Pos (14U)
AnnaBridge 172:65be27845400 22979 #define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 22980 #define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
AnnaBridge 172:65be27845400 22981 #define HRTIM_EECR1_EE3SNS_Pos (15U)
AnnaBridge 172:65be27845400 22982 #define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
AnnaBridge 172:65be27845400 22983 #define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
AnnaBridge 172:65be27845400 22984 #define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 22985 #define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 22986 #define HRTIM_EECR1_EE3FAST_Pos (17U)
AnnaBridge 172:65be27845400 22987 #define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 22988 #define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
AnnaBridge 172:65be27845400 22989
AnnaBridge 172:65be27845400 22990 #define HRTIM_EECR1_EE4SRC_Pos (18U)
AnnaBridge 172:65be27845400 22991 #define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 22992 #define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
AnnaBridge 172:65be27845400 22993 #define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 22994 #define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 22995 #define HRTIM_EECR1_EE4POL_Pos (20U)
AnnaBridge 172:65be27845400 22996 #define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 22997 #define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
AnnaBridge 172:65be27845400 22998 #define HRTIM_EECR1_EE4SNS_Pos (21U)
AnnaBridge 172:65be27845400 22999 #define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 23000 #define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
AnnaBridge 172:65be27845400 23001 #define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23002 #define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 23003 #define HRTIM_EECR1_EE4FAST_Pos (23U)
AnnaBridge 172:65be27845400 23004 #define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 23005 #define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
AnnaBridge 172:65be27845400 23006
AnnaBridge 172:65be27845400 23007 #define HRTIM_EECR1_EE5SRC_Pos (24U)
AnnaBridge 172:65be27845400 23008 #define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 23009 #define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
AnnaBridge 172:65be27845400 23010 #define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23011 #define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23012 #define HRTIM_EECR1_EE5POL_Pos (26U)
AnnaBridge 172:65be27845400 23013 #define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23014 #define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
AnnaBridge 172:65be27845400 23015 #define HRTIM_EECR1_EE5SNS_Pos (27U)
AnnaBridge 172:65be27845400 23016 #define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
AnnaBridge 172:65be27845400 23017 #define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
AnnaBridge 172:65be27845400 23018 #define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23019 #define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 23020 #define HRTIM_EECR1_EE5FAST_Pos (29U)
AnnaBridge 172:65be27845400 23021 #define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 23022 #define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
AnnaBridge 172:65be27845400 23023
AnnaBridge 172:65be27845400 23024 /******************* Bit definition for HRTIM_EECR2 register ****************/
AnnaBridge 172:65be27845400 23025 #define HRTIM_EECR2_EE6SRC_Pos (0U)
AnnaBridge 172:65be27845400 23026 #define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 23027 #define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
AnnaBridge 172:65be27845400 23028 #define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23029 #define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23030 #define HRTIM_EECR2_EE6POL_Pos (2U)
AnnaBridge 172:65be27845400 23031 #define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23032 #define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
AnnaBridge 172:65be27845400 23033 #define HRTIM_EECR2_EE6SNS_Pos (3U)
AnnaBridge 172:65be27845400 23034 #define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
AnnaBridge 172:65be27845400 23035 #define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
AnnaBridge 172:65be27845400 23036 #define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23037 #define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23038
AnnaBridge 172:65be27845400 23039 #define HRTIM_EECR2_EE7SRC_Pos (6U)
AnnaBridge 172:65be27845400 23040 #define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
AnnaBridge 172:65be27845400 23041 #define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
AnnaBridge 172:65be27845400 23042 #define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23043 #define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23044 #define HRTIM_EECR2_EE7POL_Pos (8U)
AnnaBridge 172:65be27845400 23045 #define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23046 #define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
AnnaBridge 172:65be27845400 23047 #define HRTIM_EECR2_EE7SNS_Pos (9U)
AnnaBridge 172:65be27845400 23048 #define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
AnnaBridge 172:65be27845400 23049 #define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
AnnaBridge 172:65be27845400 23050 #define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23051 #define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23052
AnnaBridge 172:65be27845400 23053 #define HRTIM_EECR2_EE8SRC_Pos (12U)
AnnaBridge 172:65be27845400 23054 #define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
AnnaBridge 172:65be27845400 23055 #define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
AnnaBridge 172:65be27845400 23056 #define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23057 #define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23058 #define HRTIM_EECR2_EE8POL_Pos (14U)
AnnaBridge 172:65be27845400 23059 #define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23060 #define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
AnnaBridge 172:65be27845400 23061 #define HRTIM_EECR2_EE8SNS_Pos (15U)
AnnaBridge 172:65be27845400 23062 #define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
AnnaBridge 172:65be27845400 23063 #define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
AnnaBridge 172:65be27845400 23064 #define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23065 #define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23066
AnnaBridge 172:65be27845400 23067 #define HRTIM_EECR2_EE9SRC_Pos (18U)
AnnaBridge 172:65be27845400 23068 #define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 23069 #define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
AnnaBridge 172:65be27845400 23070 #define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23071 #define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23072 #define HRTIM_EECR2_EE9POL_Pos (20U)
AnnaBridge 172:65be27845400 23073 #define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23074 #define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
AnnaBridge 172:65be27845400 23075 #define HRTIM_EECR2_EE9SNS_Pos (21U)
AnnaBridge 172:65be27845400 23076 #define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
AnnaBridge 172:65be27845400 23077 #define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
AnnaBridge 172:65be27845400 23078 #define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23079 #define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 23080
AnnaBridge 172:65be27845400 23081 #define HRTIM_EECR2_EE10SRC_Pos (24U)
AnnaBridge 172:65be27845400 23082 #define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 23083 #define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
AnnaBridge 172:65be27845400 23084 #define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23085 #define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23086 #define HRTIM_EECR2_EE10POL_Pos (26U)
AnnaBridge 172:65be27845400 23087 #define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23088 #define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
AnnaBridge 172:65be27845400 23089 #define HRTIM_EECR2_EE10SNS_Pos (27U)
AnnaBridge 172:65be27845400 23090 #define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
AnnaBridge 172:65be27845400 23091 #define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
AnnaBridge 172:65be27845400 23092 #define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23093 #define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 23094
AnnaBridge 172:65be27845400 23095 /******************* Bit definition for HRTIM_EECR3 register ****************/
AnnaBridge 172:65be27845400 23096 #define HRTIM_EECR3_EE6F_Pos (0U)
AnnaBridge 172:65be27845400 23097 #define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 23098 #define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
AnnaBridge 172:65be27845400 23099 #define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23100 #define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23101 #define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23102 #define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23103 #define HRTIM_EECR3_EE7F_Pos (6U)
AnnaBridge 172:65be27845400 23104 #define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
AnnaBridge 172:65be27845400 23105 #define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
AnnaBridge 172:65be27845400 23106 #define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23107 #define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23108 #define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23109 #define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23110 #define HRTIM_EECR3_EE8F_Pos (12U)
AnnaBridge 172:65be27845400 23111 #define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
AnnaBridge 172:65be27845400 23112 #define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
AnnaBridge 172:65be27845400 23113 #define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23114 #define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23115 #define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23116 #define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23117 #define HRTIM_EECR3_EE9F_Pos (18U)
AnnaBridge 172:65be27845400 23118 #define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
AnnaBridge 172:65be27845400 23119 #define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
AnnaBridge 172:65be27845400 23120 #define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23121 #define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23122 #define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23123 #define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23124 #define HRTIM_EECR3_EE10F_Pos (24U)
AnnaBridge 172:65be27845400 23125 #define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
AnnaBridge 172:65be27845400 23126 #define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
AnnaBridge 172:65be27845400 23127 #define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23128 #define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23129 #define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23130 #define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23131 #define HRTIM_EECR3_EEVSD_Pos (30U)
AnnaBridge 172:65be27845400 23132 #define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
AnnaBridge 172:65be27845400 23133 #define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
AnnaBridge 172:65be27845400 23134 #define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 23135 #define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 23136
AnnaBridge 172:65be27845400 23137 /******************* Bit definition for HRTIM_ADC1R register ****************/
AnnaBridge 172:65be27845400 23138 #define HRTIM_ADC1R_AD1MC1_Pos (0U)
AnnaBridge 172:65be27845400 23139 #define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23140 #define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
AnnaBridge 172:65be27845400 23141 #define HRTIM_ADC1R_AD1MC2_Pos (1U)
AnnaBridge 172:65be27845400 23142 #define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23143 #define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
AnnaBridge 172:65be27845400 23144 #define HRTIM_ADC1R_AD1MC3_Pos (2U)
AnnaBridge 172:65be27845400 23145 #define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23146 #define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
AnnaBridge 172:65be27845400 23147 #define HRTIM_ADC1R_AD1MC4_Pos (3U)
AnnaBridge 172:65be27845400 23148 #define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23149 #define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
AnnaBridge 172:65be27845400 23150 #define HRTIM_ADC1R_AD1MPER_Pos (4U)
AnnaBridge 172:65be27845400 23151 #define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23152 #define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
AnnaBridge 172:65be27845400 23153 #define HRTIM_ADC1R_AD1EEV1_Pos (5U)
AnnaBridge 172:65be27845400 23154 #define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23155 #define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
AnnaBridge 172:65be27845400 23156 #define HRTIM_ADC1R_AD1EEV2_Pos (6U)
AnnaBridge 172:65be27845400 23157 #define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23158 #define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
AnnaBridge 172:65be27845400 23159 #define HRTIM_ADC1R_AD1EEV3_Pos (7U)
AnnaBridge 172:65be27845400 23160 #define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23161 #define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
AnnaBridge 172:65be27845400 23162 #define HRTIM_ADC1R_AD1EEV4_Pos (8U)
AnnaBridge 172:65be27845400 23163 #define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23164 #define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
AnnaBridge 172:65be27845400 23165 #define HRTIM_ADC1R_AD1EEV5_Pos (9U)
AnnaBridge 172:65be27845400 23166 #define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23167 #define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
AnnaBridge 172:65be27845400 23168 #define HRTIM_ADC1R_AD1TAC2_Pos (10U)
AnnaBridge 172:65be27845400 23169 #define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23170 #define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
AnnaBridge 172:65be27845400 23171 #define HRTIM_ADC1R_AD1TAC3_Pos (11U)
AnnaBridge 172:65be27845400 23172 #define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23173 #define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
AnnaBridge 172:65be27845400 23174 #define HRTIM_ADC1R_AD1TAC4_Pos (12U)
AnnaBridge 172:65be27845400 23175 #define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23176 #define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
AnnaBridge 172:65be27845400 23177 #define HRTIM_ADC1R_AD1TAPER_Pos (13U)
AnnaBridge 172:65be27845400 23178 #define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23179 #define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
AnnaBridge 172:65be27845400 23180 #define HRTIM_ADC1R_AD1TARST_Pos (14U)
AnnaBridge 172:65be27845400 23181 #define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23182 #define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
AnnaBridge 172:65be27845400 23183 #define HRTIM_ADC1R_AD1TBC2_Pos (15U)
AnnaBridge 172:65be27845400 23184 #define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23185 #define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
AnnaBridge 172:65be27845400 23186 #define HRTIM_ADC1R_AD1TBC3_Pos (16U)
AnnaBridge 172:65be27845400 23187 #define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23188 #define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
AnnaBridge 172:65be27845400 23189 #define HRTIM_ADC1R_AD1TBC4_Pos (17U)
AnnaBridge 172:65be27845400 23190 #define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23191 #define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
AnnaBridge 172:65be27845400 23192 #define HRTIM_ADC1R_AD1TBPER_Pos (18U)
AnnaBridge 172:65be27845400 23193 #define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23194 #define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
AnnaBridge 172:65be27845400 23195 #define HRTIM_ADC1R_AD1TBRST_Pos (19U)
AnnaBridge 172:65be27845400 23196 #define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23197 #define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
AnnaBridge 172:65be27845400 23198 #define HRTIM_ADC1R_AD1TCC2_Pos (20U)
AnnaBridge 172:65be27845400 23199 #define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23200 #define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
AnnaBridge 172:65be27845400 23201 #define HRTIM_ADC1R_AD1TCC3_Pos (21U)
AnnaBridge 172:65be27845400 23202 #define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23203 #define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
AnnaBridge 172:65be27845400 23204 #define HRTIM_ADC1R_AD1TCC4_Pos (22U)
AnnaBridge 172:65be27845400 23205 #define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 23206 #define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
AnnaBridge 172:65be27845400 23207 #define HRTIM_ADC1R_AD1TCPER_Pos (23U)
AnnaBridge 172:65be27845400 23208 #define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 23209 #define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
AnnaBridge 172:65be27845400 23210 #define HRTIM_ADC1R_AD1TDC2_Pos (24U)
AnnaBridge 172:65be27845400 23211 #define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23212 #define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
AnnaBridge 172:65be27845400 23213 #define HRTIM_ADC1R_AD1TDC3_Pos (25U)
AnnaBridge 172:65be27845400 23214 #define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23215 #define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
AnnaBridge 172:65be27845400 23216 #define HRTIM_ADC1R_AD1TDC4_Pos (26U)
AnnaBridge 172:65be27845400 23217 #define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23218 #define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
AnnaBridge 172:65be27845400 23219 #define HRTIM_ADC1R_AD1TDPER_Pos (27U)
AnnaBridge 172:65be27845400 23220 #define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23221 #define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
AnnaBridge 172:65be27845400 23222 #define HRTIM_ADC1R_AD1TEC2_Pos (28U)
AnnaBridge 172:65be27845400 23223 #define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 23224 #define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
AnnaBridge 172:65be27845400 23225 #define HRTIM_ADC1R_AD1TEC3_Pos (29U)
AnnaBridge 172:65be27845400 23226 #define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 23227 #define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
AnnaBridge 172:65be27845400 23228 #define HRTIM_ADC1R_AD1TEC4_Pos (30U)
AnnaBridge 172:65be27845400 23229 #define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 23230 #define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
AnnaBridge 172:65be27845400 23231 #define HRTIM_ADC1R_AD1TEPER_Pos (31U)
AnnaBridge 172:65be27845400 23232 #define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 23233 #define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
AnnaBridge 172:65be27845400 23234
AnnaBridge 172:65be27845400 23235 /******************* Bit definition for HRTIM_ADC2R register ****************/
AnnaBridge 172:65be27845400 23236 #define HRTIM_ADC2R_AD2MC1_Pos (0U)
AnnaBridge 172:65be27845400 23237 #define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23238 #define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
AnnaBridge 172:65be27845400 23239 #define HRTIM_ADC2R_AD2MC2_Pos (1U)
AnnaBridge 172:65be27845400 23240 #define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23241 #define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
AnnaBridge 172:65be27845400 23242 #define HRTIM_ADC2R_AD2MC3_Pos (2U)
AnnaBridge 172:65be27845400 23243 #define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23244 #define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
AnnaBridge 172:65be27845400 23245 #define HRTIM_ADC2R_AD2MC4_Pos (3U)
AnnaBridge 172:65be27845400 23246 #define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23247 #define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
AnnaBridge 172:65be27845400 23248 #define HRTIM_ADC2R_AD2MPER_Pos (4U)
AnnaBridge 172:65be27845400 23249 #define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23250 #define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
AnnaBridge 172:65be27845400 23251 #define HRTIM_ADC2R_AD2EEV6_Pos (5U)
AnnaBridge 172:65be27845400 23252 #define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23253 #define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
AnnaBridge 172:65be27845400 23254 #define HRTIM_ADC2R_AD2EEV7_Pos (6U)
AnnaBridge 172:65be27845400 23255 #define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23256 #define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
AnnaBridge 172:65be27845400 23257 #define HRTIM_ADC2R_AD2EEV8_Pos (7U)
AnnaBridge 172:65be27845400 23258 #define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23259 #define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
AnnaBridge 172:65be27845400 23260 #define HRTIM_ADC2R_AD2EEV9_Pos (8U)
AnnaBridge 172:65be27845400 23261 #define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23262 #define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
AnnaBridge 172:65be27845400 23263 #define HRTIM_ADC2R_AD2EEV10_Pos (9U)
AnnaBridge 172:65be27845400 23264 #define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23265 #define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
AnnaBridge 172:65be27845400 23266 #define HRTIM_ADC2R_AD2TAC2_Pos (10U)
AnnaBridge 172:65be27845400 23267 #define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23268 #define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
AnnaBridge 172:65be27845400 23269 #define HRTIM_ADC2R_AD2TAC3_Pos (11U)
AnnaBridge 172:65be27845400 23270 #define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23271 #define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
AnnaBridge 172:65be27845400 23272 #define HRTIM_ADC2R_AD2TAC4_Pos (12U)
AnnaBridge 172:65be27845400 23273 #define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23274 #define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
AnnaBridge 172:65be27845400 23275 #define HRTIM_ADC2R_AD2TAPER_Pos (13U)
AnnaBridge 172:65be27845400 23276 #define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23277 #define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
AnnaBridge 172:65be27845400 23278 #define HRTIM_ADC2R_AD2TBC2_Pos (14U)
AnnaBridge 172:65be27845400 23279 #define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23280 #define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
AnnaBridge 172:65be27845400 23281 #define HRTIM_ADC2R_AD2TBC3_Pos (15U)
AnnaBridge 172:65be27845400 23282 #define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23283 #define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
AnnaBridge 172:65be27845400 23284 #define HRTIM_ADC2R_AD2TBC4_Pos (16U)
AnnaBridge 172:65be27845400 23285 #define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23286 #define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
AnnaBridge 172:65be27845400 23287 #define HRTIM_ADC2R_AD2TBPER_Pos (17U)
AnnaBridge 172:65be27845400 23288 #define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23289 #define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
AnnaBridge 172:65be27845400 23290 #define HRTIM_ADC2R_AD2TCC2_Pos (18U)
AnnaBridge 172:65be27845400 23291 #define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23292 #define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
AnnaBridge 172:65be27845400 23293 #define HRTIM_ADC2R_AD2TCC3_Pos (19U)
AnnaBridge 172:65be27845400 23294 #define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23295 #define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
AnnaBridge 172:65be27845400 23296 #define HRTIM_ADC2R_AD2TCC4_Pos (20U)
AnnaBridge 172:65be27845400 23297 #define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23298 #define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
AnnaBridge 172:65be27845400 23299 #define HRTIM_ADC2R_AD2TCPER_Pos (21U)
AnnaBridge 172:65be27845400 23300 #define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23301 #define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
AnnaBridge 172:65be27845400 23302 #define HRTIM_ADC2R_AD2TCRST_Pos (22U)
AnnaBridge 172:65be27845400 23303 #define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 23304 #define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
AnnaBridge 172:65be27845400 23305 #define HRTIM_ADC2R_AD2TDC2_Pos (23U)
AnnaBridge 172:65be27845400 23306 #define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 23307 #define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
AnnaBridge 172:65be27845400 23308 #define HRTIM_ADC2R_AD2TDC3_Pos (24U)
AnnaBridge 172:65be27845400 23309 #define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23310 #define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
AnnaBridge 172:65be27845400 23311 #define HRTIM_ADC2R_AD2TDC4_Pos (25U)
AnnaBridge 172:65be27845400 23312 #define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23313 #define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
AnnaBridge 172:65be27845400 23314 #define HRTIM_ADC2R_AD2TDPER_Pos (26U)
AnnaBridge 172:65be27845400 23315 #define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23316 #define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
AnnaBridge 172:65be27845400 23317 #define HRTIM_ADC2R_AD2TDRST_Pos (27U)
AnnaBridge 172:65be27845400 23318 #define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23319 #define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
AnnaBridge 172:65be27845400 23320 #define HRTIM_ADC2R_AD2TEC2_Pos (28U)
AnnaBridge 172:65be27845400 23321 #define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 23322 #define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
AnnaBridge 172:65be27845400 23323 #define HRTIM_ADC2R_AD2TEC3_Pos (29U)
AnnaBridge 172:65be27845400 23324 #define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 23325 #define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
AnnaBridge 172:65be27845400 23326 #define HRTIM_ADC2R_AD2TEC4_Pos (30U)
AnnaBridge 172:65be27845400 23327 #define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 23328 #define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
AnnaBridge 172:65be27845400 23329 #define HRTIM_ADC2R_AD2TERST_Pos (31U)
AnnaBridge 172:65be27845400 23330 #define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 23331 #define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
AnnaBridge 172:65be27845400 23332
AnnaBridge 172:65be27845400 23333 /******************* Bit definition for HRTIM_ADC3R register ****************/
AnnaBridge 172:65be27845400 23334 #define HRTIM_ADC3R_AD3MC1_Pos (0U)
AnnaBridge 172:65be27845400 23335 #define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23336 #define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
AnnaBridge 172:65be27845400 23337 #define HRTIM_ADC3R_AD3MC2_Pos (1U)
AnnaBridge 172:65be27845400 23338 #define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23339 #define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
AnnaBridge 172:65be27845400 23340 #define HRTIM_ADC3R_AD3MC3_Pos (2U)
AnnaBridge 172:65be27845400 23341 #define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23342 #define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
AnnaBridge 172:65be27845400 23343 #define HRTIM_ADC3R_AD3MC4_Pos (3U)
AnnaBridge 172:65be27845400 23344 #define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23345 #define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
AnnaBridge 172:65be27845400 23346 #define HRTIM_ADC3R_AD3MPER_Pos (4U)
AnnaBridge 172:65be27845400 23347 #define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23348 #define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
AnnaBridge 172:65be27845400 23349 #define HRTIM_ADC3R_AD3EEV1_Pos (5U)
AnnaBridge 172:65be27845400 23350 #define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23351 #define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
AnnaBridge 172:65be27845400 23352 #define HRTIM_ADC3R_AD3EEV2_Pos (6U)
AnnaBridge 172:65be27845400 23353 #define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23354 #define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
AnnaBridge 172:65be27845400 23355 #define HRTIM_ADC3R_AD3EEV3_Pos (7U)
AnnaBridge 172:65be27845400 23356 #define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23357 #define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
AnnaBridge 172:65be27845400 23358 #define HRTIM_ADC3R_AD3EEV4_Pos (8U)
AnnaBridge 172:65be27845400 23359 #define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23360 #define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
AnnaBridge 172:65be27845400 23361 #define HRTIM_ADC3R_AD3EEV5_Pos (9U)
AnnaBridge 172:65be27845400 23362 #define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23363 #define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
AnnaBridge 172:65be27845400 23364 #define HRTIM_ADC3R_AD3TAC2_Pos (10U)
AnnaBridge 172:65be27845400 23365 #define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23366 #define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
AnnaBridge 172:65be27845400 23367 #define HRTIM_ADC3R_AD3TAC3_Pos (11U)
AnnaBridge 172:65be27845400 23368 #define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23369 #define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
AnnaBridge 172:65be27845400 23370 #define HRTIM_ADC3R_AD3TAC4_Pos (12U)
AnnaBridge 172:65be27845400 23371 #define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23372 #define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
AnnaBridge 172:65be27845400 23373 #define HRTIM_ADC3R_AD3TAPER_Pos (13U)
AnnaBridge 172:65be27845400 23374 #define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23375 #define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
AnnaBridge 172:65be27845400 23376 #define HRTIM_ADC3R_AD3TARST_Pos (14U)
AnnaBridge 172:65be27845400 23377 #define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23378 #define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
AnnaBridge 172:65be27845400 23379 #define HRTIM_ADC3R_AD3TBC2_Pos (15U)
AnnaBridge 172:65be27845400 23380 #define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23381 #define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
AnnaBridge 172:65be27845400 23382 #define HRTIM_ADC3R_AD3TBC3_Pos (16U)
AnnaBridge 172:65be27845400 23383 #define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23384 #define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
AnnaBridge 172:65be27845400 23385 #define HRTIM_ADC3R_AD3TBC4_Pos (17U)
AnnaBridge 172:65be27845400 23386 #define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23387 #define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
AnnaBridge 172:65be27845400 23388 #define HRTIM_ADC3R_AD3TBPER_Pos (18U)
AnnaBridge 172:65be27845400 23389 #define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23390 #define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
AnnaBridge 172:65be27845400 23391 #define HRTIM_ADC3R_AD3TBRST_Pos (19U)
AnnaBridge 172:65be27845400 23392 #define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23393 #define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
AnnaBridge 172:65be27845400 23394 #define HRTIM_ADC3R_AD3TCC2_Pos (20U)
AnnaBridge 172:65be27845400 23395 #define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23396 #define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
AnnaBridge 172:65be27845400 23397 #define HRTIM_ADC3R_AD3TCC3_Pos (21U)
AnnaBridge 172:65be27845400 23398 #define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23399 #define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
AnnaBridge 172:65be27845400 23400 #define HRTIM_ADC3R_AD3TCC4_Pos (22U)
AnnaBridge 172:65be27845400 23401 #define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 23402 #define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
AnnaBridge 172:65be27845400 23403 #define HRTIM_ADC3R_AD3TCPER_Pos (23U)
AnnaBridge 172:65be27845400 23404 #define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 23405 #define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
AnnaBridge 172:65be27845400 23406 #define HRTIM_ADC3R_AD3TDC2_Pos (24U)
AnnaBridge 172:65be27845400 23407 #define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23408 #define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
AnnaBridge 172:65be27845400 23409 #define HRTIM_ADC3R_AD3TDC3_Pos (25U)
AnnaBridge 172:65be27845400 23410 #define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23411 #define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
AnnaBridge 172:65be27845400 23412 #define HRTIM_ADC3R_AD3TDC4_Pos (26U)
AnnaBridge 172:65be27845400 23413 #define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23414 #define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
AnnaBridge 172:65be27845400 23415 #define HRTIM_ADC3R_AD3TDPER_Pos (27U)
AnnaBridge 172:65be27845400 23416 #define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23417 #define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
AnnaBridge 172:65be27845400 23418 #define HRTIM_ADC3R_AD3TEC2_Pos (28U)
AnnaBridge 172:65be27845400 23419 #define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 23420 #define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
AnnaBridge 172:65be27845400 23421 #define HRTIM_ADC3R_AD3TEC3_Pos (29U)
AnnaBridge 172:65be27845400 23422 #define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 23423 #define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
AnnaBridge 172:65be27845400 23424 #define HRTIM_ADC3R_AD3TEC4_Pos (30U)
AnnaBridge 172:65be27845400 23425 #define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 23426 #define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
AnnaBridge 172:65be27845400 23427 #define HRTIM_ADC3R_AD3TEPER_Pos (31U)
AnnaBridge 172:65be27845400 23428 #define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 23429 #define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
AnnaBridge 172:65be27845400 23430
AnnaBridge 172:65be27845400 23431 /******************* Bit definition for HRTIM_ADC4R register ****************/
AnnaBridge 172:65be27845400 23432 #define HRTIM_ADC4R_AD4MC1_Pos (0U)
AnnaBridge 172:65be27845400 23433 #define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23434 #define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
AnnaBridge 172:65be27845400 23435 #define HRTIM_ADC4R_AD4MC2_Pos (1U)
AnnaBridge 172:65be27845400 23436 #define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23437 #define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
AnnaBridge 172:65be27845400 23438 #define HRTIM_ADC4R_AD4MC3_Pos (2U)
AnnaBridge 172:65be27845400 23439 #define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23440 #define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
AnnaBridge 172:65be27845400 23441 #define HRTIM_ADC4R_AD4MC4_Pos (3U)
AnnaBridge 172:65be27845400 23442 #define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23443 #define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
AnnaBridge 172:65be27845400 23444 #define HRTIM_ADC4R_AD4MPER_Pos (4U)
AnnaBridge 172:65be27845400 23445 #define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23446 #define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
AnnaBridge 172:65be27845400 23447 #define HRTIM_ADC4R_AD4EEV6_Pos (5U)
AnnaBridge 172:65be27845400 23448 #define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23449 #define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
AnnaBridge 172:65be27845400 23450 #define HRTIM_ADC4R_AD4EEV7_Pos (6U)
AnnaBridge 172:65be27845400 23451 #define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23452 #define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
AnnaBridge 172:65be27845400 23453 #define HRTIM_ADC4R_AD4EEV8_Pos (7U)
AnnaBridge 172:65be27845400 23454 #define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23455 #define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
AnnaBridge 172:65be27845400 23456 #define HRTIM_ADC4R_AD4EEV9_Pos (8U)
AnnaBridge 172:65be27845400 23457 #define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23458 #define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
AnnaBridge 172:65be27845400 23459 #define HRTIM_ADC4R_AD4EEV10_Pos (9U)
AnnaBridge 172:65be27845400 23460 #define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23461 #define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
AnnaBridge 172:65be27845400 23462 #define HRTIM_ADC4R_AD4TAC2_Pos (10U)
AnnaBridge 172:65be27845400 23463 #define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23464 #define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
AnnaBridge 172:65be27845400 23465 #define HRTIM_ADC4R_AD4TAC3_Pos (11U)
AnnaBridge 172:65be27845400 23466 #define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23467 #define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
AnnaBridge 172:65be27845400 23468 #define HRTIM_ADC4R_AD4TAC4_Pos (12U)
AnnaBridge 172:65be27845400 23469 #define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23470 #define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
AnnaBridge 172:65be27845400 23471 #define HRTIM_ADC4R_AD4TAPER_Pos (13U)
AnnaBridge 172:65be27845400 23472 #define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23473 #define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
AnnaBridge 172:65be27845400 23474 #define HRTIM_ADC4R_AD4TBC2_Pos (14U)
AnnaBridge 172:65be27845400 23475 #define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23476 #define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
AnnaBridge 172:65be27845400 23477 #define HRTIM_ADC4R_AD4TBC3_Pos (15U)
AnnaBridge 172:65be27845400 23478 #define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23479 #define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
AnnaBridge 172:65be27845400 23480 #define HRTIM_ADC4R_AD4TBC4_Pos (16U)
AnnaBridge 172:65be27845400 23481 #define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23482 #define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
AnnaBridge 172:65be27845400 23483 #define HRTIM_ADC4R_AD4TBPER_Pos (17U)
AnnaBridge 172:65be27845400 23484 #define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23485 #define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
AnnaBridge 172:65be27845400 23486 #define HRTIM_ADC4R_AD4TCC2_Pos (18U)
AnnaBridge 172:65be27845400 23487 #define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23488 #define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
AnnaBridge 172:65be27845400 23489 #define HRTIM_ADC4R_AD4TCC3_Pos (19U)
AnnaBridge 172:65be27845400 23490 #define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23491 #define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
AnnaBridge 172:65be27845400 23492 #define HRTIM_ADC4R_AD4TCC4_Pos (20U)
AnnaBridge 172:65be27845400 23493 #define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23494 #define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
AnnaBridge 172:65be27845400 23495 #define HRTIM_ADC4R_AD4TCPER_Pos (21U)
AnnaBridge 172:65be27845400 23496 #define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23497 #define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
AnnaBridge 172:65be27845400 23498 #define HRTIM_ADC4R_AD4TCRST_Pos (22U)
AnnaBridge 172:65be27845400 23499 #define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 23500 #define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
AnnaBridge 172:65be27845400 23501 #define HRTIM_ADC4R_AD4TDC2_Pos (23U)
AnnaBridge 172:65be27845400 23502 #define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 23503 #define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
AnnaBridge 172:65be27845400 23504 #define HRTIM_ADC4R_AD4TDC3_Pos (24U)
AnnaBridge 172:65be27845400 23505 #define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23506 #define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
AnnaBridge 172:65be27845400 23507 #define HRTIM_ADC4R_AD4TDC4_Pos (25U)
AnnaBridge 172:65be27845400 23508 #define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23509 #define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
AnnaBridge 172:65be27845400 23510 #define HRTIM_ADC4R_AD4TDPER_Pos (26U)
AnnaBridge 172:65be27845400 23511 #define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23512 #define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
AnnaBridge 172:65be27845400 23513 #define HRTIM_ADC4R_AD4TDRST_Pos (27U)
AnnaBridge 172:65be27845400 23514 #define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23515 #define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
AnnaBridge 172:65be27845400 23516 #define HRTIM_ADC4R_AD4TEC2_Pos (28U)
AnnaBridge 172:65be27845400 23517 #define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 23518 #define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
AnnaBridge 172:65be27845400 23519 #define HRTIM_ADC4R_AD4TEC3_Pos (29U)
AnnaBridge 172:65be27845400 23520 #define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 23521 #define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
AnnaBridge 172:65be27845400 23522 #define HRTIM_ADC4R_AD4TEC4_Pos (30U)
AnnaBridge 172:65be27845400 23523 #define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 23524 #define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
AnnaBridge 172:65be27845400 23525 #define HRTIM_ADC4R_AD4TERST_Pos (31U)
AnnaBridge 172:65be27845400 23526 #define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 23527 #define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
AnnaBridge 172:65be27845400 23528
AnnaBridge 172:65be27845400 23529 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
AnnaBridge 172:65be27845400 23530 #define HRTIM_FLTINR1_FLT1E_Pos (0U)
AnnaBridge 172:65be27845400 23531 #define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23532 #define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
AnnaBridge 172:65be27845400 23533 #define HRTIM_FLTINR1_FLT1P_Pos (1U)
AnnaBridge 172:65be27845400 23534 #define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23535 #define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
AnnaBridge 172:65be27845400 23536 #define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
AnnaBridge 172:65be27845400 23537 #define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23538 #define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
AnnaBridge 172:65be27845400 23539 #define HRTIM_FLTINR1_FLT1F_Pos (3U)
AnnaBridge 172:65be27845400 23540 #define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
AnnaBridge 172:65be27845400 23541 #define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
AnnaBridge 172:65be27845400 23542 #define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23543 #define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23544 #define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23545 #define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23546 #define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
AnnaBridge 172:65be27845400 23547 #define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23548 #define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
AnnaBridge 172:65be27845400 23549
AnnaBridge 172:65be27845400 23550 #define HRTIM_FLTINR1_FLT2E_Pos (8U)
AnnaBridge 172:65be27845400 23551 #define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23552 #define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
AnnaBridge 172:65be27845400 23553 #define HRTIM_FLTINR1_FLT2P_Pos (9U)
AnnaBridge 172:65be27845400 23554 #define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23555 #define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
AnnaBridge 172:65be27845400 23556 #define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
AnnaBridge 172:65be27845400 23557 #define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23558 #define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
AnnaBridge 172:65be27845400 23559 #define HRTIM_FLTINR1_FLT2F_Pos (11U)
AnnaBridge 172:65be27845400 23560 #define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
AnnaBridge 172:65be27845400 23561 #define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
AnnaBridge 172:65be27845400 23562 #define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23563 #define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23564 #define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23565 #define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23566 #define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
AnnaBridge 172:65be27845400 23567 #define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23568 #define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
AnnaBridge 172:65be27845400 23569
AnnaBridge 172:65be27845400 23570 #define HRTIM_FLTINR1_FLT3E_Pos (16U)
AnnaBridge 172:65be27845400 23571 #define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23572 #define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
AnnaBridge 172:65be27845400 23573 #define HRTIM_FLTINR1_FLT3P_Pos (17U)
AnnaBridge 172:65be27845400 23574 #define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23575 #define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
AnnaBridge 172:65be27845400 23576 #define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
AnnaBridge 172:65be27845400 23577 #define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23578 #define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
AnnaBridge 172:65be27845400 23579 #define HRTIM_FLTINR1_FLT3F_Pos (19U)
AnnaBridge 172:65be27845400 23580 #define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
AnnaBridge 172:65be27845400 23581 #define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
AnnaBridge 172:65be27845400 23582 #define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23583 #define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23584 #define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 23585 #define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 23586 #define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
AnnaBridge 172:65be27845400 23587 #define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 23588 #define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
AnnaBridge 172:65be27845400 23589
AnnaBridge 172:65be27845400 23590 #define HRTIM_FLTINR1_FLT4E_Pos (24U)
AnnaBridge 172:65be27845400 23591 #define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23592 #define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
AnnaBridge 172:65be27845400 23593 #define HRTIM_FLTINR1_FLT4P_Pos (25U)
AnnaBridge 172:65be27845400 23594 #define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23595 #define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
AnnaBridge 172:65be27845400 23596 #define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
AnnaBridge 172:65be27845400 23597 #define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 23598 #define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
AnnaBridge 172:65be27845400 23599 #define HRTIM_FLTINR1_FLT4F_Pos (27U)
AnnaBridge 172:65be27845400 23600 #define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
AnnaBridge 172:65be27845400 23601 #define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
AnnaBridge 172:65be27845400 23602 #define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 23603 #define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 23604 #define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 23605 #define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 23606 #define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
AnnaBridge 172:65be27845400 23607 #define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 23608 #define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
AnnaBridge 172:65be27845400 23609
AnnaBridge 172:65be27845400 23610 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
AnnaBridge 172:65be27845400 23611 #define HRTIM_FLTINR2_FLT5E_Pos (0U)
AnnaBridge 172:65be27845400 23612 #define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23613 #define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
AnnaBridge 172:65be27845400 23614 #define HRTIM_FLTINR2_FLT5P_Pos (1U)
AnnaBridge 172:65be27845400 23615 #define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23616 #define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
AnnaBridge 172:65be27845400 23617 #define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
AnnaBridge 172:65be27845400 23618 #define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23619 #define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
AnnaBridge 172:65be27845400 23620 #define HRTIM_FLTINR2_FLT5F_Pos (3U)
AnnaBridge 172:65be27845400 23621 #define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
AnnaBridge 172:65be27845400 23622 #define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
AnnaBridge 172:65be27845400 23623 #define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23624 #define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23625 #define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23626 #define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23627 #define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
AnnaBridge 172:65be27845400 23628 #define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23629 #define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
AnnaBridge 172:65be27845400 23630 #define HRTIM_FLTINR2_FLTSD_Pos (24U)
AnnaBridge 172:65be27845400 23631 #define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 23632 #define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
AnnaBridge 172:65be27845400 23633 #define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23634 #define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23635
AnnaBridge 172:65be27845400 23636 /******************* Bit definition for HRTIM_BDMUPR register ***************/
AnnaBridge 172:65be27845400 23637 #define HRTIM_BDMUPR_MCR_Pos (0U)
AnnaBridge 172:65be27845400 23638 #define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23639 #define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
AnnaBridge 172:65be27845400 23640 #define HRTIM_BDMUPR_MICR_Pos (1U)
AnnaBridge 172:65be27845400 23641 #define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23642 #define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
AnnaBridge 172:65be27845400 23643 #define HRTIM_BDMUPR_MDIER_Pos (2U)
AnnaBridge 172:65be27845400 23644 #define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23645 #define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
AnnaBridge 172:65be27845400 23646 #define HRTIM_BDMUPR_MCNT_Pos (3U)
AnnaBridge 172:65be27845400 23647 #define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23648 #define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
AnnaBridge 172:65be27845400 23649 #define HRTIM_BDMUPR_MPER_Pos (4U)
AnnaBridge 172:65be27845400 23650 #define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23651 #define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
AnnaBridge 172:65be27845400 23652 #define HRTIM_BDMUPR_MREP_Pos (5U)
AnnaBridge 172:65be27845400 23653 #define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23654 #define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
AnnaBridge 172:65be27845400 23655 #define HRTIM_BDMUPR_MCMP1_Pos (6U)
AnnaBridge 172:65be27845400 23656 #define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23657 #define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
AnnaBridge 172:65be27845400 23658 #define HRTIM_BDMUPR_MCMP2_Pos (7U)
AnnaBridge 172:65be27845400 23659 #define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23660 #define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
AnnaBridge 172:65be27845400 23661 #define HRTIM_BDMUPR_MCMP3_Pos (8U)
AnnaBridge 172:65be27845400 23662 #define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23663 #define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
AnnaBridge 172:65be27845400 23664 #define HRTIM_BDMUPR_MCMP4_Pos (9U)
AnnaBridge 172:65be27845400 23665 #define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23666 #define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
AnnaBridge 172:65be27845400 23667
AnnaBridge 172:65be27845400 23668 /******************* Bit definition for HRTIM_BDTUPR register ***************/
AnnaBridge 172:65be27845400 23669 #define HRTIM_BDTUPR_TIMCR_Pos (0U)
AnnaBridge 172:65be27845400 23670 #define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23671 #define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
AnnaBridge 172:65be27845400 23672 #define HRTIM_BDTUPR_TIMICR_Pos (1U)
AnnaBridge 172:65be27845400 23673 #define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23674 #define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
AnnaBridge 172:65be27845400 23675 #define HRTIM_BDTUPR_TIMDIER_Pos (2U)
AnnaBridge 172:65be27845400 23676 #define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23677 #define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
AnnaBridge 172:65be27845400 23678 #define HRTIM_BDTUPR_TIMCNT_Pos (3U)
AnnaBridge 172:65be27845400 23679 #define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23680 #define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
AnnaBridge 172:65be27845400 23681 #define HRTIM_BDTUPR_TIMPER_Pos (4U)
AnnaBridge 172:65be27845400 23682 #define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23683 #define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
AnnaBridge 172:65be27845400 23684 #define HRTIM_BDTUPR_TIMREP_Pos (5U)
AnnaBridge 172:65be27845400 23685 #define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23686 #define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
AnnaBridge 172:65be27845400 23687 #define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
AnnaBridge 172:65be27845400 23688 #define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23689 #define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
AnnaBridge 172:65be27845400 23690 #define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
AnnaBridge 172:65be27845400 23691 #define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23692 #define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
AnnaBridge 172:65be27845400 23693 #define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
AnnaBridge 172:65be27845400 23694 #define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23695 #define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
AnnaBridge 172:65be27845400 23696 #define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
AnnaBridge 172:65be27845400 23697 #define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23698 #define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
AnnaBridge 172:65be27845400 23699 #define HRTIM_BDTUPR_TIMDTR_Pos (10U)
AnnaBridge 172:65be27845400 23700 #define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23701 #define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
AnnaBridge 172:65be27845400 23702 #define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
AnnaBridge 172:65be27845400 23703 #define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23704 #define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
AnnaBridge 172:65be27845400 23705 #define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
AnnaBridge 172:65be27845400 23706 #define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23707 #define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
AnnaBridge 172:65be27845400 23708 #define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
AnnaBridge 172:65be27845400 23709 #define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 23710 #define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
AnnaBridge 172:65be27845400 23711 #define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
AnnaBridge 172:65be27845400 23712 #define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 23713 #define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
AnnaBridge 172:65be27845400 23714 #define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
AnnaBridge 172:65be27845400 23715 #define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 23716 #define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
AnnaBridge 172:65be27845400 23717 #define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
AnnaBridge 172:65be27845400 23718 #define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23719 #define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
AnnaBridge 172:65be27845400 23720 #define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
AnnaBridge 172:65be27845400 23721 #define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23722 #define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
AnnaBridge 172:65be27845400 23723 #define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
AnnaBridge 172:65be27845400 23724 #define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23725 #define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
AnnaBridge 172:65be27845400 23726 #define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
AnnaBridge 172:65be27845400 23727 #define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23728 #define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
AnnaBridge 172:65be27845400 23729 #define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
AnnaBridge 172:65be27845400 23730 #define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23731 #define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
AnnaBridge 172:65be27845400 23732
AnnaBridge 172:65be27845400 23733 /******************* Bit definition for HRTIM_BDMADR register ***************/
AnnaBridge 172:65be27845400 23734 #define HRTIM_BDMADR_BDMADR_Pos (0U)
AnnaBridge 172:65be27845400 23735 #define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 23736 #define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
AnnaBridge 172:65be27845400 23737
AnnaBridge 172:65be27845400 23738 /******************************************************************************/
AnnaBridge 172:65be27845400 23739 /* */
AnnaBridge 172:65be27845400 23740 /* RAM ECC monitoring */
AnnaBridge 172:65be27845400 23741 /* */
AnnaBridge 172:65be27845400 23742 /******************************************************************************/
AnnaBridge 172:65be27845400 23743 /****************** Bit definition for RAMECC_IER register ******************/
AnnaBridge 172:65be27845400 23744 #define RAMECC_IER_GECCDEBWIE_Pos (3U)
AnnaBridge 172:65be27845400 23745 #define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23746 #define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */
AnnaBridge 172:65be27845400 23747 #define RAMECC_IER_GECCDEIE_Pos (2U)
AnnaBridge 172:65be27845400 23748 #define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23749 #define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */
AnnaBridge 172:65be27845400 23750 #define RAMECC_IER_GECCSEIE_Pos (1U)
AnnaBridge 172:65be27845400 23751 #define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23752 #define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */
AnnaBridge 172:65be27845400 23753 #define RAMECC_IER_GIE_Pos (0U)
AnnaBridge 172:65be27845400 23754 #define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23755 #define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */
AnnaBridge 172:65be27845400 23756
AnnaBridge 172:65be27845400 23757 /******************* Bit definition for RAMECC_CR register ******************/
AnnaBridge 172:65be27845400 23758 #define RAMECC_CR_ECCELEN_Pos (5U)
AnnaBridge 172:65be27845400 23759 #define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23760 #define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */
AnnaBridge 172:65be27845400 23761 #define RAMECC_CR_ECCDEBWIE_Pos (4U)
AnnaBridge 172:65be27845400 23762 #define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23763 #define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */
AnnaBridge 172:65be27845400 23764 #define RAMECC_CR_ECCDEIE_Pos (3U)
AnnaBridge 172:65be27845400 23765 #define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23766 #define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */
AnnaBridge 172:65be27845400 23767 #define RAMECC_CR_ECCSEIE_Pos (2U)
AnnaBridge 172:65be27845400 23768 #define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23769 #define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */
AnnaBridge 172:65be27845400 23770
AnnaBridge 172:65be27845400 23771 /******************* Bit definition for RAMECC_SR register ******************/
AnnaBridge 172:65be27845400 23772 #define RAMECC_SR_DEBWDF_Pos (2U)
AnnaBridge 172:65be27845400 23773 #define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23774 #define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */
AnnaBridge 172:65be27845400 23775 #define RAMECC_SR_DEDF_Pos (1U)
AnnaBridge 172:65be27845400 23776 #define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23777 #define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */
AnnaBridge 172:65be27845400 23778 #define RAMECC_SR_SEDCF_Pos (0U)
AnnaBridge 172:65be27845400 23779 #define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23780 #define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */
AnnaBridge 172:65be27845400 23781
AnnaBridge 172:65be27845400 23782 /****************** Bit definition for RAMECC_FAR register ******************/
AnnaBridge 172:65be27845400 23783 #define RAMECC_FAR_FADD_Pos (0U)
AnnaBridge 172:65be27845400 23784 #define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 23785 #define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */
AnnaBridge 172:65be27845400 23786
AnnaBridge 172:65be27845400 23787 /****************** Bit definition for RAMECC_FDRL register *****************/
AnnaBridge 172:65be27845400 23788 #define RAMECC_FAR_FDATAL_Pos (0U)
AnnaBridge 172:65be27845400 23789 #define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 23790 #define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */
AnnaBridge 172:65be27845400 23791
AnnaBridge 172:65be27845400 23792 /****************** Bit definition for RAMECC_FDRH register *****************/
AnnaBridge 172:65be27845400 23793 #define RAMECC_FAR_FDATAH_Pos (0U)
AnnaBridge 172:65be27845400 23794 #define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 23795 #define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
AnnaBridge 172:65be27845400 23796
AnnaBridge 172:65be27845400 23797 /***************** Bit definition for RAMECC_FECR register ******************/
AnnaBridge 172:65be27845400 23798 #define RAMECC_FECR_FEC_Pos (0U)
AnnaBridge 172:65be27845400 23799 #define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 23800 #define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */
AnnaBridge 172:65be27845400 23801
AnnaBridge 172:65be27845400 23802 /******************************************************************************/
AnnaBridge 172:65be27845400 23803 /* */
AnnaBridge 172:65be27845400 23804 /* MDIOS */
AnnaBridge 172:65be27845400 23805 /* */
AnnaBridge 172:65be27845400 23806 /******************************************************************************/
AnnaBridge 172:65be27845400 23807 /******************** Bit definition for MDIOS_CR register *******************/
AnnaBridge 172:65be27845400 23808 #define MDIOS_CR_EN_Pos (0U)
AnnaBridge 172:65be27845400 23809 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23810 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
AnnaBridge 172:65be27845400 23811 #define MDIOS_CR_WRIE_Pos (1U)
AnnaBridge 172:65be27845400 23812 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23813 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
AnnaBridge 172:65be27845400 23814 #define MDIOS_CR_RDIE_Pos (2U)
AnnaBridge 172:65be27845400 23815 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23816 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
AnnaBridge 172:65be27845400 23817 #define MDIOS_CR_EIE_Pos (3U)
AnnaBridge 172:65be27845400 23818 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23819 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
AnnaBridge 172:65be27845400 23820 #define MDIOS_CR_DPC_Pos (7U)
AnnaBridge 172:65be27845400 23821 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23822 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
AnnaBridge 172:65be27845400 23823 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
AnnaBridge 172:65be27845400 23824 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
AnnaBridge 172:65be27845400 23825 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
AnnaBridge 172:65be27845400 23826 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23827 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23828 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23829 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23830 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23831
AnnaBridge 172:65be27845400 23832 /******************** Bit definition for MDIOS_SR register *******************/
AnnaBridge 172:65be27845400 23833 #define MDIOS_SR_PERF_Pos (0U)
AnnaBridge 172:65be27845400 23834 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23835 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
AnnaBridge 172:65be27845400 23836 #define MDIOS_SR_SERF_Pos (1U)
AnnaBridge 172:65be27845400 23837 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23838 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
AnnaBridge 172:65be27845400 23839 #define MDIOS_SR_TERF_Pos (2U)
AnnaBridge 172:65be27845400 23840 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23841 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
AnnaBridge 172:65be27845400 23842
AnnaBridge 172:65be27845400 23843 /******************** Bit definition for MDIOS_CLRFR register *******************/
AnnaBridge 172:65be27845400 23844 #define MDIOS_SR_CPERF_Pos (0U)
AnnaBridge 172:65be27845400 23845 #define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23846 #define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
AnnaBridge 172:65be27845400 23847 #define MDIOS_SR_CSERF_Pos (1U)
AnnaBridge 172:65be27845400 23848 #define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23849 #define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
AnnaBridge 172:65be27845400 23850 #define MDIOS_SR_CTERF_Pos (2U)
AnnaBridge 172:65be27845400 23851 #define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23852 #define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
AnnaBridge 172:65be27845400 23853
AnnaBridge 172:65be27845400 23854 /******************************************************************************/
AnnaBridge 172:65be27845400 23855 /* */
AnnaBridge 172:65be27845400 23856 /* USB_OTG */
AnnaBridge 172:65be27845400 23857 /* */
AnnaBridge 172:65be27845400 23858 /******************************************************************************/
AnnaBridge 172:65be27845400 23859 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
AnnaBridge 172:65be27845400 23860 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 172:65be27845400 23861 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23862 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 172:65be27845400 23863 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 172:65be27845400 23864 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23865 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 172:65be27845400 23866 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
AnnaBridge 172:65be27845400 23867 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23868 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
AnnaBridge 172:65be27845400 23869 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
AnnaBridge 172:65be27845400 23870 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 23871 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
AnnaBridge 172:65be27845400 23872 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
AnnaBridge 172:65be27845400 23873 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23874 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
AnnaBridge 172:65be27845400 23875 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
AnnaBridge 172:65be27845400 23876 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23877 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
AnnaBridge 172:65be27845400 23878 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
AnnaBridge 172:65be27845400 23879 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23880 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
AnnaBridge 172:65be27845400 23881 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
AnnaBridge 172:65be27845400 23882 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23883 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
AnnaBridge 172:65be27845400 23884 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 172:65be27845400 23885 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23886 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 172:65be27845400 23887 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 172:65be27845400 23888 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23889 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 172:65be27845400 23890 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 172:65be27845400 23891 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23892 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 172:65be27845400 23893 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 172:65be27845400 23894 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23895 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 172:65be27845400 23896 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
AnnaBridge 172:65be27845400 23897 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23898 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
AnnaBridge 172:65be27845400 23899 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 172:65be27845400 23900 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 23901 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 172:65be27845400 23902 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 172:65be27845400 23903 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23904 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 172:65be27845400 23905 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 172:65be27845400 23906 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23907 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 172:65be27845400 23908 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
AnnaBridge 172:65be27845400 23909 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23910 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
AnnaBridge 172:65be27845400 23911 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
AnnaBridge 172:65be27845400 23912 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 23913 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
AnnaBridge 172:65be27845400 23914
AnnaBridge 172:65be27845400 23915 /******************** Bit definition forUSB_OTG_HCFG register ********************/
AnnaBridge 172:65be27845400 23916
AnnaBridge 172:65be27845400 23917 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 172:65be27845400 23918 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 23919 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 172:65be27845400 23920 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23921 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23922 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 172:65be27845400 23923 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23924 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 172:65be27845400 23925
AnnaBridge 172:65be27845400 23926 /******************** Bit definition forUSB_OTG_DCFG register ********************/
AnnaBridge 172:65be27845400 23927
AnnaBridge 172:65be27845400 23928 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 172:65be27845400 23929 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 172:65be27845400 23930 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 172:65be27845400 23931 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23932 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23933 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 172:65be27845400 23934 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23935 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 172:65be27845400 23936
AnnaBridge 172:65be27845400 23937 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 172:65be27845400 23938 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 172:65be27845400 23939 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 172:65be27845400 23940 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23941 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 23942 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 23943 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 23944 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23945 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23946 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 23947
AnnaBridge 172:65be27845400 23948 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 172:65be27845400 23949 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 172:65be27845400 23950 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 172:65be27845400 23951 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 23952 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 23953
AnnaBridge 172:65be27845400 23954 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 172:65be27845400 23955 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 172:65be27845400 23956 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 172:65be27845400 23957 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 23958 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 23959
AnnaBridge 172:65be27845400 23960 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
AnnaBridge 172:65be27845400 23961 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 172:65be27845400 23962 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23963 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 172:65be27845400 23964 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 172:65be27845400 23965 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23966 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 172:65be27845400 23967 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 172:65be27845400 23968 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 23969 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 172:65be27845400 23970
AnnaBridge 172:65be27845400 23971 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
AnnaBridge 172:65be27845400 23972 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 172:65be27845400 23973 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 23974 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 172:65be27845400 23975 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 172:65be27845400 23976 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 23977 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 172:65be27845400 23978 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 172:65be27845400 23979 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 23980 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 172:65be27845400 23981 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 172:65be27845400 23982 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 23983 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 172:65be27845400 23984 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 172:65be27845400 23985 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 23986 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 172:65be27845400 23987 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 172:65be27845400 23988 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 23989 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 172:65be27845400 23990
AnnaBridge 172:65be27845400 23991 /******************** Bit definition forUSB_OTG_DCTL register ********************/
AnnaBridge 172:65be27845400 23992 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 172:65be27845400 23993 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 23994 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 172:65be27845400 23995 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 172:65be27845400 23996 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 23997 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 172:65be27845400 23998 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 172:65be27845400 23999 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24000 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 172:65be27845400 24001 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 172:65be27845400 24002 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24003 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 172:65be27845400 24004
AnnaBridge 172:65be27845400 24005 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 172:65be27845400 24006 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 172:65be27845400 24007 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 172:65be27845400 24008 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24009 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24010 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24011 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 172:65be27845400 24012 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24013 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 172:65be27845400 24014 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 172:65be27845400 24015 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24016 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 172:65be27845400 24017 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 172:65be27845400 24018 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24019 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 172:65be27845400 24020 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 172:65be27845400 24021 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24022 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 172:65be27845400 24023 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 172:65be27845400 24024 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 24025 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 172:65be27845400 24026
AnnaBridge 172:65be27845400 24027 /******************** Bit definition forUSB_OTG_HFIR register ********************/
AnnaBridge 172:65be27845400 24028 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 172:65be27845400 24029 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24030 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 172:65be27845400 24031
AnnaBridge 172:65be27845400 24032 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
AnnaBridge 172:65be27845400 24033 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 172:65be27845400 24034 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24035 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 172:65be27845400 24036 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 172:65be27845400 24037 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 24038 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 172:65be27845400 24039
AnnaBridge 172:65be27845400 24040 /******************** Bit definition forUSB_OTG_DSTS register ********************/
AnnaBridge 172:65be27845400 24041 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 172:65be27845400 24042 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24043 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 172:65be27845400 24044
AnnaBridge 172:65be27845400 24045 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 172:65be27845400 24046 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 172:65be27845400 24047 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 172:65be27845400 24048 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24049 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24050 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 172:65be27845400 24051 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24052 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 172:65be27845400 24053 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 172:65be27845400 24054 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 172:65be27845400 24055 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 172:65be27845400 24056
AnnaBridge 172:65be27845400 24057 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
AnnaBridge 172:65be27845400 24058 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 172:65be27845400 24059 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24060 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 172:65be27845400 24061
AnnaBridge 172:65be27845400 24062 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 172:65be27845400 24063 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 172:65be27845400 24064 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 172:65be27845400 24065 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24066 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24067 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24068 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24069 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 172:65be27845400 24070 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24071 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 172:65be27845400 24072 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 172:65be27845400 24073 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24074 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 172:65be27845400 24075 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 172:65be27845400 24076 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24077 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 172:65be27845400 24078
AnnaBridge 172:65be27845400 24079 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
AnnaBridge 172:65be27845400 24080
AnnaBridge 172:65be27845400 24081 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 172:65be27845400 24082 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 172:65be27845400 24083 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 172:65be27845400 24084 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24085 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24086 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24087 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 172:65be27845400 24088 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24089 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 172:65be27845400 24090 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 172:65be27845400 24091 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24092 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 172:65be27845400 24093 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 172:65be27845400 24094 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24095 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 172:65be27845400 24096
AnnaBridge 172:65be27845400 24097 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 172:65be27845400 24098 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 172:65be27845400 24099 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 172:65be27845400 24100 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24101 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 24102 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24103 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24104 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 172:65be27845400 24105 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24106 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 172:65be27845400 24107 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 172:65be27845400 24108 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24109 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 172:65be27845400 24110 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 172:65be27845400 24111 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24112 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 172:65be27845400 24113 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 172:65be27845400 24114 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24115 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 172:65be27845400 24116 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 172:65be27845400 24117 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24118 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 172:65be27845400 24119 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 172:65be27845400 24120 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24121 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 172:65be27845400 24122 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 172:65be27845400 24123 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24124 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 172:65be27845400 24125 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 172:65be27845400 24126 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24127 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 172:65be27845400 24128 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 172:65be27845400 24129 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24130 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 172:65be27845400 24131 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 172:65be27845400 24132 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24133 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 172:65be27845400 24134 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 172:65be27845400 24135 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 24136 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 172:65be27845400 24137 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 172:65be27845400 24138 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24139 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 172:65be27845400 24140 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 172:65be27845400 24141 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24142 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 172:65be27845400 24143
AnnaBridge 172:65be27845400 24144 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
AnnaBridge 172:65be27845400 24145 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 172:65be27845400 24146 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24147 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 172:65be27845400 24148 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 172:65be27845400 24149 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24150 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 172:65be27845400 24151 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 172:65be27845400 24152 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24153 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 172:65be27845400 24154 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 172:65be27845400 24155 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24156 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 172:65be27845400 24157 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 172:65be27845400 24158 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24159 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 172:65be27845400 24160
AnnaBridge 172:65be27845400 24161 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 172:65be27845400 24162 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 172:65be27845400 24163 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 172:65be27845400 24164 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24165 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24166 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24167 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24168 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24169 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 172:65be27845400 24170 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24171 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 172:65be27845400 24172 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 172:65be27845400 24173 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24174 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 172:65be27845400 24175
AnnaBridge 172:65be27845400 24176 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
AnnaBridge 172:65be27845400 24177 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 24178 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24179 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 24180 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 24181 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24182 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 24183 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 172:65be27845400 24184 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24185 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 172:65be27845400 24186 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 172:65be27845400 24187 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24188 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 172:65be27845400 24189 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 172:65be27845400 24190 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24191 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 172:65be27845400 24192 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 172:65be27845400 24193 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24194 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 172:65be27845400 24195 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 172:65be27845400 24196 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24197 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 172:65be27845400 24198 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 172:65be27845400 24199 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24200 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 24201
AnnaBridge 172:65be27845400 24202 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
AnnaBridge 172:65be27845400 24203 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 172:65be27845400 24204 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24205 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 172:65be27845400 24206
AnnaBridge 172:65be27845400 24207 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 172:65be27845400 24208 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 24209 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 172:65be27845400 24210 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24211 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24212 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24213 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24214 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24215 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24216 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24217 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24218
AnnaBridge 172:65be27845400 24219 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 172:65be27845400 24220 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 172:65be27845400 24221 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 172:65be27845400 24222 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24223 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24224 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 24225 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 24226 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 24227 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 24228 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24229 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24230
AnnaBridge 172:65be27845400 24231 /******************** Bit definition forUSB_OTG_HAINT register ********************/
AnnaBridge 172:65be27845400 24232 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 172:65be27845400 24233 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24234 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 172:65be27845400 24235
AnnaBridge 172:65be27845400 24236 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
AnnaBridge 172:65be27845400 24237 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 24238 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24239 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 24240 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 24241 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24242 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 24243 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 172:65be27845400 24244 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24245 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 172:65be27845400 24246 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 172:65be27845400 24247 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24248 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 172:65be27845400 24249 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
AnnaBridge 172:65be27845400 24250 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24251 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
AnnaBridge 172:65be27845400 24252 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 172:65be27845400 24253 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24254 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 172:65be27845400 24255 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 172:65be27845400 24256 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24257 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 172:65be27845400 24258 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 172:65be27845400 24259 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24260 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 24261
AnnaBridge 172:65be27845400 24262 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
AnnaBridge 172:65be27845400 24263 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 172:65be27845400 24264 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24265 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 172:65be27845400 24266 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 172:65be27845400 24267 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24268 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 172:65be27845400 24269 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 172:65be27845400 24270 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24271 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 172:65be27845400 24272 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 172:65be27845400 24273 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24274 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 172:65be27845400 24275 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 172:65be27845400 24276 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24277 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 172:65be27845400 24278 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 172:65be27845400 24279 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24280 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 172:65be27845400 24281 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 172:65be27845400 24282 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24283 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 172:65be27845400 24284 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 172:65be27845400 24285 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24286 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 172:65be27845400 24287 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 172:65be27845400 24288 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24289 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 172:65be27845400 24290 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 172:65be27845400 24291 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 24292 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 172:65be27845400 24293 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 172:65be27845400 24294 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24295 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 172:65be27845400 24296 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 172:65be27845400 24297 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24298 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 172:65be27845400 24299 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 172:65be27845400 24300 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 24301 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 172:65be27845400 24302 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 172:65be27845400 24303 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24304 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 172:65be27845400 24305 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 172:65be27845400 24306 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24307 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 172:65be27845400 24308 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 172:65be27845400 24309 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24310 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 172:65be27845400 24311 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 172:65be27845400 24312 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24313 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 172:65be27845400 24314 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 172:65be27845400 24315 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24316 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 172:65be27845400 24317 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 172:65be27845400 24318 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24319 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 172:65be27845400 24320 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
AnnaBridge 172:65be27845400 24321 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24322 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
AnnaBridge 172:65be27845400 24323 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 172:65be27845400 24324 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24325 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 172:65be27845400 24326 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 172:65be27845400 24327 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24328 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 172:65be27845400 24329 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 172:65be27845400 24330 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 24331 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 172:65be27845400 24332 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
AnnaBridge 172:65be27845400 24333 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 24334 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
AnnaBridge 172:65be27845400 24335 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 172:65be27845400 24336 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 24337 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 172:65be27845400 24338 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 172:65be27845400 24339 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 24340 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 172:65be27845400 24341 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 172:65be27845400 24342 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24343 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 172:65be27845400 24344 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 172:65be27845400 24345 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24346 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 172:65be27845400 24347
AnnaBridge 172:65be27845400 24348 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
AnnaBridge 172:65be27845400 24349 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 172:65be27845400 24350 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24351 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 172:65be27845400 24352 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 172:65be27845400 24353 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24354 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 172:65be27845400 24355 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 172:65be27845400 24356 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24357 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 172:65be27845400 24358 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 172:65be27845400 24359 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24360 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 172:65be27845400 24361 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 172:65be27845400 24362 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24363 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 172:65be27845400 24364 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 172:65be27845400 24365 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24366 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 172:65be27845400 24367 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 172:65be27845400 24368 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24369 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 172:65be27845400 24370 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 172:65be27845400 24371 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24372 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 172:65be27845400 24373 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 172:65be27845400 24374 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 24375 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 172:65be27845400 24376 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 172:65be27845400 24377 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24378 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 172:65be27845400 24379 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 172:65be27845400 24380 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24381 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 172:65be27845400 24382 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 172:65be27845400 24383 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 24384 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 172:65be27845400 24385 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 172:65be27845400 24386 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24387 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 172:65be27845400 24388 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 172:65be27845400 24389 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24390 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 172:65be27845400 24391 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 172:65be27845400 24392 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24393 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 172:65be27845400 24394 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 172:65be27845400 24395 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24396 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 172:65be27845400 24397 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 172:65be27845400 24398 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24399 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 172:65be27845400 24400 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 172:65be27845400 24401 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24402 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 172:65be27845400 24403 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 172:65be27845400 24404 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24405 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 172:65be27845400 24406 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
AnnaBridge 172:65be27845400 24407 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24408 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
AnnaBridge 172:65be27845400 24409 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 172:65be27845400 24410 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24411 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 172:65be27845400 24412 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 172:65be27845400 24413 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24414 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 172:65be27845400 24415 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 172:65be27845400 24416 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 24417 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 172:65be27845400 24418 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
AnnaBridge 172:65be27845400 24419 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 24420 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
AnnaBridge 172:65be27845400 24421 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 172:65be27845400 24422 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 24423 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 172:65be27845400 24424 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 172:65be27845400 24425 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 24426 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 172:65be27845400 24427 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 172:65be27845400 24428 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24429 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 172:65be27845400 24430 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 172:65be27845400 24431 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24432 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 172:65be27845400 24433
AnnaBridge 172:65be27845400 24434 /******************** Bit definition forUSB_OTG_DAINT register ********************/
AnnaBridge 172:65be27845400 24435 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 172:65be27845400 24436 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24437 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 172:65be27845400 24438 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 172:65be27845400 24439 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 24440 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 172:65be27845400 24441
AnnaBridge 172:65be27845400 24442 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
AnnaBridge 172:65be27845400 24443 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 172:65be27845400 24444 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24445 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
AnnaBridge 172:65be27845400 24446
AnnaBridge 172:65be27845400 24447 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 172:65be27845400 24448 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 172:65be27845400 24449 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 24450 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 172:65be27845400 24451 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 172:65be27845400 24452 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 172:65be27845400 24453 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 24454 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 172:65be27845400 24455 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 172:65be27845400 24456 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 24457 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 172:65be27845400 24458 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 172:65be27845400 24459 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 24460
AnnaBridge 172:65be27845400 24461 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
AnnaBridge 172:65be27845400 24462 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 172:65be27845400 24463 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24464 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 172:65be27845400 24465 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 172:65be27845400 24466 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 24467 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 172:65be27845400 24468
AnnaBridge 172:65be27845400 24469 /******************** Bit definition for OTG register ********************/
AnnaBridge 172:65be27845400 24470
AnnaBridge 172:65be27845400 24471 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 172:65be27845400 24472 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 24473 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 172:65be27845400 24474 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24475 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24476 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24477 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24478 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 172:65be27845400 24479 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 172:65be27845400 24480 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 172:65be27845400 24481
AnnaBridge 172:65be27845400 24482 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 172:65be27845400 24483 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 172:65be27845400 24484 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 172:65be27845400 24485 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24486 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24487
AnnaBridge 172:65be27845400 24488 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 172:65be27845400 24489 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 172:65be27845400 24490 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 172:65be27845400 24491 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24492 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24493 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24494 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24495
AnnaBridge 172:65be27845400 24496 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 172:65be27845400 24497 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 172:65be27845400 24498 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 172:65be27845400 24499 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24500 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24501 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24502 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24503
AnnaBridge 172:65be27845400 24504 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 172:65be27845400 24505 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 172:65be27845400 24506 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 172:65be27845400 24507 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24508 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24509 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24510 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24511
AnnaBridge 172:65be27845400 24512 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
AnnaBridge 172:65be27845400 24513 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 172:65be27845400 24514 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24515 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 172:65be27845400 24516
AnnaBridge 172:65be27845400 24517 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
AnnaBridge 172:65be27845400 24518 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 172:65be27845400 24519 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24520 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
AnnaBridge 172:65be27845400 24521
AnnaBridge 172:65be27845400 24522 /******************** Bit definition for OTG register ********************/
AnnaBridge 172:65be27845400 24523 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 172:65be27845400 24524 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24525 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 172:65be27845400 24526 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 172:65be27845400 24527 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 24528 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 172:65be27845400 24529 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 172:65be27845400 24530 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24531 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 172:65be27845400 24532 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 172:65be27845400 24533 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 24534 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
AnnaBridge 172:65be27845400 24535
AnnaBridge 172:65be27845400 24536 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
AnnaBridge 172:65be27845400 24537 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 172:65be27845400 24538 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 172:65be27845400 24539 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 172:65be27845400 24540
AnnaBridge 172:65be27845400 24541 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
AnnaBridge 172:65be27845400 24542 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 172:65be27845400 24543 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24544 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 172:65be27845400 24545
AnnaBridge 172:65be27845400 24546 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 172:65be27845400 24547 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 172:65be27845400 24548 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 172:65be27845400 24549 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24550 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24551 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24552 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24553 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24554 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24555 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24556 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24557
AnnaBridge 172:65be27845400 24558 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 172:65be27845400 24559 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 172:65be27845400 24560 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 172:65be27845400 24561 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24562 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24563 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 24564 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 24565 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 24566 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 24567 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24568
AnnaBridge 172:65be27845400 24569 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
AnnaBridge 172:65be27845400 24570 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 172:65be27845400 24571 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24572 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 172:65be27845400 24573 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 172:65be27845400 24574 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24575 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 172:65be27845400 24576
AnnaBridge 172:65be27845400 24577 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 172:65be27845400 24578 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 172:65be27845400 24579 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 172:65be27845400 24580 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24581 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24582 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24583 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24584 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24585 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24586 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24587 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24588 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24589 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 172:65be27845400 24590 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24591 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 172:65be27845400 24592
AnnaBridge 172:65be27845400 24593 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 172:65be27845400 24594 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 172:65be27845400 24595 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 172:65be27845400 24596 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24597 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24598 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24599 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24600 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24601 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24602 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24603 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24604 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24605 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 172:65be27845400 24606 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 24607 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 172:65be27845400 24608
AnnaBridge 172:65be27845400 24609 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 172:65be27845400 24610 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 172:65be27845400 24611 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24612 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 172:65be27845400 24613
AnnaBridge 172:65be27845400 24614 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
AnnaBridge 172:65be27845400 24615 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 172:65be27845400 24616 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24617 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 172:65be27845400 24618 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 172:65be27845400 24619 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24620 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 172:65be27845400 24621
AnnaBridge 172:65be27845400 24622 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
AnnaBridge 172:65be27845400 24623 #define USB_OTG_GCCFG_DCDET_Pos (0U)
AnnaBridge 172:65be27845400 24624 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24625 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
AnnaBridge 172:65be27845400 24626 #define USB_OTG_GCCFG_PDET_Pos (1U)
AnnaBridge 172:65be27845400 24627 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24628 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
AnnaBridge 172:65be27845400 24629 #define USB_OTG_GCCFG_SDET_Pos (2U)
AnnaBridge 172:65be27845400 24630 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24631 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
AnnaBridge 172:65be27845400 24632 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
AnnaBridge 172:65be27845400 24633 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24634 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
AnnaBridge 172:65be27845400 24635 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 172:65be27845400 24636 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24637 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 172:65be27845400 24638 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
AnnaBridge 172:65be27845400 24639 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24640 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
AnnaBridge 172:65be27845400 24641 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
AnnaBridge 172:65be27845400 24642 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24643 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
AnnaBridge 172:65be27845400 24644 #define USB_OTG_GCCFG_PDEN_Pos (19U)
AnnaBridge 172:65be27845400 24645 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24646 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
AnnaBridge 172:65be27845400 24647 #define USB_OTG_GCCFG_SDEN_Pos (20U)
AnnaBridge 172:65be27845400 24648 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24649 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
AnnaBridge 172:65be27845400 24650 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
AnnaBridge 172:65be27845400 24651 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24652 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
AnnaBridge 172:65be27845400 24653
AnnaBridge 172:65be27845400 24654 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
AnnaBridge 172:65be27845400 24655 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
AnnaBridge 172:65be27845400 24656 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24657 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
AnnaBridge 172:65be27845400 24658 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
AnnaBridge 172:65be27845400 24659 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24660 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
AnnaBridge 172:65be27845400 24661
AnnaBridge 172:65be27845400 24662 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
AnnaBridge 172:65be27845400 24663 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 172:65be27845400 24664 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24665 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 172:65be27845400 24666 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 172:65be27845400 24667 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24668 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 172:65be27845400 24669
AnnaBridge 172:65be27845400 24670 /******************** Bit definition forUSB_OTG_CID register ********************/
AnnaBridge 172:65be27845400 24671 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 172:65be27845400 24672 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 24673 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 172:65be27845400 24674
AnnaBridge 172:65be27845400 24675 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
AnnaBridge 172:65be27845400 24676 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
AnnaBridge 172:65be27845400 24677 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24678 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
AnnaBridge 172:65be27845400 24679 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
AnnaBridge 172:65be27845400 24680 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24681 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
AnnaBridge 172:65be27845400 24682 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
AnnaBridge 172:65be27845400 24683 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
AnnaBridge 172:65be27845400 24684 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
AnnaBridge 172:65be27845400 24685 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
AnnaBridge 172:65be27845400 24686 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24687 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
AnnaBridge 172:65be27845400 24688 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
AnnaBridge 172:65be27845400 24689 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24690 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
AnnaBridge 172:65be27845400 24691 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
AnnaBridge 172:65be27845400 24692 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
AnnaBridge 172:65be27845400 24693 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
AnnaBridge 172:65be27845400 24694 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
AnnaBridge 172:65be27845400 24695 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24696 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
AnnaBridge 172:65be27845400 24697 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
AnnaBridge 172:65be27845400 24698 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
AnnaBridge 172:65be27845400 24699 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
AnnaBridge 172:65be27845400 24700 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
AnnaBridge 172:65be27845400 24701 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24702 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
AnnaBridge 172:65be27845400 24703 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
AnnaBridge 172:65be27845400 24704 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24705 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
AnnaBridge 172:65be27845400 24706 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
AnnaBridge 172:65be27845400 24707 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
AnnaBridge 172:65be27845400 24708 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
AnnaBridge 172:65be27845400 24709 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
AnnaBridge 172:65be27845400 24710 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
AnnaBridge 172:65be27845400 24711 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
AnnaBridge 172:65be27845400 24712 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
AnnaBridge 172:65be27845400 24713 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24714 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
AnnaBridge 172:65be27845400 24715 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
AnnaBridge 172:65be27845400 24716 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
AnnaBridge 172:65be27845400 24717 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
AnnaBridge 172:65be27845400 24718 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
AnnaBridge 172:65be27845400 24719 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 24720 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
AnnaBridge 172:65be27845400 24721
AnnaBridge 172:65be27845400 24722 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 172:65be27845400 24723 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 24724 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24725 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 24726 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 24727 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24728 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 24729 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 172:65be27845400 24730 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24731 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 172:65be27845400 24732 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 172:65be27845400 24733 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24734 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 172:65be27845400 24735 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 172:65be27845400 24736 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24737 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 172:65be27845400 24738 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 172:65be27845400 24739 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24740 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 172:65be27845400 24741 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 172:65be27845400 24742 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24743 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 172:65be27845400 24744 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 172:65be27845400 24745 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24746 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 24747 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 172:65be27845400 24748 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24749 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 172:65be27845400 24750
AnnaBridge 172:65be27845400 24751 /******************** Bit definition forUSB_OTG_HPRT register ********************/
AnnaBridge 172:65be27845400 24752 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 172:65be27845400 24753 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24754 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 172:65be27845400 24755 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 172:65be27845400 24756 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24757 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 172:65be27845400 24758 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 172:65be27845400 24759 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24760 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 172:65be27845400 24761 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 172:65be27845400 24762 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24763 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 172:65be27845400 24764 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 172:65be27845400 24765 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24766 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 172:65be27845400 24767 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 172:65be27845400 24768 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24769 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 172:65be27845400 24770 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 172:65be27845400 24771 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24772 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 172:65be27845400 24773 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 172:65be27845400 24774 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24775 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 172:65be27845400 24776 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 172:65be27845400 24777 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24778 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 172:65be27845400 24779
AnnaBridge 172:65be27845400 24780 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 172:65be27845400 24781 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 172:65be27845400 24782 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 172:65be27845400 24783 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24784 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 24785 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 172:65be27845400 24786 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24787 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 172:65be27845400 24788
AnnaBridge 172:65be27845400 24789 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 172:65be27845400 24790 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 172:65be27845400 24791 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 172:65be27845400 24792 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24793 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 24794 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24795 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24796
AnnaBridge 172:65be27845400 24797 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 172:65be27845400 24798 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 172:65be27845400 24799 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 172:65be27845400 24800 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24801 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24802
AnnaBridge 172:65be27845400 24803 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 172:65be27845400 24804 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 24805 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24806 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 172:65be27845400 24807 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 172:65be27845400 24808 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24809 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 172:65be27845400 24810 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 172:65be27845400 24811 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24812 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 172:65be27845400 24813 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 172:65be27845400 24814 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24815 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 172:65be27845400 24816 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 172:65be27845400 24817 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24818 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 172:65be27845400 24819 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 172:65be27845400 24820 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24821 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 172:65be27845400 24822 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 172:65be27845400 24823 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24824 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 172:65be27845400 24825 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 172:65be27845400 24826 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24827 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 172:65be27845400 24828 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 172:65be27845400 24829 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24830 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 172:65be27845400 24831 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 172:65be27845400 24832 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24833 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 172:65be27845400 24834 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 172:65be27845400 24835 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 24836 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 172:65be27845400 24837
AnnaBridge 172:65be27845400 24838 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
AnnaBridge 172:65be27845400 24839 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 172:65be27845400 24840 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 24841 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 172:65be27845400 24842 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 172:65be27845400 24843 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 24844 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 172:65be27845400 24845
AnnaBridge 172:65be27845400 24846 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
AnnaBridge 172:65be27845400 24847 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 172:65be27845400 24848 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 24849 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 172:65be27845400 24850 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 172:65be27845400 24851 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24852 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 172:65be27845400 24853 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 172:65be27845400 24854 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24855 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 172:65be27845400 24856 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 172:65be27845400 24857 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24858 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 172:65be27845400 24859
AnnaBridge 172:65be27845400 24860 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 172:65be27845400 24861 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 24862 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 172:65be27845400 24863 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24864 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24865 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 172:65be27845400 24866 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24867 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 172:65be27845400 24868
AnnaBridge 172:65be27845400 24869 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 172:65be27845400 24870 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 172:65be27845400 24871 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 172:65be27845400 24872 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24873 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24874 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24875 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24876 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 172:65be27845400 24877 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 24878 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 172:65be27845400 24879 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 172:65be27845400 24880 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 24881 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 172:65be27845400 24882 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 172:65be27845400 24883 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 24884 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 172:65be27845400 24885 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 172:65be27845400 24886 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 24887 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 172:65be27845400 24888 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 172:65be27845400 24889 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24890 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 172:65be27845400 24891 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 172:65be27845400 24892 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24893 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 172:65be27845400 24894
AnnaBridge 172:65be27845400 24895 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
AnnaBridge 172:65be27845400 24896 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 172:65be27845400 24897 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 24898 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 172:65be27845400 24899
AnnaBridge 172:65be27845400 24900 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 172:65be27845400 24901 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 172:65be27845400 24902 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 172:65be27845400 24903 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 24904 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24905 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24906 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 24907 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 172:65be27845400 24908 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24909 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 172:65be27845400 24910 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 172:65be27845400 24911 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 24912 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 172:65be27845400 24913
AnnaBridge 172:65be27845400 24914 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 172:65be27845400 24915 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 24916 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 172:65be27845400 24917 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 24918 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 24919
AnnaBridge 172:65be27845400 24920 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 172:65be27845400 24921 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 172:65be27845400 24922 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 172:65be27845400 24923 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 24924 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 24925
AnnaBridge 172:65be27845400 24926 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 172:65be27845400 24927 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 172:65be27845400 24928 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 172:65be27845400 24929 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 172:65be27845400 24930 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 172:65be27845400 24931 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 172:65be27845400 24932 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 172:65be27845400 24933 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 24934 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 24935 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 24936 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 172:65be27845400 24937 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 24938 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 172:65be27845400 24939 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 172:65be27845400 24940 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 24941 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 172:65be27845400 24942 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 172:65be27845400 24943 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24944 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 172:65be27845400 24945
AnnaBridge 172:65be27845400 24946 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
AnnaBridge 172:65be27845400 24947
AnnaBridge 172:65be27845400 24948 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 172:65be27845400 24949 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 172:65be27845400 24950 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 172:65be27845400 24951 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24952 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24953 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24954 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24955 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24956 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 24957 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 24958
AnnaBridge 172:65be27845400 24959 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 172:65be27845400 24960 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 172:65be27845400 24961 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 172:65be27845400 24962 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 24963 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 24964 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 24965 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 24966 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 24967 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 24968 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 24969
AnnaBridge 172:65be27845400 24970 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 172:65be27845400 24971 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 172:65be27845400 24972 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 172:65be27845400 24973 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 24974 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 24975 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 172:65be27845400 24976 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 172:65be27845400 24977 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 172:65be27845400 24978 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 172:65be27845400 24979 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 24980 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 172:65be27845400 24981
AnnaBridge 172:65be27845400 24982 /******************** Bit definition forUSB_OTG_HCINT register ********************/
AnnaBridge 172:65be27845400 24983 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 172:65be27845400 24984 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 24985 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 172:65be27845400 24986 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 172:65be27845400 24987 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 24988 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 172:65be27845400 24989 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 172:65be27845400 24990 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 24991 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 172:65be27845400 24992 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 172:65be27845400 24993 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 24994 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 172:65be27845400 24995 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 172:65be27845400 24996 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 24997 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 172:65be27845400 24998 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 172:65be27845400 24999 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 25000 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 172:65be27845400 25001 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 172:65be27845400 25002 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 25003 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 172:65be27845400 25004 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 172:65be27845400 25005 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 25006 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 172:65be27845400 25007 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 172:65be27845400 25008 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 25009 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 172:65be27845400 25010 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 172:65be27845400 25011 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 25012 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 172:65be27845400 25013 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 172:65be27845400 25014 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 25015 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 172:65be27845400 25016
AnnaBridge 172:65be27845400 25017 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
AnnaBridge 172:65be27845400 25018 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 172:65be27845400 25019 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 25020 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 172:65be27845400 25021 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 172:65be27845400 25022 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 25023 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 172:65be27845400 25024 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 172:65be27845400 25025 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 25026 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 172:65be27845400 25027 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 172:65be27845400 25028 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 25029 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 172:65be27845400 25030 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 172:65be27845400 25031 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 25032 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 172:65be27845400 25033 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 172:65be27845400 25034 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 25035 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 172:65be27845400 25036 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 172:65be27845400 25037 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 25038 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 172:65be27845400 25039 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 172:65be27845400 25040 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 25041 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 172:65be27845400 25042 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 172:65be27845400 25043 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 172:65be27845400 25044 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 172:65be27845400 25045 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 172:65be27845400 25046 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 172:65be27845400 25047 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 172:65be27845400 25048 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 172:65be27845400 25049 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 172:65be27845400 25050 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
AnnaBridge 172:65be27845400 25051
AnnaBridge 172:65be27845400 25052 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
AnnaBridge 172:65be27845400 25053 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 172:65be27845400 25054 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 25055 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 172:65be27845400 25056 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 172:65be27845400 25057 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 25058 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 172:65be27845400 25059 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 172:65be27845400 25060 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 172:65be27845400 25061 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 172:65be27845400 25062 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 172:65be27845400 25063 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 25064 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 172:65be27845400 25065 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 172:65be27845400 25066 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 25067 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 172:65be27845400 25068 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 172:65be27845400 25069 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 25070 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 172:65be27845400 25071 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 172:65be27845400 25072 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 25073 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 172:65be27845400 25074 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 172:65be27845400 25075 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 172:65be27845400 25076 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 172:65be27845400 25077 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 172:65be27845400 25078 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 172:65be27845400 25079 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 172:65be27845400 25080 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 172:65be27845400 25081 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 172:65be27845400 25082 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 172:65be27845400 25083 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 172:65be27845400 25084 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 172:65be27845400 25085 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
AnnaBridge 172:65be27845400 25086
AnnaBridge 172:65be27845400 25087 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
AnnaBridge 172:65be27845400 25088
AnnaBridge 172:65be27845400 25089 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 172:65be27845400 25090 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 172:65be27845400 25091 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 172:65be27845400 25092 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 172:65be27845400 25093 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 172:65be27845400 25094 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 25095 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 172:65be27845400 25096 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 172:65be27845400 25097 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 25098 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
AnnaBridge 172:65be27845400 25099 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 172:65be27845400 25100 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 172:65be27845400 25101 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 172:65be27845400 25102 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 172:65be27845400 25103 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 172:65be27845400 25104 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 25105 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 172:65be27845400 25106 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 25107 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 172:65be27845400 25108 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 172:65be27845400 25109 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 172:65be27845400 25110 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 172:65be27845400 25111 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 25112 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 25113
AnnaBridge 172:65be27845400 25114 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
AnnaBridge 172:65be27845400 25115 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 172:65be27845400 25116 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 25117 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 172:65be27845400 25118
AnnaBridge 172:65be27845400 25119 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
AnnaBridge 172:65be27845400 25120 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 172:65be27845400 25121 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 172:65be27845400 25122 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 172:65be27845400 25123
AnnaBridge 172:65be27845400 25124 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
AnnaBridge 172:65be27845400 25125 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 172:65be27845400 25126 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 25127 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 172:65be27845400 25128
AnnaBridge 172:65be27845400 25129 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
AnnaBridge 172:65be27845400 25130 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 172:65be27845400 25131 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 172:65be27845400 25132 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 172:65be27845400 25133 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 172:65be27845400 25134 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 172:65be27845400 25135 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 172:65be27845400 25136
AnnaBridge 172:65be27845400 25137 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
AnnaBridge 172:65be27845400 25138
AnnaBridge 172:65be27845400 25139 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 172:65be27845400 25140 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 172:65be27845400 25141 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 172:65be27845400 25142 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 172:65be27845400 25143 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 172:65be27845400 25144 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 172:65be27845400 25145 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 172:65be27845400 25146 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 172:65be27845400 25147 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 172:65be27845400 25148 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 172:65be27845400 25149 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 172:65be27845400 25150 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 172:65be27845400 25151 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 172:65be27845400 25152 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 25153 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 172:65be27845400 25154 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 172:65be27845400 25155 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 172:65be27845400 25156 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 172:65be27845400 25157 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 172:65be27845400 25158 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 172:65be27845400 25159 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 172:65be27845400 25160 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 172:65be27845400 25161 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 172:65be27845400 25162 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 172:65be27845400 25163 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 172:65be27845400 25164 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 172:65be27845400 25165 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 172:65be27845400 25166 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 172:65be27845400 25167 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 172:65be27845400 25168 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 172:65be27845400 25169 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 172:65be27845400 25170 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 172:65be27845400 25171 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 172:65be27845400 25172 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 25173 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 172:65be27845400 25174 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 172:65be27845400 25175 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 172:65be27845400 25176 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 172:65be27845400 25177
AnnaBridge 172:65be27845400 25178 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
AnnaBridge 172:65be27845400 25179 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 172:65be27845400 25180 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 25181 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 172:65be27845400 25182 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 172:65be27845400 25183 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 25184 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 172:65be27845400 25185 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 172:65be27845400 25186 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 172:65be27845400 25187 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 172:65be27845400 25188 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 172:65be27845400 25189 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 25190 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 172:65be27845400 25191 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
AnnaBridge 172:65be27845400 25192 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
AnnaBridge 172:65be27845400 25193 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
AnnaBridge 172:65be27845400 25194 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 172:65be27845400 25195 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 172:65be27845400 25196 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 172:65be27845400 25197 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 172:65be27845400 25198 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 172:65be27845400 25199 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 172:65be27845400 25200
AnnaBridge 172:65be27845400 25201 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
AnnaBridge 172:65be27845400 25202
AnnaBridge 172:65be27845400 25203 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 172:65be27845400 25204 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 172:65be27845400 25205 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 172:65be27845400 25206 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 172:65be27845400 25207 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 172:65be27845400 25208 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 172:65be27845400 25209
AnnaBridge 172:65be27845400 25210 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 172:65be27845400 25211 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 172:65be27845400 25212 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 172:65be27845400 25213 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 172:65be27845400 25214 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
AnnaBridge 172:65be27845400 25215
AnnaBridge 172:65be27845400 25216 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 172:65be27845400 25217 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 172:65be27845400 25218 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 172:65be27845400 25219 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 172:65be27845400 25220 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 172:65be27845400 25221 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 172:65be27845400 25222 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 172:65be27845400 25223 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 172:65be27845400 25224 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 172:65be27845400 25225 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
AnnaBridge 172:65be27845400 25226
AnnaBridge 172:65be27845400 25227 /**
AnnaBridge 172:65be27845400 25228 * @}
AnnaBridge 172:65be27845400 25229 */
AnnaBridge 172:65be27845400 25230
AnnaBridge 172:65be27845400 25231 /**
AnnaBridge 172:65be27845400 25232 * @}
AnnaBridge 172:65be27845400 25233 */
AnnaBridge 172:65be27845400 25234
AnnaBridge 172:65be27845400 25235 /** @addtogroup Exported_macros
AnnaBridge 172:65be27845400 25236 * @{
AnnaBridge 172:65be27845400 25237 */
AnnaBridge 172:65be27845400 25238
AnnaBridge 172:65be27845400 25239 /******************************* ADC Instances ********************************/
AnnaBridge 172:65be27845400 25240 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
AnnaBridge 172:65be27845400 25241 ((INSTANCE) == ADC2) || \
AnnaBridge 172:65be27845400 25242 ((INSTANCE) == ADC3))
AnnaBridge 172:65be27845400 25243
AnnaBridge 172:65be27845400 25244 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 172:65be27845400 25245
AnnaBridge 172:65be27845400 25246 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
AnnaBridge 172:65be27845400 25247 ((INSTANCE) == ADC3_COMMON))
AnnaBridge 172:65be27845400 25248
AnnaBridge 172:65be27845400 25249 /******************************** COMP Instances ******************************/
AnnaBridge 172:65be27845400 25250 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
AnnaBridge 172:65be27845400 25251 ((INSTANCE) == COMP2))
AnnaBridge 172:65be27845400 25252
AnnaBridge 172:65be27845400 25253 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
AnnaBridge 172:65be27845400 25254 /******************** COMP Instances with window mode capability **************/
AnnaBridge 172:65be27845400 25255 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
AnnaBridge 172:65be27845400 25256
AnnaBridge 172:65be27845400 25257
AnnaBridge 172:65be27845400 25258 /******************************* CRC Instances ********************************/
AnnaBridge 172:65be27845400 25259 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 172:65be27845400 25260
AnnaBridge 172:65be27845400 25261 /******************************* DAC Instances ********************************/
AnnaBridge 172:65be27845400 25262 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
AnnaBridge 172:65be27845400 25263 /******************************* DCMI Instances *******************************/
AnnaBridge 172:65be27845400 25264 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
AnnaBridge 172:65be27845400 25265
AnnaBridge 172:65be27845400 25266 /******************************* DELAYBLOCK Instances *******************************/
AnnaBridge 172:65be27845400 25267 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
AnnaBridge 172:65be27845400 25268 ((INSTANCE) == DLYB_SDMMC2) || \
AnnaBridge 172:65be27845400 25269 ((INSTANCE) == DLYB_QUADSPI))
AnnaBridge 172:65be27845400 25270 /****************************** DFSDM Instances *******************************/
AnnaBridge 172:65be27845400 25271 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
AnnaBridge 172:65be27845400 25272 ((INSTANCE) == DFSDM1_Filter1) || \
AnnaBridge 172:65be27845400 25273 ((INSTANCE) == DFSDM1_Filter2) || \
AnnaBridge 172:65be27845400 25274 ((INSTANCE) == DFSDM1_Filter3))
AnnaBridge 172:65be27845400 25275
AnnaBridge 172:65be27845400 25276 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
AnnaBridge 172:65be27845400 25277 ((INSTANCE) == DFSDM1_Channel1) || \
AnnaBridge 172:65be27845400 25278 ((INSTANCE) == DFSDM1_Channel2) || \
AnnaBridge 172:65be27845400 25279 ((INSTANCE) == DFSDM1_Channel3) || \
AnnaBridge 172:65be27845400 25280 ((INSTANCE) == DFSDM1_Channel4) || \
AnnaBridge 172:65be27845400 25281 ((INSTANCE) == DFSDM1_Channel5) || \
AnnaBridge 172:65be27845400 25282 ((INSTANCE) == DFSDM1_Channel6) || \
AnnaBridge 172:65be27845400 25283 ((INSTANCE) == DFSDM1_Channel7))
AnnaBridge 172:65be27845400 25284 /****************************** RAMECC Instances ******************************/
AnnaBridge 172:65be27845400 25285 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
AnnaBridge 172:65be27845400 25286 ((INSTANCE) == RAMECC1_Monitor2) || \
AnnaBridge 172:65be27845400 25287 ((INSTANCE) == RAMECC1_Monitor3) || \
AnnaBridge 172:65be27845400 25288 ((INSTANCE) == RAMECC1_Monitor4) || \
AnnaBridge 172:65be27845400 25289 ((INSTANCE) == RAMECC1_Monitor5) || \
AnnaBridge 172:65be27845400 25290 ((INSTANCE) == RAMECC2_Monitor1) || \
AnnaBridge 172:65be27845400 25291 ((INSTANCE) == RAMECC2_Monitor2) || \
AnnaBridge 172:65be27845400 25292 ((INSTANCE) == RAMECC2_Monitor3) || \
AnnaBridge 172:65be27845400 25293 ((INSTANCE) == RAMECC2_Monitor4) || \
AnnaBridge 172:65be27845400 25294 ((INSTANCE) == RAMECC2_Monitor5) || \
AnnaBridge 172:65be27845400 25295 ((INSTANCE) == RAMECC3_Monitor1) || \
AnnaBridge 172:65be27845400 25296 ((INSTANCE) == RAMECC3_Monitor2))
AnnaBridge 172:65be27845400 25297
AnnaBridge 172:65be27845400 25298 /******************************** DMA Instances *******************************/
AnnaBridge 172:65be27845400 25299 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 172:65be27845400 25300 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 172:65be27845400 25301 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 172:65be27845400 25302 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 172:65be27845400 25303 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 172:65be27845400 25304 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 172:65be27845400 25305 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 172:65be27845400 25306 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 172:65be27845400 25307 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 172:65be27845400 25308 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 172:65be27845400 25309 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 172:65be27845400 25310 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 172:65be27845400 25311 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 172:65be27845400 25312 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 172:65be27845400 25313 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 172:65be27845400 25314 ((INSTANCE) == DMA2_Stream7) || \
AnnaBridge 172:65be27845400 25315 ((INSTANCE) == BDMA_Channel0) || \
AnnaBridge 172:65be27845400 25316 ((INSTANCE) == BDMA_Channel1) || \
AnnaBridge 172:65be27845400 25317 ((INSTANCE) == BDMA_Channel2) || \
AnnaBridge 172:65be27845400 25318 ((INSTANCE) == BDMA_Channel3) || \
AnnaBridge 172:65be27845400 25319 ((INSTANCE) == BDMA_Channel4) || \
AnnaBridge 172:65be27845400 25320 ((INSTANCE) == BDMA_Channel5) || \
AnnaBridge 172:65be27845400 25321 ((INSTANCE) == BDMA_Channel6) || \
AnnaBridge 172:65be27845400 25322 ((INSTANCE) == BDMA_Channel7))
AnnaBridge 172:65be27845400 25323
AnnaBridge 172:65be27845400 25324 /****************************** BDMA CHANNEL Instances ***************************/
AnnaBridge 172:65be27845400 25325 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
AnnaBridge 172:65be27845400 25326 ((INSTANCE) == BDMA_Channel1) || \
AnnaBridge 172:65be27845400 25327 ((INSTANCE) == BDMA_Channel2) || \
AnnaBridge 172:65be27845400 25328 ((INSTANCE) == BDMA_Channel3) || \
AnnaBridge 172:65be27845400 25329 ((INSTANCE) == BDMA_Channel4) || \
AnnaBridge 172:65be27845400 25330 ((INSTANCE) == BDMA_Channel5) || \
AnnaBridge 172:65be27845400 25331 ((INSTANCE) == BDMA_Channel6) || \
AnnaBridge 172:65be27845400 25332 ((INSTANCE) == BDMA_Channel7))
AnnaBridge 172:65be27845400 25333
AnnaBridge 172:65be27845400 25334 /****************************** DMA DMAMUX ALL Instances ***************************/
AnnaBridge 172:65be27845400 25335 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 172:65be27845400 25336 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 172:65be27845400 25337 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 172:65be27845400 25338 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 172:65be27845400 25339 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 172:65be27845400 25340 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 172:65be27845400 25341 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 172:65be27845400 25342 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 172:65be27845400 25343 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 172:65be27845400 25344 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 172:65be27845400 25345 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 172:65be27845400 25346 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 172:65be27845400 25347 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 172:65be27845400 25348 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 172:65be27845400 25349 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 172:65be27845400 25350 ((INSTANCE) == DMA2_Stream7) || \
AnnaBridge 172:65be27845400 25351 ((INSTANCE) == BDMA_Channel0) || \
AnnaBridge 172:65be27845400 25352 ((INSTANCE) == BDMA_Channel1) || \
AnnaBridge 172:65be27845400 25353 ((INSTANCE) == BDMA_Channel2) || \
AnnaBridge 172:65be27845400 25354 ((INSTANCE) == BDMA_Channel3) || \
AnnaBridge 172:65be27845400 25355 ((INSTANCE) == BDMA_Channel4) || \
AnnaBridge 172:65be27845400 25356 ((INSTANCE) == BDMA_Channel5) || \
AnnaBridge 172:65be27845400 25357 ((INSTANCE) == BDMA_Channel6) || \
AnnaBridge 172:65be27845400 25358 ((INSTANCE) == BDMA_Channel7))
AnnaBridge 172:65be27845400 25359
AnnaBridge 172:65be27845400 25360 /****************************** BDMA DMAMUX Instances ***************************/
AnnaBridge 172:65be27845400 25361 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
AnnaBridge 172:65be27845400 25362 ((INSTANCE) == BDMA_Channel1) || \
AnnaBridge 172:65be27845400 25363 ((INSTANCE) == BDMA_Channel2) || \
AnnaBridge 172:65be27845400 25364 ((INSTANCE) == BDMA_Channel3) || \
AnnaBridge 172:65be27845400 25365 ((INSTANCE) == BDMA_Channel4) || \
AnnaBridge 172:65be27845400 25366 ((INSTANCE) == BDMA_Channel5) || \
AnnaBridge 172:65be27845400 25367 ((INSTANCE) == BDMA_Channel6) || \
AnnaBridge 172:65be27845400 25368 ((INSTANCE) == BDMA_Channel7))
AnnaBridge 172:65be27845400 25369
AnnaBridge 172:65be27845400 25370 /****************************** DMA STREAM Instances ***************************/
AnnaBridge 172:65be27845400 25371 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 172:65be27845400 25372 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 172:65be27845400 25373 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 172:65be27845400 25374 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 172:65be27845400 25375 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 172:65be27845400 25376 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 172:65be27845400 25377 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 172:65be27845400 25378 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 172:65be27845400 25379 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 172:65be27845400 25380 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 172:65be27845400 25381 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 172:65be27845400 25382 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 172:65be27845400 25383 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 172:65be27845400 25384 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 172:65be27845400 25385 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 172:65be27845400 25386 ((INSTANCE) == DMA2_Stream7))
AnnaBridge 172:65be27845400 25387
AnnaBridge 172:65be27845400 25388 /****************************** DMA DMAMUX Instances ***************************/
AnnaBridge 172:65be27845400 25389 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
AnnaBridge 172:65be27845400 25390 ((INSTANCE) == DMA1_Stream1) || \
AnnaBridge 172:65be27845400 25391 ((INSTANCE) == DMA1_Stream2) || \
AnnaBridge 172:65be27845400 25392 ((INSTANCE) == DMA1_Stream3) || \
AnnaBridge 172:65be27845400 25393 ((INSTANCE) == DMA1_Stream4) || \
AnnaBridge 172:65be27845400 25394 ((INSTANCE) == DMA1_Stream5) || \
AnnaBridge 172:65be27845400 25395 ((INSTANCE) == DMA1_Stream6) || \
AnnaBridge 172:65be27845400 25396 ((INSTANCE) == DMA1_Stream7) || \
AnnaBridge 172:65be27845400 25397 ((INSTANCE) == DMA2_Stream0) || \
AnnaBridge 172:65be27845400 25398 ((INSTANCE) == DMA2_Stream1) || \
AnnaBridge 172:65be27845400 25399 ((INSTANCE) == DMA2_Stream2) || \
AnnaBridge 172:65be27845400 25400 ((INSTANCE) == DMA2_Stream3) || \
AnnaBridge 172:65be27845400 25401 ((INSTANCE) == DMA2_Stream4) || \
AnnaBridge 172:65be27845400 25402 ((INSTANCE) == DMA2_Stream5) || \
AnnaBridge 172:65be27845400 25403 ((INSTANCE) == DMA2_Stream6) || \
AnnaBridge 172:65be27845400 25404 ((INSTANCE) == DMA2_Stream7))
AnnaBridge 172:65be27845400 25405
AnnaBridge 172:65be27845400 25406 /******************************** DMA Request Generator Instances **************/
AnnaBridge 172:65be27845400 25407 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
AnnaBridge 172:65be27845400 25408 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
AnnaBridge 172:65be27845400 25409 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
AnnaBridge 172:65be27845400 25410 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
AnnaBridge 172:65be27845400 25411 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
AnnaBridge 172:65be27845400 25412 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
AnnaBridge 172:65be27845400 25413 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
AnnaBridge 172:65be27845400 25414 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
AnnaBridge 172:65be27845400 25415 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
AnnaBridge 172:65be27845400 25416 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
AnnaBridge 172:65be27845400 25417 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
AnnaBridge 172:65be27845400 25418 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
AnnaBridge 172:65be27845400 25419 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
AnnaBridge 172:65be27845400 25420 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
AnnaBridge 172:65be27845400 25421 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
AnnaBridge 172:65be27845400 25422 ((INSTANCE) == DMAMUX2_RequestGenerator7))
AnnaBridge 172:65be27845400 25423
AnnaBridge 172:65be27845400 25424 /******************************* DMA2D Instances *******************************/
AnnaBridge 172:65be27845400 25425 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
AnnaBridge 172:65be27845400 25426
AnnaBridge 172:65be27845400 25427 /******************************** MDMA Request Generator Instances **************/
AnnaBridge 172:65be27845400 25428 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
AnnaBridge 172:65be27845400 25429 ((INSTANCE) == MDMA_Channel1) || \
AnnaBridge 172:65be27845400 25430 ((INSTANCE) == MDMA_Channel2) || \
AnnaBridge 172:65be27845400 25431 ((INSTANCE) == MDMA_Channel3) || \
AnnaBridge 172:65be27845400 25432 ((INSTANCE) == MDMA_Channel4) || \
AnnaBridge 172:65be27845400 25433 ((INSTANCE) == MDMA_Channel5) || \
AnnaBridge 172:65be27845400 25434 ((INSTANCE) == MDMA_Channel6) || \
AnnaBridge 172:65be27845400 25435 ((INSTANCE) == MDMA_Channel7) || \
AnnaBridge 172:65be27845400 25436 ((INSTANCE) == MDMA_Channel8) || \
AnnaBridge 172:65be27845400 25437 ((INSTANCE) == MDMA_Channel9) || \
AnnaBridge 172:65be27845400 25438 ((INSTANCE) == MDMA_Channel10) || \
AnnaBridge 172:65be27845400 25439 ((INSTANCE) == MDMA_Channel11) || \
AnnaBridge 172:65be27845400 25440 ((INSTANCE) == MDMA_Channel12) || \
AnnaBridge 172:65be27845400 25441 ((INSTANCE) == MDMA_Channel13) || \
AnnaBridge 172:65be27845400 25442 ((INSTANCE) == MDMA_Channel14) || \
AnnaBridge 172:65be27845400 25443 ((INSTANCE) == MDMA_Channel15))
AnnaBridge 172:65be27845400 25444
AnnaBridge 172:65be27845400 25445 /******************************* QUADSPI Instances *******************************/
AnnaBridge 172:65be27845400 25446 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
AnnaBridge 172:65be27845400 25447
AnnaBridge 172:65be27845400 25448 /******************************* FDCAN Instances ******************************/
AnnaBridge 172:65be27845400 25449 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
AnnaBridge 172:65be27845400 25450 ((__INSTANCE__) == FDCAN2))
AnnaBridge 172:65be27845400 25451
AnnaBridge 172:65be27845400 25452 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
AnnaBridge 172:65be27845400 25453
AnnaBridge 172:65be27845400 25454 /******************************* GPIO Instances *******************************/
AnnaBridge 172:65be27845400 25455 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 172:65be27845400 25456 ((INSTANCE) == GPIOB) || \
AnnaBridge 172:65be27845400 25457 ((INSTANCE) == GPIOC) || \
AnnaBridge 172:65be27845400 25458 ((INSTANCE) == GPIOD) || \
AnnaBridge 172:65be27845400 25459 ((INSTANCE) == GPIOE) || \
AnnaBridge 172:65be27845400 25460 ((INSTANCE) == GPIOF) || \
AnnaBridge 172:65be27845400 25461 ((INSTANCE) == GPIOG) || \
AnnaBridge 172:65be27845400 25462 ((INSTANCE) == GPIOH) || \
AnnaBridge 172:65be27845400 25463 ((INSTANCE) == GPIOI) || \
AnnaBridge 172:65be27845400 25464 ((INSTANCE) == GPIOJ) || \
AnnaBridge 172:65be27845400 25465 ((INSTANCE) == GPIOK))
AnnaBridge 172:65be27845400 25466
AnnaBridge 172:65be27845400 25467 /******************************* GPIO AF Instances ****************************/
AnnaBridge 172:65be27845400 25468 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
AnnaBridge 172:65be27845400 25469
AnnaBridge 172:65be27845400 25470 /**************************** GPIO Lock Instances *****************************/
AnnaBridge 172:65be27845400 25471 /* On H7, all GPIO Bank support the Lock mechanism */
AnnaBridge 172:65be27845400 25472 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
AnnaBridge 172:65be27845400 25473
AnnaBridge 172:65be27845400 25474 /******************************** HSEM Instances *******************************/
AnnaBridge 172:65be27845400 25475 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
AnnaBridge 172:65be27845400 25476 #define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
AnnaBridge 172:65be27845400 25477 #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
AnnaBridge 172:65be27845400 25478
AnnaBridge 172:65be27845400 25479 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
AnnaBridge 172:65be27845400 25480 #define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
AnnaBridge 172:65be27845400 25481
AnnaBridge 172:65be27845400 25482 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
AnnaBridge 172:65be27845400 25483 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
AnnaBridge 172:65be27845400 25484
AnnaBridge 172:65be27845400 25485 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
AnnaBridge 172:65be27845400 25486 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
AnnaBridge 172:65be27845400 25487
AnnaBridge 172:65be27845400 25488 /******************************** I2C Instances *******************************/
AnnaBridge 172:65be27845400 25489 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 172:65be27845400 25490 ((INSTANCE) == I2C2) || \
AnnaBridge 172:65be27845400 25491 ((INSTANCE) == I2C3) || \
AnnaBridge 172:65be27845400 25492 ((INSTANCE) == I2C4))
AnnaBridge 172:65be27845400 25493 /************** I2C Instances : wakeup capability from stop modes *************/
AnnaBridge 172:65be27845400 25494 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
AnnaBridge 172:65be27845400 25495
AnnaBridge 172:65be27845400 25496 /****************************** SMBUS Instances *******************************/
AnnaBridge 172:65be27845400 25497 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 172:65be27845400 25498 ((INSTANCE) == I2C2) || \
AnnaBridge 172:65be27845400 25499 ((INSTANCE) == I2C3) || \
AnnaBridge 172:65be27845400 25500 ((INSTANCE) == I2C4))
AnnaBridge 172:65be27845400 25501 /******************************** I2S Instances *******************************/
AnnaBridge 172:65be27845400 25502 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 172:65be27845400 25503 ((INSTANCE) == SPI2) || \
AnnaBridge 172:65be27845400 25504 ((INSTANCE) == SPI3))
AnnaBridge 172:65be27845400 25505
AnnaBridge 172:65be27845400 25506 /****************************** LTDC Instances ********************************/
AnnaBridge 172:65be27845400 25507 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
AnnaBridge 172:65be27845400 25508
AnnaBridge 172:65be27845400 25509 /******************************* RNG Instances ********************************/
AnnaBridge 172:65be27845400 25510 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
AnnaBridge 172:65be27845400 25511
AnnaBridge 172:65be27845400 25512 /****************************** RTC Instances *********************************/
AnnaBridge 172:65be27845400 25513 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 172:65be27845400 25514
AnnaBridge 172:65be27845400 25515 /****************************** SDMMC Instances *********************************/
AnnaBridge 172:65be27845400 25516 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
AnnaBridge 172:65be27845400 25517 ((_INSTANCE_) == SDMMC2))
AnnaBridge 172:65be27845400 25518
AnnaBridge 172:65be27845400 25519 /******************************** SMBUS Instances *****************************/
AnnaBridge 172:65be27845400 25520 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
AnnaBridge 172:65be27845400 25521
AnnaBridge 172:65be27845400 25522 /******************************** SPI Instances *******************************/
AnnaBridge 172:65be27845400 25523 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 172:65be27845400 25524 ((INSTANCE) == SPI2) || \
AnnaBridge 172:65be27845400 25525 ((INSTANCE) == SPI3) || \
AnnaBridge 172:65be27845400 25526 ((INSTANCE) == SPI4) || \
AnnaBridge 172:65be27845400 25527 ((INSTANCE) == SPI5) || \
AnnaBridge 172:65be27845400 25528 ((INSTANCE) == SPI6))
AnnaBridge 172:65be27845400 25529
AnnaBridge 172:65be27845400 25530 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 172:65be27845400 25531 ((INSTANCE) == SPI2) || \
AnnaBridge 172:65be27845400 25532 ((INSTANCE) == SPI3))
AnnaBridge 172:65be27845400 25533
AnnaBridge 172:65be27845400 25534 /******************************** SWPMI Instances *****************************/
AnnaBridge 172:65be27845400 25535 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
AnnaBridge 172:65be27845400 25536
AnnaBridge 172:65be27845400 25537 /****************** LPTIM Instances : All supported instances *****************/
AnnaBridge 172:65be27845400 25538 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
AnnaBridge 172:65be27845400 25539 ((INSTANCE) == LPTIM2) || \
AnnaBridge 172:65be27845400 25540 ((INSTANCE) == LPTIM3) || \
AnnaBridge 172:65be27845400 25541 ((INSTANCE) == LPTIM4) || \
AnnaBridge 172:65be27845400 25542 ((INSTANCE) == LPTIM5))
AnnaBridge 172:65be27845400 25543
AnnaBridge 172:65be27845400 25544 /****************** LPTIM Instances : supporting encoder interface **************/
AnnaBridge 172:65be27845400 25545 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
AnnaBridge 172:65be27845400 25546 ((INSTANCE) == LPTIM2))
AnnaBridge 172:65be27845400 25547
AnnaBridge 172:65be27845400 25548 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 172:65be27845400 25549 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25550 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25551 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25552 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25553 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25554 ((INSTANCE) == TIM6) || \
AnnaBridge 172:65be27845400 25555 ((INSTANCE) == TIM7) || \
AnnaBridge 172:65be27845400 25556 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25557 ((INSTANCE) == TIM12) || \
AnnaBridge 172:65be27845400 25558 ((INSTANCE) == TIM13) || \
AnnaBridge 172:65be27845400 25559 ((INSTANCE) == TIM14) || \
AnnaBridge 172:65be27845400 25560 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25561 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25562 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25563 /************* TIM Instances : at least 1 capture/compare channel *************/
AnnaBridge 172:65be27845400 25564 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25565 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25566 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25567 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25568 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25569 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25570 ((INSTANCE) == TIM12) || \
AnnaBridge 172:65be27845400 25571 ((INSTANCE) == TIM13) || \
AnnaBridge 172:65be27845400 25572 ((INSTANCE) == TIM14) || \
AnnaBridge 172:65be27845400 25573 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25574 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25575 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25576 /************ TIM Instances : at least 2 capture/compare channels *************/
AnnaBridge 172:65be27845400 25577 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25578 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25579 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25580 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25581 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25582 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25583 ((INSTANCE) == TIM12) || \
AnnaBridge 172:65be27845400 25584 ((INSTANCE) == TIM15))
AnnaBridge 172:65be27845400 25585 /************ TIM Instances : at least 3 capture/compare channels *************/
AnnaBridge 172:65be27845400 25586 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25587 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25588 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25589 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25590 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25591 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25592
AnnaBridge 172:65be27845400 25593 /************ TIM Instances : at least 4 capture/compare channels *************/
AnnaBridge 172:65be27845400 25594 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25595 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25596 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25597 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25598 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25599 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25600 /************ TIM Instances : at least 5 capture/compare channels *************/
AnnaBridge 172:65be27845400 25601 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25602 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25603 /************ TIM Instances : at least 6 capture/compare channels *************/
AnnaBridge 172:65be27845400 25604 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25605 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25606
AnnaBridge 172:65be27845400 25607 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 172:65be27845400 25608 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 172:65be27845400 25609 ((__INSTANCE__) == TIM8))
AnnaBridge 172:65be27845400 25610
AnnaBridge 172:65be27845400 25611 /******************** TIM Instances : Advanced-control timers *****************/
AnnaBridge 172:65be27845400 25612
AnnaBridge 172:65be27845400 25613 /******************* TIM Instances : Timer input XOR function *****************/
AnnaBridge 172:65be27845400 25614 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25615 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25616 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25617 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25618 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25619 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25620 ((INSTANCE) == TIM15))
AnnaBridge 172:65be27845400 25621
AnnaBridge 172:65be27845400 25622 /****************** TIM Instances : DMA requests generation (UDE) *************/
AnnaBridge 172:65be27845400 25623 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25624 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25625 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25626 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25627 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25628 ((INSTANCE) == TIM6) || \
AnnaBridge 172:65be27845400 25629 ((INSTANCE) == TIM7) || \
AnnaBridge 172:65be27845400 25630 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25631 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25632 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25633 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25634
AnnaBridge 172:65be27845400 25635 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
AnnaBridge 172:65be27845400 25636 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25637 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25638 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25639 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25640 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25641 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25642 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25643 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25644 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25645
AnnaBridge 172:65be27845400 25646 /************ TIM Instances : DMA requests generation (COMDE) *****************/
AnnaBridge 172:65be27845400 25647 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25648 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25649 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25650 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25651 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25652 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25653 ((INSTANCE) == TIM15))
AnnaBridge 172:65be27845400 25654
AnnaBridge 172:65be27845400 25655 /******************** TIM Instances : DMA burst feature ***********************/
AnnaBridge 172:65be27845400 25656 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25657 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25658 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25659 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25660 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25661 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25662
AnnaBridge 172:65be27845400 25663 /*************** TIM Instances : external trigger reamp input available *******/
AnnaBridge 172:65be27845400 25664 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25665 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25666 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25667 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25668 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25669 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25670 /****************** TIM Instances : remapping capability **********************/
AnnaBridge 172:65be27845400 25671 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 172:65be27845400 25672 ((__INSTANCE__) == TIM2) || \
AnnaBridge 172:65be27845400 25673 ((__INSTANCE__) == TIM3) || \
AnnaBridge 172:65be27845400 25674 ((__INSTANCE__) == TIM5) || \
AnnaBridge 172:65be27845400 25675 ((__INSTANCE__) == TIM16) || \
AnnaBridge 172:65be27845400 25676 ((__INSTANCE__) == TIM17))
AnnaBridge 172:65be27845400 25677
AnnaBridge 172:65be27845400 25678 /*************** TIM Instances : external trigger reamp input available *******/
AnnaBridge 172:65be27845400 25679 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25680 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25681 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25682 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25683 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25684
AnnaBridge 172:65be27845400 25685 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 172:65be27845400 25686 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25687 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25688 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25689 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25690 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25691 ((INSTANCE) == TIM6) || \
AnnaBridge 172:65be27845400 25692 ((INSTANCE) == TIM7) || \
AnnaBridge 172:65be27845400 25693 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25694 ((INSTANCE) == TIM15))
AnnaBridge 172:65be27845400 25695 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
AnnaBridge 172:65be27845400 25696 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25697 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25698 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25699 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25700 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25701 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25702 ((INSTANCE) == TIM12))
AnnaBridge 172:65be27845400 25703
AnnaBridge 172:65be27845400 25704 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
AnnaBridge 172:65be27845400 25705 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25706 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25707
AnnaBridge 172:65be27845400 25708 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
AnnaBridge 172:65be27845400 25709 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25710 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25711 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25712 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25713 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25714 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25715 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25716 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25717 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25718
AnnaBridge 172:65be27845400 25719 /****************** TIM Instances : supporting commutation event *************/
AnnaBridge 172:65be27845400 25720 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25721 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25722 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25723 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25724 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25725
AnnaBridge 172:65be27845400 25726 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 172:65be27845400 25727 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 172:65be27845400 25728 ((__INSTANCE__) == TIM2) || \
AnnaBridge 172:65be27845400 25729 ((__INSTANCE__) == TIM3) || \
AnnaBridge 172:65be27845400 25730 ((__INSTANCE__) == TIM4) || \
AnnaBridge 172:65be27845400 25731 ((__INSTANCE__) == TIM5) || \
AnnaBridge 172:65be27845400 25732 ((__INSTANCE__) == TIM8))
AnnaBridge 172:65be27845400 25733
AnnaBridge 172:65be27845400 25734 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
AnnaBridge 172:65be27845400 25735 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25736 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25737 /******************* TIM Instances : output(s) available **********************/
AnnaBridge 172:65be27845400 25738 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 172:65be27845400 25739 ((((INSTANCE) == TIM1) && \
AnnaBridge 172:65be27845400 25740 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25741 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25742 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 25743 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 172:65be27845400 25744 ((CHANNEL) == TIM_CHANNEL_5) || \
AnnaBridge 172:65be27845400 25745 ((CHANNEL) == TIM_CHANNEL_6))) \
AnnaBridge 172:65be27845400 25746 || \
AnnaBridge 172:65be27845400 25747 (((INSTANCE) == TIM2) && \
AnnaBridge 172:65be27845400 25748 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25749 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25750 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 25751 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 25752 || \
AnnaBridge 172:65be27845400 25753 (((INSTANCE) == TIM3) && \
AnnaBridge 172:65be27845400 25754 (((CHANNEL) == TIM_CHANNEL_1)|| \
AnnaBridge 172:65be27845400 25755 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25756 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 25757 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 25758 || \
AnnaBridge 172:65be27845400 25759 (((INSTANCE) == TIM4) && \
AnnaBridge 172:65be27845400 25760 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25761 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25762 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 25763 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 25764 || \
AnnaBridge 172:65be27845400 25765 (((INSTANCE) == TIM5) && \
AnnaBridge 172:65be27845400 25766 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25767 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25768 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 25769 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 172:65be27845400 25770 || \
AnnaBridge 172:65be27845400 25771 (((INSTANCE) == TIM8) && \
AnnaBridge 172:65be27845400 25772 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25773 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25774 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 25775 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 172:65be27845400 25776 ((CHANNEL) == TIM_CHANNEL_5) || \
AnnaBridge 172:65be27845400 25777 ((CHANNEL) == TIM_CHANNEL_6))) \
AnnaBridge 172:65be27845400 25778 || \
AnnaBridge 172:65be27845400 25779 (((INSTANCE) == TIM12) && \
AnnaBridge 172:65be27845400 25780 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25781 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 172:65be27845400 25782 || \
AnnaBridge 172:65be27845400 25783 (((INSTANCE) == TIM13) && \
AnnaBridge 172:65be27845400 25784 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 172:65be27845400 25785 || \
AnnaBridge 172:65be27845400 25786 (((INSTANCE) == TIM14) && \
AnnaBridge 172:65be27845400 25787 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 172:65be27845400 25788 || \
AnnaBridge 172:65be27845400 25789 (((INSTANCE) == TIM15) && \
AnnaBridge 172:65be27845400 25790 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25791 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 172:65be27845400 25792 || \
AnnaBridge 172:65be27845400 25793 (((INSTANCE) == TIM16) && \
AnnaBridge 172:65be27845400 25794 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 172:65be27845400 25795 || \
AnnaBridge 172:65be27845400 25796 (((INSTANCE) == TIM17) && \
AnnaBridge 172:65be27845400 25797 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 172:65be27845400 25798
AnnaBridge 172:65be27845400 25799 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 172:65be27845400 25800 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25801 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25802 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25803 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25804 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25805 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25806
AnnaBridge 172:65be27845400 25807 /************** TIM Instances : supporting Break source selection *************/
AnnaBridge 172:65be27845400 25808 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25809 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25810
AnnaBridge 172:65be27845400 25811 /****************** TIM Instances : supporting complementary output(s) ********/
AnnaBridge 172:65be27845400 25812 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 172:65be27845400 25813 ((((INSTANCE) == TIM1) && \
AnnaBridge 172:65be27845400 25814 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25815 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25816 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 172:65be27845400 25817 || \
AnnaBridge 172:65be27845400 25818 (((INSTANCE) == TIM8) && \
AnnaBridge 172:65be27845400 25819 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 25820 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 25821 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 172:65be27845400 25822 || \
AnnaBridge 172:65be27845400 25823 (((INSTANCE) == TIM15) && \
AnnaBridge 172:65be27845400 25824 ((CHANNEL) == TIM_CHANNEL_1)) \
AnnaBridge 172:65be27845400 25825 || \
AnnaBridge 172:65be27845400 25826 (((INSTANCE) == TIM16) && \
AnnaBridge 172:65be27845400 25827 ((CHANNEL) == TIM_CHANNEL_1)) \
AnnaBridge 172:65be27845400 25828 || \
AnnaBridge 172:65be27845400 25829 (((INSTANCE) == TIM17) && \
AnnaBridge 172:65be27845400 25830 ((CHANNEL) == TIM_CHANNEL_1)))
AnnaBridge 172:65be27845400 25831
AnnaBridge 172:65be27845400 25832 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 172:65be27845400 25833 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25834 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25835 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25836 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25837 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25838 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25839 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25840
AnnaBridge 172:65be27845400 25841 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 172:65be27845400 25842 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25843 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25844 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25845 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25846 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25847 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25848
AnnaBridge 172:65be27845400 25849 /****************** TIM Instances : supporting synchronization ****************/
AnnaBridge 172:65be27845400 25850 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
AnnaBridge 172:65be27845400 25851 (((__INSTANCE__) == TIM1) || \
AnnaBridge 172:65be27845400 25852 ((__INSTANCE__) == TIM2) || \
AnnaBridge 172:65be27845400 25853 ((__INSTANCE__) == TIM3) || \
AnnaBridge 172:65be27845400 25854 ((__INSTANCE__) == TIM4) || \
AnnaBridge 172:65be27845400 25855 ((__INSTANCE__) == TIM5) || \
AnnaBridge 172:65be27845400 25856 ((__INSTANCE__) == TIM8) || \
AnnaBridge 172:65be27845400 25857 ((__INSTANCE__) == TIM12) || \
AnnaBridge 172:65be27845400 25858 ((__INSTANCE__) == TIM15))
AnnaBridge 172:65be27845400 25859
AnnaBridge 172:65be27845400 25860 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 172:65be27845400 25861 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25862 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25863 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25864 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25865 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25866 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25867 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25868 ((INSTANCE) == TIM15) || \
AnnaBridge 172:65be27845400 25869 ((INSTANCE) == TIM16) || \
AnnaBridge 172:65be27845400 25870 ((INSTANCE) == TIM17))
AnnaBridge 172:65be27845400 25871 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
AnnaBridge 172:65be27845400 25872 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25873 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25874 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25875 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25876 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25877 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25878 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25879
AnnaBridge 172:65be27845400 25880 /****************** TIM Instances : supporting external clock mode 2 **********/
AnnaBridge 172:65be27845400 25881 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25882 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25883 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25884 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25885 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25886 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25887 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25888 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
AnnaBridge 172:65be27845400 25889 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25890 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25891 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25892 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25893 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25894 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25895 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25896 ((INSTANCE) == TIM15))
AnnaBridge 172:65be27845400 25897
AnnaBridge 172:65be27845400 25898 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
AnnaBridge 172:65be27845400 25899 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25900 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25901 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25902 ((INSTANCE) == TIM3) || \
AnnaBridge 172:65be27845400 25903 ((INSTANCE) == TIM4) || \
AnnaBridge 172:65be27845400 25904 ((INSTANCE) == TIM5) || \
AnnaBridge 172:65be27845400 25905 ((INSTANCE) == TIM8) || \
AnnaBridge 172:65be27845400 25906 ((INSTANCE) == TIM15))
AnnaBridge 172:65be27845400 25907
AnnaBridge 172:65be27845400 25908 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 172:65be27845400 25909 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25910 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25911 ((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25912 ((INSTANCE) == TIM3))
AnnaBridge 172:65be27845400 25913 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
AnnaBridge 172:65be27845400 25914 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25915 (((INSTANCE) == TIM2) || \
AnnaBridge 172:65be27845400 25916 ((INSTANCE) == TIM5))
AnnaBridge 172:65be27845400 25917
AnnaBridge 172:65be27845400 25918 /****************** TIM Instances : TIM_BKIN2 ***************************/
AnnaBridge 172:65be27845400 25919 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
AnnaBridge 172:65be27845400 25920 (((INSTANCE) == TIM1) || \
AnnaBridge 172:65be27845400 25921 ((INSTANCE) == TIM8))
AnnaBridge 172:65be27845400 25922
AnnaBridge 172:65be27845400 25923 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 172:65be27845400 25924 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
AnnaBridge 172:65be27845400 25925 ((__INSTANCE__) == TIM2) || \
AnnaBridge 172:65be27845400 25926 ((__INSTANCE__) == TIM3) || \
AnnaBridge 172:65be27845400 25927 ((__INSTANCE__) == TIM4) || \
AnnaBridge 172:65be27845400 25928 ((__INSTANCE__) == TIM5) || \
AnnaBridge 172:65be27845400 25929 ((__INSTANCE__) == TIM15) || \
AnnaBridge 172:65be27845400 25930 ((__INSTANCE__) == TIM8))
AnnaBridge 172:65be27845400 25931
AnnaBridge 172:65be27845400 25932 /****************************** HRTIM Instances *******************************/
AnnaBridge 172:65be27845400 25933 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
AnnaBridge 172:65be27845400 25934
AnnaBridge 172:65be27845400 25935 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 172:65be27845400 25936 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 25937 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 25938 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 25939 ((INSTANCE) == USART6))
AnnaBridge 172:65be27845400 25940
AnnaBridge 172:65be27845400 25941 /******************** USART Instances : SPI slave mode ************************/
AnnaBridge 172:65be27845400 25942 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 25943 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 25944 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 25945 ((INSTANCE) == USART6))
AnnaBridge 172:65be27845400 25946
AnnaBridge 172:65be27845400 25947 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 172:65be27845400 25948 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 25949 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 25950 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 25951 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 25952 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 25953 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 25954 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 25955 ((INSTANCE) == UART8))
AnnaBridge 172:65be27845400 25956
AnnaBridge 172:65be27845400 25957 /******************** UART Instances : FIFO mode.******************************/
AnnaBridge 172:65be27845400 25958 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 25959 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 25960 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 25961 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 25962 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 25963 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 25964 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 25965 ((INSTANCE) == UART8))
AnnaBridge 172:65be27845400 25966
AnnaBridge 172:65be27845400 25967 /****************** UART Instances : Auto Baud Rate detection *****************/
AnnaBridge 172:65be27845400 25968 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 25969 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 25970 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 25971 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 25972 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 25973 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 25974 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 25975 ((INSTANCE) == UART8))
AnnaBridge 172:65be27845400 25976
AnnaBridge 172:65be27845400 25977 /*********************** UART Instances : Driver Enable ***********************/
AnnaBridge 172:65be27845400 25978 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 25979 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 25980 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 25981 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 25982 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 25983 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 25984 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 25985 ((INSTANCE) == UART8) || \
AnnaBridge 172:65be27845400 25986 ((INSTANCE) == LPUART1))
AnnaBridge 172:65be27845400 25987
AnnaBridge 172:65be27845400 25988 /********************* UART Instances : Half-Duplex mode **********************/
AnnaBridge 172:65be27845400 25989 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 25990 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 25991 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 25992 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 25993 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 25994 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 25995 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 25996 ((INSTANCE) == UART8) || \
AnnaBridge 172:65be27845400 25997 ((INSTANCE) == LPUART1))
AnnaBridge 172:65be27845400 25998
AnnaBridge 172:65be27845400 25999 /******************* UART Instances : Hardware Flow control *******************/
AnnaBridge 172:65be27845400 26000 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 26001 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 26002 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 26003 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 26004 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 26005 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 26006 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 26007 ((INSTANCE) == UART8) || \
AnnaBridge 172:65be27845400 26008 ((INSTANCE) == LPUART1))
AnnaBridge 172:65be27845400 26009
AnnaBridge 172:65be27845400 26010 /************************* UART Instances : LIN mode **************************/
AnnaBridge 172:65be27845400 26011 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 26012 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 26013 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 26014 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 26015 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 26016 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 26017 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 26018 ((INSTANCE) == UART8))
AnnaBridge 172:65be27845400 26019
AnnaBridge 172:65be27845400 26020 /****************** UART Instances : Wake-up from Stop mode *******************/
AnnaBridge 172:65be27845400 26021 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 26022 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 26023 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 26024 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 26025 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 26026 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 26027 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 26028 ((INSTANCE) == UART8) || \
AnnaBridge 172:65be27845400 26029 ((INSTANCE) == LPUART1))
AnnaBridge 172:65be27845400 26030
AnnaBridge 172:65be27845400 26031 /************************* UART Instances : IRDA mode *************************/
AnnaBridge 172:65be27845400 26032 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 26033 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 26034 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 26035 ((INSTANCE) == UART4) || \
AnnaBridge 172:65be27845400 26036 ((INSTANCE) == UART5) || \
AnnaBridge 172:65be27845400 26037 ((INSTANCE) == USART6) || \
AnnaBridge 172:65be27845400 26038 ((INSTANCE) == UART7) || \
AnnaBridge 172:65be27845400 26039 ((INSTANCE) == UART8))
AnnaBridge 172:65be27845400 26040
AnnaBridge 172:65be27845400 26041 /********************* USART Instances : Smard card mode **********************/
AnnaBridge 172:65be27845400 26042 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 172:65be27845400 26043 ((INSTANCE) == USART2) || \
AnnaBridge 172:65be27845400 26044 ((INSTANCE) == USART3) || \
AnnaBridge 172:65be27845400 26045 ((INSTANCE) == USART6))
AnnaBridge 172:65be27845400 26046
AnnaBridge 172:65be27845400 26047 /****************************** LPUART Instance *******************************/
AnnaBridge 172:65be27845400 26048 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
AnnaBridge 172:65be27845400 26049
AnnaBridge 172:65be27845400 26050 /****************************** IWDG Instances ********************************/
AnnaBridge 172:65be27845400 26051 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
AnnaBridge 172:65be27845400 26052 /****************************** USB Instances ********************************/
AnnaBridge 172:65be27845400 26053 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
AnnaBridge 172:65be27845400 26054
AnnaBridge 172:65be27845400 26055 /****************************** WWDG Instances ********************************/
AnnaBridge 172:65be27845400 26056 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
AnnaBridge 172:65be27845400 26057 /****************************** MDIOS Instances ********************************/
AnnaBridge 172:65be27845400 26058 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
AnnaBridge 172:65be27845400 26059
AnnaBridge 172:65be27845400 26060 /****************************** CEC Instances *********************************/
AnnaBridge 172:65be27845400 26061 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
AnnaBridge 172:65be27845400 26062
AnnaBridge 172:65be27845400 26063 /****************************** SAI Instances ********************************/
AnnaBridge 172:65be27845400 26064 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
AnnaBridge 172:65be27845400 26065 ((INSTANCE) == SAI1_Block_B) || \
AnnaBridge 172:65be27845400 26066 ((INSTANCE) == SAI2_Block_A) || \
AnnaBridge 172:65be27845400 26067 ((INSTANCE) == SAI2_Block_B) || \
AnnaBridge 172:65be27845400 26068 ((INSTANCE) == SAI3_Block_A) || \
AnnaBridge 172:65be27845400 26069 ((INSTANCE) == SAI3_Block_B) || \
AnnaBridge 172:65be27845400 26070 ((INSTANCE) == SAI4_Block_A) || \
AnnaBridge 172:65be27845400 26071 ((INSTANCE) == SAI4_Block_B))
AnnaBridge 172:65be27845400 26072
AnnaBridge 172:65be27845400 26073 /****************************** SPDIFRX Instances ********************************/
AnnaBridge 172:65be27845400 26074 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
AnnaBridge 172:65be27845400 26075
AnnaBridge 172:65be27845400 26076 /****************************** OPAMP Instances *******************************/
AnnaBridge 172:65be27845400 26077 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
AnnaBridge 172:65be27845400 26078 ((INSTANCE) == OPAMP2))
AnnaBridge 172:65be27845400 26079
AnnaBridge 172:65be27845400 26080 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
AnnaBridge 172:65be27845400 26081
AnnaBridge 172:65be27845400 26082 /*********************** USB OTG PCD Instances ********************************/
AnnaBridge 172:65be27845400 26083 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
AnnaBridge 172:65be27845400 26084 ((INSTANCE) == USB_OTG_HS))
AnnaBridge 172:65be27845400 26085
AnnaBridge 172:65be27845400 26086 /*********************** USB OTG HCD Instances ********************************/
AnnaBridge 172:65be27845400 26087 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
AnnaBridge 172:65be27845400 26088 ((INSTANCE) == USB_OTG_HS))
AnnaBridge 172:65be27845400 26089
AnnaBridge 172:65be27845400 26090 /******************************************************************************/
AnnaBridge 172:65be27845400 26091 /* For a painless codes migration between the STM32H7xx device product */
AnnaBridge 172:65be27845400 26092 /* lines, or with STM32F7xx devices the aliases defined below are put */
AnnaBridge 172:65be27845400 26093 /* in place to overcome the differences in the interrupt handlers and IRQn */
AnnaBridge 172:65be27845400 26094 /* definitions. No need to update developed interrupt code when moving */
AnnaBridge 172:65be27845400 26095 /* across product lines within the same STM32H7 Family */
AnnaBridge 172:65be27845400 26096 /******************************************************************************/
AnnaBridge 172:65be27845400 26097
AnnaBridge 172:65be27845400 26098 /* Aliases for __IRQn */
AnnaBridge 172:65be27845400 26099 #define HASH_RNG_IRQn RNG_IRQn
AnnaBridge 172:65be27845400 26100 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
AnnaBridge 172:65be27845400 26101 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
AnnaBridge 172:65be27845400 26102 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
AnnaBridge 172:65be27845400 26103 #define PVD_IRQn PVD_AVD_IRQn
AnnaBridge 172:65be27845400 26104
AnnaBridge 172:65be27845400 26105
AnnaBridge 172:65be27845400 26106 /* Aliases for __IRQHandler */
AnnaBridge 172:65be27845400 26107 #define HASH_RNG_IRQHandler RNG_IRQHandler
AnnaBridge 172:65be27845400 26108 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
AnnaBridge 172:65be27845400 26109 #define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
AnnaBridge 172:65be27845400 26110 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
AnnaBridge 172:65be27845400 26111 #define PVD_IRQHandler PVD_AVD_IRQHandler
AnnaBridge 172:65be27845400 26112
AnnaBridge 172:65be27845400 26113 /**
AnnaBridge 172:65be27845400 26114 * @}
AnnaBridge 172:65be27845400 26115 */
AnnaBridge 172:65be27845400 26116 /****************************** Product define *********************************/
AnnaBridge 172:65be27845400 26117 #define FLASH_SIZE 0x200000UL /* 2 MB */
AnnaBridge 172:65be27845400 26118 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
AnnaBridge 172:65be27845400 26119 #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
AnnaBridge 172:65be27845400 26120
AnnaBridge 172:65be27845400 26121
AnnaBridge 172:65be27845400 26122
AnnaBridge 172:65be27845400 26123 /**
AnnaBridge 172:65be27845400 26124 * @}
AnnaBridge 172:65be27845400 26125 */
AnnaBridge 172:65be27845400 26126
AnnaBridge 172:65be27845400 26127 /**
AnnaBridge 172:65be27845400 26128 * @}
AnnaBridge 172:65be27845400 26129 */
AnnaBridge 172:65be27845400 26130
AnnaBridge 172:65be27845400 26131 #ifdef __cplusplus
AnnaBridge 172:65be27845400 26132 }
AnnaBridge 172:65be27845400 26133 #endif /* __cplusplus */
AnnaBridge 172:65be27845400 26134
AnnaBridge 172:65be27845400 26135 #endif /* STM32H743xx_H */
AnnaBridge 172:65be27845400 26136
AnnaBridge 172:65be27845400 26137 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/