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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_STD/stm32h7xx_ll_spi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_spi.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of SPI LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef STM32H7xx_LL_SPI_H
AnnaBridge	172:65be27845400	22	#define STM32H7xx_LL_SPI_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	#if defined(SPI1) \|\| defined(SPI2) \|\| defined(SPI3) \|\| defined(SPI4) \|\| defined(SPI5) \|\| defined(SPI6)
AnnaBridge	172:65be27845400	36
AnnaBridge	172:65be27845400	37	/** @defgroup SPI_LL SPI
AnnaBridge	172:65be27845400	38	* @{
AnnaBridge	172:65be27845400	39	*/
AnnaBridge	172:65be27845400	40
AnnaBridge	172:65be27845400	41	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	42
AnnaBridge	172:65be27845400	43	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	44
AnnaBridge	172:65be27845400	45	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	46	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	47	/** @defgroup SPI_LL_Private_Macros SPI Private Macros
AnnaBridge	172:65be27845400	48	* @{
AnnaBridge	172:65be27845400	49	*/
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	/**
AnnaBridge	172:65be27845400	52	* @brief SPI Init structures definition
AnnaBridge	172:65be27845400	53	*/
AnnaBridge	172:65be27845400	54	typedef struct
AnnaBridge	172:65be27845400	55	{
AnnaBridge	172:65be27845400	56	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	172:65be27845400	57	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	172:65be27845400	58
AnnaBridge	172:65be27845400	59	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	172:65be27845400	60
AnnaBridge	172:65be27845400	61	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	172:65be27845400	62	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	172:65be27845400	63
AnnaBridge	172:65be27845400	64	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	172:65be27845400	65
AnnaBridge	172:65be27845400	66	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	172:65be27845400	67	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	172:65be27845400	68
AnnaBridge	172:65be27845400	69	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	172:65be27845400	70
AnnaBridge	172:65be27845400	71	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	172:65be27845400	72	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	172:65be27845400	73
AnnaBridge	172:65be27845400	74	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	172:65be27845400	75
AnnaBridge	172:65be27845400	76	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	172:65be27845400	77	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	172:65be27845400	78
AnnaBridge	172:65be27845400	79	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	172:65be27845400	80
AnnaBridge	172:65be27845400	81	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	172:65be27845400	82	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	172:65be27845400	83
AnnaBridge	172:65be27845400	84	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	172:65be27845400	85
AnnaBridge	172:65be27845400	86	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	172:65be27845400	87	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	172:65be27845400	88	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	172:65be27845400	89
AnnaBridge	172:65be27845400	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	172:65be27845400	91
AnnaBridge	172:65be27845400	92	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	172:65be27845400	93	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	172:65be27845400	94
AnnaBridge	172:65be27845400	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	172:65be27845400	96
AnnaBridge	172:65be27845400	97	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	172:65be27845400	98	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	172:65be27845400	99
AnnaBridge	172:65be27845400	100	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	172:65be27845400	101
AnnaBridge	172:65be27845400	102	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	172:65be27845400	103	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF.
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	172:65be27845400	106
AnnaBridge	172:65be27845400	107	} LL_SPI_InitTypeDef;
AnnaBridge	172:65be27845400	108
AnnaBridge	172:65be27845400	109	/**
AnnaBridge	172:65be27845400	110	* @}
AnnaBridge	172:65be27845400	111	*/
AnnaBridge	172:65be27845400	112	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	172:65be27845400	113
AnnaBridge	172:65be27845400	114	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	115
AnnaBridge	172:65be27845400	116	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	117	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	172:65be27845400	118	* @{
AnnaBridge	172:65be27845400	119	*/
AnnaBridge	172:65be27845400	120
AnnaBridge	172:65be27845400	121	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	172:65be27845400	122	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	172:65be27845400	123	* @{
AnnaBridge	172:65be27845400	124	*/
AnnaBridge	172:65be27845400	125	#define LL_SPI_SR_RXP (SPI_SR_RXP)
AnnaBridge	172:65be27845400	126	#define LL_SPI_SR_TXP (SPI_SR_TXP)
AnnaBridge	172:65be27845400	127	#define LL_SPI_SR_DXP (SPI_SR_DXP)
AnnaBridge	172:65be27845400	128	#define LL_SPI_SR_EOT (SPI_SR_EOT)
AnnaBridge	172:65be27845400	129	#define LL_SPI_SR_TXTF (SPI_SR_TXTF)
AnnaBridge	172:65be27845400	130	#define LL_SPI_SR_UDR (SPI_SR_UDR)
AnnaBridge	172:65be27845400	131	#define LL_SPI_SR_CRCERR (SPI_SR_CRCERR)
AnnaBridge	172:65be27845400	132	#define LL_SPI_SR_MODF (SPI_SR_MODF)
AnnaBridge	172:65be27845400	133	#define LL_SPI_SR_OVR (SPI_SR_OVR)
AnnaBridge	172:65be27845400	134	#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
AnnaBridge	172:65be27845400	135	#define LL_SPI_SR_TSERF (SPI_SR_TSERF)
AnnaBridge	172:65be27845400	136	#define LL_SPI_SR_SUSP (SPI_SR_SUSP)
AnnaBridge	172:65be27845400	137	#define LL_SPI_SR_TXC (SPI_SR_TXC)
AnnaBridge	172:65be27845400	138	#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
AnnaBridge	172:65be27845400	139	/**
AnnaBridge	172:65be27845400	140	* @}
AnnaBridge	172:65be27845400	141	*/
AnnaBridge	172:65be27845400	142
AnnaBridge	172:65be27845400	143	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	172:65be27845400	144	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	172:65be27845400	145	* @{
AnnaBridge	172:65be27845400	146	*/
AnnaBridge	172:65be27845400	147	#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
AnnaBridge	172:65be27845400	148	#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
AnnaBridge	172:65be27845400	149	#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
AnnaBridge	172:65be27845400	150	#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
AnnaBridge	172:65be27845400	151	#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
AnnaBridge	172:65be27845400	152	#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
AnnaBridge	172:65be27845400	153	#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
AnnaBridge	172:65be27845400	154	#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
AnnaBridge	172:65be27845400	155	#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
AnnaBridge	172:65be27845400	156	#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
AnnaBridge	172:65be27845400	157	#define LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)
AnnaBridge	172:65be27845400	158	/**
AnnaBridge	172:65be27845400	159	* @}
AnnaBridge	172:65be27845400	160	*/
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	/** @defgroup SPI_LL_EC_MODE Mode
AnnaBridge	172:65be27845400	163	* @{
AnnaBridge	172:65be27845400	164	*/
AnnaBridge	172:65be27845400	165	#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
AnnaBridge	172:65be27845400	166	#define LL_SPI_MODE_SLAVE (0x00000000UL)
AnnaBridge	172:65be27845400	167	/**
AnnaBridge	172:65be27845400	168	* @}
AnnaBridge	172:65be27845400	169	*/
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	/** @defgroup SPI_LL_EC_SS_LEVEL SS Level
AnnaBridge	172:65be27845400	172	* @{
AnnaBridge	172:65be27845400	173	*/
AnnaBridge	172:65be27845400	174	#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
AnnaBridge	172:65be27845400	175	#define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
AnnaBridge	172:65be27845400	176	/**
AnnaBridge	172:65be27845400	177	* @}
AnnaBridge	172:65be27845400	178	*/
AnnaBridge	172:65be27845400	179
AnnaBridge	172:65be27845400	180	/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
AnnaBridge	172:65be27845400	181	* @{
AnnaBridge	172:65be27845400	182	*/
AnnaBridge	172:65be27845400	183	#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
AnnaBridge	172:65be27845400	184	#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
AnnaBridge	172:65be27845400	185	#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
AnnaBridge	172:65be27845400	186	#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 \| SPI_CFG2_MSSI_1)
AnnaBridge	172:65be27845400	187	#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
AnnaBridge	172:65be27845400	188	#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 \| SPI_CFG2_MSSI_0)
AnnaBridge	172:65be27845400	189	#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 \| SPI_CFG2_MSSI_1)
AnnaBridge	172:65be27845400	190	#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 \| SPI_CFG2_MSSI_1 \| SPI_CFG2_MSSI_0)
AnnaBridge	172:65be27845400	191	#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
AnnaBridge	172:65be27845400	192	#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 \| SPI_CFG2_MSSI_0)
AnnaBridge	172:65be27845400	193	#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 \| SPI_CFG2_MSSI_1)
AnnaBridge	172:65be27845400	194	#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 \| SPI_CFG2_MSSI_1 \| SPI_CFG2_MSSI_0)
AnnaBridge	172:65be27845400	195	#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 \| SPI_CFG2_MSSI_2)
AnnaBridge	172:65be27845400	196	#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 \| SPI_CFG2_MSSI_2 \| SPI_CFG2_MSSI_0)
AnnaBridge	172:65be27845400	197	#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 \| SPI_CFG2_MSSI_2 \| SPI_CFG2_MSSI_1)
AnnaBridge	172:65be27845400	198	#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3 \| SPI_CFG2_MSSI_2 \| SPI_CFG2_MSSI_1 \| SPI_CFG2_MSSI_0)
AnnaBridge	172:65be27845400	199	/**
AnnaBridge	172:65be27845400	200	* @}
AnnaBridge	172:65be27845400	201	*/
AnnaBridge	172:65be27845400	202
AnnaBridge	172:65be27845400	203	/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
AnnaBridge	172:65be27845400	204	* @{
AnnaBridge	172:65be27845400	205	*/
AnnaBridge	172:65be27845400	206	#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
AnnaBridge	172:65be27845400	207	#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
AnnaBridge	172:65be27845400	208	#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
AnnaBridge	172:65be27845400	209	#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 \| SPI_CFG2_MIDI_1)
AnnaBridge	172:65be27845400	210	#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
AnnaBridge	172:65be27845400	211	#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 \| SPI_CFG2_MIDI_0)
AnnaBridge	172:65be27845400	212	#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 \| SPI_CFG2_MIDI_1)
AnnaBridge	172:65be27845400	213	#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 \| SPI_CFG2_MIDI_1 \| SPI_CFG2_MIDI_0)
AnnaBridge	172:65be27845400	214	#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
AnnaBridge	172:65be27845400	215	#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 \| SPI_CFG2_MIDI_0)
AnnaBridge	172:65be27845400	216	#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 \| SPI_CFG2_MIDI_1)
AnnaBridge	172:65be27845400	217	#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 \| SPI_CFG2_MIDI_1 \| SPI_CFG2_MIDI_0)
AnnaBridge	172:65be27845400	218	#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 \| SPI_CFG2_MIDI_2)
AnnaBridge	172:65be27845400	219	#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 \| SPI_CFG2_MIDI_2 \| SPI_CFG2_MIDI_0)
AnnaBridge	172:65be27845400	220	#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 \| SPI_CFG2_MIDI_2 \| SPI_CFG2_MIDI_1)
AnnaBridge	172:65be27845400	221	#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3 \| SPI_CFG2_MIDI_2 \| SPI_CFG2_MIDI_1 \| SPI_CFG2_MIDI_0)
AnnaBridge	172:65be27845400	222	/**
AnnaBridge	172:65be27845400	223	* @}
AnnaBridge	172:65be27845400	224	*/
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
AnnaBridge	172:65be27845400	227	* @{
AnnaBridge	172:65be27845400	228	*/
AnnaBridge	172:65be27845400	229	#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
AnnaBridge	172:65be27845400	230	#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
AnnaBridge	172:65be27845400	231	/**
AnnaBridge	172:65be27845400	232	* @}
AnnaBridge	172:65be27845400	233	*/
AnnaBridge	172:65be27845400	234
AnnaBridge	172:65be27845400	235	/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
AnnaBridge	172:65be27845400	236	* @{
AnnaBridge	172:65be27845400	237	*/
AnnaBridge	172:65be27845400	238	#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
AnnaBridge	172:65be27845400	239	#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
AnnaBridge	172:65be27845400	240	/**
AnnaBridge	172:65be27845400	241	* @}
AnnaBridge	172:65be27845400	242	*/
AnnaBridge	172:65be27845400	243
AnnaBridge	172:65be27845400	244	/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
AnnaBridge	172:65be27845400	245	* @{
AnnaBridge	172:65be27845400	246	*/
AnnaBridge	172:65be27845400	247	#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
AnnaBridge	172:65be27845400	248	#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)
AnnaBridge	172:65be27845400	249	#define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)
AnnaBridge	172:65be27845400	250	/**
AnnaBridge	172:65be27845400	251	* @}
AnnaBridge	172:65be27845400	252	*/
AnnaBridge	172:65be27845400	253
AnnaBridge	172:65be27845400	254	/** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data
AnnaBridge	172:65be27845400	255	* @{
AnnaBridge	172:65be27845400	256	*/
AnnaBridge	172:65be27845400	257	#define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
AnnaBridge	172:65be27845400	258	#define LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)
AnnaBridge	172:65be27845400	259	#define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)
AnnaBridge	172:65be27845400	260	/**
AnnaBridge	172:65be27845400	261	* @}
AnnaBridge	172:65be27845400	262	*/
AnnaBridge	172:65be27845400	263
AnnaBridge	172:65be27845400	264	/** @defgroup SPI_LL_EC_PROTOCOL Protocol
AnnaBridge	172:65be27845400	265	* @{
AnnaBridge	172:65be27845400	266	*/
AnnaBridge	172:65be27845400	267	#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
AnnaBridge	172:65be27845400	268	#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
AnnaBridge	172:65be27845400	269	/**
AnnaBridge	172:65be27845400	270	* @}
AnnaBridge	172:65be27845400	271	*/
AnnaBridge	172:65be27845400	272
AnnaBridge	172:65be27845400	273	/** @defgroup SPI_LL_EC_PHASE Phase
AnnaBridge	172:65be27845400	274	* @{
AnnaBridge	172:65be27845400	275	*/
AnnaBridge	172:65be27845400	276	#define LL_SPI_PHASE_1EDGE (0x00000000UL)
AnnaBridge	172:65be27845400	277	#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
AnnaBridge	172:65be27845400	278	/**
AnnaBridge	172:65be27845400	279	* @}
AnnaBridge	172:65be27845400	280	*/
AnnaBridge	172:65be27845400	281
AnnaBridge	172:65be27845400	282	/** @defgroup SPI_LL_EC_POLARITY Polarity
AnnaBridge	172:65be27845400	283	* @{
AnnaBridge	172:65be27845400	284	*/
AnnaBridge	172:65be27845400	285	#define LL_SPI_POLARITY_LOW (0x00000000UL)
AnnaBridge	172:65be27845400	286	#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
AnnaBridge	172:65be27845400	287	/**
AnnaBridge	172:65be27845400	288	* @}
AnnaBridge	172:65be27845400	289	*/
AnnaBridge	172:65be27845400	290
AnnaBridge	172:65be27845400	291	/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
AnnaBridge	172:65be27845400	292	* @{
AnnaBridge	172:65be27845400	293	*/
AnnaBridge	172:65be27845400	294	#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
AnnaBridge	172:65be27845400	295	#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
AnnaBridge	172:65be27845400	296	/**
AnnaBridge	172:65be27845400	297	* @}
AnnaBridge	172:65be27845400	298	*/
AnnaBridge	172:65be27845400	299
AnnaBridge	172:65be27845400	300	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	172:65be27845400	301	* @{
AnnaBridge	172:65be27845400	302	*/
AnnaBridge	172:65be27845400	303	#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
AnnaBridge	172:65be27845400	304	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
AnnaBridge	172:65be27845400	305	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
AnnaBridge	172:65be27845400	306	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 \| SPI_CFG1_MBR_0)
AnnaBridge	172:65be27845400	307	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
AnnaBridge	172:65be27845400	308	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 \| SPI_CFG1_MBR_0)
AnnaBridge	172:65be27845400	309	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 \| SPI_CFG1_MBR_1)
AnnaBridge	172:65be27845400	310	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 \| SPI_CFG1_MBR_1 \| SPI_CFG1_MBR_0)
AnnaBridge	172:65be27845400	311	/**
AnnaBridge	172:65be27845400	312	* @}
AnnaBridge	172:65be27845400	313	*/
AnnaBridge	172:65be27845400	314
AnnaBridge	172:65be27845400	315	/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
AnnaBridge	172:65be27845400	316	* @{
AnnaBridge	172:65be27845400	317	*/
AnnaBridge	172:65be27845400	318	#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
AnnaBridge	172:65be27845400	319	#define LL_SPI_MSB_FIRST (0x00000000UL)
AnnaBridge	172:65be27845400	320	/**
AnnaBridge	172:65be27845400	321	* @}
AnnaBridge	172:65be27845400	322	*/
AnnaBridge	172:65be27845400	323
AnnaBridge	172:65be27845400	324	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	172:65be27845400	325	* @{
AnnaBridge	172:65be27845400	326	*/
AnnaBridge	172:65be27845400	327	#define LL_SPI_FULL_DUPLEX (0x00000000UL)
AnnaBridge	172:65be27845400	328	#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
AnnaBridge	172:65be27845400	329	#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
AnnaBridge	172:65be27845400	330	#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0\|SPI_CFG2_COMM_1)
AnnaBridge	172:65be27845400	331	#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0\|SPI_CFG2_COMM_1\|SPI_CR1_HDDIR)
AnnaBridge	172:65be27845400	332	/**
AnnaBridge	172:65be27845400	333	* @}
AnnaBridge	172:65be27845400	334	*/
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	/** @defgroup SPI_LL_EC_DATAWIDTH Data Width
AnnaBridge	172:65be27845400	337	* @{
AnnaBridge	172:65be27845400	338	*/
AnnaBridge	172:65be27845400	339	#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	340	#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
AnnaBridge	172:65be27845400	341	#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	342	#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	343	#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	344	#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
AnnaBridge	172:65be27845400	345	#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	346	#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	347	#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_1 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	348	#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2)
AnnaBridge	172:65be27845400	349	#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	350	#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	351	#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	352	#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
AnnaBridge	172:65be27845400	353	#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	354	#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	355	#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_0 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	356	#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_2)
AnnaBridge	172:65be27845400	357	#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	358	#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	359	#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	360	#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3)
AnnaBridge	172:65be27845400	361	#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	362	#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	363	#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_1 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	364	#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2)
AnnaBridge	172:65be27845400	365	#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	366	#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1)
AnnaBridge	172:65be27845400	367	#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 \| SPI_CFG1_DSIZE_3 \| SPI_CFG1_DSIZE_2 \| SPI_CFG1_DSIZE_1 \| SPI_CFG1_DSIZE_0)
AnnaBridge	172:65be27845400	368	/**
AnnaBridge	172:65be27845400	369	* @}
AnnaBridge	172:65be27845400	370	*/
AnnaBridge	172:65be27845400	371
AnnaBridge	172:65be27845400	372	/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
AnnaBridge	172:65be27845400	373	* @{
AnnaBridge	172:65be27845400	374	*/
AnnaBridge	172:65be27845400	375	#define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
AnnaBridge	172:65be27845400	376	#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
AnnaBridge	172:65be27845400	377	#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
AnnaBridge	172:65be27845400	378	#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 \| SPI_CFG1_FTHLV_1)
AnnaBridge	172:65be27845400	379	#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
AnnaBridge	172:65be27845400	380	#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 \| SPI_CFG1_FTHLV_0)
AnnaBridge	172:65be27845400	381	#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 \| SPI_CFG1_FTHLV_1)
AnnaBridge	172:65be27845400	382	#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 \| SPI_CFG1_FTHLV_1 \| SPI_CFG1_FTHLV_0)
AnnaBridge	172:65be27845400	383	#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
AnnaBridge	172:65be27845400	384	#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 \| SPI_CFG1_FTHLV_0)
AnnaBridge	172:65be27845400	385	#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 \| SPI_CFG1_FTHLV_1)
AnnaBridge	172:65be27845400	386	#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 \| SPI_CFG1_FTHLV_1 \| SPI_CFG1_FTHLV_0)
AnnaBridge	172:65be27845400	387	#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 \| SPI_CFG1_FTHLV_2)
AnnaBridge	172:65be27845400	388	#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 \| SPI_CFG1_FTHLV_2 \| SPI_CFG1_FTHLV_0)
AnnaBridge	172:65be27845400	389	#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 \| SPI_CFG1_FTHLV_2 \| SPI_CFG1_FTHLV_1)
AnnaBridge	172:65be27845400	390	#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3 \| SPI_CFG1_FTHLV_2 \| SPI_CFG1_FTHLV_1 \| SPI_CFG1_FTHLV_0)
AnnaBridge	172:65be27845400	391	/**
AnnaBridge	172:65be27845400	392	* @}
AnnaBridge	172:65be27845400	393	*/
AnnaBridge	172:65be27845400	394
AnnaBridge	172:65be27845400	395	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	396
AnnaBridge	172:65be27845400	397	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	172:65be27845400	398	* @{
AnnaBridge	172:65be27845400	399	*/
AnnaBridge	172:65be27845400	400	#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /!< CRC calculation disabled /
AnnaBridge	172:65be27845400	401	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	172:65be27845400	402	/**
AnnaBridge	172:65be27845400	403	* @}
AnnaBridge	172:65be27845400	404	*/
AnnaBridge	172:65be27845400	405	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	406
AnnaBridge	172:65be27845400	407	/** @defgroup SPI_LL_EC_CRC CRC
AnnaBridge	172:65be27845400	408	* @{
AnnaBridge	172:65be27845400	409	*/
AnnaBridge	172:65be27845400	410	#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	411	#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
AnnaBridge	172:65be27845400	412	#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	413	#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	414	#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	415	#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
AnnaBridge	172:65be27845400	416	#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	417	#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	418	#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_1 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	419	#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2)
AnnaBridge	172:65be27845400	420	#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	421	#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	422	#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	423	#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
AnnaBridge	172:65be27845400	424	#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	425	#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	426	#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_0 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	427	#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_2)
AnnaBridge	172:65be27845400	428	#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	429	#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	430	#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	431	#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3)
AnnaBridge	172:65be27845400	432	#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	433	#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	434	#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_1 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	435	#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2)
AnnaBridge	172:65be27845400	436	#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	437	#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1)
AnnaBridge	172:65be27845400	438	#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 \| SPI_CFG1_CRCSIZE_3 \| SPI_CFG1_CRCSIZE_2 \| SPI_CFG1_CRCSIZE_1 \| SPI_CFG1_CRCSIZE_0)
AnnaBridge	172:65be27845400	439	/**
AnnaBridge	172:65be27845400	440	* @}
AnnaBridge	172:65be27845400	441	*/
AnnaBridge	172:65be27845400	442
AnnaBridge	172:65be27845400	443	/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
AnnaBridge	172:65be27845400	444	* @{
AnnaBridge	172:65be27845400	445	*/
AnnaBridge	172:65be27845400	446	#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
AnnaBridge	172:65be27845400	447	#define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
AnnaBridge	172:65be27845400	448	#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
AnnaBridge	172:65be27845400	449	/**
AnnaBridge	172:65be27845400	450	* @}
AnnaBridge	172:65be27845400	451	*/
AnnaBridge	172:65be27845400	452
AnnaBridge	172:65be27845400	453	/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
AnnaBridge	172:65be27845400	454	* @{
AnnaBridge	172:65be27845400	455	*/
AnnaBridge	172:65be27845400	456	#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
AnnaBridge	172:65be27845400	457	#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
AnnaBridge	172:65be27845400	458	#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
AnnaBridge	172:65be27845400	459	#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 \| SPI_SR_RXPLVL_0)
AnnaBridge	172:65be27845400	460	/**
AnnaBridge	172:65be27845400	461	* @}
AnnaBridge	172:65be27845400	462	*/
AnnaBridge	172:65be27845400	463
AnnaBridge	172:65be27845400	464	/**
AnnaBridge	172:65be27845400	465	* @}
AnnaBridge	172:65be27845400	466	*/
AnnaBridge	172:65be27845400	467
AnnaBridge	172:65be27845400	468	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	469	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	172:65be27845400	470	* @{
AnnaBridge	172:65be27845400	471	*/
AnnaBridge	172:65be27845400	472
AnnaBridge	172:65be27845400	473	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	172:65be27845400	474	* @{
AnnaBridge	172:65be27845400	475	*/
AnnaBridge	172:65be27845400	476
AnnaBridge	172:65be27845400	477	/**
AnnaBridge	172:65be27845400	478	* @brief Write a value in SPI register
AnnaBridge	172:65be27845400	479	* @param __INSTANCE__ SPI Instance
AnnaBridge	172:65be27845400	480	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	481	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	482	* @retval None
AnnaBridge	172:65be27845400	483	*/
AnnaBridge	172:65be27845400	484	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	485
AnnaBridge	172:65be27845400	486	/**
AnnaBridge	172:65be27845400	487	* @brief Read a value in SPI register
AnnaBridge	172:65be27845400	488	* @param __INSTANCE__ SPI Instance
AnnaBridge	172:65be27845400	489	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	490	* @retval Register value
AnnaBridge	172:65be27845400	491	*/
AnnaBridge	172:65be27845400	492	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	172:65be27845400	493	/**
AnnaBridge	172:65be27845400	494	* @}
AnnaBridge	172:65be27845400	495	*/
AnnaBridge	172:65be27845400	496
AnnaBridge	172:65be27845400	497	/**
AnnaBridge	172:65be27845400	498	* @}
AnnaBridge	172:65be27845400	499	*/
AnnaBridge	172:65be27845400	500
AnnaBridge	172:65be27845400	501
AnnaBridge	172:65be27845400	502	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	503
AnnaBridge	172:65be27845400	504	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	172:65be27845400	505	* @{
AnnaBridge	172:65be27845400	506	*/
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	172:65be27845400	509	* @{
AnnaBridge	172:65be27845400	510	*/
AnnaBridge	172:65be27845400	511
AnnaBridge	172:65be27845400	512	/**
AnnaBridge	172:65be27845400	513	* @brief Enable SPI peripheral
AnnaBridge	172:65be27845400	514	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	172:65be27845400	515	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	516	* @retval None
AnnaBridge	172:65be27845400	517	*/
AnnaBridge	172:65be27845400	518	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	519	{
AnnaBridge	172:65be27845400	520	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	172:65be27845400	521	}
AnnaBridge	172:65be27845400	522
AnnaBridge	172:65be27845400	523	/**
AnnaBridge	172:65be27845400	524	* @brief Disable SPI peripheral
AnnaBridge	172:65be27845400	525	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	172:65be27845400	526	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	172:65be27845400	527	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	528	* @retval None
AnnaBridge	172:65be27845400	529	*/
AnnaBridge	172:65be27845400	530	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	531	{
AnnaBridge	172:65be27845400	532	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	172:65be27845400	533	}
AnnaBridge	172:65be27845400	534
AnnaBridge	172:65be27845400	535	/**
AnnaBridge	172:65be27845400	536	* @brief Check if SPI peripheral is enabled
AnnaBridge	172:65be27845400	537	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	172:65be27845400	538	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	539	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	540	*/
AnnaBridge	172:65be27845400	541	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	542	{
AnnaBridge	172:65be27845400	543	return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	544	}
AnnaBridge	172:65be27845400	545
AnnaBridge	172:65be27845400	546	/**
AnnaBridge	172:65be27845400	547	* @brief Swap the MOSI and MISO pin
AnnaBridge	172:65be27845400	548	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	549	* @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
AnnaBridge	172:65be27845400	550	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	551	* @retval None
AnnaBridge	172:65be27845400	552	*/
AnnaBridge	172:65be27845400	553	__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	554	{
AnnaBridge	172:65be27845400	555	SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
AnnaBridge	172:65be27845400	556	}
AnnaBridge	172:65be27845400	557
AnnaBridge	172:65be27845400	558	/**
AnnaBridge	172:65be27845400	559	* @brief Restore default function for MOSI and MISO pin
AnnaBridge	172:65be27845400	560	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	561	* @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
AnnaBridge	172:65be27845400	562	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	563	* @retval None
AnnaBridge	172:65be27845400	564	*/
AnnaBridge	172:65be27845400	565	__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	566	{
AnnaBridge	172:65be27845400	567	CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
AnnaBridge	172:65be27845400	568	}
AnnaBridge	172:65be27845400	569
AnnaBridge	172:65be27845400	570	/**
AnnaBridge	172:65be27845400	571	* @brief Check if MOSI and MISO pin are swapped
AnnaBridge	172:65be27845400	572	* @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
AnnaBridge	172:65be27845400	573	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	574	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	575	*/
AnnaBridge	172:65be27845400	576	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	577	{
AnnaBridge	172:65be27845400	578	return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	579	}
AnnaBridge	172:65be27845400	580
AnnaBridge	172:65be27845400	581	/**
AnnaBridge	172:65be27845400	582	* @brief Enable GPIO control
AnnaBridge	172:65be27845400	583	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	584	* @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
AnnaBridge	172:65be27845400	585	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	586	* @retval None
AnnaBridge	172:65be27845400	587	*/
AnnaBridge	172:65be27845400	588	__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	589	{
AnnaBridge	172:65be27845400	590	SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
AnnaBridge	172:65be27845400	591	}
AnnaBridge	172:65be27845400	592
AnnaBridge	172:65be27845400	593	/**
AnnaBridge	172:65be27845400	594	* @brief Disable GPIO control
AnnaBridge	172:65be27845400	595	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	596	* @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
AnnaBridge	172:65be27845400	597	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	598	* @retval None
AnnaBridge	172:65be27845400	599	*/
AnnaBridge	172:65be27845400	600	__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	601	{
AnnaBridge	172:65be27845400	602	CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
AnnaBridge	172:65be27845400	603	}
AnnaBridge	172:65be27845400	604
AnnaBridge	172:65be27845400	605	/**
AnnaBridge	172:65be27845400	606	* @brief Check if GPIO control is active
AnnaBridge	172:65be27845400	607	* @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
AnnaBridge	172:65be27845400	608	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	609	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	610	*/
AnnaBridge	172:65be27845400	611	__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	612	{
AnnaBridge	172:65be27845400	613	return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	614	}
AnnaBridge	172:65be27845400	615
AnnaBridge	172:65be27845400	616	/**
AnnaBridge	172:65be27845400	617	* @brief Set SPI Mode to Master or Slave
AnnaBridge	172:65be27845400	618	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	619	* @rmtoll CFG2 MASTER LL_SPI_SetMode
AnnaBridge	172:65be27845400	620	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	621	* @param Mode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	622	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	172:65be27845400	623	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	172:65be27845400	624	* @retval None
AnnaBridge	172:65be27845400	625	*/
AnnaBridge	172:65be27845400	626	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	172:65be27845400	627	{
AnnaBridge	172:65be27845400	628	MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
AnnaBridge	172:65be27845400	629	}
AnnaBridge	172:65be27845400	630
AnnaBridge	172:65be27845400	631	/**
AnnaBridge	172:65be27845400	632	* @brief Get SPI Mode (Master or Slave)
AnnaBridge	172:65be27845400	633	* @rmtoll CFG2 MASTER LL_SPI_GetMode
AnnaBridge	172:65be27845400	634	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	635	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	636	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	172:65be27845400	637	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	172:65be27845400	638	*/
AnnaBridge	172:65be27845400	639	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	640	{
AnnaBridge	172:65be27845400	641	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
AnnaBridge	172:65be27845400	642	}
AnnaBridge	172:65be27845400	643
AnnaBridge	172:65be27845400	644	/**
AnnaBridge	172:65be27845400	645	* @brief Configure the Idleness applied by master between active edge of SS and first send data
AnnaBridge	172:65be27845400	646	* @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
AnnaBridge	172:65be27845400	647	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	648	* @param MasterSSIdleness This parameter can be one of the following values:
AnnaBridge	172:65be27845400	649	* @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
AnnaBridge	172:65be27845400	650	* @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
AnnaBridge	172:65be27845400	651	* @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
AnnaBridge	172:65be27845400	652	* @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
AnnaBridge	172:65be27845400	653	* @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
AnnaBridge	172:65be27845400	654	* @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
AnnaBridge	172:65be27845400	655	* @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
AnnaBridge	172:65be27845400	656	* @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
AnnaBridge	172:65be27845400	657	* @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
AnnaBridge	172:65be27845400	658	* @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
AnnaBridge	172:65be27845400	659	* @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
AnnaBridge	172:65be27845400	660	* @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
AnnaBridge	172:65be27845400	661	* @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
AnnaBridge	172:65be27845400	662	* @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
AnnaBridge	172:65be27845400	663	* @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
AnnaBridge	172:65be27845400	664	* @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
AnnaBridge	172:65be27845400	665	* @retval None
AnnaBridge	172:65be27845400	666	*/
AnnaBridge	172:65be27845400	667	__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
AnnaBridge	172:65be27845400	668	{
AnnaBridge	172:65be27845400	669	MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
AnnaBridge	172:65be27845400	670	}
AnnaBridge	172:65be27845400	671
AnnaBridge	172:65be27845400	672	/**
AnnaBridge	172:65be27845400	673	* @brief Get the configured Idleness applied by master
AnnaBridge	172:65be27845400	674	* @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
AnnaBridge	172:65be27845400	675	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	676	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	677	* @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
AnnaBridge	172:65be27845400	678	* @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
AnnaBridge	172:65be27845400	679	* @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
AnnaBridge	172:65be27845400	680	* @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
AnnaBridge	172:65be27845400	681	* @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
AnnaBridge	172:65be27845400	682	* @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
AnnaBridge	172:65be27845400	683	* @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
AnnaBridge	172:65be27845400	684	* @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
AnnaBridge	172:65be27845400	685	* @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
AnnaBridge	172:65be27845400	686	* @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
AnnaBridge	172:65be27845400	687	* @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
AnnaBridge	172:65be27845400	688	* @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
AnnaBridge	172:65be27845400	689	* @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
AnnaBridge	172:65be27845400	690	* @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
AnnaBridge	172:65be27845400	691	* @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
AnnaBridge	172:65be27845400	692	* @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
AnnaBridge	172:65be27845400	693	*/
AnnaBridge	172:65be27845400	694	__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	695	{
AnnaBridge	172:65be27845400	696	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
AnnaBridge	172:65be27845400	697	}
AnnaBridge	172:65be27845400	698
AnnaBridge	172:65be27845400	699	/**
AnnaBridge	172:65be27845400	700	* @brief Configure the idleness applied by master between data frame
AnnaBridge	172:65be27845400	701	* @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
AnnaBridge	172:65be27845400	702	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	703	* @param MasterInterDataIdleness This parameter can be one of the following values:
AnnaBridge	172:65be27845400	704	* @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
AnnaBridge	172:65be27845400	705	* @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
AnnaBridge	172:65be27845400	706	* @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
AnnaBridge	172:65be27845400	707	* @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
AnnaBridge	172:65be27845400	708	* @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
AnnaBridge	172:65be27845400	709	* @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
AnnaBridge	172:65be27845400	710	* @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
AnnaBridge	172:65be27845400	711	* @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
AnnaBridge	172:65be27845400	712	* @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
AnnaBridge	172:65be27845400	713	* @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
AnnaBridge	172:65be27845400	714	* @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
AnnaBridge	172:65be27845400	715	* @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
AnnaBridge	172:65be27845400	716	* @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
AnnaBridge	172:65be27845400	717	* @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
AnnaBridge	172:65be27845400	718	* @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
AnnaBridge	172:65be27845400	719	* @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
AnnaBridge	172:65be27845400	720	* @retval None
AnnaBridge	172:65be27845400	721	*/
AnnaBridge	172:65be27845400	722	__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
AnnaBridge	172:65be27845400	723	{
AnnaBridge	172:65be27845400	724	MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
AnnaBridge	172:65be27845400	725	}
AnnaBridge	172:65be27845400	726
AnnaBridge	172:65be27845400	727	/**
AnnaBridge	172:65be27845400	728	* @brief Get the configured inter data idleness
AnnaBridge	172:65be27845400	729	* @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
AnnaBridge	172:65be27845400	730	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	731	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	732	* @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
AnnaBridge	172:65be27845400	733	* @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
AnnaBridge	172:65be27845400	734	* @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
AnnaBridge	172:65be27845400	735	* @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
AnnaBridge	172:65be27845400	736	* @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
AnnaBridge	172:65be27845400	737	* @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
AnnaBridge	172:65be27845400	738	* @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
AnnaBridge	172:65be27845400	739	* @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
AnnaBridge	172:65be27845400	740	* @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
AnnaBridge	172:65be27845400	741	* @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
AnnaBridge	172:65be27845400	742	* @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
AnnaBridge	172:65be27845400	743	* @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
AnnaBridge	172:65be27845400	744	* @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
AnnaBridge	172:65be27845400	745	* @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
AnnaBridge	172:65be27845400	746	* @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
AnnaBridge	172:65be27845400	747	* @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
AnnaBridge	172:65be27845400	748	*/
AnnaBridge	172:65be27845400	749	__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	750	{
AnnaBridge	172:65be27845400	751	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
AnnaBridge	172:65be27845400	752	}
AnnaBridge	172:65be27845400	753
AnnaBridge	172:65be27845400	754	/**
AnnaBridge	172:65be27845400	755	* @brief Set transfer size
AnnaBridge	172:65be27845400	756	* @note Count is the number of frame to be transferred
AnnaBridge	172:65be27845400	757	* @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
AnnaBridge	172:65be27845400	758	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	759	* @param Count 0..0xFFFF
AnnaBridge	172:65be27845400	760	* @retval None
AnnaBridge	172:65be27845400	761	*/
AnnaBridge	172:65be27845400	762	__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
AnnaBridge	172:65be27845400	763	{
AnnaBridge	172:65be27845400	764	MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
AnnaBridge	172:65be27845400	765	}
AnnaBridge	172:65be27845400	766
AnnaBridge	172:65be27845400	767	/**
AnnaBridge	172:65be27845400	768	* @brief Get transfer size
AnnaBridge	172:65be27845400	769	* @note Count is the number of frame to be transferred
AnnaBridge	172:65be27845400	770	* @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
AnnaBridge	172:65be27845400	771	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	772	* @retval 0..0xFFFF
AnnaBridge	172:65be27845400	773	*/
AnnaBridge	172:65be27845400	774	__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	775	{
AnnaBridge	172:65be27845400	776	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
AnnaBridge	172:65be27845400	777	}
AnnaBridge	172:65be27845400	778
AnnaBridge	172:65be27845400	779	/**
AnnaBridge	172:65be27845400	780	* @brief Set reload transfer size
AnnaBridge	172:65be27845400	781	* @note Count is the number of frame to be transferred
AnnaBridge	172:65be27845400	782	* @rmtoll CR2 TSER LL_SPI_SetReloadSize
AnnaBridge	172:65be27845400	783	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	784	* @param Count 0..0xFFFF
AnnaBridge	172:65be27845400	785	* @retval None
AnnaBridge	172:65be27845400	786	*/
AnnaBridge	172:65be27845400	787	__STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
AnnaBridge	172:65be27845400	788	{
AnnaBridge	172:65be27845400	789	MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos);
AnnaBridge	172:65be27845400	790	}
AnnaBridge	172:65be27845400	791
AnnaBridge	172:65be27845400	792	/**
AnnaBridge	172:65be27845400	793	* @brief Get reload transfer size
AnnaBridge	172:65be27845400	794	* @note Count is the number of frame to be transferred
AnnaBridge	172:65be27845400	795	* @rmtoll CR2 TSER LL_SPI_GetReloadSize
AnnaBridge	172:65be27845400	796	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	797	* @retval 0..0xFFFF
AnnaBridge	172:65be27845400	798	*/
AnnaBridge	172:65be27845400	799	__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	800	{
AnnaBridge	172:65be27845400	801	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
AnnaBridge	172:65be27845400	802	}
AnnaBridge	172:65be27845400	803
AnnaBridge	172:65be27845400	804	/**
AnnaBridge	172:65be27845400	805	* @brief Lock the AF configuration of associated IOs
AnnaBridge	172:65be27845400	806	* @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
AnnaBridge	172:65be27845400	807	* the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
AnnaBridge	172:65be27845400	808	* @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
AnnaBridge	172:65be27845400	809	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	810	* @retval None
AnnaBridge	172:65be27845400	811	*/
AnnaBridge	172:65be27845400	812	__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	813	{
AnnaBridge	172:65be27845400	814	SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
AnnaBridge	172:65be27845400	815	}
AnnaBridge	172:65be27845400	816
AnnaBridge	172:65be27845400	817	/**
AnnaBridge	172:65be27845400	818	* @brief Check if the AF configuration is locked.
AnnaBridge	172:65be27845400	819	* @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
AnnaBridge	172:65be27845400	820	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	821	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	822	*/
AnnaBridge	172:65be27845400	823	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	824	{
AnnaBridge	172:65be27845400	825	return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	826	}
AnnaBridge	172:65be27845400	827
AnnaBridge	172:65be27845400	828	/**
AnnaBridge	172:65be27845400	829	* @brief Set Tx CRC Initialization Pattern
AnnaBridge	172:65be27845400	830	* @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
AnnaBridge	172:65be27845400	831	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	832	* @param TXCRCInitAll This parameter can be one of the following values:
AnnaBridge	172:65be27845400	833	* @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
AnnaBridge	172:65be27845400	834	* @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
AnnaBridge	172:65be27845400	835	* @retval None
AnnaBridge	172:65be27845400	836	*/
AnnaBridge	172:65be27845400	837	__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
AnnaBridge	172:65be27845400	838	{
AnnaBridge	172:65be27845400	839	MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
AnnaBridge	172:65be27845400	840	}
AnnaBridge	172:65be27845400	841
AnnaBridge	172:65be27845400	842	/**
AnnaBridge	172:65be27845400	843	* @brief Get Tx CRC Initialization Pattern
AnnaBridge	172:65be27845400	844	* @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
AnnaBridge	172:65be27845400	845	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	846	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	847	* @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
AnnaBridge	172:65be27845400	848	* @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
AnnaBridge	172:65be27845400	849	*/
AnnaBridge	172:65be27845400	850	__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	851	{
AnnaBridge	172:65be27845400	852	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
AnnaBridge	172:65be27845400	853	}
AnnaBridge	172:65be27845400	854
AnnaBridge	172:65be27845400	855	/**
AnnaBridge	172:65be27845400	856	* @brief Set Rx CRC Initialization Pattern
AnnaBridge	172:65be27845400	857	* @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
AnnaBridge	172:65be27845400	858	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	859	* @param RXCRCInitAll This parameter can be one of the following values:
AnnaBridge	172:65be27845400	860	* @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
AnnaBridge	172:65be27845400	861	* @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
AnnaBridge	172:65be27845400	862	* @retval None
AnnaBridge	172:65be27845400	863	*/
AnnaBridge	172:65be27845400	864	__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
AnnaBridge	172:65be27845400	865	{
AnnaBridge	172:65be27845400	866	MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
AnnaBridge	172:65be27845400	867	}
AnnaBridge	172:65be27845400	868
AnnaBridge	172:65be27845400	869	/**
AnnaBridge	172:65be27845400	870	* @brief Get Rx CRC Initialization Pattern
AnnaBridge	172:65be27845400	871	* @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
AnnaBridge	172:65be27845400	872	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	873	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	874	* @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
AnnaBridge	172:65be27845400	875	* @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
AnnaBridge	172:65be27845400	876	*/
AnnaBridge	172:65be27845400	877	__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	878	{
AnnaBridge	172:65be27845400	879	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
AnnaBridge	172:65be27845400	880	}
AnnaBridge	172:65be27845400	881
AnnaBridge	172:65be27845400	882	/**
AnnaBridge	172:65be27845400	883	* @brief Set internal SS input level ignoring what comes from PIN.
AnnaBridge	172:65be27845400	884	* @note This configuration has effect only with config LL_SPI_NSS_SOFT
AnnaBridge	172:65be27845400	885	* @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
AnnaBridge	172:65be27845400	886	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	887	* @param SSLevel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	888	* @arg @ref LL_SPI_SS_LEVEL_HIGH
AnnaBridge	172:65be27845400	889	* @arg @ref LL_SPI_SS_LEVEL_LOW
AnnaBridge	172:65be27845400	890	* @retval None
AnnaBridge	172:65be27845400	891	*/
AnnaBridge	172:65be27845400	892	__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
AnnaBridge	172:65be27845400	893	{
AnnaBridge	172:65be27845400	894	MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
AnnaBridge	172:65be27845400	895	}
AnnaBridge	172:65be27845400	896
AnnaBridge	172:65be27845400	897	/**
AnnaBridge	172:65be27845400	898	* @brief Get internal SS input level
AnnaBridge	172:65be27845400	899	* @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
AnnaBridge	172:65be27845400	900	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	901	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	902	* @arg @ref LL_SPI_SS_LEVEL_HIGH
AnnaBridge	172:65be27845400	903	* @arg @ref LL_SPI_SS_LEVEL_LOW
AnnaBridge	172:65be27845400	904	*/
AnnaBridge	172:65be27845400	905	__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	906	{
AnnaBridge	172:65be27845400	907	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
AnnaBridge	172:65be27845400	908	}
AnnaBridge	172:65be27845400	909
AnnaBridge	172:65be27845400	910	/**
AnnaBridge	172:65be27845400	911	* @brief Enable CRC computation on 33/17 bits
AnnaBridge	172:65be27845400	912	* @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
AnnaBridge	172:65be27845400	913	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	914	* @retval None
AnnaBridge	172:65be27845400	915	*/
AnnaBridge	172:65be27845400	916	__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	917	{
AnnaBridge	172:65be27845400	918	SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
AnnaBridge	172:65be27845400	919	}
AnnaBridge	172:65be27845400	920
AnnaBridge	172:65be27845400	921	/**
AnnaBridge	172:65be27845400	922	* @brief Disable CRC computation on 33/17 bits
AnnaBridge	172:65be27845400	923	* @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
AnnaBridge	172:65be27845400	924	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	925	* @retval None
AnnaBridge	172:65be27845400	926	*/
AnnaBridge	172:65be27845400	927	__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	928	{
AnnaBridge	172:65be27845400	929	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
AnnaBridge	172:65be27845400	930	}
AnnaBridge	172:65be27845400	931
AnnaBridge	172:65be27845400	932	/**
AnnaBridge	172:65be27845400	933	* @brief Check if Enable CRC computation on 33/17 bits is enabled
AnnaBridge	172:65be27845400	934	* @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
AnnaBridge	172:65be27845400	935	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	936	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	937	*/
AnnaBridge	172:65be27845400	938	__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	939	{
AnnaBridge	172:65be27845400	940	return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	941	}
AnnaBridge	172:65be27845400	942
AnnaBridge	172:65be27845400	943	/**
AnnaBridge	172:65be27845400	944	* @brief Suspend an ongoing transfer for Master configuration
AnnaBridge	172:65be27845400	945	* @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
AnnaBridge	172:65be27845400	946	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	947	* @retval None
AnnaBridge	172:65be27845400	948	*/
AnnaBridge	172:65be27845400	949	__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	950	{
AnnaBridge	172:65be27845400	951	SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
AnnaBridge	172:65be27845400	952	}
AnnaBridge	172:65be27845400	953
AnnaBridge	172:65be27845400	954	/**
AnnaBridge	172:65be27845400	955	* @brief Start effective transfer on wire for Master configuration
AnnaBridge	172:65be27845400	956	* @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
AnnaBridge	172:65be27845400	957	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	958	* @retval None
AnnaBridge	172:65be27845400	959	*/
AnnaBridge	172:65be27845400	960	__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	961	{
AnnaBridge	172:65be27845400	962	SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
AnnaBridge	172:65be27845400	963	}
AnnaBridge	172:65be27845400	964
AnnaBridge	172:65be27845400	965	/**
AnnaBridge	172:65be27845400	966	* @brief Check if there is an unfinished master transfer
AnnaBridge	172:65be27845400	967	* @rmtoll CR1 CSTART LL_SPI_IsMasterTransferActive
AnnaBridge	172:65be27845400	968	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	969	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	970	*/
AnnaBridge	172:65be27845400	971	__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	972	{
AnnaBridge	172:65be27845400	973	return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	974	}
AnnaBridge	172:65be27845400	975
AnnaBridge	172:65be27845400	976	/**
AnnaBridge	172:65be27845400	977	* @brief Enable Master Rx auto suspend in case of overrun
AnnaBridge	172:65be27845400	978	* @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
AnnaBridge	172:65be27845400	979	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	980	* @retval None
AnnaBridge	172:65be27845400	981	*/
AnnaBridge	172:65be27845400	982	__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	983	{
AnnaBridge	172:65be27845400	984	SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
AnnaBridge	172:65be27845400	985	}
AnnaBridge	172:65be27845400	986
AnnaBridge	172:65be27845400	987	/**
AnnaBridge	172:65be27845400	988	* @brief Disable Master Rx auto suspend in case of overrun
AnnaBridge	172:65be27845400	989	* @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
AnnaBridge	172:65be27845400	990	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	991	* @retval None
AnnaBridge	172:65be27845400	992	*/
AnnaBridge	172:65be27845400	993	__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	994	{
AnnaBridge	172:65be27845400	995	CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
AnnaBridge	172:65be27845400	996	}
AnnaBridge	172:65be27845400	997
AnnaBridge	172:65be27845400	998	/**
AnnaBridge	172:65be27845400	999	* @brief Check if Master Rx auto suspend is activated
AnnaBridge	172:65be27845400	1000	* @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
AnnaBridge	172:65be27845400	1001	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1002	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	1003	*/
AnnaBridge	172:65be27845400	1004	__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1005	{
AnnaBridge	172:65be27845400	1006	return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1007	}
AnnaBridge	172:65be27845400	1008
AnnaBridge	172:65be27845400	1009	/**
AnnaBridge	172:65be27845400	1010	* @brief Set Underrun behavior
AnnaBridge	172:65be27845400	1011	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1012	* @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
AnnaBridge	172:65be27845400	1013	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1014	* @param UDRConfig This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1015	* @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
AnnaBridge	172:65be27845400	1016	* @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
AnnaBridge	172:65be27845400	1017	* @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
AnnaBridge	172:65be27845400	1018	* @retval None
AnnaBridge	172:65be27845400	1019	*/
AnnaBridge	172:65be27845400	1020	__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
AnnaBridge	172:65be27845400	1021	{
AnnaBridge	172:65be27845400	1022	MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
AnnaBridge	172:65be27845400	1023	}
AnnaBridge	172:65be27845400	1024
AnnaBridge	172:65be27845400	1025	/**
AnnaBridge	172:65be27845400	1026	* @brief Get Underrun behavior
AnnaBridge	172:65be27845400	1027	* @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
AnnaBridge	172:65be27845400	1028	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1029	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1030	* @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
AnnaBridge	172:65be27845400	1031	* @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
AnnaBridge	172:65be27845400	1032	* @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
AnnaBridge	172:65be27845400	1033	*/
AnnaBridge	172:65be27845400	1034	__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1035	{
AnnaBridge	172:65be27845400	1036	return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
AnnaBridge	172:65be27845400	1037	}
AnnaBridge	172:65be27845400	1038
AnnaBridge	172:65be27845400	1039	/**
AnnaBridge	172:65be27845400	1040	* @brief Set Underrun Detection method
AnnaBridge	172:65be27845400	1041	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1042	* @rmtoll CFG1 UDRDET LL_SPI_SetUDRDetection
AnnaBridge	172:65be27845400	1043	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1044	* @param UDRDetection This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1045	* @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
AnnaBridge	172:65be27845400	1046	* @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
AnnaBridge	172:65be27845400	1047	* @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
AnnaBridge	172:65be27845400	1048	* @retval None
AnnaBridge	172:65be27845400	1049	*/
AnnaBridge	172:65be27845400	1050	__STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection)
AnnaBridge	172:65be27845400	1051	{
AnnaBridge	172:65be27845400	1052	MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);
AnnaBridge	172:65be27845400	1053	}
AnnaBridge	172:65be27845400	1054
AnnaBridge	172:65be27845400	1055	/**
AnnaBridge	172:65be27845400	1056	* @brief Get Underrun Detection method
AnnaBridge	172:65be27845400	1057	* @rmtoll CFG1 UDRDET LL_SPI_GetUDRDetection
AnnaBridge	172:65be27845400	1058	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1059	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1060	* @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
AnnaBridge	172:65be27845400	1061	* @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
AnnaBridge	172:65be27845400	1062	* @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
AnnaBridge	172:65be27845400	1063	*/
AnnaBridge	172:65be27845400	1064	__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1065	{
AnnaBridge	172:65be27845400	1066	return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
AnnaBridge	172:65be27845400	1067	}
AnnaBridge	172:65be27845400	1068
AnnaBridge	172:65be27845400	1069	/**
AnnaBridge	172:65be27845400	1070	* @brief Set Serial protocol used
AnnaBridge	172:65be27845400	1071	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1072	* @rmtoll CFG2 SP LL_SPI_SetStandard
AnnaBridge	172:65be27845400	1073	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1074	* @param Standard This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1075	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	172:65be27845400	1076	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	172:65be27845400	1077	* @retval None
AnnaBridge	172:65be27845400	1078	*/
AnnaBridge	172:65be27845400	1079	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	172:65be27845400	1080	{
AnnaBridge	172:65be27845400	1081	MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
AnnaBridge	172:65be27845400	1082	}
AnnaBridge	172:65be27845400	1083
AnnaBridge	172:65be27845400	1084	/**
AnnaBridge	172:65be27845400	1085	* @brief Get Serial protocol used
AnnaBridge	172:65be27845400	1086	* @rmtoll CFG2 SP LL_SPI_GetStandard
AnnaBridge	172:65be27845400	1087	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1088	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1089	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	172:65be27845400	1090	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	172:65be27845400	1091	*/
AnnaBridge	172:65be27845400	1092	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1093	{
AnnaBridge	172:65be27845400	1094	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
AnnaBridge	172:65be27845400	1095	}
AnnaBridge	172:65be27845400	1096
AnnaBridge	172:65be27845400	1097	/**
AnnaBridge	172:65be27845400	1098	* @brief Set Clock phase
AnnaBridge	172:65be27845400	1099	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1100	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	1101	* @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
AnnaBridge	172:65be27845400	1102	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1103	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1104	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	172:65be27845400	1105	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	172:65be27845400	1106	* @retval None
AnnaBridge	172:65be27845400	1107	*/
AnnaBridge	172:65be27845400	1108	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	172:65be27845400	1109	{
AnnaBridge	172:65be27845400	1110	MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
AnnaBridge	172:65be27845400	1111	}
AnnaBridge	172:65be27845400	1112
AnnaBridge	172:65be27845400	1113	/**
AnnaBridge	172:65be27845400	1114	* @brief Get Clock phase
AnnaBridge	172:65be27845400	1115	* @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
AnnaBridge	172:65be27845400	1116	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1117	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1118	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	172:65be27845400	1119	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	172:65be27845400	1120	*/
AnnaBridge	172:65be27845400	1121	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1122	{
AnnaBridge	172:65be27845400	1123	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
AnnaBridge	172:65be27845400	1124	}
AnnaBridge	172:65be27845400	1125
AnnaBridge	172:65be27845400	1126	/**
AnnaBridge	172:65be27845400	1127	* @brief Set Clock polarity
AnnaBridge	172:65be27845400	1128	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1129	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	1130	* @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
AnnaBridge	172:65be27845400	1131	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1132	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1133	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	172:65be27845400	1134	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	172:65be27845400	1135	* @retval None
AnnaBridge	172:65be27845400	1136	*/
AnnaBridge	172:65be27845400	1137	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	172:65be27845400	1138	{
AnnaBridge	172:65be27845400	1139	MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
AnnaBridge	172:65be27845400	1140	}
AnnaBridge	172:65be27845400	1141
AnnaBridge	172:65be27845400	1142	/**
AnnaBridge	172:65be27845400	1143	* @brief Get Clock polarity
AnnaBridge	172:65be27845400	1144	* @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
AnnaBridge	172:65be27845400	1145	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1146	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1147	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	172:65be27845400	1148	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	172:65be27845400	1149	*/
AnnaBridge	172:65be27845400	1150	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1151	{
AnnaBridge	172:65be27845400	1152	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
AnnaBridge	172:65be27845400	1153	}
AnnaBridge	172:65be27845400	1154
AnnaBridge	172:65be27845400	1155	/**
AnnaBridge	172:65be27845400	1156	* @brief Set NSS polarity
AnnaBridge	172:65be27845400	1157	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1158	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	1159	* @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
AnnaBridge	172:65be27845400	1160	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1161	* @param NSSPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1162	* @arg @ref LL_SPI_NSS_POLARITY_LOW
AnnaBridge	172:65be27845400	1163	* @arg @ref LL_SPI_NSS_POLARITY_HIGH
AnnaBridge	172:65be27845400	1164	* @retval None
AnnaBridge	172:65be27845400	1165	*/
AnnaBridge	172:65be27845400	1166	__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
AnnaBridge	172:65be27845400	1167	{
AnnaBridge	172:65be27845400	1168	MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
AnnaBridge	172:65be27845400	1169	}
AnnaBridge	172:65be27845400	1170
AnnaBridge	172:65be27845400	1171	/**
AnnaBridge	172:65be27845400	1172	* @brief Get NSS polarity
AnnaBridge	172:65be27845400	1173	* @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
AnnaBridge	172:65be27845400	1174	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1175	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1176	* @arg @ref LL_SPI_NSS_POLARITY_LOW
AnnaBridge	172:65be27845400	1177	* @arg @ref LL_SPI_NSS_POLARITY_HIGH
AnnaBridge	172:65be27845400	1178	*/
AnnaBridge	172:65be27845400	1179	__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1180	{
AnnaBridge	172:65be27845400	1181	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
AnnaBridge	172:65be27845400	1182	}
AnnaBridge	172:65be27845400	1183
AnnaBridge	172:65be27845400	1184	/**
AnnaBridge	172:65be27845400	1185	* @brief Set Baudrate Prescaler
AnnaBridge	172:65be27845400	1186	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1187	* SPI BaudRate = fPCLK/Pescaler.
AnnaBridge	172:65be27845400	1188	* @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler
AnnaBridge	172:65be27845400	1189	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1190	* @param Baudrate This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1191	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	172:65be27845400	1192	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	172:65be27845400	1193	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	172:65be27845400	1194	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	172:65be27845400	1195	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	172:65be27845400	1196	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	172:65be27845400	1197	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	172:65be27845400	1198	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	172:65be27845400	1199	* @retval None
AnnaBridge	172:65be27845400	1200	*/
AnnaBridge	172:65be27845400	1201	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
AnnaBridge	172:65be27845400	1202	{
AnnaBridge	172:65be27845400	1203	MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);
AnnaBridge	172:65be27845400	1204	}
AnnaBridge	172:65be27845400	1205
AnnaBridge	172:65be27845400	1206	/**
AnnaBridge	172:65be27845400	1207	* @brief Get Baudrate Prescaler
AnnaBridge	172:65be27845400	1208	* @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler
AnnaBridge	172:65be27845400	1209	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1210	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1211	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	172:65be27845400	1212	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	172:65be27845400	1213	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	172:65be27845400	1214	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	172:65be27845400	1215	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	172:65be27845400	1216	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	172:65be27845400	1217	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	172:65be27845400	1218	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	172:65be27845400	1219	*/
AnnaBridge	172:65be27845400	1220	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1221	{
AnnaBridge	172:65be27845400	1222	return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
AnnaBridge	172:65be27845400	1223	}
AnnaBridge	172:65be27845400	1224
AnnaBridge	172:65be27845400	1225	/**
AnnaBridge	172:65be27845400	1226	* @brief Set Transfer Bit Order
AnnaBridge	172:65be27845400	1227	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1228	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	1229	* @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
AnnaBridge	172:65be27845400	1230	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1231	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1232	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	172:65be27845400	1233	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	172:65be27845400	1234	* @retval None
AnnaBridge	172:65be27845400	1235	*/
AnnaBridge	172:65be27845400	1236	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	172:65be27845400	1237	{
AnnaBridge	172:65be27845400	1238	MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
AnnaBridge	172:65be27845400	1239	}
AnnaBridge	172:65be27845400	1240
AnnaBridge	172:65be27845400	1241	/**
AnnaBridge	172:65be27845400	1242	* @brief Get Transfer Bit Order
AnnaBridge	172:65be27845400	1243	* @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
AnnaBridge	172:65be27845400	1244	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1245	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1246	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	172:65be27845400	1247	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	172:65be27845400	1248	*/
AnnaBridge	172:65be27845400	1249	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1250	{
AnnaBridge	172:65be27845400	1251	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
AnnaBridge	172:65be27845400	1252	}
AnnaBridge	172:65be27845400	1253
AnnaBridge	172:65be27845400	1254	/**
AnnaBridge	172:65be27845400	1255	* @brief Set Transfer Mode
AnnaBridge	172:65be27845400	1256	* @note This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection.
AnnaBridge	172:65be27845400	1257	* @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
AnnaBridge	172:65be27845400	1258	* CFG2 COMM LL_SPI_SetTransferDirection
AnnaBridge	172:65be27845400	1259	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1260	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1261	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	172:65be27845400	1262	* @arg @ref LL_SPI_SIMPLEX_TX
AnnaBridge	172:65be27845400	1263	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	172:65be27845400	1264	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	172:65be27845400	1265	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	172:65be27845400	1266	* @retval None
AnnaBridge	172:65be27845400	1267	*/
AnnaBridge	172:65be27845400	1268	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	172:65be27845400	1269	{
AnnaBridge	172:65be27845400	1270	MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
AnnaBridge	172:65be27845400	1271	MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
AnnaBridge	172:65be27845400	1272	}
AnnaBridge	172:65be27845400	1273
AnnaBridge	172:65be27845400	1274	/**
AnnaBridge	172:65be27845400	1275	* @brief Get Transfer Mode
AnnaBridge	172:65be27845400	1276	* @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
AnnaBridge	172:65be27845400	1277	* CFG2 COMM LL_SPI_GetTransferDirection
AnnaBridge	172:65be27845400	1278	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1279	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1280	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	172:65be27845400	1281	* @arg @ref LL_SPI_SIMPLEX_TX
AnnaBridge	172:65be27845400	1282	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	172:65be27845400	1283	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	172:65be27845400	1284	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	172:65be27845400	1285	*/
AnnaBridge	172:65be27845400	1286	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1287	{
AnnaBridge	172:65be27845400	1288	register uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
AnnaBridge	172:65be27845400	1289	register uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
AnnaBridge	172:65be27845400	1290	return (Hddir \| Comm);
AnnaBridge	172:65be27845400	1291	}
AnnaBridge	172:65be27845400	1292
AnnaBridge	172:65be27845400	1293	/**
AnnaBridge	172:65be27845400	1294	* @brief Set direction for Half-Duplex Mode
AnnaBridge	172:65be27845400	1295	* @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
AnnaBridge	172:65be27845400	1296	* @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
AnnaBridge	172:65be27845400	1297	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1298	* @param HalfDuplexDirection This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1299	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	172:65be27845400	1300	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	172:65be27845400	1301	* @retval None
AnnaBridge	172:65be27845400	1302	*/
AnnaBridge	172:65be27845400	1303	__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
AnnaBridge	172:65be27845400	1304	{
AnnaBridge	172:65be27845400	1305	MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
AnnaBridge	172:65be27845400	1306	}
AnnaBridge	172:65be27845400	1307
AnnaBridge	172:65be27845400	1308	/**
AnnaBridge	172:65be27845400	1309	* @brief Get direction for Half-Duplex Mode
AnnaBridge	172:65be27845400	1310	* @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
AnnaBridge	172:65be27845400	1311	* @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
AnnaBridge	172:65be27845400	1312	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1313	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1314	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	172:65be27845400	1315	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	172:65be27845400	1316	*/
AnnaBridge	172:65be27845400	1317	__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1318	{
AnnaBridge	172:65be27845400	1319	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) \| SPI_CFG2_COMM);
AnnaBridge	172:65be27845400	1320	}
AnnaBridge	172:65be27845400	1321
AnnaBridge	172:65be27845400	1322	/**
AnnaBridge	172:65be27845400	1323	* @brief Set Frame Data Size
AnnaBridge	172:65be27845400	1324	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1325	* @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
AnnaBridge	172:65be27845400	1326	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1327	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1328	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	172:65be27845400	1329	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	172:65be27845400	1330	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	172:65be27845400	1331	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	172:65be27845400	1332	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	172:65be27845400	1333	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	172:65be27845400	1334	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	172:65be27845400	1335	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	172:65be27845400	1336	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	172:65be27845400	1337	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	172:65be27845400	1338	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	172:65be27845400	1339	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	172:65be27845400	1340	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	172:65be27845400	1341	* @arg @ref LL_SPI_DATAWIDTH_17BIT
AnnaBridge	172:65be27845400	1342	* @arg @ref LL_SPI_DATAWIDTH_18BIT
AnnaBridge	172:65be27845400	1343	* @arg @ref LL_SPI_DATAWIDTH_19BIT
AnnaBridge	172:65be27845400	1344	* @arg @ref LL_SPI_DATAWIDTH_20BIT
AnnaBridge	172:65be27845400	1345	* @arg @ref LL_SPI_DATAWIDTH_21BIT
AnnaBridge	172:65be27845400	1346	* @arg @ref LL_SPI_DATAWIDTH_22BIT
AnnaBridge	172:65be27845400	1347	* @arg @ref LL_SPI_DATAWIDTH_23BIT
AnnaBridge	172:65be27845400	1348	* @arg @ref LL_SPI_DATAWIDTH_24BIT
AnnaBridge	172:65be27845400	1349	* @arg @ref LL_SPI_DATAWIDTH_25BIT
AnnaBridge	172:65be27845400	1350	* @arg @ref LL_SPI_DATAWIDTH_26BIT
AnnaBridge	172:65be27845400	1351	* @arg @ref LL_SPI_DATAWIDTH_27BIT
AnnaBridge	172:65be27845400	1352	* @arg @ref LL_SPI_DATAWIDTH_28BIT
AnnaBridge	172:65be27845400	1353	* @arg @ref LL_SPI_DATAWIDTH_29BIT
AnnaBridge	172:65be27845400	1354	* @arg @ref LL_SPI_DATAWIDTH_30BIT
AnnaBridge	172:65be27845400	1355	* @arg @ref LL_SPI_DATAWIDTH_31BIT
AnnaBridge	172:65be27845400	1356	* @arg @ref LL_SPI_DATAWIDTH_32BIT
AnnaBridge	172:65be27845400	1357	* @retval None
AnnaBridge	172:65be27845400	1358	*/
AnnaBridge	172:65be27845400	1359	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	172:65be27845400	1360	{
AnnaBridge	172:65be27845400	1361	MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
AnnaBridge	172:65be27845400	1362	}
AnnaBridge	172:65be27845400	1363
AnnaBridge	172:65be27845400	1364	/**
AnnaBridge	172:65be27845400	1365	* @brief Get Frame Data Size
AnnaBridge	172:65be27845400	1366	* @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
AnnaBridge	172:65be27845400	1367	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1368	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1369	* @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge	172:65be27845400	1370	* @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge	172:65be27845400	1371	* @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge	172:65be27845400	1372	* @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge	172:65be27845400	1373	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	172:65be27845400	1374	* @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge	172:65be27845400	1375	* @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge	172:65be27845400	1376	* @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge	172:65be27845400	1377	* @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge	172:65be27845400	1378	* @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge	172:65be27845400	1379	* @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge	172:65be27845400	1380	* @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge	172:65be27845400	1381	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	172:65be27845400	1382	* @arg @ref LL_SPI_DATAWIDTH_17BIT
AnnaBridge	172:65be27845400	1383	* @arg @ref LL_SPI_DATAWIDTH_18BIT
AnnaBridge	172:65be27845400	1384	* @arg @ref LL_SPI_DATAWIDTH_19BIT
AnnaBridge	172:65be27845400	1385	* @arg @ref LL_SPI_DATAWIDTH_20BIT
AnnaBridge	172:65be27845400	1386	* @arg @ref LL_SPI_DATAWIDTH_21BIT
AnnaBridge	172:65be27845400	1387	* @arg @ref LL_SPI_DATAWIDTH_22BIT
AnnaBridge	172:65be27845400	1388	* @arg @ref LL_SPI_DATAWIDTH_23BIT
AnnaBridge	172:65be27845400	1389	* @arg @ref LL_SPI_DATAWIDTH_24BIT
AnnaBridge	172:65be27845400	1390	* @arg @ref LL_SPI_DATAWIDTH_25BIT
AnnaBridge	172:65be27845400	1391	* @arg @ref LL_SPI_DATAWIDTH_26BIT
AnnaBridge	172:65be27845400	1392	* @arg @ref LL_SPI_DATAWIDTH_27BIT
AnnaBridge	172:65be27845400	1393	* @arg @ref LL_SPI_DATAWIDTH_28BIT
AnnaBridge	172:65be27845400	1394	* @arg @ref LL_SPI_DATAWIDTH_29BIT
AnnaBridge	172:65be27845400	1395	* @arg @ref LL_SPI_DATAWIDTH_30BIT
AnnaBridge	172:65be27845400	1396	* @arg @ref LL_SPI_DATAWIDTH_31BIT
AnnaBridge	172:65be27845400	1397	* @arg @ref LL_SPI_DATAWIDTH_32BIT
AnnaBridge	172:65be27845400	1398	*/
AnnaBridge	172:65be27845400	1399	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1400	{
AnnaBridge	172:65be27845400	1401	return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
AnnaBridge	172:65be27845400	1402	}
AnnaBridge	172:65be27845400	1403
AnnaBridge	172:65be27845400	1404	/**
AnnaBridge	172:65be27845400	1405	* @brief Set threshold of FIFO that triggers a transfer event
AnnaBridge	172:65be27845400	1406	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1407	* @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
AnnaBridge	172:65be27845400	1408	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1409	* @param Threshold This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1410	* @arg @ref LL_SPI_FIFO_TH_01DATA
AnnaBridge	172:65be27845400	1411	* @arg @ref LL_SPI_FIFO_TH_02DATA
AnnaBridge	172:65be27845400	1412	* @arg @ref LL_SPI_FIFO_TH_03DATA
AnnaBridge	172:65be27845400	1413	* @arg @ref LL_SPI_FIFO_TH_04DATA
AnnaBridge	172:65be27845400	1414	* @arg @ref LL_SPI_FIFO_TH_05DATA
AnnaBridge	172:65be27845400	1415	* @arg @ref LL_SPI_FIFO_TH_06DATA
AnnaBridge	172:65be27845400	1416	* @arg @ref LL_SPI_FIFO_TH_07DATA
AnnaBridge	172:65be27845400	1417	* @arg @ref LL_SPI_FIFO_TH_08DATA
AnnaBridge	172:65be27845400	1418	* @arg @ref LL_SPI_FIFO_TH_09DATA
AnnaBridge	172:65be27845400	1419	* @arg @ref LL_SPI_FIFO_TH_10DATA
AnnaBridge	172:65be27845400	1420	* @arg @ref LL_SPI_FIFO_TH_11DATA
AnnaBridge	172:65be27845400	1421	* @arg @ref LL_SPI_FIFO_TH_12DATA
AnnaBridge	172:65be27845400	1422	* @arg @ref LL_SPI_FIFO_TH_13DATA
AnnaBridge	172:65be27845400	1423	* @arg @ref LL_SPI_FIFO_TH_14DATA
AnnaBridge	172:65be27845400	1424	* @arg @ref LL_SPI_FIFO_TH_15DATA
AnnaBridge	172:65be27845400	1425	* @arg @ref LL_SPI_FIFO_TH_16DATA
AnnaBridge	172:65be27845400	1426	* @retval None
AnnaBridge	172:65be27845400	1427	*/
AnnaBridge	172:65be27845400	1428	__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
AnnaBridge	172:65be27845400	1429	{
AnnaBridge	172:65be27845400	1430	MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
AnnaBridge	172:65be27845400	1431	}
AnnaBridge	172:65be27845400	1432
AnnaBridge	172:65be27845400	1433	/**
AnnaBridge	172:65be27845400	1434	* @brief Get threshold of FIFO that triggers a transfer event
AnnaBridge	172:65be27845400	1435	* @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
AnnaBridge	172:65be27845400	1436	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1437	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1438	* @arg @ref LL_SPI_FIFO_TH_01DATA
AnnaBridge	172:65be27845400	1439	* @arg @ref LL_SPI_FIFO_TH_02DATA
AnnaBridge	172:65be27845400	1440	* @arg @ref LL_SPI_FIFO_TH_03DATA
AnnaBridge	172:65be27845400	1441	* @arg @ref LL_SPI_FIFO_TH_04DATA
AnnaBridge	172:65be27845400	1442	* @arg @ref LL_SPI_FIFO_TH_05DATA
AnnaBridge	172:65be27845400	1443	* @arg @ref LL_SPI_FIFO_TH_06DATA
AnnaBridge	172:65be27845400	1444	* @arg @ref LL_SPI_FIFO_TH_07DATA
AnnaBridge	172:65be27845400	1445	* @arg @ref LL_SPI_FIFO_TH_08DATA
AnnaBridge	172:65be27845400	1446	* @arg @ref LL_SPI_FIFO_TH_09DATA
AnnaBridge	172:65be27845400	1447	* @arg @ref LL_SPI_FIFO_TH_10DATA
AnnaBridge	172:65be27845400	1448	* @arg @ref LL_SPI_FIFO_TH_11DATA
AnnaBridge	172:65be27845400	1449	* @arg @ref LL_SPI_FIFO_TH_12DATA
AnnaBridge	172:65be27845400	1450	* @arg @ref LL_SPI_FIFO_TH_13DATA
AnnaBridge	172:65be27845400	1451	* @arg @ref LL_SPI_FIFO_TH_14DATA
AnnaBridge	172:65be27845400	1452	* @arg @ref LL_SPI_FIFO_TH_15DATA
AnnaBridge	172:65be27845400	1453	* @arg @ref LL_SPI_FIFO_TH_16DATA
AnnaBridge	172:65be27845400	1454	*/
AnnaBridge	172:65be27845400	1455	__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1456	{
AnnaBridge	172:65be27845400	1457	return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
AnnaBridge	172:65be27845400	1458	}
AnnaBridge	172:65be27845400	1459
AnnaBridge	172:65be27845400	1460	/**
AnnaBridge	172:65be27845400	1461	* @brief Enable CRC
AnnaBridge	172:65be27845400	1462	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1463	* @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
AnnaBridge	172:65be27845400	1464	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1465	* @retval None
AnnaBridge	172:65be27845400	1466	*/
AnnaBridge	172:65be27845400	1467	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1468	{
AnnaBridge	172:65be27845400	1469	SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
AnnaBridge	172:65be27845400	1470	}
AnnaBridge	172:65be27845400	1471
AnnaBridge	172:65be27845400	1472	/**
AnnaBridge	172:65be27845400	1473	* @brief Disable CRC
AnnaBridge	172:65be27845400	1474	* @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
AnnaBridge	172:65be27845400	1475	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1476	* @retval None
AnnaBridge	172:65be27845400	1477	*/
AnnaBridge	172:65be27845400	1478	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1479	{
AnnaBridge	172:65be27845400	1480	CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
AnnaBridge	172:65be27845400	1481	}
AnnaBridge	172:65be27845400	1482
AnnaBridge	172:65be27845400	1483	/**
AnnaBridge	172:65be27845400	1484	* @brief Check if CRC is enabled
AnnaBridge	172:65be27845400	1485	* @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	172:65be27845400	1486	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1487	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1488	*/
AnnaBridge	172:65be27845400	1489	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1490	{
AnnaBridge	172:65be27845400	1491	return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1492	}
AnnaBridge	172:65be27845400	1493
AnnaBridge	172:65be27845400	1494	/**
AnnaBridge	172:65be27845400	1495	* @brief Set CRC Length
AnnaBridge	172:65be27845400	1496	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1497	* @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
AnnaBridge	172:65be27845400	1498	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1499	* @param CRCLength This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1500	* @arg @ref LL_SPI_CRC_4BIT
AnnaBridge	172:65be27845400	1501	* @arg @ref LL_SPI_CRC_5BIT
AnnaBridge	172:65be27845400	1502	* @arg @ref LL_SPI_CRC_6BIT
AnnaBridge	172:65be27845400	1503	* @arg @ref LL_SPI_CRC_7BIT
AnnaBridge	172:65be27845400	1504	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	172:65be27845400	1505	* @arg @ref LL_SPI_CRC_9BIT
AnnaBridge	172:65be27845400	1506	* @arg @ref LL_SPI_CRC_10BIT
AnnaBridge	172:65be27845400	1507	* @arg @ref LL_SPI_CRC_11BIT
AnnaBridge	172:65be27845400	1508	* @arg @ref LL_SPI_CRC_12BIT
AnnaBridge	172:65be27845400	1509	* @arg @ref LL_SPI_CRC_13BIT
AnnaBridge	172:65be27845400	1510	* @arg @ref LL_SPI_CRC_14BIT
AnnaBridge	172:65be27845400	1511	* @arg @ref LL_SPI_CRC_15BIT
AnnaBridge	172:65be27845400	1512	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	172:65be27845400	1513	* @arg @ref LL_SPI_CRC_17BIT
AnnaBridge	172:65be27845400	1514	* @arg @ref LL_SPI_CRC_18BIT
AnnaBridge	172:65be27845400	1515	* @arg @ref LL_SPI_CRC_19BIT
AnnaBridge	172:65be27845400	1516	* @arg @ref LL_SPI_CRC_20BIT
AnnaBridge	172:65be27845400	1517	* @arg @ref LL_SPI_CRC_21BIT
AnnaBridge	172:65be27845400	1518	* @arg @ref LL_SPI_CRC_22BIT
AnnaBridge	172:65be27845400	1519	* @arg @ref LL_SPI_CRC_23BIT
AnnaBridge	172:65be27845400	1520	* @arg @ref LL_SPI_CRC_24BIT
AnnaBridge	172:65be27845400	1521	* @arg @ref LL_SPI_CRC_25BIT
AnnaBridge	172:65be27845400	1522	* @arg @ref LL_SPI_CRC_26BIT
AnnaBridge	172:65be27845400	1523	* @arg @ref LL_SPI_CRC_27BIT
AnnaBridge	172:65be27845400	1524	* @arg @ref LL_SPI_CRC_28BIT
AnnaBridge	172:65be27845400	1525	* @arg @ref LL_SPI_CRC_29BIT
AnnaBridge	172:65be27845400	1526	* @arg @ref LL_SPI_CRC_30BIT
AnnaBridge	172:65be27845400	1527	* @arg @ref LL_SPI_CRC_31BIT
AnnaBridge	172:65be27845400	1528	* @arg @ref LL_SPI_CRC_32BIT
AnnaBridge	172:65be27845400	1529	* @retval None
AnnaBridge	172:65be27845400	1530	*/
AnnaBridge	172:65be27845400	1531	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
AnnaBridge	172:65be27845400	1532	{
AnnaBridge	172:65be27845400	1533	MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
AnnaBridge	172:65be27845400	1534	}
AnnaBridge	172:65be27845400	1535
AnnaBridge	172:65be27845400	1536	/**
AnnaBridge	172:65be27845400	1537	* @brief Get CRC Length
AnnaBridge	172:65be27845400	1538	* @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
AnnaBridge	172:65be27845400	1539	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1540	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1541	* @arg @ref LL_SPI_CRC_4BIT
AnnaBridge	172:65be27845400	1542	* @arg @ref LL_SPI_CRC_5BIT
AnnaBridge	172:65be27845400	1543	* @arg @ref LL_SPI_CRC_6BIT
AnnaBridge	172:65be27845400	1544	* @arg @ref LL_SPI_CRC_7BIT
AnnaBridge	172:65be27845400	1545	* @arg @ref LL_SPI_CRC_8BIT
AnnaBridge	172:65be27845400	1546	* @arg @ref LL_SPI_CRC_9BIT
AnnaBridge	172:65be27845400	1547	* @arg @ref LL_SPI_CRC_10BIT
AnnaBridge	172:65be27845400	1548	* @arg @ref LL_SPI_CRC_11BIT
AnnaBridge	172:65be27845400	1549	* @arg @ref LL_SPI_CRC_12BIT
AnnaBridge	172:65be27845400	1550	* @arg @ref LL_SPI_CRC_13BIT
AnnaBridge	172:65be27845400	1551	* @arg @ref LL_SPI_CRC_14BIT
AnnaBridge	172:65be27845400	1552	* @arg @ref LL_SPI_CRC_15BIT
AnnaBridge	172:65be27845400	1553	* @arg @ref LL_SPI_CRC_16BIT
AnnaBridge	172:65be27845400	1554	* @arg @ref LL_SPI_CRC_17BIT
AnnaBridge	172:65be27845400	1555	* @arg @ref LL_SPI_CRC_18BIT
AnnaBridge	172:65be27845400	1556	* @arg @ref LL_SPI_CRC_19BIT
AnnaBridge	172:65be27845400	1557	* @arg @ref LL_SPI_CRC_20BIT
AnnaBridge	172:65be27845400	1558	* @arg @ref LL_SPI_CRC_21BIT
AnnaBridge	172:65be27845400	1559	* @arg @ref LL_SPI_CRC_22BIT
AnnaBridge	172:65be27845400	1560	* @arg @ref LL_SPI_CRC_23BIT
AnnaBridge	172:65be27845400	1561	* @arg @ref LL_SPI_CRC_24BIT
AnnaBridge	172:65be27845400	1562	* @arg @ref LL_SPI_CRC_25BIT
AnnaBridge	172:65be27845400	1563	* @arg @ref LL_SPI_CRC_26BIT
AnnaBridge	172:65be27845400	1564	* @arg @ref LL_SPI_CRC_27BIT
AnnaBridge	172:65be27845400	1565	* @arg @ref LL_SPI_CRC_28BIT
AnnaBridge	172:65be27845400	1566	* @arg @ref LL_SPI_CRC_29BIT
AnnaBridge	172:65be27845400	1567	* @arg @ref LL_SPI_CRC_30BIT
AnnaBridge	172:65be27845400	1568	* @arg @ref LL_SPI_CRC_31BIT
AnnaBridge	172:65be27845400	1569	* @arg @ref LL_SPI_CRC_32BIT
AnnaBridge	172:65be27845400	1570	*/
AnnaBridge	172:65be27845400	1571	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1572	{
AnnaBridge	172:65be27845400	1573	return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
AnnaBridge	172:65be27845400	1574	}
AnnaBridge	172:65be27845400	1575
AnnaBridge	172:65be27845400	1576	/**
AnnaBridge	172:65be27845400	1577	* @brief Set NSS Mode
AnnaBridge	172:65be27845400	1578	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1579	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	1580	* @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
AnnaBridge	172:65be27845400	1581	* CFG2 SSOE LL_SPI_SetNSSMode
AnnaBridge	172:65be27845400	1582	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1583	* @param NSS This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1584	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	172:65be27845400	1585	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	172:65be27845400	1586	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	172:65be27845400	1587	* @retval None
AnnaBridge	172:65be27845400	1588	*/
AnnaBridge	172:65be27845400	1589	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	172:65be27845400	1590	{
AnnaBridge	172:65be27845400	1591	MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM \| SPI_CFG2_SSOE, NSS);
AnnaBridge	172:65be27845400	1592	}
AnnaBridge	172:65be27845400	1593
AnnaBridge	172:65be27845400	1594	/**
AnnaBridge	172:65be27845400	1595	* @brief Set NSS Mode
AnnaBridge	172:65be27845400	1596	* @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
AnnaBridge	172:65be27845400	1597	* CFG2 SSOE LL_SPI_GetNSSMode
AnnaBridge	172:65be27845400	1598	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1599	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1600	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	172:65be27845400	1601	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	172:65be27845400	1602	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	172:65be27845400	1603	*/
AnnaBridge	172:65be27845400	1604	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1605	{
AnnaBridge	172:65be27845400	1606	return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM \| SPI_CFG2_SSOE));
AnnaBridge	172:65be27845400	1607	}
AnnaBridge	172:65be27845400	1608
AnnaBridge	172:65be27845400	1609	/**
AnnaBridge	172:65be27845400	1610	* @brief Enable NSS pulse mgt
AnnaBridge	172:65be27845400	1611	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1612	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	1613	* @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
AnnaBridge	172:65be27845400	1614	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1615	* @retval None
AnnaBridge	172:65be27845400	1616	*/
AnnaBridge	172:65be27845400	1617	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1618	{
AnnaBridge	172:65be27845400	1619	SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
AnnaBridge	172:65be27845400	1620	}
AnnaBridge	172:65be27845400	1621
AnnaBridge	172:65be27845400	1622	/**
AnnaBridge	172:65be27845400	1623	* @brief Disable NSS pulse mgt
AnnaBridge	172:65be27845400	1624	* @note This configuration can not be changed when SPI is enabled.
AnnaBridge	172:65be27845400	1625	* This bit is not used in SPI TI mode.
AnnaBridge	172:65be27845400	1626	* @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
AnnaBridge	172:65be27845400	1627	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1628	* @retval None
AnnaBridge	172:65be27845400	1629	*/
AnnaBridge	172:65be27845400	1630	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1631	{
AnnaBridge	172:65be27845400	1632	CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
AnnaBridge	172:65be27845400	1633	}
AnnaBridge	172:65be27845400	1634
AnnaBridge	172:65be27845400	1635	/**
AnnaBridge	172:65be27845400	1636	* @brief Check if NSS pulse is enabled
AnnaBridge	172:65be27845400	1637	* @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
AnnaBridge	172:65be27845400	1638	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1639	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	1640	*/
AnnaBridge	172:65be27845400	1641	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1642	{
AnnaBridge	172:65be27845400	1643	return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1644	}
AnnaBridge	172:65be27845400	1645
AnnaBridge	172:65be27845400	1646	/**
AnnaBridge	172:65be27845400	1647	* @}
AnnaBridge	172:65be27845400	1648	*/
AnnaBridge	172:65be27845400	1649
AnnaBridge	172:65be27845400	1650	/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	172:65be27845400	1651	* @{
AnnaBridge	172:65be27845400	1652	*/
AnnaBridge	172:65be27845400	1653
AnnaBridge	172:65be27845400	1654	/**
AnnaBridge	172:65be27845400	1655	* @brief Check if there is enough data in FIFO to read a full packet
AnnaBridge	172:65be27845400	1656	* @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
AnnaBridge	172:65be27845400	1657	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1658	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	1659	*/
AnnaBridge	172:65be27845400	1660	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1661	{
AnnaBridge	172:65be27845400	1662	return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1663	}
AnnaBridge	172:65be27845400	1664
AnnaBridge	172:65be27845400	1665	/**
AnnaBridge	172:65be27845400	1666	* @brief Check if there is enough space in FIFO to hold a full packet
AnnaBridge	172:65be27845400	1667	* @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
AnnaBridge	172:65be27845400	1668	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1669	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	1670	*/
AnnaBridge	172:65be27845400	1671	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1672	{
AnnaBridge	172:65be27845400	1673	return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1674	}
AnnaBridge	172:65be27845400	1675
AnnaBridge	172:65be27845400	1676	/**
AnnaBridge	172:65be27845400	1677	* @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
AnnaBridge	172:65be27845400	1678	* @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
AnnaBridge	172:65be27845400	1679	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1680	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	1681	*/
AnnaBridge	172:65be27845400	1682	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1683	{
AnnaBridge	172:65be27845400	1684	return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1685	}
AnnaBridge	172:65be27845400	1686
AnnaBridge	172:65be27845400	1687	/**
AnnaBridge	172:65be27845400	1688	* @brief Check that end of transfer event occured
AnnaBridge	172:65be27845400	1689	* @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
AnnaBridge	172:65be27845400	1690	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1691	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1692	*/
AnnaBridge	172:65be27845400	1693	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1694	{
AnnaBridge	172:65be27845400	1695	return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1696	}
AnnaBridge	172:65be27845400	1697
AnnaBridge	172:65be27845400	1698	/**
AnnaBridge	172:65be27845400	1699	* @brief Check that all required data has been filled in the fifo according to transfer size
AnnaBridge	172:65be27845400	1700	* @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
AnnaBridge	172:65be27845400	1701	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1702	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1703	*/
AnnaBridge	172:65be27845400	1704	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1705	{
AnnaBridge	172:65be27845400	1706	return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1707	}
AnnaBridge	172:65be27845400	1708
AnnaBridge	172:65be27845400	1709	/**
AnnaBridge	172:65be27845400	1710	* @brief Get Underrun error flag
AnnaBridge	172:65be27845400	1711	* @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
AnnaBridge	172:65be27845400	1712	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1713	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1714	*/
AnnaBridge	172:65be27845400	1715	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1716	{
AnnaBridge	172:65be27845400	1717	return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1718	}
AnnaBridge	172:65be27845400	1719
AnnaBridge	172:65be27845400	1720	/**
AnnaBridge	172:65be27845400	1721	* @brief Get CRC error flag
AnnaBridge	172:65be27845400	1722	* @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	172:65be27845400	1723	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1724	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1725	*/
AnnaBridge	172:65be27845400	1726	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1727	{
AnnaBridge	172:65be27845400	1728	return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1729	}
AnnaBridge	172:65be27845400	1730
AnnaBridge	172:65be27845400	1731	/**
AnnaBridge	172:65be27845400	1732	* @brief Get Mode fault error flag
AnnaBridge	172:65be27845400	1733	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	172:65be27845400	1734	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1735	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1736	*/
AnnaBridge	172:65be27845400	1737	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1738	{
AnnaBridge	172:65be27845400	1739	return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1740	}
AnnaBridge	172:65be27845400	1741
AnnaBridge	172:65be27845400	1742	/**
AnnaBridge	172:65be27845400	1743	* @brief Get Overrun error flag
AnnaBridge	172:65be27845400	1744	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	172:65be27845400	1745	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1746	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1747	*/
AnnaBridge	172:65be27845400	1748	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1749	{
AnnaBridge	172:65be27845400	1750	return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1751	}
AnnaBridge	172:65be27845400	1752
AnnaBridge	172:65be27845400	1753	/**
AnnaBridge	172:65be27845400	1754	* @brief Get TI Frame format error flag
AnnaBridge	172:65be27845400	1755	* @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	172:65be27845400	1756	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1757	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1758	*/
AnnaBridge	172:65be27845400	1759	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1760	{
AnnaBridge	172:65be27845400	1761	return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1762	}
AnnaBridge	172:65be27845400	1763
AnnaBridge	172:65be27845400	1764	/**
AnnaBridge	172:65be27845400	1765	* @brief Check if the additional number of data has been reloaded
AnnaBridge	172:65be27845400	1766	* @rmtoll SR TSERF LL_SPI_IsActiveFlag_TSER
AnnaBridge	172:65be27845400	1767	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1768	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1769	*/
AnnaBridge	172:65be27845400	1770	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1771	{
AnnaBridge	172:65be27845400	1772	return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1773	}
AnnaBridge	172:65be27845400	1774
AnnaBridge	172:65be27845400	1775	/**
AnnaBridge	172:65be27845400	1776	* @brief Check if a suspend operation is done
AnnaBridge	172:65be27845400	1777	* @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
AnnaBridge	172:65be27845400	1778	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1779	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	1780	*/
AnnaBridge	172:65be27845400	1781	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1782	{
AnnaBridge	172:65be27845400	1783	return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1784	}
AnnaBridge	172:65be27845400	1785
AnnaBridge	172:65be27845400	1786	/**
AnnaBridge	172:65be27845400	1787	* @brief Get TXC flag
AnnaBridge	172:65be27845400	1788	* @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
AnnaBridge	172:65be27845400	1789	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1790	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1791	*/
AnnaBridge	172:65be27845400	1792	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1793	{
AnnaBridge	172:65be27845400	1794	return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1795	}
AnnaBridge	172:65be27845400	1796
AnnaBridge	172:65be27845400	1797	/**
AnnaBridge	172:65be27845400	1798	* @brief Check if at least one 32-bit data is available in RxFIFO
AnnaBridge	172:65be27845400	1799	* @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
AnnaBridge	172:65be27845400	1800	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1801	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	1802	*/
AnnaBridge	172:65be27845400	1803	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1804	{
AnnaBridge	172:65be27845400	1805	return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1806	}
AnnaBridge	172:65be27845400	1807
AnnaBridge	172:65be27845400	1808	/**
AnnaBridge	172:65be27845400	1809	* @brief Get number of data framed remaining in current TSIZE
AnnaBridge	172:65be27845400	1810	* @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
AnnaBridge	172:65be27845400	1811	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1812	* @retval 0..0xFFFF
AnnaBridge	172:65be27845400	1813	*/
AnnaBridge	172:65be27845400	1814	__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1815	{
AnnaBridge	172:65be27845400	1816	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
AnnaBridge	172:65be27845400	1817	}
AnnaBridge	172:65be27845400	1818
AnnaBridge	172:65be27845400	1819	/**
AnnaBridge	172:65be27845400	1820	* @brief Get RxFIFO packing Level
AnnaBridge	172:65be27845400	1821	* @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
AnnaBridge	172:65be27845400	1822	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1823	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1824	* @arg @ref LL_SPI_RX_FIFO_0PACKET
AnnaBridge	172:65be27845400	1825	* @arg @ref LL_SPI_RX_FIFO_1PACKET
AnnaBridge	172:65be27845400	1826	* @arg @ref LL_SPI_RX_FIFO_2PACKET
AnnaBridge	172:65be27845400	1827	* @arg @ref LL_SPI_RX_FIFO_3PACKET
AnnaBridge	172:65be27845400	1828	*/
AnnaBridge	172:65be27845400	1829	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1830	{
AnnaBridge	172:65be27845400	1831	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
AnnaBridge	172:65be27845400	1832	}
AnnaBridge	172:65be27845400	1833
AnnaBridge	172:65be27845400	1834	/**
AnnaBridge	172:65be27845400	1835	* @brief Clear End Of Transfer flag
AnnaBridge	172:65be27845400	1836	* @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
AnnaBridge	172:65be27845400	1837	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1838	* @retval None
AnnaBridge	172:65be27845400	1839	*/
AnnaBridge	172:65be27845400	1840	__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1841	{
AnnaBridge	172:65be27845400	1842	SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
AnnaBridge	172:65be27845400	1843	}
AnnaBridge	172:65be27845400	1844
AnnaBridge	172:65be27845400	1845	/**
AnnaBridge	172:65be27845400	1846	* @brief Clear TXTF flag
AnnaBridge	172:65be27845400	1847	* @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
AnnaBridge	172:65be27845400	1848	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1849	* @retval None
AnnaBridge	172:65be27845400	1850	*/
AnnaBridge	172:65be27845400	1851	__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1852	{
AnnaBridge	172:65be27845400	1853	SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
AnnaBridge	172:65be27845400	1854	}
AnnaBridge	172:65be27845400	1855
AnnaBridge	172:65be27845400	1856	/**
AnnaBridge	172:65be27845400	1857	* @brief Clear Underrun error flag
AnnaBridge	172:65be27845400	1858	* @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
AnnaBridge	172:65be27845400	1859	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1860	* @retval None
AnnaBridge	172:65be27845400	1861	*/
AnnaBridge	172:65be27845400	1862	__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1863	{
AnnaBridge	172:65be27845400	1864	SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
AnnaBridge	172:65be27845400	1865	}
AnnaBridge	172:65be27845400	1866
AnnaBridge	172:65be27845400	1867	/**
AnnaBridge	172:65be27845400	1868	* @brief Clear Overrun error flag
AnnaBridge	172:65be27845400	1869	* @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
AnnaBridge	172:65be27845400	1870	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1871	* @retval None
AnnaBridge	172:65be27845400	1872	*/
AnnaBridge	172:65be27845400	1873	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1874	{
AnnaBridge	172:65be27845400	1875	SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
AnnaBridge	172:65be27845400	1876	}
AnnaBridge	172:65be27845400	1877
AnnaBridge	172:65be27845400	1878	/**
AnnaBridge	172:65be27845400	1879	* @brief Clear CRC error flag
AnnaBridge	172:65be27845400	1880	* @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
AnnaBridge	172:65be27845400	1881	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1882	* @retval None
AnnaBridge	172:65be27845400	1883	*/
AnnaBridge	172:65be27845400	1884	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1885	{
AnnaBridge	172:65be27845400	1886	SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
AnnaBridge	172:65be27845400	1887	}
AnnaBridge	172:65be27845400	1888
AnnaBridge	172:65be27845400	1889	/**
AnnaBridge	172:65be27845400	1890	* @brief Clear Mode fault error flag
AnnaBridge	172:65be27845400	1891	* @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
AnnaBridge	172:65be27845400	1892	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1893	* @retval None
AnnaBridge	172:65be27845400	1894	*/
AnnaBridge	172:65be27845400	1895	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1896	{
AnnaBridge	172:65be27845400	1897	SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
AnnaBridge	172:65be27845400	1898	}
AnnaBridge	172:65be27845400	1899
AnnaBridge	172:65be27845400	1900	/**
AnnaBridge	172:65be27845400	1901	* @brief Clear Frame format error flag
AnnaBridge	172:65be27845400	1902	* @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
AnnaBridge	172:65be27845400	1903	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1904	* @retval None
AnnaBridge	172:65be27845400	1905	*/
AnnaBridge	172:65be27845400	1906	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1907	{
AnnaBridge	172:65be27845400	1908	SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
AnnaBridge	172:65be27845400	1909	}
AnnaBridge	172:65be27845400	1910
AnnaBridge	172:65be27845400	1911	/**
AnnaBridge	172:65be27845400	1912	* @brief Clear TSER flag
AnnaBridge	172:65be27845400	1913	* @rmtoll IFCR TSERFC LL_SPI_ClearFlag_TSER
AnnaBridge	172:65be27845400	1914	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1915	* @retval None
AnnaBridge	172:65be27845400	1916	*/
AnnaBridge	172:65be27845400	1917	__STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1918	{
AnnaBridge	172:65be27845400	1919	SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC);
AnnaBridge	172:65be27845400	1920	}
AnnaBridge	172:65be27845400	1921
AnnaBridge	172:65be27845400	1922	/**
AnnaBridge	172:65be27845400	1923	* @brief Clear SUSP flag
AnnaBridge	172:65be27845400	1924	* @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
AnnaBridge	172:65be27845400	1925	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1926	* @retval None
AnnaBridge	172:65be27845400	1927	*/
AnnaBridge	172:65be27845400	1928	__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1929	{
AnnaBridge	172:65be27845400	1930	SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
AnnaBridge	172:65be27845400	1931	}
AnnaBridge	172:65be27845400	1932
AnnaBridge	172:65be27845400	1933	/**
AnnaBridge	172:65be27845400	1934	* @}
AnnaBridge	172:65be27845400	1935	*/
AnnaBridge	172:65be27845400	1936
AnnaBridge	172:65be27845400	1937	/** @defgroup SPI_LL_EF_IT_Management IT_Management
AnnaBridge	172:65be27845400	1938	* @{
AnnaBridge	172:65be27845400	1939	*/
AnnaBridge	172:65be27845400	1940
AnnaBridge	172:65be27845400	1941	/**
AnnaBridge	172:65be27845400	1942	* @brief Enable Rx Packet available IT
AnnaBridge	172:65be27845400	1943	* @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
AnnaBridge	172:65be27845400	1944	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1945	* @retval None
AnnaBridge	172:65be27845400	1946	*/
AnnaBridge	172:65be27845400	1947	__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1948	{
AnnaBridge	172:65be27845400	1949	SET_BIT(SPIx->IER, SPI_IER_RXPIE);
AnnaBridge	172:65be27845400	1950	}
AnnaBridge	172:65be27845400	1951
AnnaBridge	172:65be27845400	1952	/**
AnnaBridge	172:65be27845400	1953	* @brief Enable Tx Packet space available IT
AnnaBridge	172:65be27845400	1954	* @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
AnnaBridge	172:65be27845400	1955	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1956	* @retval None
AnnaBridge	172:65be27845400	1957	*/
AnnaBridge	172:65be27845400	1958	__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1959	{
AnnaBridge	172:65be27845400	1960	SET_BIT(SPIx->IER, SPI_IER_TXPIE);
AnnaBridge	172:65be27845400	1961	}
AnnaBridge	172:65be27845400	1962
AnnaBridge	172:65be27845400	1963	/**
AnnaBridge	172:65be27845400	1964	* @brief Enable Duplex Packet available IT
AnnaBridge	172:65be27845400	1965	* @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
AnnaBridge	172:65be27845400	1966	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1967	* @retval None
AnnaBridge	172:65be27845400	1968	*/
AnnaBridge	172:65be27845400	1969	__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1970	{
AnnaBridge	172:65be27845400	1971	SET_BIT(SPIx->IER, SPI_IER_DXPIE);
AnnaBridge	172:65be27845400	1972	}
AnnaBridge	172:65be27845400	1973
AnnaBridge	172:65be27845400	1974	/**
AnnaBridge	172:65be27845400	1975	* @brief Enable End Of Transfer IT
AnnaBridge	172:65be27845400	1976	* @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
AnnaBridge	172:65be27845400	1977	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1978	* @retval None
AnnaBridge	172:65be27845400	1979	*/
AnnaBridge	172:65be27845400	1980	__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1981	{
AnnaBridge	172:65be27845400	1982	SET_BIT(SPIx->IER, SPI_IER_EOTIE);
AnnaBridge	172:65be27845400	1983	}
AnnaBridge	172:65be27845400	1984
AnnaBridge	172:65be27845400	1985	/**
AnnaBridge	172:65be27845400	1986	* @brief Enable TXTF IT
AnnaBridge	172:65be27845400	1987	* @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
AnnaBridge	172:65be27845400	1988	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	1989	* @retval None
AnnaBridge	172:65be27845400	1990	*/
AnnaBridge	172:65be27845400	1991	__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	1992	{
AnnaBridge	172:65be27845400	1993	SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
AnnaBridge	172:65be27845400	1994	}
AnnaBridge	172:65be27845400	1995
AnnaBridge	172:65be27845400	1996	/**
AnnaBridge	172:65be27845400	1997	* @brief Enable Underrun IT
AnnaBridge	172:65be27845400	1998	* @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
AnnaBridge	172:65be27845400	1999	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2000	* @retval None
AnnaBridge	172:65be27845400	2001	*/
AnnaBridge	172:65be27845400	2002	__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2003	{
AnnaBridge	172:65be27845400	2004	SET_BIT(SPIx->IER, SPI_IER_UDRIE);
AnnaBridge	172:65be27845400	2005	}
AnnaBridge	172:65be27845400	2006
AnnaBridge	172:65be27845400	2007	/**
AnnaBridge	172:65be27845400	2008	* @brief Enable Overrun IT
AnnaBridge	172:65be27845400	2009	* @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
AnnaBridge	172:65be27845400	2010	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2011	* @retval None
AnnaBridge	172:65be27845400	2012	*/
AnnaBridge	172:65be27845400	2013	__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2014	{
AnnaBridge	172:65be27845400	2015	SET_BIT(SPIx->IER, SPI_IER_OVRIE);
AnnaBridge	172:65be27845400	2016	}
AnnaBridge	172:65be27845400	2017
AnnaBridge	172:65be27845400	2018	/**
AnnaBridge	172:65be27845400	2019	* @brief Enable CRC Error IT
AnnaBridge	172:65be27845400	2020	* @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
AnnaBridge	172:65be27845400	2021	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2022	* @retval None
AnnaBridge	172:65be27845400	2023	*/
AnnaBridge	172:65be27845400	2024	__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2025	{
AnnaBridge	172:65be27845400	2026	SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
AnnaBridge	172:65be27845400	2027	}
AnnaBridge	172:65be27845400	2028
AnnaBridge	172:65be27845400	2029	/**
AnnaBridge	172:65be27845400	2030	* @brief Enable TI Frame Format Error IT
AnnaBridge	172:65be27845400	2031	* @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
AnnaBridge	172:65be27845400	2032	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2033	* @retval None
AnnaBridge	172:65be27845400	2034	*/
AnnaBridge	172:65be27845400	2035	__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2036	{
AnnaBridge	172:65be27845400	2037	SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
AnnaBridge	172:65be27845400	2038	}
AnnaBridge	172:65be27845400	2039
AnnaBridge	172:65be27845400	2040	/**
AnnaBridge	172:65be27845400	2041	* @brief Enable MODF IT
AnnaBridge	172:65be27845400	2042	* @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
AnnaBridge	172:65be27845400	2043	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2044	* @retval None
AnnaBridge	172:65be27845400	2045	*/
AnnaBridge	172:65be27845400	2046	__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2047	{
AnnaBridge	172:65be27845400	2048	SET_BIT(SPIx->IER, SPI_IER_MODFIE);
AnnaBridge	172:65be27845400	2049	}
AnnaBridge	172:65be27845400	2050
AnnaBridge	172:65be27845400	2051	/**
AnnaBridge	172:65be27845400	2052	* @brief Enable TSER reload IT
AnnaBridge	172:65be27845400	2053	* @rmtoll IER TSERFIE LL_SPI_EnableIT_TSER
AnnaBridge	172:65be27845400	2054	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2055	* @retval None
AnnaBridge	172:65be27845400	2056	*/
AnnaBridge	172:65be27845400	2057	__STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2058	{
AnnaBridge	172:65be27845400	2059	SET_BIT(SPIx->IER, SPI_IER_TSERFIE);
AnnaBridge	172:65be27845400	2060	}
AnnaBridge	172:65be27845400	2061
AnnaBridge	172:65be27845400	2062	/**
AnnaBridge	172:65be27845400	2063	* @brief Disable Rx Packet available IT
AnnaBridge	172:65be27845400	2064	* @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
AnnaBridge	172:65be27845400	2065	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2066	* @retval None
AnnaBridge	172:65be27845400	2067	*/
AnnaBridge	172:65be27845400	2068	__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2069	{
AnnaBridge	172:65be27845400	2070	CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
AnnaBridge	172:65be27845400	2071	}
AnnaBridge	172:65be27845400	2072
AnnaBridge	172:65be27845400	2073	/**
AnnaBridge	172:65be27845400	2074	* @brief Disable Tx Packet space available IT
AnnaBridge	172:65be27845400	2075	* @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
AnnaBridge	172:65be27845400	2076	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2077	* @retval None
AnnaBridge	172:65be27845400	2078	*/
AnnaBridge	172:65be27845400	2079	__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2080	{
AnnaBridge	172:65be27845400	2081	CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
AnnaBridge	172:65be27845400	2082	}
AnnaBridge	172:65be27845400	2083
AnnaBridge	172:65be27845400	2084	/**
AnnaBridge	172:65be27845400	2085	* @brief Disable Duplex Packet available IT
AnnaBridge	172:65be27845400	2086	* @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
AnnaBridge	172:65be27845400	2087	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2088	* @retval None
AnnaBridge	172:65be27845400	2089	*/
AnnaBridge	172:65be27845400	2090	__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2091	{
AnnaBridge	172:65be27845400	2092	CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
AnnaBridge	172:65be27845400	2093	}
AnnaBridge	172:65be27845400	2094
AnnaBridge	172:65be27845400	2095	/**
AnnaBridge	172:65be27845400	2096	* @brief Disable End Of Transfer IT
AnnaBridge	172:65be27845400	2097	* @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
AnnaBridge	172:65be27845400	2098	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2099	* @retval None
AnnaBridge	172:65be27845400	2100	*/
AnnaBridge	172:65be27845400	2101	__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2102	{
AnnaBridge	172:65be27845400	2103	CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
AnnaBridge	172:65be27845400	2104	}
AnnaBridge	172:65be27845400	2105
AnnaBridge	172:65be27845400	2106	/**
AnnaBridge	172:65be27845400	2107	* @brief Disable TXTF IT
AnnaBridge	172:65be27845400	2108	* @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
AnnaBridge	172:65be27845400	2109	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2110	* @retval None
AnnaBridge	172:65be27845400	2111	*/
AnnaBridge	172:65be27845400	2112	__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2113	{
AnnaBridge	172:65be27845400	2114	CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
AnnaBridge	172:65be27845400	2115	}
AnnaBridge	172:65be27845400	2116
AnnaBridge	172:65be27845400	2117	/**
AnnaBridge	172:65be27845400	2118	* @brief Disable Underrun IT
AnnaBridge	172:65be27845400	2119	* @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
AnnaBridge	172:65be27845400	2120	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2121	* @retval None
AnnaBridge	172:65be27845400	2122	*/
AnnaBridge	172:65be27845400	2123	__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2124	{
AnnaBridge	172:65be27845400	2125	CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
AnnaBridge	172:65be27845400	2126	}
AnnaBridge	172:65be27845400	2127
AnnaBridge	172:65be27845400	2128	/**
AnnaBridge	172:65be27845400	2129	* @brief Disable Overrun IT
AnnaBridge	172:65be27845400	2130	* @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
AnnaBridge	172:65be27845400	2131	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2132	* @retval None
AnnaBridge	172:65be27845400	2133	*/
AnnaBridge	172:65be27845400	2134	__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2135	{
AnnaBridge	172:65be27845400	2136	CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
AnnaBridge	172:65be27845400	2137	}
AnnaBridge	172:65be27845400	2138
AnnaBridge	172:65be27845400	2139	/**
AnnaBridge	172:65be27845400	2140	* @brief Disable CRC Error IT
AnnaBridge	172:65be27845400	2141	* @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
AnnaBridge	172:65be27845400	2142	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2143	* @retval None
AnnaBridge	172:65be27845400	2144	*/
AnnaBridge	172:65be27845400	2145	__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2146	{
AnnaBridge	172:65be27845400	2147	CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
AnnaBridge	172:65be27845400	2148	}
AnnaBridge	172:65be27845400	2149
AnnaBridge	172:65be27845400	2150	/**
AnnaBridge	172:65be27845400	2151	* @brief Disable TI Frame Format Error IT
AnnaBridge	172:65be27845400	2152	* @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
AnnaBridge	172:65be27845400	2153	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2154	* @retval None
AnnaBridge	172:65be27845400	2155	*/
AnnaBridge	172:65be27845400	2156	__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2157	{
AnnaBridge	172:65be27845400	2158	CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
AnnaBridge	172:65be27845400	2159	}
AnnaBridge	172:65be27845400	2160
AnnaBridge	172:65be27845400	2161	/**
AnnaBridge	172:65be27845400	2162	* @brief Disable MODF IT
AnnaBridge	172:65be27845400	2163	* @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
AnnaBridge	172:65be27845400	2164	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2165	* @retval None
AnnaBridge	172:65be27845400	2166	*/
AnnaBridge	172:65be27845400	2167	__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2168	{
AnnaBridge	172:65be27845400	2169	CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
AnnaBridge	172:65be27845400	2170	}
AnnaBridge	172:65be27845400	2171
AnnaBridge	172:65be27845400	2172	/**
AnnaBridge	172:65be27845400	2173	* @brief Disable TSER reload IT
AnnaBridge	172:65be27845400	2174	* @rmtoll IER TSERFIE LL_SPI_DisableIT_TSER
AnnaBridge	172:65be27845400	2175	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2176	* @retval None
AnnaBridge	172:65be27845400	2177	*/
AnnaBridge	172:65be27845400	2178	__STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2179	{
AnnaBridge	172:65be27845400	2180	CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE);
AnnaBridge	172:65be27845400	2181	}
AnnaBridge	172:65be27845400	2182
AnnaBridge	172:65be27845400	2183	/**
AnnaBridge	172:65be27845400	2184	* @brief Check if Rx Packet available IT is enabled
AnnaBridge	172:65be27845400	2185	* @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
AnnaBridge	172:65be27845400	2186	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2187	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2188	*/
AnnaBridge	172:65be27845400	2189	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2190	{
AnnaBridge	172:65be27845400	2191	return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2192	}
AnnaBridge	172:65be27845400	2193
AnnaBridge	172:65be27845400	2194	/**
AnnaBridge	172:65be27845400	2195	* @brief Check if Tx Packet space available IT is enabled
AnnaBridge	172:65be27845400	2196	* @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
AnnaBridge	172:65be27845400	2197	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2198	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2199	*/
AnnaBridge	172:65be27845400	2200	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2201	{
AnnaBridge	172:65be27845400	2202	return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2203	}
AnnaBridge	172:65be27845400	2204
AnnaBridge	172:65be27845400	2205	/**
AnnaBridge	172:65be27845400	2206	* @brief Check if Duplex Packet available IT is enabled
AnnaBridge	172:65be27845400	2207	* @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
AnnaBridge	172:65be27845400	2208	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2209	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2210	*/
AnnaBridge	172:65be27845400	2211	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2212	{
AnnaBridge	172:65be27845400	2213	return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2214	}
AnnaBridge	172:65be27845400	2215
AnnaBridge	172:65be27845400	2216	/**
AnnaBridge	172:65be27845400	2217	* @brief Check if End Of Transfer IT is enabled
AnnaBridge	172:65be27845400	2218	* @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
AnnaBridge	172:65be27845400	2219	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2220	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2221	*/
AnnaBridge	172:65be27845400	2222	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2223	{
AnnaBridge	172:65be27845400	2224	return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2225	}
AnnaBridge	172:65be27845400	2226
AnnaBridge	172:65be27845400	2227	/**
AnnaBridge	172:65be27845400	2228	* @brief Check if TXTF IT is enabled
AnnaBridge	172:65be27845400	2229	* @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
AnnaBridge	172:65be27845400	2230	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2231	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2232	*/
AnnaBridge	172:65be27845400	2233	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2234	{
AnnaBridge	172:65be27845400	2235	return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2236	}
AnnaBridge	172:65be27845400	2237
AnnaBridge	172:65be27845400	2238	/**
AnnaBridge	172:65be27845400	2239	* @brief Check if Underrun IT is enabled
AnnaBridge	172:65be27845400	2240	* @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
AnnaBridge	172:65be27845400	2241	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2242	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2243	*/
AnnaBridge	172:65be27845400	2244	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2245	{
AnnaBridge	172:65be27845400	2246	return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2247	}
AnnaBridge	172:65be27845400	2248
AnnaBridge	172:65be27845400	2249	/**
AnnaBridge	172:65be27845400	2250	* @brief Check if Overrun IT is enabled
AnnaBridge	172:65be27845400	2251	* @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
AnnaBridge	172:65be27845400	2252	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2253	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2254	*/
AnnaBridge	172:65be27845400	2255	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2256	{
AnnaBridge	172:65be27845400	2257	return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2258	}
AnnaBridge	172:65be27845400	2259
AnnaBridge	172:65be27845400	2260	/**
AnnaBridge	172:65be27845400	2261	* @brief Check if CRC Error IT is enabled
AnnaBridge	172:65be27845400	2262	* @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
AnnaBridge	172:65be27845400	2263	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2264	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2265	*/
AnnaBridge	172:65be27845400	2266	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2267	{
AnnaBridge	172:65be27845400	2268	return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2269	}
AnnaBridge	172:65be27845400	2270
AnnaBridge	172:65be27845400	2271	/**
AnnaBridge	172:65be27845400	2272	* @brief Check if TI Frame Format Error IT is enabled
AnnaBridge	172:65be27845400	2273	* @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
AnnaBridge	172:65be27845400	2274	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2275	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2276	*/
AnnaBridge	172:65be27845400	2277	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2278	{
AnnaBridge	172:65be27845400	2279	return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2280	}
AnnaBridge	172:65be27845400	2281
AnnaBridge	172:65be27845400	2282	/**
AnnaBridge	172:65be27845400	2283	* @brief Check if MODF IT is enabled
AnnaBridge	172:65be27845400	2284	* @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
AnnaBridge	172:65be27845400	2285	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2286	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2287	*/
AnnaBridge	172:65be27845400	2288	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2289	{
AnnaBridge	172:65be27845400	2290	return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2291	}
AnnaBridge	172:65be27845400	2292
AnnaBridge	172:65be27845400	2293	/**
AnnaBridge	172:65be27845400	2294	* @brief Check if TSER reload IT is enabled
AnnaBridge	172:65be27845400	2295	* @rmtoll IER TSERFIE LL_SPI_IsEnabledIT_TSER
AnnaBridge	172:65be27845400	2296	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2297	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2298	*/
AnnaBridge	172:65be27845400	2299	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2300	{
AnnaBridge	172:65be27845400	2301	return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2302	}
AnnaBridge	172:65be27845400	2303
AnnaBridge	172:65be27845400	2304	/**
AnnaBridge	172:65be27845400	2305	* @}
AnnaBridge	172:65be27845400	2306	*/
AnnaBridge	172:65be27845400	2307
AnnaBridge	172:65be27845400	2308	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	172:65be27845400	2309	* @{
AnnaBridge	172:65be27845400	2310	*/
AnnaBridge	172:65be27845400	2311
AnnaBridge	172:65be27845400	2312	/**
AnnaBridge	172:65be27845400	2313	* @brief Enable DMA Rx
AnnaBridge	172:65be27845400	2314	* @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	172:65be27845400	2315	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2316	* @retval None
AnnaBridge	172:65be27845400	2317	*/
AnnaBridge	172:65be27845400	2318	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2319	{
AnnaBridge	172:65be27845400	2320	SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
AnnaBridge	172:65be27845400	2321	}
AnnaBridge	172:65be27845400	2322
AnnaBridge	172:65be27845400	2323	/**
AnnaBridge	172:65be27845400	2324	* @brief Disable DMA Rx
AnnaBridge	172:65be27845400	2325	* @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	172:65be27845400	2326	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2327	* @retval None
AnnaBridge	172:65be27845400	2328	*/
AnnaBridge	172:65be27845400	2329	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2330	{
AnnaBridge	172:65be27845400	2331	CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
AnnaBridge	172:65be27845400	2332	}
AnnaBridge	172:65be27845400	2333
AnnaBridge	172:65be27845400	2334	/**
AnnaBridge	172:65be27845400	2335	* @brief Check if DMA Rx is enabled
AnnaBridge	172:65be27845400	2336	* @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	172:65be27845400	2337	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2338	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2339	*/
AnnaBridge	172:65be27845400	2340	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2341	{
AnnaBridge	172:65be27845400	2342	return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2343	}
AnnaBridge	172:65be27845400	2344
AnnaBridge	172:65be27845400	2345	/**
AnnaBridge	172:65be27845400	2346	* @brief Enable DMA Tx
AnnaBridge	172:65be27845400	2347	* @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	172:65be27845400	2348	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2349	* @retval None
AnnaBridge	172:65be27845400	2350	*/
AnnaBridge	172:65be27845400	2351	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2352	{
AnnaBridge	172:65be27845400	2353	SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
AnnaBridge	172:65be27845400	2354	}
AnnaBridge	172:65be27845400	2355
AnnaBridge	172:65be27845400	2356	/**
AnnaBridge	172:65be27845400	2357	* @brief Disable DMA Tx
AnnaBridge	172:65be27845400	2358	* @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	172:65be27845400	2359	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2360	* @retval None
AnnaBridge	172:65be27845400	2361	*/
AnnaBridge	172:65be27845400	2362	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2363	{
AnnaBridge	172:65be27845400	2364	CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
AnnaBridge	172:65be27845400	2365	}
AnnaBridge	172:65be27845400	2366
AnnaBridge	172:65be27845400	2367	/**
AnnaBridge	172:65be27845400	2368	* @brief Check if DMA Tx is enabled
AnnaBridge	172:65be27845400	2369	* @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	172:65be27845400	2370	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2371	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2372	*/
AnnaBridge	172:65be27845400	2373	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2374	{
AnnaBridge	172:65be27845400	2375	return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2376	}
AnnaBridge	172:65be27845400	2377
AnnaBridge	172:65be27845400	2378	/**
AnnaBridge	172:65be27845400	2379	* @}
AnnaBridge	172:65be27845400	2380	*/
AnnaBridge	172:65be27845400	2381
AnnaBridge	172:65be27845400	2382	/** @defgroup SPI_LL_EF_DATA_Management DATA_Management
AnnaBridge	172:65be27845400	2383	* @{
AnnaBridge	172:65be27845400	2384	*/
AnnaBridge	172:65be27845400	2385
AnnaBridge	172:65be27845400	2386	/**
AnnaBridge	172:65be27845400	2387	* @brief Read Data Register
AnnaBridge	172:65be27845400	2388	* @rmtoll RXDR . LL_SPI_ReceiveData8
AnnaBridge	172:65be27845400	2389	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2390	* @retval 0..0xFF
AnnaBridge	172:65be27845400	2391	*/
AnnaBridge	172:65be27845400	2392	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2393	{
AnnaBridge	172:65be27845400	2394	return (((__IO uint8_t )&SPIx->RXDR));
AnnaBridge	172:65be27845400	2395	}
AnnaBridge	172:65be27845400	2396
AnnaBridge	172:65be27845400	2397	/**
AnnaBridge	172:65be27845400	2398	* @brief Read Data Register
AnnaBridge	172:65be27845400	2399	* @rmtoll RXDR . LL_SPI_ReceiveData16
AnnaBridge	172:65be27845400	2400	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2401	* @retval 0..0xFFFF
AnnaBridge	172:65be27845400	2402	*/
AnnaBridge	172:65be27845400	2403	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2404	{
AnnaBridge	172:65be27845400	2405	return (((__IO uint16_t )&SPIx->RXDR));
AnnaBridge	172:65be27845400	2406	}
AnnaBridge	172:65be27845400	2407
AnnaBridge	172:65be27845400	2408	/**
AnnaBridge	172:65be27845400	2409	* @brief Read Data Register
AnnaBridge	172:65be27845400	2410	* @rmtoll RXDR . LL_SPI_ReceiveData32
AnnaBridge	172:65be27845400	2411	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2412	* @retval 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2413	*/
AnnaBridge	172:65be27845400	2414	__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2415	{
AnnaBridge	172:65be27845400	2416	return (((__IO uint32_t )&SPIx->RXDR));
AnnaBridge	172:65be27845400	2417	}
AnnaBridge	172:65be27845400	2418
AnnaBridge	172:65be27845400	2419	/**
AnnaBridge	172:65be27845400	2420	* @brief Write Data Register
AnnaBridge	172:65be27845400	2421	* @rmtoll TXDR . LL_SPI_TransmitData8
AnnaBridge	172:65be27845400	2422	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2423	* @param TxData 0..0xFF
AnnaBridge	172:65be27845400	2424	* @retval None
AnnaBridge	172:65be27845400	2425	*/
AnnaBridge	172:65be27845400	2426	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	172:65be27845400	2427	{
AnnaBridge	172:65be27845400	2428	((__IO uint8_t )&SPIx->TXDR) = TxData;
AnnaBridge	172:65be27845400	2429	}
AnnaBridge	172:65be27845400	2430
AnnaBridge	172:65be27845400	2431	/**
AnnaBridge	172:65be27845400	2432	* @brief Write Data Register
AnnaBridge	172:65be27845400	2433	* @rmtoll TXDR . LL_SPI_TransmitData16
AnnaBridge	172:65be27845400	2434	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2435	* @param TxData 0..0xFFFF
AnnaBridge	172:65be27845400	2436	* @retval None
AnnaBridge	172:65be27845400	2437	*/
AnnaBridge	172:65be27845400	2438	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	172:65be27845400	2439	{
AnnaBridge	172:65be27845400	2440	((__IO uint16_t )&SPIx->TXDR) = TxData;
AnnaBridge	172:65be27845400	2441	}
AnnaBridge	172:65be27845400	2442
AnnaBridge	172:65be27845400	2443	/**
AnnaBridge	172:65be27845400	2444	* @brief Write Data Register
AnnaBridge	172:65be27845400	2445	* @rmtoll TXDR . LL_SPI_TransmitData32
AnnaBridge	172:65be27845400	2446	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2447	* @param TxData 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2448	* @retval None
AnnaBridge	172:65be27845400	2449	*/
AnnaBridge	172:65be27845400	2450	__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
AnnaBridge	172:65be27845400	2451	{
AnnaBridge	172:65be27845400	2452	((__IO uint32_t )&SPIx->TXDR) = TxData;
AnnaBridge	172:65be27845400	2453	}
AnnaBridge	172:65be27845400	2454
AnnaBridge	172:65be27845400	2455	/**
AnnaBridge	172:65be27845400	2456	* @brief Set polynomial for CRC calcul
AnnaBridge	172:65be27845400	2457	* @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	172:65be27845400	2458	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2459	* @param CRCPoly 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2460	* @retval None
AnnaBridge	172:65be27845400	2461	*/
AnnaBridge	172:65be27845400	2462	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	172:65be27845400	2463	{
AnnaBridge	172:65be27845400	2464	WRITE_REG(SPIx->CRCPOLY, CRCPoly);
AnnaBridge	172:65be27845400	2465	}
AnnaBridge	172:65be27845400	2466
AnnaBridge	172:65be27845400	2467	/**
AnnaBridge	172:65be27845400	2468	* @brief Get polynomial for CRC calcul
AnnaBridge	172:65be27845400	2469	* @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	172:65be27845400	2470	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2471	* @retval 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2472	*/
AnnaBridge	172:65be27845400	2473	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2474	{
AnnaBridge	172:65be27845400	2475	return (uint32_t)(READ_REG(SPIx->CRCPOLY));
AnnaBridge	172:65be27845400	2476	}
AnnaBridge	172:65be27845400	2477
AnnaBridge	172:65be27845400	2478	/**
AnnaBridge	172:65be27845400	2479	* @brief Set the underrun pattern
AnnaBridge	172:65be27845400	2480	* @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
AnnaBridge	172:65be27845400	2481	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2482	* @param Pattern 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2483	* @retval None
AnnaBridge	172:65be27845400	2484	*/
AnnaBridge	172:65be27845400	2485	__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
AnnaBridge	172:65be27845400	2486	{
AnnaBridge	172:65be27845400	2487	WRITE_REG(SPIx->UDRDR, Pattern);
AnnaBridge	172:65be27845400	2488	}
AnnaBridge	172:65be27845400	2489
AnnaBridge	172:65be27845400	2490	/**
AnnaBridge	172:65be27845400	2491	* @brief Get the underrun pattern
AnnaBridge	172:65be27845400	2492	* @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
AnnaBridge	172:65be27845400	2493	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2494	* @retval 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2495	*/
AnnaBridge	172:65be27845400	2496	__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2497	{
AnnaBridge	172:65be27845400	2498	return (uint32_t)(READ_REG(SPIx->UDRDR));
AnnaBridge	172:65be27845400	2499	}
AnnaBridge	172:65be27845400	2500
AnnaBridge	172:65be27845400	2501	/**
AnnaBridge	172:65be27845400	2502	* @brief Get Rx CRC
AnnaBridge	172:65be27845400	2503	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	172:65be27845400	2504	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2505	* @retval 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2506	*/
AnnaBridge	172:65be27845400	2507	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2508	{
AnnaBridge	172:65be27845400	2509	return (uint32_t)(READ_REG(SPIx->RXCRC));
AnnaBridge	172:65be27845400	2510	}
AnnaBridge	172:65be27845400	2511
AnnaBridge	172:65be27845400	2512	/**
AnnaBridge	172:65be27845400	2513	* @brief Get Tx CRC
AnnaBridge	172:65be27845400	2514	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	172:65be27845400	2515	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	2516	* @retval 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	2517	*/
AnnaBridge	172:65be27845400	2518	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2519	{
AnnaBridge	172:65be27845400	2520	return (uint32_t)(READ_REG(SPIx->TXCRC));
AnnaBridge	172:65be27845400	2521	}
AnnaBridge	172:65be27845400	2522
AnnaBridge	172:65be27845400	2523	/**
AnnaBridge	172:65be27845400	2524	* @}
AnnaBridge	172:65be27845400	2525	*/
AnnaBridge	172:65be27845400	2526
AnnaBridge	172:65be27845400	2527	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	2528	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	172:65be27845400	2529	* @{
AnnaBridge	172:65be27845400	2530	*/
AnnaBridge	172:65be27845400	2531
AnnaBridge	172:65be27845400	2532	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	172:65be27845400	2533	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	172:65be27845400	2534	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	172:65be27845400	2535
AnnaBridge	172:65be27845400	2536	/**
AnnaBridge	172:65be27845400	2537	* @}
AnnaBridge	172:65be27845400	2538	*/
AnnaBridge	172:65be27845400	2539	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	2540
AnnaBridge	172:65be27845400	2541
AnnaBridge	172:65be27845400	2542	/** @defgroup I2S_LL I2S
AnnaBridge	172:65be27845400	2543	* @{
AnnaBridge	172:65be27845400	2544	*/
AnnaBridge	172:65be27845400	2545
AnnaBridge	172:65be27845400	2546	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	2547	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	2548	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	2549
AnnaBridge	172:65be27845400	2550	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	2551	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	2552	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	172:65be27845400	2553	* @{
AnnaBridge	172:65be27845400	2554	*/
AnnaBridge	172:65be27845400	2555
AnnaBridge	172:65be27845400	2556	/**
AnnaBridge	172:65be27845400	2557	* @brief I2S Init structure definition
AnnaBridge	172:65be27845400	2558	*/
AnnaBridge	172:65be27845400	2559
AnnaBridge	172:65be27845400	2560	typedef struct
AnnaBridge	172:65be27845400	2561	{
AnnaBridge	172:65be27845400	2562	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	172:65be27845400	2563	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	172:65be27845400	2564
AnnaBridge	172:65be27845400	2565	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	172:65be27845400	2566
AnnaBridge	172:65be27845400	2567	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	172:65be27845400	2568	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	172:65be27845400	2569
AnnaBridge	172:65be27845400	2570	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	172:65be27845400	2571
AnnaBridge	172:65be27845400	2572
AnnaBridge	172:65be27845400	2573	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	172:65be27845400	2574	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	172:65be27845400	2575
AnnaBridge	172:65be27845400	2576	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	172:65be27845400	2577
AnnaBridge	172:65be27845400	2578
AnnaBridge	172:65be27845400	2579	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	172:65be27845400	2580	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	172:65be27845400	2581
AnnaBridge	172:65be27845400	2582	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	172:65be27845400	2583
AnnaBridge	172:65be27845400	2584
AnnaBridge	172:65be27845400	2585	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	172:65be27845400	2586	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	172:65be27845400	2587
AnnaBridge	172:65be27845400	2588	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	172:65be27845400	2589	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	172:65be27845400	2590
AnnaBridge	172:65be27845400	2591
AnnaBridge	172:65be27845400	2592	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	172:65be27845400	2593	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	172:65be27845400	2594
AnnaBridge	172:65be27845400	2595	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	172:65be27845400	2596
AnnaBridge	172:65be27845400	2597	} LL_I2S_InitTypeDef;
AnnaBridge	172:65be27845400	2598
AnnaBridge	172:65be27845400	2599	/**
AnnaBridge	172:65be27845400	2600	* @}
AnnaBridge	172:65be27845400	2601	*/
AnnaBridge	172:65be27845400	2602	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	172:65be27845400	2603
AnnaBridge	172:65be27845400	2604	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	2605	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	172:65be27845400	2606	* @{
AnnaBridge	172:65be27845400	2607	*/
AnnaBridge	172:65be27845400	2608
AnnaBridge	172:65be27845400	2609	/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
AnnaBridge	172:65be27845400	2610	* @{
AnnaBridge	172:65be27845400	2611	*/
AnnaBridge	172:65be27845400	2612	#define LL_I2S_DATAFORMAT_16B (0x00000000UL)
AnnaBridge	172:65be27845400	2613	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
AnnaBridge	172:65be27845400	2614	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0)
AnnaBridge	172:65be27845400	2615	#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0 \| SPI_I2SCFGR_DATFMT)
AnnaBridge	172:65be27845400	2616	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1)
AnnaBridge	172:65be27845400	2617	/**
AnnaBridge	172:65be27845400	2618	* @}
AnnaBridge	172:65be27845400	2619	*/
AnnaBridge	172:65be27845400	2620
AnnaBridge	172:65be27845400	2621	/** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
AnnaBridge	172:65be27845400	2622	* @{
AnnaBridge	172:65be27845400	2623	*/
AnnaBridge	172:65be27845400	2624	#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
AnnaBridge	172:65be27845400	2625	#define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
AnnaBridge	172:65be27845400	2626	/**
AnnaBridge	172:65be27845400	2627	* @}
AnnaBridge	172:65be27845400	2628	*/
AnnaBridge	172:65be27845400	2629
AnnaBridge	172:65be27845400	2630	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	172:65be27845400	2631	* @{
AnnaBridge	172:65be27845400	2632	*/
AnnaBridge	172:65be27845400	2633	#define LL_I2S_POLARITY_LOW (0x00000000UL)
AnnaBridge	172:65be27845400	2634	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
AnnaBridge	172:65be27845400	2635	/**
AnnaBridge	172:65be27845400	2636	* @}
AnnaBridge	172:65be27845400	2637	*/
AnnaBridge	172:65be27845400	2638
AnnaBridge	172:65be27845400	2639	/** @defgroup I2S_LL_EC_STANDARD I2S Standard
AnnaBridge	172:65be27845400	2640	* @{
AnnaBridge	172:65be27845400	2641	*/
AnnaBridge	172:65be27845400	2642	#define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
AnnaBridge	172:65be27845400	2643	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
AnnaBridge	172:65be27845400	2644	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
AnnaBridge	172:65be27845400	2645	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1)
AnnaBridge	172:65be27845400	2646	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC)
AnnaBridge	172:65be27845400	2647	/**
AnnaBridge	172:65be27845400	2648	* @}
AnnaBridge	172:65be27845400	2649	*/
AnnaBridge	172:65be27845400	2650
AnnaBridge	172:65be27845400	2651	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	172:65be27845400	2652	* @{
AnnaBridge	172:65be27845400	2653	*/
AnnaBridge	172:65be27845400	2654	#define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
AnnaBridge	172:65be27845400	2655	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
AnnaBridge	172:65be27845400	2656	#define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
AnnaBridge	172:65be27845400	2657	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
AnnaBridge	172:65be27845400	2658	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 \| SPI_I2SCFGR_I2SCFG_0)
AnnaBridge	172:65be27845400	2659	#define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 \| SPI_I2SCFGR_I2SCFG_0)
AnnaBridge	172:65be27845400	2660	/**
AnnaBridge	172:65be27845400	2661	* @}
AnnaBridge	172:65be27845400	2662	*/
AnnaBridge	172:65be27845400	2663
AnnaBridge	172:65be27845400	2664	/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
AnnaBridge	172:65be27845400	2665	* @{
AnnaBridge	172:65be27845400	2666	*/
AnnaBridge	172:65be27845400	2667	#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	172:65be27845400	2668	#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	172:65be27845400	2669	/**
AnnaBridge	172:65be27845400	2670	* @}
AnnaBridge	172:65be27845400	2671	*/
AnnaBridge	172:65be27845400	2672
AnnaBridge	172:65be27845400	2673	/** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
AnnaBridge	172:65be27845400	2674	* @{
AnnaBridge	172:65be27845400	2675	*/
AnnaBridge	172:65be27845400	2676	#define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
AnnaBridge	172:65be27845400	2677	#define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
AnnaBridge	172:65be27845400	2678	#define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
AnnaBridge	172:65be27845400	2679	#define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
AnnaBridge	172:65be27845400	2680	#define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
AnnaBridge	172:65be27845400	2681	#define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
AnnaBridge	172:65be27845400	2682	#define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
AnnaBridge	172:65be27845400	2683	#define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
AnnaBridge	172:65be27845400	2684	/**
AnnaBridge	172:65be27845400	2685	* @}
AnnaBridge	172:65be27845400	2686	*/
AnnaBridge	172:65be27845400	2687
AnnaBridge	172:65be27845400	2688	/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	172:65be27845400	2689	* @{
AnnaBridge	172:65be27845400	2690	*/
AnnaBridge	172:65be27845400	2691	#define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
AnnaBridge	172:65be27845400	2692	#define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
AnnaBridge	172:65be27845400	2693	/**
AnnaBridge	172:65be27845400	2694	* @}
AnnaBridge	172:65be27845400	2695	*/
AnnaBridge	172:65be27845400	2696
AnnaBridge	172:65be27845400	2697	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	2698
AnnaBridge	172:65be27845400	2699	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	172:65be27845400	2700	* @{
AnnaBridge	172:65be27845400	2701	*/
AnnaBridge	172:65be27845400	2702	#define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
AnnaBridge	172:65be27845400	2703	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
AnnaBridge	172:65be27845400	2704	/**
AnnaBridge	172:65be27845400	2705	* @}
AnnaBridge	172:65be27845400	2706	*/
AnnaBridge	172:65be27845400	2707
AnnaBridge	172:65be27845400	2708	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	172:65be27845400	2709	* @{
AnnaBridge	172:65be27845400	2710	*/
AnnaBridge	172:65be27845400	2711
AnnaBridge	172:65be27845400	2712	#define LL_I2S_AUDIOFREQ_192K 192000UL /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	172:65be27845400	2713	#define LL_I2S_AUDIOFREQ_96K 96000UL /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	172:65be27845400	2714	#define LL_I2S_AUDIOFREQ_48K 48000UL /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	172:65be27845400	2715	#define LL_I2S_AUDIOFREQ_44K 44100UL /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	172:65be27845400	2716	#define LL_I2S_AUDIOFREQ_32K 32000UL /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	172:65be27845400	2717	#define LL_I2S_AUDIOFREQ_22K 22050UL /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	172:65be27845400	2718	#define LL_I2S_AUDIOFREQ_16K 16000UL /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	172:65be27845400	2719	#define LL_I2S_AUDIOFREQ_11K 11025UL /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	172:65be27845400	2720	#define LL_I2S_AUDIOFREQ_8K 8000UL /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	172:65be27845400	2721	#define LL_I2S_AUDIOFREQ_DEFAULT 0UL /!< Audio Freq not specified. Register I2SDIV = 0 /
AnnaBridge	172:65be27845400	2722	/**
AnnaBridge	172:65be27845400	2723	* @}
AnnaBridge	172:65be27845400	2724	*/
AnnaBridge	172:65be27845400	2725	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	2726
AnnaBridge	172:65be27845400	2727	/**
AnnaBridge	172:65be27845400	2728	* @}
AnnaBridge	172:65be27845400	2729	*/
AnnaBridge	172:65be27845400	2730
AnnaBridge	172:65be27845400	2731	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	2732	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	172:65be27845400	2733	* @{
AnnaBridge	172:65be27845400	2734	*/
AnnaBridge	172:65be27845400	2735
AnnaBridge	172:65be27845400	2736	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	172:65be27845400	2737	* @{
AnnaBridge	172:65be27845400	2738	*/
AnnaBridge	172:65be27845400	2739
AnnaBridge	172:65be27845400	2740	/**
AnnaBridge	172:65be27845400	2741	* @brief Write a value in I2S register
AnnaBridge	172:65be27845400	2742	* @param __INSTANCE__ I2S Instance
AnnaBridge	172:65be27845400	2743	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	2744	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	2745	* @retval None
AnnaBridge	172:65be27845400	2746	*/
AnnaBridge	172:65be27845400	2747	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	2748
AnnaBridge	172:65be27845400	2749	/**
AnnaBridge	172:65be27845400	2750	* @brief Read a value in I2S register
AnnaBridge	172:65be27845400	2751	* @param __INSTANCE__ I2S Instance
AnnaBridge	172:65be27845400	2752	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	2753	* @retval Register value
AnnaBridge	172:65be27845400	2754	*/
AnnaBridge	172:65be27845400	2755	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	172:65be27845400	2756	/**
AnnaBridge	172:65be27845400	2757	* @}
AnnaBridge	172:65be27845400	2758	*/
AnnaBridge	172:65be27845400	2759
AnnaBridge	172:65be27845400	2760	/**
AnnaBridge	172:65be27845400	2761	* @}
AnnaBridge	172:65be27845400	2762	*/
AnnaBridge	172:65be27845400	2763
AnnaBridge	172:65be27845400	2764
AnnaBridge	172:65be27845400	2765	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	2766
AnnaBridge	172:65be27845400	2767	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	172:65be27845400	2768	* @{
AnnaBridge	172:65be27845400	2769	*/
AnnaBridge	172:65be27845400	2770
AnnaBridge	172:65be27845400	2771	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	172:65be27845400	2772	* @{
AnnaBridge	172:65be27845400	2773	*/
AnnaBridge	172:65be27845400	2774
AnnaBridge	172:65be27845400	2775	/**
AnnaBridge	172:65be27845400	2776	* @brief Set I2S Data frame format
AnnaBridge	172:65be27845400	2777	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	172:65be27845400	2778	* I2SCFGR CHLEN LL_I2S_SetDataFormat\n
AnnaBridge	172:65be27845400	2779	* I2SCFGR DATFMT LL_I2S_SetDataFormat
AnnaBridge	172:65be27845400	2780	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2781	* @param DataLength This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2782	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	172:65be27845400	2783	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	172:65be27845400	2784	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	172:65be27845400	2785	* @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
AnnaBridge	172:65be27845400	2786	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	172:65be27845400	2787	* @retval None
AnnaBridge	172:65be27845400	2788	*/
AnnaBridge	172:65be27845400	2789	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
AnnaBridge	172:65be27845400	2790	{
AnnaBridge	172:65be27845400	2791	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATFMT, DataLength);
AnnaBridge	172:65be27845400	2792	}
AnnaBridge	172:65be27845400	2793
AnnaBridge	172:65be27845400	2794	/**
AnnaBridge	172:65be27845400	2795	* @brief Get I2S Data frame format
AnnaBridge	172:65be27845400	2796	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	172:65be27845400	2797	* I2SCFGR CHLEN LL_I2S_GetDataFormat\n
AnnaBridge	172:65be27845400	2798	* I2SCFGR DATFMT LL_I2S_GetDataFormat
AnnaBridge	172:65be27845400	2799	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2800	* @retval Return value can be one of the following values:
AnnaBridge	172:65be27845400	2801	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	172:65be27845400	2802	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	172:65be27845400	2803	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	172:65be27845400	2804	* @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
AnnaBridge	172:65be27845400	2805	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	172:65be27845400	2806	*/
AnnaBridge	172:65be27845400	2807	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2808	{
AnnaBridge	172:65be27845400	2809	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATFMT));
AnnaBridge	172:65be27845400	2810	}
AnnaBridge	172:65be27845400	2811
AnnaBridge	172:65be27845400	2812	/**
AnnaBridge	172:65be27845400	2813	* @brief Set I2S Channel Length Type
AnnaBridge	172:65be27845400	2814	* @note This feature is usefull with SLAVE only
AnnaBridge	172:65be27845400	2815	* @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType
AnnaBridge	172:65be27845400	2816	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2817	* @param ChannelLengthType This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2818	* @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
AnnaBridge	172:65be27845400	2819	* @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
AnnaBridge	172:65be27845400	2820	* @retval None
AnnaBridge	172:65be27845400	2821	*/
AnnaBridge	172:65be27845400	2822	__STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
AnnaBridge	172:65be27845400	2823	{
AnnaBridge	172:65be27845400	2824	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
AnnaBridge	172:65be27845400	2825	}
AnnaBridge	172:65be27845400	2826
AnnaBridge	172:65be27845400	2827	/**
AnnaBridge	172:65be27845400	2828	* @brief Get I2S Channel Length Type
AnnaBridge	172:65be27845400	2829	* @note This feature is usefull with SLAVE only
AnnaBridge	172:65be27845400	2830	* @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType
AnnaBridge	172:65be27845400	2831	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2832	* @retval Return value can be one of the following values:
AnnaBridge	172:65be27845400	2833	* @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
AnnaBridge	172:65be27845400	2834	* @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
AnnaBridge	172:65be27845400	2835	*/
AnnaBridge	172:65be27845400	2836	__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2837	{
AnnaBridge	172:65be27845400	2838	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
AnnaBridge	172:65be27845400	2839	}
AnnaBridge	172:65be27845400	2840
AnnaBridge	172:65be27845400	2841	/**
AnnaBridge	172:65be27845400	2842	* @brief Invert the default polarity of WS signal
AnnaBridge	172:65be27845400	2843	* @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion
AnnaBridge	172:65be27845400	2844	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2845	* @retval None
AnnaBridge	172:65be27845400	2846	*/
AnnaBridge	172:65be27845400	2847	__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2848	{
AnnaBridge	172:65be27845400	2849	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
AnnaBridge	172:65be27845400	2850	}
AnnaBridge	172:65be27845400	2851
AnnaBridge	172:65be27845400	2852	/**
AnnaBridge	172:65be27845400	2853	* @brief Use the default polarity of WS signal
AnnaBridge	172:65be27845400	2854	* @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion
AnnaBridge	172:65be27845400	2855	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2856	* @retval None
AnnaBridge	172:65be27845400	2857	*/
AnnaBridge	172:65be27845400	2858	__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2859	{
AnnaBridge	172:65be27845400	2860	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
AnnaBridge	172:65be27845400	2861	}
AnnaBridge	172:65be27845400	2862
AnnaBridge	172:65be27845400	2863	/**
AnnaBridge	172:65be27845400	2864	* @brief Check if polarity of WS signal is inverted
AnnaBridge	172:65be27845400	2865	* @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion
AnnaBridge	172:65be27845400	2866	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2867	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	2868	*/
AnnaBridge	172:65be27845400	2869	__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2870	{
AnnaBridge	172:65be27845400	2871	return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2872	}
AnnaBridge	172:65be27845400	2873
AnnaBridge	172:65be27845400	2874	/**
AnnaBridge	172:65be27845400	2875	* @brief Set 2S Clock Polarity
AnnaBridge	172:65be27845400	2876	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	172:65be27845400	2877	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2878	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2879	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	172:65be27845400	2880	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	172:65be27845400	2881	* @retval None
AnnaBridge	172:65be27845400	2882	*/
AnnaBridge	172:65be27845400	2883	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	172:65be27845400	2884	{
AnnaBridge	172:65be27845400	2885	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
AnnaBridge	172:65be27845400	2886	}
AnnaBridge	172:65be27845400	2887
AnnaBridge	172:65be27845400	2888	/**
AnnaBridge	172:65be27845400	2889	* @brief Get 2S Clock Polarity
AnnaBridge	172:65be27845400	2890	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	172:65be27845400	2891	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2892	* @retval Return value can be one of the following values:
AnnaBridge	172:65be27845400	2893	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	172:65be27845400	2894	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	172:65be27845400	2895	*/
AnnaBridge	172:65be27845400	2896	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2897	{
AnnaBridge	172:65be27845400	2898	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	172:65be27845400	2899	}
AnnaBridge	172:65be27845400	2900
AnnaBridge	172:65be27845400	2901	/**
AnnaBridge	172:65be27845400	2902	* @brief Set I2S standard
AnnaBridge	172:65be27845400	2903	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	172:65be27845400	2904	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	172:65be27845400	2905	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2906	* @param Standard This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2907	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	172:65be27845400	2908	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	172:65be27845400	2909	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	172:65be27845400	2910	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	172:65be27845400	2911	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	172:65be27845400	2912	* @retval None
AnnaBridge	172:65be27845400	2913	*/
AnnaBridge	172:65be27845400	2914	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	172:65be27845400	2915	{
AnnaBridge	172:65be27845400	2916	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	172:65be27845400	2917	}
AnnaBridge	172:65be27845400	2918
AnnaBridge	172:65be27845400	2919	/**
AnnaBridge	172:65be27845400	2920	* @brief Get I2S standard
AnnaBridge	172:65be27845400	2921	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	172:65be27845400	2922	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	172:65be27845400	2923	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2924	* @retval Return value can be one of the following values:
AnnaBridge	172:65be27845400	2925	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	172:65be27845400	2926	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	172:65be27845400	2927	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	172:65be27845400	2928	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	172:65be27845400	2929	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	172:65be27845400	2930	*/
AnnaBridge	172:65be27845400	2931	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2932	{
AnnaBridge	172:65be27845400	2933	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	172:65be27845400	2934	}
AnnaBridge	172:65be27845400	2935
AnnaBridge	172:65be27845400	2936	/**
AnnaBridge	172:65be27845400	2937	* @brief Set I2S config
AnnaBridge	172:65be27845400	2938	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	172:65be27845400	2939	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2940	* @param Standard This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2941	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	172:65be27845400	2942	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	172:65be27845400	2943	* @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
AnnaBridge	172:65be27845400	2944	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	172:65be27845400	2945	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	172:65be27845400	2946	* @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
AnnaBridge	172:65be27845400	2947	* @retval None
AnnaBridge	172:65be27845400	2948	*/
AnnaBridge	172:65be27845400	2949	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	172:65be27845400	2950	{
AnnaBridge	172:65be27845400	2951	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
AnnaBridge	172:65be27845400	2952	}
AnnaBridge	172:65be27845400	2953
AnnaBridge	172:65be27845400	2954	/**
AnnaBridge	172:65be27845400	2955	* @brief Get I2S config
AnnaBridge	172:65be27845400	2956	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	172:65be27845400	2957	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2958	* @retval Return value can be one of the following values:
AnnaBridge	172:65be27845400	2959	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	172:65be27845400	2960	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	172:65be27845400	2961	* @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
AnnaBridge	172:65be27845400	2962	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	172:65be27845400	2963	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	172:65be27845400	2964	* @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
AnnaBridge	172:65be27845400	2965	*/
AnnaBridge	172:65be27845400	2966	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2967	{
AnnaBridge	172:65be27845400	2968	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	172:65be27845400	2969	}
AnnaBridge	172:65be27845400	2970
AnnaBridge	172:65be27845400	2971	/**
AnnaBridge	172:65be27845400	2972	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	172:65be27845400	2973	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	172:65be27845400	2974	* CR1 SPE LL_I2S_Enable
AnnaBridge	172:65be27845400	2975	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2976	* @retval None
AnnaBridge	172:65be27845400	2977	*/
AnnaBridge	172:65be27845400	2978	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2979	{
AnnaBridge	172:65be27845400	2980	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
AnnaBridge	172:65be27845400	2981	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	172:65be27845400	2982	}
AnnaBridge	172:65be27845400	2983
AnnaBridge	172:65be27845400	2984	/**
AnnaBridge	172:65be27845400	2985	* @brief Disable I2S peripheral and disable I2S mode
AnnaBridge	172:65be27845400	2986	* @rmtoll CR1 SPE LL_I2S_Disable\n
AnnaBridge	172:65be27845400	2987	* I2SCFGR I2SMOD LL_I2S_Disable
AnnaBridge	172:65be27845400	2988	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	2989	* @retval None
AnnaBridge	172:65be27845400	2990	*/
AnnaBridge	172:65be27845400	2991	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	2992	{
AnnaBridge	172:65be27845400	2993	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	172:65be27845400	2994	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
AnnaBridge	172:65be27845400	2995	}
AnnaBridge	172:65be27845400	2996
AnnaBridge	172:65be27845400	2997	/**
AnnaBridge	172:65be27845400	2998	* @brief Swap the SDO and SDI pin
AnnaBridge	172:65be27845400	2999	* @note This configuration can not be changed when I2S is enabled.
AnnaBridge	172:65be27845400	3000	* @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap
AnnaBridge	172:65be27845400	3001	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3002	* @retval None
AnnaBridge	172:65be27845400	3003	*/
AnnaBridge	172:65be27845400	3004	__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3005	{
AnnaBridge	172:65be27845400	3006	LL_SPI_EnableIOSwap(SPIx);
AnnaBridge	172:65be27845400	3007	}
AnnaBridge	172:65be27845400	3008
AnnaBridge	172:65be27845400	3009	/**
AnnaBridge	172:65be27845400	3010	* @brief Restore default function for SDO and SDI pin
AnnaBridge	172:65be27845400	3011	* @note This configuration can not be changed when I2S is enabled.
AnnaBridge	172:65be27845400	3012	* @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap
AnnaBridge	172:65be27845400	3013	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3014	* @retval None
AnnaBridge	172:65be27845400	3015	*/
AnnaBridge	172:65be27845400	3016	__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3017	{
AnnaBridge	172:65be27845400	3018	LL_SPI_DisableIOSwap(SPIx);
AnnaBridge	172:65be27845400	3019	}
AnnaBridge	172:65be27845400	3020
AnnaBridge	172:65be27845400	3021	/**
AnnaBridge	172:65be27845400	3022	* @brief Check if SDO and SDI pin are swapped
AnnaBridge	172:65be27845400	3023	* @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap
AnnaBridge	172:65be27845400	3024	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3025	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3026	*/
AnnaBridge	172:65be27845400	3027	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3028	{
AnnaBridge	172:65be27845400	3029	return LL_SPI_IsEnabledIOSwap(SPIx);
AnnaBridge	172:65be27845400	3030	}
AnnaBridge	172:65be27845400	3031
AnnaBridge	172:65be27845400	3032	/**
AnnaBridge	172:65be27845400	3033	* @brief Enable GPIO control
AnnaBridge	172:65be27845400	3034	* @note This configuration can not be changed when I2S is enabled.
AnnaBridge	172:65be27845400	3035	* @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl
AnnaBridge	172:65be27845400	3036	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3037	* @retval None
AnnaBridge	172:65be27845400	3038	*/
AnnaBridge	172:65be27845400	3039	__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3040	{
AnnaBridge	172:65be27845400	3041	LL_SPI_EnableGPIOControl(SPIx);
AnnaBridge	172:65be27845400	3042	}
AnnaBridge	172:65be27845400	3043
AnnaBridge	172:65be27845400	3044	/**
AnnaBridge	172:65be27845400	3045	* @brief Disable GPIO control
AnnaBridge	172:65be27845400	3046	* @note This configuration can not be changed when I2S is enabled.
AnnaBridge	172:65be27845400	3047	* @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl
AnnaBridge	172:65be27845400	3048	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3049	* @retval None
AnnaBridge	172:65be27845400	3050	*/
AnnaBridge	172:65be27845400	3051	__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3052	{
AnnaBridge	172:65be27845400	3053	LL_SPI_DisableGPIOControl(SPIx);
AnnaBridge	172:65be27845400	3054	}
AnnaBridge	172:65be27845400	3055
AnnaBridge	172:65be27845400	3056	/**
AnnaBridge	172:65be27845400	3057	* @brief Check if GPIO control is active
AnnaBridge	172:65be27845400	3058	* @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl
AnnaBridge	172:65be27845400	3059	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3060	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3061	*/
AnnaBridge	172:65be27845400	3062	__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3063	{
AnnaBridge	172:65be27845400	3064	return LL_SPI_IsEnabledGPIOControl(SPIx);
AnnaBridge	172:65be27845400	3065	}
AnnaBridge	172:65be27845400	3066
AnnaBridge	172:65be27845400	3067	/**
AnnaBridge	172:65be27845400	3068	* @brief Lock the AF configuration of associated IOs
AnnaBridge	172:65be27845400	3069	* @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
AnnaBridge	172:65be27845400	3070	* The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
AnnaBridge	172:65be27845400	3071	* @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
AnnaBridge	172:65be27845400	3072	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3073	* @retval None
AnnaBridge	172:65be27845400	3074	*/
AnnaBridge	172:65be27845400	3075	__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3076	{
AnnaBridge	172:65be27845400	3077	LL_SPI_EnableIOLock(SPIx);
AnnaBridge	172:65be27845400	3078	}
AnnaBridge	172:65be27845400	3079
AnnaBridge	172:65be27845400	3080	/**
AnnaBridge	172:65be27845400	3081	* @brief Check if the the SPI_CFG2 register is locked
AnnaBridge	172:65be27845400	3082	* @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock
AnnaBridge	172:65be27845400	3083	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3084	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3085	*/
AnnaBridge	172:65be27845400	3086	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3087	{
AnnaBridge	172:65be27845400	3088	return LL_SPI_IsEnabledIOLock(SPIx);
AnnaBridge	172:65be27845400	3089	}
AnnaBridge	172:65be27845400	3090
AnnaBridge	172:65be27845400	3091	/**
AnnaBridge	172:65be27845400	3092	* @brief Set Transfer Bit Order
AnnaBridge	172:65be27845400	3093	* @note This configuration can not be changed when I2S is enabled.
AnnaBridge	172:65be27845400	3094	* @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder
AnnaBridge	172:65be27845400	3095	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3096	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3097	* @arg @ref LL_I2S_LSB_FIRST
AnnaBridge	172:65be27845400	3098	* @arg @ref LL_I2S_MSB_FIRST
AnnaBridge	172:65be27845400	3099	* @retval None
AnnaBridge	172:65be27845400	3100	*/
AnnaBridge	172:65be27845400	3101	__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	172:65be27845400	3102	{
AnnaBridge	172:65be27845400	3103	LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
AnnaBridge	172:65be27845400	3104	}
AnnaBridge	172:65be27845400	3105	/**
AnnaBridge	172:65be27845400	3106	* @brief Get Transfer Bit Order
AnnaBridge	172:65be27845400	3107	* @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder
AnnaBridge	172:65be27845400	3108	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3109	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3110	* @arg @ref LL_I2S_LSB_FIRST
AnnaBridge	172:65be27845400	3111	* @arg @ref LL_I2S_MSB_FIRST
AnnaBridge	172:65be27845400	3112	*/
AnnaBridge	172:65be27845400	3113	__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3114	{
AnnaBridge	172:65be27845400	3115	return LL_SPI_GetTransferBitOrder(SPIx);
AnnaBridge	172:65be27845400	3116	}
AnnaBridge	172:65be27845400	3117
AnnaBridge	172:65be27845400	3118	/**
AnnaBridge	172:65be27845400	3119	* @brief Start effective transfer on wire
AnnaBridge	172:65be27845400	3120	* @rmtoll CR1 CSTART LL_I2S_StartTransfer
AnnaBridge	172:65be27845400	3121	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3122	* @retval None
AnnaBridge	172:65be27845400	3123	*/
AnnaBridge	172:65be27845400	3124	__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3125	{
AnnaBridge	172:65be27845400	3126	LL_SPI_StartMasterTransfer(SPIx);
AnnaBridge	172:65be27845400	3127	}
AnnaBridge	172:65be27845400	3128
AnnaBridge	172:65be27845400	3129	/**
AnnaBridge	172:65be27845400	3130	* @brief Check if there is an unfinished transfer
AnnaBridge	172:65be27845400	3131	* @rmtoll CR1 CSTART LL_I2S_IsTransferActive
AnnaBridge	172:65be27845400	3132	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3133	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3134	*/
AnnaBridge	172:65be27845400	3135	__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3136	{
AnnaBridge	172:65be27845400	3137	return LL_SPI_IsActiveMasterTransfer(SPIx);
AnnaBridge	172:65be27845400	3138	}
AnnaBridge	172:65be27845400	3139
AnnaBridge	172:65be27845400	3140	/**
AnnaBridge	172:65be27845400	3141	* @brief Set threshold of FIFO that triggers a transfer event
AnnaBridge	172:65be27845400	3142	* @note This configuration can not be changed when I2S is enabled.
AnnaBridge	172:65be27845400	3143	* @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold
AnnaBridge	172:65be27845400	3144	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3145	* @param Threshold This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3146	* @arg @ref LL_I2S_FIFO_TH_01DATA
AnnaBridge	172:65be27845400	3147	* @arg @ref LL_I2S_FIFO_TH_02DATA
AnnaBridge	172:65be27845400	3148	* @arg @ref LL_I2S_FIFO_TH_03DATA
AnnaBridge	172:65be27845400	3149	* @arg @ref LL_I2S_FIFO_TH_04DATA
AnnaBridge	172:65be27845400	3150	* @arg @ref LL_I2S_FIFO_TH_05DATA
AnnaBridge	172:65be27845400	3151	* @arg @ref LL_I2S_FIFO_TH_06DATA
AnnaBridge	172:65be27845400	3152	* @arg @ref LL_I2S_FIFO_TH_07DATA
AnnaBridge	172:65be27845400	3153	* @arg @ref LL_I2S_FIFO_TH_08DATA
AnnaBridge	172:65be27845400	3154	* @retval None
AnnaBridge	172:65be27845400	3155	*/
AnnaBridge	172:65be27845400	3156	__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
AnnaBridge	172:65be27845400	3157	{
AnnaBridge	172:65be27845400	3158	LL_SPI_SetFIFOThreshold(SPIx, Threshold);
AnnaBridge	172:65be27845400	3159	}
AnnaBridge	172:65be27845400	3160
AnnaBridge	172:65be27845400	3161	/**
AnnaBridge	172:65be27845400	3162	* @brief Get threshold of FIFO that triggers a transfer event
AnnaBridge	172:65be27845400	3163	* @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold
AnnaBridge	172:65be27845400	3164	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3165	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3166	* @arg @ref LL_I2S_FIFO_TH_01DATA
AnnaBridge	172:65be27845400	3167	* @arg @ref LL_I2S_FIFO_TH_02DATA
AnnaBridge	172:65be27845400	3168	* @arg @ref LL_I2S_FIFO_TH_03DATA
AnnaBridge	172:65be27845400	3169	* @arg @ref LL_I2S_FIFO_TH_04DATA
AnnaBridge	172:65be27845400	3170	* @arg @ref LL_I2S_FIFO_TH_05DATA
AnnaBridge	172:65be27845400	3171	* @arg @ref LL_I2S_FIFO_TH_06DATA
AnnaBridge	172:65be27845400	3172	* @arg @ref LL_I2S_FIFO_TH_07DATA
AnnaBridge	172:65be27845400	3173	* @arg @ref LL_I2S_FIFO_TH_08DATA
AnnaBridge	172:65be27845400	3174	*/
AnnaBridge	172:65be27845400	3175	__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3176	{
AnnaBridge	172:65be27845400	3177	return LL_SPI_GetFIFOThreshold(SPIx);
AnnaBridge	172:65be27845400	3178	}
AnnaBridge	172:65be27845400	3179
AnnaBridge	172:65be27845400	3180	/**
AnnaBridge	172:65be27845400	3181	* @brief Set I2S linear prescaler
AnnaBridge	172:65be27845400	3182	* @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	172:65be27845400	3183	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3184	* @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	3185	* @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	172:65be27845400	3186	* @retval None
AnnaBridge	172:65be27845400	3187	*/
AnnaBridge	172:65be27845400	3188	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
AnnaBridge	172:65be27845400	3189	{
AnnaBridge	172:65be27845400	3190	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
AnnaBridge	172:65be27845400	3191	}
AnnaBridge	172:65be27845400	3192
AnnaBridge	172:65be27845400	3193	/**
AnnaBridge	172:65be27845400	3194	* @brief Get I2S linear prescaler
AnnaBridge	172:65be27845400	3195	* @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	172:65be27845400	3196	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3197	* @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	3198	*/
AnnaBridge	172:65be27845400	3199	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3200	{
AnnaBridge	172:65be27845400	3201	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
AnnaBridge	172:65be27845400	3202	}
AnnaBridge	172:65be27845400	3203
AnnaBridge	172:65be27845400	3204	/**
AnnaBridge	172:65be27845400	3205	* @brief Set I2S parity prescaler
AnnaBridge	172:65be27845400	3206	* @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity
AnnaBridge	172:65be27845400	3207	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3208	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3209	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	172:65be27845400	3210	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	172:65be27845400	3211	* @retval None
AnnaBridge	172:65be27845400	3212	*/
AnnaBridge	172:65be27845400	3213	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	172:65be27845400	3214	{
AnnaBridge	172:65be27845400	3215	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
AnnaBridge	172:65be27845400	3216	}
AnnaBridge	172:65be27845400	3217
AnnaBridge	172:65be27845400	3218	/**
AnnaBridge	172:65be27845400	3219	* @brief Get I2S parity prescaler
AnnaBridge	172:65be27845400	3220	* @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity
AnnaBridge	172:65be27845400	3221	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3222	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3223	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	172:65be27845400	3224	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	172:65be27845400	3225	*/
AnnaBridge	172:65be27845400	3226	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3227	{
AnnaBridge	172:65be27845400	3228	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
AnnaBridge	172:65be27845400	3229	}
AnnaBridge	172:65be27845400	3230
AnnaBridge	172:65be27845400	3231	/**
AnnaBridge	172:65be27845400	3232	* @brief Enable the Master Clock Output (Pin MCK)
AnnaBridge	172:65be27845400	3233	* @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	172:65be27845400	3234	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	3235	* @retval None
AnnaBridge	172:65be27845400	3236	*/
AnnaBridge	172:65be27845400	3237	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3238	{
AnnaBridge	172:65be27845400	3239	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
AnnaBridge	172:65be27845400	3240	}
AnnaBridge	172:65be27845400	3241
AnnaBridge	172:65be27845400	3242	/**
AnnaBridge	172:65be27845400	3243	* @brief Disable the Master Clock Ouput (Pin MCK)
AnnaBridge	172:65be27845400	3244	* @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	172:65be27845400	3245	* @param SPIx SPI Handle
AnnaBridge	172:65be27845400	3246	* @retval None
AnnaBridge	172:65be27845400	3247	*/
AnnaBridge	172:65be27845400	3248	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3249	{
AnnaBridge	172:65be27845400	3250	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
AnnaBridge	172:65be27845400	3251	}
AnnaBridge	172:65be27845400	3252
AnnaBridge	172:65be27845400	3253	/**
AnnaBridge	172:65be27845400	3254	* @brief Check if the master clock output (Pin MCK) is enabled
AnnaBridge	172:65be27845400	3255	* @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	172:65be27845400	3256	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3257	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3258	*/
AnnaBridge	172:65be27845400	3259	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3260	{
AnnaBridge	172:65be27845400	3261	return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3262	}
AnnaBridge	172:65be27845400	3263
AnnaBridge	172:65be27845400	3264
AnnaBridge	172:65be27845400	3265	/** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	172:65be27845400	3266	* @{
AnnaBridge	172:65be27845400	3267	*/
AnnaBridge	172:65be27845400	3268
AnnaBridge	172:65be27845400	3269	/**
AnnaBridge	172:65be27845400	3270	* @brief Check if there enough data in FIFO to read a full packet
AnnaBridge	172:65be27845400	3271	* @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP
AnnaBridge	172:65be27845400	3272	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3273	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3274	*/
AnnaBridge	172:65be27845400	3275	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3276	{
AnnaBridge	172:65be27845400	3277	return LL_SPI_IsActiveFlag_RXP(SPIx);
AnnaBridge	172:65be27845400	3278	}
AnnaBridge	172:65be27845400	3279
AnnaBridge	172:65be27845400	3280	/**
AnnaBridge	172:65be27845400	3281	* @brief Check if there enough space in FIFO to hold a full packet
AnnaBridge	172:65be27845400	3282	* @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP
AnnaBridge	172:65be27845400	3283	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3284	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3285	*/
AnnaBridge	172:65be27845400	3286	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3287	{
AnnaBridge	172:65be27845400	3288	return LL_SPI_IsActiveFlag_TXP(SPIx);
AnnaBridge	172:65be27845400	3289	}
AnnaBridge	172:65be27845400	3290
AnnaBridge	172:65be27845400	3291	/**
AnnaBridge	172:65be27845400	3292	* @brief Get Underrun error flag
AnnaBridge	172:65be27845400	3293	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	172:65be27845400	3294	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3295	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3296	*/
AnnaBridge	172:65be27845400	3297	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3298	{
AnnaBridge	172:65be27845400	3299	return LL_SPI_IsActiveFlag_UDR(SPIx);
AnnaBridge	172:65be27845400	3300	}
AnnaBridge	172:65be27845400	3301
AnnaBridge	172:65be27845400	3302	/**
AnnaBridge	172:65be27845400	3303	* @brief Get Overrun error flag
AnnaBridge	172:65be27845400	3304	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	172:65be27845400	3305	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3306	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3307	*/
AnnaBridge	172:65be27845400	3308	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3309	{
AnnaBridge	172:65be27845400	3310	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	172:65be27845400	3311	}
AnnaBridge	172:65be27845400	3312
AnnaBridge	172:65be27845400	3313	/**
AnnaBridge	172:65be27845400	3314	* @brief Get TI Frame format error flag
AnnaBridge	172:65be27845400	3315	* @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE
AnnaBridge	172:65be27845400	3316	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3317	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3318	*/
AnnaBridge	172:65be27845400	3319	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3320	{
AnnaBridge	172:65be27845400	3321	return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge	172:65be27845400	3322	}
AnnaBridge	172:65be27845400	3323
AnnaBridge	172:65be27845400	3324	/**
AnnaBridge	172:65be27845400	3325	* @brief Clear Underrun error flag
AnnaBridge	172:65be27845400	3326	* @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR
AnnaBridge	172:65be27845400	3327	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3328	* @retval None
AnnaBridge	172:65be27845400	3329	*/
AnnaBridge	172:65be27845400	3330	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3331	{
AnnaBridge	172:65be27845400	3332	LL_SPI_ClearFlag_UDR(SPIx);
AnnaBridge	172:65be27845400	3333	}
AnnaBridge	172:65be27845400	3334
AnnaBridge	172:65be27845400	3335	/**
AnnaBridge	172:65be27845400	3336	* @brief Clear Overrun error flag
AnnaBridge	172:65be27845400	3337	* @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR
AnnaBridge	172:65be27845400	3338	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3339	* @retval None
AnnaBridge	172:65be27845400	3340	*/
AnnaBridge	172:65be27845400	3341	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3342	{
AnnaBridge	172:65be27845400	3343	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	172:65be27845400	3344	}
AnnaBridge	172:65be27845400	3345
AnnaBridge	172:65be27845400	3346	/**
AnnaBridge	172:65be27845400	3347	* @brief Clear Frame format error flag
AnnaBridge	172:65be27845400	3348	* @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE
AnnaBridge	172:65be27845400	3349	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3350	* @retval None
AnnaBridge	172:65be27845400	3351	*/
AnnaBridge	172:65be27845400	3352	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3353	{
AnnaBridge	172:65be27845400	3354	LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge	172:65be27845400	3355	}
AnnaBridge	172:65be27845400	3356
AnnaBridge	172:65be27845400	3357	/**
AnnaBridge	172:65be27845400	3358	* @}
AnnaBridge	172:65be27845400	3359	*/
AnnaBridge	172:65be27845400	3360
AnnaBridge	172:65be27845400	3361	/** @defgroup I2S_LL_EF_IT_Management IT_Management
AnnaBridge	172:65be27845400	3362	* @{
AnnaBridge	172:65be27845400	3363	*/
AnnaBridge	172:65be27845400	3364
AnnaBridge	172:65be27845400	3365	/**
AnnaBridge	172:65be27845400	3366	* @brief Enable Rx Packet available IT
AnnaBridge	172:65be27845400	3367	* @rmtoll IER RXPIE LL_I2S_EnableIT_RXP
AnnaBridge	172:65be27845400	3368	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3369	* @retval None
AnnaBridge	172:65be27845400	3370	*/
AnnaBridge	172:65be27845400	3371	__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3372	{
AnnaBridge	172:65be27845400	3373	LL_SPI_EnableIT_RXP(SPIx);
AnnaBridge	172:65be27845400	3374	}
AnnaBridge	172:65be27845400	3375
AnnaBridge	172:65be27845400	3376	/**
AnnaBridge	172:65be27845400	3377	* @brief Enable Tx Packet space available IT
AnnaBridge	172:65be27845400	3378	* @rmtoll IER TXPIE LL_I2S_EnableIT_TXP
AnnaBridge	172:65be27845400	3379	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3380	* @retval None
AnnaBridge	172:65be27845400	3381	*/
AnnaBridge	172:65be27845400	3382	__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3383	{
AnnaBridge	172:65be27845400	3384	LL_SPI_EnableIT_TXP(SPIx);
AnnaBridge	172:65be27845400	3385	}
AnnaBridge	172:65be27845400	3386
AnnaBridge	172:65be27845400	3387	/**
AnnaBridge	172:65be27845400	3388	* @brief Enable Underrun IT
AnnaBridge	172:65be27845400	3389	* @rmtoll IER UDRIE LL_I2S_EnableIT_UDR
AnnaBridge	172:65be27845400	3390	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3391	* @retval None
AnnaBridge	172:65be27845400	3392	*/
AnnaBridge	172:65be27845400	3393	__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3394	{
AnnaBridge	172:65be27845400	3395	LL_SPI_EnableIT_UDR(SPIx);
AnnaBridge	172:65be27845400	3396	}
AnnaBridge	172:65be27845400	3397
AnnaBridge	172:65be27845400	3398	/**
AnnaBridge	172:65be27845400	3399	* @brief Enable Overrun IT
AnnaBridge	172:65be27845400	3400	* @rmtoll IER OVRIE LL_I2S_EnableIT_OVR
AnnaBridge	172:65be27845400	3401	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3402	* @retval None
AnnaBridge	172:65be27845400	3403	*/
AnnaBridge	172:65be27845400	3404	__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3405	{
AnnaBridge	172:65be27845400	3406	LL_SPI_EnableIT_OVR(SPIx);
AnnaBridge	172:65be27845400	3407	}
AnnaBridge	172:65be27845400	3408
AnnaBridge	172:65be27845400	3409	/**
AnnaBridge	172:65be27845400	3410	* @brief Enable TI Frame Format Error IT
AnnaBridge	172:65be27845400	3411	* @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE
AnnaBridge	172:65be27845400	3412	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3413	* @retval None
AnnaBridge	172:65be27845400	3414	*/
AnnaBridge	172:65be27845400	3415	__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3416	{
AnnaBridge	172:65be27845400	3417	LL_SPI_EnableIT_FRE(SPIx);
AnnaBridge	172:65be27845400	3418	}
AnnaBridge	172:65be27845400	3419
AnnaBridge	172:65be27845400	3420	/**
AnnaBridge	172:65be27845400	3421	* @brief Disable Rx Packet available IT
AnnaBridge	172:65be27845400	3422	* @rmtoll IER RXPIE LL_I2S_DisableIT_RXP
AnnaBridge	172:65be27845400	3423	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3424	* @retval None
AnnaBridge	172:65be27845400	3425	*/
AnnaBridge	172:65be27845400	3426	__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3427	{
AnnaBridge	172:65be27845400	3428	LL_SPI_DisableIT_RXP(SPIx);
AnnaBridge	172:65be27845400	3429	}
AnnaBridge	172:65be27845400	3430
AnnaBridge	172:65be27845400	3431	/**
AnnaBridge	172:65be27845400	3432	* @brief Disable Tx Packet space available IT
AnnaBridge	172:65be27845400	3433	* @rmtoll IER TXPIE LL_I2S_DisableIT_TXP
AnnaBridge	172:65be27845400	3434	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3435	* @retval None
AnnaBridge	172:65be27845400	3436	*/
AnnaBridge	172:65be27845400	3437	__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3438	{
AnnaBridge	172:65be27845400	3439	LL_SPI_DisableIT_TXP(SPIx);
AnnaBridge	172:65be27845400	3440	}
AnnaBridge	172:65be27845400	3441
AnnaBridge	172:65be27845400	3442	/**
AnnaBridge	172:65be27845400	3443	* @brief Disable Underrun IT
AnnaBridge	172:65be27845400	3444	* @rmtoll IER UDRIE LL_I2S_DisableIT_UDR
AnnaBridge	172:65be27845400	3445	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3446	* @retval None
AnnaBridge	172:65be27845400	3447	*/
AnnaBridge	172:65be27845400	3448	__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3449	{
AnnaBridge	172:65be27845400	3450	LL_SPI_DisableIT_UDR(SPIx);
AnnaBridge	172:65be27845400	3451	}
AnnaBridge	172:65be27845400	3452
AnnaBridge	172:65be27845400	3453	/**
AnnaBridge	172:65be27845400	3454	* @brief Disable Overrun IT
AnnaBridge	172:65be27845400	3455	* @rmtoll IER OVRIE LL_I2S_DisableIT_OVR
AnnaBridge	172:65be27845400	3456	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3457	* @retval None
AnnaBridge	172:65be27845400	3458	*/
AnnaBridge	172:65be27845400	3459	__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3460	{
AnnaBridge	172:65be27845400	3461	LL_SPI_DisableIT_OVR(SPIx);
AnnaBridge	172:65be27845400	3462	}
AnnaBridge	172:65be27845400	3463
AnnaBridge	172:65be27845400	3464	/**
AnnaBridge	172:65be27845400	3465	* @brief Disable TI Frame Format Error IT
AnnaBridge	172:65be27845400	3466	* @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE
AnnaBridge	172:65be27845400	3467	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3468	* @retval None
AnnaBridge	172:65be27845400	3469	*/
AnnaBridge	172:65be27845400	3470	__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3471	{
AnnaBridge	172:65be27845400	3472	LL_SPI_DisableIT_FRE(SPIx);
AnnaBridge	172:65be27845400	3473	}
AnnaBridge	172:65be27845400	3474
AnnaBridge	172:65be27845400	3475	/**
AnnaBridge	172:65be27845400	3476	* @brief Check if Rx Packet available IT is enabled
AnnaBridge	172:65be27845400	3477	* @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP
AnnaBridge	172:65be27845400	3478	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3479	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3480	*/
AnnaBridge	172:65be27845400	3481	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3482	{
AnnaBridge	172:65be27845400	3483	return LL_SPI_IsEnabledIT_RXP(SPIx);
AnnaBridge	172:65be27845400	3484	}
AnnaBridge	172:65be27845400	3485
AnnaBridge	172:65be27845400	3486	/**
AnnaBridge	172:65be27845400	3487	* @brief Check if Tx Packet space available IT is enabled
AnnaBridge	172:65be27845400	3488	* @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP
AnnaBridge	172:65be27845400	3489	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3490	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3491	*/
AnnaBridge	172:65be27845400	3492	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3493	{
AnnaBridge	172:65be27845400	3494	return LL_SPI_IsEnabledIT_TXP(SPIx);
AnnaBridge	172:65be27845400	3495	}
AnnaBridge	172:65be27845400	3496
AnnaBridge	172:65be27845400	3497	/**
AnnaBridge	172:65be27845400	3498	* @brief Check if Underrun IT is enabled
AnnaBridge	172:65be27845400	3499	* @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR
AnnaBridge	172:65be27845400	3500	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3501	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3502	*/
AnnaBridge	172:65be27845400	3503	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3504	{
AnnaBridge	172:65be27845400	3505	return LL_SPI_IsEnabledIT_UDR(SPIx);
AnnaBridge	172:65be27845400	3506	}
AnnaBridge	172:65be27845400	3507
AnnaBridge	172:65be27845400	3508	/**
AnnaBridge	172:65be27845400	3509	* @brief Check if Overrun IT is enabled
AnnaBridge	172:65be27845400	3510	* @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR
AnnaBridge	172:65be27845400	3511	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3512	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3513	*/
AnnaBridge	172:65be27845400	3514	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3515	{
AnnaBridge	172:65be27845400	3516	return LL_SPI_IsEnabledIT_OVR(SPIx);
AnnaBridge	172:65be27845400	3517	}
AnnaBridge	172:65be27845400	3518
AnnaBridge	172:65be27845400	3519	/**
AnnaBridge	172:65be27845400	3520	* @brief Check if TI Frame Format Error IT is enabled
AnnaBridge	172:65be27845400	3521	* @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE
AnnaBridge	172:65be27845400	3522	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3523	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3524	*/
AnnaBridge	172:65be27845400	3525	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3526	{
AnnaBridge	172:65be27845400	3527	return LL_SPI_IsEnabledIT_FRE(SPIx);
AnnaBridge	172:65be27845400	3528	}
AnnaBridge	172:65be27845400	3529
AnnaBridge	172:65be27845400	3530	/**
AnnaBridge	172:65be27845400	3531	* @}
AnnaBridge	172:65be27845400	3532	*/
AnnaBridge	172:65be27845400	3533
AnnaBridge	172:65be27845400	3534	/** @defgroup I2S_LL_EF_DMA_Management DMA_Management
AnnaBridge	172:65be27845400	3535	* @{
AnnaBridge	172:65be27845400	3536	*/
AnnaBridge	172:65be27845400	3537
AnnaBridge	172:65be27845400	3538	/**
AnnaBridge	172:65be27845400	3539	* @brief Enable DMA Rx
AnnaBridge	172:65be27845400	3540	* @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	172:65be27845400	3541	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3542	* @retval None
AnnaBridge	172:65be27845400	3543	*/
AnnaBridge	172:65be27845400	3544	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3545	{
AnnaBridge	172:65be27845400	3546	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	172:65be27845400	3547	}
AnnaBridge	172:65be27845400	3548
AnnaBridge	172:65be27845400	3549	/**
AnnaBridge	172:65be27845400	3550	* @brief Disable DMA Rx
AnnaBridge	172:65be27845400	3551	* @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	172:65be27845400	3552	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3553	* @retval None
AnnaBridge	172:65be27845400	3554	*/
AnnaBridge	172:65be27845400	3555	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3556	{
AnnaBridge	172:65be27845400	3557	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	172:65be27845400	3558	}
AnnaBridge	172:65be27845400	3559
AnnaBridge	172:65be27845400	3560	/**
AnnaBridge	172:65be27845400	3561	* @brief Check if DMA Rx is enabled
AnnaBridge	172:65be27845400	3562	* @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	172:65be27845400	3563	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3564	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3565	*/
AnnaBridge	172:65be27845400	3566	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3567	{
AnnaBridge	172:65be27845400	3568	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	172:65be27845400	3569	}
AnnaBridge	172:65be27845400	3570
AnnaBridge	172:65be27845400	3571	/**
AnnaBridge	172:65be27845400	3572	* @brief Enable DMA Tx
AnnaBridge	172:65be27845400	3573	* @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	172:65be27845400	3574	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3575	* @retval None
AnnaBridge	172:65be27845400	3576	*/
AnnaBridge	172:65be27845400	3577	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3578	{
AnnaBridge	172:65be27845400	3579	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	172:65be27845400	3580	}
AnnaBridge	172:65be27845400	3581
AnnaBridge	172:65be27845400	3582	/**
AnnaBridge	172:65be27845400	3583	* @brief Disable DMA Tx
AnnaBridge	172:65be27845400	3584	* @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	172:65be27845400	3585	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3586	* @retval None
AnnaBridge	172:65be27845400	3587	*/
AnnaBridge	172:65be27845400	3588	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3589	{
AnnaBridge	172:65be27845400	3590	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	172:65be27845400	3591	}
AnnaBridge	172:65be27845400	3592
AnnaBridge	172:65be27845400	3593	/**
AnnaBridge	172:65be27845400	3594	* @brief Check if DMA Tx is enabled
AnnaBridge	172:65be27845400	3595	* @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	172:65be27845400	3596	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3597	* @retval State of bit (1 or 0)
AnnaBridge	172:65be27845400	3598	*/
AnnaBridge	172:65be27845400	3599	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3600	{
AnnaBridge	172:65be27845400	3601	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	172:65be27845400	3602	}
AnnaBridge	172:65be27845400	3603
AnnaBridge	172:65be27845400	3604	/**
AnnaBridge	172:65be27845400	3605	* @}
AnnaBridge	172:65be27845400	3606	*/
AnnaBridge	172:65be27845400	3607
AnnaBridge	172:65be27845400	3608	/** @defgroup I2S_LL_EF_DATA_Management DATA_Management
AnnaBridge	172:65be27845400	3609	* @{
AnnaBridge	172:65be27845400	3610	*/
AnnaBridge	172:65be27845400	3611
AnnaBridge	172:65be27845400	3612	/**
AnnaBridge	172:65be27845400	3613	* @brief Read Data Register
AnnaBridge	172:65be27845400	3614	* @rmtoll RXDR . LL_I2S_ReceiveData16
AnnaBridge	172:65be27845400	3615	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3616	* @retval 0..0xFFFF
AnnaBridge	172:65be27845400	3617	*/
AnnaBridge	172:65be27845400	3618	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3619	{
AnnaBridge	172:65be27845400	3620	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	172:65be27845400	3621	}
AnnaBridge	172:65be27845400	3622
AnnaBridge	172:65be27845400	3623	/**
AnnaBridge	172:65be27845400	3624	* @brief Read Data Register
AnnaBridge	172:65be27845400	3625	* @rmtoll RXDR . LL_I2S_ReceiveData32
AnnaBridge	172:65be27845400	3626	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3627	* @retval 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	3628	*/
AnnaBridge	172:65be27845400	3629	__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
AnnaBridge	172:65be27845400	3630	{
AnnaBridge	172:65be27845400	3631	return LL_SPI_ReceiveData32(SPIx);
AnnaBridge	172:65be27845400	3632	}
AnnaBridge	172:65be27845400	3633
AnnaBridge	172:65be27845400	3634	/**
AnnaBridge	172:65be27845400	3635	* @brief Write Data Register
AnnaBridge	172:65be27845400	3636	* @rmtoll TXDR . LL_I2S_TransmitData16
AnnaBridge	172:65be27845400	3637	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3638	* @param TxData 0..0xFFFF
AnnaBridge	172:65be27845400	3639	* @retval None
AnnaBridge	172:65be27845400	3640	*/
AnnaBridge	172:65be27845400	3641	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	172:65be27845400	3642	{
AnnaBridge	172:65be27845400	3643	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	172:65be27845400	3644	}
AnnaBridge	172:65be27845400	3645
AnnaBridge	172:65be27845400	3646	/**
AnnaBridge	172:65be27845400	3647	* @brief Write Data Register
AnnaBridge	172:65be27845400	3648	* @rmtoll TXDR . LL_I2S_TransmitData32
AnnaBridge	172:65be27845400	3649	* @param SPIx SPI Instance
AnnaBridge	172:65be27845400	3650	* @param TxData 0..0xFFFFFFFF
AnnaBridge	172:65be27845400	3651	* @retval None
AnnaBridge	172:65be27845400	3652	*/
AnnaBridge	172:65be27845400	3653	__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
AnnaBridge	172:65be27845400	3654	{
AnnaBridge	172:65be27845400	3655	LL_SPI_TransmitData32(SPIx, TxData);
AnnaBridge	172:65be27845400	3656	}
AnnaBridge	172:65be27845400	3657
AnnaBridge	172:65be27845400	3658	/**
AnnaBridge	172:65be27845400	3659	* @}
AnnaBridge	172:65be27845400	3660	*/
AnnaBridge	172:65be27845400	3661
AnnaBridge	172:65be27845400	3662
AnnaBridge	172:65be27845400	3663	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	3664	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	172:65be27845400	3665	* @{
AnnaBridge	172:65be27845400	3666	*/
AnnaBridge	172:65be27845400	3667
AnnaBridge	172:65be27845400	3668	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	172:65be27845400	3669	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	172:65be27845400	3670	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	172:65be27845400	3671	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	172:65be27845400	3672
AnnaBridge	172:65be27845400	3673	/**
AnnaBridge	172:65be27845400	3674	* @}
AnnaBridge	172:65be27845400	3675	*/
AnnaBridge	172:65be27845400	3676	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	3677
AnnaBridge	172:65be27845400	3678	/**
AnnaBridge	172:65be27845400	3679	* @}
AnnaBridge	172:65be27845400	3680	*/
AnnaBridge	172:65be27845400	3681
AnnaBridge	172:65be27845400	3682	/**
AnnaBridge	172:65be27845400	3683	* @}
AnnaBridge	172:65be27845400	3684	*/
AnnaBridge	172:65be27845400	3685
AnnaBridge	172:65be27845400	3686	/**
AnnaBridge	172:65be27845400	3687	* @}
AnnaBridge	172:65be27845400	3688	*/
AnnaBridge	172:65be27845400	3689	#endif /* defined(SPI1) \|\| defined(SPI2) \|\| defined(SPI3) \|\| defined(SPI4) \|\| defined(SPI5) \|\| defined(SPI6) */
AnnaBridge	172:65be27845400	3690
AnnaBridge	172:65be27845400	3691	/**
AnnaBridge	172:65be27845400	3692	* @}
AnnaBridge	172:65be27845400	3693	*/
AnnaBridge	172:65be27845400	3694
AnnaBridge	172:65be27845400	3695	/**
AnnaBridge	172:65be27845400	3696	* @}
AnnaBridge	172:65be27845400	3697	*/
AnnaBridge	172:65be27845400	3698
AnnaBridge	172:65be27845400	3699	/**
AnnaBridge	172:65be27845400	3700	* @}
AnnaBridge	172:65be27845400	3701	*/
AnnaBridge	172:65be27845400	3702	#ifdef __cplusplus
AnnaBridge	172:65be27845400	3703	}
AnnaBridge	172:65be27845400	3704	#endif
AnnaBridge	172:65be27845400	3705
AnnaBridge	172:65be27845400	3706	#endif /* STM32H7xx_LL_SPI_H */
AnnaBridge	172:65be27845400	3707
AnnaBridge	172:65be27845400	3708	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/