mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_STD/stm32h7xx_hal_tim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32h7xx_hal_tim.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of TIM HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
AnnaBridge 172:65be27845400 10 * All rights reserved.</center></h2>
AnnaBridge 172:65be27845400 11 *
AnnaBridge 172:65be27845400 12 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 172:65be27845400 13 * the "License"; You may not use this file except in compliance with the
AnnaBridge 172:65be27845400 14 * License. You may obtain a copy of the License at:
AnnaBridge 172:65be27845400 15 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 172:65be27845400 16 *
AnnaBridge 172:65be27845400 17 ******************************************************************************
AnnaBridge 172:65be27845400 18 */
AnnaBridge 172:65be27845400 19
AnnaBridge 172:65be27845400 20 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 21 #ifndef STM32H7xx_HAL_TIM_H
AnnaBridge 172:65be27845400 22 #define STM32H7xx_HAL_TIM_H
AnnaBridge 172:65be27845400 23
AnnaBridge 172:65be27845400 24 #ifdef __cplusplus
AnnaBridge 172:65be27845400 25 extern "C" {
AnnaBridge 172:65be27845400 26 #endif
AnnaBridge 172:65be27845400 27
AnnaBridge 172:65be27845400 28 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 29 #include "stm32h7xx_hal_def.h"
AnnaBridge 172:65be27845400 30
AnnaBridge 172:65be27845400 31 /** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge 172:65be27845400 32 * @{
AnnaBridge 172:65be27845400 33 */
AnnaBridge 172:65be27845400 34
AnnaBridge 172:65be27845400 35 /** @addtogroup TIM
AnnaBridge 172:65be27845400 36 * @{
AnnaBridge 172:65be27845400 37 */
AnnaBridge 172:65be27845400 38
AnnaBridge 172:65be27845400 39 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 40 /** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge 172:65be27845400 41 * @{
AnnaBridge 172:65be27845400 42 */
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 /**
AnnaBridge 172:65be27845400 45 * @brief TIM Time base Configuration Structure definition
AnnaBridge 172:65be27845400 46 */
AnnaBridge 172:65be27845400 47 typedef struct
AnnaBridge 172:65be27845400 48 {
AnnaBridge 172:65be27845400 49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge 172:65be27845400 50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 172:65be27845400 51
AnnaBridge 172:65be27845400 52 uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge 172:65be27845400 53 This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge 172:65be27845400 54
AnnaBridge 172:65be27845400 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge 172:65be27845400 56 Auto-Reload Register at the next update event.
AnnaBridge 172:65be27845400 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge 172:65be27845400 58
AnnaBridge 172:65be27845400 59 uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge 172:65be27845400 60 This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge 172:65be27845400 61
AnnaBridge 172:65be27845400 62 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge 172:65be27845400 63 reaches zero, an update event is generated and counting restarts
AnnaBridge 172:65be27845400 64 from the RCR value (N).
AnnaBridge 172:65be27845400 65 This means in PWM mode that (N+1) corresponds to:
AnnaBridge 172:65be27845400 66 - the number of PWM periods in edge-aligned mode
AnnaBridge 172:65be27845400 67 - the number of half PWM period in center-aligned mode
AnnaBridge 172:65be27845400 68 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge 172:65be27845400 69 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge 172:65be27845400 70
AnnaBridge 172:65be27845400 71 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
AnnaBridge 172:65be27845400 72 This parameter can be a value of @ref TIM_AutoReloadPreload */
AnnaBridge 172:65be27845400 73 } TIM_Base_InitTypeDef;
AnnaBridge 172:65be27845400 74
AnnaBridge 172:65be27845400 75 /**
AnnaBridge 172:65be27845400 76 * @brief TIM Output Compare Configuration Structure definition
AnnaBridge 172:65be27845400 77 */
AnnaBridge 172:65be27845400 78 typedef struct
AnnaBridge 172:65be27845400 79 {
AnnaBridge 172:65be27845400 80 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 172:65be27845400 81 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 172:65be27845400 82
AnnaBridge 172:65be27845400 83 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 172:65be27845400 84 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 172:65be27845400 85
AnnaBridge 172:65be27845400 86 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 172:65be27845400 87 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 172:65be27845400 88
AnnaBridge 172:65be27845400 89 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 172:65be27845400 90 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 172:65be27845400 91 @note This parameter is valid only for timer instances supporting break feature. */
AnnaBridge 172:65be27845400 92
AnnaBridge 172:65be27845400 93 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge 172:65be27845400 94 This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge 172:65be27845400 95 @note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge 172:65be27845400 96
AnnaBridge 172:65be27845400 97
AnnaBridge 172:65be27845400 98 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 172:65be27845400 99 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 172:65be27845400 100 @note This parameter is valid only for timer instances supporting break feature. */
AnnaBridge 172:65be27845400 101
AnnaBridge 172:65be27845400 102 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 172:65be27845400 103 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 172:65be27845400 104 @note This parameter is valid only for timer instances supporting break feature. */
AnnaBridge 172:65be27845400 105 } TIM_OC_InitTypeDef;
AnnaBridge 172:65be27845400 106
AnnaBridge 172:65be27845400 107 /**
AnnaBridge 172:65be27845400 108 * @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge 172:65be27845400 109 */
AnnaBridge 172:65be27845400 110 typedef struct
AnnaBridge 172:65be27845400 111 {
AnnaBridge 172:65be27845400 112 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 172:65be27845400 113 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 172:65be27845400 114
AnnaBridge 172:65be27845400 115 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 172:65be27845400 116 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 172:65be27845400 117
AnnaBridge 172:65be27845400 118 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 172:65be27845400 119 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 172:65be27845400 120
AnnaBridge 172:65be27845400 121 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 172:65be27845400 122 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 172:65be27845400 123 @note This parameter is valid only for timer instances supporting break feature. */
AnnaBridge 172:65be27845400 124
AnnaBridge 172:65be27845400 125 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 172:65be27845400 126 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 172:65be27845400 127 @note This parameter is valid only for timer instances supporting break feature. */
AnnaBridge 172:65be27845400 128
AnnaBridge 172:65be27845400 129 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 172:65be27845400 130 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 172:65be27845400 131 @note This parameter is valid only for timer instances supporting break feature. */
AnnaBridge 172:65be27845400 132
AnnaBridge 172:65be27845400 133 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 172:65be27845400 134 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 172:65be27845400 135
AnnaBridge 172:65be27845400 136 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 172:65be27845400 137 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 172:65be27845400 138
AnnaBridge 172:65be27845400 139 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 172:65be27845400 140 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 141 } TIM_OnePulse_InitTypeDef;
AnnaBridge 172:65be27845400 142
AnnaBridge 172:65be27845400 143 /**
AnnaBridge 172:65be27845400 144 * @brief TIM Input Capture Configuration Structure definition
AnnaBridge 172:65be27845400 145 */
AnnaBridge 172:65be27845400 146 typedef struct
AnnaBridge 172:65be27845400 147 {
AnnaBridge 172:65be27845400 148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 172:65be27845400 149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 172:65be27845400 150
AnnaBridge 172:65be27845400 151 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 172:65be27845400 152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 172:65be27845400 153
AnnaBridge 172:65be27845400 154 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 172:65be27845400 155 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 172:65be27845400 156
AnnaBridge 172:65be27845400 157 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 172:65be27845400 158 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 159 } TIM_IC_InitTypeDef;
AnnaBridge 172:65be27845400 160
AnnaBridge 172:65be27845400 161 /**
AnnaBridge 172:65be27845400 162 * @brief TIM Encoder Configuration Structure definition
AnnaBridge 172:65be27845400 163 */
AnnaBridge 172:65be27845400 164 typedef struct
AnnaBridge 172:65be27845400 165 {
AnnaBridge 172:65be27845400 166 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge 172:65be27845400 167 This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge 172:65be27845400 168
AnnaBridge 172:65be27845400 169 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 172:65be27845400 170 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 172:65be27845400 171
AnnaBridge 172:65be27845400 172 uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge 172:65be27845400 173 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 172:65be27845400 174
AnnaBridge 172:65be27845400 175 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 172:65be27845400 176 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 172:65be27845400 177
AnnaBridge 172:65be27845400 178 uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge 172:65be27845400 179 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 180
AnnaBridge 172:65be27845400 181 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 172:65be27845400 182 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 172:65be27845400 183
AnnaBridge 172:65be27845400 184 uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge 172:65be27845400 185 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 172:65be27845400 186
AnnaBridge 172:65be27845400 187 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 172:65be27845400 188 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 172:65be27845400 189
AnnaBridge 172:65be27845400 190 uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge 172:65be27845400 191 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 192 } TIM_Encoder_InitTypeDef;
AnnaBridge 172:65be27845400 193
AnnaBridge 172:65be27845400 194 /**
AnnaBridge 172:65be27845400 195 * @brief Clock Configuration Handle Structure definition
AnnaBridge 172:65be27845400 196 */
AnnaBridge 172:65be27845400 197 typedef struct
AnnaBridge 172:65be27845400 198 {
AnnaBridge 172:65be27845400 199 uint32_t ClockSource; /*!< TIM clock sources
AnnaBridge 172:65be27845400 200 This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge 172:65be27845400 201 uint32_t ClockPolarity; /*!< TIM clock polarity
AnnaBridge 172:65be27845400 202 This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge 172:65be27845400 203 uint32_t ClockPrescaler; /*!< TIM clock prescaler
AnnaBridge 172:65be27845400 204 This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge 172:65be27845400 205 uint32_t ClockFilter; /*!< TIM clock filter
AnnaBridge 172:65be27845400 206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 207 } TIM_ClockConfigTypeDef;
AnnaBridge 172:65be27845400 208
AnnaBridge 172:65be27845400 209 /**
AnnaBridge 172:65be27845400 210 * @brief TIM Clear Input Configuration Handle Structure definition
AnnaBridge 172:65be27845400 211 */
AnnaBridge 172:65be27845400 212 typedef struct
AnnaBridge 172:65be27845400 213 {
AnnaBridge 172:65be27845400 214 uint32_t ClearInputState; /*!< TIM clear Input state
AnnaBridge 172:65be27845400 215 This parameter can be ENABLE or DISABLE */
AnnaBridge 172:65be27845400 216 uint32_t ClearInputSource; /*!< TIM clear Input sources
AnnaBridge 172:65be27845400 217 This parameter can be a value of @ref TIM_ClearInput_Source */
AnnaBridge 172:65be27845400 218 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
AnnaBridge 172:65be27845400 219 This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge 172:65be27845400 220 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
AnnaBridge 172:65be27845400 221 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
AnnaBridge 172:65be27845400 222 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
AnnaBridge 172:65be27845400 223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 224 } TIM_ClearInputConfigTypeDef;
AnnaBridge 172:65be27845400 225
AnnaBridge 172:65be27845400 226 /**
AnnaBridge 172:65be27845400 227 * @brief TIM Master configuration Structure definition
AnnaBridge 172:65be27845400 228 * @note Advanced timers provide TRGO2 internal line which is redirected
AnnaBridge 172:65be27845400 229 * to the ADC
AnnaBridge 172:65be27845400 230 */
AnnaBridge 172:65be27845400 231 typedef struct
AnnaBridge 172:65be27845400 232 {
AnnaBridge 172:65be27845400 233 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
AnnaBridge 172:65be27845400 234 This parameter can be a value of @ref TIM_Master_Mode_Selection */
AnnaBridge 172:65be27845400 235 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
AnnaBridge 172:65be27845400 236 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
AnnaBridge 172:65be27845400 237 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
AnnaBridge 172:65be27845400 238 This parameter can be a value of @ref TIM_Master_Slave_Mode */
AnnaBridge 172:65be27845400 239 } TIM_MasterConfigTypeDef;
AnnaBridge 172:65be27845400 240
AnnaBridge 172:65be27845400 241 /**
AnnaBridge 172:65be27845400 242 * @brief TIM Slave configuration Structure definition
AnnaBridge 172:65be27845400 243 */
AnnaBridge 172:65be27845400 244 typedef struct
AnnaBridge 172:65be27845400 245 {
AnnaBridge 172:65be27845400 246 uint32_t SlaveMode; /*!< Slave mode selection
AnnaBridge 172:65be27845400 247 This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge 172:65be27845400 248 uint32_t InputTrigger; /*!< Input Trigger source
AnnaBridge 172:65be27845400 249 This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge 172:65be27845400 250 uint32_t TriggerPolarity; /*!< Input Trigger polarity
AnnaBridge 172:65be27845400 251 This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge 172:65be27845400 252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
AnnaBridge 172:65be27845400 253 This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge 172:65be27845400 254 uint32_t TriggerFilter; /*!< Input trigger filter
AnnaBridge 172:65be27845400 255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 256
AnnaBridge 172:65be27845400 257 } TIM_SlaveConfigTypeDef;
AnnaBridge 172:65be27845400 258
AnnaBridge 172:65be27845400 259 /**
AnnaBridge 172:65be27845400 260 * @brief TIM Break input(s) and Dead time configuration Structure definition
AnnaBridge 172:65be27845400 261 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
AnnaBridge 172:65be27845400 262 * filter and polarity.
AnnaBridge 172:65be27845400 263 */
AnnaBridge 172:65be27845400 264 typedef struct
AnnaBridge 172:65be27845400 265 {
AnnaBridge 172:65be27845400 266 uint32_t OffStateRunMode; /*!< TIM off state in run mode
AnnaBridge 172:65be27845400 267 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
AnnaBridge 172:65be27845400 268 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
AnnaBridge 172:65be27845400 269 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
AnnaBridge 172:65be27845400 270 uint32_t LockLevel; /*!< TIM Lock level
AnnaBridge 172:65be27845400 271 This parameter can be a value of @ref TIM_Lock_level */
AnnaBridge 172:65be27845400 272 uint32_t DeadTime; /*!< TIM dead Time
AnnaBridge 172:65be27845400 273 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge 172:65be27845400 274 uint32_t BreakState; /*!< TIM Break State
AnnaBridge 172:65be27845400 275 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
AnnaBridge 172:65be27845400 276 uint32_t BreakPolarity; /*!< TIM Break input polarity
AnnaBridge 172:65be27845400 277 This parameter can be a value of @ref TIM_Break_Polarity */
AnnaBridge 172:65be27845400 278 uint32_t BreakFilter; /*!< Specifies the break input filter.
AnnaBridge 172:65be27845400 279 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 280 uint32_t Break2State; /*!< TIM Break2 State
AnnaBridge 172:65be27845400 281 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
AnnaBridge 172:65be27845400 282 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
AnnaBridge 172:65be27845400 283 This parameter can be a value of @ref TIM_Break2_Polarity */
AnnaBridge 172:65be27845400 284 uint32_t Break2Filter; /*!< TIM break2 input filter.
AnnaBridge 172:65be27845400 285 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 172:65be27845400 286 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
AnnaBridge 172:65be27845400 287 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
AnnaBridge 172:65be27845400 288 } TIM_BreakDeadTimeConfigTypeDef;
AnnaBridge 172:65be27845400 289
AnnaBridge 172:65be27845400 290 /**
AnnaBridge 172:65be27845400 291 * @brief HAL State structures definition
AnnaBridge 172:65be27845400 292 */
AnnaBridge 172:65be27845400 293 typedef enum
AnnaBridge 172:65be27845400 294 {
AnnaBridge 172:65be27845400 295 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
AnnaBridge 172:65be27845400 296 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 172:65be27845400 297 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
AnnaBridge 172:65be27845400 298 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
AnnaBridge 172:65be27845400 299 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
AnnaBridge 172:65be27845400 300 } HAL_TIM_StateTypeDef;
AnnaBridge 172:65be27845400 301
AnnaBridge 172:65be27845400 302 /**
AnnaBridge 172:65be27845400 303 * @brief HAL Active channel structures definition
AnnaBridge 172:65be27845400 304 */
AnnaBridge 172:65be27845400 305 typedef enum
AnnaBridge 172:65be27845400 306 {
AnnaBridge 172:65be27845400 307 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
AnnaBridge 172:65be27845400 308 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
AnnaBridge 172:65be27845400 309 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
AnnaBridge 172:65be27845400 310 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
AnnaBridge 172:65be27845400 311 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
AnnaBridge 172:65be27845400 312 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
AnnaBridge 172:65be27845400 313 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
AnnaBridge 172:65be27845400 314 } HAL_TIM_ActiveChannel;
AnnaBridge 172:65be27845400 315
AnnaBridge 172:65be27845400 316 /**
AnnaBridge 172:65be27845400 317 * @brief TIM Time Base Handle Structure definition
AnnaBridge 172:65be27845400 318 */
AnnaBridge 172:65be27845400 319 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 320 typedef struct __TIM_HandleTypeDef
AnnaBridge 172:65be27845400 321 #else
AnnaBridge 172:65be27845400 322 typedef struct
AnnaBridge 172:65be27845400 323 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 324 {
AnnaBridge 172:65be27845400 325 TIM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 172:65be27845400 326 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
AnnaBridge 172:65be27845400 327 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
AnnaBridge 172:65be27845400 328 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
AnnaBridge 172:65be27845400 329 This array is accessed by a @ref DMA_Handle_index */
AnnaBridge 172:65be27845400 330 HAL_LockTypeDef Lock; /*!< Locking object */
AnnaBridge 172:65be27845400 331 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
AnnaBridge 172:65be27845400 332
AnnaBridge 172:65be27845400 333 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 334 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
AnnaBridge 172:65be27845400 335 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
AnnaBridge 172:65be27845400 336 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
AnnaBridge 172:65be27845400 337 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
AnnaBridge 172:65be27845400 338 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
AnnaBridge 172:65be27845400 339 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
AnnaBridge 172:65be27845400 340 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
AnnaBridge 172:65be27845400 341 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
AnnaBridge 172:65be27845400 342 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
AnnaBridge 172:65be27845400 343 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
AnnaBridge 172:65be27845400 344 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
AnnaBridge 172:65be27845400 345 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
AnnaBridge 172:65be27845400 346 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
AnnaBridge 172:65be27845400 347 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
AnnaBridge 172:65be27845400 348 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
AnnaBridge 172:65be27845400 349 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
AnnaBridge 172:65be27845400 350 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
AnnaBridge 172:65be27845400 351 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
AnnaBridge 172:65be27845400 352 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
AnnaBridge 172:65be27845400 353 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
AnnaBridge 172:65be27845400 354 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
AnnaBridge 172:65be27845400 355 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
AnnaBridge 172:65be27845400 356 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
AnnaBridge 172:65be27845400 357 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
AnnaBridge 172:65be27845400 358 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
AnnaBridge 172:65be27845400 359 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
AnnaBridge 172:65be27845400 360 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
AnnaBridge 172:65be27845400 361 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
AnnaBridge 172:65be27845400 362 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 363 } TIM_HandleTypeDef;
AnnaBridge 172:65be27845400 364
AnnaBridge 172:65be27845400 365 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 366 /**
AnnaBridge 172:65be27845400 367 * @brief HAL TIM Callback ID enumeration definition
AnnaBridge 172:65be27845400 368 */
AnnaBridge 172:65be27845400 369 typedef enum
AnnaBridge 172:65be27845400 370 {
AnnaBridge 172:65be27845400 371 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
AnnaBridge 172:65be27845400 372 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
AnnaBridge 172:65be27845400 373 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
AnnaBridge 172:65be27845400 374 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
AnnaBridge 172:65be27845400 375 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
AnnaBridge 172:65be27845400 376 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
AnnaBridge 172:65be27845400 377 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
AnnaBridge 172:65be27845400 378 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
AnnaBridge 172:65be27845400 379 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
AnnaBridge 172:65be27845400 380 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
AnnaBridge 172:65be27845400 381 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
AnnaBridge 172:65be27845400 382 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
AnnaBridge 172:65be27845400 383 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
AnnaBridge 172:65be27845400 384 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
AnnaBridge 172:65be27845400 385 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
AnnaBridge 172:65be27845400 386 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
AnnaBridge 172:65be27845400 387 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
AnnaBridge 172:65be27845400 388 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
AnnaBridge 172:65be27845400 389
AnnaBridge 172:65be27845400 390 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
AnnaBridge 172:65be27845400 391 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
AnnaBridge 172:65be27845400 392 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
AnnaBridge 172:65be27845400 393 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
AnnaBridge 172:65be27845400 394 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
AnnaBridge 172:65be27845400 395 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
AnnaBridge 172:65be27845400 396 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
AnnaBridge 172:65be27845400 397 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
AnnaBridge 172:65be27845400 398 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
AnnaBridge 172:65be27845400 399 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
AnnaBridge 172:65be27845400 400 } HAL_TIM_CallbackIDTypeDef;
AnnaBridge 172:65be27845400 401
AnnaBridge 172:65be27845400 402 /**
AnnaBridge 172:65be27845400 403 * @brief HAL TIM Callback pointer definition
AnnaBridge 172:65be27845400 404 */
AnnaBridge 172:65be27845400 405 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
AnnaBridge 172:65be27845400 406
AnnaBridge 172:65be27845400 407 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 408
AnnaBridge 172:65be27845400 409 /**
AnnaBridge 172:65be27845400 410 * @}
AnnaBridge 172:65be27845400 411 */
AnnaBridge 172:65be27845400 412 /* End of exported types -----------------------------------------------------*/
AnnaBridge 172:65be27845400 413
AnnaBridge 172:65be27845400 414 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 415 /** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge 172:65be27845400 416 * @{
AnnaBridge 172:65be27845400 417 */
AnnaBridge 172:65be27845400 418
AnnaBridge 172:65be27845400 419 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
AnnaBridge 172:65be27845400 420 * @{
AnnaBridge 172:65be27845400 421 */
AnnaBridge 172:65be27845400 422 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
AnnaBridge 172:65be27845400 423 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
AnnaBridge 172:65be27845400 424 /**
AnnaBridge 172:65be27845400 425 * @}
AnnaBridge 172:65be27845400 426 */
AnnaBridge 172:65be27845400 427
AnnaBridge 172:65be27845400 428 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
AnnaBridge 172:65be27845400 429 * @{
AnnaBridge 172:65be27845400 430 */
AnnaBridge 172:65be27845400 431 #define TIM_DMABASE_CR1 0x00000000U
AnnaBridge 172:65be27845400 432 #define TIM_DMABASE_CR2 0x00000001U
AnnaBridge 172:65be27845400 433 #define TIM_DMABASE_SMCR 0x00000002U
AnnaBridge 172:65be27845400 434 #define TIM_DMABASE_DIER 0x00000003U
AnnaBridge 172:65be27845400 435 #define TIM_DMABASE_SR 0x00000004U
AnnaBridge 172:65be27845400 436 #define TIM_DMABASE_EGR 0x00000005U
AnnaBridge 172:65be27845400 437 #define TIM_DMABASE_CCMR1 0x00000006U
AnnaBridge 172:65be27845400 438 #define TIM_DMABASE_CCMR2 0x00000007U
AnnaBridge 172:65be27845400 439 #define TIM_DMABASE_CCER 0x00000008U
AnnaBridge 172:65be27845400 440 #define TIM_DMABASE_CNT 0x00000009U
AnnaBridge 172:65be27845400 441 #define TIM_DMABASE_PSC 0x0000000AU
AnnaBridge 172:65be27845400 442 #define TIM_DMABASE_ARR 0x0000000BU
AnnaBridge 172:65be27845400 443 #define TIM_DMABASE_RCR 0x0000000CU
AnnaBridge 172:65be27845400 444 #define TIM_DMABASE_CCR1 0x0000000DU
AnnaBridge 172:65be27845400 445 #define TIM_DMABASE_CCR2 0x0000000EU
AnnaBridge 172:65be27845400 446 #define TIM_DMABASE_CCR3 0x0000000FU
AnnaBridge 172:65be27845400 447 #define TIM_DMABASE_CCR4 0x00000010U
AnnaBridge 172:65be27845400 448 #define TIM_DMABASE_BDTR 0x00000011U
AnnaBridge 172:65be27845400 449 #define TIM_DMABASE_DCR 0x00000012U
AnnaBridge 172:65be27845400 450 #define TIM_DMABASE_DMAR 0x00000013U
AnnaBridge 172:65be27845400 451 #define TIM_DMABASE_OR 0x00000014U
AnnaBridge 172:65be27845400 452 #define TIM_DMABASE_CCMR3 0x00000015U
AnnaBridge 172:65be27845400 453 #define TIM_DMABASE_CCR5 0x00000016U
AnnaBridge 172:65be27845400 454 #define TIM_DMABASE_CCR6 0x00000017U
AnnaBridge 172:65be27845400 455 #if defined(TIM_BREAK_INPUT_SUPPORT)
AnnaBridge 172:65be27845400 456 #define TIM_DMABASE_AF1 0x00000018U
AnnaBridge 172:65be27845400 457 #define TIM_DMABASE_AF2 0x00000019U
AnnaBridge 172:65be27845400 458 #endif /* TIM_BREAK_INPUT_SUPPORT */
AnnaBridge 172:65be27845400 459 /**
AnnaBridge 172:65be27845400 460 * @}
AnnaBridge 172:65be27845400 461 */
AnnaBridge 172:65be27845400 462
AnnaBridge 172:65be27845400 463 /** @defgroup TIM_Event_Source TIM Event Source
AnnaBridge 172:65be27845400 464 * @{
AnnaBridge 172:65be27845400 465 */
AnnaBridge 172:65be27845400 466 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
AnnaBridge 172:65be27845400 467 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
AnnaBridge 172:65be27845400 468 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
AnnaBridge 172:65be27845400 469 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
AnnaBridge 172:65be27845400 470 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
AnnaBridge 172:65be27845400 471 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
AnnaBridge 172:65be27845400 472 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
AnnaBridge 172:65be27845400 473 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
AnnaBridge 172:65be27845400 474 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
AnnaBridge 172:65be27845400 475 /**
AnnaBridge 172:65be27845400 476 * @}
AnnaBridge 172:65be27845400 477 */
AnnaBridge 172:65be27845400 478
AnnaBridge 172:65be27845400 479 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
AnnaBridge 172:65be27845400 480 * @{
AnnaBridge 172:65be27845400 481 */
AnnaBridge 172:65be27845400 482 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
AnnaBridge 172:65be27845400 483 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
AnnaBridge 172:65be27845400 484 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
AnnaBridge 172:65be27845400 485 /**
AnnaBridge 172:65be27845400 486 * @}
AnnaBridge 172:65be27845400 487 */
AnnaBridge 172:65be27845400 488
AnnaBridge 172:65be27845400 489 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
AnnaBridge 172:65be27845400 490 * @{
AnnaBridge 172:65be27845400 491 */
AnnaBridge 172:65be27845400 492 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
AnnaBridge 172:65be27845400 493 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
AnnaBridge 172:65be27845400 494 /**
AnnaBridge 172:65be27845400 495 * @}
AnnaBridge 172:65be27845400 496 */
AnnaBridge 172:65be27845400 497
AnnaBridge 172:65be27845400 498 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
AnnaBridge 172:65be27845400 499 * @{
AnnaBridge 172:65be27845400 500 */
AnnaBridge 172:65be27845400 501 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
AnnaBridge 172:65be27845400 502 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
AnnaBridge 172:65be27845400 503 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
AnnaBridge 172:65be27845400 504 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
AnnaBridge 172:65be27845400 505 /**
AnnaBridge 172:65be27845400 506 * @}
AnnaBridge 172:65be27845400 507 */
AnnaBridge 172:65be27845400 508
AnnaBridge 172:65be27845400 509 /** @defgroup TIM_Counter_Mode TIM Counter Mode
AnnaBridge 172:65be27845400 510 * @{
AnnaBridge 172:65be27845400 511 */
AnnaBridge 172:65be27845400 512 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
AnnaBridge 172:65be27845400 513 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
AnnaBridge 172:65be27845400 514 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
AnnaBridge 172:65be27845400 515 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
AnnaBridge 172:65be27845400 516 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
AnnaBridge 172:65be27845400 517 /**
AnnaBridge 172:65be27845400 518 * @}
AnnaBridge 172:65be27845400 519 */
AnnaBridge 172:65be27845400 520
AnnaBridge 172:65be27845400 521 /** @defgroup TIM_ClockDivision TIM Clock Division
AnnaBridge 172:65be27845400 522 * @{
AnnaBridge 172:65be27845400 523 */
AnnaBridge 172:65be27845400 524 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
AnnaBridge 172:65be27845400 525 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
AnnaBridge 172:65be27845400 526 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
AnnaBridge 172:65be27845400 527 /**
AnnaBridge 172:65be27845400 528 * @}
AnnaBridge 172:65be27845400 529 */
AnnaBridge 172:65be27845400 530
AnnaBridge 172:65be27845400 531 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
AnnaBridge 172:65be27845400 532 * @{
AnnaBridge 172:65be27845400 533 */
AnnaBridge 172:65be27845400 534 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
AnnaBridge 172:65be27845400 535 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
AnnaBridge 172:65be27845400 536 /**
AnnaBridge 172:65be27845400 537 * @}
AnnaBridge 172:65be27845400 538 */
AnnaBridge 172:65be27845400 539
AnnaBridge 172:65be27845400 540 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
AnnaBridge 172:65be27845400 541 * @{
AnnaBridge 172:65be27845400 542 */
AnnaBridge 172:65be27845400 543 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
AnnaBridge 172:65be27845400 544 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
AnnaBridge 172:65be27845400 545
AnnaBridge 172:65be27845400 546 /**
AnnaBridge 172:65be27845400 547 * @}
AnnaBridge 172:65be27845400 548 */
AnnaBridge 172:65be27845400 549
AnnaBridge 172:65be27845400 550 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
AnnaBridge 172:65be27845400 551 * @{
AnnaBridge 172:65be27845400 552 */
AnnaBridge 172:65be27845400 553 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
AnnaBridge 172:65be27845400 554 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
AnnaBridge 172:65be27845400 555 /**
AnnaBridge 172:65be27845400 556 * @}
AnnaBridge 172:65be27845400 557 */
AnnaBridge 172:65be27845400 558
AnnaBridge 172:65be27845400 559 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
AnnaBridge 172:65be27845400 560 * @{
AnnaBridge 172:65be27845400 561 */
AnnaBridge 172:65be27845400 562 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
AnnaBridge 172:65be27845400 563 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
AnnaBridge 172:65be27845400 564 /**
AnnaBridge 172:65be27845400 565 * @}
AnnaBridge 172:65be27845400 566 */
AnnaBridge 172:65be27845400 567
AnnaBridge 172:65be27845400 568 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
AnnaBridge 172:65be27845400 569 * @{
AnnaBridge 172:65be27845400 570 */
AnnaBridge 172:65be27845400 571 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
AnnaBridge 172:65be27845400 572 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
AnnaBridge 172:65be27845400 573 /**
AnnaBridge 172:65be27845400 574 * @}
AnnaBridge 172:65be27845400 575 */
AnnaBridge 172:65be27845400 576
AnnaBridge 172:65be27845400 577 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
AnnaBridge 172:65be27845400 578 * @{
AnnaBridge 172:65be27845400 579 */
AnnaBridge 172:65be27845400 580 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
AnnaBridge 172:65be27845400 581 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
AnnaBridge 172:65be27845400 582 /**
AnnaBridge 172:65be27845400 583 * @}
AnnaBridge 172:65be27845400 584 */
AnnaBridge 172:65be27845400 585
AnnaBridge 172:65be27845400 586 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
AnnaBridge 172:65be27845400 587 * @{
AnnaBridge 172:65be27845400 588 */
AnnaBridge 172:65be27845400 589 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
AnnaBridge 172:65be27845400 590 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
AnnaBridge 172:65be27845400 591 /**
AnnaBridge 172:65be27845400 592 * @}
AnnaBridge 172:65be27845400 593 */
AnnaBridge 172:65be27845400 594
AnnaBridge 172:65be27845400 595 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
AnnaBridge 172:65be27845400 596 * @{
AnnaBridge 172:65be27845400 597 */
AnnaBridge 172:65be27845400 598 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
AnnaBridge 172:65be27845400 599 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
AnnaBridge 172:65be27845400 600 /**
AnnaBridge 172:65be27845400 601 * @}
AnnaBridge 172:65be27845400 602 */
AnnaBridge 172:65be27845400 603
AnnaBridge 172:65be27845400 604 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
AnnaBridge 172:65be27845400 605 * @{
AnnaBridge 172:65be27845400 606 */
AnnaBridge 172:65be27845400 607 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
AnnaBridge 172:65be27845400 608 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
AnnaBridge 172:65be27845400 609 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
AnnaBridge 172:65be27845400 610 /**
AnnaBridge 172:65be27845400 611 * @}
AnnaBridge 172:65be27845400 612 */
AnnaBridge 172:65be27845400 613
AnnaBridge 172:65be27845400 614 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
AnnaBridge 172:65be27845400 615 * @{
AnnaBridge 172:65be27845400 616 */
AnnaBridge 172:65be27845400 617 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 172:65be27845400 618 connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge 172:65be27845400 619 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 172:65be27845400 620 connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge 172:65be27845400 621 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
AnnaBridge 172:65be27845400 622 /**
AnnaBridge 172:65be27845400 623 * @}
AnnaBridge 172:65be27845400 624 */
AnnaBridge 172:65be27845400 625
AnnaBridge 172:65be27845400 626 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
AnnaBridge 172:65be27845400 627 * @{
AnnaBridge 172:65be27845400 628 */
AnnaBridge 172:65be27845400 629 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
AnnaBridge 172:65be27845400 630 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
AnnaBridge 172:65be27845400 631 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
AnnaBridge 172:65be27845400 632 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
AnnaBridge 172:65be27845400 633 /**
AnnaBridge 172:65be27845400 634 * @}
AnnaBridge 172:65be27845400 635 */
AnnaBridge 172:65be27845400 636
AnnaBridge 172:65be27845400 637 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
AnnaBridge 172:65be27845400 638 * @{
AnnaBridge 172:65be27845400 639 */
AnnaBridge 172:65be27845400 640 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
AnnaBridge 172:65be27845400 641 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
AnnaBridge 172:65be27845400 642 /**
AnnaBridge 172:65be27845400 643 * @}
AnnaBridge 172:65be27845400 644 */
AnnaBridge 172:65be27845400 645
AnnaBridge 172:65be27845400 646 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
AnnaBridge 172:65be27845400 647 * @{
AnnaBridge 172:65be27845400 648 */
AnnaBridge 172:65be27845400 649 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
AnnaBridge 172:65be27845400 650 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
AnnaBridge 172:65be27845400 651 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
AnnaBridge 172:65be27845400 652 /**
AnnaBridge 172:65be27845400 653 * @}
AnnaBridge 172:65be27845400 654 */
AnnaBridge 172:65be27845400 655
AnnaBridge 172:65be27845400 656 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
AnnaBridge 172:65be27845400 657 * @{
AnnaBridge 172:65be27845400 658 */
AnnaBridge 172:65be27845400 659 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
AnnaBridge 172:65be27845400 660 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
AnnaBridge 172:65be27845400 661 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
AnnaBridge 172:65be27845400 662 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
AnnaBridge 172:65be27845400 663 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
AnnaBridge 172:65be27845400 664 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
AnnaBridge 172:65be27845400 665 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
AnnaBridge 172:65be27845400 666 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
AnnaBridge 172:65be27845400 667 /**
AnnaBridge 172:65be27845400 668 * @}
AnnaBridge 172:65be27845400 669 */
AnnaBridge 172:65be27845400 670
AnnaBridge 172:65be27845400 671 /** @defgroup TIM_Commutation_Source TIM Commutation Source
AnnaBridge 172:65be27845400 672 * @{
AnnaBridge 172:65be27845400 673 */
AnnaBridge 172:65be27845400 674 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
AnnaBridge 172:65be27845400 675 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
AnnaBridge 172:65be27845400 676 /**
AnnaBridge 172:65be27845400 677 * @}
AnnaBridge 172:65be27845400 678 */
AnnaBridge 172:65be27845400 679
AnnaBridge 172:65be27845400 680 /** @defgroup TIM_DMA_sources TIM DMA Sources
AnnaBridge 172:65be27845400 681 * @{
AnnaBridge 172:65be27845400 682 */
AnnaBridge 172:65be27845400 683 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
AnnaBridge 172:65be27845400 684 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
AnnaBridge 172:65be27845400 685 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
AnnaBridge 172:65be27845400 686 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
AnnaBridge 172:65be27845400 687 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
AnnaBridge 172:65be27845400 688 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
AnnaBridge 172:65be27845400 689 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
AnnaBridge 172:65be27845400 690 /**
AnnaBridge 172:65be27845400 691 * @}
AnnaBridge 172:65be27845400 692 */
AnnaBridge 172:65be27845400 693
AnnaBridge 172:65be27845400 694 /** @defgroup TIM_Flag_definition TIM Flag Definition
AnnaBridge 172:65be27845400 695 * @{
AnnaBridge 172:65be27845400 696 */
AnnaBridge 172:65be27845400 697 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
AnnaBridge 172:65be27845400 698 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
AnnaBridge 172:65be27845400 699 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
AnnaBridge 172:65be27845400 700 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
AnnaBridge 172:65be27845400 701 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
AnnaBridge 172:65be27845400 702 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
AnnaBridge 172:65be27845400 703 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
AnnaBridge 172:65be27845400 704 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
AnnaBridge 172:65be27845400 705 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
AnnaBridge 172:65be27845400 706 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
AnnaBridge 172:65be27845400 707 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
AnnaBridge 172:65be27845400 708 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
AnnaBridge 172:65be27845400 709 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
AnnaBridge 172:65be27845400 710 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
AnnaBridge 172:65be27845400 711 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
AnnaBridge 172:65be27845400 712 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
AnnaBridge 172:65be27845400 713 /**
AnnaBridge 172:65be27845400 714 * @}
AnnaBridge 172:65be27845400 715 */
AnnaBridge 172:65be27845400 716
AnnaBridge 172:65be27845400 717 /** @defgroup TIM_Channel TIM Channel
AnnaBridge 172:65be27845400 718 * @{
AnnaBridge 172:65be27845400 719 */
AnnaBridge 172:65be27845400 720 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
AnnaBridge 172:65be27845400 721 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
AnnaBridge 172:65be27845400 722 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
AnnaBridge 172:65be27845400 723 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
AnnaBridge 172:65be27845400 724 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
AnnaBridge 172:65be27845400 725 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
AnnaBridge 172:65be27845400 726 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
AnnaBridge 172:65be27845400 727 /**
AnnaBridge 172:65be27845400 728 * @}
AnnaBridge 172:65be27845400 729 */
AnnaBridge 172:65be27845400 730
AnnaBridge 172:65be27845400 731 /** @defgroup TIM_Clock_Source TIM Clock Source
AnnaBridge 172:65be27845400 732 * @{
AnnaBridge 172:65be27845400 733 */
AnnaBridge 172:65be27845400 734 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
AnnaBridge 172:65be27845400 735 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
AnnaBridge 172:65be27845400 736 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
AnnaBridge 172:65be27845400 737 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
AnnaBridge 172:65be27845400 738 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
AnnaBridge 172:65be27845400 739 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
AnnaBridge 172:65be27845400 740 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
AnnaBridge 172:65be27845400 741 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
AnnaBridge 172:65be27845400 742 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
AnnaBridge 172:65be27845400 743 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
AnnaBridge 172:65be27845400 744 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
AnnaBridge 172:65be27845400 745 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
AnnaBridge 172:65be27845400 746 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
AnnaBridge 172:65be27845400 747 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
AnnaBridge 172:65be27845400 748 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
AnnaBridge 172:65be27845400 749 /**
AnnaBridge 172:65be27845400 750 * @}
AnnaBridge 172:65be27845400 751 */
AnnaBridge 172:65be27845400 752
AnnaBridge 172:65be27845400 753 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
AnnaBridge 172:65be27845400 754 * @{
AnnaBridge 172:65be27845400 755 */
AnnaBridge 172:65be27845400 756 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 172:65be27845400 757 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 172:65be27845400 758 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
AnnaBridge 172:65be27845400 759 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
AnnaBridge 172:65be27845400 760 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
AnnaBridge 172:65be27845400 761 /**
AnnaBridge 172:65be27845400 762 * @}
AnnaBridge 172:65be27845400 763 */
AnnaBridge 172:65be27845400 764
AnnaBridge 172:65be27845400 765 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
AnnaBridge 172:65be27845400 766 * @{
AnnaBridge 172:65be27845400 767 */
AnnaBridge 172:65be27845400 768 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 172:65be27845400 769 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
AnnaBridge 172:65be27845400 770 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
AnnaBridge 172:65be27845400 771 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
AnnaBridge 172:65be27845400 772 /**
AnnaBridge 172:65be27845400 773 * @}
AnnaBridge 172:65be27845400 774 */
AnnaBridge 172:65be27845400 775
AnnaBridge 172:65be27845400 776 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
AnnaBridge 172:65be27845400 777 * @{
AnnaBridge 172:65be27845400 778 */
AnnaBridge 172:65be27845400 779 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
AnnaBridge 172:65be27845400 780 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
AnnaBridge 172:65be27845400 781 /**
AnnaBridge 172:65be27845400 782 * @}
AnnaBridge 172:65be27845400 783 */
AnnaBridge 172:65be27845400 784
AnnaBridge 172:65be27845400 785 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
AnnaBridge 172:65be27845400 786 * @{
AnnaBridge 172:65be27845400 787 */
AnnaBridge 172:65be27845400 788 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 172:65be27845400 789 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
AnnaBridge 172:65be27845400 790 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
AnnaBridge 172:65be27845400 791 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
AnnaBridge 172:65be27845400 792 /**
AnnaBridge 172:65be27845400 793 * @}
AnnaBridge 172:65be27845400 794 */
AnnaBridge 172:65be27845400 795
AnnaBridge 172:65be27845400 796 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
AnnaBridge 172:65be27845400 797 * @{
AnnaBridge 172:65be27845400 798 */
AnnaBridge 172:65be27845400 799 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
AnnaBridge 172:65be27845400 800 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
AnnaBridge 172:65be27845400 801 /**
AnnaBridge 172:65be27845400 802 * @}
AnnaBridge 172:65be27845400 803 */
AnnaBridge 172:65be27845400 804
AnnaBridge 172:65be27845400 805 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
AnnaBridge 172:65be27845400 806 * @{
AnnaBridge 172:65be27845400 807 */
AnnaBridge 172:65be27845400 808 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
AnnaBridge 172:65be27845400 809 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
AnnaBridge 172:65be27845400 810 /**
AnnaBridge 172:65be27845400 811 * @}
AnnaBridge 172:65be27845400 812 */
AnnaBridge 172:65be27845400 813 /** @defgroup TIM_Lock_level TIM Lock level
AnnaBridge 172:65be27845400 814 * @{
AnnaBridge 172:65be27845400 815 */
AnnaBridge 172:65be27845400 816 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
AnnaBridge 172:65be27845400 817 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
AnnaBridge 172:65be27845400 818 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
AnnaBridge 172:65be27845400 819 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
AnnaBridge 172:65be27845400 820 /**
AnnaBridge 172:65be27845400 821 * @}
AnnaBridge 172:65be27845400 822 */
AnnaBridge 172:65be27845400 823
AnnaBridge 172:65be27845400 824 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
AnnaBridge 172:65be27845400 825 * @{
AnnaBridge 172:65be27845400 826 */
AnnaBridge 172:65be27845400 827 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
AnnaBridge 172:65be27845400 828 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
AnnaBridge 172:65be27845400 829 /**
AnnaBridge 172:65be27845400 830 * @}
AnnaBridge 172:65be27845400 831 */
AnnaBridge 172:65be27845400 832
AnnaBridge 172:65be27845400 833 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
AnnaBridge 172:65be27845400 834 * @{
AnnaBridge 172:65be27845400 835 */
AnnaBridge 172:65be27845400 836 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
AnnaBridge 172:65be27845400 837 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
AnnaBridge 172:65be27845400 838 /**
AnnaBridge 172:65be27845400 839 * @}
AnnaBridge 172:65be27845400 840 */
AnnaBridge 172:65be27845400 841
AnnaBridge 172:65be27845400 842 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
AnnaBridge 172:65be27845400 843 * @{
AnnaBridge 172:65be27845400 844 */
AnnaBridge 172:65be27845400 845 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
AnnaBridge 172:65be27845400 846 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
AnnaBridge 172:65be27845400 847 /**
AnnaBridge 172:65be27845400 848 * @}
AnnaBridge 172:65be27845400 849 */
AnnaBridge 172:65be27845400 850
AnnaBridge 172:65be27845400 851 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
AnnaBridge 172:65be27845400 852 * @{
AnnaBridge 172:65be27845400 853 */
AnnaBridge 172:65be27845400 854 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
AnnaBridge 172:65be27845400 855 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
AnnaBridge 172:65be27845400 856 /**
AnnaBridge 172:65be27845400 857 * @}
AnnaBridge 172:65be27845400 858 */
AnnaBridge 172:65be27845400 859
AnnaBridge 172:65be27845400 860 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
AnnaBridge 172:65be27845400 861 * @{
AnnaBridge 172:65be27845400 862 */
AnnaBridge 172:65be27845400 863 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
AnnaBridge 172:65be27845400 864 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
AnnaBridge 172:65be27845400 865 (if none of the break inputs BRK and BRK2 is active) */
AnnaBridge 172:65be27845400 866 /**
AnnaBridge 172:65be27845400 867 * @}
AnnaBridge 172:65be27845400 868 */
AnnaBridge 172:65be27845400 869
AnnaBridge 172:65be27845400 870 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
AnnaBridge 172:65be27845400 871 * @{
AnnaBridge 172:65be27845400 872 */
AnnaBridge 172:65be27845400 873 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
AnnaBridge 172:65be27845400 874 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
AnnaBridge 172:65be27845400 875 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
AnnaBridge 172:65be27845400 876 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
AnnaBridge 172:65be27845400 877 /**
AnnaBridge 172:65be27845400 878 * @}
AnnaBridge 172:65be27845400 879 */
AnnaBridge 172:65be27845400 880
AnnaBridge 172:65be27845400 881 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge 172:65be27845400 882 * @{
AnnaBridge 172:65be27845400 883 */
AnnaBridge 172:65be27845400 884 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
AnnaBridge 172:65be27845400 885 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
AnnaBridge 172:65be27845400 886 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
AnnaBridge 172:65be27845400 887 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
AnnaBridge 172:65be27845400 888 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
AnnaBridge 172:65be27845400 889 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
AnnaBridge 172:65be27845400 890 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
AnnaBridge 172:65be27845400 891 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
AnnaBridge 172:65be27845400 892 /**
AnnaBridge 172:65be27845400 893 * @}
AnnaBridge 172:65be27845400 894 */
AnnaBridge 172:65be27845400 895
AnnaBridge 172:65be27845400 896 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
AnnaBridge 172:65be27845400 897 * @{
AnnaBridge 172:65be27845400 898 */
AnnaBridge 172:65be27845400 899 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 900 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 901 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 902 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 903 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 904 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 905 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 906 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 907 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 908 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
AnnaBridge 172:65be27845400 909 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
AnnaBridge 172:65be27845400 910 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
AnnaBridge 172:65be27845400 911 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
AnnaBridge 172:65be27845400 912 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
AnnaBridge 172:65be27845400 913 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
AnnaBridge 172:65be27845400 914 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
AnnaBridge 172:65be27845400 915 /**
AnnaBridge 172:65be27845400 916 * @}
AnnaBridge 172:65be27845400 917 */
AnnaBridge 172:65be27845400 918
AnnaBridge 172:65be27845400 919 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
AnnaBridge 172:65be27845400 920 * @{
AnnaBridge 172:65be27845400 921 */
AnnaBridge 172:65be27845400 922 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
AnnaBridge 172:65be27845400 923 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
AnnaBridge 172:65be27845400 924 /**
AnnaBridge 172:65be27845400 925 * @}
AnnaBridge 172:65be27845400 926 */
AnnaBridge 172:65be27845400 927
AnnaBridge 172:65be27845400 928 /** @defgroup TIM_Slave_Mode TIM Slave mode
AnnaBridge 172:65be27845400 929 * @{
AnnaBridge 172:65be27845400 930 */
AnnaBridge 172:65be27845400 931 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
AnnaBridge 172:65be27845400 932 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
AnnaBridge 172:65be27845400 933 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
AnnaBridge 172:65be27845400 934 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
AnnaBridge 172:65be27845400 935 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
AnnaBridge 172:65be27845400 936 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
AnnaBridge 172:65be27845400 937 /**
AnnaBridge 172:65be27845400 938 * @}
AnnaBridge 172:65be27845400 939 */
AnnaBridge 172:65be27845400 940
AnnaBridge 172:65be27845400 941 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
AnnaBridge 172:65be27845400 942 * @{
AnnaBridge 172:65be27845400 943 */
AnnaBridge 172:65be27845400 944 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
AnnaBridge 172:65be27845400 945 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
AnnaBridge 172:65be27845400 946 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
AnnaBridge 172:65be27845400 947 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
AnnaBridge 172:65be27845400 948 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
AnnaBridge 172:65be27845400 949 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
AnnaBridge 172:65be27845400 950 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
AnnaBridge 172:65be27845400 951 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
AnnaBridge 172:65be27845400 952 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
AnnaBridge 172:65be27845400 953 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
AnnaBridge 172:65be27845400 954 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
AnnaBridge 172:65be27845400 955 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
AnnaBridge 172:65be27845400 956 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
AnnaBridge 172:65be27845400 957 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
AnnaBridge 172:65be27845400 958 /**
AnnaBridge 172:65be27845400 959 * @}
AnnaBridge 172:65be27845400 960 */
AnnaBridge 172:65be27845400 961
AnnaBridge 172:65be27845400 962 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
AnnaBridge 172:65be27845400 963 * @{
AnnaBridge 172:65be27845400 964 */
AnnaBridge 172:65be27845400 965 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
AnnaBridge 172:65be27845400 966 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
AnnaBridge 172:65be27845400 967 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
AnnaBridge 172:65be27845400 968 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
AnnaBridge 172:65be27845400 969 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
AnnaBridge 172:65be27845400 970 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
AnnaBridge 172:65be27845400 971 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
AnnaBridge 172:65be27845400 972 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
AnnaBridge 172:65be27845400 973 #define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */
AnnaBridge 172:65be27845400 974 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
AnnaBridge 172:65be27845400 975 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
AnnaBridge 172:65be27845400 976 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
AnnaBridge 172:65be27845400 977 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
AnnaBridge 172:65be27845400 978 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
AnnaBridge 172:65be27845400 979 /**
AnnaBridge 172:65be27845400 980 * @}
AnnaBridge 172:65be27845400 981 */
AnnaBridge 172:65be27845400 982
AnnaBridge 172:65be27845400 983 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
AnnaBridge 172:65be27845400 984 * @{
AnnaBridge 172:65be27845400 985 */
AnnaBridge 172:65be27845400 986 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 172:65be27845400 987 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 172:65be27845400 988 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 172:65be27845400 989 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 172:65be27845400 990 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 172:65be27845400 991 /**
AnnaBridge 172:65be27845400 992 * @}
AnnaBridge 172:65be27845400 993 */
AnnaBridge 172:65be27845400 994
AnnaBridge 172:65be27845400 995 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
AnnaBridge 172:65be27845400 996 * @{
AnnaBridge 172:65be27845400 997 */
AnnaBridge 172:65be27845400 998 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 172:65be27845400 999 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
AnnaBridge 172:65be27845400 1000 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
AnnaBridge 172:65be27845400 1001 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
AnnaBridge 172:65be27845400 1002 /**
AnnaBridge 172:65be27845400 1003 * @}
AnnaBridge 172:65be27845400 1004 */
AnnaBridge 172:65be27845400 1005
AnnaBridge 172:65be27845400 1006 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
AnnaBridge 172:65be27845400 1007 * @{
AnnaBridge 172:65be27845400 1008 */
AnnaBridge 172:65be27845400 1009 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
AnnaBridge 172:65be27845400 1010 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
AnnaBridge 172:65be27845400 1011 /**
AnnaBridge 172:65be27845400 1012 * @}
AnnaBridge 172:65be27845400 1013 */
AnnaBridge 172:65be27845400 1014
AnnaBridge 172:65be27845400 1015 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
AnnaBridge 172:65be27845400 1016 * @{
AnnaBridge 172:65be27845400 1017 */
AnnaBridge 172:65be27845400 1018 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1019 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1020 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1021 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1022 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1023 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1024 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1025 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1026 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1027 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1028 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1029 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1030 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1031 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1032 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1033 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1034 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1035 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
AnnaBridge 172:65be27845400 1036 /**
AnnaBridge 172:65be27845400 1037 * @}
AnnaBridge 172:65be27845400 1038 */
AnnaBridge 172:65be27845400 1039
AnnaBridge 172:65be27845400 1040 /** @defgroup DMA_Handle_index TIM DMA Handle Index
AnnaBridge 172:65be27845400 1041 * @{
AnnaBridge 172:65be27845400 1042 */
AnnaBridge 172:65be27845400 1043 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
AnnaBridge 172:65be27845400 1044 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
AnnaBridge 172:65be27845400 1045 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
AnnaBridge 172:65be27845400 1046 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
AnnaBridge 172:65be27845400 1047 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
AnnaBridge 172:65be27845400 1048 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
AnnaBridge 172:65be27845400 1049 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
AnnaBridge 172:65be27845400 1050 /**
AnnaBridge 172:65be27845400 1051 * @}
AnnaBridge 172:65be27845400 1052 */
AnnaBridge 172:65be27845400 1053
AnnaBridge 172:65be27845400 1054 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
AnnaBridge 172:65be27845400 1055 * @{
AnnaBridge 172:65be27845400 1056 */
AnnaBridge 172:65be27845400 1057 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
AnnaBridge 172:65be27845400 1058 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
AnnaBridge 172:65be27845400 1059 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
AnnaBridge 172:65be27845400 1060 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
AnnaBridge 172:65be27845400 1061 /**
AnnaBridge 172:65be27845400 1062 * @}
AnnaBridge 172:65be27845400 1063 */
AnnaBridge 172:65be27845400 1064
AnnaBridge 172:65be27845400 1065 /** @defgroup TIM_Break_System TIM Break System
AnnaBridge 172:65be27845400 1066 * @{
AnnaBridge 172:65be27845400 1067 */
AnnaBridge 172:65be27845400 1068 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
AnnaBridge 172:65be27845400 1069 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
AnnaBridge 172:65be27845400 1070 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
AnnaBridge 172:65be27845400 1071 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
AnnaBridge 172:65be27845400 1072 /**
AnnaBridge 172:65be27845400 1073 * @}
AnnaBridge 172:65be27845400 1074 */
AnnaBridge 172:65be27845400 1075
AnnaBridge 172:65be27845400 1076 /**
AnnaBridge 172:65be27845400 1077 * @}
AnnaBridge 172:65be27845400 1078 */
AnnaBridge 172:65be27845400 1079 /* End of exported constants -------------------------------------------------*/
AnnaBridge 172:65be27845400 1080
AnnaBridge 172:65be27845400 1081 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 172:65be27845400 1082 /** @defgroup TIM_Exported_Macros TIM Exported Macros
AnnaBridge 172:65be27845400 1083 * @{
AnnaBridge 172:65be27845400 1084 */
AnnaBridge 172:65be27845400 1085
AnnaBridge 172:65be27845400 1086 /** @brief Reset TIM handle state.
AnnaBridge 172:65be27845400 1087 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1088 * @retval None
AnnaBridge 172:65be27845400 1089 */
AnnaBridge 172:65be27845400 1090 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 1091 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
AnnaBridge 172:65be27845400 1092 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
AnnaBridge 172:65be27845400 1093 (__HANDLE__)->Base_MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 1094 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 1095 (__HANDLE__)->IC_MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 1096 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 1097 (__HANDLE__)->OC_MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 1098 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 1099 (__HANDLE__)->PWM_MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 1100 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 1101 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 1102 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 1103 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 1104 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 1105 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 1106 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 1107 } while(0)
AnnaBridge 172:65be27845400 1108 #else
AnnaBridge 172:65be27845400 1109 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge 172:65be27845400 1110 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 1111
AnnaBridge 172:65be27845400 1112 /**
AnnaBridge 172:65be27845400 1113 * @brief Enable the TIM peripheral.
AnnaBridge 172:65be27845400 1114 * @param __HANDLE__ TIM handle
AnnaBridge 172:65be27845400 1115 * @retval None
AnnaBridge 172:65be27845400 1116 */
AnnaBridge 172:65be27845400 1117 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
AnnaBridge 172:65be27845400 1118
AnnaBridge 172:65be27845400 1119 /**
AnnaBridge 172:65be27845400 1120 * @brief Enable the TIM main Output.
AnnaBridge 172:65be27845400 1121 * @param __HANDLE__ TIM handle
AnnaBridge 172:65be27845400 1122 * @retval None
AnnaBridge 172:65be27845400 1123 */
AnnaBridge 172:65be27845400 1124 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
AnnaBridge 172:65be27845400 1125
AnnaBridge 172:65be27845400 1126 /**
AnnaBridge 172:65be27845400 1127 * @brief Disable the TIM peripheral.
AnnaBridge 172:65be27845400 1128 * @param __HANDLE__ TIM handle
AnnaBridge 172:65be27845400 1129 * @retval None
AnnaBridge 172:65be27845400 1130 */
AnnaBridge 172:65be27845400 1131 #define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge 172:65be27845400 1132 do { \
AnnaBridge 172:65be27845400 1133 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
AnnaBridge 172:65be27845400 1134 { \
AnnaBridge 172:65be27845400 1135 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
AnnaBridge 172:65be27845400 1136 { \
AnnaBridge 172:65be27845400 1137 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge 172:65be27845400 1138 } \
AnnaBridge 172:65be27845400 1139 } \
AnnaBridge 172:65be27845400 1140 } while(0)
AnnaBridge 172:65be27845400 1141
AnnaBridge 172:65be27845400 1142 /**
AnnaBridge 172:65be27845400 1143 * @brief Disable the TIM main Output.
AnnaBridge 172:65be27845400 1144 * @param __HANDLE__ TIM handle
AnnaBridge 172:65be27845400 1145 * @retval None
AnnaBridge 172:65be27845400 1146 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
AnnaBridge 172:65be27845400 1147 */
AnnaBridge 172:65be27845400 1148 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
AnnaBridge 172:65be27845400 1149 do { \
AnnaBridge 172:65be27845400 1150 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
AnnaBridge 172:65be27845400 1151 { \
AnnaBridge 172:65be27845400 1152 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
AnnaBridge 172:65be27845400 1153 { \
AnnaBridge 172:65be27845400 1154 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
AnnaBridge 172:65be27845400 1155 } \
AnnaBridge 172:65be27845400 1156 } \
AnnaBridge 172:65be27845400 1157 } while(0)
AnnaBridge 172:65be27845400 1158
AnnaBridge 172:65be27845400 1159 /**
AnnaBridge 172:65be27845400 1160 * @brief Disable the TIM main Output.
AnnaBridge 172:65be27845400 1161 * @param __HANDLE__ TIM handle
AnnaBridge 172:65be27845400 1162 * @retval None
AnnaBridge 172:65be27845400 1163 * @note The Main Output Enable of a timer instance is disabled unconditionally
AnnaBridge 172:65be27845400 1164 */
AnnaBridge 172:65be27845400 1165 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
AnnaBridge 172:65be27845400 1166
AnnaBridge 172:65be27845400 1167 /** @brief Enable the specified TIM interrupt.
AnnaBridge 172:65be27845400 1168 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 172:65be27845400 1169 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
AnnaBridge 172:65be27845400 1170 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1171 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 172:65be27845400 1172 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 172:65be27845400 1173 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 172:65be27845400 1174 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 172:65be27845400 1175 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 172:65be27845400 1176 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 172:65be27845400 1177 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 172:65be27845400 1178 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 172:65be27845400 1179 * @retval None
AnnaBridge 172:65be27845400 1180 */
AnnaBridge 172:65be27845400 1181 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
AnnaBridge 172:65be27845400 1182
AnnaBridge 172:65be27845400 1183 /** @brief Disable the specified TIM interrupt.
AnnaBridge 172:65be27845400 1184 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 172:65be27845400 1185 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
AnnaBridge 172:65be27845400 1186 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1187 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 172:65be27845400 1188 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 172:65be27845400 1189 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 172:65be27845400 1190 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 172:65be27845400 1191 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 172:65be27845400 1192 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 172:65be27845400 1193 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 172:65be27845400 1194 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 172:65be27845400 1195 * @retval None
AnnaBridge 172:65be27845400 1196 */
AnnaBridge 172:65be27845400 1197 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge 172:65be27845400 1198
AnnaBridge 172:65be27845400 1199 /** @brief Enable the specified DMA request.
AnnaBridge 172:65be27845400 1200 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 172:65be27845400 1201 * @param __DMA__ specifies the TIM DMA request to enable.
AnnaBridge 172:65be27845400 1202 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1203 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 172:65be27845400 1204 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 172:65be27845400 1205 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 172:65be27845400 1206 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 172:65be27845400 1207 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 172:65be27845400 1208 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 172:65be27845400 1209 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 172:65be27845400 1210 * @retval None
AnnaBridge 172:65be27845400 1211 */
AnnaBridge 172:65be27845400 1212 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
AnnaBridge 172:65be27845400 1213
AnnaBridge 172:65be27845400 1214 /** @brief Disable the specified DMA request.
AnnaBridge 172:65be27845400 1215 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 172:65be27845400 1216 * @param __DMA__ specifies the TIM DMA request to disable.
AnnaBridge 172:65be27845400 1217 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1218 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 172:65be27845400 1219 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 172:65be27845400 1220 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 172:65be27845400 1221 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 172:65be27845400 1222 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 172:65be27845400 1223 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 172:65be27845400 1224 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 172:65be27845400 1225 * @retval None
AnnaBridge 172:65be27845400 1226 */
AnnaBridge 172:65be27845400 1227 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge 172:65be27845400 1228
AnnaBridge 172:65be27845400 1229 /** @brief Check whether the specified TIM interrupt flag is set or not.
AnnaBridge 172:65be27845400 1230 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 172:65be27845400 1231 * @param __FLAG__ specifies the TIM interrupt flag to check.
AnnaBridge 172:65be27845400 1232 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1233 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 172:65be27845400 1234 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 172:65be27845400 1235 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 172:65be27845400 1236 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 172:65be27845400 1237 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 172:65be27845400 1238 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge 172:65be27845400 1239 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge 172:65be27845400 1240 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 172:65be27845400 1241 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 172:65be27845400 1242 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 172:65be27845400 1243 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge 172:65be27845400 1244 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge 172:65be27845400 1245 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 172:65be27845400 1246 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 172:65be27845400 1247 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 172:65be27845400 1248 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 172:65be27845400 1249 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 172:65be27845400 1250 */
AnnaBridge 172:65be27845400 1251 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge 172:65be27845400 1252
AnnaBridge 172:65be27845400 1253 /** @brief Clear the specified TIM interrupt flag.
AnnaBridge 172:65be27845400 1254 * @param __HANDLE__ specifies the TIM Handle.
AnnaBridge 172:65be27845400 1255 * @param __FLAG__ specifies the TIM interrupt flag to clear.
AnnaBridge 172:65be27845400 1256 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1257 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 172:65be27845400 1258 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 172:65be27845400 1259 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 172:65be27845400 1260 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 172:65be27845400 1261 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 172:65be27845400 1262 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
AnnaBridge 172:65be27845400 1263 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
AnnaBridge 172:65be27845400 1264 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 172:65be27845400 1265 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 172:65be27845400 1266 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 172:65be27845400 1267 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
AnnaBridge 172:65be27845400 1268 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
AnnaBridge 172:65be27845400 1269 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 172:65be27845400 1270 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 172:65be27845400 1271 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 172:65be27845400 1272 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 172:65be27845400 1273 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 172:65be27845400 1274 */
AnnaBridge 172:65be27845400 1275 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge 172:65be27845400 1276
AnnaBridge 172:65be27845400 1277 /**
AnnaBridge 172:65be27845400 1278 * @brief Check whether the specified TIM interrupt source is enabled or not.
AnnaBridge 172:65be27845400 1279 * @param __HANDLE__ TIM handle
AnnaBridge 172:65be27845400 1280 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
AnnaBridge 172:65be27845400 1281 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1282 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 172:65be27845400 1283 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 172:65be27845400 1284 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 172:65be27845400 1285 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 172:65be27845400 1286 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 172:65be27845400 1287 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 172:65be27845400 1288 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 172:65be27845400 1289 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 172:65be27845400 1290 * @retval The state of TIM_IT (SET or RESET).
AnnaBridge 172:65be27845400 1291 */
AnnaBridge 172:65be27845400 1292 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 172:65be27845400 1293
AnnaBridge 172:65be27845400 1294 /** @brief Clear the TIM interrupt pending bits.
AnnaBridge 172:65be27845400 1295 * @param __HANDLE__ TIM handle
AnnaBridge 172:65be27845400 1296 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 172:65be27845400 1297 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1298 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 172:65be27845400 1299 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 172:65be27845400 1300 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 172:65be27845400 1301 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 172:65be27845400 1302 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 172:65be27845400 1303 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 172:65be27845400 1304 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 172:65be27845400 1305 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 172:65be27845400 1306 * @retval None
AnnaBridge 172:65be27845400 1307 */
AnnaBridge 172:65be27845400 1308 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge 172:65be27845400 1309
AnnaBridge 172:65be27845400 1310 /**
AnnaBridge 172:65be27845400 1311 * @brief Indicates whether or not the TIM Counter is used as downcounter.
AnnaBridge 172:65be27845400 1312 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1313 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
AnnaBridge 172:65be27845400 1314 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
AnnaBridge 172:65be27845400 1315 mode.
AnnaBridge 172:65be27845400 1316 */
AnnaBridge 172:65be27845400 1317 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge 172:65be27845400 1318
AnnaBridge 172:65be27845400 1319 /**
AnnaBridge 172:65be27845400 1320 * @brief Set the TIM Prescaler on runtime.
AnnaBridge 172:65be27845400 1321 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1322 * @param __PRESC__ specifies the Prescaler new value.
AnnaBridge 172:65be27845400 1323 * @retval None
AnnaBridge 172:65be27845400 1324 */
AnnaBridge 172:65be27845400 1325 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge 172:65be27845400 1326
AnnaBridge 172:65be27845400 1327 /**
AnnaBridge 172:65be27845400 1328 * @brief Set the TIM Counter Register value on runtime.
AnnaBridge 172:65be27845400 1329 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1330 * @param __COUNTER__ specifies the Counter register new value.
AnnaBridge 172:65be27845400 1331 * @retval None
AnnaBridge 172:65be27845400 1332 */
AnnaBridge 172:65be27845400 1333 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge 172:65be27845400 1334
AnnaBridge 172:65be27845400 1335 /**
AnnaBridge 172:65be27845400 1336 * @brief Get the TIM Counter Register value on runtime.
AnnaBridge 172:65be27845400 1337 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1338 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
AnnaBridge 172:65be27845400 1339 */
AnnaBridge 172:65be27845400 1340 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
AnnaBridge 172:65be27845400 1341 ((__HANDLE__)->Instance->CNT)
AnnaBridge 172:65be27845400 1342
AnnaBridge 172:65be27845400 1343 /**
AnnaBridge 172:65be27845400 1344 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
AnnaBridge 172:65be27845400 1345 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1346 * @param __AUTORELOAD__ specifies the Counter register new value.
AnnaBridge 172:65be27845400 1347 * @retval None
AnnaBridge 172:65be27845400 1348 */
AnnaBridge 172:65be27845400 1349 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge 172:65be27845400 1350 do{ \
AnnaBridge 172:65be27845400 1351 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge 172:65be27845400 1352 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge 172:65be27845400 1353 } while(0)
AnnaBridge 172:65be27845400 1354
AnnaBridge 172:65be27845400 1355 /**
AnnaBridge 172:65be27845400 1356 * @brief Get the TIM Autoreload Register value on runtime.
AnnaBridge 172:65be27845400 1357 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1358 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
AnnaBridge 172:65be27845400 1359 */
AnnaBridge 172:65be27845400 1360 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
AnnaBridge 172:65be27845400 1361 ((__HANDLE__)->Instance->ARR)
AnnaBridge 172:65be27845400 1362
AnnaBridge 172:65be27845400 1363 /**
AnnaBridge 172:65be27845400 1364 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
AnnaBridge 172:65be27845400 1365 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1366 * @param __CKD__ specifies the clock division value.
AnnaBridge 172:65be27845400 1367 * This parameter can be one of the following value:
AnnaBridge 172:65be27845400 1368 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge 172:65be27845400 1369 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge 172:65be27845400 1370 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge 172:65be27845400 1371 * @retval None
AnnaBridge 172:65be27845400 1372 */
AnnaBridge 172:65be27845400 1373 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge 172:65be27845400 1374 do{ \
AnnaBridge 172:65be27845400 1375 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
AnnaBridge 172:65be27845400 1376 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
AnnaBridge 172:65be27845400 1377 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge 172:65be27845400 1378 } while(0)
AnnaBridge 172:65be27845400 1379
AnnaBridge 172:65be27845400 1380 /**
AnnaBridge 172:65be27845400 1381 * @brief Get the TIM Clock Division value on runtime.
AnnaBridge 172:65be27845400 1382 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1383 * @retval The clock division can be one of the following values:
AnnaBridge 172:65be27845400 1384 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge 172:65be27845400 1385 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge 172:65be27845400 1386 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
AnnaBridge 172:65be27845400 1387 */
AnnaBridge 172:65be27845400 1388 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
AnnaBridge 172:65be27845400 1389 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge 172:65be27845400 1390
AnnaBridge 172:65be27845400 1391 /**
AnnaBridge 172:65be27845400 1392 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge 172:65be27845400 1393 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1394 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 172:65be27845400 1395 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1396 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 172:65be27845400 1397 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 172:65be27845400 1398 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 172:65be27845400 1399 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 172:65be27845400 1400 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
AnnaBridge 172:65be27845400 1401 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1402 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 172:65be27845400 1403 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 172:65be27845400 1404 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 172:65be27845400 1405 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 172:65be27845400 1406 * @retval None
AnnaBridge 172:65be27845400 1407 */
AnnaBridge 172:65be27845400 1408 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 172:65be27845400 1409 do{ \
AnnaBridge 172:65be27845400 1410 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 172:65be27845400 1411 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge 172:65be27845400 1412 } while(0)
AnnaBridge 172:65be27845400 1413
AnnaBridge 172:65be27845400 1414 /**
AnnaBridge 172:65be27845400 1415 * @brief Get the TIM Input Capture prescaler on runtime.
AnnaBridge 172:65be27845400 1416 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1417 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 172:65be27845400 1418 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1419 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge 172:65be27845400 1420 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge 172:65be27845400 1421 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge 172:65be27845400 1422 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge 172:65be27845400 1423 * @retval The input capture prescaler can be one of the following values:
AnnaBridge 172:65be27845400 1424 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 172:65be27845400 1425 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 172:65be27845400 1426 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 172:65be27845400 1427 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 172:65be27845400 1428 */
AnnaBridge 172:65be27845400 1429 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge 172:65be27845400 1430 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge 172:65be27845400 1431 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
AnnaBridge 172:65be27845400 1432 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge 172:65be27845400 1433 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
AnnaBridge 172:65be27845400 1434
AnnaBridge 172:65be27845400 1435 /**
AnnaBridge 172:65be27845400 1436 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
AnnaBridge 172:65be27845400 1437 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1438 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 172:65be27845400 1439 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1440 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 172:65be27845400 1441 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 172:65be27845400 1442 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 172:65be27845400 1443 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 172:65be27845400 1444 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge 172:65be27845400 1445 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge 172:65be27845400 1446 * @param __COMPARE__ specifies the Capture Compare register new value.
AnnaBridge 172:65be27845400 1447 * @retval None
AnnaBridge 172:65be27845400 1448 */
AnnaBridge 172:65be27845400 1449 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge 172:65be27845400 1450 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
AnnaBridge 172:65be27845400 1451 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
AnnaBridge 172:65be27845400 1452 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
AnnaBridge 172:65be27845400 1453 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
AnnaBridge 172:65be27845400 1454 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
AnnaBridge 172:65be27845400 1455 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
AnnaBridge 172:65be27845400 1456
AnnaBridge 172:65be27845400 1457 /**
AnnaBridge 172:65be27845400 1458 * @brief Get the TIM Capture Compare Register value on runtime.
AnnaBridge 172:65be27845400 1459 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1460 * @param __CHANNEL__ TIM Channel associated with the capture compare register
AnnaBridge 172:65be27845400 1461 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1462 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge 172:65be27845400 1463 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge 172:65be27845400 1464 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge 172:65be27845400 1465 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge 172:65be27845400 1466 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
AnnaBridge 172:65be27845400 1467 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
AnnaBridge 172:65be27845400 1468 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
AnnaBridge 172:65be27845400 1469 */
AnnaBridge 172:65be27845400 1470 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge 172:65be27845400 1471 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
AnnaBridge 172:65be27845400 1472 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
AnnaBridge 172:65be27845400 1473 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
AnnaBridge 172:65be27845400 1474 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
AnnaBridge 172:65be27845400 1475 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
AnnaBridge 172:65be27845400 1476 ((__HANDLE__)->Instance->CCR6))
AnnaBridge 172:65be27845400 1477
AnnaBridge 172:65be27845400 1478 /**
AnnaBridge 172:65be27845400 1479 * @brief Set the TIM Output compare preload.
AnnaBridge 172:65be27845400 1480 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1481 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 172:65be27845400 1482 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1483 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 172:65be27845400 1484 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 172:65be27845400 1485 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 172:65be27845400 1486 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 172:65be27845400 1487 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge 172:65be27845400 1488 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge 172:65be27845400 1489 * @retval None
AnnaBridge 172:65be27845400 1490 */
AnnaBridge 172:65be27845400 1491 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 172:65be27845400 1492 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
AnnaBridge 172:65be27845400 1493 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
AnnaBridge 172:65be27845400 1494 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
AnnaBridge 172:65be27845400 1495 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
AnnaBridge 172:65be27845400 1496 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
AnnaBridge 172:65be27845400 1497 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
AnnaBridge 172:65be27845400 1498
AnnaBridge 172:65be27845400 1499 /**
AnnaBridge 172:65be27845400 1500 * @brief Reset the TIM Output compare preload.
AnnaBridge 172:65be27845400 1501 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1502 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 172:65be27845400 1503 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1504 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 172:65be27845400 1505 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 172:65be27845400 1506 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 172:65be27845400 1507 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 172:65be27845400 1508 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
AnnaBridge 172:65be27845400 1509 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
AnnaBridge 172:65be27845400 1510 * @retval None
AnnaBridge 172:65be27845400 1511 */
AnnaBridge 172:65be27845400 1512 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 172:65be27845400 1513 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
AnnaBridge 172:65be27845400 1514 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
AnnaBridge 172:65be27845400 1515 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
AnnaBridge 172:65be27845400 1516 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
AnnaBridge 172:65be27845400 1517 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
AnnaBridge 172:65be27845400 1518 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
AnnaBridge 172:65be27845400 1519
AnnaBridge 172:65be27845400 1520 /**
AnnaBridge 172:65be27845400 1521 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
AnnaBridge 172:65be27845400 1522 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1523 * @note When the URS bit of the TIMx_CR1 register is set, only counter
AnnaBridge 172:65be27845400 1524 * overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge 172:65be27845400 1525 * enabled)
AnnaBridge 172:65be27845400 1526 * @retval None
AnnaBridge 172:65be27845400 1527 */
AnnaBridge 172:65be27845400 1528 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge 172:65be27845400 1529 ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
AnnaBridge 172:65be27845400 1530
AnnaBridge 172:65be27845400 1531 /**
AnnaBridge 172:65be27845400 1532 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
AnnaBridge 172:65be27845400 1533 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1534 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
AnnaBridge 172:65be27845400 1535 * following events generate an update interrupt or DMA request (if
AnnaBridge 172:65be27845400 1536 * enabled):
AnnaBridge 172:65be27845400 1537 * _ Counter overflow underflow
AnnaBridge 172:65be27845400 1538 * _ Setting the UG bit
AnnaBridge 172:65be27845400 1539 * _ Update generation through the slave mode controller
AnnaBridge 172:65be27845400 1540 * @retval None
AnnaBridge 172:65be27845400 1541 */
AnnaBridge 172:65be27845400 1542 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge 172:65be27845400 1543 ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
AnnaBridge 172:65be27845400 1544
AnnaBridge 172:65be27845400 1545 /**
AnnaBridge 172:65be27845400 1546 * @brief Set the TIM Capture x input polarity on runtime.
AnnaBridge 172:65be27845400 1547 * @param __HANDLE__ TIM handle.
AnnaBridge 172:65be27845400 1548 * @param __CHANNEL__ TIM Channels to be configured.
AnnaBridge 172:65be27845400 1549 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 1550 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 172:65be27845400 1551 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 172:65be27845400 1552 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 172:65be27845400 1553 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 172:65be27845400 1554 * @param __POLARITY__ Polarity for TIx source
AnnaBridge 172:65be27845400 1555 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge 172:65be27845400 1556 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge 172:65be27845400 1557 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge 172:65be27845400 1558 * @retval None
AnnaBridge 172:65be27845400 1559 */
AnnaBridge 172:65be27845400 1560 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 172:65be27845400 1561 do{ \
AnnaBridge 172:65be27845400 1562 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 172:65be27845400 1563 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge 172:65be27845400 1564 }while(0)
AnnaBridge 172:65be27845400 1565
AnnaBridge 172:65be27845400 1566 /**
AnnaBridge 172:65be27845400 1567 * @}
AnnaBridge 172:65be27845400 1568 */
AnnaBridge 172:65be27845400 1569 /* End of exported macros ----------------------------------------------------*/
AnnaBridge 172:65be27845400 1570
AnnaBridge 172:65be27845400 1571 /* Private constants ---------------------------------------------------------*/
AnnaBridge 172:65be27845400 1572 /** @defgroup TIM_Private_Constants TIM Private Constants
AnnaBridge 172:65be27845400 1573 * @{
AnnaBridge 172:65be27845400 1574 */
AnnaBridge 172:65be27845400 1575 /* The counter of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge 172:65be27845400 1576 channels have been disabled */
AnnaBridge 172:65be27845400 1577 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
AnnaBridge 172:65be27845400 1578 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
AnnaBridge 172:65be27845400 1579 /**
AnnaBridge 172:65be27845400 1580 * @}
AnnaBridge 172:65be27845400 1581 */
AnnaBridge 172:65be27845400 1582 /* End of private constants --------------------------------------------------*/
AnnaBridge 172:65be27845400 1583
AnnaBridge 172:65be27845400 1584 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 1585 /** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge 172:65be27845400 1586 * @{
AnnaBridge 172:65be27845400 1587 */
AnnaBridge 172:65be27845400 1588 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
AnnaBridge 172:65be27845400 1589 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
AnnaBridge 172:65be27845400 1590
AnnaBridge 172:65be27845400 1591 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
AnnaBridge 172:65be27845400 1592 ((__BASE__) == TIM_DMABASE_CR2) || \
AnnaBridge 172:65be27845400 1593 ((__BASE__) == TIM_DMABASE_SMCR) || \
AnnaBridge 172:65be27845400 1594 ((__BASE__) == TIM_DMABASE_DIER) || \
AnnaBridge 172:65be27845400 1595 ((__BASE__) == TIM_DMABASE_SR) || \
AnnaBridge 172:65be27845400 1596 ((__BASE__) == TIM_DMABASE_EGR) || \
AnnaBridge 172:65be27845400 1597 ((__BASE__) == TIM_DMABASE_CCMR1) || \
AnnaBridge 172:65be27845400 1598 ((__BASE__) == TIM_DMABASE_CCMR2) || \
AnnaBridge 172:65be27845400 1599 ((__BASE__) == TIM_DMABASE_CCER) || \
AnnaBridge 172:65be27845400 1600 ((__BASE__) == TIM_DMABASE_CNT) || \
AnnaBridge 172:65be27845400 1601 ((__BASE__) == TIM_DMABASE_PSC) || \
AnnaBridge 172:65be27845400 1602 ((__BASE__) == TIM_DMABASE_ARR) || \
AnnaBridge 172:65be27845400 1603 ((__BASE__) == TIM_DMABASE_RCR) || \
AnnaBridge 172:65be27845400 1604 ((__BASE__) == TIM_DMABASE_CCR1) || \
AnnaBridge 172:65be27845400 1605 ((__BASE__) == TIM_DMABASE_CCR2) || \
AnnaBridge 172:65be27845400 1606 ((__BASE__) == TIM_DMABASE_CCR3) || \
AnnaBridge 172:65be27845400 1607 ((__BASE__) == TIM_DMABASE_CCR4) || \
AnnaBridge 172:65be27845400 1608 ((__BASE__) == TIM_DMABASE_BDTR) || \
AnnaBridge 172:65be27845400 1609 ((__BASE__) == TIM_DMABASE_CCMR3) || \
AnnaBridge 172:65be27845400 1610 ((__BASE__) == TIM_DMABASE_CCR5) || \
AnnaBridge 172:65be27845400 1611 ((__BASE__) == TIM_DMABASE_CCR6) || \
AnnaBridge 172:65be27845400 1612 ((__BASE__) == TIM_DMABASE_OR) || \
AnnaBridge 172:65be27845400 1613 ((__BASE__) == TIM_DMABASE_AF1) || \
AnnaBridge 172:65be27845400 1614 ((__BASE__) == TIM_DMABASE_AF2))
AnnaBridge 172:65be27845400 1615
AnnaBridge 172:65be27845400 1616 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge 172:65be27845400 1617
AnnaBridge 172:65be27845400 1618 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
AnnaBridge 172:65be27845400 1619 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
AnnaBridge 172:65be27845400 1620 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
AnnaBridge 172:65be27845400 1621 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
AnnaBridge 172:65be27845400 1622 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge 172:65be27845400 1623
AnnaBridge 172:65be27845400 1624 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
AnnaBridge 172:65be27845400 1625 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
AnnaBridge 172:65be27845400 1626 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge 172:65be27845400 1627
AnnaBridge 172:65be27845400 1628 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
AnnaBridge 172:65be27845400 1629 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
AnnaBridge 172:65be27845400 1630
AnnaBridge 172:65be27845400 1631 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
AnnaBridge 172:65be27845400 1632 ((__STATE__) == TIM_OCFAST_ENABLE))
AnnaBridge 172:65be27845400 1633
AnnaBridge 172:65be27845400 1634 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
AnnaBridge 172:65be27845400 1635 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
AnnaBridge 172:65be27845400 1636
AnnaBridge 172:65be27845400 1637 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
AnnaBridge 172:65be27845400 1638 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
AnnaBridge 172:65be27845400 1639
AnnaBridge 172:65be27845400 1640 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
AnnaBridge 172:65be27845400 1641 ((__STATE__) == TIM_OCIDLESTATE_RESET))
AnnaBridge 172:65be27845400 1642
AnnaBridge 172:65be27845400 1643 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
AnnaBridge 172:65be27845400 1644 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
AnnaBridge 172:65be27845400 1645
AnnaBridge 172:65be27845400 1646 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
AnnaBridge 172:65be27845400 1647 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
AnnaBridge 172:65be27845400 1648 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge 172:65be27845400 1649
AnnaBridge 172:65be27845400 1650 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
AnnaBridge 172:65be27845400 1651 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
AnnaBridge 172:65be27845400 1652 ((__SELECTION__) == TIM_ICSELECTION_TRC))
AnnaBridge 172:65be27845400 1653
AnnaBridge 172:65be27845400 1654 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
AnnaBridge 172:65be27845400 1655 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
AnnaBridge 172:65be27845400 1656 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
AnnaBridge 172:65be27845400 1657 ((__PRESCALER__) == TIM_ICPSC_DIV8))
AnnaBridge 172:65be27845400 1658
AnnaBridge 172:65be27845400 1659 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
AnnaBridge 172:65be27845400 1660 ((__MODE__) == TIM_OPMODE_REPETITIVE))
AnnaBridge 172:65be27845400 1661
AnnaBridge 172:65be27845400 1662 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
AnnaBridge 172:65be27845400 1663 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
AnnaBridge 172:65be27845400 1664 ((__MODE__) == TIM_ENCODERMODE_TI12))
AnnaBridge 172:65be27845400 1665
AnnaBridge 172:65be27845400 1666 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge 172:65be27845400 1667
AnnaBridge 172:65be27845400 1668 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 1669 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 1670 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 1671 ((__CHANNEL__) == TIM_CHANNEL_4) || \
AnnaBridge 172:65be27845400 1672 ((__CHANNEL__) == TIM_CHANNEL_5) || \
AnnaBridge 172:65be27845400 1673 ((__CHANNEL__) == TIM_CHANNEL_6) || \
AnnaBridge 172:65be27845400 1674 ((__CHANNEL__) == TIM_CHANNEL_ALL))
AnnaBridge 172:65be27845400 1675
AnnaBridge 172:65be27845400 1676 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 1677 ((__CHANNEL__) == TIM_CHANNEL_2))
AnnaBridge 172:65be27845400 1678
AnnaBridge 172:65be27845400 1679 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 1680 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 1681 ((__CHANNEL__) == TIM_CHANNEL_3))
AnnaBridge 172:65be27845400 1682
AnnaBridge 172:65be27845400 1683 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
AnnaBridge 172:65be27845400 1684 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
AnnaBridge 172:65be27845400 1685 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
AnnaBridge 172:65be27845400 1686 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
AnnaBridge 172:65be27845400 1687 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
AnnaBridge 172:65be27845400 1688 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
AnnaBridge 172:65be27845400 1689 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
AnnaBridge 172:65be27845400 1690 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
AnnaBridge 172:65be27845400 1691 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
AnnaBridge 172:65be27845400 1692 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge 172:65be27845400 1693
AnnaBridge 172:65be27845400 1694 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
AnnaBridge 172:65be27845400 1695 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
AnnaBridge 172:65be27845400 1696 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
AnnaBridge 172:65be27845400 1697 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
AnnaBridge 172:65be27845400 1698 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge 172:65be27845400 1699
AnnaBridge 172:65be27845400 1700 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
AnnaBridge 172:65be27845400 1701 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
AnnaBridge 172:65be27845400 1702 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
AnnaBridge 172:65be27845400 1703 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge 172:65be27845400 1704
AnnaBridge 172:65be27845400 1705 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge 172:65be27845400 1706
AnnaBridge 172:65be27845400 1707 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
AnnaBridge 172:65be27845400 1708 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge 172:65be27845400 1709
AnnaBridge 172:65be27845400 1710 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
AnnaBridge 172:65be27845400 1711 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
AnnaBridge 172:65be27845400 1712 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
AnnaBridge 172:65be27845400 1713 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge 172:65be27845400 1714
AnnaBridge 172:65be27845400 1715 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge 172:65be27845400 1716
AnnaBridge 172:65be27845400 1717 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
AnnaBridge 172:65be27845400 1718 ((__STATE__) == TIM_OSSR_DISABLE))
AnnaBridge 172:65be27845400 1719
AnnaBridge 172:65be27845400 1720 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
AnnaBridge 172:65be27845400 1721 ((__STATE__) == TIM_OSSI_DISABLE))
AnnaBridge 172:65be27845400 1722
AnnaBridge 172:65be27845400 1723 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
AnnaBridge 172:65be27845400 1724 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
AnnaBridge 172:65be27845400 1725 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
AnnaBridge 172:65be27845400 1726 ((__LEVEL__) == TIM_LOCKLEVEL_3))
AnnaBridge 172:65be27845400 1727
AnnaBridge 172:65be27845400 1728 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
AnnaBridge 172:65be27845400 1729
AnnaBridge 172:65be27845400 1730
AnnaBridge 172:65be27845400 1731 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
AnnaBridge 172:65be27845400 1732 ((__STATE__) == TIM_BREAK_DISABLE))
AnnaBridge 172:65be27845400 1733
AnnaBridge 172:65be27845400 1734 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
AnnaBridge 172:65be27845400 1735 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
AnnaBridge 172:65be27845400 1736
AnnaBridge 172:65be27845400 1737 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
AnnaBridge 172:65be27845400 1738 ((__STATE__) == TIM_BREAK2_DISABLE))
AnnaBridge 172:65be27845400 1739
AnnaBridge 172:65be27845400 1740 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
AnnaBridge 172:65be27845400 1741 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
AnnaBridge 172:65be27845400 1742
AnnaBridge 172:65be27845400 1743 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
AnnaBridge 172:65be27845400 1744 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
AnnaBridge 172:65be27845400 1745
AnnaBridge 172:65be27845400 1746 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
AnnaBridge 172:65be27845400 1747
AnnaBridge 172:65be27845400 1748 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
AnnaBridge 172:65be27845400 1749 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
AnnaBridge 172:65be27845400 1750 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
AnnaBridge 172:65be27845400 1751 ((__SOURCE__) == TIM_TRGO_OC1) || \
AnnaBridge 172:65be27845400 1752 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
AnnaBridge 172:65be27845400 1753 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
AnnaBridge 172:65be27845400 1754 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
AnnaBridge 172:65be27845400 1755 ((__SOURCE__) == TIM_TRGO_OC4REF))
AnnaBridge 172:65be27845400 1756
AnnaBridge 172:65be27845400 1757 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
AnnaBridge 172:65be27845400 1758 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
AnnaBridge 172:65be27845400 1759 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
AnnaBridge 172:65be27845400 1760 ((__SOURCE__) == TIM_TRGO2_OC1) || \
AnnaBridge 172:65be27845400 1761 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
AnnaBridge 172:65be27845400 1762 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
AnnaBridge 172:65be27845400 1763 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
AnnaBridge 172:65be27845400 1764 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
AnnaBridge 172:65be27845400 1765 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
AnnaBridge 172:65be27845400 1766 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
AnnaBridge 172:65be27845400 1767 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
AnnaBridge 172:65be27845400 1768 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
AnnaBridge 172:65be27845400 1769 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
AnnaBridge 172:65be27845400 1770 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
AnnaBridge 172:65be27845400 1771 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
AnnaBridge 172:65be27845400 1772 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
AnnaBridge 172:65be27845400 1773 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
AnnaBridge 172:65be27845400 1774
AnnaBridge 172:65be27845400 1775 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
AnnaBridge 172:65be27845400 1776 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge 172:65be27845400 1777
AnnaBridge 172:65be27845400 1778 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
AnnaBridge 172:65be27845400 1779 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
AnnaBridge 172:65be27845400 1780 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
AnnaBridge 172:65be27845400 1781 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 172:65be27845400 1782 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
AnnaBridge 172:65be27845400 1783 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
AnnaBridge 172:65be27845400 1784
AnnaBridge 172:65be27845400 1785 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
AnnaBridge 172:65be27845400 1786 ((__MODE__) == TIM_OCMODE_PWM2) || \
AnnaBridge 172:65be27845400 1787 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
AnnaBridge 172:65be27845400 1788 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
AnnaBridge 172:65be27845400 1789 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
AnnaBridge 172:65be27845400 1790 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
AnnaBridge 172:65be27845400 1791
AnnaBridge 172:65be27845400 1792 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
AnnaBridge 172:65be27845400 1793 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
AnnaBridge 172:65be27845400 1794 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
AnnaBridge 172:65be27845400 1795 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
AnnaBridge 172:65be27845400 1796 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
AnnaBridge 172:65be27845400 1797 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
AnnaBridge 172:65be27845400 1798 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
AnnaBridge 172:65be27845400 1799 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
AnnaBridge 172:65be27845400 1800
AnnaBridge 172:65be27845400 1801 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
AnnaBridge 172:65be27845400 1802 ((__SELECTION__) == TIM_TS_ITR1) || \
AnnaBridge 172:65be27845400 1803 ((__SELECTION__) == TIM_TS_ITR2) || \
AnnaBridge 172:65be27845400 1804 ((__SELECTION__) == TIM_TS_ITR3) || \
AnnaBridge 172:65be27845400 1805 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
AnnaBridge 172:65be27845400 1806 ((__SELECTION__) == TIM_TS_TI1FP1) || \
AnnaBridge 172:65be27845400 1807 ((__SELECTION__) == TIM_TS_TI2FP2) || \
AnnaBridge 172:65be27845400 1808 ((__SELECTION__) == TIM_TS_ETRF) || \
AnnaBridge 172:65be27845400 1809 ((__SELECTION__) == TIM_TS_ITR4) || \
AnnaBridge 172:65be27845400 1810 ((__SELECTION__) == TIM_TS_ITR5) || \
AnnaBridge 172:65be27845400 1811 ((__SELECTION__) == TIM_TS_ITR6) || \
AnnaBridge 172:65be27845400 1812 ((__SELECTION__) == TIM_TS_ITR7) || \
AnnaBridge 172:65be27845400 1813 ((__SELECTION__) == TIM_TS_ITR8))
AnnaBridge 172:65be27845400 1814
AnnaBridge 172:65be27845400 1815 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
AnnaBridge 172:65be27845400 1816 ((__SELECTION__) == TIM_TS_ITR1) || \
AnnaBridge 172:65be27845400 1817 ((__SELECTION__) == TIM_TS_ITR2) || \
AnnaBridge 172:65be27845400 1818 ((__SELECTION__) == TIM_TS_ITR3) || \
AnnaBridge 172:65be27845400 1819 ((__SELECTION__) == TIM_TS_ITR4) || \
AnnaBridge 172:65be27845400 1820 ((__SELECTION__) == TIM_TS_ITR5) || \
AnnaBridge 172:65be27845400 1821 ((__SELECTION__) == TIM_TS_ITR6) || \
AnnaBridge 172:65be27845400 1822 ((__SELECTION__) == TIM_TS_ITR7) || \
AnnaBridge 172:65be27845400 1823 ((__SELECTION__) == TIM_TS_ITR8) || \
AnnaBridge 172:65be27845400 1824 ((__SELECTION__) == TIM_TS_NONE))
AnnaBridge 172:65be27845400 1825
AnnaBridge 172:65be27845400 1826 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
AnnaBridge 172:65be27845400 1827 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
AnnaBridge 172:65be27845400 1828 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
AnnaBridge 172:65be27845400 1829 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
AnnaBridge 172:65be27845400 1830 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge 172:65be27845400 1831
AnnaBridge 172:65be27845400 1832 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
AnnaBridge 172:65be27845400 1833 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
AnnaBridge 172:65be27845400 1834 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
AnnaBridge 172:65be27845400 1835 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge 172:65be27845400 1836
AnnaBridge 172:65be27845400 1837 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge 172:65be27845400 1838
AnnaBridge 172:65be27845400 1839 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
AnnaBridge 172:65be27845400 1840 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge 172:65be27845400 1841
AnnaBridge 172:65be27845400 1842 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
AnnaBridge 172:65be27845400 1843 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
AnnaBridge 172:65be27845400 1844 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
AnnaBridge 172:65be27845400 1845 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
AnnaBridge 172:65be27845400 1846 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
AnnaBridge 172:65be27845400 1847 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
AnnaBridge 172:65be27845400 1848 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
AnnaBridge 172:65be27845400 1849 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
AnnaBridge 172:65be27845400 1850 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
AnnaBridge 172:65be27845400 1851 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
AnnaBridge 172:65be27845400 1852 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
AnnaBridge 172:65be27845400 1853 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
AnnaBridge 172:65be27845400 1854 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
AnnaBridge 172:65be27845400 1855 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
AnnaBridge 172:65be27845400 1856 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
AnnaBridge 172:65be27845400 1857 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
AnnaBridge 172:65be27845400 1858 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
AnnaBridge 172:65be27845400 1859 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
AnnaBridge 172:65be27845400 1860
AnnaBridge 172:65be27845400 1861 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
AnnaBridge 172:65be27845400 1862
AnnaBridge 172:65be27845400 1863 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge 172:65be27845400 1864
AnnaBridge 172:65be27845400 1865 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
AnnaBridge 172:65be27845400 1866
AnnaBridge 172:65be27845400 1867 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
AnnaBridge 172:65be27845400 1868 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
AnnaBridge 172:65be27845400 1869 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
AnnaBridge 172:65be27845400 1870 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
AnnaBridge 172:65be27845400 1871
AnnaBridge 172:65be27845400 1872 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 172:65be27845400 1873 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
AnnaBridge 172:65be27845400 1874
AnnaBridge 172:65be27845400 1875 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 172:65be27845400 1876 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
AnnaBridge 172:65be27845400 1877 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
AnnaBridge 172:65be27845400 1878 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
AnnaBridge 172:65be27845400 1879 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
AnnaBridge 172:65be27845400 1880
AnnaBridge 172:65be27845400 1881 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge 172:65be27845400 1882 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
AnnaBridge 172:65be27845400 1883 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
AnnaBridge 172:65be27845400 1884 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
AnnaBridge 172:65be27845400 1885 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
AnnaBridge 172:65be27845400 1886
AnnaBridge 172:65be27845400 1887 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 172:65be27845400 1888 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
AnnaBridge 172:65be27845400 1889 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
AnnaBridge 172:65be27845400 1890 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
AnnaBridge 172:65be27845400 1891 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
AnnaBridge 172:65be27845400 1892
AnnaBridge 172:65be27845400 1893 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge 172:65be27845400 1894 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
AnnaBridge 172:65be27845400 1895 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
AnnaBridge 172:65be27845400 1896 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
AnnaBridge 172:65be27845400 1897 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
AnnaBridge 172:65be27845400 1898
AnnaBridge 172:65be27845400 1899 /**
AnnaBridge 172:65be27845400 1900 * @}
AnnaBridge 172:65be27845400 1901 */
AnnaBridge 172:65be27845400 1902 /* End of private macros -----------------------------------------------------*/
AnnaBridge 172:65be27845400 1903
AnnaBridge 172:65be27845400 1904 /* Include TIM HAL Extended module */
AnnaBridge 172:65be27845400 1905 #include "stm32h7xx_hal_tim_ex.h"
AnnaBridge 172:65be27845400 1906
AnnaBridge 172:65be27845400 1907 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 1908 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
AnnaBridge 172:65be27845400 1909 * @{
AnnaBridge 172:65be27845400 1910 */
AnnaBridge 172:65be27845400 1911
AnnaBridge 172:65be27845400 1912 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
AnnaBridge 172:65be27845400 1913 * @brief Time Base functions
AnnaBridge 172:65be27845400 1914 * @{
AnnaBridge 172:65be27845400 1915 */
AnnaBridge 172:65be27845400 1916 /* Time Base functions ********************************************************/
AnnaBridge 172:65be27845400 1917 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1918 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1919 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1920 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1921 /* Blocking mode: Polling */
AnnaBridge 172:65be27845400 1922 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1923 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1924 /* Non-Blocking mode: Interrupt */
AnnaBridge 172:65be27845400 1925 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1926 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1927 /* Non-Blocking mode: DMA */
AnnaBridge 172:65be27845400 1928 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
AnnaBridge 172:65be27845400 1929 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1930 /**
AnnaBridge 172:65be27845400 1931 * @}
AnnaBridge 172:65be27845400 1932 */
AnnaBridge 172:65be27845400 1933
AnnaBridge 172:65be27845400 1934 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
AnnaBridge 172:65be27845400 1935 * @brief TIM Output Compare functions
AnnaBridge 172:65be27845400 1936 * @{
AnnaBridge 172:65be27845400 1937 */
AnnaBridge 172:65be27845400 1938 /* Timer Output Compare functions *********************************************/
AnnaBridge 172:65be27845400 1939 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1940 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1941 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1942 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1943 /* Blocking mode: Polling */
AnnaBridge 172:65be27845400 1944 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1945 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1946 /* Non-Blocking mode: Interrupt */
AnnaBridge 172:65be27845400 1947 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1948 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1949 /* Non-Blocking mode: DMA */
AnnaBridge 172:65be27845400 1950 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 172:65be27845400 1951 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1952 /**
AnnaBridge 172:65be27845400 1953 * @}
AnnaBridge 172:65be27845400 1954 */
AnnaBridge 172:65be27845400 1955
AnnaBridge 172:65be27845400 1956 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
AnnaBridge 172:65be27845400 1957 * @brief TIM PWM functions
AnnaBridge 172:65be27845400 1958 * @{
AnnaBridge 172:65be27845400 1959 */
AnnaBridge 172:65be27845400 1960 /* Timer PWM functions ********************************************************/
AnnaBridge 172:65be27845400 1961 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1962 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1963 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1964 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1965 /* Blocking mode: Polling */
AnnaBridge 172:65be27845400 1966 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1967 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1968 /* Non-Blocking mode: Interrupt */
AnnaBridge 172:65be27845400 1969 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1970 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1971 /* Non-Blocking mode: DMA */
AnnaBridge 172:65be27845400 1972 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 172:65be27845400 1973 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1974 /**
AnnaBridge 172:65be27845400 1975 * @}
AnnaBridge 172:65be27845400 1976 */
AnnaBridge 172:65be27845400 1977
AnnaBridge 172:65be27845400 1978 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
AnnaBridge 172:65be27845400 1979 * @brief TIM Input Capture functions
AnnaBridge 172:65be27845400 1980 * @{
AnnaBridge 172:65be27845400 1981 */
AnnaBridge 172:65be27845400 1982 /* Timer Input Capture functions **********************************************/
AnnaBridge 172:65be27845400 1983 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1984 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1985 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1986 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 1987 /* Blocking mode: Polling */
AnnaBridge 172:65be27845400 1988 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1989 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1990 /* Non-Blocking mode: Interrupt */
AnnaBridge 172:65be27845400 1991 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1992 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1993 /* Non-Blocking mode: DMA */
AnnaBridge 172:65be27845400 1994 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 172:65be27845400 1995 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 1996 /**
AnnaBridge 172:65be27845400 1997 * @}
AnnaBridge 172:65be27845400 1998 */
AnnaBridge 172:65be27845400 1999
AnnaBridge 172:65be27845400 2000 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
AnnaBridge 172:65be27845400 2001 * @brief TIM One Pulse functions
AnnaBridge 172:65be27845400 2002 * @{
AnnaBridge 172:65be27845400 2003 */
AnnaBridge 172:65be27845400 2004 /* Timer One Pulse functions **************************************************/
AnnaBridge 172:65be27845400 2005 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge 172:65be27845400 2006 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2007 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2008 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2009 /* Blocking mode: Polling */
AnnaBridge 172:65be27845400 2010 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 172:65be27845400 2011 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 172:65be27845400 2012 /* Non-Blocking mode: Interrupt */
AnnaBridge 172:65be27845400 2013 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 172:65be27845400 2014 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 172:65be27845400 2015 /**
AnnaBridge 172:65be27845400 2016 * @}
AnnaBridge 172:65be27845400 2017 */
AnnaBridge 172:65be27845400 2018
AnnaBridge 172:65be27845400 2019 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
AnnaBridge 172:65be27845400 2020 * @brief TIM Encoder functions
AnnaBridge 172:65be27845400 2021 * @{
AnnaBridge 172:65be27845400 2022 */
AnnaBridge 172:65be27845400 2023 /* Timer Encoder functions ****************************************************/
AnnaBridge 172:65be27845400 2024 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
AnnaBridge 172:65be27845400 2025 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2026 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2027 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2028 /* Blocking mode: Polling */
AnnaBridge 172:65be27845400 2029 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 2030 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 2031 /* Non-Blocking mode: Interrupt */
AnnaBridge 172:65be27845400 2032 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 2033 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 2034 /* Non-Blocking mode: DMA */
AnnaBridge 172:65be27845400 2035 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge 172:65be27845400 2036 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 2037 /**
AnnaBridge 172:65be27845400 2038 * @}
AnnaBridge 172:65be27845400 2039 */
AnnaBridge 172:65be27845400 2040
AnnaBridge 172:65be27845400 2041 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
AnnaBridge 172:65be27845400 2042 * @brief IRQ handler management
AnnaBridge 172:65be27845400 2043 * @{
AnnaBridge 172:65be27845400 2044 */
AnnaBridge 172:65be27845400 2045 /* Interrupt Handler functions ***********************************************/
AnnaBridge 172:65be27845400 2046 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2047 /**
AnnaBridge 172:65be27845400 2048 * @}
AnnaBridge 172:65be27845400 2049 */
AnnaBridge 172:65be27845400 2050
AnnaBridge 172:65be27845400 2051 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
AnnaBridge 172:65be27845400 2052 * @brief Peripheral Control functions
AnnaBridge 172:65be27845400 2053 * @{
AnnaBridge 172:65be27845400 2054 */
AnnaBridge 172:65be27845400 2055 /* Control functions *********************************************************/
AnnaBridge 172:65be27845400 2056 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
AnnaBridge 172:65be27845400 2057 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
AnnaBridge 172:65be27845400 2058 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
AnnaBridge 172:65be27845400 2059 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge 172:65be27845400 2060 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
AnnaBridge 172:65be27845400 2061 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
AnnaBridge 172:65be27845400 2062 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge 172:65be27845400 2063 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
AnnaBridge 172:65be27845400 2064 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
AnnaBridge 172:65be27845400 2065 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 172:65be27845400 2066 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 172:65be27845400 2067 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 172:65be27845400 2068 uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
AnnaBridge 172:65be27845400 2069 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 172:65be27845400 2070 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 172:65be27845400 2071 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 172:65be27845400 2072 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 172:65be27845400 2073 uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
AnnaBridge 172:65be27845400 2074 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 172:65be27845400 2075 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge 172:65be27845400 2076 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 172:65be27845400 2077 /**
AnnaBridge 172:65be27845400 2078 * @}
AnnaBridge 172:65be27845400 2079 */
AnnaBridge 172:65be27845400 2080
AnnaBridge 172:65be27845400 2081 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
AnnaBridge 172:65be27845400 2082 * @brief TIM Callbacks functions
AnnaBridge 172:65be27845400 2083 * @{
AnnaBridge 172:65be27845400 2084 */
AnnaBridge 172:65be27845400 2085 /* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge 172:65be27845400 2086 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2087 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2088 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2089 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2090 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2091 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2092 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2093 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2094 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2095 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2096
AnnaBridge 172:65be27845400 2097 /* Callbacks Register/UnRegister functions ***********************************/
AnnaBridge 172:65be27845400 2098 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 2099 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
AnnaBridge 172:65be27845400 2100 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
AnnaBridge 172:65be27845400 2101 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 2102
AnnaBridge 172:65be27845400 2103 /**
AnnaBridge 172:65be27845400 2104 * @}
AnnaBridge 172:65be27845400 2105 */
AnnaBridge 172:65be27845400 2106
AnnaBridge 172:65be27845400 2107 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
AnnaBridge 172:65be27845400 2108 * @brief Peripheral State functions
AnnaBridge 172:65be27845400 2109 * @{
AnnaBridge 172:65be27845400 2110 */
AnnaBridge 172:65be27845400 2111 /* Peripheral State functions ************************************************/
AnnaBridge 172:65be27845400 2112 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2113 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2114 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2115 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2116 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2117 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2118 /**
AnnaBridge 172:65be27845400 2119 * @}
AnnaBridge 172:65be27845400 2120 */
AnnaBridge 172:65be27845400 2121
AnnaBridge 172:65be27845400 2122 /**
AnnaBridge 172:65be27845400 2123 * @}
AnnaBridge 172:65be27845400 2124 */
AnnaBridge 172:65be27845400 2125 /* End of exported functions -------------------------------------------------*/
AnnaBridge 172:65be27845400 2126
AnnaBridge 172:65be27845400 2127 /* Private functions----------------------------------------------------------*/
AnnaBridge 172:65be27845400 2128 /** @defgroup TIM_Private_Functions TIM Private Functions
AnnaBridge 172:65be27845400 2129 * @{
AnnaBridge 172:65be27845400 2130 */
AnnaBridge 172:65be27845400 2131 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
AnnaBridge 172:65be27845400 2132 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
AnnaBridge 172:65be27845400 2133 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
AnnaBridge 172:65be27845400 2134 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
AnnaBridge 172:65be27845400 2135 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
AnnaBridge 172:65be27845400 2136
AnnaBridge 172:65be27845400 2137 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 2138 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 2139 void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 2140 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 2141 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 2142 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
AnnaBridge 172:65be27845400 2143
AnnaBridge 172:65be27845400 2144 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 2145 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
AnnaBridge 172:65be27845400 2146 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 2147
AnnaBridge 172:65be27845400 2148 /**
AnnaBridge 172:65be27845400 2149 * @}
AnnaBridge 172:65be27845400 2150 */
AnnaBridge 172:65be27845400 2151 /* End of private functions --------------------------------------------------*/
AnnaBridge 172:65be27845400 2152
AnnaBridge 172:65be27845400 2153 /**
AnnaBridge 172:65be27845400 2154 * @}
AnnaBridge 172:65be27845400 2155 */
AnnaBridge 172:65be27845400 2156
AnnaBridge 172:65be27845400 2157 /**
AnnaBridge 172:65be27845400 2158 * @}
AnnaBridge 172:65be27845400 2159 */
AnnaBridge 172:65be27845400 2160
AnnaBridge 172:65be27845400 2161 #ifdef __cplusplus
AnnaBridge 172:65be27845400 2162 }
AnnaBridge 172:65be27845400 2163 #endif
AnnaBridge 172:65be27845400 2164
AnnaBridge 172:65be27845400 2165 #endif /* STM32H7xx_HAL_TIM_H */
AnnaBridge 172:65be27845400 2166
AnnaBridge 172:65be27845400 2167 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/