mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_ll_tim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_tim.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of TIM LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef __STM32H7xx_LL_TIM_H
AnnaBridge	172:65be27845400	22	#define __STM32H7xx_LL_TIM_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM6) \|\| defined (TIM7) \|\| defined (TIM8) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17)
AnnaBridge	172:65be27845400	36
AnnaBridge	172:65be27845400	37	/** @defgroup TIM_LL TIM
AnnaBridge	172:65be27845400	38	* @{
AnnaBridge	172:65be27845400	39	*/
AnnaBridge	172:65be27845400	40
AnnaBridge	172:65be27845400	41	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	42	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	172:65be27845400	44	* @{
AnnaBridge	172:65be27845400	45	*/
AnnaBridge	172:65be27845400	46	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	172:65be27845400	47	{
AnnaBridge	172:65be27845400	48	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	172:65be27845400	49	0x00U, /* 1: TIMx_CH1N */
AnnaBridge	172:65be27845400	50	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	172:65be27845400	51	0x00U, /* 3: TIMx_CH2N */
AnnaBridge	172:65be27845400	52	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	172:65be27845400	53	0x04U, /* 5: TIMx_CH3N */
AnnaBridge	172:65be27845400	54	0x04U, /* 6: TIMx_CH4 */
AnnaBridge	172:65be27845400	55	0x3CU, /* 7: TIMx_CH5 */
AnnaBridge	172:65be27845400	56	0x3CU /* 8: TIMx_CH6 */
AnnaBridge	172:65be27845400	57	};
AnnaBridge	172:65be27845400	58
AnnaBridge	172:65be27845400	59	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	172:65be27845400	60	{
AnnaBridge	172:65be27845400	61	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	172:65be27845400	62	0U, /* 1: - NA */
AnnaBridge	172:65be27845400	63	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	172:65be27845400	64	0U, /* 3: - NA */
AnnaBridge	172:65be27845400	65	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	172:65be27845400	66	0U, /* 5: - NA */
AnnaBridge	172:65be27845400	67	8U, /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	172:65be27845400	68	0U, /* 7: OC5M, OC5FE, OC5PE */
AnnaBridge	172:65be27845400	69	8U /* 8: OC6M, OC6FE, OC6PE */
AnnaBridge	172:65be27845400	70	};
AnnaBridge	172:65be27845400	71
AnnaBridge	172:65be27845400	72	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	172:65be27845400	73	{
AnnaBridge	172:65be27845400	74	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	172:65be27845400	75	0U, /* 1: - NA */
AnnaBridge	172:65be27845400	76	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	172:65be27845400	77	0U, /* 3: - NA */
AnnaBridge	172:65be27845400	78	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	172:65be27845400	79	0U, /* 5: - NA */
AnnaBridge	172:65be27845400	80	8U, /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	172:65be27845400	81	0U, /* 7: - NA */
AnnaBridge	172:65be27845400	82	0U /* 8: - NA */
AnnaBridge	172:65be27845400	83	};
AnnaBridge	172:65be27845400	84
AnnaBridge	172:65be27845400	85	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	172:65be27845400	86	{
AnnaBridge	172:65be27845400	87	0U, /* 0: CC1P */
AnnaBridge	172:65be27845400	88	2U, /* 1: CC1NP */
AnnaBridge	172:65be27845400	89	4U, /* 2: CC2P */
AnnaBridge	172:65be27845400	90	6U, /* 3: CC2NP */
AnnaBridge	172:65be27845400	91	8U, /* 4: CC3P */
AnnaBridge	172:65be27845400	92	10U, /* 5: CC3NP */
AnnaBridge	172:65be27845400	93	12U, /* 6: CC4P */
AnnaBridge	172:65be27845400	94	16U, /* 7: CC5P */
AnnaBridge	172:65be27845400	95	20U /* 8: CC6P */
AnnaBridge	172:65be27845400	96	};
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	static const uint8_t SHIFT_TAB_OISx[] =
AnnaBridge	172:65be27845400	99	{
AnnaBridge	172:65be27845400	100	0U, /* 0: OIS1 */
AnnaBridge	172:65be27845400	101	1U, /* 1: OIS1N */
AnnaBridge	172:65be27845400	102	2U, /* 2: OIS2 */
AnnaBridge	172:65be27845400	103	3U, /* 3: OIS2N */
AnnaBridge	172:65be27845400	104	4U, /* 4: OIS3 */
AnnaBridge	172:65be27845400	105	5U, /* 5: OIS3N */
AnnaBridge	172:65be27845400	106	6U, /* 6: OIS4 */
AnnaBridge	172:65be27845400	107	8U, /* 7: OIS5 */
AnnaBridge	172:65be27845400	108	10U /* 8: OIS6 */
AnnaBridge	172:65be27845400	109	};
AnnaBridge	172:65be27845400	110	/**
AnnaBridge	172:65be27845400	111	* @}
AnnaBridge	172:65be27845400	112	*/
AnnaBridge	172:65be27845400	113
AnnaBridge	172:65be27845400	114	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	115	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	172:65be27845400	116	* @{
AnnaBridge	172:65be27845400	117	*/
AnnaBridge	172:65be27845400	118
AnnaBridge	172:65be27845400	119	#if defined(TIM_BREAK_INPUT_SUPPORT)
AnnaBridge	172:65be27845400	120	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	172:65be27845400	121	#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FU)
AnnaBridge	172:65be27845400	122
AnnaBridge	172:65be27845400	123	/* Generic bit definitions for TIMx_AF1 register */
AnnaBridge	172:65be27845400	124	#define TIMx_AF1_BKINE TIM1_AF1_BKINE /!< BRK BKIN input enable /
AnnaBridge	172:65be27845400	125	#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /!< BRK COMP1 enable /
AnnaBridge	172:65be27845400	126	#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /!< BRK COMP2 enable /
AnnaBridge	172:65be27845400	127	#define TIMx_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E /!< BRK DFSDM1_BREAK[0] enable /
AnnaBridge	172:65be27845400	128	#define TIMx_AF1_BKINP TIM1_AF1_BKINP /!< BRK BKIN input polarity /
AnnaBridge	172:65be27845400	129	#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /!< BRK COMP1 input polarity /
AnnaBridge	172:65be27845400	130	#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /!< BRK COMP2 input polarity /
AnnaBridge	172:65be27845400	131	#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /!< TIMx ETR source selection /
AnnaBridge	172:65be27845400	132
AnnaBridge	172:65be27845400	133	/* Generic bit definitions for TIMx_AF2 register */
AnnaBridge	172:65be27845400	134	#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /!< BRK2 BKIN2 input enable /
AnnaBridge	172:65be27845400	135	#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /!< BRK2 COMP1 enable /
AnnaBridge	172:65be27845400	136	#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /!< BRK2 COMP2 enable /
AnnaBridge	172:65be27845400	137	#define TIMx_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E /!< BRK2 DFSDM1_BREAK[1] enable /
AnnaBridge	172:65be27845400	138	#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /!< BRK2 BKIN2 input polarity /
AnnaBridge	172:65be27845400	139	#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /!< BRK2 COMP1 input polarity /
AnnaBridge	172:65be27845400	140	#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /!< BRK2 COMP2 input polarity /
AnnaBridge	172:65be27845400	141	#endif /* TIM_BREAK_INPUT_SUPPORT */
AnnaBridge	172:65be27845400	142
AnnaBridge	172:65be27845400	143
AnnaBridge	172:65be27845400	144	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
AnnaBridge	172:65be27845400	145	#define DT_DELAY_1 ((uint8_t)0x7F)
AnnaBridge	172:65be27845400	146	#define DT_DELAY_2 ((uint8_t)0x3F)
AnnaBridge	172:65be27845400	147	#define DT_DELAY_3 ((uint8_t)0x1F)
AnnaBridge	172:65be27845400	148	#define DT_DELAY_4 ((uint8_t)0x1F)
AnnaBridge	172:65be27845400	149
AnnaBridge	172:65be27845400	150	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
AnnaBridge	172:65be27845400	151	#define DT_RANGE_1 ((uint8_t)0x00)
AnnaBridge	172:65be27845400	152	#define DT_RANGE_2 ((uint8_t)0x80)
AnnaBridge	172:65be27845400	153	#define DT_RANGE_3 ((uint8_t)0xC0)
AnnaBridge	172:65be27845400	154	#define DT_RANGE_4 ((uint8_t)0xE0)
AnnaBridge	172:65be27845400	155
AnnaBridge	172:65be27845400	156
AnnaBridge	172:65be27845400	157	/**
AnnaBridge	172:65be27845400	158	* @}
AnnaBridge	172:65be27845400	159	*/
AnnaBridge	172:65be27845400	160
AnnaBridge	172:65be27845400	161	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	162	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	172:65be27845400	163	* @{
AnnaBridge	172:65be27845400	164	*/
AnnaBridge	172:65be27845400	165	/** @brief Convert channel id into channel index.
AnnaBridge	172:65be27845400	166	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	167	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	168	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	169	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	170	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	171	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	172	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	173	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	174	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	175	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	176	* @retval none
AnnaBridge	172:65be27845400	177	*/
AnnaBridge	172:65be27845400	178	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	172:65be27845400	179	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	172:65be27845400	180	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	172:65be27845400	181	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	172:65be27845400	182	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	172:65be27845400	183	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	172:65be27845400	184	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
AnnaBridge	172:65be27845400	185	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
AnnaBridge	172:65be27845400	186	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
AnnaBridge	172:65be27845400	187
AnnaBridge	172:65be27845400	188	/** @brief Calculate the deadtime sampling period(in ps).
AnnaBridge	172:65be27845400	189	* @param __TIMCLK__ timer input clock frequency (in Hz).
AnnaBridge	172:65be27845400	190	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	191	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	192	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	193	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	194	* @retval none
AnnaBridge	172:65be27845400	195	*/
AnnaBridge	172:65be27845400	196	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
AnnaBridge	172:65be27845400	197	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
AnnaBridge	172:65be27845400	198	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
AnnaBridge	172:65be27845400	199	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
AnnaBridge	172:65be27845400	200	/**
AnnaBridge	172:65be27845400	201	* @}
AnnaBridge	172:65be27845400	202	*/
AnnaBridge	172:65be27845400	203
AnnaBridge	172:65be27845400	204
AnnaBridge	172:65be27845400	205	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	206	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	207	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	172:65be27845400	208	* @{
AnnaBridge	172:65be27845400	209	*/
AnnaBridge	172:65be27845400	210
AnnaBridge	172:65be27845400	211	/**
AnnaBridge	172:65be27845400	212	* @brief TIM Time Base configuration structure definition.
AnnaBridge	172:65be27845400	213	*/
AnnaBridge	172:65be27845400	214	typedef struct
AnnaBridge	172:65be27845400	215	{
AnnaBridge	172:65be27845400	216	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	172:65be27845400	217	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	172:65be27845400	218
AnnaBridge	172:65be27845400	219	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	172:65be27845400	220
AnnaBridge	172:65be27845400	221	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	172:65be27845400	222	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	172:65be27845400	223
AnnaBridge	172:65be27845400	224	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	172:65be27845400	227	Auto-Reload Register at the next update event.
AnnaBridge	172:65be27845400	228	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	172:65be27845400	229	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	230
AnnaBridge	172:65be27845400	231	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	172:65be27845400	232
AnnaBridge	172:65be27845400	233	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	172:65be27845400	234	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	172:65be27845400	235
AnnaBridge	172:65be27845400	236	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	172:65be27845400	237
AnnaBridge	172:65be27845400	238	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	172:65be27845400	239	reaches zero, an update event is generated and counting restarts
AnnaBridge	172:65be27845400	240	from the RCR value (N).
AnnaBridge	172:65be27845400	241	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	172:65be27845400	242	- the number of PWM periods in edge-aligned mode
AnnaBridge	172:65be27845400	243	- the number of half PWM period in center-aligned mode
AnnaBridge	172:65be27845400	244	This parameter must be a number between 0x00 and 0xFF.
AnnaBridge	172:65be27845400	245
AnnaBridge	172:65be27845400	246	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
AnnaBridge	172:65be27845400	247	} LL_TIM_InitTypeDef;
AnnaBridge	172:65be27845400	248
AnnaBridge	172:65be27845400	249	/**
AnnaBridge	172:65be27845400	250	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	172:65be27845400	251	*/
AnnaBridge	172:65be27845400	252	typedef struct
AnnaBridge	172:65be27845400	253	{
AnnaBridge	172:65be27845400	254	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	172:65be27845400	255	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	172:65be27845400	256
AnnaBridge	172:65be27845400	257	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	172:65be27845400	258
AnnaBridge	172:65be27845400	259	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	172:65be27845400	260	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	172:65be27845400	261
AnnaBridge	172:65be27845400	262	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	172:65be27845400	263
AnnaBridge	172:65be27845400	264	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
AnnaBridge	172:65be27845400	265	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	172:65be27845400	266
AnnaBridge	172:65be27845400	267	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	172:65be27845400	268
AnnaBridge	172:65be27845400	269	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	172:65be27845400	270	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	172:65be27845400	271
AnnaBridge	172:65be27845400	272	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	172:65be27845400	273
AnnaBridge	172:65be27845400	274	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	172:65be27845400	275	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	172:65be27845400	276
AnnaBridge	172:65be27845400	277	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	172:65be27845400	278
AnnaBridge	172:65be27845400	279	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	172:65be27845400	280	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	172:65be27845400	281
AnnaBridge	172:65be27845400	282	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	172:65be27845400	283
AnnaBridge	172:65be27845400	284
AnnaBridge	172:65be27845400	285	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	172:65be27845400	286	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	172:65be27845400	287
AnnaBridge	172:65be27845400	288	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	172:65be27845400	289
AnnaBridge	172:65be27845400	290	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	172:65be27845400	291	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	172:65be27845400	292
AnnaBridge	172:65be27845400	293	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	172:65be27845400	294	} LL_TIM_OC_InitTypeDef;
AnnaBridge	172:65be27845400	295
AnnaBridge	172:65be27845400	296	/**
AnnaBridge	172:65be27845400	297	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	172:65be27845400	298	*/
AnnaBridge	172:65be27845400	299
AnnaBridge	172:65be27845400	300	typedef struct
AnnaBridge	172:65be27845400	301	{
AnnaBridge	172:65be27845400	302
AnnaBridge	172:65be27845400	303	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	172:65be27845400	304	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	305
AnnaBridge	172:65be27845400	306	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	307
AnnaBridge	172:65be27845400	308	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	172:65be27845400	309	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	172:65be27845400	310
AnnaBridge	172:65be27845400	311	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	172:65be27845400	312
AnnaBridge	172:65be27845400	313	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	172:65be27845400	314	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	315
AnnaBridge	172:65be27845400	316	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	317
AnnaBridge	172:65be27845400	318	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	172:65be27845400	319	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	320
AnnaBridge	172:65be27845400	321	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	322	} LL_TIM_IC_InitTypeDef;
AnnaBridge	172:65be27845400	323
AnnaBridge	172:65be27845400	324
AnnaBridge	172:65be27845400	325	/**
AnnaBridge	172:65be27845400	326	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	172:65be27845400	327	*/
AnnaBridge	172:65be27845400	328	typedef struct
AnnaBridge	172:65be27845400	329	{
AnnaBridge	172:65be27845400	330	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	172:65be27845400	331	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	172:65be27845400	332
AnnaBridge	172:65be27845400	333	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	172:65be27845400	334
AnnaBridge	172:65be27845400	335	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	172:65be27845400	336	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	337
AnnaBridge	172:65be27845400	338	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	339
AnnaBridge	172:65be27845400	340	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	172:65be27845400	341	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	172:65be27845400	342
AnnaBridge	172:65be27845400	343	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	172:65be27845400	344
AnnaBridge	172:65be27845400	345	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	172:65be27845400	346	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	347
AnnaBridge	172:65be27845400	348	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	349
AnnaBridge	172:65be27845400	350	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	172:65be27845400	351	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	352
AnnaBridge	172:65be27845400	353	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	354
AnnaBridge	172:65be27845400	355	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	172:65be27845400	356	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	357
AnnaBridge	172:65be27845400	358	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	359
AnnaBridge	172:65be27845400	360	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	172:65be27845400	361	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	172:65be27845400	362
AnnaBridge	172:65be27845400	363	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	172:65be27845400	364
AnnaBridge	172:65be27845400	365	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	172:65be27845400	366	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	367
AnnaBridge	172:65be27845400	368	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	369
AnnaBridge	172:65be27845400	370	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	172:65be27845400	371	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	372
AnnaBridge	172:65be27845400	373	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	374
AnnaBridge	172:65be27845400	375	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	172:65be27845400	376
AnnaBridge	172:65be27845400	377	/**
AnnaBridge	172:65be27845400	378	* @brief TIM Hall sensor interface configuration structure definition.
AnnaBridge	172:65be27845400	379	*/
AnnaBridge	172:65be27845400	380	typedef struct
AnnaBridge	172:65be27845400	381	{
AnnaBridge	172:65be27845400	382
AnnaBridge	172:65be27845400	383	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	172:65be27845400	384	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	385
AnnaBridge	172:65be27845400	386	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	387
AnnaBridge	172:65be27845400	388	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	172:65be27845400	389	Prescaler must be set to get a maximum counter period longer than the
AnnaBridge	172:65be27845400	390	time interval between 2 consecutive changes on the Hall inputs.
AnnaBridge	172:65be27845400	391	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	392
AnnaBridge	172:65be27845400	393	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	394
AnnaBridge	172:65be27845400	395	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	172:65be27845400	396	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	397
AnnaBridge	172:65be27845400	398	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	399
AnnaBridge	172:65be27845400	400	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
AnnaBridge	172:65be27845400	401	A positive pulse (TRGO event) is generated with a programmable delay every time
AnnaBridge	172:65be27845400	402	a change occurs on the Hall inputs.
AnnaBridge	172:65be27845400	403	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
AnnaBridge	172:65be27845400	404
AnnaBridge	172:65be27845400	405	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
AnnaBridge	172:65be27845400	406	} LL_TIM_HALLSENSOR_InitTypeDef;
AnnaBridge	172:65be27845400	407
AnnaBridge	172:65be27845400	408	/**
AnnaBridge	172:65be27845400	409	* @brief BDTR (Break and Dead Time) structure definition
AnnaBridge	172:65be27845400	410	*/
AnnaBridge	172:65be27845400	411	typedef struct
AnnaBridge	172:65be27845400	412	{
AnnaBridge	172:65be27845400	413	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
AnnaBridge	172:65be27845400	414	This parameter can be a value of @ref TIM_LL_EC_OSSR
AnnaBridge	172:65be27845400	415
AnnaBridge	172:65be27845400	416	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	172:65be27845400	417
AnnaBridge	172:65be27845400	418	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	172:65be27845400	419
AnnaBridge	172:65be27845400	420	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
AnnaBridge	172:65be27845400	421	This parameter can be a value of @ref TIM_LL_EC_OSSI
AnnaBridge	172:65be27845400	422
AnnaBridge	172:65be27845400	423	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	172:65be27845400	424
AnnaBridge	172:65be27845400	425	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	172:65be27845400	426
AnnaBridge	172:65be27845400	427	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
AnnaBridge	172:65be27845400	428	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
AnnaBridge	172:65be27845400	429
AnnaBridge	172:65be27845400	430	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
AnnaBridge	172:65be27845400	431	has been written, their content is frozen until the next reset.*/
AnnaBridge	172:65be27845400	432
AnnaBridge	172:65be27845400	433	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
AnnaBridge	172:65be27845400	434	switching-on of the outputs.
AnnaBridge	172:65be27845400	435	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	172:65be27845400	436
AnnaBridge	172:65be27845400	437	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
AnnaBridge	172:65be27845400	438
AnnaBridge	172:65be27845400	439	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
AnnaBridge	172:65be27845400	440
AnnaBridge	172:65be27845400	441	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
AnnaBridge	172:65be27845400	442	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
AnnaBridge	172:65be27845400	443
AnnaBridge	172:65be27845400	444	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
AnnaBridge	172:65be27845400	445
AnnaBridge	172:65be27845400	446	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	447
AnnaBridge	172:65be27845400	448	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
AnnaBridge	172:65be27845400	449	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
AnnaBridge	172:65be27845400	450
AnnaBridge	172:65be27845400	451	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	172:65be27845400	452
AnnaBridge	172:65be27845400	453	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	454
AnnaBridge	172:65be27845400	455	uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
AnnaBridge	172:65be27845400	456	This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
AnnaBridge	172:65be27845400	457
AnnaBridge	172:65be27845400	458	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	172:65be27845400	459
AnnaBridge	172:65be27845400	460	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	461
AnnaBridge	172:65be27845400	462	uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
AnnaBridge	172:65be27845400	463	This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
AnnaBridge	172:65be27845400	464
AnnaBridge	172:65be27845400	465	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
AnnaBridge	172:65be27845400	466
AnnaBridge	172:65be27845400	467	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	468
AnnaBridge	172:65be27845400	469	uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
AnnaBridge	172:65be27845400	470	This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
AnnaBridge	172:65be27845400	471
AnnaBridge	172:65be27845400	472	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	172:65be27845400	473
AnnaBridge	172:65be27845400	474	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	475
AnnaBridge	172:65be27845400	476	uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
AnnaBridge	172:65be27845400	477	This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
AnnaBridge	172:65be27845400	478
AnnaBridge	172:65be27845400	479	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	172:65be27845400	480
AnnaBridge	172:65be27845400	481	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	482
AnnaBridge	172:65be27845400	483	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
AnnaBridge	172:65be27845400	484	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
AnnaBridge	172:65be27845400	485
AnnaBridge	172:65be27845400	486	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
AnnaBridge	172:65be27845400	487
AnnaBridge	172:65be27845400	488	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	489	} LL_TIM_BDTR_InitTypeDef;
AnnaBridge	172:65be27845400	490
AnnaBridge	172:65be27845400	491	/**
AnnaBridge	172:65be27845400	492	* @}
AnnaBridge	172:65be27845400	493	*/
AnnaBridge	172:65be27845400	494	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	495
AnnaBridge	172:65be27845400	496	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	497	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	172:65be27845400	498	* @{
AnnaBridge	172:65be27845400	499	*/
AnnaBridge	172:65be27845400	500
AnnaBridge	172:65be27845400	501	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	172:65be27845400	502	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	172:65be27845400	503	* @{
AnnaBridge	172:65be27845400	504	*/
AnnaBridge	172:65be27845400	505	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	172:65be27845400	506	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	172:65be27845400	507	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	172:65be27845400	508	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	172:65be27845400	509	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	172:65be27845400	510	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
AnnaBridge	172:65be27845400	511	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
AnnaBridge	172:65be27845400	512	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
AnnaBridge	172:65be27845400	513	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	172:65be27845400	514	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
AnnaBridge	172:65be27845400	515	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
AnnaBridge	172:65be27845400	516	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	172:65be27845400	517	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	172:65be27845400	518	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	172:65be27845400	519	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	172:65be27845400	520	#define LL_TIM_SR_SBIF TIM_SR_SBIF /!< System Break interrupt flag /
AnnaBridge	172:65be27845400	521	/**
AnnaBridge	172:65be27845400	522	* @}
AnnaBridge	172:65be27845400	523	*/
AnnaBridge	172:65be27845400	524
AnnaBridge	172:65be27845400	525	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	526	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
AnnaBridge	172:65be27845400	527	* @{
AnnaBridge	172:65be27845400	528	*/
AnnaBridge	172:65be27845400	529	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
AnnaBridge	172:65be27845400	530	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
AnnaBridge	172:65be27845400	531	/**
AnnaBridge	172:65be27845400	532	* @}
AnnaBridge	172:65be27845400	533	*/
AnnaBridge	172:65be27845400	534
AnnaBridge	172:65be27845400	535	/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
AnnaBridge	172:65be27845400	536	* @{
AnnaBridge	172:65be27845400	537	*/
AnnaBridge	172:65be27845400	538	#define LL_TIM_BREAK2_DISABLE 0x00000000U /!< Break2 function disabled /
AnnaBridge	172:65be27845400	539	#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break2 function enabled /
AnnaBridge	172:65be27845400	540	/**
AnnaBridge	172:65be27845400	541	* @}
AnnaBridge	172:65be27845400	542	*/
AnnaBridge	172:65be27845400	543
AnnaBridge	172:65be27845400	544	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
AnnaBridge	172:65be27845400	545	* @{
AnnaBridge	172:65be27845400	546	*/
AnnaBridge	172:65be27845400	547	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
AnnaBridge	172:65be27845400	548	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
AnnaBridge	172:65be27845400	549	/**
AnnaBridge	172:65be27845400	550	* @}
AnnaBridge	172:65be27845400	551	*/
AnnaBridge	172:65be27845400	552	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	553
AnnaBridge	172:65be27845400	554	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	172:65be27845400	555	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	172:65be27845400	556	* @{
AnnaBridge	172:65be27845400	557	*/
AnnaBridge	172:65be27845400	558	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	172:65be27845400	559	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	172:65be27845400	560	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	172:65be27845400	561	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	172:65be27845400	562	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	172:65be27845400	563	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
AnnaBridge	172:65be27845400	564	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	172:65be27845400	565	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
AnnaBridge	172:65be27845400	566	/**
AnnaBridge	172:65be27845400	567	* @}
AnnaBridge	172:65be27845400	568	*/
AnnaBridge	172:65be27845400	569
AnnaBridge	172:65be27845400	570	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	172:65be27845400	571	* @{
AnnaBridge	172:65be27845400	572	*/
AnnaBridge	172:65be27845400	573	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	172:65be27845400	574	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	172:65be27845400	575	/**
AnnaBridge	172:65be27845400	576	* @}
AnnaBridge	172:65be27845400	577	*/
AnnaBridge	172:65be27845400	578
AnnaBridge	172:65be27845400	579	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	172:65be27845400	580	* @{
AnnaBridge	172:65be27845400	581	*/
AnnaBridge	172:65be27845400	582	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	172:65be27845400	583	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	172:65be27845400	584	/**
AnnaBridge	172:65be27845400	585	* @}
AnnaBridge	172:65be27845400	586	*/
AnnaBridge	172:65be27845400	587
AnnaBridge	172:65be27845400	588	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	172:65be27845400	589	* @{
AnnaBridge	172:65be27845400	590	*/
AnnaBridge	172:65be27845400	591	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	172:65be27845400	592	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	172:65be27845400	593	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	172:65be27845400	594	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	172:65be27845400	595	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	172:65be27845400	596	/**
AnnaBridge	172:65be27845400	597	* @}
AnnaBridge	172:65be27845400	598	*/
AnnaBridge	172:65be27845400	599
AnnaBridge	172:65be27845400	600	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	172:65be27845400	601	* @{
AnnaBridge	172:65be27845400	602	*/
AnnaBridge	172:65be27845400	603	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	172:65be27845400	604	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	172:65be27845400	605	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	172:65be27845400	606	/**
AnnaBridge	172:65be27845400	607	* @}
AnnaBridge	172:65be27845400	608	*/
AnnaBridge	172:65be27845400	609
AnnaBridge	172:65be27845400	610	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	172:65be27845400	611	* @{
AnnaBridge	172:65be27845400	612	*/
AnnaBridge	172:65be27845400	613	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	172:65be27845400	614	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	172:65be27845400	615	/**
AnnaBridge	172:65be27845400	616	* @}
AnnaBridge	172:65be27845400	617	*/
AnnaBridge	172:65be27845400	618
AnnaBridge	172:65be27845400	619	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
AnnaBridge	172:65be27845400	620	* @{
AnnaBridge	172:65be27845400	621	*/
AnnaBridge	172:65be27845400	622	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
AnnaBridge	172:65be27845400	623	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
AnnaBridge	172:65be27845400	624	/**
AnnaBridge	172:65be27845400	625	* @}
AnnaBridge	172:65be27845400	626	*/
AnnaBridge	172:65be27845400	627
AnnaBridge	172:65be27845400	628	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	172:65be27845400	629	* @{
AnnaBridge	172:65be27845400	630	*/
AnnaBridge	172:65be27845400	631	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	172:65be27845400	632	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	172:65be27845400	633	/**
AnnaBridge	172:65be27845400	634	* @}
AnnaBridge	172:65be27845400	635	*/
AnnaBridge	172:65be27845400	636
AnnaBridge	172:65be27845400	637	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
AnnaBridge	172:65be27845400	638	* @{
AnnaBridge	172:65be27845400	639	*/
AnnaBridge	172:65be27845400	640	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
AnnaBridge	172:65be27845400	641	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
AnnaBridge	172:65be27845400	642	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
AnnaBridge	172:65be27845400	643	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
AnnaBridge	172:65be27845400	644	/**
AnnaBridge	172:65be27845400	645	* @}
AnnaBridge	172:65be27845400	646	*/
AnnaBridge	172:65be27845400	647
AnnaBridge	172:65be27845400	648	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	172:65be27845400	649	* @{
AnnaBridge	172:65be27845400	650	*/
AnnaBridge	172:65be27845400	651	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	172:65be27845400	652	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	172:65be27845400	653	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	172:65be27845400	654	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	172:65be27845400	655	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	172:65be27845400	656	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	172:65be27845400	657	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	172:65be27845400	658	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
AnnaBridge	172:65be27845400	659	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
AnnaBridge	172:65be27845400	660	/**
AnnaBridge	172:65be27845400	661	* @}
AnnaBridge	172:65be27845400	662	*/
AnnaBridge	172:65be27845400	663
AnnaBridge	172:65be27845400	664	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	665	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	172:65be27845400	666	* @{
AnnaBridge	172:65be27845400	667	*/
AnnaBridge	172:65be27845400	668	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	172:65be27845400	669	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	172:65be27845400	670	/**
AnnaBridge	172:65be27845400	671	* @}
AnnaBridge	172:65be27845400	672	*/
AnnaBridge	172:65be27845400	673	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	674
AnnaBridge	172:65be27845400	675	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	172:65be27845400	676	* @{
AnnaBridge	172:65be27845400	677	*/
AnnaBridge	172:65be27845400	678	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	172:65be27845400	679	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	172:65be27845400	680	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	172:65be27845400	681	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	172:65be27845400	682	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	172:65be27845400	683	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	172:65be27845400	684	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	172:65be27845400	685	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	172:65be27845400	686	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
AnnaBridge	172:65be27845400	687	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
AnnaBridge	172:65be27845400	688	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
AnnaBridge	172:65be27845400	689	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
AnnaBridge	172:65be27845400	690	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
AnnaBridge	172:65be27845400	691	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
AnnaBridge	172:65be27845400	692	/**
AnnaBridge	172:65be27845400	693	* @}
AnnaBridge	172:65be27845400	694	*/
AnnaBridge	172:65be27845400	695
AnnaBridge	172:65be27845400	696	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	172:65be27845400	697	* @{
AnnaBridge	172:65be27845400	698	*/
AnnaBridge	172:65be27845400	699	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	172:65be27845400	700	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	172:65be27845400	701	/**
AnnaBridge	172:65be27845400	702	* @}
AnnaBridge	172:65be27845400	703	*/
AnnaBridge	172:65be27845400	704
AnnaBridge	172:65be27845400	705	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
AnnaBridge	172:65be27845400	706	* @{
AnnaBridge	172:65be27845400	707	*/
AnnaBridge	172:65be27845400	708	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	172:65be27845400	709	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	172:65be27845400	710	/**
AnnaBridge	172:65be27845400	711	* @}
AnnaBridge	172:65be27845400	712	*/
AnnaBridge	172:65be27845400	713
AnnaBridge	172:65be27845400	714	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
AnnaBridge	172:65be27845400	715	* @{
AnnaBridge	172:65be27845400	716	*/
AnnaBridge	172:65be27845400	717	#define LL_TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
AnnaBridge	172:65be27845400	718	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
AnnaBridge	172:65be27845400	719	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
AnnaBridge	172:65be27845400	720	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
AnnaBridge	172:65be27845400	721	/**
AnnaBridge	172:65be27845400	722	* @}
AnnaBridge	172:65be27845400	723	*/
AnnaBridge	172:65be27845400	724
AnnaBridge	172:65be27845400	725	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	172:65be27845400	726	* @{
AnnaBridge	172:65be27845400	727	*/
AnnaBridge	172:65be27845400	728	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	172:65be27845400	729	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	172:65be27845400	730	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	172:65be27845400	731	/**
AnnaBridge	172:65be27845400	732	* @}
AnnaBridge	172:65be27845400	733	*/
AnnaBridge	172:65be27845400	734
AnnaBridge	172:65be27845400	735	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	172:65be27845400	736	* @{
AnnaBridge	172:65be27845400	737	*/
AnnaBridge	172:65be27845400	738	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	172:65be27845400	739	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	172:65be27845400	740	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	172:65be27845400	741	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	172:65be27845400	742	/**
AnnaBridge	172:65be27845400	743	* @}
AnnaBridge	172:65be27845400	744	*/
AnnaBridge	172:65be27845400	745
AnnaBridge	172:65be27845400	746	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	172:65be27845400	747	* @{
AnnaBridge	172:65be27845400	748	*/
AnnaBridge	172:65be27845400	749	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	172:65be27845400	750	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	751	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	752	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	753	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	754	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	755	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	756	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	757	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	172:65be27845400	758	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	759	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	760	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	761	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	762	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	763	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	764	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	765	/**
AnnaBridge	172:65be27845400	766	* @}
AnnaBridge	172:65be27845400	767	*/
AnnaBridge	172:65be27845400	768
AnnaBridge	172:65be27845400	769	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	172:65be27845400	770	* @{
AnnaBridge	172:65be27845400	771	*/
AnnaBridge	172:65be27845400	772	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	172:65be27845400	773	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	172:65be27845400	774	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	172:65be27845400	775	/**
AnnaBridge	172:65be27845400	776	* @}
AnnaBridge	172:65be27845400	777	*/
AnnaBridge	172:65be27845400	778
AnnaBridge	172:65be27845400	779	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	172:65be27845400	780	* @{
AnnaBridge	172:65be27845400	781	*/
AnnaBridge	172:65be27845400	782	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	172:65be27845400	783	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
AnnaBridge	172:65be27845400	784	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	172:65be27845400	785	/**
AnnaBridge	172:65be27845400	786	* @}
AnnaBridge	172:65be27845400	787	*/
AnnaBridge	172:65be27845400	788
AnnaBridge	172:65be27845400	789	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	172:65be27845400	790	* @{
AnnaBridge	172:65be27845400	791	*/
AnnaBridge	172:65be27845400	792	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	172:65be27845400	793	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	172:65be27845400	794	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
AnnaBridge	172:65be27845400	795	/**
AnnaBridge	172:65be27845400	796	* @}
AnnaBridge	172:65be27845400	797	*/
AnnaBridge	172:65be27845400	798
AnnaBridge	172:65be27845400	799	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	172:65be27845400	800	* @{
AnnaBridge	172:65be27845400	801	*/
AnnaBridge	172:65be27845400	802	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	172:65be27845400	803	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	172:65be27845400	804	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	172:65be27845400	805	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	172:65be27845400	806	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	172:65be27845400	807	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	172:65be27845400	808	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	172:65be27845400	809	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	172:65be27845400	810	/**
AnnaBridge	172:65be27845400	811	* @}
AnnaBridge	172:65be27845400	812	*/
AnnaBridge	172:65be27845400	813
AnnaBridge	172:65be27845400	814	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
AnnaBridge	172:65be27845400	815	* @{
AnnaBridge	172:65be27845400	816	*/
AnnaBridge	172:65be27845400	817	#define LL_TIM_TRGO2_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
AnnaBridge	172:65be27845400	818	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
AnnaBridge	172:65be27845400	819	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
AnnaBridge	172:65be27845400	820	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
AnnaBridge	172:65be27845400	821	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	822	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	823	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	824	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	825	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	826	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	827	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	828	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	829	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	830	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	831	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	832	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	833	/**
AnnaBridge	172:65be27845400	834	* @}
AnnaBridge	172:65be27845400	835	*/
AnnaBridge	172:65be27845400	836
AnnaBridge	172:65be27845400	837	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	172:65be27845400	838	* @{
AnnaBridge	172:65be27845400	839	*/
AnnaBridge	172:65be27845400	840	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	172:65be27845400	841	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	172:65be27845400	842	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	172:65be27845400	843	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	172:65be27845400	844	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
AnnaBridge	172:65be27845400	845	/**
AnnaBridge	172:65be27845400	846	* @}
AnnaBridge	172:65be27845400	847	*/
AnnaBridge	172:65be27845400	848
AnnaBridge	172:65be27845400	849	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	172:65be27845400	850	* @{
AnnaBridge	172:65be27845400	851	*/
AnnaBridge	172:65be27845400	852	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	172:65be27845400	853	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	172:65be27845400	854	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	172:65be27845400	855	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	172:65be27845400	856	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	172:65be27845400	857	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	172:65be27845400	858	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	172:65be27845400	859	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	172:65be27845400	860	#define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /!< Internal Trigger 4 (ITR4) is used as trigger input /
AnnaBridge	172:65be27845400	861	#define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_3) /!< Internal Trigger 5 (ITR5) is used as trigger input /
AnnaBridge	172:65be27845400	862	#define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_3) /!< Internal Trigger 6 (ITR6) is used as trigger input /
AnnaBridge	172:65be27845400	863	#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_3) /!< Internal Trigger 7 (ITR7) is used as trigger input /
AnnaBridge	172:65be27845400	864	#define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_3) /!< Internal Trigger 8 (ITR8) is used as trigger input /
AnnaBridge	172:65be27845400	865	/**
AnnaBridge	172:65be27845400	866	* @}
AnnaBridge	172:65be27845400	867	*/
AnnaBridge	172:65be27845400	868
AnnaBridge	172:65be27845400	869	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	172:65be27845400	870	* @{
AnnaBridge	172:65be27845400	871	*/
AnnaBridge	172:65be27845400	872	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	172:65be27845400	873	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	172:65be27845400	874	/**
AnnaBridge	172:65be27845400	875	* @}
AnnaBridge	172:65be27845400	876	*/
AnnaBridge	172:65be27845400	877
AnnaBridge	172:65be27845400	878	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	172:65be27845400	879	* @{
AnnaBridge	172:65be27845400	880	*/
AnnaBridge	172:65be27845400	881	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	172:65be27845400	882	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	172:65be27845400	883	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	172:65be27845400	884	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	172:65be27845400	885	/**
AnnaBridge	172:65be27845400	886	* @}
AnnaBridge	172:65be27845400	887	*/
AnnaBridge	172:65be27845400	888
AnnaBridge	172:65be27845400	889	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	172:65be27845400	890	* @{
AnnaBridge	172:65be27845400	891	*/
AnnaBridge	172:65be27845400	892	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	172:65be27845400	893	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	894	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	895	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	896	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	897	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	898	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	899	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	900	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	901	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	902	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	903	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	904	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	905	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	906	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	907	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	908	/**
AnnaBridge	172:65be27845400	909	* @}
AnnaBridge	172:65be27845400	910	*/
AnnaBridge	172:65be27845400	911
AnnaBridge	172:65be27845400	912
AnnaBridge	172:65be27845400	913	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
AnnaBridge	172:65be27845400	914	* @{
AnnaBridge	172:65be27845400	915	*/
AnnaBridge	172:65be27845400	916	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
AnnaBridge	172:65be27845400	917	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
AnnaBridge	172:65be27845400	918	/**
AnnaBridge	172:65be27845400	919	* @}
AnnaBridge	172:65be27845400	920	*/
AnnaBridge	172:65be27845400	921
AnnaBridge	172:65be27845400	922	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
AnnaBridge	172:65be27845400	923	* @{
AnnaBridge	172:65be27845400	924	*/
AnnaBridge	172:65be27845400	925	#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	172:65be27845400	926	#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	927	#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	928	#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	929	#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	930	#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	931	#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	932	#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	933	#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	172:65be27845400	934	#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	935	#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	936	#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	937	#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	938	#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	939	#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	940	#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	941	/**
AnnaBridge	172:65be27845400	942	* @}
AnnaBridge	172:65be27845400	943	*/
AnnaBridge	172:65be27845400	944
AnnaBridge	172:65be27845400	945	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
AnnaBridge	172:65be27845400	946	* @{
AnnaBridge	172:65be27845400	947	*/
AnnaBridge	172:65be27845400	948	#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
AnnaBridge	172:65be27845400	949	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
AnnaBridge	172:65be27845400	950	/**
AnnaBridge	172:65be27845400	951	* @}
AnnaBridge	172:65be27845400	952	*/
AnnaBridge	172:65be27845400	953
AnnaBridge	172:65be27845400	954	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
AnnaBridge	172:65be27845400	955	* @{
AnnaBridge	172:65be27845400	956	*/
AnnaBridge	172:65be27845400	957	#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	172:65be27845400	958	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	959	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	960	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	961	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	962	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	963	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	964	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	965	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	172:65be27845400	966	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	967	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	968	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	969	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	970	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	971	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	972	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	973	/**
AnnaBridge	172:65be27845400	974	* @}
AnnaBridge	172:65be27845400	975	*/
AnnaBridge	172:65be27845400	976
AnnaBridge	172:65be27845400	977	/** @defgroup TIM_LL_EC_OSSI OSSI
AnnaBridge	172:65be27845400	978	* @{
AnnaBridge	172:65be27845400	979	*/
AnnaBridge	172:65be27845400	980	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	172:65be27845400	981	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
AnnaBridge	172:65be27845400	982	/**
AnnaBridge	172:65be27845400	983	* @}
AnnaBridge	172:65be27845400	984	*/
AnnaBridge	172:65be27845400	985
AnnaBridge	172:65be27845400	986	/** @defgroup TIM_LL_EC_OSSR OSSR
AnnaBridge	172:65be27845400	987	* @{
AnnaBridge	172:65be27845400	988	*/
AnnaBridge	172:65be27845400	989	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	172:65be27845400	990	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
AnnaBridge	172:65be27845400	991	/**
AnnaBridge	172:65be27845400	992	* @}
AnnaBridge	172:65be27845400	993	*/
AnnaBridge	172:65be27845400	994
AnnaBridge	172:65be27845400	995	#if defined(TIM_BREAK_INPUT_SUPPORT)
AnnaBridge	172:65be27845400	996	/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
AnnaBridge	172:65be27845400	997	* @{
AnnaBridge	172:65be27845400	998	*/
AnnaBridge	172:65be27845400	999	#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /!< TIMx_BKIN input /
AnnaBridge	172:65be27845400	1000	#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /!< TIMx_BKIN2 input /
AnnaBridge	172:65be27845400	1001	/**
AnnaBridge	172:65be27845400	1002	* @}
AnnaBridge	172:65be27845400	1003	*/
AnnaBridge	172:65be27845400	1004
AnnaBridge	172:65be27845400	1005	/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
AnnaBridge	172:65be27845400	1006	* @{
AnnaBridge	172:65be27845400	1007	*/
AnnaBridge	172:65be27845400	1008	#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /!< BKIN input from AF controller /
AnnaBridge	172:65be27845400	1009	#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /!< internal signal: COMP1 output /
AnnaBridge	172:65be27845400	1010	#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /!< internal signal: COMP2 output /
AnnaBridge	172:65be27845400	1011	#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /!< internal signal: DFSDM1 break output /
AnnaBridge	172:65be27845400	1012	/**
AnnaBridge	172:65be27845400	1013	* @}
AnnaBridge	172:65be27845400	1014	*/
AnnaBridge	172:65be27845400	1015
AnnaBridge	172:65be27845400	1016	/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
AnnaBridge	172:65be27845400	1017	* @{
AnnaBridge	172:65be27845400	1018	*/
AnnaBridge	172:65be27845400	1019	#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /!< BRK BKIN input is active low /
AnnaBridge	172:65be27845400	1020	#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /!< BRK BKIN input is active high /
AnnaBridge	172:65be27845400	1021	/**
AnnaBridge	172:65be27845400	1022	* @}
AnnaBridge	172:65be27845400	1023	*/
AnnaBridge	172:65be27845400	1024	#endif /* TIM_BREAK_INPUT_SUPPORT */
AnnaBridge	172:65be27845400	1025
AnnaBridge	172:65be27845400	1026	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	172:65be27845400	1027	* @{
AnnaBridge	172:65be27845400	1028	*/
AnnaBridge	172:65be27845400	1029	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1030	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1031	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1032	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1033	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1034	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1035	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1036	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1037	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1038	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1039	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1040	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1041	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1042	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1043	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1044	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1045	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1046	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1047	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1048	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1049	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1050	#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_TISEL register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1051	#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_AF1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1052	#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_AF2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1053	/**
AnnaBridge	172:65be27845400	1054	* @}
AnnaBridge	172:65be27845400	1055	*/
AnnaBridge	172:65be27845400	1056
AnnaBridge	172:65be27845400	1057	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	172:65be27845400	1058	* @{
AnnaBridge	172:65be27845400	1059	*/
AnnaBridge	172:65be27845400	1060	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1061	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1062	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1063	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1064	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1065	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1066	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1067	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1068	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1069	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1070	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1071	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1072	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1073	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1074	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1075	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1076	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1077	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1078	/**
AnnaBridge	172:65be27845400	1079	* @}
AnnaBridge	172:65be27845400	1080	*/
AnnaBridge	172:65be27845400	1081
AnnaBridge	172:65be27845400	1082
AnnaBridge	172:65be27845400	1083	#if defined(TIM_BREAK_INPUT_SUPPORT)
AnnaBridge	172:65be27845400	1084	/** Legacy definitions for compatibility purpose
AnnaBridge	172:65be27845400	1085	@cond 0
AnnaBridge	172:65be27845400	1086	*/
AnnaBridge	172:65be27845400	1087	#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	172:65be27845400	1088	/**
AnnaBridge	172:65be27845400	1089	@endcond
AnnaBridge	172:65be27845400	1090	*/
AnnaBridge	172:65be27845400	1091	#endif /* TIM_BREAK_INPUT_SUPPORT */
AnnaBridge	172:65be27845400	1092	/**
AnnaBridge	172:65be27845400	1093	* @}
AnnaBridge	172:65be27845400	1094	*/
AnnaBridge	172:65be27845400	1095
AnnaBridge	172:65be27845400	1096	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	1097	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	172:65be27845400	1098	* @{
AnnaBridge	172:65be27845400	1099	*/
AnnaBridge	172:65be27845400	1100
AnnaBridge	172:65be27845400	1101	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	172:65be27845400	1102	* @{
AnnaBridge	172:65be27845400	1103	*/
AnnaBridge	172:65be27845400	1104	/**
AnnaBridge	172:65be27845400	1105	* @brief Write a value in TIM register.
AnnaBridge	172:65be27845400	1106	* @param __INSTANCE__ TIM Instance
AnnaBridge	172:65be27845400	1107	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	1108	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	1109	* @retval None
AnnaBridge	172:65be27845400	1110	*/
AnnaBridge	172:65be27845400	1111	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	1112
AnnaBridge	172:65be27845400	1113	/**
AnnaBridge	172:65be27845400	1114	* @brief Read a value in TIM register.
AnnaBridge	172:65be27845400	1115	* @param __INSTANCE__ TIM Instance
AnnaBridge	172:65be27845400	1116	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	1117	* @retval Register value
AnnaBridge	172:65be27845400	1118	*/
AnnaBridge	172:65be27845400	1119	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
AnnaBridge	172:65be27845400	1120	/**
AnnaBridge	172:65be27845400	1121	* @}
AnnaBridge	172:65be27845400	1122	*/
AnnaBridge	172:65be27845400	1123
AnnaBridge	172:65be27845400	1124	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	172:65be27845400	1125	* @{
AnnaBridge	172:65be27845400	1126	*/
AnnaBridge	172:65be27845400	1127
AnnaBridge	172:65be27845400	1128	/**
AnnaBridge	172:65be27845400	1129	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
AnnaBridge	172:65be27845400	1130	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
AnnaBridge	172:65be27845400	1131	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
AnnaBridge	172:65be27845400	1132	* to TIMx_CNT register bit 31)
AnnaBridge	172:65be27845400	1133	* @param __CNT__ Counter value
AnnaBridge	172:65be27845400	1134	* @retval UIF status bit
AnnaBridge	172:65be27845400	1135	*/
AnnaBridge	172:65be27845400	1136	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
AnnaBridge	172:65be27845400	1137	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
AnnaBridge	172:65be27845400	1138
AnnaBridge	172:65be27845400	1139	/**
AnnaBridge	172:65be27845400	1140	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
AnnaBridge	172:65be27845400	1141	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
AnnaBridge	172:65be27845400	1142	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1143	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1144	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	1145	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	1146	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	1147	* @param __DT__ deadtime duration (in ns)
AnnaBridge	172:65be27845400	1148	* @retval DTG[0:7]
AnnaBridge	172:65be27845400	1149	*/
AnnaBridge	172:65be27845400	1150	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
AnnaBridge	172:65be27845400	1151	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
AnnaBridge	172:65be27845400	1152	(((uint64_t)((__DT__)1000U)) < ((64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
AnnaBridge	172:65be27845400	1153	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
AnnaBridge	172:65be27845400	1154	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
AnnaBridge	172:65be27845400	1155	0U)
AnnaBridge	172:65be27845400	1156
AnnaBridge	172:65be27845400	1157	/**
AnnaBridge	172:65be27845400	1158	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	172:65be27845400	1159	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	172:65be27845400	1160	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1161	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	172:65be27845400	1162	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1163	*/
AnnaBridge	172:65be27845400	1164	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	172:65be27845400	1165	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
AnnaBridge	172:65be27845400	1166
AnnaBridge	172:65be27845400	1167	/**
AnnaBridge	172:65be27845400	1168	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	172:65be27845400	1169	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	172:65be27845400	1170	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1171	* @param __PSC__ prescaler
AnnaBridge	172:65be27845400	1172	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	172:65be27845400	1173	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1174	*/
AnnaBridge	172:65be27845400	1175	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	172:65be27845400	1176	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
AnnaBridge	172:65be27845400	1177
AnnaBridge	172:65be27845400	1178	/**
AnnaBridge	172:65be27845400	1179	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	172:65be27845400	1180	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	172:65be27845400	1181	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1182	* @param __PSC__ prescaler
AnnaBridge	172:65be27845400	1183	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	172:65be27845400	1184	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1185	*/
AnnaBridge	172:65be27845400	1186	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	172:65be27845400	1187	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	172:65be27845400	1188	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	172:65be27845400	1189
AnnaBridge	172:65be27845400	1190	/**
AnnaBridge	172:65be27845400	1191	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	172:65be27845400	1192	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	172:65be27845400	1193	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1194	* @param __PSC__ prescaler
AnnaBridge	172:65be27845400	1195	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	172:65be27845400	1196	* @param __PULSE__ pulse duration (in us)
AnnaBridge	172:65be27845400	1197	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1198	*/
AnnaBridge	172:65be27845400	1199	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	172:65be27845400	1200	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	172:65be27845400	1201	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	172:65be27845400	1202
AnnaBridge	172:65be27845400	1203	/**
AnnaBridge	172:65be27845400	1204	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	172:65be27845400	1205	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	172:65be27845400	1206	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1207	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	172:65be27845400	1208	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	172:65be27845400	1209	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	172:65be27845400	1210	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	1211	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	172:65be27845400	1212	*/
AnnaBridge	172:65be27845400	1213	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	172:65be27845400	1214	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	172:65be27845400	1215
AnnaBridge	172:65be27845400	1216
AnnaBridge	172:65be27845400	1217	/**
AnnaBridge	172:65be27845400	1218	* @}
AnnaBridge	172:65be27845400	1219	*/
AnnaBridge	172:65be27845400	1220
AnnaBridge	172:65be27845400	1221
AnnaBridge	172:65be27845400	1222	/**
AnnaBridge	172:65be27845400	1223	* @}
AnnaBridge	172:65be27845400	1224	*/
AnnaBridge	172:65be27845400	1225
AnnaBridge	172:65be27845400	1226	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	1227	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	172:65be27845400	1228	* @{
AnnaBridge	172:65be27845400	1229	*/
AnnaBridge	172:65be27845400	1230
AnnaBridge	172:65be27845400	1231	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	172:65be27845400	1232	* @{
AnnaBridge	172:65be27845400	1233	*/
AnnaBridge	172:65be27845400	1234	/**
AnnaBridge	172:65be27845400	1235	* @brief Enable timer counter.
AnnaBridge	172:65be27845400	1236	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	172:65be27845400	1237	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1238	* @retval None
AnnaBridge	172:65be27845400	1239	*/
AnnaBridge	172:65be27845400	1240	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1241	{
AnnaBridge	172:65be27845400	1242	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	172:65be27845400	1243	}
AnnaBridge	172:65be27845400	1244
AnnaBridge	172:65be27845400	1245	/**
AnnaBridge	172:65be27845400	1246	* @brief Disable timer counter.
AnnaBridge	172:65be27845400	1247	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	172:65be27845400	1248	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1249	* @retval None
AnnaBridge	172:65be27845400	1250	*/
AnnaBridge	172:65be27845400	1251	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1252	{
AnnaBridge	172:65be27845400	1253	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	172:65be27845400	1254	}
AnnaBridge	172:65be27845400	1255
AnnaBridge	172:65be27845400	1256	/**
AnnaBridge	172:65be27845400	1257	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	172:65be27845400	1258	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	172:65be27845400	1259	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1260	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1261	*/
AnnaBridge	172:65be27845400	1262	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1263	{
AnnaBridge	172:65be27845400	1264	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1265	}
AnnaBridge	172:65be27845400	1266
AnnaBridge	172:65be27845400	1267	/**
AnnaBridge	172:65be27845400	1268	* @brief Enable update event generation.
AnnaBridge	172:65be27845400	1269	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	172:65be27845400	1270	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1271	* @retval None
AnnaBridge	172:65be27845400	1272	*/
AnnaBridge	172:65be27845400	1273	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1274	{
AnnaBridge	172:65be27845400	1275	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	172:65be27845400	1276	}
AnnaBridge	172:65be27845400	1277
AnnaBridge	172:65be27845400	1278	/**
AnnaBridge	172:65be27845400	1279	* @brief Disable update event generation.
AnnaBridge	172:65be27845400	1280	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	172:65be27845400	1281	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1282	* @retval None
AnnaBridge	172:65be27845400	1283	*/
AnnaBridge	172:65be27845400	1284	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1285	{
AnnaBridge	172:65be27845400	1286	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	172:65be27845400	1287	}
AnnaBridge	172:65be27845400	1288
AnnaBridge	172:65be27845400	1289	/**
AnnaBridge	172:65be27845400	1290	* @brief Indicates whether update event generation is enabled.
AnnaBridge	172:65be27845400	1291	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	172:65be27845400	1292	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1293	* @retval Inverted state of bit (0 or 1).
AnnaBridge	172:65be27845400	1294	*/
AnnaBridge	172:65be27845400	1295	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1296	{
AnnaBridge	172:65be27845400	1297	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1298	}
AnnaBridge	172:65be27845400	1299
AnnaBridge	172:65be27845400	1300	/**
AnnaBridge	172:65be27845400	1301	* @brief Set update event source
AnnaBridge	172:65be27845400	1302	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	172:65be27845400	1303	* generate an update interrupt or DMA request if enabled:
AnnaBridge	172:65be27845400	1304	* - Counter overflow/underflow
AnnaBridge	172:65be27845400	1305	* - Setting the UG bit
AnnaBridge	172:65be27845400	1306	* - Update generation through the slave mode controller
AnnaBridge	172:65be27845400	1307	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	172:65be27845400	1308	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	172:65be27845400	1309	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	172:65be27845400	1310	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1311	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1312	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	172:65be27845400	1313	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	172:65be27845400	1314	* @retval None
AnnaBridge	172:65be27845400	1315	*/
AnnaBridge	172:65be27845400	1316	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	172:65be27845400	1317	{
AnnaBridge	172:65be27845400	1318	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	172:65be27845400	1319	}
AnnaBridge	172:65be27845400	1320
AnnaBridge	172:65be27845400	1321	/**
AnnaBridge	172:65be27845400	1322	* @brief Get actual event update source
AnnaBridge	172:65be27845400	1323	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	172:65be27845400	1324	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1325	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1326	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	172:65be27845400	1327	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	172:65be27845400	1328	*/
AnnaBridge	172:65be27845400	1329	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1330	{
AnnaBridge	172:65be27845400	1331	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	172:65be27845400	1332	}
AnnaBridge	172:65be27845400	1333
AnnaBridge	172:65be27845400	1334	/**
AnnaBridge	172:65be27845400	1335	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	172:65be27845400	1336	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	172:65be27845400	1337	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1338	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1339	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	172:65be27845400	1340	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	172:65be27845400	1341	* @retval None
AnnaBridge	172:65be27845400	1342	*/
AnnaBridge	172:65be27845400	1343	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	172:65be27845400	1344	{
AnnaBridge	172:65be27845400	1345	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	172:65be27845400	1346	}
AnnaBridge	172:65be27845400	1347
AnnaBridge	172:65be27845400	1348	/**
AnnaBridge	172:65be27845400	1349	* @brief Get actual one pulse mode.
AnnaBridge	172:65be27845400	1350	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	172:65be27845400	1351	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1352	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1353	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	172:65be27845400	1354	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	172:65be27845400	1355	*/
AnnaBridge	172:65be27845400	1356	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1357	{
AnnaBridge	172:65be27845400	1358	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	172:65be27845400	1359	}
AnnaBridge	172:65be27845400	1360
AnnaBridge	172:65be27845400	1361	/**
AnnaBridge	172:65be27845400	1362	* @brief Set the timer counter counting mode.
AnnaBridge	172:65be27845400	1363	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	172:65be27845400	1364	* check whether or not the counter mode selection feature is supported
AnnaBridge	172:65be27845400	1365	* by a timer instance.
AnnaBridge	172:65be27845400	1366	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
AnnaBridge	172:65be27845400	1367	* requires a timer reset to avoid unexpected direction
AnnaBridge	172:65be27845400	1368	* due to DIR bit readonly in center aligned mode.
AnnaBridge	172:65be27845400	1369	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	172:65be27845400	1370	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	172:65be27845400	1371	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1372	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1373	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	172:65be27845400	1374	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	172:65be27845400	1375	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	172:65be27845400	1376	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	172:65be27845400	1377	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	172:65be27845400	1378	* @retval None
AnnaBridge	172:65be27845400	1379	*/
AnnaBridge	172:65be27845400	1380	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	172:65be27845400	1381	{
AnnaBridge	172:65be27845400	1382	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
AnnaBridge	172:65be27845400	1383	}
AnnaBridge	172:65be27845400	1384
AnnaBridge	172:65be27845400	1385	/**
AnnaBridge	172:65be27845400	1386	* @brief Get actual counter mode.
AnnaBridge	172:65be27845400	1387	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	172:65be27845400	1388	* check whether or not the counter mode selection feature is supported
AnnaBridge	172:65be27845400	1389	* by a timer instance.
AnnaBridge	172:65be27845400	1390	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	172:65be27845400	1391	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	172:65be27845400	1392	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1393	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1394	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	172:65be27845400	1395	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	172:65be27845400	1396	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	172:65be27845400	1397	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	172:65be27845400	1398	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	172:65be27845400	1399	*/
AnnaBridge	172:65be27845400	1400	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1401	{
AnnaBridge	172:65be27845400	1402	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	172:65be27845400	1403	}
AnnaBridge	172:65be27845400	1404
AnnaBridge	172:65be27845400	1405	/**
AnnaBridge	172:65be27845400	1406	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	172:65be27845400	1407	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	172:65be27845400	1408	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1409	* @retval None
AnnaBridge	172:65be27845400	1410	*/
AnnaBridge	172:65be27845400	1411	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1412	{
AnnaBridge	172:65be27845400	1413	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	172:65be27845400	1414	}
AnnaBridge	172:65be27845400	1415
AnnaBridge	172:65be27845400	1416	/**
AnnaBridge	172:65be27845400	1417	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	172:65be27845400	1418	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	172:65be27845400	1419	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1420	* @retval None
AnnaBridge	172:65be27845400	1421	*/
AnnaBridge	172:65be27845400	1422	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1423	{
AnnaBridge	172:65be27845400	1424	CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE);
AnnaBridge	172:65be27845400	1425	}
AnnaBridge	172:65be27845400	1426
AnnaBridge	172:65be27845400	1427	/**
AnnaBridge	172:65be27845400	1428	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	172:65be27845400	1429	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	172:65be27845400	1430	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1431	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1432	*/
AnnaBridge	172:65be27845400	1433	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1434	{
AnnaBridge	172:65be27845400	1435	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1436	}
AnnaBridge	172:65be27845400	1437
AnnaBridge	172:65be27845400	1438	/**
AnnaBridge	172:65be27845400	1439	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	172:65be27845400	1440	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1441	* whether or not the clock division feature is supported by the timer
AnnaBridge	172:65be27845400	1442	* instance.
AnnaBridge	172:65be27845400	1443	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	172:65be27845400	1444	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1445	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1446	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	1447	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	1448	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	1449	* @retval None
AnnaBridge	172:65be27845400	1450	*/
AnnaBridge	172:65be27845400	1451	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	172:65be27845400	1452	{
AnnaBridge	172:65be27845400	1453	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	172:65be27845400	1454	}
AnnaBridge	172:65be27845400	1455
AnnaBridge	172:65be27845400	1456	/**
AnnaBridge	172:65be27845400	1457	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	172:65be27845400	1458	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1459	* whether or not the clock division feature is supported by the timer
AnnaBridge	172:65be27845400	1460	* instance.
AnnaBridge	172:65be27845400	1461	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	172:65be27845400	1462	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1463	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1464	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	1465	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	1466	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	1467	*/
AnnaBridge	172:65be27845400	1468	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1469	{
AnnaBridge	172:65be27845400	1470	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	172:65be27845400	1471	}
AnnaBridge	172:65be27845400	1472
AnnaBridge	172:65be27845400	1473	/**
AnnaBridge	172:65be27845400	1474	* @brief Set the counter value.
AnnaBridge	172:65be27845400	1475	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1476	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1477	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	172:65be27845400	1478	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1479	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	172:65be27845400	1480	* @retval None
AnnaBridge	172:65be27845400	1481	*/
AnnaBridge	172:65be27845400	1482	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	172:65be27845400	1483	{
AnnaBridge	172:65be27845400	1484	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	172:65be27845400	1485	}
AnnaBridge	172:65be27845400	1486
AnnaBridge	172:65be27845400	1487	/**
AnnaBridge	172:65be27845400	1488	* @brief Get the counter value.
AnnaBridge	172:65be27845400	1489	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1490	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1491	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	172:65be27845400	1492	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1493	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	172:65be27845400	1494	*/
AnnaBridge	172:65be27845400	1495	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1496	{
AnnaBridge	172:65be27845400	1497	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	172:65be27845400	1498	}
AnnaBridge	172:65be27845400	1499
AnnaBridge	172:65be27845400	1500	/**
AnnaBridge	172:65be27845400	1501	* @brief Get the current direction of the counter
AnnaBridge	172:65be27845400	1502	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	172:65be27845400	1503	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1504	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1505	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	172:65be27845400	1506	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	172:65be27845400	1507	*/
AnnaBridge	172:65be27845400	1508	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1509	{
AnnaBridge	172:65be27845400	1510	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	172:65be27845400	1511	}
AnnaBridge	172:65be27845400	1512
AnnaBridge	172:65be27845400	1513	/**
AnnaBridge	172:65be27845400	1514	* @brief Set the prescaler value.
AnnaBridge	172:65be27845400	1515	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	172:65be27845400	1516	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	172:65be27845400	1517	* prescaler ratio is taken into account at the next update event.
AnnaBridge	172:65be27845400	1518	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	172:65be27845400	1519	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	172:65be27845400	1520	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1521	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	1522	* @retval None
AnnaBridge	172:65be27845400	1523	*/
AnnaBridge	172:65be27845400	1524	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	172:65be27845400	1525	{
AnnaBridge	172:65be27845400	1526	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	172:65be27845400	1527	}
AnnaBridge	172:65be27845400	1528
AnnaBridge	172:65be27845400	1529	/**
AnnaBridge	172:65be27845400	1530	* @brief Get the prescaler value.
AnnaBridge	172:65be27845400	1531	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	172:65be27845400	1532	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1533	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	1534	*/
AnnaBridge	172:65be27845400	1535	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1536	{
AnnaBridge	172:65be27845400	1537	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	172:65be27845400	1538	}
AnnaBridge	172:65be27845400	1539
AnnaBridge	172:65be27845400	1540	/**
AnnaBridge	172:65be27845400	1541	* @brief Set the auto-reload value.
AnnaBridge	172:65be27845400	1542	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	172:65be27845400	1543	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1544	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1545	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	172:65be27845400	1546	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	172:65be27845400	1547	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1548	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	1549	* @retval None
AnnaBridge	172:65be27845400	1550	*/
AnnaBridge	172:65be27845400	1551	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	172:65be27845400	1552	{
AnnaBridge	172:65be27845400	1553	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	172:65be27845400	1554	}
AnnaBridge	172:65be27845400	1555
AnnaBridge	172:65be27845400	1556	/**
AnnaBridge	172:65be27845400	1557	* @brief Get the auto-reload value.
AnnaBridge	172:65be27845400	1558	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	172:65be27845400	1559	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1560	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1561	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1562	* @retval Auto-reload value
AnnaBridge	172:65be27845400	1563	*/
AnnaBridge	172:65be27845400	1564	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1565	{
AnnaBridge	172:65be27845400	1566	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	172:65be27845400	1567	}
AnnaBridge	172:65be27845400	1568
AnnaBridge	172:65be27845400	1569	/**
AnnaBridge	172:65be27845400	1570	* @brief Set the repetition counter value.
AnnaBridge	172:65be27845400	1571	* @note For advanced timer instances RepetitionCounter can be up to 65535.
AnnaBridge	172:65be27845400	1572	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1573	* whether or not a timer instance supports a repetition counter.
AnnaBridge	172:65be27845400	1574	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
AnnaBridge	172:65be27845400	1575	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1576	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
AnnaBridge	172:65be27845400	1577	* @retval None
AnnaBridge	172:65be27845400	1578	*/
AnnaBridge	172:65be27845400	1579	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
AnnaBridge	172:65be27845400	1580	{
AnnaBridge	172:65be27845400	1581	WRITE_REG(TIMx->RCR, RepetitionCounter);
AnnaBridge	172:65be27845400	1582	}
AnnaBridge	172:65be27845400	1583
AnnaBridge	172:65be27845400	1584	/**
AnnaBridge	172:65be27845400	1585	* @brief Get the repetition counter value.
AnnaBridge	172:65be27845400	1586	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1587	* whether or not a timer instance supports a repetition counter.
AnnaBridge	172:65be27845400	1588	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
AnnaBridge	172:65be27845400	1589	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1590	* @retval Repetition counter value
AnnaBridge	172:65be27845400	1591	*/
AnnaBridge	172:65be27845400	1592	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1593	{
AnnaBridge	172:65be27845400	1594	return (uint32_t)(READ_REG(TIMx->RCR));
AnnaBridge	172:65be27845400	1595	}
AnnaBridge	172:65be27845400	1596
AnnaBridge	172:65be27845400	1597	/**
AnnaBridge	172:65be27845400	1598	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
AnnaBridge	172:65be27845400	1599	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
AnnaBridge	172:65be27845400	1600	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
AnnaBridge	172:65be27845400	1601	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1602	* @retval None
AnnaBridge	172:65be27845400	1603	*/
AnnaBridge	172:65be27845400	1604	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1605	{
AnnaBridge	172:65be27845400	1606	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	172:65be27845400	1607	}
AnnaBridge	172:65be27845400	1608
AnnaBridge	172:65be27845400	1609	/**
AnnaBridge	172:65be27845400	1610	* @brief Disable update interrupt flag (UIF) remapping.
AnnaBridge	172:65be27845400	1611	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
AnnaBridge	172:65be27845400	1612	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1613	* @retval None
AnnaBridge	172:65be27845400	1614	*/
AnnaBridge	172:65be27845400	1615	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1616	{
AnnaBridge	172:65be27845400	1617	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	172:65be27845400	1618	}
AnnaBridge	172:65be27845400	1619
AnnaBridge	172:65be27845400	1620	/**
AnnaBridge	172:65be27845400	1621	* @}
AnnaBridge	172:65be27845400	1622	*/
AnnaBridge	172:65be27845400	1623
AnnaBridge	172:65be27845400	1624	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	172:65be27845400	1625	* @{
AnnaBridge	172:65be27845400	1626	*/
AnnaBridge	172:65be27845400	1627	/**
AnnaBridge	172:65be27845400	1628	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	172:65be27845400	1629	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
AnnaBridge	172:65be27845400	1630	* they are updated only when a commutation event (COM) occurs.
AnnaBridge	172:65be27845400	1631	* @note Only on channels that have a complementary output.
AnnaBridge	172:65be27845400	1632	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1633	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	172:65be27845400	1634	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
AnnaBridge	172:65be27845400	1635	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1636	* @retval None
AnnaBridge	172:65be27845400	1637	*/
AnnaBridge	172:65be27845400	1638	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1639	{
AnnaBridge	172:65be27845400	1640	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	172:65be27845400	1641	}
AnnaBridge	172:65be27845400	1642
AnnaBridge	172:65be27845400	1643	/**
AnnaBridge	172:65be27845400	1644	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	172:65be27845400	1645	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1646	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	172:65be27845400	1647	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
AnnaBridge	172:65be27845400	1648	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1649	* @retval None
AnnaBridge	172:65be27845400	1650	*/
AnnaBridge	172:65be27845400	1651	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1652	{
AnnaBridge	172:65be27845400	1653	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	172:65be27845400	1654	}
AnnaBridge	172:65be27845400	1655
AnnaBridge	172:65be27845400	1656	/**
AnnaBridge	172:65be27845400	1657	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
AnnaBridge	172:65be27845400	1658	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1659	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	172:65be27845400	1660	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
AnnaBridge	172:65be27845400	1661	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1662	* @param CCUpdateSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1663	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
AnnaBridge	172:65be27845400	1664	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
AnnaBridge	172:65be27845400	1665	* @retval None
AnnaBridge	172:65be27845400	1666	*/
AnnaBridge	172:65be27845400	1667	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
AnnaBridge	172:65be27845400	1668	{
AnnaBridge	172:65be27845400	1669	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
AnnaBridge	172:65be27845400	1670	}
AnnaBridge	172:65be27845400	1671
AnnaBridge	172:65be27845400	1672	/**
AnnaBridge	172:65be27845400	1673	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	172:65be27845400	1674	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	172:65be27845400	1675	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1676	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1677	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	172:65be27845400	1678	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	172:65be27845400	1679	* @retval None
AnnaBridge	172:65be27845400	1680	*/
AnnaBridge	172:65be27845400	1681	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	172:65be27845400	1682	{
AnnaBridge	172:65be27845400	1683	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	172:65be27845400	1684	}
AnnaBridge	172:65be27845400	1685
AnnaBridge	172:65be27845400	1686	/**
AnnaBridge	172:65be27845400	1687	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	172:65be27845400	1688	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	172:65be27845400	1689	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1690	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1691	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	172:65be27845400	1692	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	172:65be27845400	1693	*/
AnnaBridge	172:65be27845400	1694	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1695	{
AnnaBridge	172:65be27845400	1696	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	172:65be27845400	1697	}
AnnaBridge	172:65be27845400	1698
AnnaBridge	172:65be27845400	1699	/**
AnnaBridge	172:65be27845400	1700	* @brief Set the lock level to freeze the
AnnaBridge	172:65be27845400	1701	* configuration of several capture/compare parameters.
AnnaBridge	172:65be27845400	1702	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	1703	* the lock mechanism is supported by a timer instance.
AnnaBridge	172:65be27845400	1704	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
AnnaBridge	172:65be27845400	1705	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1706	* @param LockLevel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1707	* @arg @ref LL_TIM_LOCKLEVEL_OFF
AnnaBridge	172:65be27845400	1708	* @arg @ref LL_TIM_LOCKLEVEL_1
AnnaBridge	172:65be27845400	1709	* @arg @ref LL_TIM_LOCKLEVEL_2
AnnaBridge	172:65be27845400	1710	* @arg @ref LL_TIM_LOCKLEVEL_3
AnnaBridge	172:65be27845400	1711	* @retval None
AnnaBridge	172:65be27845400	1712	*/
AnnaBridge	172:65be27845400	1713	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
AnnaBridge	172:65be27845400	1714	{
AnnaBridge	172:65be27845400	1715	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
AnnaBridge	172:65be27845400	1716	}
AnnaBridge	172:65be27845400	1717
AnnaBridge	172:65be27845400	1718	/**
AnnaBridge	172:65be27845400	1719	* @brief Enable capture/compare channels.
AnnaBridge	172:65be27845400	1720	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1721	* CCER CC1NE LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1722	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1723	* CCER CC2NE LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1724	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1725	* CCER CC3NE LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1726	* CCER CC4E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1727	* CCER CC5E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1728	* CCER CC6E LL_TIM_CC_EnableChannel
AnnaBridge	172:65be27845400	1729	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1730	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1731	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1732	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	1733	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1734	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	1735	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1736	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	1737	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1738	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1739	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1740	* @retval None
AnnaBridge	172:65be27845400	1741	*/
AnnaBridge	172:65be27845400	1742	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	172:65be27845400	1743	{
AnnaBridge	172:65be27845400	1744	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	172:65be27845400	1745	}
AnnaBridge	172:65be27845400	1746
AnnaBridge	172:65be27845400	1747	/**
AnnaBridge	172:65be27845400	1748	* @brief Disable capture/compare channels.
AnnaBridge	172:65be27845400	1749	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1750	* CCER CC1NE LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1751	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1752	* CCER CC2NE LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1753	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1754	* CCER CC3NE LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1755	* CCER CC4E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1756	* CCER CC5E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1757	* CCER CC6E LL_TIM_CC_DisableChannel
AnnaBridge	172:65be27845400	1758	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1759	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1760	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1761	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	1762	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1763	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	1764	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1765	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	1766	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1767	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1768	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1769	* @retval None
AnnaBridge	172:65be27845400	1770	*/
AnnaBridge	172:65be27845400	1771	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	172:65be27845400	1772	{
AnnaBridge	172:65be27845400	1773	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	172:65be27845400	1774	}
AnnaBridge	172:65be27845400	1775
AnnaBridge	172:65be27845400	1776	/**
AnnaBridge	172:65be27845400	1777	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	172:65be27845400	1778	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1779	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1780	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1781	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1782	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1783	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1784	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1785	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1786	* CCER CC6E LL_TIM_CC_IsEnabledChannel
AnnaBridge	172:65be27845400	1787	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1788	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1789	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1790	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	1791	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1792	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	1793	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1794	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	1795	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1796	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1797	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1798	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1799	*/
AnnaBridge	172:65be27845400	1800	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	172:65be27845400	1801	{
AnnaBridge	172:65be27845400	1802	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1803	}
AnnaBridge	172:65be27845400	1804
AnnaBridge	172:65be27845400	1805	/**
AnnaBridge	172:65be27845400	1806	* @}
AnnaBridge	172:65be27845400	1807	*/
AnnaBridge	172:65be27845400	1808
AnnaBridge	172:65be27845400	1809	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	172:65be27845400	1810	* @{
AnnaBridge	172:65be27845400	1811	*/
AnnaBridge	172:65be27845400	1812	/**
AnnaBridge	172:65be27845400	1813	* @brief Configure an output channel.
AnnaBridge	172:65be27845400	1814	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1815	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1816	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1817	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1818	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1819	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1820	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1821	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1822	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1823	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1824	* CCER CC5P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1825	* CCER CC6P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1826	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1827	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1828	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1829	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1830	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	1831	* CR2 OIS6 LL_TIM_OC_ConfigOutput
AnnaBridge	172:65be27845400	1832	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1833	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1834	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1835	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1836	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1837	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1838	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1839	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1840	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	172:65be27845400	1841	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	172:65be27845400	1842	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	172:65be27845400	1843	* @retval None
AnnaBridge	172:65be27845400	1844	*/
AnnaBridge	172:65be27845400	1845	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	172:65be27845400	1846	{
AnnaBridge	172:65be27845400	1847	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	1848	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	1849	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	1850	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	172:65be27845400	1851	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	1852	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
AnnaBridge	172:65be27845400	1853	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	172:65be27845400	1854	}
AnnaBridge	172:65be27845400	1855
AnnaBridge	172:65be27845400	1856	/**
AnnaBridge	172:65be27845400	1857	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	172:65be27845400	1858	* OCx and OCxN (when relevant) are derived.
AnnaBridge	172:65be27845400	1859	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	1860	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	1861	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	1862	* CCMR2 OC4M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	1863	* CCMR3 OC5M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	1864	* CCMR3 OC6M LL_TIM_OC_SetMode
AnnaBridge	172:65be27845400	1865	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1866	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1867	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1868	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1869	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1870	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1871	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1872	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1873	* @param Mode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1874	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	172:65be27845400	1875	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	172:65be27845400	1876	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	172:65be27845400	1877	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	172:65be27845400	1878	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	172:65be27845400	1879	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	172:65be27845400	1880	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	172:65be27845400	1881	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	172:65be27845400	1882	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	172:65be27845400	1883	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	172:65be27845400	1884	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	172:65be27845400	1885	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	172:65be27845400	1886	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	172:65be27845400	1887	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	172:65be27845400	1888	* @retval None
AnnaBridge	172:65be27845400	1889	*/
AnnaBridge	172:65be27845400	1890	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	172:65be27845400	1891	{
AnnaBridge	172:65be27845400	1892	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	1893	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	1894	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	172:65be27845400	1895	}
AnnaBridge	172:65be27845400	1896
AnnaBridge	172:65be27845400	1897	/**
AnnaBridge	172:65be27845400	1898	* @brief Get the output compare mode of an output channel.
AnnaBridge	172:65be27845400	1899	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	1900	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	1901	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	1902	* CCMR2 OC4M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	1903	* CCMR3 OC5M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	1904	* CCMR3 OC6M LL_TIM_OC_GetMode
AnnaBridge	172:65be27845400	1905	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1906	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1907	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1908	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1909	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1910	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1911	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1912	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1913	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1914	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	172:65be27845400	1915	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	172:65be27845400	1916	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	172:65be27845400	1917	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	172:65be27845400	1918	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	172:65be27845400	1919	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	172:65be27845400	1920	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	172:65be27845400	1921	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	172:65be27845400	1922	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	172:65be27845400	1923	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	172:65be27845400	1924	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	172:65be27845400	1925	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	172:65be27845400	1926	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	172:65be27845400	1927	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	172:65be27845400	1928	*/
AnnaBridge	172:65be27845400	1929	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	1930	{
AnnaBridge	172:65be27845400	1931	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	1932	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	1933	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	172:65be27845400	1934	}
AnnaBridge	172:65be27845400	1935
AnnaBridge	172:65be27845400	1936	/**
AnnaBridge	172:65be27845400	1937	* @brief Set the polarity of an output channel.
AnnaBridge	172:65be27845400	1938	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1939	* CCER CC1NP LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1940	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1941	* CCER CC2NP LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1942	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1943	* CCER CC3NP LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1944	* CCER CC4P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1945	* CCER CC5P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	1946	* CCER CC6P LL_TIM_OC_SetPolarity
AnnaBridge	172:65be27845400	1947	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1948	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1949	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1950	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	1951	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1952	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	1953	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1954	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	1955	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1956	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1957	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1958	* @param Polarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1959	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	172:65be27845400	1960	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	172:65be27845400	1961	* @retval None
AnnaBridge	172:65be27845400	1962	*/
AnnaBridge	172:65be27845400	1963	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	172:65be27845400	1964	{
AnnaBridge	172:65be27845400	1965	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	1966	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	1967	}
AnnaBridge	172:65be27845400	1968
AnnaBridge	172:65be27845400	1969	/**
AnnaBridge	172:65be27845400	1970	* @brief Get the polarity of an output channel.
AnnaBridge	172:65be27845400	1971	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1972	* CCER CC1NP LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1973	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1974	* CCER CC2NP LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1975	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1976	* CCER CC3NP LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1977	* CCER CC4P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1978	* CCER CC5P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	1979	* CCER CC6P LL_TIM_OC_GetPolarity
AnnaBridge	172:65be27845400	1980	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1981	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1982	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1983	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	1984	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1985	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	1986	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1987	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	1988	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1989	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1990	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1991	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1992	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	172:65be27845400	1993	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	172:65be27845400	1994	*/
AnnaBridge	172:65be27845400	1995	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	1996	{
AnnaBridge	172:65be27845400	1997	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	1998	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	1999	}
AnnaBridge	172:65be27845400	2000
AnnaBridge	172:65be27845400	2001	/**
AnnaBridge	172:65be27845400	2002	* @brief Set the IDLE state of an output channel
AnnaBridge	172:65be27845400	2003	* @note This function is significant only for the timer instances
AnnaBridge	172:65be27845400	2004	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
AnnaBridge	172:65be27845400	2005	* can be used to check whether or not a timer instance provides
AnnaBridge	172:65be27845400	2006	* a break input.
AnnaBridge	172:65be27845400	2007	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2008	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2009	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2010	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2011	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2012	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2013	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2014	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2015	* CR2 OIS6 LL_TIM_OC_SetIdleState
AnnaBridge	172:65be27845400	2016	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2017	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2018	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2019	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	2020	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2021	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	2022	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2023	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	2024	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2025	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2026	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2027	* @param IdleState This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2028	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	172:65be27845400	2029	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	172:65be27845400	2030	* @retval None
AnnaBridge	172:65be27845400	2031	*/
AnnaBridge	172:65be27845400	2032	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
AnnaBridge	172:65be27845400	2033	{
AnnaBridge	172:65be27845400	2034	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2035	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	172:65be27845400	2036	}
AnnaBridge	172:65be27845400	2037
AnnaBridge	172:65be27845400	2038	/**
AnnaBridge	172:65be27845400	2039	* @brief Get the IDLE state of an output channel
AnnaBridge	172:65be27845400	2040	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2041	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2042	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2043	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2044	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2045	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2046	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2047	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2048	* CR2 OIS6 LL_TIM_OC_GetIdleState
AnnaBridge	172:65be27845400	2049	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2050	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2051	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2052	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	2053	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2054	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	2055	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2056	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	2057	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2058	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2059	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2060	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2061	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	172:65be27845400	2062	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	172:65be27845400	2063	*/
AnnaBridge	172:65be27845400	2064	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2065	{
AnnaBridge	172:65be27845400	2066	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2067	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
AnnaBridge	172:65be27845400	2068	}
AnnaBridge	172:65be27845400	2069
AnnaBridge	172:65be27845400	2070	/**
AnnaBridge	172:65be27845400	2071	* @brief Enable fast mode for the output channel.
AnnaBridge	172:65be27845400	2072	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	172:65be27845400	2073	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2074	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2075	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2076	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2077	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2078	* CCMR3 OC6FE LL_TIM_OC_EnableFast
AnnaBridge	172:65be27845400	2079	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2080	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2081	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2082	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2083	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2084	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2085	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2086	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2087	* @retval None
AnnaBridge	172:65be27845400	2088	*/
AnnaBridge	172:65be27845400	2089	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2090	{
AnnaBridge	172:65be27845400	2091	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2092	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2093	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2094
AnnaBridge	172:65be27845400	2095	}
AnnaBridge	172:65be27845400	2096
AnnaBridge	172:65be27845400	2097	/**
AnnaBridge	172:65be27845400	2098	* @brief Disable fast mode for the output channel.
AnnaBridge	172:65be27845400	2099	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2100	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2101	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2102	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2103	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2104	* CCMR3 OC6FE LL_TIM_OC_DisableFast
AnnaBridge	172:65be27845400	2105	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2106	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2107	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2108	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2109	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2110	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2111	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2112	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2113	* @retval None
AnnaBridge	172:65be27845400	2114	*/
AnnaBridge	172:65be27845400	2115	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2116	{
AnnaBridge	172:65be27845400	2117	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2118	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2119	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2120
AnnaBridge	172:65be27845400	2121	}
AnnaBridge	172:65be27845400	2122
AnnaBridge	172:65be27845400	2123	/**
AnnaBridge	172:65be27845400	2124	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	172:65be27845400	2125	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2126	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2127	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2128	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2129	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2130	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
AnnaBridge	172:65be27845400	2131	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2132	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2133	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2134	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2135	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2136	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2137	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2138	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2139	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2140	*/
AnnaBridge	172:65be27845400	2141	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2142	{
AnnaBridge	172:65be27845400	2143	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2144	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2145	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	172:65be27845400	2146	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2147	}
AnnaBridge	172:65be27845400	2148
AnnaBridge	172:65be27845400	2149	/**
AnnaBridge	172:65be27845400	2150	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	172:65be27845400	2151	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2152	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2153	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2154	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2155	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2156	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
AnnaBridge	172:65be27845400	2157	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2158	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2159	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2160	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2161	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2162	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2163	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2164	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2165	* @retval None
AnnaBridge	172:65be27845400	2166	*/
AnnaBridge	172:65be27845400	2167	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2168	{
AnnaBridge	172:65be27845400	2169	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2170	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2171	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2172	}
AnnaBridge	172:65be27845400	2173
AnnaBridge	172:65be27845400	2174	/**
AnnaBridge	172:65be27845400	2175	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	172:65be27845400	2176	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2177	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2178	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2179	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2180	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2181	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
AnnaBridge	172:65be27845400	2182	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2183	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2184	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2185	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2186	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2187	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2188	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2189	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2190	* @retval None
AnnaBridge	172:65be27845400	2191	*/
AnnaBridge	172:65be27845400	2192	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2193	{
AnnaBridge	172:65be27845400	2194	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2195	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2196	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2197	}
AnnaBridge	172:65be27845400	2198
AnnaBridge	172:65be27845400	2199	/**
AnnaBridge	172:65be27845400	2200	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	172:65be27845400	2201	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2202	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2203	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2204	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2205	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2206	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
AnnaBridge	172:65be27845400	2207	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2208	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2209	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2210	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2211	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2212	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2213	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2214	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2215	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2216	*/
AnnaBridge	172:65be27845400	2217	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2218	{
AnnaBridge	172:65be27845400	2219	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2220	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2221	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	172:65be27845400	2222	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2223	}
AnnaBridge	172:65be27845400	2224
AnnaBridge	172:65be27845400	2225	/**
AnnaBridge	172:65be27845400	2226	* @brief Enable clearing the output channel on an external event.
AnnaBridge	172:65be27845400	2227	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	172:65be27845400	2228	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	2229	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	172:65be27845400	2230	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2231	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2232	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2233	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2234	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2235	* CCMR3 OC6CE LL_TIM_OC_EnableClear
AnnaBridge	172:65be27845400	2236	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2237	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2238	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2239	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2240	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2241	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2242	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2243	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2244	* @retval None
AnnaBridge	172:65be27845400	2245	*/
AnnaBridge	172:65be27845400	2246	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2247	{
AnnaBridge	172:65be27845400	2248	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2249	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2250	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2251	}
AnnaBridge	172:65be27845400	2252
AnnaBridge	172:65be27845400	2253	/**
AnnaBridge	172:65be27845400	2254	* @brief Disable clearing the output channel on an external event.
AnnaBridge	172:65be27845400	2255	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	2256	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	172:65be27845400	2257	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2258	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2259	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2260	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2261	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2262	* CCMR3 OC6CE LL_TIM_OC_DisableClear
AnnaBridge	172:65be27845400	2263	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2264	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2265	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2266	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2267	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2268	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2269	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2270	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2271	* @retval None
AnnaBridge	172:65be27845400	2272	*/
AnnaBridge	172:65be27845400	2273	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2274	{
AnnaBridge	172:65be27845400	2275	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2276	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2277	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2278	}
AnnaBridge	172:65be27845400	2279
AnnaBridge	172:65be27845400	2280	/**
AnnaBridge	172:65be27845400	2281	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	172:65be27845400	2282	* @note This function enables clearing the output channel on an external event.
AnnaBridge	172:65be27845400	2283	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	172:65be27845400	2284	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	2285	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	172:65be27845400	2286	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2287	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2288	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2289	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2290	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2291	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
AnnaBridge	172:65be27845400	2292	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2293	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2294	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2295	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2296	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2297	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2298	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2299	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2300	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2301	*/
AnnaBridge	172:65be27845400	2302	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2303	{
AnnaBridge	172:65be27845400	2304	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2305	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2306	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	172:65be27845400	2307	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2308	}
AnnaBridge	172:65be27845400	2309
AnnaBridge	172:65be27845400	2310	/**
AnnaBridge	172:65be27845400	2311	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
AnnaBridge	172:65be27845400	2312	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2313	* dead-time insertion feature is supported by a timer instance.
AnnaBridge	172:65be27845400	2314	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
AnnaBridge	172:65be27845400	2315	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
AnnaBridge	172:65be27845400	2316	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2317	* @param DeadTime between Min_Data=0 and Max_Data=255
AnnaBridge	172:65be27845400	2318	* @retval None
AnnaBridge	172:65be27845400	2319	*/
AnnaBridge	172:65be27845400	2320	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
AnnaBridge	172:65be27845400	2321	{
AnnaBridge	172:65be27845400	2322	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
AnnaBridge	172:65be27845400	2323	}
AnnaBridge	172:65be27845400	2324
AnnaBridge	172:65be27845400	2325	/**
AnnaBridge	172:65be27845400	2326	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	172:65be27845400	2327	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2328	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2329	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2330	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2331	* output channel 1 is supported by a timer instance.
AnnaBridge	172:65be27845400	2332	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	172:65be27845400	2333	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2334	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2335	* @retval None
AnnaBridge	172:65be27845400	2336	*/
AnnaBridge	172:65be27845400	2337	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2338	{
AnnaBridge	172:65be27845400	2339	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	172:65be27845400	2340	}
AnnaBridge	172:65be27845400	2341
AnnaBridge	172:65be27845400	2342	/**
AnnaBridge	172:65be27845400	2343	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	172:65be27845400	2344	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2345	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2346	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2347	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2348	* output channel 2 is supported by a timer instance.
AnnaBridge	172:65be27845400	2349	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	172:65be27845400	2350	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2351	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2352	* @retval None
AnnaBridge	172:65be27845400	2353	*/
AnnaBridge	172:65be27845400	2354	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2355	{
AnnaBridge	172:65be27845400	2356	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	172:65be27845400	2357	}
AnnaBridge	172:65be27845400	2358
AnnaBridge	172:65be27845400	2359	/**
AnnaBridge	172:65be27845400	2360	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	172:65be27845400	2361	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2362	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2363	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2364	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2365	* output channel is supported by a timer instance.
AnnaBridge	172:65be27845400	2366	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	172:65be27845400	2367	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2368	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2369	* @retval None
AnnaBridge	172:65be27845400	2370	*/
AnnaBridge	172:65be27845400	2371	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2372	{
AnnaBridge	172:65be27845400	2373	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	172:65be27845400	2374	}
AnnaBridge	172:65be27845400	2375
AnnaBridge	172:65be27845400	2376	/**
AnnaBridge	172:65be27845400	2377	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	172:65be27845400	2378	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2379	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2380	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2381	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2382	* output channel 4 is supported by a timer instance.
AnnaBridge	172:65be27845400	2383	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	172:65be27845400	2384	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2385	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2386	* @retval None
AnnaBridge	172:65be27845400	2387	*/
AnnaBridge	172:65be27845400	2388	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2389	{
AnnaBridge	172:65be27845400	2390	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	172:65be27845400	2391	}
AnnaBridge	172:65be27845400	2392
AnnaBridge	172:65be27845400	2393	/**
AnnaBridge	172:65be27845400	2394	* @brief Set compare value for output channel 5 (TIMx_CCR5).
AnnaBridge	172:65be27845400	2395	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2396	* output channel 5 is supported by a timer instance.
AnnaBridge	172:65be27845400	2397	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
AnnaBridge	172:65be27845400	2398	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2399	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2400	* @retval None
AnnaBridge	172:65be27845400	2401	*/
AnnaBridge	172:65be27845400	2402	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2403	{
AnnaBridge	172:65be27845400	2404	WRITE_REG(TIMx->CCR5, CompareValue);
AnnaBridge	172:65be27845400	2405	}
AnnaBridge	172:65be27845400	2406
AnnaBridge	172:65be27845400	2407	/**
AnnaBridge	172:65be27845400	2408	* @brief Set compare value for output channel 6 (TIMx_CCR6).
AnnaBridge	172:65be27845400	2409	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2410	* output channel 6 is supported by a timer instance.
AnnaBridge	172:65be27845400	2411	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
AnnaBridge	172:65be27845400	2412	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2413	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2414	* @retval None
AnnaBridge	172:65be27845400	2415	*/
AnnaBridge	172:65be27845400	2416	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2417	{
AnnaBridge	172:65be27845400	2418	WRITE_REG(TIMx->CCR6, CompareValue);
AnnaBridge	172:65be27845400	2419	}
AnnaBridge	172:65be27845400	2420
AnnaBridge	172:65be27845400	2421	/**
AnnaBridge	172:65be27845400	2422	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	172:65be27845400	2423	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2424	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2425	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2426	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2427	* output channel 1 is supported by a timer instance.
AnnaBridge	172:65be27845400	2428	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	172:65be27845400	2429	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2430	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2431	*/
AnnaBridge	172:65be27845400	2432	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2433	{
AnnaBridge	172:65be27845400	2434	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	172:65be27845400	2435	}
AnnaBridge	172:65be27845400	2436
AnnaBridge	172:65be27845400	2437	/**
AnnaBridge	172:65be27845400	2438	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	172:65be27845400	2439	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2440	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2441	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2442	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2443	* output channel 2 is supported by a timer instance.
AnnaBridge	172:65be27845400	2444	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	172:65be27845400	2445	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2446	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2447	*/
AnnaBridge	172:65be27845400	2448	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2449	{
AnnaBridge	172:65be27845400	2450	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	172:65be27845400	2451	}
AnnaBridge	172:65be27845400	2452
AnnaBridge	172:65be27845400	2453	/**
AnnaBridge	172:65be27845400	2454	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	172:65be27845400	2455	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2456	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2457	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2458	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2459	* output channel 3 is supported by a timer instance.
AnnaBridge	172:65be27845400	2460	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	172:65be27845400	2461	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2462	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2463	*/
AnnaBridge	172:65be27845400	2464	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2465	{
AnnaBridge	172:65be27845400	2466	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	172:65be27845400	2467	}
AnnaBridge	172:65be27845400	2468
AnnaBridge	172:65be27845400	2469	/**
AnnaBridge	172:65be27845400	2470	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	172:65be27845400	2471	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2472	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2473	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2474	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2475	* output channel 4 is supported by a timer instance.
AnnaBridge	172:65be27845400	2476	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	172:65be27845400	2477	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2478	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2479	*/
AnnaBridge	172:65be27845400	2480	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2481	{
AnnaBridge	172:65be27845400	2482	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	172:65be27845400	2483	}
AnnaBridge	172:65be27845400	2484
AnnaBridge	172:65be27845400	2485	/**
AnnaBridge	172:65be27845400	2486	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
AnnaBridge	172:65be27845400	2487	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2488	* output channel 5 is supported by a timer instance.
AnnaBridge	172:65be27845400	2489	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
AnnaBridge	172:65be27845400	2490	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2491	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2492	*/
AnnaBridge	172:65be27845400	2493	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2494	{
AnnaBridge	172:65be27845400	2495	return (uint32_t)(READ_REG(TIMx->CCR5));
AnnaBridge	172:65be27845400	2496	}
AnnaBridge	172:65be27845400	2497
AnnaBridge	172:65be27845400	2498	/**
AnnaBridge	172:65be27845400	2499	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
AnnaBridge	172:65be27845400	2500	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2501	* output channel 6 is supported by a timer instance.
AnnaBridge	172:65be27845400	2502	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
AnnaBridge	172:65be27845400	2503	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2504	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2505	*/
AnnaBridge	172:65be27845400	2506	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2507	{
AnnaBridge	172:65be27845400	2508	return (uint32_t)(READ_REG(TIMx->CCR6));
AnnaBridge	172:65be27845400	2509	}
AnnaBridge	172:65be27845400	2510
AnnaBridge	172:65be27845400	2511	/**
AnnaBridge	172:65be27845400	2512	* @brief Select on which reference signal the OC5REF is combined to.
AnnaBridge	172:65be27845400	2513	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2514	* whether or not a timer instance supports the combined 3-phase PWM mode.
AnnaBridge	172:65be27845400	2515	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	172:65be27845400	2516	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	172:65be27845400	2517	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
AnnaBridge	172:65be27845400	2518	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2519	* @param GroupCH5 This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2520	* @arg @ref LL_TIM_GROUPCH5_NONE
AnnaBridge	172:65be27845400	2521	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
AnnaBridge	172:65be27845400	2522	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
AnnaBridge	172:65be27845400	2523	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
AnnaBridge	172:65be27845400	2524	* @retval None
AnnaBridge	172:65be27845400	2525	*/
AnnaBridge	172:65be27845400	2526	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
AnnaBridge	172:65be27845400	2527	{
AnnaBridge	172:65be27845400	2528	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
AnnaBridge	172:65be27845400	2529	}
AnnaBridge	172:65be27845400	2530
AnnaBridge	172:65be27845400	2531	/**
AnnaBridge	172:65be27845400	2532	* @}
AnnaBridge	172:65be27845400	2533	*/
AnnaBridge	172:65be27845400	2534
AnnaBridge	172:65be27845400	2535	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	172:65be27845400	2536	* @{
AnnaBridge	172:65be27845400	2537	*/
AnnaBridge	172:65be27845400	2538	/**
AnnaBridge	172:65be27845400	2539	* @brief Configure input channel.
AnnaBridge	172:65be27845400	2540	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2541	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2542	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2543	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2544	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2545	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2546	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2547	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2548	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2549	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2550	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2551	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2552	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2553	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2554	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2555	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2556	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2557	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2558	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2559	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	172:65be27845400	2560	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2561	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2562	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2563	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2564	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2565	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2566	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	172:65be27845400	2567	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	172:65be27845400	2568	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	2569	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	2570	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	172:65be27845400	2571	* @retval None
AnnaBridge	172:65be27845400	2572	*/
AnnaBridge	172:65be27845400	2573	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	172:65be27845400	2574	{
AnnaBridge	172:65be27845400	2575	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2576	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2577	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	172:65be27845400	2578	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2579	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	172:65be27845400	2580	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2581	}
AnnaBridge	172:65be27845400	2582
AnnaBridge	172:65be27845400	2583	/**
AnnaBridge	172:65be27845400	2584	* @brief Set the active input.
AnnaBridge	172:65be27845400	2585	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	172:65be27845400	2586	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	172:65be27845400	2587	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	172:65be27845400	2588	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	172:65be27845400	2589	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2590	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2591	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2592	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2593	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2594	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2595	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2596	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	172:65be27845400	2597	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	172:65be27845400	2598	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	172:65be27845400	2599	* @retval None
AnnaBridge	172:65be27845400	2600	*/
AnnaBridge	172:65be27845400	2601	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	172:65be27845400	2602	{
AnnaBridge	172:65be27845400	2603	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2604	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2605	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2606	}
AnnaBridge	172:65be27845400	2607
AnnaBridge	172:65be27845400	2608	/**
AnnaBridge	172:65be27845400	2609	* @brief Get the current active input.
AnnaBridge	172:65be27845400	2610	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	172:65be27845400	2611	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	172:65be27845400	2612	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	172:65be27845400	2613	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	172:65be27845400	2614	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2615	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2616	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2617	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2618	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2619	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2620	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2621	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	172:65be27845400	2622	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	172:65be27845400	2623	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	172:65be27845400	2624	*/
AnnaBridge	172:65be27845400	2625	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2626	{
AnnaBridge	172:65be27845400	2627	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2628	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2629	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	172:65be27845400	2630	}
AnnaBridge	172:65be27845400	2631
AnnaBridge	172:65be27845400	2632	/**
AnnaBridge	172:65be27845400	2633	* @brief Set the prescaler of input channel.
AnnaBridge	172:65be27845400	2634	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	172:65be27845400	2635	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	172:65be27845400	2636	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	172:65be27845400	2637	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	172:65be27845400	2638	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2639	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2640	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2641	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2642	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2643	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2644	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2645	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	172:65be27845400	2646	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	172:65be27845400	2647	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	172:65be27845400	2648	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	2649	* @retval None
AnnaBridge	172:65be27845400	2650	*/
AnnaBridge	172:65be27845400	2651	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	172:65be27845400	2652	{
AnnaBridge	172:65be27845400	2653	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2654	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2655	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2656	}
AnnaBridge	172:65be27845400	2657
AnnaBridge	172:65be27845400	2658	/**
AnnaBridge	172:65be27845400	2659	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	172:65be27845400	2660	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	172:65be27845400	2661	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	172:65be27845400	2662	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	172:65be27845400	2663	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	172:65be27845400	2664	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2665	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2666	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2667	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2668	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2669	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2670	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2671	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	172:65be27845400	2672	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	172:65be27845400	2673	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	172:65be27845400	2674	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	2675	*/
AnnaBridge	172:65be27845400	2676	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2677	{
AnnaBridge	172:65be27845400	2678	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2679	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2680	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	172:65be27845400	2681	}
AnnaBridge	172:65be27845400	2682
AnnaBridge	172:65be27845400	2683	/**
AnnaBridge	172:65be27845400	2684	* @brief Set the input filter duration.
AnnaBridge	172:65be27845400	2685	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	172:65be27845400	2686	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	172:65be27845400	2687	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	172:65be27845400	2688	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	172:65be27845400	2689	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2690	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2691	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2692	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2693	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2694	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2695	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2696	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	172:65be27845400	2697	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	2698	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	2699	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	2700	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	2701	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	2702	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	2703	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	2704	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	2705	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	2706	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	2707	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	2708	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	2709	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	2710	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	2711	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	2712	* @retval None
AnnaBridge	172:65be27845400	2713	*/
AnnaBridge	172:65be27845400	2714	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	172:65be27845400	2715	{
AnnaBridge	172:65be27845400	2716	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2717	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2718	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2719	}
AnnaBridge	172:65be27845400	2720
AnnaBridge	172:65be27845400	2721	/**
AnnaBridge	172:65be27845400	2722	* @brief Get the input filter duration.
AnnaBridge	172:65be27845400	2723	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	172:65be27845400	2724	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	172:65be27845400	2725	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	172:65be27845400	2726	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	172:65be27845400	2727	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2728	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2729	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2730	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2731	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2732	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2733	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2734	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	172:65be27845400	2735	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	2736	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	2737	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	2738	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	2739	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	2740	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	2741	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	2742	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	2743	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	2744	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	2745	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	2746	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	2747	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	2748	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	2749	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	2750	*/
AnnaBridge	172:65be27845400	2751	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2752	{
AnnaBridge	172:65be27845400	2753	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2754	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2755	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	172:65be27845400	2756	}
AnnaBridge	172:65be27845400	2757
AnnaBridge	172:65be27845400	2758	/**
AnnaBridge	172:65be27845400	2759	* @brief Set the input channel polarity.
AnnaBridge	172:65be27845400	2760	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2761	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2762	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2763	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2764	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2765	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2766	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2767	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	172:65be27845400	2768	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2769	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2770	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2771	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2772	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2773	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2774	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2775	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	172:65be27845400	2776	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	172:65be27845400	2777	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	172:65be27845400	2778	* @retval None
AnnaBridge	172:65be27845400	2779	*/
AnnaBridge	172:65be27845400	2780	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	172:65be27845400	2781	{
AnnaBridge	172:65be27845400	2782	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2783	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	172:65be27845400	2784	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2785	}
AnnaBridge	172:65be27845400	2786
AnnaBridge	172:65be27845400	2787	/**
AnnaBridge	172:65be27845400	2788	* @brief Get the current input channel polarity.
AnnaBridge	172:65be27845400	2789	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	2790	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	2791	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	2792	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	2793	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	2794	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	2795	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	2796	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	172:65be27845400	2797	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2798	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2799	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2800	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2801	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2802	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2803	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2804	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	172:65be27845400	2805	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	172:65be27845400	2806	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	172:65be27845400	2807	*/
AnnaBridge	172:65be27845400	2808	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2809	{
AnnaBridge	172:65be27845400	2810	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2811	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	172:65be27845400	2812	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2813	}
AnnaBridge	172:65be27845400	2814
AnnaBridge	172:65be27845400	2815	/**
AnnaBridge	172:65be27845400	2816	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	172:65be27845400	2817	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2818	* a timer instance provides an XOR input.
AnnaBridge	172:65be27845400	2819	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	172:65be27845400	2820	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2821	* @retval None
AnnaBridge	172:65be27845400	2822	*/
AnnaBridge	172:65be27845400	2823	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2824	{
AnnaBridge	172:65be27845400	2825	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	172:65be27845400	2826	}
AnnaBridge	172:65be27845400	2827
AnnaBridge	172:65be27845400	2828	/**
AnnaBridge	172:65be27845400	2829	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	172:65be27845400	2830	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2831	* a timer instance provides an XOR input.
AnnaBridge	172:65be27845400	2832	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	172:65be27845400	2833	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2834	* @retval None
AnnaBridge	172:65be27845400	2835	*/
AnnaBridge	172:65be27845400	2836	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2837	{
AnnaBridge	172:65be27845400	2838	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	172:65be27845400	2839	}
AnnaBridge	172:65be27845400	2840
AnnaBridge	172:65be27845400	2841	/**
AnnaBridge	172:65be27845400	2842	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	172:65be27845400	2843	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2844	* a timer instance provides an XOR input.
AnnaBridge	172:65be27845400	2845	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	172:65be27845400	2846	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2847	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2848	*/
AnnaBridge	172:65be27845400	2849	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2850	{
AnnaBridge	172:65be27845400	2851	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2852	}
AnnaBridge	172:65be27845400	2853
AnnaBridge	172:65be27845400	2854	/**
AnnaBridge	172:65be27845400	2855	* @brief Get captured value for input channel 1.
AnnaBridge	172:65be27845400	2856	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2857	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2858	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2859	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2860	* input channel 1 is supported by a timer instance.
AnnaBridge	172:65be27845400	2861	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	172:65be27845400	2862	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2863	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2864	*/
AnnaBridge	172:65be27845400	2865	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2866	{
AnnaBridge	172:65be27845400	2867	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	172:65be27845400	2868	}
AnnaBridge	172:65be27845400	2869
AnnaBridge	172:65be27845400	2870	/**
AnnaBridge	172:65be27845400	2871	* @brief Get captured value for input channel 2.
AnnaBridge	172:65be27845400	2872	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2873	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2874	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2875	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2876	* input channel 2 is supported by a timer instance.
AnnaBridge	172:65be27845400	2877	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	172:65be27845400	2878	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2879	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2880	*/
AnnaBridge	172:65be27845400	2881	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2882	{
AnnaBridge	172:65be27845400	2883	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	172:65be27845400	2884	}
AnnaBridge	172:65be27845400	2885
AnnaBridge	172:65be27845400	2886	/**
AnnaBridge	172:65be27845400	2887	* @brief Get captured value for input channel 3.
AnnaBridge	172:65be27845400	2888	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2889	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2890	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2891	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2892	* input channel 3 is supported by a timer instance.
AnnaBridge	172:65be27845400	2893	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	172:65be27845400	2894	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2895	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2896	*/
AnnaBridge	172:65be27845400	2897	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2898	{
AnnaBridge	172:65be27845400	2899	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	172:65be27845400	2900	}
AnnaBridge	172:65be27845400	2901
AnnaBridge	172:65be27845400	2902	/**
AnnaBridge	172:65be27845400	2903	* @brief Get captured value for input channel 4.
AnnaBridge	172:65be27845400	2904	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2905	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2906	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2907	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2908	* input channel 4 is supported by a timer instance.
AnnaBridge	172:65be27845400	2909	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	172:65be27845400	2910	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2911	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2912	*/
AnnaBridge	172:65be27845400	2913	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2914	{
AnnaBridge	172:65be27845400	2915	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	172:65be27845400	2916	}
AnnaBridge	172:65be27845400	2917
AnnaBridge	172:65be27845400	2918	/**
AnnaBridge	172:65be27845400	2919	* @}
AnnaBridge	172:65be27845400	2920	*/
AnnaBridge	172:65be27845400	2921
AnnaBridge	172:65be27845400	2922	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	172:65be27845400	2923	* @{
AnnaBridge	172:65be27845400	2924	*/
AnnaBridge	172:65be27845400	2925	/**
AnnaBridge	172:65be27845400	2926	* @brief Enable external clock mode 2.
AnnaBridge	172:65be27845400	2927	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	172:65be27845400	2928	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2929	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	2930	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	172:65be27845400	2931	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2932	* @retval None
AnnaBridge	172:65be27845400	2933	*/
AnnaBridge	172:65be27845400	2934	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2935	{
AnnaBridge	172:65be27845400	2936	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	172:65be27845400	2937	}
AnnaBridge	172:65be27845400	2938
AnnaBridge	172:65be27845400	2939	/**
AnnaBridge	172:65be27845400	2940	* @brief Disable external clock mode 2.
AnnaBridge	172:65be27845400	2941	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2942	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	2943	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	172:65be27845400	2944	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2945	* @retval None
AnnaBridge	172:65be27845400	2946	*/
AnnaBridge	172:65be27845400	2947	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2948	{
AnnaBridge	172:65be27845400	2949	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	172:65be27845400	2950	}
AnnaBridge	172:65be27845400	2951
AnnaBridge	172:65be27845400	2952	/**
AnnaBridge	172:65be27845400	2953	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	172:65be27845400	2954	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2955	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	2956	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	172:65be27845400	2957	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2958	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2959	*/
AnnaBridge	172:65be27845400	2960	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2961	{
AnnaBridge	172:65be27845400	2962	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	2963	}
AnnaBridge	172:65be27845400	2964
AnnaBridge	172:65be27845400	2965	/**
AnnaBridge	172:65be27845400	2966	* @brief Set the clock source of the counter clock.
AnnaBridge	172:65be27845400	2967	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	172:65be27845400	2968	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	172:65be27845400	2969	* function. This timer input must be configured by calling
AnnaBridge	172:65be27845400	2970	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	172:65be27845400	2971	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2972	* whether or not a timer instance supports external clock mode1.
AnnaBridge	172:65be27845400	2973	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2974	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	2975	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	172:65be27845400	2976	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	172:65be27845400	2977	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2978	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2979	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	172:65be27845400	2980	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	172:65be27845400	2981	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	172:65be27845400	2982	* @retval None
AnnaBridge	172:65be27845400	2983	*/
AnnaBridge	172:65be27845400	2984	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	172:65be27845400	2985	{
AnnaBridge	172:65be27845400	2986	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	172:65be27845400	2987	}
AnnaBridge	172:65be27845400	2988
AnnaBridge	172:65be27845400	2989	/**
AnnaBridge	172:65be27845400	2990	* @brief Set the encoder interface mode.
AnnaBridge	172:65be27845400	2991	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2992	* whether or not a timer instance supports the encoder mode.
AnnaBridge	172:65be27845400	2993	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	172:65be27845400	2994	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2995	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2996	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	172:65be27845400	2997	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	172:65be27845400	2998	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	172:65be27845400	2999	* @retval None
AnnaBridge	172:65be27845400	3000	*/
AnnaBridge	172:65be27845400	3001	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	172:65be27845400	3002	{
AnnaBridge	172:65be27845400	3003	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	172:65be27845400	3004	}
AnnaBridge	172:65be27845400	3005
AnnaBridge	172:65be27845400	3006	/**
AnnaBridge	172:65be27845400	3007	* @}
AnnaBridge	172:65be27845400	3008	*/
AnnaBridge	172:65be27845400	3009
AnnaBridge	172:65be27845400	3010	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	172:65be27845400	3011	* @{
AnnaBridge	172:65be27845400	3012	*/
AnnaBridge	172:65be27845400	3013	/**
AnnaBridge	172:65be27845400	3014	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	172:65be27845400	3015	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3016	* whether or not a timer instance can operate as a master timer.
AnnaBridge	172:65be27845400	3017	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	172:65be27845400	3018	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3019	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3020	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	172:65be27845400	3021	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	172:65be27845400	3022	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	172:65be27845400	3023	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	172:65be27845400	3024	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	172:65be27845400	3025	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	172:65be27845400	3026	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	172:65be27845400	3027	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	172:65be27845400	3028	* @retval None
AnnaBridge	172:65be27845400	3029	*/
AnnaBridge	172:65be27845400	3030	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	172:65be27845400	3031	{
AnnaBridge	172:65be27845400	3032	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	172:65be27845400	3033	}
AnnaBridge	172:65be27845400	3034
AnnaBridge	172:65be27845400	3035	/**
AnnaBridge	172:65be27845400	3036	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
AnnaBridge	172:65be27845400	3037	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3038	* whether or not a timer instance can be used for ADC synchronization.
AnnaBridge	172:65be27845400	3039	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
AnnaBridge	172:65be27845400	3040	* @param TIMx Timer Instance
AnnaBridge	172:65be27845400	3041	* @param ADCSynchronization This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3042	* @arg @ref LL_TIM_TRGO2_RESET
AnnaBridge	172:65be27845400	3043	* @arg @ref LL_TIM_TRGO2_ENABLE
AnnaBridge	172:65be27845400	3044	* @arg @ref LL_TIM_TRGO2_UPDATE
AnnaBridge	172:65be27845400	3045	* @arg @ref LL_TIM_TRGO2_CC1F
AnnaBridge	172:65be27845400	3046	* @arg @ref LL_TIM_TRGO2_OC1
AnnaBridge	172:65be27845400	3047	* @arg @ref LL_TIM_TRGO2_OC2
AnnaBridge	172:65be27845400	3048	* @arg @ref LL_TIM_TRGO2_OC3
AnnaBridge	172:65be27845400	3049	* @arg @ref LL_TIM_TRGO2_OC4
AnnaBridge	172:65be27845400	3050	* @arg @ref LL_TIM_TRGO2_OC5
AnnaBridge	172:65be27845400	3051	* @arg @ref LL_TIM_TRGO2_OC6
AnnaBridge	172:65be27845400	3052	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
AnnaBridge	172:65be27845400	3053	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
AnnaBridge	172:65be27845400	3054	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
AnnaBridge	172:65be27845400	3055	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
AnnaBridge	172:65be27845400	3056	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
AnnaBridge	172:65be27845400	3057	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
AnnaBridge	172:65be27845400	3058	* @retval None
AnnaBridge	172:65be27845400	3059	*/
AnnaBridge	172:65be27845400	3060	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
AnnaBridge	172:65be27845400	3061	{
AnnaBridge	172:65be27845400	3062	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
AnnaBridge	172:65be27845400	3063	}
AnnaBridge	172:65be27845400	3064
AnnaBridge	172:65be27845400	3065	/**
AnnaBridge	172:65be27845400	3066	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	172:65be27845400	3067	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3068	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3069	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	172:65be27845400	3070	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3071	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3072	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	172:65be27845400	3073	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	172:65be27845400	3074	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	172:65be27845400	3075	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	172:65be27845400	3076	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
AnnaBridge	172:65be27845400	3077	* @retval None
AnnaBridge	172:65be27845400	3078	*/
AnnaBridge	172:65be27845400	3079	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	172:65be27845400	3080	{
AnnaBridge	172:65be27845400	3081	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	172:65be27845400	3082	}
AnnaBridge	172:65be27845400	3083
AnnaBridge	172:65be27845400	3084	/**
AnnaBridge	172:65be27845400	3085	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	172:65be27845400	3086	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3087	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3088	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	172:65be27845400	3089	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3090	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3091	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	172:65be27845400	3092	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	172:65be27845400	3093	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	172:65be27845400	3094	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	172:65be27845400	3095	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	172:65be27845400	3096	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	172:65be27845400	3097	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	172:65be27845400	3098	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	172:65be27845400	3099	* @arg @ref LL_TIM_TS_ITR4
AnnaBridge	172:65be27845400	3100	* @arg @ref LL_TIM_TS_ITR5
AnnaBridge	172:65be27845400	3101	* @arg @ref LL_TIM_TS_ITR6
AnnaBridge	172:65be27845400	3102	* @arg @ref LL_TIM_TS_ITR7
AnnaBridge	172:65be27845400	3103	* @arg @ref LL_TIM_TS_ITR8
AnnaBridge	172:65be27845400	3104	* @retval None
AnnaBridge	172:65be27845400	3105	*/
AnnaBridge	172:65be27845400	3106	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	172:65be27845400	3107	{
AnnaBridge	172:65be27845400	3108	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	172:65be27845400	3109	}
AnnaBridge	172:65be27845400	3110
AnnaBridge	172:65be27845400	3111	/**
AnnaBridge	172:65be27845400	3112	* @brief Enable the Master/Slave mode.
AnnaBridge	172:65be27845400	3113	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3114	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3115	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	172:65be27845400	3116	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3117	* @retval None
AnnaBridge	172:65be27845400	3118	*/
AnnaBridge	172:65be27845400	3119	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3120	{
AnnaBridge	172:65be27845400	3121	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	172:65be27845400	3122	}
AnnaBridge	172:65be27845400	3123
AnnaBridge	172:65be27845400	3124	/**
AnnaBridge	172:65be27845400	3125	* @brief Disable the Master/Slave mode.
AnnaBridge	172:65be27845400	3126	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3127	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3128	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	172:65be27845400	3129	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3130	* @retval None
AnnaBridge	172:65be27845400	3131	*/
AnnaBridge	172:65be27845400	3132	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3133	{
AnnaBridge	172:65be27845400	3134	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	172:65be27845400	3135	}
AnnaBridge	172:65be27845400	3136
AnnaBridge	172:65be27845400	3137	/**
AnnaBridge	172:65be27845400	3138	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	172:65be27845400	3139	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3140	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3141	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	172:65be27845400	3142	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3143	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3144	*/
AnnaBridge	172:65be27845400	3145	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3146	{
AnnaBridge	172:65be27845400	3147	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3148	}
AnnaBridge	172:65be27845400	3149
AnnaBridge	172:65be27845400	3150	/**
AnnaBridge	172:65be27845400	3151	* @brief Configure the external trigger (ETR) input.
AnnaBridge	172:65be27845400	3152	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3153	* a timer instance provides an external trigger input.
AnnaBridge	172:65be27845400	3154	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	172:65be27845400	3155	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	172:65be27845400	3156	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	172:65be27845400	3157	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3158	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3159	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	172:65be27845400	3160	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	172:65be27845400	3161	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3162	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	172:65be27845400	3163	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	172:65be27845400	3164	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	172:65be27845400	3165	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	172:65be27845400	3166	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3167	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	172:65be27845400	3168	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	3169	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	3170	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	3171	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	3172	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	3173	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	3174	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	3175	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	3176	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	3177	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	3178	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	3179	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	3180	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	3181	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	3182	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	3183	* @retval None
AnnaBridge	172:65be27845400	3184	*/
AnnaBridge	172:65be27845400	3185	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	172:65be27845400	3186	uint32_t ETRFilter)
AnnaBridge	172:65be27845400	3187	{
AnnaBridge	172:65be27845400	3188	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	172:65be27845400	3189	}
AnnaBridge	172:65be27845400	3190
AnnaBridge	172:65be27845400	3191	/**
AnnaBridge	172:65be27845400	3192	* @}
AnnaBridge	172:65be27845400	3193	*/
AnnaBridge	172:65be27845400	3194
AnnaBridge	172:65be27845400	3195	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
AnnaBridge	172:65be27845400	3196	* @{
AnnaBridge	172:65be27845400	3197	*/
AnnaBridge	172:65be27845400	3198	/**
AnnaBridge	172:65be27845400	3199	* @brief Enable the break function.
AnnaBridge	172:65be27845400	3200	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3201	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3202	* @rmtoll BDTR BKE LL_TIM_EnableBRK
AnnaBridge	172:65be27845400	3203	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3204	* @retval None
AnnaBridge	172:65be27845400	3205	*/
AnnaBridge	172:65be27845400	3206	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3207	{
AnnaBridge	172:65be27845400	3208	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	172:65be27845400	3209	}
AnnaBridge	172:65be27845400	3210
AnnaBridge	172:65be27845400	3211	/**
AnnaBridge	172:65be27845400	3212	* @brief Disable the break function.
AnnaBridge	172:65be27845400	3213	* @rmtoll BDTR BKE LL_TIM_DisableBRK
AnnaBridge	172:65be27845400	3214	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3215	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3216	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3217	* @retval None
AnnaBridge	172:65be27845400	3218	*/
AnnaBridge	172:65be27845400	3219	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3220	{
AnnaBridge	172:65be27845400	3221	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	172:65be27845400	3222	}
AnnaBridge	172:65be27845400	3223
AnnaBridge	172:65be27845400	3224	/**
AnnaBridge	172:65be27845400	3225	* @brief Configure the break input.
AnnaBridge	172:65be27845400	3226	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3227	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3228	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
AnnaBridge	172:65be27845400	3229	* BDTR BKF LL_TIM_ConfigBRK
AnnaBridge	172:65be27845400	3230	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3231	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3232	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	172:65be27845400	3233	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	172:65be27845400	3234	* @param BreakFilter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3235	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
AnnaBridge	172:65be27845400	3236	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	3237	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	3238	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	3239	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	3240	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	3241	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	3242	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	3243	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	3244	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	3245	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	3246	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	3247	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	3248	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	3249	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	3250	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	3251	* @retval None
AnnaBridge	172:65be27845400	3252	*/
AnnaBridge	172:65be27845400	3253	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
AnnaBridge	172:65be27845400	3254	{
AnnaBridge	172:65be27845400	3255	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
AnnaBridge	172:65be27845400	3256	}
AnnaBridge	172:65be27845400	3257
AnnaBridge	172:65be27845400	3258	/**
AnnaBridge	172:65be27845400	3259	* @brief Enable the break 2 function.
AnnaBridge	172:65be27845400	3260	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3261	* a timer instance provides a second break input.
AnnaBridge	172:65be27845400	3262	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
AnnaBridge	172:65be27845400	3263	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3264	* @retval None
AnnaBridge	172:65be27845400	3265	*/
AnnaBridge	172:65be27845400	3266	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3267	{
AnnaBridge	172:65be27845400	3268	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	172:65be27845400	3269	}
AnnaBridge	172:65be27845400	3270
AnnaBridge	172:65be27845400	3271	/**
AnnaBridge	172:65be27845400	3272	* @brief Disable the break 2 function.
AnnaBridge	172:65be27845400	3273	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3274	* a timer instance provides a second break input.
AnnaBridge	172:65be27845400	3275	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
AnnaBridge	172:65be27845400	3276	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3277	* @retval None
AnnaBridge	172:65be27845400	3278	*/
AnnaBridge	172:65be27845400	3279	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3280	{
AnnaBridge	172:65be27845400	3281	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	172:65be27845400	3282	}
AnnaBridge	172:65be27845400	3283
AnnaBridge	172:65be27845400	3284	/**
AnnaBridge	172:65be27845400	3285	* @brief Configure the break 2 input.
AnnaBridge	172:65be27845400	3286	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3287	* a timer instance provides a second break input.
AnnaBridge	172:65be27845400	3288	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
AnnaBridge	172:65be27845400	3289	* BDTR BK2F LL_TIM_ConfigBRK2
AnnaBridge	172:65be27845400	3290	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3291	* @param Break2Polarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3292	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
AnnaBridge	172:65be27845400	3293	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
AnnaBridge	172:65be27845400	3294	* @param Break2Filter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3295	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
AnnaBridge	172:65be27845400	3296	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	3297	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	3298	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	3299	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	3300	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	3301	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	3302	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	3303	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	3304	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	3305	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	3306	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	3307	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	3308	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	3309	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	3310	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	3311	* @retval None
AnnaBridge	172:65be27845400	3312	*/
AnnaBridge	172:65be27845400	3313	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
AnnaBridge	172:65be27845400	3314	{
AnnaBridge	172:65be27845400	3315	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
AnnaBridge	172:65be27845400	3316	}
AnnaBridge	172:65be27845400	3317
AnnaBridge	172:65be27845400	3318	/**
AnnaBridge	172:65be27845400	3319	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
AnnaBridge	172:65be27845400	3320	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3321	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3322	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
AnnaBridge	172:65be27845400	3323	* BDTR OSSR LL_TIM_SetOffStates
AnnaBridge	172:65be27845400	3324	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3325	* @param OffStateIdle This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3326	* @arg @ref LL_TIM_OSSI_DISABLE
AnnaBridge	172:65be27845400	3327	* @arg @ref LL_TIM_OSSI_ENABLE
AnnaBridge	172:65be27845400	3328	* @param OffStateRun This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3329	* @arg @ref LL_TIM_OSSR_DISABLE
AnnaBridge	172:65be27845400	3330	* @arg @ref LL_TIM_OSSR_ENABLE
AnnaBridge	172:65be27845400	3331	* @retval None
AnnaBridge	172:65be27845400	3332	*/
AnnaBridge	172:65be27845400	3333	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
AnnaBridge	172:65be27845400	3334	{
AnnaBridge	172:65be27845400	3335	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
AnnaBridge	172:65be27845400	3336	}
AnnaBridge	172:65be27845400	3337
AnnaBridge	172:65be27845400	3338	/**
AnnaBridge	172:65be27845400	3339	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
AnnaBridge	172:65be27845400	3340	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3341	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3342	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
AnnaBridge	172:65be27845400	3343	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3344	* @retval None
AnnaBridge	172:65be27845400	3345	*/
AnnaBridge	172:65be27845400	3346	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3347	{
AnnaBridge	172:65be27845400	3348	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	172:65be27845400	3349	}
AnnaBridge	172:65be27845400	3350
AnnaBridge	172:65be27845400	3351	/**
AnnaBridge	172:65be27845400	3352	* @brief Disable automatic output (MOE can be set only by software).
AnnaBridge	172:65be27845400	3353	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3354	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3355	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
AnnaBridge	172:65be27845400	3356	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3357	* @retval None
AnnaBridge	172:65be27845400	3358	*/
AnnaBridge	172:65be27845400	3359	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3360	{
AnnaBridge	172:65be27845400	3361	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	172:65be27845400	3362	}
AnnaBridge	172:65be27845400	3363
AnnaBridge	172:65be27845400	3364	/**
AnnaBridge	172:65be27845400	3365	* @brief Indicate whether automatic output is enabled.
AnnaBridge	172:65be27845400	3366	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3367	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3368	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
AnnaBridge	172:65be27845400	3369	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3370	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3371	*/
AnnaBridge	172:65be27845400	3372	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3373	{
AnnaBridge	172:65be27845400	3374	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3375	}
AnnaBridge	172:65be27845400	3376
AnnaBridge	172:65be27845400	3377	/**
AnnaBridge	172:65be27845400	3378	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
AnnaBridge	172:65be27845400	3379	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	172:65be27845400	3380	* software and is reset in case of break or break2 event
AnnaBridge	172:65be27845400	3381	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3382	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3383	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
AnnaBridge	172:65be27845400	3384	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3385	* @retval None
AnnaBridge	172:65be27845400	3386	*/
AnnaBridge	172:65be27845400	3387	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3388	{
AnnaBridge	172:65be27845400	3389	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	172:65be27845400	3390	}
AnnaBridge	172:65be27845400	3391
AnnaBridge	172:65be27845400	3392	/**
AnnaBridge	172:65be27845400	3393	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
AnnaBridge	172:65be27845400	3394	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	172:65be27845400	3395	* software and is reset in case of break or break2 event.
AnnaBridge	172:65be27845400	3396	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3397	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3398	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
AnnaBridge	172:65be27845400	3399	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3400	* @retval None
AnnaBridge	172:65be27845400	3401	*/
AnnaBridge	172:65be27845400	3402	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3403	{
AnnaBridge	172:65be27845400	3404	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	172:65be27845400	3405	}
AnnaBridge	172:65be27845400	3406
AnnaBridge	172:65be27845400	3407	/**
AnnaBridge	172:65be27845400	3408	* @brief Indicates whether outputs are enabled.
AnnaBridge	172:65be27845400	3409	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3410	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3411	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
AnnaBridge	172:65be27845400	3412	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3413	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3414	*/
AnnaBridge	172:65be27845400	3415	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3416	{
AnnaBridge	172:65be27845400	3417	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3418	}
AnnaBridge	172:65be27845400	3419
AnnaBridge	172:65be27845400	3420	#if defined(TIM_BREAK_INPUT_SUPPORT)
AnnaBridge	172:65be27845400	3421	/**
AnnaBridge	172:65be27845400	3422	* @brief Enable the signals connected to the designated timer break input.
AnnaBridge	172:65be27845400	3423	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	3424	* or not a timer instance allows for break input selection.
AnnaBridge	172:65be27845400	3425	* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3426	* AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3427	* AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3428	* AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3429	* AF2 BK2INE LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3430	* AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3431	* AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3432	* AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
AnnaBridge	172:65be27845400	3433	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3434	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3435	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	172:65be27845400	3436	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	172:65be27845400	3437	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3438	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	172:65be27845400	3439	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	172:65be27845400	3440	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	172:65be27845400	3441	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	172:65be27845400	3442	* @retval None
AnnaBridge	172:65be27845400	3443	*/
AnnaBridge	172:65be27845400	3444	__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
AnnaBridge	172:65be27845400	3445	{
AnnaBridge	172:65be27845400	3446	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
AnnaBridge	172:65be27845400	3447	SET_BIT(*pReg, Source);
AnnaBridge	172:65be27845400	3448	}
AnnaBridge	172:65be27845400	3449
AnnaBridge	172:65be27845400	3450	/**
AnnaBridge	172:65be27845400	3451	* @brief Disable the signals connected to the designated timer break input.
AnnaBridge	172:65be27845400	3452	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	3453	* or not a timer instance allows for break input selection.
AnnaBridge	172:65be27845400	3454	* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3455	* AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3456	* AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3457	* AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3458	* AF2 BK2INE LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3459	* AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3460	* AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3461	* AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
AnnaBridge	172:65be27845400	3462	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3463	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3464	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	172:65be27845400	3465	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	172:65be27845400	3466	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3467	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	172:65be27845400	3468	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	172:65be27845400	3469	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	172:65be27845400	3470	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	172:65be27845400	3471	* @retval None
AnnaBridge	172:65be27845400	3472	*/
AnnaBridge	172:65be27845400	3473	__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
AnnaBridge	172:65be27845400	3474	{
AnnaBridge	172:65be27845400	3475	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
AnnaBridge	172:65be27845400	3476	CLEAR_BIT(*pReg, Source);
AnnaBridge	172:65be27845400	3477	}
AnnaBridge	172:65be27845400	3478
AnnaBridge	172:65be27845400	3479	/**
AnnaBridge	172:65be27845400	3480	* @brief Set the polarity of the break signal for the timer break input.
AnnaBridge	172:65be27845400	3481	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	3482	* or not a timer instance allows for break input selection.
AnnaBridge	172:65be27845400	3483	* @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3484	* AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3485	* AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3486	* AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3487	* AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3488	* AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
AnnaBridge	172:65be27845400	3489	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3490	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3491	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	172:65be27845400	3492	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	172:65be27845400	3493	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3494	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	172:65be27845400	3495	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	172:65be27845400	3496	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	172:65be27845400	3497	* @param Polarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3498	* @arg @ref LL_TIM_BKIN_POLARITY_LOW
AnnaBridge	172:65be27845400	3499	* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
AnnaBridge	172:65be27845400	3500	* @retval None
AnnaBridge	172:65be27845400	3501	*/
AnnaBridge	172:65be27845400	3502	__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
AnnaBridge	172:65be27845400	3503	uint32_t Polarity)
AnnaBridge	172:65be27845400	3504	{
AnnaBridge	172:65be27845400	3505	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
AnnaBridge	172:65be27845400	3506	MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
AnnaBridge	172:65be27845400	3507	}
AnnaBridge	172:65be27845400	3508	#endif /* TIM_BREAK_INPUT_SUPPORT */
AnnaBridge	172:65be27845400	3509	/**
AnnaBridge	172:65be27845400	3510	* @}
AnnaBridge	172:65be27845400	3511	*/
AnnaBridge	172:65be27845400	3512
AnnaBridge	172:65be27845400	3513	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	172:65be27845400	3514	* @{
AnnaBridge	172:65be27845400	3515	*/
AnnaBridge	172:65be27845400	3516	/**
AnnaBridge	172:65be27845400	3517	* @brief Configures the timer DMA burst feature.
AnnaBridge	172:65be27845400	3518	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	172:65be27845400	3519	* not a timer instance supports the DMA burst mode.
AnnaBridge	172:65be27845400	3520	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	172:65be27845400	3521	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	172:65be27845400	3522	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3523	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3524	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	172:65be27845400	3525	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	172:65be27845400	3526	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	172:65be27845400	3527	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	172:65be27845400	3528	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	172:65be27845400	3529	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	172:65be27845400	3530	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	172:65be27845400	3531	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	172:65be27845400	3532	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	172:65be27845400	3533	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	172:65be27845400	3534	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	172:65be27845400	3535	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	172:65be27845400	3536	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	172:65be27845400	3537	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	172:65be27845400	3538	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	172:65be27845400	3539	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	172:65be27845400	3540	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	172:65be27845400	3541	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	172:65be27845400	3542	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
AnnaBridge	172:65be27845400	3543	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
AnnaBridge	172:65be27845400	3544	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
AnnaBridge	172:65be27845400	3545	* @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
AnnaBridge	172:65be27845400	3546	* @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
AnnaBridge	172:65be27845400	3547	* @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
AnnaBridge	172:65be27845400	3548	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3549	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	172:65be27845400	3550	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	172:65be27845400	3551	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	172:65be27845400	3552	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	172:65be27845400	3553	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	172:65be27845400	3554	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	172:65be27845400	3555	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	172:65be27845400	3556	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	172:65be27845400	3557	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	172:65be27845400	3558	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	172:65be27845400	3559	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	172:65be27845400	3560	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	172:65be27845400	3561	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	172:65be27845400	3562	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	172:65be27845400	3563	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	172:65be27845400	3564	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	172:65be27845400	3565	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	172:65be27845400	3566	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	172:65be27845400	3567	* @retval None
AnnaBridge	172:65be27845400	3568	*/
AnnaBridge	172:65be27845400	3569	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	172:65be27845400	3570	{
AnnaBridge	172:65be27845400	3571	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
AnnaBridge	172:65be27845400	3572	}
AnnaBridge	172:65be27845400	3573
AnnaBridge	172:65be27845400	3574	/**
AnnaBridge	172:65be27845400	3575	* @}
AnnaBridge	172:65be27845400	3576	*/
AnnaBridge	172:65be27845400	3577
AnnaBridge	172:65be27845400	3578	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	172:65be27845400	3579	* @{
AnnaBridge	172:65be27845400	3580	*/
AnnaBridge	172:65be27845400	3581	/**
AnnaBridge	172:65be27845400	3582	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	172:65be27845400	3583	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3584	* a some timer inputs can be remapped.
AnnaBridge	172:65be27845400	3585	* @retval None
AnnaBridge	172:65be27845400	3586	*/
AnnaBridge	172:65be27845400	3587	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
AnnaBridge	172:65be27845400	3588	{
AnnaBridge	172:65be27845400	3589	MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL \| TIM_TISEL_TI2SEL \| TIM_TISEL_TI3SEL \| TIM_TISEL_TI4SEL), Remap);
AnnaBridge	172:65be27845400	3590	}
AnnaBridge	172:65be27845400	3591
AnnaBridge	172:65be27845400	3592	/**
AnnaBridge	172:65be27845400	3593	* @}
AnnaBridge	172:65be27845400	3594	*/
AnnaBridge	172:65be27845400	3595
AnnaBridge	172:65be27845400	3596	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	172:65be27845400	3597	* @{
AnnaBridge	172:65be27845400	3598	*/
AnnaBridge	172:65be27845400	3599	/**
AnnaBridge	172:65be27845400	3600	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	172:65be27845400	3601	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	172:65be27845400	3602	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3603	* @retval None
AnnaBridge	172:65be27845400	3604	*/
AnnaBridge	172:65be27845400	3605	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3606	{
AnnaBridge	172:65be27845400	3607	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	172:65be27845400	3608	}
AnnaBridge	172:65be27845400	3609
AnnaBridge	172:65be27845400	3610	/**
AnnaBridge	172:65be27845400	3611	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	172:65be27845400	3612	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	172:65be27845400	3613	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3614	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3615	*/
AnnaBridge	172:65be27845400	3616	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3617	{
AnnaBridge	172:65be27845400	3618	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3619	}
AnnaBridge	172:65be27845400	3620
AnnaBridge	172:65be27845400	3621	/**
AnnaBridge	172:65be27845400	3622	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	172:65be27845400	3623	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	172:65be27845400	3624	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3625	* @retval None
AnnaBridge	172:65be27845400	3626	*/
AnnaBridge	172:65be27845400	3627	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3628	{
AnnaBridge	172:65be27845400	3629	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	172:65be27845400	3630	}
AnnaBridge	172:65be27845400	3631
AnnaBridge	172:65be27845400	3632	/**
AnnaBridge	172:65be27845400	3633	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	172:65be27845400	3634	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	172:65be27845400	3635	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3636	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3637	*/
AnnaBridge	172:65be27845400	3638	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3639	{
AnnaBridge	172:65be27845400	3640	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3641	}
AnnaBridge	172:65be27845400	3642
AnnaBridge	172:65be27845400	3643	/**
AnnaBridge	172:65be27845400	3644	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	172:65be27845400	3645	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	172:65be27845400	3646	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3647	* @retval None
AnnaBridge	172:65be27845400	3648	*/
AnnaBridge	172:65be27845400	3649	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3650	{
AnnaBridge	172:65be27845400	3651	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	172:65be27845400	3652	}
AnnaBridge	172:65be27845400	3653
AnnaBridge	172:65be27845400	3654	/**
AnnaBridge	172:65be27845400	3655	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	172:65be27845400	3656	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	172:65be27845400	3657	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3658	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3659	*/
AnnaBridge	172:65be27845400	3660	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3661	{
AnnaBridge	172:65be27845400	3662	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3663	}
AnnaBridge	172:65be27845400	3664
AnnaBridge	172:65be27845400	3665	/**
AnnaBridge	172:65be27845400	3666	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	172:65be27845400	3667	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	172:65be27845400	3668	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3669	* @retval None
AnnaBridge	172:65be27845400	3670	*/
AnnaBridge	172:65be27845400	3671	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3672	{
AnnaBridge	172:65be27845400	3673	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	172:65be27845400	3674	}
AnnaBridge	172:65be27845400	3675
AnnaBridge	172:65be27845400	3676	/**
AnnaBridge	172:65be27845400	3677	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	172:65be27845400	3678	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	172:65be27845400	3679	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3680	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3681	*/
AnnaBridge	172:65be27845400	3682	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3683	{
AnnaBridge	172:65be27845400	3684	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3685	}
AnnaBridge	172:65be27845400	3686
AnnaBridge	172:65be27845400	3687	/**
AnnaBridge	172:65be27845400	3688	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	172:65be27845400	3689	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	172:65be27845400	3690	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3691	* @retval None
AnnaBridge	172:65be27845400	3692	*/
AnnaBridge	172:65be27845400	3693	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3694	{
AnnaBridge	172:65be27845400	3695	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	172:65be27845400	3696	}
AnnaBridge	172:65be27845400	3697
AnnaBridge	172:65be27845400	3698	/**
AnnaBridge	172:65be27845400	3699	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	172:65be27845400	3700	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	172:65be27845400	3701	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3702	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3703	*/
AnnaBridge	172:65be27845400	3704	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3705	{
AnnaBridge	172:65be27845400	3706	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3707	}
AnnaBridge	172:65be27845400	3708
AnnaBridge	172:65be27845400	3709	/**
AnnaBridge	172:65be27845400	3710	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
AnnaBridge	172:65be27845400	3711	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
AnnaBridge	172:65be27845400	3712	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3713	* @retval None
AnnaBridge	172:65be27845400	3714	*/
AnnaBridge	172:65be27845400	3715	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3716	{
AnnaBridge	172:65be27845400	3717	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
AnnaBridge	172:65be27845400	3718	}
AnnaBridge	172:65be27845400	3719
AnnaBridge	172:65be27845400	3720	/**
AnnaBridge	172:65be27845400	3721	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
AnnaBridge	172:65be27845400	3722	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
AnnaBridge	172:65be27845400	3723	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3724	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3725	*/
AnnaBridge	172:65be27845400	3726	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3727	{
AnnaBridge	172:65be27845400	3728	return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3729	}
AnnaBridge	172:65be27845400	3730
AnnaBridge	172:65be27845400	3731	/**
AnnaBridge	172:65be27845400	3732	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
AnnaBridge	172:65be27845400	3733	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
AnnaBridge	172:65be27845400	3734	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3735	* @retval None
AnnaBridge	172:65be27845400	3736	*/
AnnaBridge	172:65be27845400	3737	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3738	{
AnnaBridge	172:65be27845400	3739	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
AnnaBridge	172:65be27845400	3740	}
AnnaBridge	172:65be27845400	3741
AnnaBridge	172:65be27845400	3742	/**
AnnaBridge	172:65be27845400	3743	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
AnnaBridge	172:65be27845400	3744	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
AnnaBridge	172:65be27845400	3745	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3746	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3747	*/
AnnaBridge	172:65be27845400	3748	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3749	{
AnnaBridge	172:65be27845400	3750	return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3751	}
AnnaBridge	172:65be27845400	3752
AnnaBridge	172:65be27845400	3753	/**
AnnaBridge	172:65be27845400	3754	* @brief Clear the commutation interrupt flag (COMIF).
AnnaBridge	172:65be27845400	3755	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
AnnaBridge	172:65be27845400	3756	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3757	* @retval None
AnnaBridge	172:65be27845400	3758	*/
AnnaBridge	172:65be27845400	3759	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3760	{
AnnaBridge	172:65be27845400	3761	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
AnnaBridge	172:65be27845400	3762	}
AnnaBridge	172:65be27845400	3763
AnnaBridge	172:65be27845400	3764	/**
AnnaBridge	172:65be27845400	3765	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
AnnaBridge	172:65be27845400	3766	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
AnnaBridge	172:65be27845400	3767	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3768	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3769	*/
AnnaBridge	172:65be27845400	3770	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3771	{
AnnaBridge	172:65be27845400	3772	return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3773	}
AnnaBridge	172:65be27845400	3774
AnnaBridge	172:65be27845400	3775	/**
AnnaBridge	172:65be27845400	3776	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	172:65be27845400	3777	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	172:65be27845400	3778	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3779	* @retval None
AnnaBridge	172:65be27845400	3780	*/
AnnaBridge	172:65be27845400	3781	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3782	{
AnnaBridge	172:65be27845400	3783	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	172:65be27845400	3784	}
AnnaBridge	172:65be27845400	3785
AnnaBridge	172:65be27845400	3786	/**
AnnaBridge	172:65be27845400	3787	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	172:65be27845400	3788	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	172:65be27845400	3789	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3790	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3791	*/
AnnaBridge	172:65be27845400	3792	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3793	{
AnnaBridge	172:65be27845400	3794	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3795	}
AnnaBridge	172:65be27845400	3796
AnnaBridge	172:65be27845400	3797	/**
AnnaBridge	172:65be27845400	3798	* @brief Clear the break interrupt flag (BIF).
AnnaBridge	172:65be27845400	3799	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
AnnaBridge	172:65be27845400	3800	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3801	* @retval None
AnnaBridge	172:65be27845400	3802	*/
AnnaBridge	172:65be27845400	3803	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3804	{
AnnaBridge	172:65be27845400	3805	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
AnnaBridge	172:65be27845400	3806	}
AnnaBridge	172:65be27845400	3807
AnnaBridge	172:65be27845400	3808	/**
AnnaBridge	172:65be27845400	3809	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
AnnaBridge	172:65be27845400	3810	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
AnnaBridge	172:65be27845400	3811	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3812	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3813	*/
AnnaBridge	172:65be27845400	3814	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3815	{
AnnaBridge	172:65be27845400	3816	return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3817	}
AnnaBridge	172:65be27845400	3818
AnnaBridge	172:65be27845400	3819	/**
AnnaBridge	172:65be27845400	3820	* @brief Clear the break 2 interrupt flag (B2IF).
AnnaBridge	172:65be27845400	3821	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
AnnaBridge	172:65be27845400	3822	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3823	* @retval None
AnnaBridge	172:65be27845400	3824	*/
AnnaBridge	172:65be27845400	3825	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3826	{
AnnaBridge	172:65be27845400	3827	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
AnnaBridge	172:65be27845400	3828	}
AnnaBridge	172:65be27845400	3829
AnnaBridge	172:65be27845400	3830	/**
AnnaBridge	172:65be27845400	3831	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
AnnaBridge	172:65be27845400	3832	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
AnnaBridge	172:65be27845400	3833	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3834	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3835	*/
AnnaBridge	172:65be27845400	3836	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3837	{
AnnaBridge	172:65be27845400	3838	return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3839	}
AnnaBridge	172:65be27845400	3840
AnnaBridge	172:65be27845400	3841	/**
AnnaBridge	172:65be27845400	3842	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	172:65be27845400	3843	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	172:65be27845400	3844	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3845	* @retval None
AnnaBridge	172:65be27845400	3846	*/
AnnaBridge	172:65be27845400	3847	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3848	{
AnnaBridge	172:65be27845400	3849	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	172:65be27845400	3850	}
AnnaBridge	172:65be27845400	3851
AnnaBridge	172:65be27845400	3852	/**
AnnaBridge	172:65be27845400	3853	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	172:65be27845400	3854	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	172:65be27845400	3855	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3856	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3857	*/
AnnaBridge	172:65be27845400	3858	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3859	{
AnnaBridge	172:65be27845400	3860	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3861	}
AnnaBridge	172:65be27845400	3862
AnnaBridge	172:65be27845400	3863	/**
AnnaBridge	172:65be27845400	3864	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	172:65be27845400	3865	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	172:65be27845400	3866	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3867	* @retval None
AnnaBridge	172:65be27845400	3868	*/
AnnaBridge	172:65be27845400	3869	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3870	{
AnnaBridge	172:65be27845400	3871	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	172:65be27845400	3872	}
AnnaBridge	172:65be27845400	3873
AnnaBridge	172:65be27845400	3874	/**
AnnaBridge	172:65be27845400	3875	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	172:65be27845400	3876	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	172:65be27845400	3877	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3878	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3879	*/
AnnaBridge	172:65be27845400	3880	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3881	{
AnnaBridge	172:65be27845400	3882	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3883	}
AnnaBridge	172:65be27845400	3884
AnnaBridge	172:65be27845400	3885	/**
AnnaBridge	172:65be27845400	3886	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	172:65be27845400	3887	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	172:65be27845400	3888	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3889	* @retval None
AnnaBridge	172:65be27845400	3890	*/
AnnaBridge	172:65be27845400	3891	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3892	{
AnnaBridge	172:65be27845400	3893	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	172:65be27845400	3894	}
AnnaBridge	172:65be27845400	3895
AnnaBridge	172:65be27845400	3896	/**
AnnaBridge	172:65be27845400	3897	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	172:65be27845400	3898	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	172:65be27845400	3899	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3900	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3901	*/
AnnaBridge	172:65be27845400	3902	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3903	{
AnnaBridge	172:65be27845400	3904	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3905	}
AnnaBridge	172:65be27845400	3906
AnnaBridge	172:65be27845400	3907	/**
AnnaBridge	172:65be27845400	3908	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	172:65be27845400	3909	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	172:65be27845400	3910	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3911	* @retval None
AnnaBridge	172:65be27845400	3912	*/
AnnaBridge	172:65be27845400	3913	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3914	{
AnnaBridge	172:65be27845400	3915	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	172:65be27845400	3916	}
AnnaBridge	172:65be27845400	3917
AnnaBridge	172:65be27845400	3918	/**
AnnaBridge	172:65be27845400	3919	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	172:65be27845400	3920	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	172:65be27845400	3921	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3922	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3923	*/
AnnaBridge	172:65be27845400	3924	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3925	{
AnnaBridge	172:65be27845400	3926	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3927	}
AnnaBridge	172:65be27845400	3928
AnnaBridge	172:65be27845400	3929	/**
AnnaBridge	172:65be27845400	3930	* @brief Clear the system break interrupt flag (SBIF).
AnnaBridge	172:65be27845400	3931	* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
AnnaBridge	172:65be27845400	3932	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3933	* @retval None
AnnaBridge	172:65be27845400	3934	*/
AnnaBridge	172:65be27845400	3935	__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3936	{
AnnaBridge	172:65be27845400	3937	WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
AnnaBridge	172:65be27845400	3938	}
AnnaBridge	172:65be27845400	3939
AnnaBridge	172:65be27845400	3940	/**
AnnaBridge	172:65be27845400	3941	* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
AnnaBridge	172:65be27845400	3942	* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
AnnaBridge	172:65be27845400	3943	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3944	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3945	*/
AnnaBridge	172:65be27845400	3946	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3947	{
AnnaBridge	172:65be27845400	3948	return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3949	}
AnnaBridge	172:65be27845400	3950
AnnaBridge	172:65be27845400	3951	/**
AnnaBridge	172:65be27845400	3952	* @}
AnnaBridge	172:65be27845400	3953	*/
AnnaBridge	172:65be27845400	3954
AnnaBridge	172:65be27845400	3955	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	172:65be27845400	3956	* @{
AnnaBridge	172:65be27845400	3957	*/
AnnaBridge	172:65be27845400	3958	/**
AnnaBridge	172:65be27845400	3959	* @brief Enable update interrupt (UIE).
AnnaBridge	172:65be27845400	3960	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	172:65be27845400	3961	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3962	* @retval None
AnnaBridge	172:65be27845400	3963	*/
AnnaBridge	172:65be27845400	3964	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3965	{
AnnaBridge	172:65be27845400	3966	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	172:65be27845400	3967	}
AnnaBridge	172:65be27845400	3968
AnnaBridge	172:65be27845400	3969	/**
AnnaBridge	172:65be27845400	3970	* @brief Disable update interrupt (UIE).
AnnaBridge	172:65be27845400	3971	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	172:65be27845400	3972	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3973	* @retval None
AnnaBridge	172:65be27845400	3974	*/
AnnaBridge	172:65be27845400	3975	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3976	{
AnnaBridge	172:65be27845400	3977	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	172:65be27845400	3978	}
AnnaBridge	172:65be27845400	3979
AnnaBridge	172:65be27845400	3980	/**
AnnaBridge	172:65be27845400	3981	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	172:65be27845400	3982	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	172:65be27845400	3983	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3984	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3985	*/
AnnaBridge	172:65be27845400	3986	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3987	{
AnnaBridge	172:65be27845400	3988	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	3989	}
AnnaBridge	172:65be27845400	3990
AnnaBridge	172:65be27845400	3991	/**
AnnaBridge	172:65be27845400	3992	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	172:65be27845400	3993	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	172:65be27845400	3994	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3995	* @retval None
AnnaBridge	172:65be27845400	3996	*/
AnnaBridge	172:65be27845400	3997	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3998	{
AnnaBridge	172:65be27845400	3999	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	172:65be27845400	4000	}
AnnaBridge	172:65be27845400	4001
AnnaBridge	172:65be27845400	4002	/**
AnnaBridge	172:65be27845400	4003	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	172:65be27845400	4004	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	172:65be27845400	4005	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4006	* @retval None
AnnaBridge	172:65be27845400	4007	*/
AnnaBridge	172:65be27845400	4008	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4009	{
AnnaBridge	172:65be27845400	4010	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	172:65be27845400	4011	}
AnnaBridge	172:65be27845400	4012
AnnaBridge	172:65be27845400	4013	/**
AnnaBridge	172:65be27845400	4014	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	172:65be27845400	4015	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	172:65be27845400	4016	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4017	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4018	*/
AnnaBridge	172:65be27845400	4019	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4020	{
AnnaBridge	172:65be27845400	4021	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4022	}
AnnaBridge	172:65be27845400	4023
AnnaBridge	172:65be27845400	4024	/**
AnnaBridge	172:65be27845400	4025	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	172:65be27845400	4026	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	172:65be27845400	4027	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4028	* @retval None
AnnaBridge	172:65be27845400	4029	*/
AnnaBridge	172:65be27845400	4030	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4031	{
AnnaBridge	172:65be27845400	4032	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	172:65be27845400	4033	}
AnnaBridge	172:65be27845400	4034
AnnaBridge	172:65be27845400	4035	/**
AnnaBridge	172:65be27845400	4036	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	172:65be27845400	4037	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	172:65be27845400	4038	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4039	* @retval None
AnnaBridge	172:65be27845400	4040	*/
AnnaBridge	172:65be27845400	4041	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4042	{
AnnaBridge	172:65be27845400	4043	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	172:65be27845400	4044	}
AnnaBridge	172:65be27845400	4045
AnnaBridge	172:65be27845400	4046	/**
AnnaBridge	172:65be27845400	4047	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	172:65be27845400	4048	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	172:65be27845400	4049	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4050	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4051	*/
AnnaBridge	172:65be27845400	4052	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4053	{
AnnaBridge	172:65be27845400	4054	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4055	}
AnnaBridge	172:65be27845400	4056
AnnaBridge	172:65be27845400	4057	/**
AnnaBridge	172:65be27845400	4058	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	172:65be27845400	4059	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	172:65be27845400	4060	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4061	* @retval None
AnnaBridge	172:65be27845400	4062	*/
AnnaBridge	172:65be27845400	4063	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4064	{
AnnaBridge	172:65be27845400	4065	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	172:65be27845400	4066	}
AnnaBridge	172:65be27845400	4067
AnnaBridge	172:65be27845400	4068	/**
AnnaBridge	172:65be27845400	4069	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	172:65be27845400	4070	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	172:65be27845400	4071	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4072	* @retval None
AnnaBridge	172:65be27845400	4073	*/
AnnaBridge	172:65be27845400	4074	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4075	{
AnnaBridge	172:65be27845400	4076	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	172:65be27845400	4077	}
AnnaBridge	172:65be27845400	4078
AnnaBridge	172:65be27845400	4079	/**
AnnaBridge	172:65be27845400	4080	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	172:65be27845400	4081	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	172:65be27845400	4082	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4083	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4084	*/
AnnaBridge	172:65be27845400	4085	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4086	{
AnnaBridge	172:65be27845400	4087	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4088	}
AnnaBridge	172:65be27845400	4089
AnnaBridge	172:65be27845400	4090	/**
AnnaBridge	172:65be27845400	4091	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	172:65be27845400	4092	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	172:65be27845400	4093	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4094	* @retval None
AnnaBridge	172:65be27845400	4095	*/
AnnaBridge	172:65be27845400	4096	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4097	{
AnnaBridge	172:65be27845400	4098	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	172:65be27845400	4099	}
AnnaBridge	172:65be27845400	4100
AnnaBridge	172:65be27845400	4101	/**
AnnaBridge	172:65be27845400	4102	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	172:65be27845400	4103	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	172:65be27845400	4104	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4105	* @retval None
AnnaBridge	172:65be27845400	4106	*/
AnnaBridge	172:65be27845400	4107	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4108	{
AnnaBridge	172:65be27845400	4109	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	172:65be27845400	4110	}
AnnaBridge	172:65be27845400	4111
AnnaBridge	172:65be27845400	4112	/**
AnnaBridge	172:65be27845400	4113	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	172:65be27845400	4114	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	172:65be27845400	4115	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4116	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4117	*/
AnnaBridge	172:65be27845400	4118	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4119	{
AnnaBridge	172:65be27845400	4120	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4121	}
AnnaBridge	172:65be27845400	4122
AnnaBridge	172:65be27845400	4123	/**
AnnaBridge	172:65be27845400	4124	* @brief Enable commutation interrupt (COMIE).
AnnaBridge	172:65be27845400	4125	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
AnnaBridge	172:65be27845400	4126	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4127	* @retval None
AnnaBridge	172:65be27845400	4128	*/
AnnaBridge	172:65be27845400	4129	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4130	{
AnnaBridge	172:65be27845400	4131	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	172:65be27845400	4132	}
AnnaBridge	172:65be27845400	4133
AnnaBridge	172:65be27845400	4134	/**
AnnaBridge	172:65be27845400	4135	* @brief Disable commutation interrupt (COMIE).
AnnaBridge	172:65be27845400	4136	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
AnnaBridge	172:65be27845400	4137	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4138	* @retval None
AnnaBridge	172:65be27845400	4139	*/
AnnaBridge	172:65be27845400	4140	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4141	{
AnnaBridge	172:65be27845400	4142	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	172:65be27845400	4143	}
AnnaBridge	172:65be27845400	4144
AnnaBridge	172:65be27845400	4145	/**
AnnaBridge	172:65be27845400	4146	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
AnnaBridge	172:65be27845400	4147	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
AnnaBridge	172:65be27845400	4148	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4149	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4150	*/
AnnaBridge	172:65be27845400	4151	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4152	{
AnnaBridge	172:65be27845400	4153	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4154	}
AnnaBridge	172:65be27845400	4155
AnnaBridge	172:65be27845400	4156	/**
AnnaBridge	172:65be27845400	4157	* @brief Enable trigger interrupt (TIE).
AnnaBridge	172:65be27845400	4158	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	172:65be27845400	4159	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4160	* @retval None
AnnaBridge	172:65be27845400	4161	*/
AnnaBridge	172:65be27845400	4162	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4163	{
AnnaBridge	172:65be27845400	4164	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	172:65be27845400	4165	}
AnnaBridge	172:65be27845400	4166
AnnaBridge	172:65be27845400	4167	/**
AnnaBridge	172:65be27845400	4168	* @brief Disable trigger interrupt (TIE).
AnnaBridge	172:65be27845400	4169	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	172:65be27845400	4170	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4171	* @retval None
AnnaBridge	172:65be27845400	4172	*/
AnnaBridge	172:65be27845400	4173	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4174	{
AnnaBridge	172:65be27845400	4175	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	172:65be27845400	4176	}
AnnaBridge	172:65be27845400	4177
AnnaBridge	172:65be27845400	4178	/**
AnnaBridge	172:65be27845400	4179	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	172:65be27845400	4180	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	172:65be27845400	4181	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4182	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4183	*/
AnnaBridge	172:65be27845400	4184	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4185	{
AnnaBridge	172:65be27845400	4186	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4187	}
AnnaBridge	172:65be27845400	4188
AnnaBridge	172:65be27845400	4189	/**
AnnaBridge	172:65be27845400	4190	* @brief Enable break interrupt (BIE).
AnnaBridge	172:65be27845400	4191	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
AnnaBridge	172:65be27845400	4192	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4193	* @retval None
AnnaBridge	172:65be27845400	4194	*/
AnnaBridge	172:65be27845400	4195	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4196	{
AnnaBridge	172:65be27845400	4197	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	172:65be27845400	4198	}
AnnaBridge	172:65be27845400	4199
AnnaBridge	172:65be27845400	4200	/**
AnnaBridge	172:65be27845400	4201	* @brief Disable break interrupt (BIE).
AnnaBridge	172:65be27845400	4202	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
AnnaBridge	172:65be27845400	4203	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4204	* @retval None
AnnaBridge	172:65be27845400	4205	*/
AnnaBridge	172:65be27845400	4206	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4207	{
AnnaBridge	172:65be27845400	4208	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	172:65be27845400	4209	}
AnnaBridge	172:65be27845400	4210
AnnaBridge	172:65be27845400	4211	/**
AnnaBridge	172:65be27845400	4212	* @brief Indicates whether the break interrupt (BIE) is enabled.
AnnaBridge	172:65be27845400	4213	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
AnnaBridge	172:65be27845400	4214	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4215	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4216	*/
AnnaBridge	172:65be27845400	4217	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4218	{
AnnaBridge	172:65be27845400	4219	return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4220	}
AnnaBridge	172:65be27845400	4221
AnnaBridge	172:65be27845400	4222	/**
AnnaBridge	172:65be27845400	4223	* @}
AnnaBridge	172:65be27845400	4224	*/
AnnaBridge	172:65be27845400	4225
AnnaBridge	172:65be27845400	4226	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	172:65be27845400	4227	* @{
AnnaBridge	172:65be27845400	4228	*/
AnnaBridge	172:65be27845400	4229	/**
AnnaBridge	172:65be27845400	4230	* @brief Enable update DMA request (UDE).
AnnaBridge	172:65be27845400	4231	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	172:65be27845400	4232	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4233	* @retval None
AnnaBridge	172:65be27845400	4234	*/
AnnaBridge	172:65be27845400	4235	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4236	{
AnnaBridge	172:65be27845400	4237	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	172:65be27845400	4238	}
AnnaBridge	172:65be27845400	4239
AnnaBridge	172:65be27845400	4240	/**
AnnaBridge	172:65be27845400	4241	* @brief Disable update DMA request (UDE).
AnnaBridge	172:65be27845400	4242	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	172:65be27845400	4243	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4244	* @retval None
AnnaBridge	172:65be27845400	4245	*/
AnnaBridge	172:65be27845400	4246	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4247	{
AnnaBridge	172:65be27845400	4248	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	172:65be27845400	4249	}
AnnaBridge	172:65be27845400	4250
AnnaBridge	172:65be27845400	4251	/**
AnnaBridge	172:65be27845400	4252	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	172:65be27845400	4253	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	172:65be27845400	4254	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4255	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4256	*/
AnnaBridge	172:65be27845400	4257	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4258	{
AnnaBridge	172:65be27845400	4259	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4260	}
AnnaBridge	172:65be27845400	4261
AnnaBridge	172:65be27845400	4262	/**
AnnaBridge	172:65be27845400	4263	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	172:65be27845400	4264	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	172:65be27845400	4265	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4266	* @retval None
AnnaBridge	172:65be27845400	4267	*/
AnnaBridge	172:65be27845400	4268	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4269	{
AnnaBridge	172:65be27845400	4270	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	172:65be27845400	4271	}
AnnaBridge	172:65be27845400	4272
AnnaBridge	172:65be27845400	4273	/**
AnnaBridge	172:65be27845400	4274	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	172:65be27845400	4275	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	172:65be27845400	4276	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4277	* @retval None
AnnaBridge	172:65be27845400	4278	*/
AnnaBridge	172:65be27845400	4279	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4280	{
AnnaBridge	172:65be27845400	4281	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	172:65be27845400	4282	}
AnnaBridge	172:65be27845400	4283
AnnaBridge	172:65be27845400	4284	/**
AnnaBridge	172:65be27845400	4285	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	172:65be27845400	4286	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	172:65be27845400	4287	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4288	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4289	*/
AnnaBridge	172:65be27845400	4290	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4291	{
AnnaBridge	172:65be27845400	4292	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4293	}
AnnaBridge	172:65be27845400	4294
AnnaBridge	172:65be27845400	4295	/**
AnnaBridge	172:65be27845400	4296	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	172:65be27845400	4297	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	172:65be27845400	4298	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4299	* @retval None
AnnaBridge	172:65be27845400	4300	*/
AnnaBridge	172:65be27845400	4301	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4302	{
AnnaBridge	172:65be27845400	4303	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	172:65be27845400	4304	}
AnnaBridge	172:65be27845400	4305
AnnaBridge	172:65be27845400	4306	/**
AnnaBridge	172:65be27845400	4307	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	172:65be27845400	4308	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	172:65be27845400	4309	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4310	* @retval None
AnnaBridge	172:65be27845400	4311	*/
AnnaBridge	172:65be27845400	4312	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4313	{
AnnaBridge	172:65be27845400	4314	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	172:65be27845400	4315	}
AnnaBridge	172:65be27845400	4316
AnnaBridge	172:65be27845400	4317	/**
AnnaBridge	172:65be27845400	4318	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	172:65be27845400	4319	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	172:65be27845400	4320	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4321	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4322	*/
AnnaBridge	172:65be27845400	4323	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4324	{
AnnaBridge	172:65be27845400	4325	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4326	}
AnnaBridge	172:65be27845400	4327
AnnaBridge	172:65be27845400	4328	/**
AnnaBridge	172:65be27845400	4329	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	172:65be27845400	4330	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	172:65be27845400	4331	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4332	* @retval None
AnnaBridge	172:65be27845400	4333	*/
AnnaBridge	172:65be27845400	4334	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4335	{
AnnaBridge	172:65be27845400	4336	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	172:65be27845400	4337	}
AnnaBridge	172:65be27845400	4338
AnnaBridge	172:65be27845400	4339	/**
AnnaBridge	172:65be27845400	4340	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	172:65be27845400	4341	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	172:65be27845400	4342	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4343	* @retval None
AnnaBridge	172:65be27845400	4344	*/
AnnaBridge	172:65be27845400	4345	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4346	{
AnnaBridge	172:65be27845400	4347	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	172:65be27845400	4348	}
AnnaBridge	172:65be27845400	4349
AnnaBridge	172:65be27845400	4350	/**
AnnaBridge	172:65be27845400	4351	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	172:65be27845400	4352	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	172:65be27845400	4353	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4354	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4355	*/
AnnaBridge	172:65be27845400	4356	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4357	{
AnnaBridge	172:65be27845400	4358	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4359	}
AnnaBridge	172:65be27845400	4360
AnnaBridge	172:65be27845400	4361	/**
AnnaBridge	172:65be27845400	4362	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	172:65be27845400	4363	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	172:65be27845400	4364	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4365	* @retval None
AnnaBridge	172:65be27845400	4366	*/
AnnaBridge	172:65be27845400	4367	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4368	{
AnnaBridge	172:65be27845400	4369	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	172:65be27845400	4370	}
AnnaBridge	172:65be27845400	4371
AnnaBridge	172:65be27845400	4372	/**
AnnaBridge	172:65be27845400	4373	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	172:65be27845400	4374	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	172:65be27845400	4375	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4376	* @retval None
AnnaBridge	172:65be27845400	4377	*/
AnnaBridge	172:65be27845400	4378	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4379	{
AnnaBridge	172:65be27845400	4380	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	172:65be27845400	4381	}
AnnaBridge	172:65be27845400	4382
AnnaBridge	172:65be27845400	4383	/**
AnnaBridge	172:65be27845400	4384	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	172:65be27845400	4385	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	172:65be27845400	4386	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4387	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4388	*/
AnnaBridge	172:65be27845400	4389	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4390	{
AnnaBridge	172:65be27845400	4391	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4392	}
AnnaBridge	172:65be27845400	4393
AnnaBridge	172:65be27845400	4394	/**
AnnaBridge	172:65be27845400	4395	* @brief Enable commutation DMA request (COMDE).
AnnaBridge	172:65be27845400	4396	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
AnnaBridge	172:65be27845400	4397	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4398	* @retval None
AnnaBridge	172:65be27845400	4399	*/
AnnaBridge	172:65be27845400	4400	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4401	{
AnnaBridge	172:65be27845400	4402	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	172:65be27845400	4403	}
AnnaBridge	172:65be27845400	4404
AnnaBridge	172:65be27845400	4405	/**
AnnaBridge	172:65be27845400	4406	* @brief Disable commutation DMA request (COMDE).
AnnaBridge	172:65be27845400	4407	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
AnnaBridge	172:65be27845400	4408	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4409	* @retval None
AnnaBridge	172:65be27845400	4410	*/
AnnaBridge	172:65be27845400	4411	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4412	{
AnnaBridge	172:65be27845400	4413	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	172:65be27845400	4414	}
AnnaBridge	172:65be27845400	4415
AnnaBridge	172:65be27845400	4416	/**
AnnaBridge	172:65be27845400	4417	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
AnnaBridge	172:65be27845400	4418	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
AnnaBridge	172:65be27845400	4419	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4420	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4421	*/
AnnaBridge	172:65be27845400	4422	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4423	{
AnnaBridge	172:65be27845400	4424	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4425	}
AnnaBridge	172:65be27845400	4426
AnnaBridge	172:65be27845400	4427	/**
AnnaBridge	172:65be27845400	4428	* @brief Enable trigger interrupt (TDE).
AnnaBridge	172:65be27845400	4429	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	172:65be27845400	4430	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4431	* @retval None
AnnaBridge	172:65be27845400	4432	*/
AnnaBridge	172:65be27845400	4433	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4434	{
AnnaBridge	172:65be27845400	4435	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	172:65be27845400	4436	}
AnnaBridge	172:65be27845400	4437
AnnaBridge	172:65be27845400	4438	/**
AnnaBridge	172:65be27845400	4439	* @brief Disable trigger interrupt (TDE).
AnnaBridge	172:65be27845400	4440	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	172:65be27845400	4441	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4442	* @retval None
AnnaBridge	172:65be27845400	4443	*/
AnnaBridge	172:65be27845400	4444	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4445	{
AnnaBridge	172:65be27845400	4446	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	172:65be27845400	4447	}
AnnaBridge	172:65be27845400	4448
AnnaBridge	172:65be27845400	4449	/**
AnnaBridge	172:65be27845400	4450	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	172:65be27845400	4451	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	172:65be27845400	4452	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4453	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4454	*/
AnnaBridge	172:65be27845400	4455	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4456	{
AnnaBridge	172:65be27845400	4457	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	4458	}
AnnaBridge	172:65be27845400	4459
AnnaBridge	172:65be27845400	4460	/**
AnnaBridge	172:65be27845400	4461	* @}
AnnaBridge	172:65be27845400	4462	*/
AnnaBridge	172:65be27845400	4463
AnnaBridge	172:65be27845400	4464	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	172:65be27845400	4465	* @{
AnnaBridge	172:65be27845400	4466	*/
AnnaBridge	172:65be27845400	4467	/**
AnnaBridge	172:65be27845400	4468	* @brief Generate an update event.
AnnaBridge	172:65be27845400	4469	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	172:65be27845400	4470	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4471	* @retval None
AnnaBridge	172:65be27845400	4472	*/
AnnaBridge	172:65be27845400	4473	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4474	{
AnnaBridge	172:65be27845400	4475	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	172:65be27845400	4476	}
AnnaBridge	172:65be27845400	4477
AnnaBridge	172:65be27845400	4478	/**
AnnaBridge	172:65be27845400	4479	* @brief Generate Capture/Compare 1 event.
AnnaBridge	172:65be27845400	4480	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	172:65be27845400	4481	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4482	* @retval None
AnnaBridge	172:65be27845400	4483	*/
AnnaBridge	172:65be27845400	4484	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4485	{
AnnaBridge	172:65be27845400	4486	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	172:65be27845400	4487	}
AnnaBridge	172:65be27845400	4488
AnnaBridge	172:65be27845400	4489	/**
AnnaBridge	172:65be27845400	4490	* @brief Generate Capture/Compare 2 event.
AnnaBridge	172:65be27845400	4491	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	172:65be27845400	4492	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4493	* @retval None
AnnaBridge	172:65be27845400	4494	*/
AnnaBridge	172:65be27845400	4495	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4496	{
AnnaBridge	172:65be27845400	4497	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	172:65be27845400	4498	}
AnnaBridge	172:65be27845400	4499
AnnaBridge	172:65be27845400	4500	/**
AnnaBridge	172:65be27845400	4501	* @brief Generate Capture/Compare 3 event.
AnnaBridge	172:65be27845400	4502	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	172:65be27845400	4503	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4504	* @retval None
AnnaBridge	172:65be27845400	4505	*/
AnnaBridge	172:65be27845400	4506	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4507	{
AnnaBridge	172:65be27845400	4508	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	172:65be27845400	4509	}
AnnaBridge	172:65be27845400	4510
AnnaBridge	172:65be27845400	4511	/**
AnnaBridge	172:65be27845400	4512	* @brief Generate Capture/Compare 4 event.
AnnaBridge	172:65be27845400	4513	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	172:65be27845400	4514	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4515	* @retval None
AnnaBridge	172:65be27845400	4516	*/
AnnaBridge	172:65be27845400	4517	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4518	{
AnnaBridge	172:65be27845400	4519	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	172:65be27845400	4520	}
AnnaBridge	172:65be27845400	4521
AnnaBridge	172:65be27845400	4522	/**
AnnaBridge	172:65be27845400	4523	* @brief Generate commutation event.
AnnaBridge	172:65be27845400	4524	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
AnnaBridge	172:65be27845400	4525	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4526	* @retval None
AnnaBridge	172:65be27845400	4527	*/
AnnaBridge	172:65be27845400	4528	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4529	{
AnnaBridge	172:65be27845400	4530	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
AnnaBridge	172:65be27845400	4531	}
AnnaBridge	172:65be27845400	4532
AnnaBridge	172:65be27845400	4533	/**
AnnaBridge	172:65be27845400	4534	* @brief Generate trigger event.
AnnaBridge	172:65be27845400	4535	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	172:65be27845400	4536	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4537	* @retval None
AnnaBridge	172:65be27845400	4538	*/
AnnaBridge	172:65be27845400	4539	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4540	{
AnnaBridge	172:65be27845400	4541	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	172:65be27845400	4542	}
AnnaBridge	172:65be27845400	4543
AnnaBridge	172:65be27845400	4544	/**
AnnaBridge	172:65be27845400	4545	* @brief Generate break event.
AnnaBridge	172:65be27845400	4546	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
AnnaBridge	172:65be27845400	4547	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4548	* @retval None
AnnaBridge	172:65be27845400	4549	*/
AnnaBridge	172:65be27845400	4550	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4551	{
AnnaBridge	172:65be27845400	4552	SET_BIT(TIMx->EGR, TIM_EGR_BG);
AnnaBridge	172:65be27845400	4553	}
AnnaBridge	172:65be27845400	4554
AnnaBridge	172:65be27845400	4555	/**
AnnaBridge	172:65be27845400	4556	* @brief Generate break 2 event.
AnnaBridge	172:65be27845400	4557	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
AnnaBridge	172:65be27845400	4558	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4559	* @retval None
AnnaBridge	172:65be27845400	4560	*/
AnnaBridge	172:65be27845400	4561	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4562	{
AnnaBridge	172:65be27845400	4563	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
AnnaBridge	172:65be27845400	4564	}
AnnaBridge	172:65be27845400	4565
AnnaBridge	172:65be27845400	4566	/**
AnnaBridge	172:65be27845400	4567	* @}
AnnaBridge	172:65be27845400	4568	*/
AnnaBridge	172:65be27845400	4569
AnnaBridge	172:65be27845400	4570	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	4571	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	172:65be27845400	4572	* @{
AnnaBridge	172:65be27845400	4573	*/
AnnaBridge	172:65be27845400	4574
AnnaBridge	172:65be27845400	4575	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	172:65be27845400	4576	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	172:65be27845400	4577	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	172:65be27845400	4578	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	172:65be27845400	4579	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	172:65be27845400	4580	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	172:65be27845400	4581	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	172:65be27845400	4582	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	172:65be27845400	4583	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	172:65be27845400	4584	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
AnnaBridge	172:65be27845400	4585	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
AnnaBridge	172:65be27845400	4586	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
AnnaBridge	172:65be27845400	4587	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
AnnaBridge	172:65be27845400	4588	/**
AnnaBridge	172:65be27845400	4589	* @}
AnnaBridge	172:65be27845400	4590	*/
AnnaBridge	172:65be27845400	4591	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	4592
AnnaBridge	172:65be27845400	4593	/**
AnnaBridge	172:65be27845400	4594	* @}
AnnaBridge	172:65be27845400	4595	*/
AnnaBridge	172:65be27845400	4596
AnnaBridge	172:65be27845400	4597	/**
AnnaBridge	172:65be27845400	4598	* @}
AnnaBridge	172:65be27845400	4599	*/
AnnaBridge	172:65be27845400	4600
AnnaBridge	172:65be27845400	4601	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM6 \|\| TIM7 \|\| TIM8 \|\| TIM12 \|\| TIM13 \|\|TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 */
AnnaBridge	172:65be27845400	4602
AnnaBridge	172:65be27845400	4603	/**
AnnaBridge	172:65be27845400	4604	* @}
AnnaBridge	172:65be27845400	4605	*/
AnnaBridge	172:65be27845400	4606
AnnaBridge	172:65be27845400	4607	#ifdef __cplusplus
AnnaBridge	172:65be27845400	4608	}
AnnaBridge	172:65be27845400	4609	#endif
AnnaBridge	172:65be27845400	4610
AnnaBridge	172:65be27845400	4611	#endif /* __STM32H7xx_LL_TIM_H */
AnnaBridge	172:65be27845400	4612	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/