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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_system.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of SYSTEM LL module.
AnnaBridge	172:65be27845400	6	@verbatim
AnnaBridge	172:65be27845400	7	==============================================================================
AnnaBridge	172:65be27845400	8	##### How to use this driver #####
AnnaBridge	172:65be27845400	9	==============================================================================
AnnaBridge	172:65be27845400	10	[..]
AnnaBridge	172:65be27845400	11	The LL SYSTEM driver contains a set of generic APIs that can be
AnnaBridge	172:65be27845400	12	used by user:
AnnaBridge	172:65be27845400	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
AnnaBridge	172:65be27845400	14	(+) Access to DBGCMU registers
AnnaBridge	172:65be27845400	15	(+) Access to SYSCFG registers
AnnaBridge	172:65be27845400	16
AnnaBridge	172:65be27845400	17	@endverbatim
AnnaBridge	172:65be27845400	18	******************************************************************************
AnnaBridge	172:65be27845400	19	* @attention
AnnaBridge	172:65be27845400	20	*
AnnaBridge	172:65be27845400	21	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	22	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	23	*
AnnaBridge	172:65be27845400	24	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	25	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	26	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	27	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	28	*
AnnaBridge	172:65be27845400	29	******************************************************************************
AnnaBridge	172:65be27845400	30	*/
AnnaBridge	172:65be27845400	31
AnnaBridge	172:65be27845400	32	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	33	#ifndef __STM32H7xx_LL_SYSTEM_H
AnnaBridge	172:65be27845400	34	#define __STM32H7xx_LL_SYSTEM_H
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	#ifdef __cplusplus
AnnaBridge	172:65be27845400	37	extern "C" {
AnnaBridge	172:65be27845400	38	#endif
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	41	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	42
AnnaBridge	172:65be27845400	43	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	44	* @{
AnnaBridge	172:65be27845400	45	*/
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
AnnaBridge	172:65be27845400	48
AnnaBridge	172:65be27845400	49	/** @defgroup SYSTEM_LL SYSTEM
AnnaBridge	172:65be27845400	50	* @{
AnnaBridge	172:65be27845400	51	*/
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	54	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	55
AnnaBridge	172:65be27845400	56	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	57	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
AnnaBridge	172:65be27845400	58	* @{
AnnaBridge	172:65be27845400	59	*/
AnnaBridge	172:65be27845400	60	/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
AnnaBridge	172:65be27845400	61	* @{
AnnaBridge	172:65be27845400	62	*/
AnnaBridge	172:65be27845400	63	#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
AnnaBridge	172:65be27845400	64	#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
AnnaBridge	172:65be27845400	65	#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
AnnaBridge	172:65be27845400	66	#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
AnnaBridge	172:65be27845400	67	#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
AnnaBridge	172:65be27845400	68	#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
AnnaBridge	172:65be27845400	69	#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
AnnaBridge	172:65be27845400	70	#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
AnnaBridge	172:65be27845400	71	/**
AnnaBridge	172:65be27845400	72	* @}
AnnaBridge	172:65be27845400	73	*/
AnnaBridge	172:65be27845400	74
AnnaBridge	172:65be27845400	75	/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
AnnaBridge	172:65be27845400	76	* @{
AnnaBridge	172:65be27845400	77	*/
AnnaBridge	172:65be27845400	78	#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
AnnaBridge	172:65be27845400	79	#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
AnnaBridge	172:65be27845400	80	#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
AnnaBridge	172:65be27845400	81	#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
AnnaBridge	172:65be27845400	82	#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
AnnaBridge	172:65be27845400	83	#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
AnnaBridge	172:65be27845400	84	#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
AnnaBridge	172:65be27845400	85	#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
AnnaBridge	172:65be27845400	86	/**
AnnaBridge	172:65be27845400	87	* @}
AnnaBridge	172:65be27845400	88	*/
AnnaBridge	172:65be27845400	89	/**
AnnaBridge	172:65be27845400	90	* @}
AnnaBridge	172:65be27845400	91	*/
AnnaBridge	172:65be27845400	92
AnnaBridge	172:65be27845400	93	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	94
AnnaBridge	172:65be27845400	95	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	96	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	97	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
AnnaBridge	172:65be27845400	98	* @{
AnnaBridge	172:65be27845400	99	*/
AnnaBridge	172:65be27845400	100
AnnaBridge	172:65be27845400	101	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
AnnaBridge	172:65be27845400	102	* @{
AnnaBridge	172:65be27845400	103	*/
AnnaBridge	172:65be27845400	104	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /!< Enable Fast Mode Plus for I2C1 /
AnnaBridge	172:65be27845400	105	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /!< Enable Fast Mode Plus for I2C2 /
AnnaBridge	172:65be27845400	106	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /!< Enable Fast Mode Plus for I2C3 /
AnnaBridge	172:65be27845400	107	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /!< Enable Fast Mode Plus for I2C4 /
AnnaBridge	172:65be27845400	108	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /!< Enable Fast Mode Plus on PB6 /
AnnaBridge	172:65be27845400	109	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /!< Enable Fast Mode Plus on PB7 /
AnnaBridge	172:65be27845400	110	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /!< Enable Fast Mode Plus on PB8 /
AnnaBridge	172:65be27845400	111	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /!< Enable Fast Mode Plus on PB9 /
AnnaBridge	172:65be27845400	112	/**
AnnaBridge	172:65be27845400	113	* @}
AnnaBridge	172:65be27845400	114	*/
AnnaBridge	172:65be27845400	115
AnnaBridge	172:65be27845400	116	/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
AnnaBridge	172:65be27845400	117	* @{
AnnaBridge	172:65be27845400	118	*/
AnnaBridge	172:65be27845400	119	#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /!< I/O analog switch voltage booster enable /
AnnaBridge	172:65be27845400	120	#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /!< PA0 Switch Open /
AnnaBridge	172:65be27845400	121	#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /!< PA1 Switch Open /
AnnaBridge	172:65be27845400	122	#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /!< PC2 Switch Open /
AnnaBridge	172:65be27845400	123	#define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /!< PC3 Switch Open /
AnnaBridge	172:65be27845400	124	/**
AnnaBridge	172:65be27845400	125	* @}
AnnaBridge	172:65be27845400	126	*/
AnnaBridge	172:65be27845400	127
AnnaBridge	172:65be27845400	128	/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
AnnaBridge	172:65be27845400	129	* @{
AnnaBridge	172:65be27845400	130	*/
AnnaBridge	172:65be27845400	131	#define LL_SYSCFG_ETH_MII 0x00000000U /!< ETH Media MII interface /
AnnaBridge	172:65be27845400	132	#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL /!< ETH Media RMII interface /
AnnaBridge	172:65be27845400	133	/**
AnnaBridge	172:65be27845400	134	* @}
AnnaBridge	172:65be27845400	135	*/
AnnaBridge	172:65be27845400	136
AnnaBridge	172:65be27845400	137	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
AnnaBridge	172:65be27845400	138	* @{
AnnaBridge	172:65be27845400	139	*/
AnnaBridge	172:65be27845400	140	#define LL_SYSCFG_EXTI_PORTA 0U /!< EXTI PORT A /
AnnaBridge	172:65be27845400	141	#define LL_SYSCFG_EXTI_PORTB 1U /!< EXTI PORT B /
AnnaBridge	172:65be27845400	142	#define LL_SYSCFG_EXTI_PORTC 2U /!< EXTI PORT C /
AnnaBridge	172:65be27845400	143	#define LL_SYSCFG_EXTI_PORTD 3U /!< EXTI PORT D /
AnnaBridge	172:65be27845400	144	#define LL_SYSCFG_EXTI_PORTE 4U /!< EXTI PORT E /
AnnaBridge	172:65be27845400	145	#define LL_SYSCFG_EXTI_PORTF 5U /!< EXTI PORT F /
AnnaBridge	172:65be27845400	146	#define LL_SYSCFG_EXTI_PORTG 6U /!< EXTI PORT G /
AnnaBridge	172:65be27845400	147	#define LL_SYSCFG_EXTI_PORTH 7U /!< EXTI PORT H /
AnnaBridge	172:65be27845400	148	#define LL_SYSCFG_EXTI_PORTI 8U /!< EXTI PORT I /
AnnaBridge	172:65be27845400	149	#define LL_SYSCFG_EXTI_PORTJ 9U /!< EXTI PORT J /
AnnaBridge	172:65be27845400	150	#define LL_SYSCFG_EXTI_PORTK 10U /!< EXTI PORT k /
AnnaBridge	172:65be27845400	151	/**
AnnaBridge	172:65be27845400	152	* @}
AnnaBridge	172:65be27845400	153	*/
AnnaBridge	172:65be27845400	154
AnnaBridge	172:65be27845400	155	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
AnnaBridge	172:65be27845400	156	* @{
AnnaBridge	172:65be27845400	157	*/
AnnaBridge	172:65be27845400	158	#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
AnnaBridge	172:65be27845400	159	#define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
AnnaBridge	172:65be27845400	160	#define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
AnnaBridge	172:65be27845400	161	#define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
AnnaBridge	172:65be27845400	162	#define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
AnnaBridge	172:65be27845400	163	#define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
AnnaBridge	172:65be27845400	164	#define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
AnnaBridge	172:65be27845400	165	#define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
AnnaBridge	172:65be27845400	166	#define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
AnnaBridge	172:65be27845400	167	#define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
AnnaBridge	172:65be27845400	168	#define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
AnnaBridge	172:65be27845400	169	#define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
AnnaBridge	172:65be27845400	170	#define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
AnnaBridge	172:65be27845400	171	#define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
AnnaBridge	172:65be27845400	172	#define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
AnnaBridge	172:65be27845400	173	#define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
AnnaBridge	172:65be27845400	174	/**
AnnaBridge	172:65be27845400	175	* @}
AnnaBridge	172:65be27845400	176	*/
AnnaBridge	172:65be27845400	177
AnnaBridge	172:65be27845400	178
AnnaBridge	172:65be27845400	179	/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
AnnaBridge	172:65be27845400	180	* @{
AnnaBridge	172:65be27845400	181	*/
AnnaBridge	172:65be27845400	182	#define LL_SYSCFG_CELL_CODE 0U
AnnaBridge	172:65be27845400	183	#define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
AnnaBridge	172:65be27845400	184	/**
AnnaBridge	172:65be27845400	185	* @}
AnnaBridge	172:65be27845400	186	*/
AnnaBridge	172:65be27845400	187
AnnaBridge	172:65be27845400	188	/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
AnnaBridge	172:65be27845400	189	* @{
AnnaBridge	172:65be27845400	190	*/
AnnaBridge	172:65be27845400	191	#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
AnnaBridge	172:65be27845400	192	#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
AnnaBridge	172:65be27845400	193	/**
AnnaBridge	172:65be27845400	194	* @}
AnnaBridge	172:65be27845400	195	*/
AnnaBridge	172:65be27845400	196
AnnaBridge	172:65be27845400	197	/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
AnnaBridge	172:65be27845400	198	* @{
AnnaBridge	172:65be27845400	199	*/
AnnaBridge	172:65be27845400	200	#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
AnnaBridge	172:65be27845400	201	#define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
AnnaBridge	172:65be27845400	202	#define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
AnnaBridge	172:65be27845400	203	#define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
AnnaBridge	172:65be27845400	204	/**
AnnaBridge	172:65be27845400	205	* @}
AnnaBridge	172:65be27845400	206	*/
AnnaBridge	172:65be27845400	207
AnnaBridge	172:65be27845400	208	/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
AnnaBridge	172:65be27845400	209	* @{
AnnaBridge	172:65be27845400	210	*/
AnnaBridge	172:65be27845400	211	#define LL_SYSCFG_LQFP100_PACKAGE 0U
AnnaBridge	172:65be27845400	212	#define LL_SYSCFG_TQFP144_PACKAGE 2U
AnnaBridge	172:65be27845400	213	#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
AnnaBridge	172:65be27845400	214	#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
AnnaBridge	172:65be27845400	215	/**
AnnaBridge	172:65be27845400	216	* @}
AnnaBridge	172:65be27845400	217	*/
AnnaBridge	172:65be27845400	218
AnnaBridge	172:65be27845400	219	/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
AnnaBridge	172:65be27845400	220	* @{
AnnaBridge	172:65be27845400	221	*/
AnnaBridge	172:65be27845400	222	#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
AnnaBridge	172:65be27845400	223	#define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
AnnaBridge	172:65be27845400	224	#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
AnnaBridge	172:65be27845400	225	#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
AnnaBridge	172:65be27845400	226
AnnaBridge	172:65be27845400	227	/**
AnnaBridge	172:65be27845400	228	* @}
AnnaBridge	172:65be27845400	229	*/
AnnaBridge	172:65be27845400	230
AnnaBridge	172:65be27845400	231	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
AnnaBridge	172:65be27845400	232	* @{
AnnaBridge	172:65be27845400	233	*/
AnnaBridge	172:65be27845400	234	#define LL_DBGMCU_TRACE_NONE 0x00000000U /!< TRACE pins not assigned (default state) /
AnnaBridge	172:65be27845400	235	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
AnnaBridge	172:65be27845400	236	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
AnnaBridge	172:65be27845400	237	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
AnnaBridge	172:65be27845400	238	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
AnnaBridge	172:65be27845400	239	/**
AnnaBridge	172:65be27845400	240	* @}
AnnaBridge	172:65be27845400	241	*/
AnnaBridge	172:65be27845400	242
AnnaBridge	172:65be27845400	243	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
AnnaBridge	172:65be27845400	244	* @{
AnnaBridge	172:65be27845400	245	*/
AnnaBridge	172:65be27845400	246	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /!< TIM2 counter stopped when core is halted /
AnnaBridge	172:65be27845400	247	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /!< TIM3 counter stopped when core is halted /
AnnaBridge	172:65be27845400	248	#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /!< TIM4 counter stopped when core is halted /
AnnaBridge	172:65be27845400	249	#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /!< TIM5 counter stopped when core is halted /
AnnaBridge	172:65be27845400	250	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /!< TIM6 counter stopped when core is halted /
AnnaBridge	172:65be27845400	251	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /!< TIM7 counter stopped when core is halted /
AnnaBridge	172:65be27845400	252	#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /!< TIM12 counter stopped when core is halted /
AnnaBridge	172:65be27845400	253	#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /!< TIM13 counter stopped when core is halted /
AnnaBridge	172:65be27845400	254	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /!< TIM14 counter stopped when core is halted /
AnnaBridge	172:65be27845400	255	#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /!< LPTIM1 counter stopped when core is halted /
AnnaBridge	172:65be27845400	256	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /!< I2C1 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	172:65be27845400	257	#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /!< I2C2 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	172:65be27845400	258	#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /!< I2C3 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	172:65be27845400	259	/**
AnnaBridge	172:65be27845400	260	* @}
AnnaBridge	172:65be27845400	261	*/
AnnaBridge	172:65be27845400	262
AnnaBridge	172:65be27845400	263	/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
AnnaBridge	172:65be27845400	264	* @{
AnnaBridge	172:65be27845400	265	*/
AnnaBridge	172:65be27845400	266	#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /!< FDCAN is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	267	/**
AnnaBridge	172:65be27845400	268	* @}
AnnaBridge	172:65be27845400	269	*/
AnnaBridge	172:65be27845400	270
AnnaBridge	172:65be27845400	271	/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
AnnaBridge	172:65be27845400	272	* @{
AnnaBridge	172:65be27845400	273	*/
AnnaBridge	172:65be27845400	274	#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /!< TIM1 counter stopped when core is halted /
AnnaBridge	172:65be27845400	275	#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /!< TIM8 counter stopped when core is halted /
AnnaBridge	172:65be27845400	276	#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /!< TIM15 counter stopped when core is halted /
AnnaBridge	172:65be27845400	277	#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /!< TIM16 counter stopped when core is halted /
AnnaBridge	172:65be27845400	278	#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /!< TIM17 counter stopped when core is halted /
AnnaBridge	172:65be27845400	279	#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /!< HRTIM counter stopped when core is halted /
AnnaBridge	172:65be27845400	280	/**
AnnaBridge	172:65be27845400	281	* @}
AnnaBridge	172:65be27845400	282	*/
AnnaBridge	172:65be27845400	283
AnnaBridge	172:65be27845400	284	/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
AnnaBridge	172:65be27845400	285	* @{
AnnaBridge	172:65be27845400	286	*/
AnnaBridge	172:65be27845400	287	#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /!< WWDG1 is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	288	/**
AnnaBridge	172:65be27845400	289	* @}
AnnaBridge	172:65be27845400	290	*/
AnnaBridge	172:65be27845400	291
AnnaBridge	172:65be27845400	292	/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
AnnaBridge	172:65be27845400	293	* @{
AnnaBridge	172:65be27845400	294	*/
AnnaBridge	172:65be27845400	295	#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /!< I2C4 is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	296	#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /!< LPTIM2 is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	297	#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /!< LPTIM3 is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	298	#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /!< LPTIM4 is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	299	#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /!< LPTIM5 is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	300	#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /!< RTC is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	301	#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /!< IWDG1 is frozen while the core is in debug mode /
AnnaBridge	172:65be27845400	302	/**
AnnaBridge	172:65be27845400	303	* @}
AnnaBridge	172:65be27845400	304	*/
AnnaBridge	172:65be27845400	305
AnnaBridge	172:65be27845400	306	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
AnnaBridge	172:65be27845400	307	* @{
AnnaBridge	172:65be27845400	308	*/
AnnaBridge	172:65be27845400	309	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
AnnaBridge	172:65be27845400	310	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
AnnaBridge	172:65be27845400	311	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
AnnaBridge	172:65be27845400	312	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
AnnaBridge	172:65be27845400	313	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
AnnaBridge	172:65be27845400	314	#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /!< FLASH five wait state /
AnnaBridge	172:65be27845400	315	#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /!< FLASH six wait state /
AnnaBridge	172:65be27845400	316	#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /!< FLASH seven wait states /
AnnaBridge	172:65be27845400	317	/**
AnnaBridge	172:65be27845400	318	* @}
AnnaBridge	172:65be27845400	319	*/
AnnaBridge	172:65be27845400	320
AnnaBridge	172:65be27845400	321	/**
AnnaBridge	172:65be27845400	322	* @}
AnnaBridge	172:65be27845400	323	*/
AnnaBridge	172:65be27845400	324
AnnaBridge	172:65be27845400	325	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	326
AnnaBridge	172:65be27845400	327	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	328	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
AnnaBridge	172:65be27845400	329	* @{
AnnaBridge	172:65be27845400	330	*/
AnnaBridge	172:65be27845400	331
AnnaBridge	172:65be27845400	332	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
AnnaBridge	172:65be27845400	333	* @{
AnnaBridge	172:65be27845400	334	*/
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	/**
AnnaBridge	172:65be27845400	337	* @brief Select Ethernet PHY interface
AnnaBridge	172:65be27845400	338	* @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface
AnnaBridge	172:65be27845400	339	* @param Interface This parameter can be one of the following values:
AnnaBridge	172:65be27845400	340	* @arg @ref LL_SYSCFG_ETH_MII
AnnaBridge	172:65be27845400	341	* @arg @ref LL_SYSCFG_ETH_RMII
AnnaBridge	172:65be27845400	342	* @retval None
AnnaBridge	172:65be27845400	343	*/
AnnaBridge	172:65be27845400	344	__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
AnnaBridge	172:65be27845400	345	{
AnnaBridge	172:65be27845400	346	MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
AnnaBridge	172:65be27845400	347	}
AnnaBridge	172:65be27845400	348
AnnaBridge	172:65be27845400	349	/**
AnnaBridge	172:65be27845400	350	* @brief Get Ethernet PHY interface
AnnaBridge	172:65be27845400	351	* @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface
AnnaBridge	172:65be27845400	352	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	353	* @arg @ref LL_SYSCFG_ETH_MII
AnnaBridge	172:65be27845400	354	* @arg @ref LL_SYSCFG_ETH_RMII
AnnaBridge	172:65be27845400	355	*/
AnnaBridge	172:65be27845400	356	__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
AnnaBridge	172:65be27845400	357	{
AnnaBridge	172:65be27845400	358	return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
AnnaBridge	172:65be27845400	359	}
AnnaBridge	172:65be27845400	360
AnnaBridge	172:65be27845400	361	/**
AnnaBridge	172:65be27845400	362	* @brief Open an Analog Switch
AnnaBridge	172:65be27845400	363	* @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch
AnnaBridge	172:65be27845400	364	* @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch
AnnaBridge	172:65be27845400	365	* @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch
AnnaBridge	172:65be27845400	366	* @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch
AnnaBridge	172:65be27845400	367	* @param AnalogSwitch This parameter can be one of the following values:
AnnaBridge	172:65be27845400	368	* @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
AnnaBridge	172:65be27845400	369	* @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
AnnaBridge	172:65be27845400	370	* @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
AnnaBridge	172:65be27845400	371	* @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
AnnaBridge	172:65be27845400	372	* @retval None
AnnaBridge	172:65be27845400	373	*/
AnnaBridge	172:65be27845400	374	__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
AnnaBridge	172:65be27845400	375	{
AnnaBridge	172:65be27845400	376	SET_BIT(SYSCFG->PMCR, AnalogSwitch);
AnnaBridge	172:65be27845400	377	}
AnnaBridge	172:65be27845400	378
AnnaBridge	172:65be27845400	379	/**
AnnaBridge	172:65be27845400	380	* @brief Close an Analog Switch
AnnaBridge	172:65be27845400	381	* @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch
AnnaBridge	172:65be27845400	382	* @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch
AnnaBridge	172:65be27845400	383	* @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch
AnnaBridge	172:65be27845400	384	* @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch
AnnaBridge	172:65be27845400	385	* @param AnalogSwitch This parameter can be one of the following values:
AnnaBridge	172:65be27845400	386	* @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
AnnaBridge	172:65be27845400	387	* @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
AnnaBridge	172:65be27845400	388	* @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
AnnaBridge	172:65be27845400	389	* @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
AnnaBridge	172:65be27845400	390	* @retval None
AnnaBridge	172:65be27845400	391	*/
AnnaBridge	172:65be27845400	392	__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
AnnaBridge	172:65be27845400	393	{
AnnaBridge	172:65be27845400	394	CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
AnnaBridge	172:65be27845400	395	}
AnnaBridge	172:65be27845400	396
AnnaBridge	172:65be27845400	397	/**
AnnaBridge	172:65be27845400	398	* @brief Enable the Analog booster to reduce the total harmonic distortion
AnnaBridge	172:65be27845400	399	* of the analog switch when the supply voltage is lower than 2.7 V
AnnaBridge	172:65be27845400	400	* @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster
AnnaBridge	172:65be27845400	401	* @note Activating the booster allows to guaranty the analog switch AC performance
AnnaBridge	172:65be27845400	402	* when the supply voltage is below 2.7 V: in this case, the analog switch
AnnaBridge	172:65be27845400	403	* performance is the same on the full voltage range
AnnaBridge	172:65be27845400	404	* @retval None
AnnaBridge	172:65be27845400	405	*/
AnnaBridge	172:65be27845400	406	__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
AnnaBridge	172:65be27845400	407	{
AnnaBridge	172:65be27845400	408	SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
AnnaBridge	172:65be27845400	409	}
AnnaBridge	172:65be27845400	410
AnnaBridge	172:65be27845400	411	/**
AnnaBridge	172:65be27845400	412	* @brief Disable the Analog booster
AnnaBridge	172:65be27845400	413	* @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster
AnnaBridge	172:65be27845400	414	* @note Activating the booster allows to guaranty the analog switch AC performance
AnnaBridge	172:65be27845400	415	* when the supply voltage is below 2.7 V: in this case, the analog switch
AnnaBridge	172:65be27845400	416	* performance is the same on the full voltage range
AnnaBridge	172:65be27845400	417	* @retval None
AnnaBridge	172:65be27845400	418	*/
AnnaBridge	172:65be27845400	419	__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
AnnaBridge	172:65be27845400	420	{
AnnaBridge	172:65be27845400	421	CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
AnnaBridge	172:65be27845400	422	}
AnnaBridge	172:65be27845400	423
AnnaBridge	172:65be27845400	424	/**
AnnaBridge	172:65be27845400	425	* @brief Enable the I2C fast mode plus driving capability.
AnnaBridge	172:65be27845400	426	* @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	172:65be27845400	427	* SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus
AnnaBridge	172:65be27845400	428	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	429	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
AnnaBridge	172:65be27845400	430	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
AnnaBridge	172:65be27845400	431	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
AnnaBridge	172:65be27845400	432	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
AnnaBridge	172:65be27845400	433	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
AnnaBridge	172:65be27845400	434	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
AnnaBridge	172:65be27845400	435	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
AnnaBridge	172:65be27845400	436	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
AnnaBridge	172:65be27845400	437	*
AnnaBridge	172:65be27845400	438	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	439	* @retval None
AnnaBridge	172:65be27845400	440	*/
AnnaBridge	172:65be27845400	441	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	172:65be27845400	442	{
AnnaBridge	172:65be27845400	443	SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
AnnaBridge	172:65be27845400	444	}
AnnaBridge	172:65be27845400	445
AnnaBridge	172:65be27845400	446	/**
AnnaBridge	172:65be27845400	447	* @brief Disable the I2C fast mode plus driving capability.
AnnaBridge	172:65be27845400	448	* @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	172:65be27845400	449	* SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus
AnnaBridge	172:65be27845400	450	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	451	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
AnnaBridge	172:65be27845400	452	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
AnnaBridge	172:65be27845400	453	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
AnnaBridge	172:65be27845400	454	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
AnnaBridge	172:65be27845400	455	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
AnnaBridge	172:65be27845400	456	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
AnnaBridge	172:65be27845400	457	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
AnnaBridge	172:65be27845400	458	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
AnnaBridge	172:65be27845400	459	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	460	* @retval None
AnnaBridge	172:65be27845400	461	*/
AnnaBridge	172:65be27845400	462	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	172:65be27845400	463	{
AnnaBridge	172:65be27845400	464	CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
AnnaBridge	172:65be27845400	465	}
AnnaBridge	172:65be27845400	466
AnnaBridge	172:65be27845400	467	/**
AnnaBridge	172:65be27845400	468	* @brief Configure source input for the EXTI external interrupt.
AnnaBridge	172:65be27845400	469	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	172:65be27845400	470	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	172:65be27845400	471	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
AnnaBridge	172:65be27845400	472	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
AnnaBridge	172:65be27845400	473	* @param Port This parameter can be one of the following values:
AnnaBridge	172:65be27845400	474	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	172:65be27845400	475	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	172:65be27845400	476	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	172:65be27845400	477	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	172:65be27845400	478	* @arg @ref LL_SYSCFG_EXTI_PORTE
AnnaBridge	172:65be27845400	479	* @arg @ref LL_SYSCFG_EXTI_PORTF
AnnaBridge	172:65be27845400	480	* @arg @ref LL_SYSCFG_EXTI_PORTG
AnnaBridge	172:65be27845400	481	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	172:65be27845400	482	* @arg @ref LL_SYSCFG_EXTI_PORTI
AnnaBridge	172:65be27845400	483	* @arg @ref LL_SYSCFG_EXTI_PORTJ
AnnaBridge	172:65be27845400	484	* @arg @ref LL_SYSCFG_EXTI_PORTK
AnnaBridge	172:65be27845400	485	*
AnnaBridge	172:65be27845400	486	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	487	* @param Line This parameter can be one of the following values:
AnnaBridge	172:65be27845400	488	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	172:65be27845400	489	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	172:65be27845400	490	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	172:65be27845400	491	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	172:65be27845400	492	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	172:65be27845400	493	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	172:65be27845400	494	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	172:65be27845400	495	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	172:65be27845400	496	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	172:65be27845400	497	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	172:65be27845400	498	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	172:65be27845400	499	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	172:65be27845400	500	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	172:65be27845400	501	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	172:65be27845400	502	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	172:65be27845400	503	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	172:65be27845400	504	* @retval None
AnnaBridge	172:65be27845400	505	*/
AnnaBridge	172:65be27845400	506	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
AnnaBridge	172:65be27845400	507	{
AnnaBridge	172:65be27845400	508	MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
AnnaBridge	172:65be27845400	509	}
AnnaBridge	172:65be27845400	510
AnnaBridge	172:65be27845400	511	/**
AnnaBridge	172:65be27845400	512	* @brief Get the configured defined for specific EXTI Line
AnnaBridge	172:65be27845400	513	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	172:65be27845400	514	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	172:65be27845400	515	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
AnnaBridge	172:65be27845400	516	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
AnnaBridge	172:65be27845400	517	* @param Line This parameter can be one of the following values:
AnnaBridge	172:65be27845400	518	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	172:65be27845400	519	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	172:65be27845400	520	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	172:65be27845400	521	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	172:65be27845400	522	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	172:65be27845400	523	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	172:65be27845400	524	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	172:65be27845400	525	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	172:65be27845400	526	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	172:65be27845400	527	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	172:65be27845400	528	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	172:65be27845400	529	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	172:65be27845400	530	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	172:65be27845400	531	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	172:65be27845400	532	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	172:65be27845400	533	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	172:65be27845400	534	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	535	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	172:65be27845400	536	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	172:65be27845400	537	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	172:65be27845400	538	* @arg @ref LL_SYSCFG_EXTI_PORTD
AnnaBridge	172:65be27845400	539	* @arg @ref LL_SYSCFG_EXTI_PORTE
AnnaBridge	172:65be27845400	540	* @arg @ref LL_SYSCFG_EXTI_PORTF
AnnaBridge	172:65be27845400	541	* @arg @ref LL_SYSCFG_EXTI_PORTG
AnnaBridge	172:65be27845400	542	* @arg @ref LL_SYSCFG_EXTI_PORTH
AnnaBridge	172:65be27845400	543	* @arg @ref LL_SYSCFG_EXTI_PORTI
AnnaBridge	172:65be27845400	544	* @arg @ref LL_SYSCFG_EXTI_PORTJ
AnnaBridge	172:65be27845400	545	* @arg @ref LL_SYSCFG_EXTI_PORTK
AnnaBridge	172:65be27845400	546	* (*) value not defined in all devices
AnnaBridge	172:65be27845400	547	*/
AnnaBridge	172:65be27845400	548	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
AnnaBridge	172:65be27845400	549	{
AnnaBridge	172:65be27845400	550	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
AnnaBridge	172:65be27845400	551	}
AnnaBridge	172:65be27845400	552
AnnaBridge	172:65be27845400	553	/**
AnnaBridge	172:65be27845400	554	* @brief Enable the Compensation Cell
AnnaBridge	172:65be27845400	555	* @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell
AnnaBridge	172:65be27845400	556	* @note The I/O compensation cell can be used only when the device supply
AnnaBridge	172:65be27845400	557	* voltage ranges from 2.4 to 3.6 V
AnnaBridge	172:65be27845400	558	* @retval None
AnnaBridge	172:65be27845400	559	*/
AnnaBridge	172:65be27845400	560	__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
AnnaBridge	172:65be27845400	561	{
AnnaBridge	172:65be27845400	562	SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
AnnaBridge	172:65be27845400	563	}
AnnaBridge	172:65be27845400	564
AnnaBridge	172:65be27845400	565	/**
AnnaBridge	172:65be27845400	566	* @brief Disable the Compensation Cell
AnnaBridge	172:65be27845400	567	* @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell
AnnaBridge	172:65be27845400	568	* @note The I/O compensation cell can be used only when the device supply
AnnaBridge	172:65be27845400	569	* voltage ranges from 2.4 to 3.6 V
AnnaBridge	172:65be27845400	570	* @retval None
AnnaBridge	172:65be27845400	571	*/
AnnaBridge	172:65be27845400	572	__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
AnnaBridge	172:65be27845400	573	{
AnnaBridge	172:65be27845400	574	CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
AnnaBridge	172:65be27845400	575	}
AnnaBridge	172:65be27845400	576
AnnaBridge	172:65be27845400	577	/**
AnnaBridge	172:65be27845400	578	* @brief Check if the Compensation Cell is enabled
AnnaBridge	172:65be27845400	579	* @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell
AnnaBridge	172:65be27845400	580	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	581	*/
AnnaBridge	172:65be27845400	582	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
AnnaBridge	172:65be27845400	583	{
AnnaBridge	172:65be27845400	584	return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	585	}
AnnaBridge	172:65be27845400	586
AnnaBridge	172:65be27845400	587	/**
AnnaBridge	172:65be27845400	588	* @brief Get Compensation Cell ready Flag
AnnaBridge	172:65be27845400	589	* @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR
AnnaBridge	172:65be27845400	590	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	591	*/
AnnaBridge	172:65be27845400	592	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
AnnaBridge	172:65be27845400	593	{
AnnaBridge	172:65be27845400	594	return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	595	}
AnnaBridge	172:65be27845400	596
AnnaBridge	172:65be27845400	597	/**
AnnaBridge	172:65be27845400	598	* @brief Enable the I/O speed optimization when the product voltage is low.
AnnaBridge	172:65be27845400	599	* @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize
AnnaBridge	172:65be27845400	600	* @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
AnnaBridge	172:65be27845400	601	* product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
AnnaBridge	172:65be27845400	602	* might be destructive.
AnnaBridge	172:65be27845400	603	* @retval None
AnnaBridge	172:65be27845400	604	*/
AnnaBridge	172:65be27845400	605	__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
AnnaBridge	172:65be27845400	606	{
AnnaBridge	172:65be27845400	607	SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
AnnaBridge	172:65be27845400	608	}
AnnaBridge	172:65be27845400	609
AnnaBridge	172:65be27845400	610	/**
AnnaBridge	172:65be27845400	611	* @brief To Disable optimize the I/O speed when the product voltage is low.
AnnaBridge	172:65be27845400	612	* @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize
AnnaBridge	172:65be27845400	613	* @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
AnnaBridge	172:65be27845400	614	* product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
AnnaBridge	172:65be27845400	615	* might be destructive.
AnnaBridge	172:65be27845400	616	* @retval None
AnnaBridge	172:65be27845400	617	*/
AnnaBridge	172:65be27845400	618	__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
AnnaBridge	172:65be27845400	619	{
AnnaBridge	172:65be27845400	620	CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
AnnaBridge	172:65be27845400	621	}
AnnaBridge	172:65be27845400	622
AnnaBridge	172:65be27845400	623	/**
AnnaBridge	172:65be27845400	624	* @brief Check if the I/O speed optimization is enabled
AnnaBridge	172:65be27845400	625	* @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization
AnnaBridge	172:65be27845400	626	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	627	*/
AnnaBridge	172:65be27845400	628	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
AnnaBridge	172:65be27845400	629	{
AnnaBridge	172:65be27845400	630	return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	631	}
AnnaBridge	172:65be27845400	632
AnnaBridge	172:65be27845400	633	/**
AnnaBridge	172:65be27845400	634	* @brief Set the code selection for the I/O Compensation cell
AnnaBridge	172:65be27845400	635	* @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode
AnnaBridge	172:65be27845400	636	* @param CompCode: Selects the code to be applied for the I/O compensation cell
AnnaBridge	172:65be27845400	637	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	638	* @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
AnnaBridge	172:65be27845400	639	* @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
AnnaBridge	172:65be27845400	640	* @retval None
AnnaBridge	172:65be27845400	641	*/
AnnaBridge	172:65be27845400	642	__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
AnnaBridge	172:65be27845400	643	{
AnnaBridge	172:65be27845400	644	SET_BIT(SYSCFG->CCCSR, CompCode);
AnnaBridge	172:65be27845400	645	}
AnnaBridge	172:65be27845400	646
AnnaBridge	172:65be27845400	647	/**
AnnaBridge	172:65be27845400	648	* @brief Get the code selected for the I/O Compensation cell
AnnaBridge	172:65be27845400	649	* @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
AnnaBridge	172:65be27845400	650	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	651	* @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
AnnaBridge	172:65be27845400	652	* @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
AnnaBridge	172:65be27845400	653	*/
AnnaBridge	172:65be27845400	654	__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
AnnaBridge	172:65be27845400	655	{
AnnaBridge	172:65be27845400	656	return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
AnnaBridge	172:65be27845400	657	}
AnnaBridge	172:65be27845400	658
AnnaBridge	172:65be27845400	659	/**
AnnaBridge	172:65be27845400	660	* @brief Get I/O compensation cell value for PMOS transistors
AnnaBridge	172:65be27845400	661	* @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue
AnnaBridge	172:65be27845400	662	* @retval Returned value is the I/O compensation cell value for PMOS transistors
AnnaBridge	172:65be27845400	663	*/
AnnaBridge	172:65be27845400	664	__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
AnnaBridge	172:65be27845400	665	{
AnnaBridge	172:65be27845400	666	return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
AnnaBridge	172:65be27845400	667	}
AnnaBridge	172:65be27845400	668
AnnaBridge	172:65be27845400	669	/**
AnnaBridge	172:65be27845400	670	* @brief Get I/O compensation cell value for NMOS transistors
AnnaBridge	172:65be27845400	671	* @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue
AnnaBridge	172:65be27845400	672	* @retval Returned value is the I/O compensation cell value for NMOS transistors
AnnaBridge	172:65be27845400	673	*/
AnnaBridge	172:65be27845400	674	__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
AnnaBridge	172:65be27845400	675	{
AnnaBridge	172:65be27845400	676	return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
AnnaBridge	172:65be27845400	677	}
AnnaBridge	172:65be27845400	678
AnnaBridge	172:65be27845400	679	/**
AnnaBridge	172:65be27845400	680	* @brief Set I/O compensation cell code for PMOS transistors
AnnaBridge	172:65be27845400	681	* @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
AnnaBridge	172:65be27845400	682	* @param PMOSCode PMOS compensation code
AnnaBridge	172:65be27845400	683	* This code is applied to the I/O compensation cell when the CS bit of the
AnnaBridge	172:65be27845400	684	* SYSCFG_CMPCR is set
AnnaBridge	172:65be27845400	685	* @retval None
AnnaBridge	172:65be27845400	686	*/
AnnaBridge	172:65be27845400	687	__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
AnnaBridge	172:65be27845400	688	{
AnnaBridge	172:65be27845400	689	MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
AnnaBridge	172:65be27845400	690	}
AnnaBridge	172:65be27845400	691
AnnaBridge	172:65be27845400	692	/**
AnnaBridge	172:65be27845400	693	* @brief Get I/O compensation cell code for PMOS transistors
AnnaBridge	172:65be27845400	694	* @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
AnnaBridge	172:65be27845400	695	* @retval Returned value is the I/O compensation cell code for PMOS transistors
AnnaBridge	172:65be27845400	696	*/
AnnaBridge	172:65be27845400	697	__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
AnnaBridge	172:65be27845400	698	{
AnnaBridge	172:65be27845400	699	return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
AnnaBridge	172:65be27845400	700	}
AnnaBridge	172:65be27845400	701
AnnaBridge	172:65be27845400	702	/**
AnnaBridge	172:65be27845400	703	* @brief Set I/O compensation cell code for NMOS transistors
AnnaBridge	172:65be27845400	704	* @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
AnnaBridge	172:65be27845400	705	* @param NMOSCode NMOS compensation code
AnnaBridge	172:65be27845400	706	* This code is applied to the I/O compensation cell when the CS bit of the
AnnaBridge	172:65be27845400	707	* SYSCFG_CMPCR is set
AnnaBridge	172:65be27845400	708	* @retval None
AnnaBridge	172:65be27845400	709	*/
AnnaBridge	172:65be27845400	710	__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
AnnaBridge	172:65be27845400	711	{
AnnaBridge	172:65be27845400	712	MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
AnnaBridge	172:65be27845400	713	}
AnnaBridge	172:65be27845400	714
AnnaBridge	172:65be27845400	715	/**
AnnaBridge	172:65be27845400	716	* @brief Get I/O compensation cell code for NMOS transistors
AnnaBridge	172:65be27845400	717	* @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
AnnaBridge	172:65be27845400	718	* @retval Returned value is the I/O compensation cell code for NMOS transistors
AnnaBridge	172:65be27845400	719	*/
AnnaBridge	172:65be27845400	720	__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
AnnaBridge	172:65be27845400	721	{
AnnaBridge	172:65be27845400	722	return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
AnnaBridge	172:65be27845400	723	}
AnnaBridge	172:65be27845400	724
AnnaBridge	172:65be27845400	725	/**
AnnaBridge	172:65be27845400	726	* @brief Get the device package
AnnaBridge	172:65be27845400	727	* @rmtoll PKGR PKG LL_SYSCFG_GetPackage
AnnaBridge	172:65be27845400	728	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	729	* @arg @ref LL_SYSCFG_LQFP100_PACKAGE
AnnaBridge	172:65be27845400	730	* @arg @ref LL_SYSCFG_TQFP144_PACKAGE
AnnaBridge	172:65be27845400	731	* @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE
AnnaBridge	172:65be27845400	732	* @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE
AnnaBridge	172:65be27845400	733	*/
AnnaBridge	172:65be27845400	734	__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
AnnaBridge	172:65be27845400	735	{
AnnaBridge	172:65be27845400	736	return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
AnnaBridge	172:65be27845400	737	}
AnnaBridge	172:65be27845400	738
AnnaBridge	172:65be27845400	739	/**
AnnaBridge	172:65be27845400	740	* @brief Get the Flash memory protection level
AnnaBridge	172:65be27845400	741	* @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel
AnnaBridge	172:65be27845400	742	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	743	* 0xAA : RDP level 0
AnnaBridge	172:65be27845400	744	* 0xCC : RDP level 2
AnnaBridge	172:65be27845400	745	* Any other value : RDP level 1
AnnaBridge	172:65be27845400	746	*/
AnnaBridge	172:65be27845400	747	__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
AnnaBridge	172:65be27845400	748	{
AnnaBridge	172:65be27845400	749	return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
AnnaBridge	172:65be27845400	750	}
AnnaBridge	172:65be27845400	751
AnnaBridge	172:65be27845400	752	/**
AnnaBridge	172:65be27845400	753	* @brief Indicate if the Flash memory bank addresses are inverted or not
AnnaBridge	172:65be27845400	754	* @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped
AnnaBridge	172:65be27845400	755	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	756	*/
AnnaBridge	172:65be27845400	757	__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
AnnaBridge	172:65be27845400	758	{
AnnaBridge	172:65be27845400	759	return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	760	}
AnnaBridge	172:65be27845400	761
AnnaBridge	172:65be27845400	762	/**
AnnaBridge	172:65be27845400	763	* @brief Get the BOR Threshold Reset Level
AnnaBridge	172:65be27845400	764	* @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel
AnnaBridge	172:65be27845400	765	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	766	* @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
AnnaBridge	172:65be27845400	767	* @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
AnnaBridge	172:65be27845400	768	* @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
AnnaBridge	172:65be27845400	769	* @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
AnnaBridge	172:65be27845400	770	*/
AnnaBridge	172:65be27845400	771	__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
AnnaBridge	172:65be27845400	772	{
AnnaBridge	172:65be27845400	773	return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
AnnaBridge	172:65be27845400	774	}
AnnaBridge	172:65be27845400	775
AnnaBridge	172:65be27845400	776	/**
AnnaBridge	172:65be27845400	777	* @brief BootCM7 address 0 configuration
AnnaBridge	172:65be27845400	778	* @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0
AnnaBridge	172:65be27845400	779	* @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
AnnaBridge	172:65be27845400	780	* @retval None
AnnaBridge	172:65be27845400	781	*/
AnnaBridge	172:65be27845400	782	__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
AnnaBridge	172:65be27845400	783	{
AnnaBridge	172:65be27845400	784	/* Configure CM7 BOOT ADD0 */
AnnaBridge	172:65be27845400	785	MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
AnnaBridge	172:65be27845400	786	}
AnnaBridge	172:65be27845400	787
AnnaBridge	172:65be27845400	788	/**
AnnaBridge	172:65be27845400	789	* @brief Get BootCM7 address 0
AnnaBridge	172:65be27845400	790	* @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0
AnnaBridge	172:65be27845400	791	* @retval Returned the CM7 Boot Address0
AnnaBridge	172:65be27845400	792	*/
AnnaBridge	172:65be27845400	793	__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
AnnaBridge	172:65be27845400	794	{
AnnaBridge	172:65be27845400	795	/* Get CM7 BOOT ADD0 */
AnnaBridge	172:65be27845400	796	return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
AnnaBridge	172:65be27845400	797	}
AnnaBridge	172:65be27845400	798
AnnaBridge	172:65be27845400	799	/**
AnnaBridge	172:65be27845400	800	* @brief BootCM7 address 1 configuration
AnnaBridge	172:65be27845400	801	* @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1
AnnaBridge	172:65be27845400	802	* @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
AnnaBridge	172:65be27845400	803	* @retval None
AnnaBridge	172:65be27845400	804	*/
AnnaBridge	172:65be27845400	805	__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
AnnaBridge	172:65be27845400	806	{
AnnaBridge	172:65be27845400	807	/* Configure CM7 BOOT ADD1 */
AnnaBridge	172:65be27845400	808	MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
AnnaBridge	172:65be27845400	809	}
AnnaBridge	172:65be27845400	810
AnnaBridge	172:65be27845400	811	/**
AnnaBridge	172:65be27845400	812	* @brief Get BootCM7 address 1
AnnaBridge	172:65be27845400	813	* @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1
AnnaBridge	172:65be27845400	814	* @retval Returned the CM7 Boot Address0
AnnaBridge	172:65be27845400	815	*/
AnnaBridge	172:65be27845400	816	__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
AnnaBridge	172:65be27845400	817	{
AnnaBridge	172:65be27845400	818	/* Get CM7 BOOT ADD0 */
AnnaBridge	172:65be27845400	819	return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
AnnaBridge	172:65be27845400	820	}
AnnaBridge	172:65be27845400	821
AnnaBridge	172:65be27845400	822	/**
AnnaBridge	172:65be27845400	823	* @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase
AnnaBridge	172:65be27845400	824	* @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable
AnnaBridge	172:65be27845400	825	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	826	*/
AnnaBridge	172:65be27845400	827	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
AnnaBridge	172:65be27845400	828	{
AnnaBridge	172:65be27845400	829	return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	830	}
AnnaBridge	172:65be27845400	831
AnnaBridge	172:65be27845400	832	/**
AnnaBridge	172:65be27845400	833	* @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase
AnnaBridge	172:65be27845400	834	* @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable
AnnaBridge	172:65be27845400	835	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	836	*/
AnnaBridge	172:65be27845400	837	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
AnnaBridge	172:65be27845400	838	{
AnnaBridge	172:65be27845400	839	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	840	}
AnnaBridge	172:65be27845400	841
AnnaBridge	172:65be27845400	842	/**
AnnaBridge	172:65be27845400	843	* @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	844	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected
AnnaBridge	172:65be27845400	845	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	846	*/
AnnaBridge	172:65be27845400	847	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
AnnaBridge	172:65be27845400	848	{
AnnaBridge	172:65be27845400	849	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	850	}
AnnaBridge	172:65be27845400	851
AnnaBridge	172:65be27845400	852	/**
AnnaBridge	172:65be27845400	853	* @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	854	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected
AnnaBridge	172:65be27845400	855	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	856	*/
AnnaBridge	172:65be27845400	857	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
AnnaBridge	172:65be27845400	858	{
AnnaBridge	172:65be27845400	859	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	860	}
AnnaBridge	172:65be27845400	861
AnnaBridge	172:65be27845400	862	/**
AnnaBridge	172:65be27845400	863	* @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	864	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected
AnnaBridge	172:65be27845400	865	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	866	*/
AnnaBridge	172:65be27845400	867	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
AnnaBridge	172:65be27845400	868	{
AnnaBridge	172:65be27845400	869	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	870	}
AnnaBridge	172:65be27845400	871
AnnaBridge	172:65be27845400	872	/**
AnnaBridge	172:65be27845400	873	* @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	874	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected
AnnaBridge	172:65be27845400	875	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	876	*/
AnnaBridge	172:65be27845400	877	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
AnnaBridge	172:65be27845400	878	{
AnnaBridge	172:65be27845400	879	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	880	}
AnnaBridge	172:65be27845400	881
AnnaBridge	172:65be27845400	882	/**
AnnaBridge	172:65be27845400	883	* @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	884	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected
AnnaBridge	172:65be27845400	885	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	886	*/
AnnaBridge	172:65be27845400	887	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
AnnaBridge	172:65be27845400	888	{
AnnaBridge	172:65be27845400	889	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	890	}
AnnaBridge	172:65be27845400	891
AnnaBridge	172:65be27845400	892	/**
AnnaBridge	172:65be27845400	893	* @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	894	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected
AnnaBridge	172:65be27845400	895	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	896	*/
AnnaBridge	172:65be27845400	897	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
AnnaBridge	172:65be27845400	898	{
AnnaBridge	172:65be27845400	899	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	900	}
AnnaBridge	172:65be27845400	901
AnnaBridge	172:65be27845400	902	/**
AnnaBridge	172:65be27845400	903	* @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	904	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected
AnnaBridge	172:65be27845400	905	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	906	*/
AnnaBridge	172:65be27845400	907	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
AnnaBridge	172:65be27845400	908	{
AnnaBridge	172:65be27845400	909	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	910	}
AnnaBridge	172:65be27845400	911
AnnaBridge	172:65be27845400	912	/**
AnnaBridge	172:65be27845400	913	* @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected
AnnaBridge	172:65be27845400	914	* @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected
AnnaBridge	172:65be27845400	915	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	916	*/
AnnaBridge	172:65be27845400	917	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
AnnaBridge	172:65be27845400	918	{
AnnaBridge	172:65be27845400	919	return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	920	}
AnnaBridge	172:65be27845400	921
AnnaBridge	172:65be27845400	922	/**
AnnaBridge	172:65be27845400	923	* @brief Get the protected area start address for Flash bank 1
AnnaBridge	172:65be27845400	924	* @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
AnnaBridge	172:65be27845400	925	* @retval Returned the protected area start address for Flash bank 1
AnnaBridge	172:65be27845400	926	*/
AnnaBridge	172:65be27845400	927	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
AnnaBridge	172:65be27845400	928	{
AnnaBridge	172:65be27845400	929	return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
AnnaBridge	172:65be27845400	930	}
AnnaBridge	172:65be27845400	931
AnnaBridge	172:65be27845400	932	/**
AnnaBridge	172:65be27845400	933	* @brief Get the protected area end address for Flash bank 1
AnnaBridge	172:65be27845400	934	* @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
AnnaBridge	172:65be27845400	935	* @retval Returned the protected area end address for Flash bank 1
AnnaBridge	172:65be27845400	936	*/
AnnaBridge	172:65be27845400	937	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
AnnaBridge	172:65be27845400	938	{
AnnaBridge	172:65be27845400	939	return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
AnnaBridge	172:65be27845400	940	}
AnnaBridge	172:65be27845400	941
AnnaBridge	172:65be27845400	942	/**
AnnaBridge	172:65be27845400	943	* @brief Get the secured area start address for Flash bank 1
AnnaBridge	172:65be27845400	944	* @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
AnnaBridge	172:65be27845400	945	* @retval Returned the secured area start address for Flash bank 1
AnnaBridge	172:65be27845400	946	*/
AnnaBridge	172:65be27845400	947	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
AnnaBridge	172:65be27845400	948	{
AnnaBridge	172:65be27845400	949	return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
AnnaBridge	172:65be27845400	950	}
AnnaBridge	172:65be27845400	951
AnnaBridge	172:65be27845400	952	/**
AnnaBridge	172:65be27845400	953	* @brief Get the secured area end address for Flash bank 1
AnnaBridge	172:65be27845400	954	* @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
AnnaBridge	172:65be27845400	955	* @retval Returned the secured area end address for Flash bank 1
AnnaBridge	172:65be27845400	956	*/
AnnaBridge	172:65be27845400	957	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
AnnaBridge	172:65be27845400	958	{
AnnaBridge	172:65be27845400	959	return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
AnnaBridge	172:65be27845400	960	}
AnnaBridge	172:65be27845400	961
AnnaBridge	172:65be27845400	962	/**
AnnaBridge	172:65be27845400	963	* @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase
AnnaBridge	172:65be27845400	964	* @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable
AnnaBridge	172:65be27845400	965	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	966	*/
AnnaBridge	172:65be27845400	967	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
AnnaBridge	172:65be27845400	968	{
AnnaBridge	172:65be27845400	969	return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	970	}
AnnaBridge	172:65be27845400	971
AnnaBridge	172:65be27845400	972	/**
AnnaBridge	172:65be27845400	973	* @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase
AnnaBridge	172:65be27845400	974	* @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable
AnnaBridge	172:65be27845400	975	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	976	*/
AnnaBridge	172:65be27845400	977	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
AnnaBridge	172:65be27845400	978	{
AnnaBridge	172:65be27845400	979	return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	980	}
AnnaBridge	172:65be27845400	981
AnnaBridge	172:65be27845400	982	/**
AnnaBridge	172:65be27845400	983	* @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	984	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected
AnnaBridge	172:65be27845400	985	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	986	*/
AnnaBridge	172:65be27845400	987	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
AnnaBridge	172:65be27845400	988	{
AnnaBridge	172:65be27845400	989	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	990	}
AnnaBridge	172:65be27845400	991
AnnaBridge	172:65be27845400	992	/**
AnnaBridge	172:65be27845400	993	* @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	994	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected
AnnaBridge	172:65be27845400	995	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	996	*/
AnnaBridge	172:65be27845400	997	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
AnnaBridge	172:65be27845400	998	{
AnnaBridge	172:65be27845400	999	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1000	}
AnnaBridge	172:65be27845400	1001
AnnaBridge	172:65be27845400	1002	/**
AnnaBridge	172:65be27845400	1003	* @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	1004	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected
AnnaBridge	172:65be27845400	1005	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1006	*/
AnnaBridge	172:65be27845400	1007	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
AnnaBridge	172:65be27845400	1008	{
AnnaBridge	172:65be27845400	1009	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1010	}
AnnaBridge	172:65be27845400	1011
AnnaBridge	172:65be27845400	1012	/**
AnnaBridge	172:65be27845400	1013	* @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	1014	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected
AnnaBridge	172:65be27845400	1015	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1016	*/
AnnaBridge	172:65be27845400	1017	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
AnnaBridge	172:65be27845400	1018	{
AnnaBridge	172:65be27845400	1019	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1020	}
AnnaBridge	172:65be27845400	1021
AnnaBridge	172:65be27845400	1022	/**
AnnaBridge	172:65be27845400	1023	* @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	1024	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected
AnnaBridge	172:65be27845400	1025	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1026	*/
AnnaBridge	172:65be27845400	1027	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
AnnaBridge	172:65be27845400	1028	{
AnnaBridge	172:65be27845400	1029	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1030	}
AnnaBridge	172:65be27845400	1031
AnnaBridge	172:65be27845400	1032	/**
AnnaBridge	172:65be27845400	1033	* @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	1034	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected
AnnaBridge	172:65be27845400	1035	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1036	*/
AnnaBridge	172:65be27845400	1037	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
AnnaBridge	172:65be27845400	1038	{
AnnaBridge	172:65be27845400	1039	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1040	}
AnnaBridge	172:65be27845400	1041
AnnaBridge	172:65be27845400	1042	/**
AnnaBridge	172:65be27845400	1043	* @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	1044	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected
AnnaBridge	172:65be27845400	1045	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1046	*/
AnnaBridge	172:65be27845400	1047	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
AnnaBridge	172:65be27845400	1048	{
AnnaBridge	172:65be27845400	1049	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1050	}
AnnaBridge	172:65be27845400	1051
AnnaBridge	172:65be27845400	1052	/**
AnnaBridge	172:65be27845400	1053	* @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected
AnnaBridge	172:65be27845400	1054	* @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected
AnnaBridge	172:65be27845400	1055	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1056	*/
AnnaBridge	172:65be27845400	1057	__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
AnnaBridge	172:65be27845400	1058	{
AnnaBridge	172:65be27845400	1059	return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1060	}
AnnaBridge	172:65be27845400	1061
AnnaBridge	172:65be27845400	1062	/**
AnnaBridge	172:65be27845400	1063	* @brief Get the protected area start address for Flash bank 2
AnnaBridge	172:65be27845400	1064	* @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
AnnaBridge	172:65be27845400	1065	* @retval Returned the protected area start address for Flash bank 2
AnnaBridge	172:65be27845400	1066	*/
AnnaBridge	172:65be27845400	1067	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
AnnaBridge	172:65be27845400	1068	{
AnnaBridge	172:65be27845400	1069	return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
AnnaBridge	172:65be27845400	1070	}
AnnaBridge	172:65be27845400	1071
AnnaBridge	172:65be27845400	1072	/**
AnnaBridge	172:65be27845400	1073	* @brief Get the protected area end address for Flash bank 2
AnnaBridge	172:65be27845400	1074	* @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
AnnaBridge	172:65be27845400	1075	* @retval Returned the protected area end address for Flash bank 2
AnnaBridge	172:65be27845400	1076	*/
AnnaBridge	172:65be27845400	1077	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
AnnaBridge	172:65be27845400	1078	{
AnnaBridge	172:65be27845400	1079	return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
AnnaBridge	172:65be27845400	1080	}
AnnaBridge	172:65be27845400	1081
AnnaBridge	172:65be27845400	1082	/**
AnnaBridge	172:65be27845400	1083	* @brief Get the secured area start address for Flash bank 2
AnnaBridge	172:65be27845400	1084	* @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
AnnaBridge	172:65be27845400	1085	* @retval Returned the secured area start address for Flash bank 2
AnnaBridge	172:65be27845400	1086	*/
AnnaBridge	172:65be27845400	1087	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
AnnaBridge	172:65be27845400	1088	{
AnnaBridge	172:65be27845400	1089	return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
AnnaBridge	172:65be27845400	1090	}
AnnaBridge	172:65be27845400	1091
AnnaBridge	172:65be27845400	1092	/**
AnnaBridge	172:65be27845400	1093	* @brief Get the secured area end address for Flash bank 2
AnnaBridge	172:65be27845400	1094	* @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
AnnaBridge	172:65be27845400	1095	* @retval Returned the secured area end address for Flash bank 2
AnnaBridge	172:65be27845400	1096	*/
AnnaBridge	172:65be27845400	1097	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
AnnaBridge	172:65be27845400	1098	{
AnnaBridge	172:65be27845400	1099	return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
AnnaBridge	172:65be27845400	1100	}
AnnaBridge	172:65be27845400	1101
AnnaBridge	172:65be27845400	1102	/**
AnnaBridge	172:65be27845400	1103	* @brief Get the Independent Watchdog 1 control mode (Software or Hardware)
AnnaBridge	172:65be27845400	1104	* @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode
AnnaBridge	172:65be27845400	1105	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1106	* @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
AnnaBridge	172:65be27845400	1107	* @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
AnnaBridge	172:65be27845400	1108	*/
AnnaBridge	172:65be27845400	1109	__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
AnnaBridge	172:65be27845400	1110	{
AnnaBridge	172:65be27845400	1111	return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
AnnaBridge	172:65be27845400	1112	}
AnnaBridge	172:65be27845400	1113
AnnaBridge	172:65be27845400	1114	/**
AnnaBridge	172:65be27845400	1115	* @brief Indicates the Secure mode status
AnnaBridge	172:65be27845400	1116	* @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled
AnnaBridge	172:65be27845400	1117	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1118	*/
AnnaBridge	172:65be27845400	1119	__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
AnnaBridge	172:65be27845400	1120	{
AnnaBridge	172:65be27845400	1121	return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1122	}
AnnaBridge	172:65be27845400	1123
AnnaBridge	172:65be27845400	1124	/**
AnnaBridge	172:65be27845400	1125	* @brief Indicates if a reset is generated when D1 domain enters DStandby mode
AnnaBridge	172:65be27845400	1126	* @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset
AnnaBridge	172:65be27845400	1127	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1128	*/
AnnaBridge	172:65be27845400	1129	__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
AnnaBridge	172:65be27845400	1130	{
AnnaBridge	172:65be27845400	1131	return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1132	}
AnnaBridge	172:65be27845400	1133
AnnaBridge	172:65be27845400	1134	/**
AnnaBridge	172:65be27845400	1135	* @brief Get the secured DTCM RAM size
AnnaBridge	172:65be27845400	1136	* @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize
AnnaBridge	172:65be27845400	1137	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1138	* @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
AnnaBridge	172:65be27845400	1139	* @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
AnnaBridge	172:65be27845400	1140	* @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
AnnaBridge	172:65be27845400	1141	* @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
AnnaBridge	172:65be27845400	1142	*/
AnnaBridge	172:65be27845400	1143	__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
AnnaBridge	172:65be27845400	1144	{
AnnaBridge	172:65be27845400	1145	return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
AnnaBridge	172:65be27845400	1146	}
AnnaBridge	172:65be27845400	1147
AnnaBridge	172:65be27845400	1148	/**
AnnaBridge	172:65be27845400	1149	* @brief Indicates if a reset is generated when D1 domain enters DStop mode
AnnaBridge	172:65be27845400	1150	* @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset
AnnaBridge	172:65be27845400	1151	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1152	*/
AnnaBridge	172:65be27845400	1153	__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
AnnaBridge	172:65be27845400	1154	{
AnnaBridge	172:65be27845400	1155	return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1156	}
AnnaBridge	172:65be27845400	1157
AnnaBridge	172:65be27845400	1158	/**
AnnaBridge	172:65be27845400	1159	* @brief Indicates if the independent watchdog is frozen in Standby mode
AnnaBridge	172:65be27845400	1160	* @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode
AnnaBridge	172:65be27845400	1161	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1162	*/
AnnaBridge	172:65be27845400	1163	__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
AnnaBridge	172:65be27845400	1164	{
AnnaBridge	172:65be27845400	1165	return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1166	}
AnnaBridge	172:65be27845400	1167
AnnaBridge	172:65be27845400	1168	/**
AnnaBridge	172:65be27845400	1169	* @brief Indicates if the independent watchdog is frozen in Stop mode
AnnaBridge	172:65be27845400	1170	* @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode
AnnaBridge	172:65be27845400	1171	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1172	*/
AnnaBridge	172:65be27845400	1173	__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
AnnaBridge	172:65be27845400	1174	{
AnnaBridge	172:65be27845400	1175	return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1176	}
AnnaBridge	172:65be27845400	1177
AnnaBridge	172:65be27845400	1178	/**
AnnaBridge	172:65be27845400	1179	* @brief Indicates if the device private key is programmed
AnnaBridge	172:65be27845400	1180	* @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed
AnnaBridge	172:65be27845400	1181	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1182	*/
AnnaBridge	172:65be27845400	1183	__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
AnnaBridge	172:65be27845400	1184	{
AnnaBridge	172:65be27845400	1185	return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1186	}
AnnaBridge	172:65be27845400	1187
AnnaBridge	172:65be27845400	1188	/**
AnnaBridge	172:65be27845400	1189	* @brief Indicates if the Product is working on the full voltage range or not
AnnaBridge	172:65be27845400	1190	* @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV
AnnaBridge	172:65be27845400	1191	* @note When the IOHSLV option bit is set the Product is working below 2.7 V.
AnnaBridge	172:65be27845400	1192	* When the IOHSLV option bit is reset the Product is working on the
AnnaBridge	172:65be27845400	1193	* full voltage range.
AnnaBridge	172:65be27845400	1194	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1195	*/
AnnaBridge	172:65be27845400	1196	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
AnnaBridge	172:65be27845400	1197	{
AnnaBridge	172:65be27845400	1198	return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1199	}
AnnaBridge	172:65be27845400	1200
AnnaBridge	172:65be27845400	1201	/**
AnnaBridge	172:65be27845400	1202	* @}
AnnaBridge	172:65be27845400	1203	*/
AnnaBridge	172:65be27845400	1204
AnnaBridge	172:65be27845400	1205	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
AnnaBridge	172:65be27845400	1206	* @{
AnnaBridge	172:65be27845400	1207	*/
AnnaBridge	172:65be27845400	1208
AnnaBridge	172:65be27845400	1209	/**
AnnaBridge	172:65be27845400	1210	* @brief Return the device identifier
AnnaBridge	172:65be27845400	1211	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
AnnaBridge	172:65be27845400	1212	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1213	*/
AnnaBridge	172:65be27845400	1214	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
AnnaBridge	172:65be27845400	1215	{
AnnaBridge	172:65be27845400	1216	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
AnnaBridge	172:65be27845400	1217	}
AnnaBridge	172:65be27845400	1218
AnnaBridge	172:65be27845400	1219	/**
AnnaBridge	172:65be27845400	1220	* @brief Return the device revision identifier
AnnaBridge	172:65be27845400	1221	* @note This field indicates the revision of the device.
AnnaBridge	172:65be27845400	1222	For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
AnnaBridge	172:65be27845400	1223	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
AnnaBridge	172:65be27845400	1224	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	172:65be27845400	1225	*/
AnnaBridge	172:65be27845400	1226	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
AnnaBridge	172:65be27845400	1227	{
AnnaBridge	172:65be27845400	1228	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
AnnaBridge	172:65be27845400	1229	}
AnnaBridge	172:65be27845400	1230
AnnaBridge	172:65be27845400	1231	/**
AnnaBridge	172:65be27845400	1232	* @brief Enable D1 Domain debug during SLEEP mode
AnnaBridge	172:65be27845400	1233	* @rmtoll DBGMCU_CR DBGSLEEP_D1 LL_DBGMCU_EnableD1DebugInSleepMode
AnnaBridge	172:65be27845400	1234	* @retval None
AnnaBridge	172:65be27845400	1235	*/
AnnaBridge	172:65be27845400	1236	__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
AnnaBridge	172:65be27845400	1237	{
AnnaBridge	172:65be27845400	1238	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
AnnaBridge	172:65be27845400	1239	}
AnnaBridge	172:65be27845400	1240
AnnaBridge	172:65be27845400	1241	/**
AnnaBridge	172:65be27845400	1242	* @brief Disable D1 Domain debug during SLEEP mode
AnnaBridge	172:65be27845400	1243	* @rmtoll DBGMCU_CR DBGSLEEP_D1 LL_DBGMCU_DisableD1DebugInSleepMode
AnnaBridge	172:65be27845400	1244	* @retval None
AnnaBridge	172:65be27845400	1245	*/
AnnaBridge	172:65be27845400	1246	__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
AnnaBridge	172:65be27845400	1247	{
AnnaBridge	172:65be27845400	1248	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
AnnaBridge	172:65be27845400	1249	}
AnnaBridge	172:65be27845400	1250
AnnaBridge	172:65be27845400	1251	/**
AnnaBridge	172:65be27845400	1252	* @brief Enable D1 Domain debug during STOP mode
AnnaBridge	172:65be27845400	1253	* @rmtoll DBGMCU_CR DBGSTOP_D1 LL_DBGMCU_EnableD1DebugInStopMode
AnnaBridge	172:65be27845400	1254	* @retval None
AnnaBridge	172:65be27845400	1255	*/
AnnaBridge	172:65be27845400	1256	__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
AnnaBridge	172:65be27845400	1257	{
AnnaBridge	172:65be27845400	1258	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
AnnaBridge	172:65be27845400	1259	}
AnnaBridge	172:65be27845400	1260
AnnaBridge	172:65be27845400	1261	/**
AnnaBridge	172:65be27845400	1262	* @brief Disable D1 Domain debug during STOP mode
AnnaBridge	172:65be27845400	1263	* @rmtoll DBGMCU_CR DBGSTOP_D1 LL_DBGMCU_DisableD1DebugInStopMode
AnnaBridge	172:65be27845400	1264	* @retval None
AnnaBridge	172:65be27845400	1265	*/
AnnaBridge	172:65be27845400	1266	__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
AnnaBridge	172:65be27845400	1267	{
AnnaBridge	172:65be27845400	1268	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
AnnaBridge	172:65be27845400	1269	}
AnnaBridge	172:65be27845400	1270
AnnaBridge	172:65be27845400	1271	/**
AnnaBridge	172:65be27845400	1272	* @brief Enable D1 Domain debug during STANDBY mode
AnnaBridge	172:65be27845400	1273	* @rmtoll DBGMCU_CR DBGSTBY_D1 LL_DBGMCU_EnableD1DebugInStandbyMode
AnnaBridge	172:65be27845400	1274	* @retval None
AnnaBridge	172:65be27845400	1275	*/
AnnaBridge	172:65be27845400	1276	__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
AnnaBridge	172:65be27845400	1277	{
AnnaBridge	172:65be27845400	1278	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
AnnaBridge	172:65be27845400	1279	}
AnnaBridge	172:65be27845400	1280
AnnaBridge	172:65be27845400	1281	/**
AnnaBridge	172:65be27845400	1282	* @brief Disable D1 Domain debug during STANDBY mode
AnnaBridge	172:65be27845400	1283	* @rmtoll DBGMCU_CR DBGSTBY_D1 LL_DBGMCU_DisableD1DebugInStandbyMode
AnnaBridge	172:65be27845400	1284	* @retval None
AnnaBridge	172:65be27845400	1285	*/
AnnaBridge	172:65be27845400	1286	__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
AnnaBridge	172:65be27845400	1287	{
AnnaBridge	172:65be27845400	1288	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
AnnaBridge	172:65be27845400	1289	}
AnnaBridge	172:65be27845400	1290
AnnaBridge	172:65be27845400	1291
AnnaBridge	172:65be27845400	1292	/**
AnnaBridge	172:65be27845400	1293	* @brief Enable D3 Domain debug during STOP mode
AnnaBridge	172:65be27845400	1294	* @rmtoll DBGMCU_CR DBGSTOP_D3 LL_DBGMCU_EnableD3DebugInStopMode
AnnaBridge	172:65be27845400	1295	* @retval None
AnnaBridge	172:65be27845400	1296	*/
AnnaBridge	172:65be27845400	1297	__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
AnnaBridge	172:65be27845400	1298	{
AnnaBridge	172:65be27845400	1299	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
AnnaBridge	172:65be27845400	1300	}
AnnaBridge	172:65be27845400	1301
AnnaBridge	172:65be27845400	1302	/**
AnnaBridge	172:65be27845400	1303	* @brief Disable D3 Domain debug during STOP mode
AnnaBridge	172:65be27845400	1304	* @rmtoll DBGMCU_CR DBGSTOP_D3 LL_DBGMCU_DisableD3DebugInStopMode
AnnaBridge	172:65be27845400	1305	* @retval None
AnnaBridge	172:65be27845400	1306	*/
AnnaBridge	172:65be27845400	1307	__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
AnnaBridge	172:65be27845400	1308	{
AnnaBridge	172:65be27845400	1309	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
AnnaBridge	172:65be27845400	1310	}
AnnaBridge	172:65be27845400	1311
AnnaBridge	172:65be27845400	1312	/**
AnnaBridge	172:65be27845400	1313	* @brief Enable D3 Domain debug during STANDBY mode
AnnaBridge	172:65be27845400	1314	* @rmtoll DBGMCU_CR DBGSTBY_D3 LL_DBGMCU_EnableD3DebugInStandbyMode
AnnaBridge	172:65be27845400	1315	* @retval None
AnnaBridge	172:65be27845400	1316	*/
AnnaBridge	172:65be27845400	1317	__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
AnnaBridge	172:65be27845400	1318	{
AnnaBridge	172:65be27845400	1319	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
AnnaBridge	172:65be27845400	1320	}
AnnaBridge	172:65be27845400	1321
AnnaBridge	172:65be27845400	1322	/**
AnnaBridge	172:65be27845400	1323	* @brief Disable D3 Domain debug during STANDBY mode
AnnaBridge	172:65be27845400	1324	* @rmtoll DBGMCU_CR DBGSTBY_D3 LL_DBGMCU_DisableD3DebugInStandbyMode
AnnaBridge	172:65be27845400	1325	* @retval None
AnnaBridge	172:65be27845400	1326	*/
AnnaBridge	172:65be27845400	1327	__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
AnnaBridge	172:65be27845400	1328	{
AnnaBridge	172:65be27845400	1329	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
AnnaBridge	172:65be27845400	1330	}
AnnaBridge	172:65be27845400	1331
AnnaBridge	172:65be27845400	1332	/**
AnnaBridge	172:65be27845400	1333	* @brief Enable the trace port clock
AnnaBridge	172:65be27845400	1334	* @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock
AnnaBridge	172:65be27845400	1335	* @retval None
AnnaBridge	172:65be27845400	1336	*/
AnnaBridge	172:65be27845400	1337	__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
AnnaBridge	172:65be27845400	1338	{
AnnaBridge	172:65be27845400	1339	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
AnnaBridge	172:65be27845400	1340	}
AnnaBridge	172:65be27845400	1341
AnnaBridge	172:65be27845400	1342	/**
AnnaBridge	172:65be27845400	1343	* @brief Disable the trace port clock
AnnaBridge	172:65be27845400	1344	* @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock
AnnaBridge	172:65be27845400	1345	* @retval None
AnnaBridge	172:65be27845400	1346	*/
AnnaBridge	172:65be27845400	1347	__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
AnnaBridge	172:65be27845400	1348	{
AnnaBridge	172:65be27845400	1349	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
AnnaBridge	172:65be27845400	1350	}
AnnaBridge	172:65be27845400	1351
AnnaBridge	172:65be27845400	1352	/**
AnnaBridge	172:65be27845400	1353	* @brief Enable the D1 debug clock enable
AnnaBridge	172:65be27845400	1354	* @rmtoll DBGMCU_CR CKD1EN LL_DBGMCU_EnableD1DebugClock
AnnaBridge	172:65be27845400	1355	* @retval None
AnnaBridge	172:65be27845400	1356	*/
AnnaBridge	172:65be27845400	1357	__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
AnnaBridge	172:65be27845400	1358	{
AnnaBridge	172:65be27845400	1359	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
AnnaBridge	172:65be27845400	1360	}
AnnaBridge	172:65be27845400	1361
AnnaBridge	172:65be27845400	1362	/**
AnnaBridge	172:65be27845400	1363	* @brief Disable the D1 debug clock enable
AnnaBridge	172:65be27845400	1364	* @rmtoll DBGMCU_CR CKD1EN LL_DBGMCU_DisableD1DebugClock
AnnaBridge	172:65be27845400	1365	* @retval None
AnnaBridge	172:65be27845400	1366	*/
AnnaBridge	172:65be27845400	1367	__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
AnnaBridge	172:65be27845400	1368	{
AnnaBridge	172:65be27845400	1369	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
AnnaBridge	172:65be27845400	1370	}
AnnaBridge	172:65be27845400	1371
AnnaBridge	172:65be27845400	1372	/**
AnnaBridge	172:65be27845400	1373	* @brief Enable the D3 debug clock enable
AnnaBridge	172:65be27845400	1374	* @rmtoll DBGMCU_CR CKD3EN LL_DBGMCU_EnableD3DebugClock
AnnaBridge	172:65be27845400	1375	* @retval None
AnnaBridge	172:65be27845400	1376	*/
AnnaBridge	172:65be27845400	1377	__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
AnnaBridge	172:65be27845400	1378	{
AnnaBridge	172:65be27845400	1379	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
AnnaBridge	172:65be27845400	1380	}
AnnaBridge	172:65be27845400	1381
AnnaBridge	172:65be27845400	1382	/**
AnnaBridge	172:65be27845400	1383	* @brief Disable the D3 debug clock enable
AnnaBridge	172:65be27845400	1384	* @rmtoll DBGMCU_CR CKD3EN LL_DBGMCU_DisableD3DebugClock
AnnaBridge	172:65be27845400	1385	* @retval None
AnnaBridge	172:65be27845400	1386	*/
AnnaBridge	172:65be27845400	1387	__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
AnnaBridge	172:65be27845400	1388	{
AnnaBridge	172:65be27845400	1389	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
AnnaBridge	172:65be27845400	1390	}
AnnaBridge	172:65be27845400	1391
AnnaBridge	172:65be27845400	1392	#define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
AnnaBridge	172:65be27845400	1393	#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN
AnnaBridge	172:65be27845400	1394	/**
AnnaBridge	172:65be27845400	1395	* @brief Set the direction of the bi-directional trigger pin TRGIO
AnnaBridge	172:65be27845400	1396	* @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n
AnnaBridge	172:65be27845400	1397	* @param PinDirection This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1398	* @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
AnnaBridge	172:65be27845400	1399	* @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
AnnaBridge	172:65be27845400	1400	* @retval None
AnnaBridge	172:65be27845400	1401	*/
AnnaBridge	172:65be27845400	1402	__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
AnnaBridge	172:65be27845400	1403	{
AnnaBridge	172:65be27845400	1404	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
AnnaBridge	172:65be27845400	1405	}
AnnaBridge	172:65be27845400	1406
AnnaBridge	172:65be27845400	1407	/**
AnnaBridge	172:65be27845400	1408	* @brief Get the direction of the bi-directional trigger pin TRGIO
AnnaBridge	172:65be27845400	1409	* @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n
AnnaBridge	172:65be27845400	1410	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1411	* @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
AnnaBridge	172:65be27845400	1412	* @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
AnnaBridge	172:65be27845400	1413	*/
AnnaBridge	172:65be27845400	1414	__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
AnnaBridge	172:65be27845400	1415	{
AnnaBridge	172:65be27845400	1416	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
AnnaBridge	172:65be27845400	1417	}
AnnaBridge	172:65be27845400	1418
AnnaBridge	172:65be27845400	1419	/**
AnnaBridge	172:65be27845400	1420	* @brief Freeze APB1 group1 peripherals
AnnaBridge	172:65be27845400	1421	* @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1422	* DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1423	* DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1424	* DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1425	* DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1426	* DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1427	* DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1428	* DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1429	* DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1430	* DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1431	* DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1432	* DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1433	* DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1434	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1435	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
AnnaBridge	172:65be27845400	1436	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
AnnaBridge	172:65be27845400	1437	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
AnnaBridge	172:65be27845400	1438	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
AnnaBridge	172:65be27845400	1439	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
AnnaBridge	172:65be27845400	1440	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
AnnaBridge	172:65be27845400	1441	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
AnnaBridge	172:65be27845400	1442	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
AnnaBridge	172:65be27845400	1443	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
AnnaBridge	172:65be27845400	1444	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
AnnaBridge	172:65be27845400	1445	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	172:65be27845400	1446	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
AnnaBridge	172:65be27845400	1447	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
AnnaBridge	172:65be27845400	1448	* @retval None
AnnaBridge	172:65be27845400	1449	*/
AnnaBridge	172:65be27845400	1450	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1451	{
AnnaBridge	172:65be27845400	1452	SET_BIT(DBGMCU->APB1LFZ1, Periphs);
AnnaBridge	172:65be27845400	1453	}
AnnaBridge	172:65be27845400	1454
AnnaBridge	172:65be27845400	1455	/**
AnnaBridge	172:65be27845400	1456	* @brief Unfreeze APB1 peripherals (group1 peripherals)
AnnaBridge	172:65be27845400	1457	* @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1458	* DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1459	* DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1460	* DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1461	* DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1462	* DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1463	* DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1464	* DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1465	* DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1466	* DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1467	* DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1468	* DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1469	* DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1470	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1471	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
AnnaBridge	172:65be27845400	1472	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
AnnaBridge	172:65be27845400	1473	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
AnnaBridge	172:65be27845400	1474	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
AnnaBridge	172:65be27845400	1475	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
AnnaBridge	172:65be27845400	1476	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
AnnaBridge	172:65be27845400	1477	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
AnnaBridge	172:65be27845400	1478	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
AnnaBridge	172:65be27845400	1479	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
AnnaBridge	172:65be27845400	1480	* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
AnnaBridge	172:65be27845400	1481	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	172:65be27845400	1482	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
AnnaBridge	172:65be27845400	1483	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
AnnaBridge	172:65be27845400	1484	* @retval None
AnnaBridge	172:65be27845400	1485	*/
AnnaBridge	172:65be27845400	1486	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1487	{
AnnaBridge	172:65be27845400	1488	CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
AnnaBridge	172:65be27845400	1489	}
AnnaBridge	172:65be27845400	1490
AnnaBridge	172:65be27845400	1491	/**
AnnaBridge	172:65be27845400	1492	* @brief Freeze APB1 group2 peripherals
AnnaBridge	172:65be27845400	1493	* @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n
AnnaBridge	172:65be27845400	1494	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1495	* @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
AnnaBridge	172:65be27845400	1496	* @retval None
AnnaBridge	172:65be27845400	1497	*/
AnnaBridge	172:65be27845400	1498	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1499	{
AnnaBridge	172:65be27845400	1500	SET_BIT(DBGMCU->APB1HFZ1, Periphs);
AnnaBridge	172:65be27845400	1501	}
AnnaBridge	172:65be27845400	1502
AnnaBridge	172:65be27845400	1503	/**
AnnaBridge	172:65be27845400	1504	* @brief Unfreeze APB1 group2 peripherals
AnnaBridge	172:65be27845400	1505	* @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
AnnaBridge	172:65be27845400	1506	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1507	* @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
AnnaBridge	172:65be27845400	1508	* @retval None
AnnaBridge	172:65be27845400	1509	*/
AnnaBridge	172:65be27845400	1510	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1511	{
AnnaBridge	172:65be27845400	1512	CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
AnnaBridge	172:65be27845400	1513	}
AnnaBridge	172:65be27845400	1514
AnnaBridge	172:65be27845400	1515	/**
AnnaBridge	172:65be27845400	1516	* @brief Freeze APB2 peripherals
AnnaBridge	172:65be27845400	1517	* @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1518	* DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1519	* DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1520	* DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1521	* DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
AnnaBridge	172:65be27845400	1522	* DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
AnnaBridge	172:65be27845400	1523	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1524	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
AnnaBridge	172:65be27845400	1525	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
AnnaBridge	172:65be27845400	1526	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
AnnaBridge	172:65be27845400	1527	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
AnnaBridge	172:65be27845400	1528	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
AnnaBridge	172:65be27845400	1529	* @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
AnnaBridge	172:65be27845400	1530	* @retval None
AnnaBridge	172:65be27845400	1531	*/
AnnaBridge	172:65be27845400	1532	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1533	{
AnnaBridge	172:65be27845400	1534	SET_BIT(DBGMCU->APB2FZ1, Periphs);
AnnaBridge	172:65be27845400	1535	}
AnnaBridge	172:65be27845400	1536
AnnaBridge	172:65be27845400	1537	/**
AnnaBridge	172:65be27845400	1538	* @brief Unfreeze APB2 peripherals
AnnaBridge	172:65be27845400	1539	* @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1540	* DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1541	* DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1542	* DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1543	* DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
AnnaBridge	172:65be27845400	1544	* DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
AnnaBridge	172:65be27845400	1545	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1546	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
AnnaBridge	172:65be27845400	1547	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
AnnaBridge	172:65be27845400	1548	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
AnnaBridge	172:65be27845400	1549	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
AnnaBridge	172:65be27845400	1550	* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
AnnaBridge	172:65be27845400	1551	* @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP
AnnaBridge	172:65be27845400	1552	* @retval None
AnnaBridge	172:65be27845400	1553	*/
AnnaBridge	172:65be27845400	1554	__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1555	{
AnnaBridge	172:65be27845400	1556	CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
AnnaBridge	172:65be27845400	1557	}
AnnaBridge	172:65be27845400	1558
AnnaBridge	172:65be27845400	1559	/**
AnnaBridge	172:65be27845400	1560	* @brief Freeze APB3 peripherals
AnnaBridge	172:65be27845400	1561	* @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1562	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1563	* @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
AnnaBridge	172:65be27845400	1564	* @retval None
AnnaBridge	172:65be27845400	1565	*/
AnnaBridge	172:65be27845400	1566	__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1567	{
AnnaBridge	172:65be27845400	1568	SET_BIT(DBGMCU->APB3FZ1, Periphs);
AnnaBridge	172:65be27845400	1569	}
AnnaBridge	172:65be27845400	1570
AnnaBridge	172:65be27845400	1571	/**
AnnaBridge	172:65be27845400	1572	* @brief Unfreeze APB3 peripherals
AnnaBridge	172:65be27845400	1573	* @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
AnnaBridge	172:65be27845400	1574	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1575	* @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
AnnaBridge	172:65be27845400	1576	* @retval None
AnnaBridge	172:65be27845400	1577	*/
AnnaBridge	172:65be27845400	1578	__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1579	{
AnnaBridge	172:65be27845400	1580	CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
AnnaBridge	172:65be27845400	1581	}
AnnaBridge	172:65be27845400	1582
AnnaBridge	172:65be27845400	1583	/**
AnnaBridge	172:65be27845400	1584	* @brief Freeze APB4 peripherals
AnnaBridge	172:65be27845400	1585	* @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1586	* @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1587	* @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1588	* @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1589	* @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1590	* @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1591	* @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1592	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1593	* @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
AnnaBridge	172:65be27845400	1594	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
AnnaBridge	172:65be27845400	1595	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
AnnaBridge	172:65be27845400	1596	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
AnnaBridge	172:65be27845400	1597	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
AnnaBridge	172:65be27845400	1598	* @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
AnnaBridge	172:65be27845400	1599	* @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
AnnaBridge	172:65be27845400	1600	* @retval None
AnnaBridge	172:65be27845400	1601	*/
AnnaBridge	172:65be27845400	1602	__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1603	{
AnnaBridge	172:65be27845400	1604	SET_BIT(DBGMCU->APB4FZ1, Periphs);
AnnaBridge	172:65be27845400	1605	}
AnnaBridge	172:65be27845400	1606
AnnaBridge	172:65be27845400	1607	/**
AnnaBridge	172:65be27845400	1608	* @brief Unfreeze APB4 peripherals
AnnaBridge	172:65be27845400	1609	* @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1610	* @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1611	* @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1612	* @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1613	* @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1614	* @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1615	* @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
AnnaBridge	172:65be27845400	1616	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1617	* @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
AnnaBridge	172:65be27845400	1618	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
AnnaBridge	172:65be27845400	1619	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
AnnaBridge	172:65be27845400	1620	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
AnnaBridge	172:65be27845400	1621	* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
AnnaBridge	172:65be27845400	1622	* @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
AnnaBridge	172:65be27845400	1623	* @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
AnnaBridge	172:65be27845400	1624	* @retval None
AnnaBridge	172:65be27845400	1625	*/
AnnaBridge	172:65be27845400	1626	__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	172:65be27845400	1627	{
AnnaBridge	172:65be27845400	1628	CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
AnnaBridge	172:65be27845400	1629	}
AnnaBridge	172:65be27845400	1630	/**
AnnaBridge	172:65be27845400	1631	* @}
AnnaBridge	172:65be27845400	1632	*/
AnnaBridge	172:65be27845400	1633
AnnaBridge	172:65be27845400	1634	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
AnnaBridge	172:65be27845400	1635	* @{
AnnaBridge	172:65be27845400	1636	*/
AnnaBridge	172:65be27845400	1637
AnnaBridge	172:65be27845400	1638	/**
AnnaBridge	172:65be27845400	1639	* @brief Set FLASH Latency
AnnaBridge	172:65be27845400	1640	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
AnnaBridge	172:65be27845400	1641	* @param Latency This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1642	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	172:65be27845400	1643	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	172:65be27845400	1644	* @arg @ref LL_FLASH_LATENCY_2
AnnaBridge	172:65be27845400	1645	* @arg @ref LL_FLASH_LATENCY_3
AnnaBridge	172:65be27845400	1646	* @arg @ref LL_FLASH_LATENCY_4
AnnaBridge	172:65be27845400	1647	* @arg @ref LL_FLASH_LATENCY_5
AnnaBridge	172:65be27845400	1648	* @arg @ref LL_FLASH_LATENCY_6
AnnaBridge	172:65be27845400	1649	* @arg @ref LL_FLASH_LATENCY_7
AnnaBridge	172:65be27845400	1650	* @retval None
AnnaBridge	172:65be27845400	1651	*/
AnnaBridge	172:65be27845400	1652	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
AnnaBridge	172:65be27845400	1653	{
AnnaBridge	172:65be27845400	1654	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
AnnaBridge	172:65be27845400	1655	}
AnnaBridge	172:65be27845400	1656
AnnaBridge	172:65be27845400	1657	/**
AnnaBridge	172:65be27845400	1658	* @brief Get FLASH Latency
AnnaBridge	172:65be27845400	1659	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
AnnaBridge	172:65be27845400	1660	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1661	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	172:65be27845400	1662	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	172:65be27845400	1663	* @arg @ref LL_FLASH_LATENCY_2
AnnaBridge	172:65be27845400	1664	* @arg @ref LL_FLASH_LATENCY_3
AnnaBridge	172:65be27845400	1665	* @arg @ref LL_FLASH_LATENCY_4
AnnaBridge	172:65be27845400	1666	* @arg @ref LL_FLASH_LATENCY_5
AnnaBridge	172:65be27845400	1667	* @arg @ref LL_FLASH_LATENCY_6
AnnaBridge	172:65be27845400	1668	* @arg @ref LL_FLASH_LATENCY_7
AnnaBridge	172:65be27845400	1669	*/
AnnaBridge	172:65be27845400	1670	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
AnnaBridge	172:65be27845400	1671	{
AnnaBridge	172:65be27845400	1672	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
AnnaBridge	172:65be27845400	1673	}
AnnaBridge	172:65be27845400	1674
AnnaBridge	172:65be27845400	1675	/**
AnnaBridge	172:65be27845400	1676	* @}
AnnaBridge	172:65be27845400	1677	*/
AnnaBridge	172:65be27845400	1678
AnnaBridge	172:65be27845400	1679	/**
AnnaBridge	172:65be27845400	1680	* @}
AnnaBridge	172:65be27845400	1681	*/
AnnaBridge	172:65be27845400	1682
AnnaBridge	172:65be27845400	1683	/**
AnnaBridge	172:65be27845400	1684	* @}
AnnaBridge	172:65be27845400	1685	*/
AnnaBridge	172:65be27845400	1686
AnnaBridge	172:65be27845400	1687	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
AnnaBridge	172:65be27845400	1688
AnnaBridge	172:65be27845400	1689	/**
AnnaBridge	172:65be27845400	1690	* @}
AnnaBridge	172:65be27845400	1691	*/
AnnaBridge	172:65be27845400	1692
AnnaBridge	172:65be27845400	1693	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1694	}
AnnaBridge	172:65be27845400	1695	#endif
AnnaBridge	172:65be27845400	1696
AnnaBridge	172:65be27845400	1697	#endif /* __STM32H7xx_LL_SYSTEM_H */
AnnaBridge	172:65be27845400	1698
AnnaBridge	172:65be27845400	1699	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/