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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_ll_dac.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_dac.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of DAC LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef __STM32H7xx_LL_DAC_H
AnnaBridge	172:65be27845400	22	#define __STM32H7xx_LL_DAC_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	#if defined (DAC1)
AnnaBridge	172:65be27845400	36
AnnaBridge	172:65be27845400	37	/** @defgroup DAC_LL DAC
AnnaBridge	172:65be27845400	38	* @{
AnnaBridge	172:65be27845400	39	*/
AnnaBridge	172:65be27845400	40
AnnaBridge	172:65be27845400	41	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	42	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
AnnaBridge	172:65be27845400	46	* @{
AnnaBridge	172:65be27845400	47	*/
AnnaBridge	172:65be27845400	48
AnnaBridge	172:65be27845400	49	/* Internal masks for DAC channels definition */
AnnaBridge	172:65be27845400	50	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
AnnaBridge	172:65be27845400	51	/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
AnnaBridge	172:65be27845400	52	/* - channel bits position into register SWTRIG */
AnnaBridge	172:65be27845400	53	/* - channel register offset of data holding register DHRx */
AnnaBridge	172:65be27845400	54	/* - channel register offset of data output register DORx */
AnnaBridge	172:65be27845400	55	/* - channel register offset of sample-and-hold sample time register SHSRx */
AnnaBridge	172:65be27845400	56
AnnaBridge	172:65be27845400	57	#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
AnnaBridge	172:65be27845400	58	#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
AnnaBridge	172:65be27845400	59	#define DAC_CR_CHX_BITOFFSET_MASK (uint32_t)(DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
AnnaBridge	172:65be27845400	60
AnnaBridge	172:65be27845400	61	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
AnnaBridge	172:65be27845400	62	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
AnnaBridge	172:65be27845400	63	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
AnnaBridge	172:65be27845400	64
AnnaBridge	172:65be27845400	65	#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
AnnaBridge	172:65be27845400	66	#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	172:65be27845400	67	#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	172:65be27845400	68	#define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
AnnaBridge	172:65be27845400	69	#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	172:65be27845400	70	#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	172:65be27845400	71	#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U
AnnaBridge	172:65be27845400	72	#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
AnnaBridge	172:65be27845400	73	#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
AnnaBridge	172:65be27845400	74	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
AnnaBridge	172:65be27845400	75
AnnaBridge	172:65be27845400	76	#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
AnnaBridge	172:65be27845400	77	#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
AnnaBridge	172:65be27845400	78	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	#define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */
AnnaBridge	172:65be27845400	81	#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
AnnaBridge	172:65be27845400	82	#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_SHSR2_REGOFFSET)
AnnaBridge	172:65be27845400	83
AnnaBridge	172:65be27845400	84	#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
AnnaBridge	172:65be27845400	85	#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */
AnnaBridge	172:65be27845400	86	#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */
AnnaBridge	172:65be27845400	87
AnnaBridge	172:65be27845400	88	#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
AnnaBridge	172:65be27845400	89	#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	172:65be27845400	90	#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	172:65be27845400	91	#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
AnnaBridge	172:65be27845400	92	#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
AnnaBridge	172:65be27845400	93
AnnaBridge	172:65be27845400	94	/* DAC registers bits positions */
AnnaBridge	172:65be27845400	95	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
AnnaBridge	172:65be27845400	96	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
AnnaBridge	172:65be27845400	97	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
AnnaBridge	172:65be27845400	98
AnnaBridge	172:65be27845400	99	/* Miscellaneous data */
AnnaBridge	172:65be27845400	100	#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
AnnaBridge	172:65be27845400	101
AnnaBridge	172:65be27845400	102	/**
AnnaBridge	172:65be27845400	103	* @}
AnnaBridge	172:65be27845400	104	*/
AnnaBridge	172:65be27845400	105
AnnaBridge	172:65be27845400	106
AnnaBridge	172:65be27845400	107	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	108	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
AnnaBridge	172:65be27845400	109	* @{
AnnaBridge	172:65be27845400	110	*/
AnnaBridge	172:65be27845400	111
AnnaBridge	172:65be27845400	112	/**
AnnaBridge	172:65be27845400	113	* @brief Driver macro reserved for internal use: set a pointer to
AnnaBridge	172:65be27845400	114	* a register from a register basis from which an offset
AnnaBridge	172:65be27845400	115	* is applied.
AnnaBridge	172:65be27845400	116	* @param __REG__ Register basis from which the offset is applied.
AnnaBridge	172:65be27845400	117	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
AnnaBridge	172:65be27845400	118	* @retval Pointer to register address
AnnaBridge	172:65be27845400	119	*/
AnnaBridge	172:65be27845400	120	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
AnnaBridge	172:65be27845400	121	((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
AnnaBridge	172:65be27845400	122
AnnaBridge	172:65be27845400	123	/**
AnnaBridge	172:65be27845400	124	* @}
AnnaBridge	172:65be27845400	125	*/
AnnaBridge	172:65be27845400	126
AnnaBridge	172:65be27845400	127
AnnaBridge	172:65be27845400	128	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	129	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	130	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
AnnaBridge	172:65be27845400	131	* @{
AnnaBridge	172:65be27845400	132	*/
AnnaBridge	172:65be27845400	133
AnnaBridge	172:65be27845400	134	/**
AnnaBridge	172:65be27845400	135	* @brief Structure definition of some features of DAC instance.
AnnaBridge	172:65be27845400	136	*/
AnnaBridge	172:65be27845400	137	typedef struct
AnnaBridge	172:65be27845400	138	{
AnnaBridge	172:65be27845400	139	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
AnnaBridge	172:65be27845400	140	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
AnnaBridge	172:65be27845400	141
AnnaBridge	172:65be27845400	142	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
AnnaBridge	172:65be27845400	143
AnnaBridge	172:65be27845400	144	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	172:65be27845400	145	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
AnnaBridge	172:65be27845400	146
AnnaBridge	172:65be27845400	147	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
AnnaBridge	172:65be27845400	148
AnnaBridge	172:65be27845400	149	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	172:65be27845400	150	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
AnnaBridge	172:65be27845400	151	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
AnnaBridge	172:65be27845400	152	@note If waveform automatic generation mode is disabled, this parameter is discarded.
AnnaBridge	172:65be27845400	153
AnnaBridge	172:65be27845400	154	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()
AnnaBridge	172:65be27845400	155	depending on the wave automatic generation selected. */
AnnaBridge	172:65be27845400	156
AnnaBridge	172:65be27845400	157	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
AnnaBridge	172:65be27845400	158	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
AnnaBridge	172:65be27845400	159
AnnaBridge	172:65be27845400	160	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
AnnaBridge	172:65be27845400	163	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
AnnaBridge	172:65be27845400	164
AnnaBridge	172:65be27845400	165	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
AnnaBridge	172:65be27845400	166
AnnaBridge	172:65be27845400	167	uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
AnnaBridge	172:65be27845400	168	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
AnnaBridge	172:65be27845400	169
AnnaBridge	172:65be27845400	170	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
AnnaBridge	172:65be27845400	171
AnnaBridge	172:65be27845400	172	} LL_DAC_InitTypeDef;
AnnaBridge	172:65be27845400	173
AnnaBridge	172:65be27845400	174	/**
AnnaBridge	172:65be27845400	175	* @}
AnnaBridge	172:65be27845400	176	*/
AnnaBridge	172:65be27845400	177	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	178
AnnaBridge	172:65be27845400	179	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	180	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
AnnaBridge	172:65be27845400	181	* @{
AnnaBridge	172:65be27845400	182	*/
AnnaBridge	172:65be27845400	183
AnnaBridge	172:65be27845400	184	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
AnnaBridge	172:65be27845400	185	* @brief Flags defines which can be used with LL_DAC_ReadReg function
AnnaBridge	172:65be27845400	186	* @{
AnnaBridge	172:65be27845400	187	*/
AnnaBridge	172:65be27845400	188	/* DAC channel 1 flags */
AnnaBridge	172:65be27845400	189	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
AnnaBridge	172:65be27845400	190	#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /!< DAC channel 1 flag offset calibration status /
AnnaBridge	172:65be27845400	191	#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /!< DAC channel 1 flag busy writing sample time /
AnnaBridge	172:65be27845400	192
AnnaBridge	172:65be27845400	193	/* DAC channel 2 flags */
AnnaBridge	172:65be27845400	194	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
AnnaBridge	172:65be27845400	195	#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /!< DAC channel 2 flag offset calibration status /
AnnaBridge	172:65be27845400	196	#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /!< DAC channel 2 flag busy writing sample time /
AnnaBridge	172:65be27845400	197	/**
AnnaBridge	172:65be27845400	198	* @}
AnnaBridge	172:65be27845400	199	*/
AnnaBridge	172:65be27845400	200
AnnaBridge	172:65be27845400	201	/** @defgroup DAC_LL_EC_IT DAC interruptions
AnnaBridge	172:65be27845400	202	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
AnnaBridge	172:65be27845400	203	* @{
AnnaBridge	172:65be27845400	204	*/
AnnaBridge	172:65be27845400	205	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
AnnaBridge	172:65be27845400	206	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
AnnaBridge	172:65be27845400	207	/**
AnnaBridge	172:65be27845400	208	* @}
AnnaBridge	172:65be27845400	209	*/
AnnaBridge	172:65be27845400	210
AnnaBridge	172:65be27845400	211	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
AnnaBridge	172:65be27845400	212	* @{
AnnaBridge	172:65be27845400	213	*/
AnnaBridge	172:65be27845400	214	#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET \| DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
AnnaBridge	172:65be27845400	215	#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET \| DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
AnnaBridge	172:65be27845400	216	/**
AnnaBridge	172:65be27845400	217	* @}
AnnaBridge	172:65be27845400	218	*/
AnnaBridge	172:65be27845400	219
AnnaBridge	172:65be27845400	220	/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
AnnaBridge	172:65be27845400	221	* @{
AnnaBridge	172:65be27845400	222	*/
AnnaBridge	172:65be27845400	223	#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /!< DAC channel in mode normal operation /
AnnaBridge	172:65be27845400	224	#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /!< DAC channel in mode calibration /
AnnaBridge	172:65be27845400	225	/**
AnnaBridge	172:65be27845400	226	* @}
AnnaBridge	172:65be27845400	227	*/
AnnaBridge	172:65be27845400	228
AnnaBridge	172:65be27845400	229	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
AnnaBridge	172:65be27845400	230	* @{
AnnaBridge	172:65be27845400	231	*/
AnnaBridge	172:65be27845400	232	#define LL_DAC_TRIG_SOFTWARE 0x00000000U /!< DAC channel conversion trigger internal (SW start) /
AnnaBridge	172:65be27845400	233	#define LL_DAC_TRIG_EXT_TIM1_TRGO DAC_CR_TSEL1_0 /!< DAC channel conversion trigger from external IP: TIM1 TRGO. /
AnnaBridge	172:65be27845400	234	#define LL_DAC_TRIG_EXT_TIM2_TRGO DAC_CR_TSEL1_1 /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
AnnaBridge	172:65be27845400	235	#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
AnnaBridge	172:65be27845400	236	#define LL_DAC_TRIG_EXT_TIM5_TRGO DAC_CR_TSEL1_2 /!< DAC channel conversion trigger from external IP: TIM5 TRGO. /
AnnaBridge	172:65be27845400	237	#define LL_DAC_TRIG_EXT_TIM6_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
AnnaBridge	172:65be27845400	238	#define LL_DAC_TRIG_EXT_TIM7_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
AnnaBridge	172:65be27845400	239	#define LL_DAC_TRIG_EXT_TIM8_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM8 TRGO. /
AnnaBridge	172:65be27845400	240	#define LL_DAC_TRIG_EXT_TIM15_TRGO DAC_CR_TSEL1_3 /!< DAC channel conversion trigger from external IP: TIM15 TRGO. /
AnnaBridge	172:65be27845400	241	#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_0) /!< HR1 TRGO1 selected as external conversion trigger for DAC channel /
AnnaBridge	172:65be27845400	242	#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_1) /!< HR1 TRGO2 selected as external conversion trigger for DAC channel /
AnnaBridge	172:65be27845400	243	#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: LPTIM1 TRGO. /
AnnaBridge	172:65be27845400	244	#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_2) /!< DAC channel conversion trigger from external IP: LPTIM2 TRGO. /
AnnaBridge	172:65be27845400	245	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 \| DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
AnnaBridge	172:65be27845400	246	/**
AnnaBridge	172:65be27845400	247	* @}
AnnaBridge	172:65be27845400	248	*/
AnnaBridge	172:65be27845400	249
AnnaBridge	172:65be27845400	250	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
AnnaBridge	172:65be27845400	251	* @{
AnnaBridge	172:65be27845400	252	*/
AnnaBridge	172:65be27845400	253	#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /!< DAC channel wave auto generation mode disabled. /
AnnaBridge	172:65be27845400	254	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
AnnaBridge	172:65be27845400	255	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
AnnaBridge	172:65be27845400	256	/**
AnnaBridge	172:65be27845400	257	* @}
AnnaBridge	172:65be27845400	258	*/
AnnaBridge	172:65be27845400	259
AnnaBridge	172:65be27845400	260	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
AnnaBridge	172:65be27845400	261	* @{
AnnaBridge	172:65be27845400	262	*/
AnnaBridge	172:65be27845400	263	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
AnnaBridge	172:65be27845400	264	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	265	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	266	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	267	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	268	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	269	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	270	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	271	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	272	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	273	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	274	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
AnnaBridge	172:65be27845400	275	/**
AnnaBridge	172:65be27845400	276	* @}
AnnaBridge	172:65be27845400	277	*/
AnnaBridge	172:65be27845400	278
AnnaBridge	172:65be27845400	279	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
AnnaBridge	172:65be27845400	280	* @{
AnnaBridge	172:65be27845400	281	*/
AnnaBridge	172:65be27845400	282	#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	283	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	284	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	285	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	286	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	287	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	288	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	289	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	290	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	291	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	292	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	293	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	172:65be27845400	294	/**
AnnaBridge	172:65be27845400	295	* @}
AnnaBridge	172:65be27845400	296	*/
AnnaBridge	172:65be27845400	297
AnnaBridge	172:65be27845400	298	/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
AnnaBridge	172:65be27845400	299	* @{
AnnaBridge	172:65be27845400	300	*/
AnnaBridge	172:65be27845400	301	#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /!< The selected DAC channel output is on mode normal. /
AnnaBridge	172:65be27845400	302	#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). /
AnnaBridge	172:65be27845400	303	/**
AnnaBridge	172:65be27845400	304	* @}
AnnaBridge	172:65be27845400	305	*/
AnnaBridge	172:65be27845400	306
AnnaBridge	172:65be27845400	307	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
AnnaBridge	172:65be27845400	308	* @{
AnnaBridge	172:65be27845400	309	*/
AnnaBridge	172:65be27845400	310	#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
AnnaBridge	172:65be27845400	311	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
AnnaBridge	172:65be27845400	312	/**
AnnaBridge	172:65be27845400	313	* @}
AnnaBridge	172:65be27845400	314	*/
AnnaBridge	172:65be27845400	315
AnnaBridge	172:65be27845400	316	/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
AnnaBridge	172:65be27845400	317	* @{
AnnaBridge	172:65be27845400	318	*/
AnnaBridge	172:65be27845400	319	#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /!< The selected DAC channel output is connected to external pin /
AnnaBridge	172:65be27845400	320	#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). /
AnnaBridge	172:65be27845400	321	/**
AnnaBridge	172:65be27845400	322	* @}
AnnaBridge	172:65be27845400	323	*/
AnnaBridge	172:65be27845400	324
AnnaBridge	172:65be27845400	325	/** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
AnnaBridge	172:65be27845400	326	* @{
AnnaBridge	172:65be27845400	327	*/
AnnaBridge	172:65be27845400	328	#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
AnnaBridge	172:65be27845400	329	#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
AnnaBridge	172:65be27845400	330	#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
AnnaBridge	172:65be27845400	331	#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
AnnaBridge	172:65be27845400	332	#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
AnnaBridge	172:65be27845400	333	#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
AnnaBridge	172:65be27845400	334	#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
AnnaBridge	172:65be27845400	337	#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
AnnaBridge	172:65be27845400	338	#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
AnnaBridge	172:65be27845400	339
AnnaBridge	172:65be27845400	340	#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
AnnaBridge	172:65be27845400	341	#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
AnnaBridge	172:65be27845400	342	/**
AnnaBridge	172:65be27845400	343	* @}
AnnaBridge	172:65be27845400	344	*/
AnnaBridge	172:65be27845400	345
AnnaBridge	172:65be27845400	346	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
AnnaBridge	172:65be27845400	347	* @{
AnnaBridge	172:65be27845400	348	*/
AnnaBridge	172:65be27845400	349	#define LL_DAC_RESOLUTION_12B 0x00000000U /!< DAC channel resolution 12 bits /
AnnaBridge	172:65be27845400	350	#define LL_DAC_RESOLUTION_8B 0x00000002U /!< DAC channel resolution 8 bits /
AnnaBridge	172:65be27845400	351	/**
AnnaBridge	172:65be27845400	352	* @}
AnnaBridge	172:65be27845400	353	*/
AnnaBridge	172:65be27845400	354
AnnaBridge	172:65be27845400	355	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
AnnaBridge	172:65be27845400	356	* @{
AnnaBridge	172:65be27845400	357	*/
AnnaBridge	172:65be27845400	358	/* List of DAC registers intended to be used (most commonly) with */
AnnaBridge	172:65be27845400	359	/* DMA transfer. */
AnnaBridge	172:65be27845400	360	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
AnnaBridge	172:65be27845400	361	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits right aligned /
AnnaBridge	172:65be27845400	362	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 12 bits left aligned /
AnnaBridge	172:65be27845400	363	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /!< DAC channel data holding register 8 bits right aligned /
AnnaBridge	172:65be27845400	364	/**
AnnaBridge	172:65be27845400	365	* @}
AnnaBridge	172:65be27845400	366	*/
AnnaBridge	172:65be27845400	367
AnnaBridge	172:65be27845400	368	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
AnnaBridge	172:65be27845400	369	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
AnnaBridge	172:65be27845400	370	* not timeout values.
AnnaBridge	172:65be27845400	371	* For details on delays values, refer to descriptions in source code
AnnaBridge	172:65be27845400	372	* above each literal definition.
AnnaBridge	172:65be27845400	373	* @{
AnnaBridge	172:65be27845400	374	*/
AnnaBridge	172:65be27845400	375
AnnaBridge	172:65be27845400	376	/* Delay for DAC channel voltage settling time from DAC channel startup */
AnnaBridge	172:65be27845400	377	/* (transition from disable to enable). */
AnnaBridge	172:65be27845400	378	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	172:65be27845400	379	/* impedance connected to DAC channel output. */
AnnaBridge	172:65be27845400	380	/* The delay below is specified under conditions: */
AnnaBridge	172:65be27845400	381	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	172:65be27845400	382	/* - until voltage reaches final value +-1LSB */
AnnaBridge	172:65be27845400	383	/* - DAC channel output buffer enabled */
AnnaBridge	172:65be27845400	384	/* - load impedance of 5kOhm (min), 50pF (max) */
AnnaBridge	172:65be27845400	385	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	172:65be27845400	386	/* parameter "tWAKEUP"). */
AnnaBridge	172:65be27845400	387	/* Unit: us */
AnnaBridge	172:65be27845400	388	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
AnnaBridge	172:65be27845400	389
AnnaBridge	172:65be27845400	390
AnnaBridge	172:65be27845400	391	/* Delay for DAC channel voltage settling time. */
AnnaBridge	172:65be27845400	392	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	172:65be27845400	393	/* impedance connected to DAC channel output. */
AnnaBridge	172:65be27845400	394	/* The delay below is specified under conditions: */
AnnaBridge	172:65be27845400	395	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	172:65be27845400	396	/* - until voltage reaches final value +-1LSB */
AnnaBridge	172:65be27845400	397	/* - DAC channel output buffer enabled */
AnnaBridge	172:65be27845400	398	/* - load impedance of 5kOhm min, 50pF max */
AnnaBridge	172:65be27845400	399	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	172:65be27845400	400	/* parameter "tSETTLING"). */
AnnaBridge	172:65be27845400	401	/* Unit: us */
AnnaBridge	172:65be27845400	402	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 2U /!< Delay for DAC channel voltage settling time /
AnnaBridge	172:65be27845400	403
AnnaBridge	172:65be27845400	404	/**
AnnaBridge	172:65be27845400	405	* @}
AnnaBridge	172:65be27845400	406	*/
AnnaBridge	172:65be27845400	407
AnnaBridge	172:65be27845400	408	/**
AnnaBridge	172:65be27845400	409	* @}
AnnaBridge	172:65be27845400	410	*/
AnnaBridge	172:65be27845400	411
AnnaBridge	172:65be27845400	412	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	413	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
AnnaBridge	172:65be27845400	414	* @{
AnnaBridge	172:65be27845400	415	*/
AnnaBridge	172:65be27845400	416
AnnaBridge	172:65be27845400	417	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
AnnaBridge	172:65be27845400	418	* @{
AnnaBridge	172:65be27845400	419	*/
AnnaBridge	172:65be27845400	420
AnnaBridge	172:65be27845400	421	/**
AnnaBridge	172:65be27845400	422	* @brief Write a value in DAC register
AnnaBridge	172:65be27845400	423	* @param __INSTANCE__ DAC Instance
AnnaBridge	172:65be27845400	424	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	425	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	426	* @retval None
AnnaBridge	172:65be27845400	427	*/
AnnaBridge	172:65be27845400	428	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	429
AnnaBridge	172:65be27845400	430	/**
AnnaBridge	172:65be27845400	431	* @brief Read a value in DAC register
AnnaBridge	172:65be27845400	432	* @param __INSTANCE__ DAC Instance
AnnaBridge	172:65be27845400	433	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	434	* @retval Register value
AnnaBridge	172:65be27845400	435	*/
AnnaBridge	172:65be27845400	436	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	172:65be27845400	437
AnnaBridge	172:65be27845400	438	/**
AnnaBridge	172:65be27845400	439	* @}
AnnaBridge	172:65be27845400	440	*/
AnnaBridge	172:65be27845400	441
AnnaBridge	172:65be27845400	442	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
AnnaBridge	172:65be27845400	443	* @{
AnnaBridge	172:65be27845400	444	*/
AnnaBridge	172:65be27845400	445
AnnaBridge	172:65be27845400	446	/**
AnnaBridge	172:65be27845400	447	* @brief Helper macro to get DAC channel number in decimal format
AnnaBridge	172:65be27845400	448	* from literals LL_DAC_CHANNEL_x.
AnnaBridge	172:65be27845400	449	* Example:
AnnaBridge	172:65be27845400	450	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
AnnaBridge	172:65be27845400	451	* will return decimal number "1".
AnnaBridge	172:65be27845400	452	* @note The input can be a value from functions where a channel
AnnaBridge	172:65be27845400	453	* number is returned.
AnnaBridge	172:65be27845400	454	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	455	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	456	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	457	* @retval 1...2
AnnaBridge	172:65be27845400	458	*/
AnnaBridge	172:65be27845400	459	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
AnnaBridge	172:65be27845400	460	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
AnnaBridge	172:65be27845400	461
AnnaBridge	172:65be27845400	462	/**
AnnaBridge	172:65be27845400	463	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
AnnaBridge	172:65be27845400	464	* from number in decimal format.
AnnaBridge	172:65be27845400	465	* Example:
AnnaBridge	172:65be27845400	466	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
AnnaBridge	172:65be27845400	467	* will return a data equivalent to "LL_DAC_CHANNEL_1".
AnnaBridge	172:65be27845400	468	* @note If the input parameter does not correspond to a DAC channel,
AnnaBridge	172:65be27845400	469	* this macro returns value '0'.
AnnaBridge	172:65be27845400	470	* @param __DECIMAL_NB__ 1...2
AnnaBridge	172:65be27845400	471	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	472	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	473	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	474	*/
AnnaBridge	172:65be27845400	475	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge	172:65be27845400	476	(((__DECIMAL_NB__) == 1U) \
AnnaBridge	172:65be27845400	477	? ( \
AnnaBridge	172:65be27845400	478	LL_DAC_CHANNEL_1 \
AnnaBridge	172:65be27845400	479	) \
AnnaBridge	172:65be27845400	480	: \
AnnaBridge	172:65be27845400	481	(((__DECIMAL_NB__) == 2U) \
AnnaBridge	172:65be27845400	482	? ( \
AnnaBridge	172:65be27845400	483	LL_DAC_CHANNEL_2 \
AnnaBridge	172:65be27845400	484	) \
AnnaBridge	172:65be27845400	485	: \
AnnaBridge	172:65be27845400	486	( \
AnnaBridge	172:65be27845400	487	0 \
AnnaBridge	172:65be27845400	488	) \
AnnaBridge	172:65be27845400	489	) \
AnnaBridge	172:65be27845400	490	)
AnnaBridge	172:65be27845400	491
AnnaBridge	172:65be27845400	492	/**
AnnaBridge	172:65be27845400	493	* @brief Helper macro to define the DAC conversion data full-scale digital
AnnaBridge	172:65be27845400	494	* value corresponding to the selected DAC resolution.
AnnaBridge	172:65be27845400	495	* @note DAC conversion data full-scale corresponds to voltage range
AnnaBridge	172:65be27845400	496	* determined by analog voltage references Vref+ and Vref-
AnnaBridge	172:65be27845400	497	* (refer to reference manual).
AnnaBridge	172:65be27845400	498	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	499	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	172:65be27845400	500	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	172:65be27845400	501	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
AnnaBridge	172:65be27845400	502	*/
AnnaBridge	172:65be27845400	503	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	172:65be27845400	504	((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
AnnaBridge	172:65be27845400	505
AnnaBridge	172:65be27845400	506	/**
AnnaBridge	172:65be27845400	507	* @brief Helper macro to calculate the DAC conversion data (unit: digital
AnnaBridge	172:65be27845400	508	* value) corresponding to a voltage (unit: mVolt).
AnnaBridge	172:65be27845400	509	* @note This helper macro is intended to provide input data in voltage
AnnaBridge	172:65be27845400	510	* rather than digital value,
AnnaBridge	172:65be27845400	511	* to be used with LL DAC functions such as
AnnaBridge	172:65be27845400	512	* @ref LL_DAC_ConvertData12RightAligned().
AnnaBridge	172:65be27845400	513	* @note Analog reference voltage (Vref+) must be either known from
AnnaBridge	172:65be27845400	514	* user board environment or can be calculated using ADC measurement
AnnaBridge	172:65be27845400	515	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
AnnaBridge	172:65be27845400	516	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
AnnaBridge	172:65be27845400	517	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
AnnaBridge	172:65be27845400	518	* (unit: mVolt).
AnnaBridge	172:65be27845400	519	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	520	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	172:65be27845400	521	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	172:65be27845400	522	* @retval DAC conversion data (unit: digital value)
AnnaBridge	172:65be27845400	523	*/
AnnaBridge	172:65be27845400	524	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
AnnaBridge	172:65be27845400	525	__DAC_VOLTAGE__,\
AnnaBridge	172:65be27845400	526	__DAC_RESOLUTION__) \
AnnaBridge	172:65be27845400	527	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	172:65be27845400	528	/ (__VREFANALOG_VOLTAGE__) \
AnnaBridge	172:65be27845400	529	)
AnnaBridge	172:65be27845400	530
AnnaBridge	172:65be27845400	531	/**
AnnaBridge	172:65be27845400	532	* @}
AnnaBridge	172:65be27845400	533	*/
AnnaBridge	172:65be27845400	534
AnnaBridge	172:65be27845400	535	/**
AnnaBridge	172:65be27845400	536	* @}
AnnaBridge	172:65be27845400	537	*/
AnnaBridge	172:65be27845400	538
AnnaBridge	172:65be27845400	539
AnnaBridge	172:65be27845400	540	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	541	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
AnnaBridge	172:65be27845400	542	* @{
AnnaBridge	172:65be27845400	543	*/
AnnaBridge	172:65be27845400	544	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
AnnaBridge	172:65be27845400	545	* @{
AnnaBridge	172:65be27845400	546	*/
AnnaBridge	172:65be27845400	547
AnnaBridge	172:65be27845400	548	/**
AnnaBridge	172:65be27845400	549	* @brief Set the operating mode for the selected DAC channel:
AnnaBridge	172:65be27845400	550	* calibration or normal operating mode.
AnnaBridge	172:65be27845400	551	* @rmtoll CR CEN1 LL_DAC_SetMode\n
AnnaBridge	172:65be27845400	552	* CR CEN2 LL_DAC_SetMode
AnnaBridge	172:65be27845400	553	* @param DACx DAC instance
AnnaBridge	172:65be27845400	554	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	555	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	556	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	557	* @param ChannelMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	558	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
AnnaBridge	172:65be27845400	559	* @arg @ref LL_DAC_MODE_CALIBRATION
AnnaBridge	172:65be27845400	560	* @retval None
AnnaBridge	172:65be27845400	561	*/
AnnaBridge	172:65be27845400	562	__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
AnnaBridge	172:65be27845400	563	{
AnnaBridge	172:65be27845400	564	MODIFY_REG(DACx->CR,
AnnaBridge	172:65be27845400	565	DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	566	ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	567	}
AnnaBridge	172:65be27845400	568
AnnaBridge	172:65be27845400	569	/**
AnnaBridge	172:65be27845400	570	* @brief Get the operating mode for the selected DAC channel:
AnnaBridge	172:65be27845400	571	* calibration or normal operating mode.
AnnaBridge	172:65be27845400	572	* @rmtoll CR CEN1 LL_DAC_GetMode\n
AnnaBridge	172:65be27845400	573	* CR CEN2 LL_DAC_GetMode
AnnaBridge	172:65be27845400	574	* @param DACx DAC instance
AnnaBridge	172:65be27845400	575	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	576	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	577	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	578	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	579	* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
AnnaBridge	172:65be27845400	580	* @arg @ref LL_DAC_MODE_CALIBRATION
AnnaBridge	172:65be27845400	581	*/
AnnaBridge	172:65be27845400	582	__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	583	{
AnnaBridge	172:65be27845400	584	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	585	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	586	);
AnnaBridge	172:65be27845400	587	}
AnnaBridge	172:65be27845400	588
AnnaBridge	172:65be27845400	589	/**
AnnaBridge	172:65be27845400	590	* @brief Set the offset trimming value for the selected DAC channel.
AnnaBridge	172:65be27845400	591	* Trimming has an impact when output buffer is enabled
AnnaBridge	172:65be27845400	592	* and is intended to replace factory calibration default values.
AnnaBridge	172:65be27845400	593	* @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
AnnaBridge	172:65be27845400	594	* CCR OTRIM2 LL_DAC_SetTrimmingValue
AnnaBridge	172:65be27845400	595	* @param DACx DAC instance
AnnaBridge	172:65be27845400	596	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	597	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	598	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	599	* @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
AnnaBridge	172:65be27845400	600	* @retval None
AnnaBridge	172:65be27845400	601	*/
AnnaBridge	172:65be27845400	602	__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
AnnaBridge	172:65be27845400	603	{
AnnaBridge	172:65be27845400	604	MODIFY_REG(DACx->CCR,
AnnaBridge	172:65be27845400	605	DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	606	TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	607	}
AnnaBridge	172:65be27845400	608
AnnaBridge	172:65be27845400	609	/**
AnnaBridge	172:65be27845400	610	* @brief Get the offset trimming value for the selected DAC channel.
AnnaBridge	172:65be27845400	611	* Trimming has an impact when output buffer is enabled
AnnaBridge	172:65be27845400	612	* and is intended to replace factory calibration default values.
AnnaBridge	172:65be27845400	613	* @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
AnnaBridge	172:65be27845400	614	* CCR OTRIM2 LL_DAC_GetTrimmingValue
AnnaBridge	172:65be27845400	615	* @param DACx DAC instance
AnnaBridge	172:65be27845400	616	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	617	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	618	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	619	* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
AnnaBridge	172:65be27845400	620	*/
AnnaBridge	172:65be27845400	621	__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	622	{
AnnaBridge	172:65be27845400	623	return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	624	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	625	);
AnnaBridge	172:65be27845400	626	}
AnnaBridge	172:65be27845400	627
AnnaBridge	172:65be27845400	628	/**
AnnaBridge	172:65be27845400	629	* @brief Set the conversion trigger source for the selected DAC channel.
AnnaBridge	172:65be27845400	630	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	172:65be27845400	631	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	172:65be27845400	632	* @note To set conversion trigger source, DAC channel must be disabled.
AnnaBridge	172:65be27845400	633	* Otherwise, the setting is discarded.
AnnaBridge	172:65be27845400	634	* @note Availability of parameters of trigger sources from timer
AnnaBridge	172:65be27845400	635	* depends on timers availability on the selected device.
AnnaBridge	172:65be27845400	636	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
AnnaBridge	172:65be27845400	637	* CR TSEL2 LL_DAC_SetTriggerSource
AnnaBridge	172:65be27845400	638	* @param DACx DAC instance
AnnaBridge	172:65be27845400	639	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	640	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	641	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	642	* @param TriggerSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	643	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	172:65be27845400	644	* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
AnnaBridge	172:65be27845400	645	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	172:65be27845400	646	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge	172:65be27845400	647	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge	172:65be27845400	648	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	172:65be27845400	649	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	172:65be27845400	650	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge	172:65be27845400	651	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
AnnaBridge	172:65be27845400	652	* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1
AnnaBridge	172:65be27845400	653	* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2
AnnaBridge	172:65be27845400	654	* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
AnnaBridge	172:65be27845400	655	* @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
AnnaBridge	172:65be27845400	656	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge	172:65be27845400	657	* @retval None
AnnaBridge	172:65be27845400	658	*/
AnnaBridge	172:65be27845400	659	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
AnnaBridge	172:65be27845400	660	{
AnnaBridge	172:65be27845400	661	MODIFY_REG(DACx->CR,
AnnaBridge	172:65be27845400	662	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	663	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	664	}
AnnaBridge	172:65be27845400	665
AnnaBridge	172:65be27845400	666	/**
AnnaBridge	172:65be27845400	667	* @brief Get the conversion trigger source for the selected DAC channel.
AnnaBridge	172:65be27845400	668	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	172:65be27845400	669	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	172:65be27845400	670	* @note Availability of parameters of trigger sources from timer
AnnaBridge	172:65be27845400	671	* depends on timers availability on the selected device.
AnnaBridge	172:65be27845400	672	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
AnnaBridge	172:65be27845400	673	* CR TSEL2 LL_DAC_GetTriggerSource
AnnaBridge	172:65be27845400	674	* @param DACx DAC instance
AnnaBridge	172:65be27845400	675	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	676	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	677	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	678	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	679	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	172:65be27845400	680	* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
AnnaBridge	172:65be27845400	681	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	172:65be27845400	682	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge	172:65be27845400	683	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge	172:65be27845400	684	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	172:65be27845400	685	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	172:65be27845400	686	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge	172:65be27845400	687	* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
AnnaBridge	172:65be27845400	688	* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1
AnnaBridge	172:65be27845400	689	* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2
AnnaBridge	172:65be27845400	690	* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
AnnaBridge	172:65be27845400	691	* @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
AnnaBridge	172:65be27845400	692	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge	172:65be27845400	693	*/
AnnaBridge	172:65be27845400	694	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	695	{
AnnaBridge	172:65be27845400	696	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	697	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	698	);
AnnaBridge	172:65be27845400	699	}
AnnaBridge	172:65be27845400	700
AnnaBridge	172:65be27845400	701	/**
AnnaBridge	172:65be27845400	702	* @brief Set the waveform automatic generation mode
AnnaBridge	172:65be27845400	703	* for the selected DAC channel.
AnnaBridge	172:65be27845400	704	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
AnnaBridge	172:65be27845400	705	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
AnnaBridge	172:65be27845400	706	* @param DACx DAC instance
AnnaBridge	172:65be27845400	707	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	708	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	709	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	710	* @param WaveAutoGeneration This parameter can be one of the following values:
AnnaBridge	172:65be27845400	711	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	172:65be27845400	712	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	172:65be27845400	713	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	172:65be27845400	714	* @retval None
AnnaBridge	172:65be27845400	715	*/
AnnaBridge	172:65be27845400	716	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
AnnaBridge	172:65be27845400	717	{
AnnaBridge	172:65be27845400	718	MODIFY_REG(DACx->CR,
AnnaBridge	172:65be27845400	719	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	720	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	721	}
AnnaBridge	172:65be27845400	722
AnnaBridge	172:65be27845400	723	/**
AnnaBridge	172:65be27845400	724	* @brief Get the waveform automatic generation mode
AnnaBridge	172:65be27845400	725	* for the selected DAC channel.
AnnaBridge	172:65be27845400	726	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
AnnaBridge	172:65be27845400	727	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
AnnaBridge	172:65be27845400	728	* @param DACx DAC instance
AnnaBridge	172:65be27845400	729	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	730	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	731	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	732	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	733	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	172:65be27845400	734	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	172:65be27845400	735	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	172:65be27845400	736	*/
AnnaBridge	172:65be27845400	737	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	738	{
AnnaBridge	172:65be27845400	739	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	740	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	741	);
AnnaBridge	172:65be27845400	742	}
AnnaBridge	172:65be27845400	743
AnnaBridge	172:65be27845400	744	/**
AnnaBridge	172:65be27845400	745	* @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge	172:65be27845400	746	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	172:65be27845400	747	* @note For wave generation to be effective, DAC channel
AnnaBridge	172:65be27845400	748	* wave generation mode must be enabled using
AnnaBridge	172:65be27845400	749	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	172:65be27845400	750	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	172:65be27845400	751	* (otherwise, the setting operation is ignored).
AnnaBridge	172:65be27845400	752	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
AnnaBridge	172:65be27845400	753	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
AnnaBridge	172:65be27845400	754	* @param DACx DAC instance
AnnaBridge	172:65be27845400	755	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	756	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	757	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	758	* @param NoiseLFSRMask This parameter can be one of the following values:
AnnaBridge	172:65be27845400	759	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	172:65be27845400	760	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	172:65be27845400	761	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	172:65be27845400	762	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	172:65be27845400	763	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	172:65be27845400	764	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	172:65be27845400	765	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	172:65be27845400	766	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	172:65be27845400	767	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	172:65be27845400	768	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	172:65be27845400	769	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	172:65be27845400	770	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	172:65be27845400	771	* @retval None
AnnaBridge	172:65be27845400	772	*/
AnnaBridge	172:65be27845400	773	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
AnnaBridge	172:65be27845400	774	{
AnnaBridge	172:65be27845400	775	MODIFY_REG(DACx->CR,
AnnaBridge	172:65be27845400	776	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	777	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	778	}
AnnaBridge	172:65be27845400	779
AnnaBridge	172:65be27845400	780	/**
AnnaBridge	172:65be27845400	781	* @brief Get the noise waveform generation for the selected DAC channel:
AnnaBridge	172:65be27845400	782	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	172:65be27845400	783	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
AnnaBridge	172:65be27845400	784	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
AnnaBridge	172:65be27845400	785	* @param DACx DAC instance
AnnaBridge	172:65be27845400	786	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	787	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	788	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	789	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	790	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	172:65be27845400	791	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	172:65be27845400	792	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	172:65be27845400	793	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	172:65be27845400	794	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	172:65be27845400	795	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	172:65be27845400	796	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	172:65be27845400	797	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	172:65be27845400	798	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	172:65be27845400	799	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	172:65be27845400	800	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	172:65be27845400	801	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	172:65be27845400	802	*/
AnnaBridge	172:65be27845400	803	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	804	{
AnnaBridge	172:65be27845400	805	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	806	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	807	);
AnnaBridge	172:65be27845400	808	}
AnnaBridge	172:65be27845400	809
AnnaBridge	172:65be27845400	810	/**
AnnaBridge	172:65be27845400	811	* @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge	172:65be27845400	812	* triangle mode and amplitude.
AnnaBridge	172:65be27845400	813	* @note For wave generation to be effective, DAC channel
AnnaBridge	172:65be27845400	814	* wave generation mode must be enabled using
AnnaBridge	172:65be27845400	815	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	172:65be27845400	816	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	172:65be27845400	817	* (otherwise, the setting operation is ignored).
AnnaBridge	172:65be27845400	818	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
AnnaBridge	172:65be27845400	819	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
AnnaBridge	172:65be27845400	820	* @param DACx DAC instance
AnnaBridge	172:65be27845400	821	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	822	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	823	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	824	* @param TriangleAmplitude This parameter can be one of the following values:
AnnaBridge	172:65be27845400	825	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	172:65be27845400	826	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	172:65be27845400	827	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	172:65be27845400	828	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	172:65be27845400	829	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	172:65be27845400	830	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	172:65be27845400	831	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	172:65be27845400	832	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	172:65be27845400	833	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	172:65be27845400	834	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	172:65be27845400	835	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	172:65be27845400	836	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	172:65be27845400	837	* @retval None
AnnaBridge	172:65be27845400	838	*/
AnnaBridge	172:65be27845400	839	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
AnnaBridge	172:65be27845400	840	{
AnnaBridge	172:65be27845400	841	MODIFY_REG(DACx->CR,
AnnaBridge	172:65be27845400	842	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	843	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	844	}
AnnaBridge	172:65be27845400	845
AnnaBridge	172:65be27845400	846	/**
AnnaBridge	172:65be27845400	847	* @brief Get the triangle waveform generation for the selected DAC channel:
AnnaBridge	172:65be27845400	848	* triangle mode and amplitude.
AnnaBridge	172:65be27845400	849	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
AnnaBridge	172:65be27845400	850	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
AnnaBridge	172:65be27845400	851	* @param DACx DAC instance
AnnaBridge	172:65be27845400	852	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	853	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	854	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	855	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	856	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	172:65be27845400	857	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	172:65be27845400	858	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	172:65be27845400	859	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	172:65be27845400	860	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	172:65be27845400	861	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	172:65be27845400	862	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	172:65be27845400	863	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	172:65be27845400	864	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	172:65be27845400	865	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	172:65be27845400	866	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	172:65be27845400	867	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	172:65be27845400	868	*/
AnnaBridge	172:65be27845400	869	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	870	{
AnnaBridge	172:65be27845400	871	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	872	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	873	);
AnnaBridge	172:65be27845400	874	}
AnnaBridge	172:65be27845400	875
AnnaBridge	172:65be27845400	876	/**
AnnaBridge	172:65be27845400	877	* @brief Set the output for the selected DAC channel.
AnnaBridge	172:65be27845400	878	* @note This function set several features:
AnnaBridge	172:65be27845400	879	* - mode normal or sample-and-hold
AnnaBridge	172:65be27845400	880	* - buffer
AnnaBridge	172:65be27845400	881	* - connection to GPIO or internal path.
AnnaBridge	172:65be27845400	882	* These features can also be set individually using
AnnaBridge	172:65be27845400	883	* dedicated functions:
AnnaBridge	172:65be27845400	884	* - @ref LL_DAC_SetOutputBuffer()
AnnaBridge	172:65be27845400	885	* - @ref LL_DAC_SetOutputMode()
AnnaBridge	172:65be27845400	886	* - @ref LL_DAC_SetOutputConnection()
AnnaBridge	172:65be27845400	887	* @note On this STM32 serie, output connection depends on output mode
AnnaBridge	172:65be27845400	888	* (normal or sample and hold) and output buffer state.
AnnaBridge	172:65be27845400	889	* - if output connection is set to internal path and output buffer
AnnaBridge	172:65be27845400	890	* is enabled (whatever output mode):
AnnaBridge	172:65be27845400	891	* output connection is also connected to GPIO pin
AnnaBridge	172:65be27845400	892	* (both connections to GPIO pin and internal path).
AnnaBridge	172:65be27845400	893	* - if output connection is set to GPIO pin, output buffer
AnnaBridge	172:65be27845400	894	* is disabled, output mode set to sample and hold:
AnnaBridge	172:65be27845400	895	* output connection is also connected to internal path
AnnaBridge	172:65be27845400	896	* (both connections to GPIO pin and internal path).
AnnaBridge	172:65be27845400	897	* @note Mode sample-and-hold requires an external capacitor
AnnaBridge	172:65be27845400	898	* to be connected between DAC channel output and ground.
AnnaBridge	172:65be27845400	899	* Capacitor value depends on load on DAC channel output and
AnnaBridge	172:65be27845400	900	* sample-and-hold timings configured.
AnnaBridge	172:65be27845400	901	* As indication, capacitor typical value is 100nF
AnnaBridge	172:65be27845400	902	* (refer to device datasheet, parameter "CSH").
AnnaBridge	172:65be27845400	903	* @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
AnnaBridge	172:65be27845400	904	* CR MODE2 LL_DAC_ConfigOutput
AnnaBridge	172:65be27845400	905	* @param DACx DAC instance
AnnaBridge	172:65be27845400	906	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	907	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	908	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	909	* @param OutputMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	910	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
AnnaBridge	172:65be27845400	911	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
AnnaBridge	172:65be27845400	912	* @param OutputBuffer This parameter can be one of the following values:
AnnaBridge	172:65be27845400	913	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	172:65be27845400	914	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	172:65be27845400	915	* @param OutputConnection This parameter can be one of the following values:
AnnaBridge	172:65be27845400	916	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
AnnaBridge	172:65be27845400	917	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
AnnaBridge	172:65be27845400	918	* @retval None
AnnaBridge	172:65be27845400	919	*/
AnnaBridge	172:65be27845400	920	__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection)
AnnaBridge	172:65be27845400	921	{
AnnaBridge	172:65be27845400	922	MODIFY_REG(DACx->MCR,
AnnaBridge	172:65be27845400	923	(DAC_MCR_MODE1_2 \| DAC_MCR_MODE1_1 \| DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	924	(OutputMode \| OutputBuffer \| OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	925	}
AnnaBridge	172:65be27845400	926
AnnaBridge	172:65be27845400	927	/**
AnnaBridge	172:65be27845400	928	* @brief Set the output mode normal or sample-and-hold
AnnaBridge	172:65be27845400	929	* for the selected DAC channel.
AnnaBridge	172:65be27845400	930	* @note Mode sample-and-hold requires an external capacitor
AnnaBridge	172:65be27845400	931	* to be connected between DAC channel output and ground.
AnnaBridge	172:65be27845400	932	* Capacitor value depends on load on DAC channel output and
AnnaBridge	172:65be27845400	933	* sample-and-hold timings configured.
AnnaBridge	172:65be27845400	934	* As indication, capacitor typical value is 100nF
AnnaBridge	172:65be27845400	935	* (refer to device datasheet, parameter "CSH").
AnnaBridge	172:65be27845400	936	* @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
AnnaBridge	172:65be27845400	937	* CR MODE2 LL_DAC_SetOutputMode
AnnaBridge	172:65be27845400	938	* @param DACx DAC instance
AnnaBridge	172:65be27845400	939	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	940	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	941	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	942	* @param OutputMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	943	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
AnnaBridge	172:65be27845400	944	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
AnnaBridge	172:65be27845400	945	* @retval None
AnnaBridge	172:65be27845400	946	*/
AnnaBridge	172:65be27845400	947	__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
AnnaBridge	172:65be27845400	948	{
AnnaBridge	172:65be27845400	949	MODIFY_REG(DACx->MCR,
AnnaBridge	172:65be27845400	950	(uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	951	OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	952	}
AnnaBridge	172:65be27845400	953
AnnaBridge	172:65be27845400	954	/**
AnnaBridge	172:65be27845400	955	* @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
AnnaBridge	172:65be27845400	956	* @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
AnnaBridge	172:65be27845400	957	* CR MODE2 LL_DAC_GetOutputMode
AnnaBridge	172:65be27845400	958	* @param DACx DAC instance
AnnaBridge	172:65be27845400	959	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	960	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	961	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	962	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	963	* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
AnnaBridge	172:65be27845400	964	* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
AnnaBridge	172:65be27845400	965	*/
AnnaBridge	172:65be27845400	966	__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	967	{
AnnaBridge	172:65be27845400	968	return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	969	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	970	);
AnnaBridge	172:65be27845400	971	}
AnnaBridge	172:65be27845400	972
AnnaBridge	172:65be27845400	973	/**
AnnaBridge	172:65be27845400	974	* @brief Set the output buffer for the selected DAC channel.
AnnaBridge	172:65be27845400	975	* @note On this STM32 serie, when buffer is enabled, its offset can be
AnnaBridge	172:65be27845400	976	* trimmed: factory calibration default values can be
AnnaBridge	172:65be27845400	977	* replaced by user trimming values, using function
AnnaBridge	172:65be27845400	978	* @ref LL_DAC_SetTrimmingValue().
AnnaBridge	172:65be27845400	979	* @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
AnnaBridge	172:65be27845400	980	* CR MODE2 LL_DAC_SetOutputBuffer
AnnaBridge	172:65be27845400	981	* @param DACx DAC instance
AnnaBridge	172:65be27845400	982	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	983	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	984	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	985	* @param OutputBuffer This parameter can be one of the following values:
AnnaBridge	172:65be27845400	986	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	172:65be27845400	987	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	172:65be27845400	988	* @retval None
AnnaBridge	172:65be27845400	989	*/
AnnaBridge	172:65be27845400	990	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
AnnaBridge	172:65be27845400	991	{
AnnaBridge	172:65be27845400	992	MODIFY_REG(DACx->MCR,
AnnaBridge	172:65be27845400	993	(uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	994	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	995	}
AnnaBridge	172:65be27845400	996
AnnaBridge	172:65be27845400	997	/**
AnnaBridge	172:65be27845400	998	* @brief Get the output buffer state for the selected DAC channel.
AnnaBridge	172:65be27845400	999	* @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
AnnaBridge	172:65be27845400	1000	* CR MODE2 LL_DAC_GetOutputBuffer
AnnaBridge	172:65be27845400	1001	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1002	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1003	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1004	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1005	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1006	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	172:65be27845400	1007	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	172:65be27845400	1008	*/
AnnaBridge	172:65be27845400	1009	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1010	{
AnnaBridge	172:65be27845400	1011	return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	1012	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	1013	);
AnnaBridge	172:65be27845400	1014	}
AnnaBridge	172:65be27845400	1015
AnnaBridge	172:65be27845400	1016	/**
AnnaBridge	172:65be27845400	1017	* @brief Set the output connection for the selected DAC channel.
AnnaBridge	172:65be27845400	1018	* @note On this STM32 serie, output connection depends on output mode (normal or
AnnaBridge	172:65be27845400	1019	* sample and hold) and output buffer state.
AnnaBridge	172:65be27845400	1020	* - if output connection is set to internal path and output buffer
AnnaBridge	172:65be27845400	1021	* is enabled (whatever output mode):
AnnaBridge	172:65be27845400	1022	* output connection is also connected to GPIO pin
AnnaBridge	172:65be27845400	1023	* (both connections to GPIO pin and internal path).
AnnaBridge	172:65be27845400	1024	* - if output connection is set to GPIO pin, output buffer
AnnaBridge	172:65be27845400	1025	* is disabled, output mode set to sample and hold:
AnnaBridge	172:65be27845400	1026	* output connection is also connected to internal path
AnnaBridge	172:65be27845400	1027	* (both connections to GPIO pin and internal path).
AnnaBridge	172:65be27845400	1028	* @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
AnnaBridge	172:65be27845400	1029	* CR MODE2 LL_DAC_SetOutputConnection
AnnaBridge	172:65be27845400	1030	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1031	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1032	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1033	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1034	* @param OutputConnection This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1035	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
AnnaBridge	172:65be27845400	1036	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
AnnaBridge	172:65be27845400	1037	* @retval None
AnnaBridge	172:65be27845400	1038	*/
AnnaBridge	172:65be27845400	1039	__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
AnnaBridge	172:65be27845400	1040	{
AnnaBridge	172:65be27845400	1041	MODIFY_REG(DACx->MCR,
AnnaBridge	172:65be27845400	1042	(uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	1043	OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1044	}
AnnaBridge	172:65be27845400	1045
AnnaBridge	172:65be27845400	1046	/**
AnnaBridge	172:65be27845400	1047	* @brief Get the output connection for the selected DAC channel.
AnnaBridge	172:65be27845400	1048	* @note On this STM32 serie, output connection depends on output mode (normal or
AnnaBridge	172:65be27845400	1049	* sample and hold) and output buffer state.
AnnaBridge	172:65be27845400	1050	* - if output connection is set to internal path and output buffer
AnnaBridge	172:65be27845400	1051	* is enabled (whatever output mode):
AnnaBridge	172:65be27845400	1052	* output connection is also connected to GPIO pin
AnnaBridge	172:65be27845400	1053	* (both connections to GPIO pin and internal path).
AnnaBridge	172:65be27845400	1054	* - if output connection is set to GPIO pin, output buffer
AnnaBridge	172:65be27845400	1055	* is disabled, output mode set to sample and hold:
AnnaBridge	172:65be27845400	1056	* output connection is also connected to internal path
AnnaBridge	172:65be27845400	1057	* (both connections to GPIO pin and internal path).
AnnaBridge	172:65be27845400	1058	* @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
AnnaBridge	172:65be27845400	1059	* CR MODE2 LL_DAC_GetOutputConnection
AnnaBridge	172:65be27845400	1060	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1061	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1062	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1063	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1064	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1065	* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
AnnaBridge	172:65be27845400	1066	* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
AnnaBridge	172:65be27845400	1067	*/
AnnaBridge	172:65be27845400	1068	__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1069	{
AnnaBridge	172:65be27845400	1070	return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	1071	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	1072	);
AnnaBridge	172:65be27845400	1073	}
AnnaBridge	172:65be27845400	1074
AnnaBridge	172:65be27845400	1075	/**
AnnaBridge	172:65be27845400	1076	* @brief Set the sample-and-hold timing for the selected DAC channel:
AnnaBridge	172:65be27845400	1077	* sample time
AnnaBridge	172:65be27845400	1078	* @note Sample time must be set when DAC channel is disabled
AnnaBridge	172:65be27845400	1079	* or during DAC operation when DAC channel flag BWSTx is reset,
AnnaBridge	172:65be27845400	1080	* otherwise the setting is ignored.
AnnaBridge	172:65be27845400	1081	* Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
AnnaBridge	172:65be27845400	1082	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
AnnaBridge	172:65be27845400	1083	* SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
AnnaBridge	172:65be27845400	1084	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1085	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1086	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1087	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1088	* @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	172:65be27845400	1089	* @retval None
AnnaBridge	172:65be27845400	1090	*/
AnnaBridge	172:65be27845400	1091	__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
AnnaBridge	172:65be27845400	1092	{
AnnaBridge	172:65be27845400	1093	register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
AnnaBridge	172:65be27845400	1094
AnnaBridge	172:65be27845400	1095	MODIFY_REG(*preg,
AnnaBridge	172:65be27845400	1096	DAC_SHSR1_TSAMPLE1,
AnnaBridge	172:65be27845400	1097	SampleTime);
AnnaBridge	172:65be27845400	1098	}
AnnaBridge	172:65be27845400	1099
AnnaBridge	172:65be27845400	1100	/**
AnnaBridge	172:65be27845400	1101	* @brief Get the sample-and-hold timing for the selected DAC channel:
AnnaBridge	172:65be27845400	1102	* sample time
AnnaBridge	172:65be27845400	1103	* @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
AnnaBridge	172:65be27845400	1104	* SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
AnnaBridge	172:65be27845400	1105	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1106	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1107	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1108	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1109	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	172:65be27845400	1110	*/
AnnaBridge	172:65be27845400	1111	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1112	{
AnnaBridge	172:65be27845400	1113	register __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
AnnaBridge	172:65be27845400	1114
AnnaBridge	172:65be27845400	1115	return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
AnnaBridge	172:65be27845400	1116	}
AnnaBridge	172:65be27845400	1117
AnnaBridge	172:65be27845400	1118	/**
AnnaBridge	172:65be27845400	1119	* @brief Set the sample-and-hold timing for the selected DAC channel:
AnnaBridge	172:65be27845400	1120	* hold time
AnnaBridge	172:65be27845400	1121	* @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
AnnaBridge	172:65be27845400	1122	* SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
AnnaBridge	172:65be27845400	1123	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1124	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1125	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1126	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1127	* @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	172:65be27845400	1128	* @retval None
AnnaBridge	172:65be27845400	1129	*/
AnnaBridge	172:65be27845400	1130	__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
AnnaBridge	172:65be27845400	1131	{
AnnaBridge	172:65be27845400	1132	MODIFY_REG(DACx->SHHR,
AnnaBridge	172:65be27845400	1133	DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	1134	HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1135	}
AnnaBridge	172:65be27845400	1136
AnnaBridge	172:65be27845400	1137	/**
AnnaBridge	172:65be27845400	1138	* @brief Get the sample-and-hold timing for the selected DAC channel:
AnnaBridge	172:65be27845400	1139	* hold time
AnnaBridge	172:65be27845400	1140	* @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
AnnaBridge	172:65be27845400	1141	* SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
AnnaBridge	172:65be27845400	1142	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1143	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1144	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1145	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1146	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
AnnaBridge	172:65be27845400	1147	*/
AnnaBridge	172:65be27845400	1148	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1149	{
AnnaBridge	172:65be27845400	1150	return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	1151	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	1152	);
AnnaBridge	172:65be27845400	1153	}
AnnaBridge	172:65be27845400	1154
AnnaBridge	172:65be27845400	1155	/**
AnnaBridge	172:65be27845400	1156	* @brief Set the sample-and-hold timing for the selected DAC channel:
AnnaBridge	172:65be27845400	1157	* refresh time
AnnaBridge	172:65be27845400	1158	* @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
AnnaBridge	172:65be27845400	1159	* SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
AnnaBridge	172:65be27845400	1160	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1161	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1162	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1163	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1164	* @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	1165	* @retval None
AnnaBridge	172:65be27845400	1166	*/
AnnaBridge	172:65be27845400	1167	__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
AnnaBridge	172:65be27845400	1168	{
AnnaBridge	172:65be27845400	1169	MODIFY_REG(DACx->SHRR,
AnnaBridge	172:65be27845400	1170	DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	172:65be27845400	1171	RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1172	}
AnnaBridge	172:65be27845400	1173
AnnaBridge	172:65be27845400	1174	/**
AnnaBridge	172:65be27845400	1175	* @brief Get the sample-and-hold timing for the selected DAC channel:
AnnaBridge	172:65be27845400	1176	* refresh time
AnnaBridge	172:65be27845400	1177	* @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
AnnaBridge	172:65be27845400	1178	* SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
AnnaBridge	172:65be27845400	1179	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1180	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1181	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1182	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1183	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	1184	*/
AnnaBridge	172:65be27845400	1185	__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1186	{
AnnaBridge	172:65be27845400	1187	return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	1188	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	172:65be27845400	1189	);
AnnaBridge	172:65be27845400	1190	}
AnnaBridge	172:65be27845400	1191
AnnaBridge	172:65be27845400	1192	/**
AnnaBridge	172:65be27845400	1193	* @}
AnnaBridge	172:65be27845400	1194	*/
AnnaBridge	172:65be27845400	1195
AnnaBridge	172:65be27845400	1196	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
AnnaBridge	172:65be27845400	1197	* @{
AnnaBridge	172:65be27845400	1198	*/
AnnaBridge	172:65be27845400	1199
AnnaBridge	172:65be27845400	1200	/**
AnnaBridge	172:65be27845400	1201	* @brief Enable DAC DMA transfer request of the selected channel.
AnnaBridge	172:65be27845400	1202	* @note To configure DMA source address (peripheral address),
AnnaBridge	172:65be27845400	1203	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	172:65be27845400	1204	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
AnnaBridge	172:65be27845400	1205	* CR DMAEN2 LL_DAC_EnableDMAReq
AnnaBridge	172:65be27845400	1206	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1207	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1208	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1209	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1210	* @retval None
AnnaBridge	172:65be27845400	1211	*/
AnnaBridge	172:65be27845400	1212	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1213	{
AnnaBridge	172:65be27845400	1214	SET_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1215	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1216	}
AnnaBridge	172:65be27845400	1217
AnnaBridge	172:65be27845400	1218	/**
AnnaBridge	172:65be27845400	1219	* @brief Disable DAC DMA transfer request of the selected channel.
AnnaBridge	172:65be27845400	1220	* @note To configure DMA source address (peripheral address),
AnnaBridge	172:65be27845400	1221	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	172:65be27845400	1222	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
AnnaBridge	172:65be27845400	1223	* CR DMAEN2 LL_DAC_DisableDMAReq
AnnaBridge	172:65be27845400	1224	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1225	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1226	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1227	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1228	* @retval None
AnnaBridge	172:65be27845400	1229	*/
AnnaBridge	172:65be27845400	1230	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1231	{
AnnaBridge	172:65be27845400	1232	CLEAR_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1233	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1234	}
AnnaBridge	172:65be27845400	1235
AnnaBridge	172:65be27845400	1236	/**
AnnaBridge	172:65be27845400	1237	* @brief Get DAC DMA transfer request state of the selected channel.
AnnaBridge	172:65be27845400	1238	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
AnnaBridge	172:65be27845400	1239	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
AnnaBridge	172:65be27845400	1240	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
AnnaBridge	172:65be27845400	1241	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1242	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1243	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1244	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1245	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1246	*/
AnnaBridge	172:65be27845400	1247	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1248	{
AnnaBridge	172:65be27845400	1249	return ((READ_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1250	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	1251	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1252	}
AnnaBridge	172:65be27845400	1253
AnnaBridge	172:65be27845400	1254	/**
AnnaBridge	172:65be27845400	1255	* @brief Function to help to configure DMA transfer to DAC: retrieve the
AnnaBridge	172:65be27845400	1256	* DAC register address from DAC instance and a list of DAC registers
AnnaBridge	172:65be27845400	1257	* intended to be used (most commonly) with DMA transfer.
AnnaBridge	172:65be27845400	1258	* @note These DAC registers are data holding registers:
AnnaBridge	172:65be27845400	1259	* when DAC conversion is requested, DAC generates a DMA transfer
AnnaBridge	172:65be27845400	1260	* request to have data available in DAC data holding registers.
AnnaBridge	172:65be27845400	1261	* @note This macro is intended to be used with LL DMA driver, refer to
AnnaBridge	172:65be27845400	1262	* function "LL_DMA_ConfigAddresses()".
AnnaBridge	172:65be27845400	1263	* Example:
AnnaBridge	172:65be27845400	1264	* LL_DMA_ConfigAddresses(DMA1,
AnnaBridge	172:65be27845400	1265	* LL_DMA_CHANNEL_1,
AnnaBridge	172:65be27845400	1266	* (uint32_t)&< array or variable >,
AnnaBridge	172:65be27845400	1267	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
AnnaBridge	172:65be27845400	1268	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
AnnaBridge	172:65be27845400	1269	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	172:65be27845400	1270	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	172:65be27845400	1271	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	172:65be27845400	1272	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	172:65be27845400	1273	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	172:65be27845400	1274	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
AnnaBridge	172:65be27845400	1275	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1276	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1277	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1278	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1279	* @param Register This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1280	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
AnnaBridge	172:65be27845400	1281	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
AnnaBridge	172:65be27845400	1282	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
AnnaBridge	172:65be27845400	1283	* @retval DAC register address
AnnaBridge	172:65be27845400	1284	*/
AnnaBridge	172:65be27845400	1285	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
AnnaBridge	172:65be27845400	1286	{
AnnaBridge	172:65be27845400	1287	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
AnnaBridge	172:65be27845400	1288	/* DAC channel selected. */
AnnaBridge	172:65be27845400	1289	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
AnnaBridge	172:65be27845400	1290	}
AnnaBridge	172:65be27845400	1291	/**
AnnaBridge	172:65be27845400	1292	* @}
AnnaBridge	172:65be27845400	1293	*/
AnnaBridge	172:65be27845400	1294
AnnaBridge	172:65be27845400	1295	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
AnnaBridge	172:65be27845400	1296	* @{
AnnaBridge	172:65be27845400	1297	*/
AnnaBridge	172:65be27845400	1298
AnnaBridge	172:65be27845400	1299	/**
AnnaBridge	172:65be27845400	1300	* @brief Enable DAC selected channel.
AnnaBridge	172:65be27845400	1301	* @rmtoll CR EN1 LL_DAC_Enable\n
AnnaBridge	172:65be27845400	1302	* CR EN2 LL_DAC_Enable
AnnaBridge	172:65be27845400	1303	* @note After enable from off state, DAC channel requires a delay
AnnaBridge	172:65be27845400	1304	* for output voltage to reach accuracy +/- 1 LSB.
AnnaBridge	172:65be27845400	1305	* Refer to device datasheet, parameter "tWAKEUP".
AnnaBridge	172:65be27845400	1306	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1307	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1308	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1309	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1310	* @retval None
AnnaBridge	172:65be27845400	1311	*/
AnnaBridge	172:65be27845400	1312	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1313	{
AnnaBridge	172:65be27845400	1314	SET_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1315	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1316	}
AnnaBridge	172:65be27845400	1317
AnnaBridge	172:65be27845400	1318	/**
AnnaBridge	172:65be27845400	1319	* @brief Disable DAC selected channel.
AnnaBridge	172:65be27845400	1320	* @rmtoll CR EN1 LL_DAC_Disable\n
AnnaBridge	172:65be27845400	1321	* CR EN2 LL_DAC_Disable
AnnaBridge	172:65be27845400	1322	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1323	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1324	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1325	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1326	* @retval None
AnnaBridge	172:65be27845400	1327	*/
AnnaBridge	172:65be27845400	1328	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1329	{
AnnaBridge	172:65be27845400	1330	CLEAR_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1331	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1332	}
AnnaBridge	172:65be27845400	1333
AnnaBridge	172:65be27845400	1334	/**
AnnaBridge	172:65be27845400	1335	* @brief Get DAC enable state of the selected channel.
AnnaBridge	172:65be27845400	1336	* (0: DAC channel is disabled, 1: DAC channel is enabled)
AnnaBridge	172:65be27845400	1337	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
AnnaBridge	172:65be27845400	1338	* CR EN2 LL_DAC_IsEnabled
AnnaBridge	172:65be27845400	1339	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1340	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1341	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1342	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1343	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1344	*/
AnnaBridge	172:65be27845400	1345	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1346	{
AnnaBridge	172:65be27845400	1347	return ((READ_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1348	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	1349	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1350	}
AnnaBridge	172:65be27845400	1351
AnnaBridge	172:65be27845400	1352	/**
AnnaBridge	172:65be27845400	1353	* @brief Enable DAC trigger of the selected channel.
AnnaBridge	172:65be27845400	1354	* @note - If DAC trigger is disabled, DAC conversion is performed
AnnaBridge	172:65be27845400	1355	* automatically once the data holding register is updated,
AnnaBridge	172:65be27845400	1356	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	172:65be27845400	1357	* @ref LL_DAC_ConvertData12RightAligned(), ...
AnnaBridge	172:65be27845400	1358	* - If DAC trigger is enabled, DAC conversion is performed
AnnaBridge	172:65be27845400	1359	* only when a hardware of software trigger event is occurring.
AnnaBridge	172:65be27845400	1360	* Select trigger source using
AnnaBridge	172:65be27845400	1361	* function @ref LL_DAC_SetTriggerSource().
AnnaBridge	172:65be27845400	1362	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
AnnaBridge	172:65be27845400	1363	* CR TEN2 LL_DAC_EnableTrigger
AnnaBridge	172:65be27845400	1364	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1365	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1366	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1367	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1368	* @retval None
AnnaBridge	172:65be27845400	1369	*/
AnnaBridge	172:65be27845400	1370	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1371	{
AnnaBridge	172:65be27845400	1372	SET_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1373	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1374	}
AnnaBridge	172:65be27845400	1375
AnnaBridge	172:65be27845400	1376	/**
AnnaBridge	172:65be27845400	1377	* @brief Disable DAC trigger of the selected channel.
AnnaBridge	172:65be27845400	1378	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
AnnaBridge	172:65be27845400	1379	* CR TEN2 LL_DAC_DisableTrigger
AnnaBridge	172:65be27845400	1380	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1381	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1382	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1383	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1384	* @retval None
AnnaBridge	172:65be27845400	1385	*/
AnnaBridge	172:65be27845400	1386	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1387	{
AnnaBridge	172:65be27845400	1388	CLEAR_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1389	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	172:65be27845400	1390	}
AnnaBridge	172:65be27845400	1391
AnnaBridge	172:65be27845400	1392	/**
AnnaBridge	172:65be27845400	1393	* @brief Get DAC trigger state of the selected channel.
AnnaBridge	172:65be27845400	1394	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
AnnaBridge	172:65be27845400	1395	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
AnnaBridge	172:65be27845400	1396	* CR TEN2 LL_DAC_IsTriggerEnabled
AnnaBridge	172:65be27845400	1397	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1398	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1399	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1400	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1401	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1402	*/
AnnaBridge	172:65be27845400	1403	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1404	{
AnnaBridge	172:65be27845400	1405	return ((READ_BIT(DACx->CR,
AnnaBridge	172:65be27845400	1406	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	172:65be27845400	1407	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1408	}
AnnaBridge	172:65be27845400	1409
AnnaBridge	172:65be27845400	1410	/**
AnnaBridge	172:65be27845400	1411	* @brief Trig DAC conversion by software for the selected DAC channel.
AnnaBridge	172:65be27845400	1412	* @note Preliminarily, DAC trigger must be set to software trigger
AnnaBridge	172:65be27845400	1413	* using function
AnnaBridge	172:65be27845400	1414	* @ref LL_DAC_Init()
AnnaBridge	172:65be27845400	1415	* @ref LL_DAC_SetTriggerSource()
AnnaBridge	172:65be27845400	1416	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
AnnaBridge	172:65be27845400	1417	* and DAC trigger must be enabled using
AnnaBridge	172:65be27845400	1418	* function @ref LL_DAC_EnableTrigger().
AnnaBridge	172:65be27845400	1419	* @note For devices featuring DAC with 2 channels: this function
AnnaBridge	172:65be27845400	1420	* can perform a SW start of both DAC channels simultaneously.
AnnaBridge	172:65be27845400	1421	* Two channels can be selected as parameter.
AnnaBridge	172:65be27845400	1422	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
AnnaBridge	172:65be27845400	1423	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
AnnaBridge	172:65be27845400	1424	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
AnnaBridge	172:65be27845400	1425	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1426	* @param DAC_Channel This parameter can a combination of the following values:
AnnaBridge	172:65be27845400	1427	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1428	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1429	* @retval None
AnnaBridge	172:65be27845400	1430	*/
AnnaBridge	172:65be27845400	1431	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1432	{
AnnaBridge	172:65be27845400	1433	SET_BIT(DACx->SWTRIGR,
AnnaBridge	172:65be27845400	1434	(DAC_Channel & DAC_SWTR_CHX_MASK));
AnnaBridge	172:65be27845400	1435	}
AnnaBridge	172:65be27845400	1436
AnnaBridge	172:65be27845400	1437	/**
AnnaBridge	172:65be27845400	1438	* @brief Set the data to be loaded in the data holding register
AnnaBridge	172:65be27845400	1439	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	172:65be27845400	1440	* for the selected DAC channel.
AnnaBridge	172:65be27845400	1441	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
AnnaBridge	172:65be27845400	1442	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
AnnaBridge	172:65be27845400	1443	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1444	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1445	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1446	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1447	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1448	* @retval None
AnnaBridge	172:65be27845400	1449	*/
AnnaBridge	172:65be27845400	1450	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	172:65be27845400	1451	{
AnnaBridge	172:65be27845400	1452	register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
AnnaBridge	172:65be27845400	1453
AnnaBridge	172:65be27845400	1454	MODIFY_REG(*preg,
AnnaBridge	172:65be27845400	1455	DAC_DHR12R1_DACC1DHR,
AnnaBridge	172:65be27845400	1456	Data);
AnnaBridge	172:65be27845400	1457	}
AnnaBridge	172:65be27845400	1458
AnnaBridge	172:65be27845400	1459	/**
AnnaBridge	172:65be27845400	1460	* @brief Set the data to be loaded in the data holding register
AnnaBridge	172:65be27845400	1461	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	172:65be27845400	1462	* for the selected DAC channel.
AnnaBridge	172:65be27845400	1463	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
AnnaBridge	172:65be27845400	1464	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
AnnaBridge	172:65be27845400	1465	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1466	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1467	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1468	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1469	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1470	* @retval None
AnnaBridge	172:65be27845400	1471	*/
AnnaBridge	172:65be27845400	1472	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	172:65be27845400	1473	{
AnnaBridge	172:65be27845400	1474	register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
AnnaBridge	172:65be27845400	1475
AnnaBridge	172:65be27845400	1476	MODIFY_REG(*preg,
AnnaBridge	172:65be27845400	1477	DAC_DHR12L1_DACC1DHR,
AnnaBridge	172:65be27845400	1478	Data);
AnnaBridge	172:65be27845400	1479	}
AnnaBridge	172:65be27845400	1480
AnnaBridge	172:65be27845400	1481	/**
AnnaBridge	172:65be27845400	1482	* @brief Set the data to be loaded in the data holding register
AnnaBridge	172:65be27845400	1483	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	172:65be27845400	1484	* for the selected DAC channel.
AnnaBridge	172:65be27845400	1485	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
AnnaBridge	172:65be27845400	1486	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
AnnaBridge	172:65be27845400	1487	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1488	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1489	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1490	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1491	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	1492	* @retval None
AnnaBridge	172:65be27845400	1493	*/
AnnaBridge	172:65be27845400	1494	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	172:65be27845400	1495	{
AnnaBridge	172:65be27845400	1496	register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
AnnaBridge	172:65be27845400	1497
AnnaBridge	172:65be27845400	1498	MODIFY_REG(*preg,
AnnaBridge	172:65be27845400	1499	DAC_DHR8R1_DACC1DHR,
AnnaBridge	172:65be27845400	1500	Data);
AnnaBridge	172:65be27845400	1501	}
AnnaBridge	172:65be27845400	1502
AnnaBridge	172:65be27845400	1503
AnnaBridge	172:65be27845400	1504	/**
AnnaBridge	172:65be27845400	1505	* @brief Set the data to be loaded in the data holding register
AnnaBridge	172:65be27845400	1506	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	172:65be27845400	1507	* for both DAC channels.
AnnaBridge	172:65be27845400	1508	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
AnnaBridge	172:65be27845400	1509	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
AnnaBridge	172:65be27845400	1510	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1511	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1512	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1513	* @retval None
AnnaBridge	172:65be27845400	1514	*/
AnnaBridge	172:65be27845400	1515	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	172:65be27845400	1516	{
AnnaBridge	172:65be27845400	1517	MODIFY_REG(DACx->DHR12RD,
AnnaBridge	172:65be27845400	1518	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
AnnaBridge	172:65be27845400	1519	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	172:65be27845400	1520	}
AnnaBridge	172:65be27845400	1521
AnnaBridge	172:65be27845400	1522	/**
AnnaBridge	172:65be27845400	1523	* @brief Set the data to be loaded in the data holding register
AnnaBridge	172:65be27845400	1524	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	172:65be27845400	1525	* for both DAC channels.
AnnaBridge	172:65be27845400	1526	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
AnnaBridge	172:65be27845400	1527	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
AnnaBridge	172:65be27845400	1528	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1529	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1530	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1531	* @retval None
AnnaBridge	172:65be27845400	1532	*/
AnnaBridge	172:65be27845400	1533	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	172:65be27845400	1534	{
AnnaBridge	172:65be27845400	1535	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
AnnaBridge	172:65be27845400	1536	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
AnnaBridge	172:65be27845400	1537	/* the 4 LSB must be taken into account for the shift value. */
AnnaBridge	172:65be27845400	1538	MODIFY_REG(DACx->DHR12LD,
AnnaBridge	172:65be27845400	1539	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
AnnaBridge	172:65be27845400	1540	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
AnnaBridge	172:65be27845400	1541	}
AnnaBridge	172:65be27845400	1542
AnnaBridge	172:65be27845400	1543	/**
AnnaBridge	172:65be27845400	1544	* @brief Set the data to be loaded in the data holding register
AnnaBridge	172:65be27845400	1545	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	172:65be27845400	1546	* for both DAC channels.
AnnaBridge	172:65be27845400	1547	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
AnnaBridge	172:65be27845400	1548	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
AnnaBridge	172:65be27845400	1549	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1550	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	1551	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	172:65be27845400	1552	* @retval None
AnnaBridge	172:65be27845400	1553	*/
AnnaBridge	172:65be27845400	1554	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	172:65be27845400	1555	{
AnnaBridge	172:65be27845400	1556	MODIFY_REG(DACx->DHR8RD,
AnnaBridge	172:65be27845400	1557	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
AnnaBridge	172:65be27845400	1558	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	172:65be27845400	1559	}
AnnaBridge	172:65be27845400	1560
AnnaBridge	172:65be27845400	1561
AnnaBridge	172:65be27845400	1562	/**
AnnaBridge	172:65be27845400	1563	* @brief Retrieve output data currently generated for the selected DAC channel.
AnnaBridge	172:65be27845400	1564	* @note Whatever alignment and resolution settings
AnnaBridge	172:65be27845400	1565	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	172:65be27845400	1566	* @ref LL_DAC_ConvertData12RightAligned(), ...),
AnnaBridge	172:65be27845400	1567	* output data format is 12 bits right aligned (LSB aligned on bit 0).
AnnaBridge	172:65be27845400	1568	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
AnnaBridge	172:65be27845400	1569	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
AnnaBridge	172:65be27845400	1570	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1571	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1572	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	172:65be27845400	1573	* @arg @ref LL_DAC_CHANNEL_2
AnnaBridge	172:65be27845400	1574	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	172:65be27845400	1575	*/
AnnaBridge	172:65be27845400	1576	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	172:65be27845400	1577	{
AnnaBridge	172:65be27845400	1578	register __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
AnnaBridge	172:65be27845400	1579
AnnaBridge	172:65be27845400	1580	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
AnnaBridge	172:65be27845400	1581	}
AnnaBridge	172:65be27845400	1582
AnnaBridge	172:65be27845400	1583	/**
AnnaBridge	172:65be27845400	1584	* @}
AnnaBridge	172:65be27845400	1585	*/
AnnaBridge	172:65be27845400	1586
AnnaBridge	172:65be27845400	1587	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	172:65be27845400	1588	* @{
AnnaBridge	172:65be27845400	1589	*/
AnnaBridge	172:65be27845400	1590	/**
AnnaBridge	172:65be27845400	1591	* @brief Get DAC calibration offset flag for DAC channel 1
AnnaBridge	172:65be27845400	1592	* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
AnnaBridge	172:65be27845400	1593	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1594	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1595	*/
AnnaBridge	172:65be27845400	1596	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1597	{
AnnaBridge	172:65be27845400	1598	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1599	}
AnnaBridge	172:65be27845400	1600
AnnaBridge	172:65be27845400	1601
AnnaBridge	172:65be27845400	1602	/**
AnnaBridge	172:65be27845400	1603	* @brief Get DAC calibration offset flag for DAC channel 2
AnnaBridge	172:65be27845400	1604	* @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
AnnaBridge	172:65be27845400	1605	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1606	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1607	*/
AnnaBridge	172:65be27845400	1608	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1609	{
AnnaBridge	172:65be27845400	1610	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1611	}
AnnaBridge	172:65be27845400	1612
AnnaBridge	172:65be27845400	1613
AnnaBridge	172:65be27845400	1614	/**
AnnaBridge	172:65be27845400	1615	* @brief Get DAC busy writing sample time flag for DAC channel 1
AnnaBridge	172:65be27845400	1616	* @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
AnnaBridge	172:65be27845400	1617	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1618	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1619	*/
AnnaBridge	172:65be27845400	1620	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1621	{
AnnaBridge	172:65be27845400	1622	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1623	}
AnnaBridge	172:65be27845400	1624
AnnaBridge	172:65be27845400	1625
AnnaBridge	172:65be27845400	1626	/**
AnnaBridge	172:65be27845400	1627	* @brief Get DAC busy writing sample time flag for DAC channel 2
AnnaBridge	172:65be27845400	1628	* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
AnnaBridge	172:65be27845400	1629	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1630	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1631	*/
AnnaBridge	172:65be27845400	1632	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1633	{
AnnaBridge	172:65be27845400	1634	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1635	}
AnnaBridge	172:65be27845400	1636
AnnaBridge	172:65be27845400	1637
AnnaBridge	172:65be27845400	1638	/**
AnnaBridge	172:65be27845400	1639	* @brief Get DAC underrun flag for DAC channel 1
AnnaBridge	172:65be27845400	1640	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
AnnaBridge	172:65be27845400	1641	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1642	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1643	*/
AnnaBridge	172:65be27845400	1644	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1645	{
AnnaBridge	172:65be27845400	1646	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1647	}
AnnaBridge	172:65be27845400	1648
AnnaBridge	172:65be27845400	1649
AnnaBridge	172:65be27845400	1650	/**
AnnaBridge	172:65be27845400	1651	* @brief Get DAC underrun flag for DAC channel 2
AnnaBridge	172:65be27845400	1652	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
AnnaBridge	172:65be27845400	1653	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1654	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1655	*/
AnnaBridge	172:65be27845400	1656	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1657	{
AnnaBridge	172:65be27845400	1658	return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1659	}
AnnaBridge	172:65be27845400	1660
AnnaBridge	172:65be27845400	1661
AnnaBridge	172:65be27845400	1662	/**
AnnaBridge	172:65be27845400	1663	* @brief Clear DAC underrun flag for DAC channel 1
AnnaBridge	172:65be27845400	1664	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
AnnaBridge	172:65be27845400	1665	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1666	* @retval None
AnnaBridge	172:65be27845400	1667	*/
AnnaBridge	172:65be27845400	1668	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1669	{
AnnaBridge	172:65be27845400	1670	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
AnnaBridge	172:65be27845400	1671	}
AnnaBridge	172:65be27845400	1672
AnnaBridge	172:65be27845400	1673
AnnaBridge	172:65be27845400	1674	/**
AnnaBridge	172:65be27845400	1675	* @brief Clear DAC underrun flag for DAC channel 2
AnnaBridge	172:65be27845400	1676	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
AnnaBridge	172:65be27845400	1677	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1678	* @retval None
AnnaBridge	172:65be27845400	1679	*/
AnnaBridge	172:65be27845400	1680	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1681	{
AnnaBridge	172:65be27845400	1682	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
AnnaBridge	172:65be27845400	1683	}
AnnaBridge	172:65be27845400	1684
AnnaBridge	172:65be27845400	1685
AnnaBridge	172:65be27845400	1686	/**
AnnaBridge	172:65be27845400	1687	* @}
AnnaBridge	172:65be27845400	1688	*/
AnnaBridge	172:65be27845400	1689
AnnaBridge	172:65be27845400	1690	/** @defgroup DAC_LL_EF_IT_Management IT management
AnnaBridge	172:65be27845400	1691	* @{
AnnaBridge	172:65be27845400	1692	*/
AnnaBridge	172:65be27845400	1693
AnnaBridge	172:65be27845400	1694	/**
AnnaBridge	172:65be27845400	1695	* @brief Enable DMA underrun interrupt for DAC channel 1
AnnaBridge	172:65be27845400	1696	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
AnnaBridge	172:65be27845400	1697	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1698	* @retval None
AnnaBridge	172:65be27845400	1699	*/
AnnaBridge	172:65be27845400	1700	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1701	{
AnnaBridge	172:65be27845400	1702	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	172:65be27845400	1703	}
AnnaBridge	172:65be27845400	1704
AnnaBridge	172:65be27845400	1705
AnnaBridge	172:65be27845400	1706	/**
AnnaBridge	172:65be27845400	1707	* @brief Enable DMA underrun interrupt for DAC channel 2
AnnaBridge	172:65be27845400	1708	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
AnnaBridge	172:65be27845400	1709	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1710	* @retval None
AnnaBridge	172:65be27845400	1711	*/
AnnaBridge	172:65be27845400	1712	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1713	{
AnnaBridge	172:65be27845400	1714	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	172:65be27845400	1715	}
AnnaBridge	172:65be27845400	1716
AnnaBridge	172:65be27845400	1717
AnnaBridge	172:65be27845400	1718	/**
AnnaBridge	172:65be27845400	1719	* @brief Disable DMA underrun interrupt for DAC channel 1
AnnaBridge	172:65be27845400	1720	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
AnnaBridge	172:65be27845400	1721	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1722	* @retval None
AnnaBridge	172:65be27845400	1723	*/
AnnaBridge	172:65be27845400	1724	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1725	{
AnnaBridge	172:65be27845400	1726	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	172:65be27845400	1727	}
AnnaBridge	172:65be27845400	1728
AnnaBridge	172:65be27845400	1729
AnnaBridge	172:65be27845400	1730	/**
AnnaBridge	172:65be27845400	1731	* @brief Disable DMA underrun interrupt for DAC channel 2
AnnaBridge	172:65be27845400	1732	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
AnnaBridge	172:65be27845400	1733	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1734	* @retval None
AnnaBridge	172:65be27845400	1735	*/
AnnaBridge	172:65be27845400	1736	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1737	{
AnnaBridge	172:65be27845400	1738	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	172:65be27845400	1739	}
AnnaBridge	172:65be27845400	1740
AnnaBridge	172:65be27845400	1741
AnnaBridge	172:65be27845400	1742	/**
AnnaBridge	172:65be27845400	1743	* @brief Get DMA underrun interrupt for DAC channel 1
AnnaBridge	172:65be27845400	1744	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
AnnaBridge	172:65be27845400	1745	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1746	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1747	*/
AnnaBridge	172:65be27845400	1748	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1749	{
AnnaBridge	172:65be27845400	1750	return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1751	}
AnnaBridge	172:65be27845400	1752
AnnaBridge	172:65be27845400	1753
AnnaBridge	172:65be27845400	1754	/**
AnnaBridge	172:65be27845400	1755	* @brief Get DMA underrun interrupt for DAC channel 2
AnnaBridge	172:65be27845400	1756	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
AnnaBridge	172:65be27845400	1757	* @param DACx DAC instance
AnnaBridge	172:65be27845400	1758	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1759	*/
AnnaBridge	172:65be27845400	1760	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	172:65be27845400	1761	{
AnnaBridge	172:65be27845400	1762	return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
AnnaBridge	172:65be27845400	1763	}
AnnaBridge	172:65be27845400	1764
AnnaBridge	172:65be27845400	1765
AnnaBridge	172:65be27845400	1766	/**
AnnaBridge	172:65be27845400	1767	* @}
AnnaBridge	172:65be27845400	1768	*/
AnnaBridge	172:65be27845400	1769
AnnaBridge	172:65be27845400	1770	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	1771	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	172:65be27845400	1772	* @{
AnnaBridge	172:65be27845400	1773	*/
AnnaBridge	172:65be27845400	1774
AnnaBridge	172:65be27845400	1775	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
AnnaBridge	172:65be27845400	1776	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	172:65be27845400	1777	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	172:65be27845400	1778
AnnaBridge	172:65be27845400	1779	/**
AnnaBridge	172:65be27845400	1780	* @}
AnnaBridge	172:65be27845400	1781	*/
AnnaBridge	172:65be27845400	1782	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	1783
AnnaBridge	172:65be27845400	1784	/**
AnnaBridge	172:65be27845400	1785	* @}
AnnaBridge	172:65be27845400	1786	*/
AnnaBridge	172:65be27845400	1787
AnnaBridge	172:65be27845400	1788	/**
AnnaBridge	172:65be27845400	1789	* @}
AnnaBridge	172:65be27845400	1790	*/
AnnaBridge	172:65be27845400	1791
AnnaBridge	172:65be27845400	1792	#endif /* DAC1 */
AnnaBridge	172:65be27845400	1793
AnnaBridge	172:65be27845400	1794	/**
AnnaBridge	172:65be27845400	1795	* @}
AnnaBridge	172:65be27845400	1796	*/
AnnaBridge	172:65be27845400	1797
AnnaBridge	172:65be27845400	1798	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1799	}
AnnaBridge	172:65be27845400	1800	#endif
AnnaBridge	172:65be27845400	1801
AnnaBridge	172:65be27845400	1802	#endif /* __STM32H7xx_LL_DAC_H */
AnnaBridge	172:65be27845400	1803
AnnaBridge	172:65be27845400	1804	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/