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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_ll_bus.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_ll_bus.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @version $VERSION$
AnnaBridge	172:65be27845400	6	* @date $DATE$
AnnaBridge	172:65be27845400	7	* @brief Header file of BUS LL module.
AnnaBridge	172:65be27845400	8
AnnaBridge	172:65be27845400	9	@verbatim
AnnaBridge	172:65be27845400	10	##### RCC Limitations #####
AnnaBridge	172:65be27845400	11	==============================================================================
AnnaBridge	172:65be27845400	12	[..]
AnnaBridge	172:65be27845400	13	A delay between an RCC peripheral clock enable and the effective peripheral
AnnaBridge	172:65be27845400	14	enabling should be taken into account in order to manage the peripheral read/write
AnnaBridge	172:65be27845400	15	from/to registers.
AnnaBridge	172:65be27845400	16	(+) This delay depends on the peripheral mapping.
AnnaBridge	172:65be27845400	17	(++) AHB & APB peripherals, 1 dummy read is necessary
AnnaBridge	172:65be27845400	18
AnnaBridge	172:65be27845400	19	[..]
AnnaBridge	172:65be27845400	20	Workarounds:
AnnaBridge	172:65be27845400	21	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
AnnaBridge	172:65be27845400	22	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	@endverbatim
AnnaBridge	172:65be27845400	25	******************************************************************************
AnnaBridge	172:65be27845400	26	* @attention
AnnaBridge	172:65be27845400	27	*
AnnaBridge	172:65be27845400	28	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	29	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	30	*
AnnaBridge	172:65be27845400	31	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	32	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	33	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	34	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	35	*
AnnaBridge	172:65be27845400	36	******************************************************************************
AnnaBridge	172:65be27845400	37	*/
AnnaBridge	172:65be27845400	38
AnnaBridge	172:65be27845400	39	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	40	#ifndef STM32H7xx_LL_BUS_H
AnnaBridge	172:65be27845400	41	#define STM32H7xx_LL_BUS_H
AnnaBridge	172:65be27845400	42
AnnaBridge	172:65be27845400	43	#ifdef __cplusplus
AnnaBridge	172:65be27845400	44	extern "C" {
AnnaBridge	172:65be27845400	45	#endif
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	48	#include "stm32h7xx.h"
AnnaBridge	172:65be27845400	49
AnnaBridge	172:65be27845400	50	/** @addtogroup STM32H7xx_LL_Driver
AnnaBridge	172:65be27845400	51	* @{
AnnaBridge	172:65be27845400	52	*/
AnnaBridge	172:65be27845400	53
AnnaBridge	172:65be27845400	54	#if defined(RCC)
AnnaBridge	172:65be27845400	55
AnnaBridge	172:65be27845400	56	/** @defgroup BUS_LL BUS
AnnaBridge	172:65be27845400	57	* @{
AnnaBridge	172:65be27845400	58	*/
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	61
AnnaBridge	172:65be27845400	62	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	63
AnnaBridge	172:65be27845400	64	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	65
AnnaBridge	172:65be27845400	66	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	67
AnnaBridge	172:65be27845400	68	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	69	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
AnnaBridge	172:65be27845400	70	* @{
AnnaBridge	172:65be27845400	71	*/
AnnaBridge	172:65be27845400	72
AnnaBridge	172:65be27845400	73	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
AnnaBridge	172:65be27845400	74	* @{
AnnaBridge	172:65be27845400	75	*/
AnnaBridge	172:65be27845400	76	#define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN
AnnaBridge	172:65be27845400	77	#define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN
AnnaBridge	172:65be27845400	78	#define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN
AnnaBridge	172:65be27845400	79	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
AnnaBridge	172:65be27845400	80	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
AnnaBridge	172:65be27845400	81	#define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN
AnnaBridge	172:65be27845400	82	#define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN
AnnaBridge	172:65be27845400	83	#define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN
AnnaBridge	172:65be27845400	84	#define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN
AnnaBridge	172:65be27845400	85	#define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN
AnnaBridge	172:65be27845400	86	#define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN
AnnaBridge	172:65be27845400	87	/**
AnnaBridge	172:65be27845400	88	* @}
AnnaBridge	172:65be27845400	89	*/
AnnaBridge	172:65be27845400	90
AnnaBridge	172:65be27845400	91
AnnaBridge	172:65be27845400	92	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
AnnaBridge	172:65be27845400	93	* @{
AnnaBridge	172:65be27845400	94	*/
AnnaBridge	172:65be27845400	95	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
AnnaBridge	172:65be27845400	96	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
AnnaBridge	172:65be27845400	97	#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN
AnnaBridge	172:65be27845400	98	#define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN
AnnaBridge	172:65be27845400	99	#define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN
AnnaBridge	172:65be27845400	100	#define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN
AnnaBridge	172:65be27845400	101	#define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN
AnnaBridge	172:65be27845400	102	#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN
AnnaBridge	172:65be27845400	103	#define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN
AnnaBridge	172:65be27845400	104	#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN
AnnaBridge	172:65be27845400	105	/**
AnnaBridge	172:65be27845400	106	* @}
AnnaBridge	172:65be27845400	107	*/
AnnaBridge	172:65be27845400	108
AnnaBridge	172:65be27845400	109
AnnaBridge	172:65be27845400	110	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
AnnaBridge	172:65be27845400	111	* @{
AnnaBridge	172:65be27845400	112	*/
AnnaBridge	172:65be27845400	113	#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
AnnaBridge	172:65be27845400	114	#if defined(CRYP)
AnnaBridge	172:65be27845400	115	#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
AnnaBridge	172:65be27845400	116	#endif /* CRYP */
AnnaBridge	172:65be27845400	117	#if defined(HASH)
AnnaBridge	172:65be27845400	118	#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
AnnaBridge	172:65be27845400	119	#endif /* HASH */
AnnaBridge	172:65be27845400	120	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
AnnaBridge	172:65be27845400	121	#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN
AnnaBridge	172:65be27845400	122	#define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN
AnnaBridge	172:65be27845400	123	#define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN
AnnaBridge	172:65be27845400	124	#define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN
AnnaBridge	172:65be27845400	125	/**
AnnaBridge	172:65be27845400	126	* @}
AnnaBridge	172:65be27845400	127	*/
AnnaBridge	172:65be27845400	128
AnnaBridge	172:65be27845400	129
AnnaBridge	172:65be27845400	130	/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH
AnnaBridge	172:65be27845400	131	* @{
AnnaBridge	172:65be27845400	132	*/
AnnaBridge	172:65be27845400	133	#define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN
AnnaBridge	172:65be27845400	134	#define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN
AnnaBridge	172:65be27845400	135	#define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN
AnnaBridge	172:65be27845400	136	#define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN
AnnaBridge	172:65be27845400	137	#define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN
AnnaBridge	172:65be27845400	138	#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN
AnnaBridge	172:65be27845400	139	#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN
AnnaBridge	172:65be27845400	140	#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN
AnnaBridge	172:65be27845400	141	#define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN
AnnaBridge	172:65be27845400	142	#define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN
AnnaBridge	172:65be27845400	143	#define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN
AnnaBridge	172:65be27845400	144	#define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN
AnnaBridge	172:65be27845400	145	#define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN
AnnaBridge	172:65be27845400	146	#define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN
AnnaBridge	172:65be27845400	147	#if defined(HSEM)
AnnaBridge	172:65be27845400	148	#define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN
AnnaBridge	172:65be27845400	149	#endif /* HSEM */
AnnaBridge	172:65be27845400	150	#define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN
AnnaBridge	172:65be27845400	151	#define LL_AHB4_GRP1_PERIPH_D3SRAM1 RCC_AHB4ENR_D3SRAM1EN
AnnaBridge	172:65be27845400	152	/**
AnnaBridge	172:65be27845400	153	* @}
AnnaBridge	172:65be27845400	154	*/
AnnaBridge	172:65be27845400	155
AnnaBridge	172:65be27845400	156
AnnaBridge	172:65be27845400	157	/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
AnnaBridge	172:65be27845400	158	* @{
AnnaBridge	172:65be27845400	159	*/
AnnaBridge	172:65be27845400	160	#define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN
AnnaBridge	172:65be27845400	161	#define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN
AnnaBridge	172:65be27845400	162	/**
AnnaBridge	172:65be27845400	163	* @}
AnnaBridge	172:65be27845400	164	*/
AnnaBridge	172:65be27845400	165
AnnaBridge	172:65be27845400	166
AnnaBridge	172:65be27845400	167	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
AnnaBridge	172:65be27845400	168	* @{
AnnaBridge	172:65be27845400	169	*/
AnnaBridge	172:65be27845400	170	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN
AnnaBridge	172:65be27845400	171	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN
AnnaBridge	172:65be27845400	172	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN
AnnaBridge	172:65be27845400	173	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN
AnnaBridge	172:65be27845400	174	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN
AnnaBridge	172:65be27845400	175	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN
AnnaBridge	172:65be27845400	176	#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN
AnnaBridge	172:65be27845400	177	#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN
AnnaBridge	172:65be27845400	178	#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN
AnnaBridge	172:65be27845400	179	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN
AnnaBridge	172:65be27845400	180	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN
AnnaBridge	172:65be27845400	181	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN
AnnaBridge	172:65be27845400	182	#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN
AnnaBridge	172:65be27845400	183	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN
AnnaBridge	172:65be27845400	184	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN
AnnaBridge	172:65be27845400	185	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN
AnnaBridge	172:65be27845400	186	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN
AnnaBridge	172:65be27845400	187	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN
AnnaBridge	172:65be27845400	188	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN
AnnaBridge	172:65be27845400	189	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN
AnnaBridge	172:65be27845400	190	#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN
AnnaBridge	172:65be27845400	191	#define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN
AnnaBridge	172:65be27845400	192	#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN
AnnaBridge	172:65be27845400	193	#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN
AnnaBridge	172:65be27845400	194	/**
AnnaBridge	172:65be27845400	195	* @}
AnnaBridge	172:65be27845400	196	*/
AnnaBridge	172:65be27845400	197
AnnaBridge	172:65be27845400	198
AnnaBridge	172:65be27845400	199	/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
AnnaBridge	172:65be27845400	200	* @{
AnnaBridge	172:65be27845400	201	*/
AnnaBridge	172:65be27845400	202	#define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN
AnnaBridge	172:65be27845400	203	#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN
AnnaBridge	172:65be27845400	204	#define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN
AnnaBridge	172:65be27845400	205	#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN
AnnaBridge	172:65be27845400	206	#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN
AnnaBridge	172:65be27845400	207	/**
AnnaBridge	172:65be27845400	208	* @}
AnnaBridge	172:65be27845400	209	*/
AnnaBridge	172:65be27845400	210
AnnaBridge	172:65be27845400	211
AnnaBridge	172:65be27845400	212	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
AnnaBridge	172:65be27845400	213	* @{
AnnaBridge	172:65be27845400	214	*/
AnnaBridge	172:65be27845400	215	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
AnnaBridge	172:65be27845400	216	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
AnnaBridge	172:65be27845400	217	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
AnnaBridge	172:65be27845400	218	#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
AnnaBridge	172:65be27845400	219	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
AnnaBridge	172:65be27845400	220	#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
AnnaBridge	172:65be27845400	221	#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
AnnaBridge	172:65be27845400	222	#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
AnnaBridge	172:65be27845400	223	#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
AnnaBridge	172:65be27845400	224	#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
AnnaBridge	172:65be27845400	225	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
AnnaBridge	172:65be27845400	226	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
AnnaBridge	172:65be27845400	227	#define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN
AnnaBridge	172:65be27845400	228	#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
AnnaBridge	172:65be27845400	229	#define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN
AnnaBridge	172:65be27845400	230	/**
AnnaBridge	172:65be27845400	231	* @}
AnnaBridge	172:65be27845400	232	*/
AnnaBridge	172:65be27845400	233
AnnaBridge	172:65be27845400	234
AnnaBridge	172:65be27845400	235	/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH
AnnaBridge	172:65be27845400	236	* @{
AnnaBridge	172:65be27845400	237	*/
AnnaBridge	172:65be27845400	238	#define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN
AnnaBridge	172:65be27845400	239	#define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN
AnnaBridge	172:65be27845400	240	#define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN
AnnaBridge	172:65be27845400	241	#define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN
AnnaBridge	172:65be27845400	242	#define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN
AnnaBridge	172:65be27845400	243	#define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN
AnnaBridge	172:65be27845400	244	#define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN
AnnaBridge	172:65be27845400	245	#define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN
AnnaBridge	172:65be27845400	246	#define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN
AnnaBridge	172:65be27845400	247	#define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN
AnnaBridge	172:65be27845400	248	#define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN
AnnaBridge	172:65be27845400	249	#define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN
AnnaBridge	172:65be27845400	250	/**
AnnaBridge	172:65be27845400	251	* @}
AnnaBridge	172:65be27845400	252	*/
AnnaBridge	172:65be27845400	253
AnnaBridge	172:65be27845400	254	/** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH
AnnaBridge	172:65be27845400	255	* @{
AnnaBridge	172:65be27845400	256	*/
AnnaBridge	172:65be27845400	257	#define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN
AnnaBridge	172:65be27845400	258	#define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN
AnnaBridge	172:65be27845400	259	#define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN
AnnaBridge	172:65be27845400	260	#define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN
AnnaBridge	172:65be27845400	261	#define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN
AnnaBridge	172:65be27845400	262	#define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN
AnnaBridge	172:65be27845400	263	#define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN
AnnaBridge	172:65be27845400	264	#define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN
AnnaBridge	172:65be27845400	265	#define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN
AnnaBridge	172:65be27845400	266	#define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN
AnnaBridge	172:65be27845400	267	#define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN
AnnaBridge	172:65be27845400	268	#define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN
AnnaBridge	172:65be27845400	269	#define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN
AnnaBridge	172:65be27845400	270	#define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN
AnnaBridge	172:65be27845400	271	#define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN
AnnaBridge	172:65be27845400	272	#define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN
AnnaBridge	172:65be27845400	273	/**
AnnaBridge	172:65be27845400	274	* @}
AnnaBridge	172:65be27845400	275	*/
AnnaBridge	172:65be27845400	276
AnnaBridge	172:65be27845400	277	/**
AnnaBridge	172:65be27845400	278	* @}
AnnaBridge	172:65be27845400	279	*/
AnnaBridge	172:65be27845400	280
AnnaBridge	172:65be27845400	281	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	282
AnnaBridge	172:65be27845400	283	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	284
AnnaBridge	172:65be27845400	285	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
AnnaBridge	172:65be27845400	286	* @{
AnnaBridge	172:65be27845400	287	*/
AnnaBridge	172:65be27845400	288
AnnaBridge	172:65be27845400	289	/** @defgroup BUS_LL_EF_AHB3 AHB3
AnnaBridge	172:65be27845400	290	* @{
AnnaBridge	172:65be27845400	291	*/
AnnaBridge	172:65be27845400	292
AnnaBridge	172:65be27845400	293	/**
AnnaBridge	172:65be27845400	294	* @brief Enable AHB3 peripherals clock.
AnnaBridge	172:65be27845400	295	* @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	296	* AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	297	* AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	298	* AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	299	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	300	* AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	301	* AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	302	* AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	303	* AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	304	* AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	305	* AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock
AnnaBridge	172:65be27845400	306	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	307	* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
AnnaBridge	172:65be27845400	308	* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
AnnaBridge	172:65be27845400	309	* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
AnnaBridge	172:65be27845400	310	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
AnnaBridge	172:65be27845400	311	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
AnnaBridge	172:65be27845400	312	* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
AnnaBridge	172:65be27845400	313	* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
AnnaBridge	172:65be27845400	314	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
AnnaBridge	172:65be27845400	315	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
AnnaBridge	172:65be27845400	316	* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
AnnaBridge	172:65be27845400	317	* @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
AnnaBridge	172:65be27845400	318	*
AnnaBridge	172:65be27845400	319	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	320	* @retval None
AnnaBridge	172:65be27845400	321	*/
AnnaBridge	172:65be27845400	322	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	323	{
AnnaBridge	172:65be27845400	324	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	325	SET_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	172:65be27845400	326	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	327	tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	172:65be27845400	328	(void)tmpreg;
AnnaBridge	172:65be27845400	329	}
AnnaBridge	172:65be27845400	330
AnnaBridge	172:65be27845400	331	/**
AnnaBridge	172:65be27845400	332	* @brief Check if AHB3 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	333	* @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	334	* AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	335	* AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	336	* AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	337	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	338	* AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	339	* AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	340	* AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	341	* AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	342	* AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	343	* AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	344	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	345	* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
AnnaBridge	172:65be27845400	346	* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
AnnaBridge	172:65be27845400	347	* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
AnnaBridge	172:65be27845400	348	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
AnnaBridge	172:65be27845400	349	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
AnnaBridge	172:65be27845400	350	* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
AnnaBridge	172:65be27845400	351	* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
AnnaBridge	172:65be27845400	352	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
AnnaBridge	172:65be27845400	353	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
AnnaBridge	172:65be27845400	354	* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
AnnaBridge	172:65be27845400	355	* @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
AnnaBridge	172:65be27845400	356	*
AnnaBridge	172:65be27845400	357	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	358	* @retval uint32_t
AnnaBridge	172:65be27845400	359	*/
AnnaBridge	172:65be27845400	360	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	361	{
AnnaBridge	172:65be27845400	362	return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	363	}
AnnaBridge	172:65be27845400	364
AnnaBridge	172:65be27845400	365	/**
AnnaBridge	172:65be27845400	366	* @brief Disable AHB3 peripherals clock.
AnnaBridge	172:65be27845400	367	* @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	368	* AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	369	* AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	370	* AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	371	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	372	* AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	373	* AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	374	* AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	375	* AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	376	* AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	377	* AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock
AnnaBridge	172:65be27845400	378	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	379	* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
AnnaBridge	172:65be27845400	380	* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
AnnaBridge	172:65be27845400	381	* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
AnnaBridge	172:65be27845400	382	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
AnnaBridge	172:65be27845400	383	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
AnnaBridge	172:65be27845400	384	* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
AnnaBridge	172:65be27845400	385	* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)
AnnaBridge	172:65be27845400	386	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)
AnnaBridge	172:65be27845400	387	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)
AnnaBridge	172:65be27845400	388	* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)
AnnaBridge	172:65be27845400	389	* @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)
AnnaBridge	172:65be27845400	390	*
AnnaBridge	172:65be27845400	391	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	392	* @retval None
AnnaBridge	172:65be27845400	393	*/
AnnaBridge	172:65be27845400	394	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	395	{
AnnaBridge	172:65be27845400	396	CLEAR_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	172:65be27845400	397	}
AnnaBridge	172:65be27845400	398
AnnaBridge	172:65be27845400	399	/**
AnnaBridge	172:65be27845400	400	* @brief Force AHB3 peripherals reset.
AnnaBridge	172:65be27845400	401	* @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	402	* AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	403	* AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	404	* AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	405	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	406	* AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset
AnnaBridge	172:65be27845400	407	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	408	* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
AnnaBridge	172:65be27845400	409	* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
AnnaBridge	172:65be27845400	410	* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
AnnaBridge	172:65be27845400	411	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
AnnaBridge	172:65be27845400	412	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
AnnaBridge	172:65be27845400	413	* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
AnnaBridge	172:65be27845400	414	* @retval None
AnnaBridge	172:65be27845400	415	*/
AnnaBridge	172:65be27845400	416	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	417	{
AnnaBridge	172:65be27845400	418	SET_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	172:65be27845400	419	}
AnnaBridge	172:65be27845400	420
AnnaBridge	172:65be27845400	421	/**
AnnaBridge	172:65be27845400	422	* @brief Release AHB3 peripherals reset.
AnnaBridge	172:65be27845400	423	* @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	424	* AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	425	* AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	426	* AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	427	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	428	* AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset
AnnaBridge	172:65be27845400	429	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	430	* @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
AnnaBridge	172:65be27845400	431	* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
AnnaBridge	172:65be27845400	432	* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
AnnaBridge	172:65be27845400	433	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
AnnaBridge	172:65be27845400	434	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
AnnaBridge	172:65be27845400	435	* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
AnnaBridge	172:65be27845400	436	* @retval None
AnnaBridge	172:65be27845400	437	*/
AnnaBridge	172:65be27845400	438	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	439	{
AnnaBridge	172:65be27845400	440	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	172:65be27845400	441	}
AnnaBridge	172:65be27845400	442
AnnaBridge	172:65be27845400	443	/**
AnnaBridge	172:65be27845400	444	* @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	445	* @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	446	* AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	447	* AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	448	* AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	449	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	450	* AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	451	* AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	452	* AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	453	* AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	454	* AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	455	* AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	456	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	457	* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
AnnaBridge	172:65be27845400	458	* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
AnnaBridge	172:65be27845400	459	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
AnnaBridge	172:65be27845400	460	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
AnnaBridge	172:65be27845400	461	* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
AnnaBridge	172:65be27845400	462	* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
AnnaBridge	172:65be27845400	463	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
AnnaBridge	172:65be27845400	464	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
AnnaBridge	172:65be27845400	465	* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
AnnaBridge	172:65be27845400	466	* @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
AnnaBridge	172:65be27845400	467	* @retval None
AnnaBridge	172:65be27845400	468	*/
AnnaBridge	172:65be27845400	469	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	470	{
AnnaBridge	172:65be27845400	471	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	472	SET_BIT(RCC->AHB3LPENR, Periphs);
AnnaBridge	172:65be27845400	473	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	474	tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
AnnaBridge	172:65be27845400	475	(void)tmpreg;
AnnaBridge	172:65be27845400	476	}
AnnaBridge	172:65be27845400	477
AnnaBridge	172:65be27845400	478	/**
AnnaBridge	172:65be27845400	479	* @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	480	* @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	481	* AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	482	* AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	483	* AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	484	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	485	* AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	486	* AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	487	* AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	488	* AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	489	* AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	490	* AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	491	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	492	* @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D
AnnaBridge	172:65be27845400	493	* @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC
AnnaBridge	172:65be27845400	494	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
AnnaBridge	172:65be27845400	495	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
AnnaBridge	172:65be27845400	496	* @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1
AnnaBridge	172:65be27845400	497	* @arg @ref LL_AHB3_GRP1_PERIPH_FLASH
AnnaBridge	172:65be27845400	498	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1
AnnaBridge	172:65be27845400	499	* @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2
AnnaBridge	172:65be27845400	500	* @arg @ref LL_AHB3_GRP1_PERIPH_ITCM
AnnaBridge	172:65be27845400	501	* @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM
AnnaBridge	172:65be27845400	502	* @retval None
AnnaBridge	172:65be27845400	503	*/
AnnaBridge	172:65be27845400	504	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	505	{
AnnaBridge	172:65be27845400	506	CLEAR_BIT(RCC->AHB3LPENR, Periphs);
AnnaBridge	172:65be27845400	507	}
AnnaBridge	172:65be27845400	508
AnnaBridge	172:65be27845400	509	/**
AnnaBridge	172:65be27845400	510	* @}
AnnaBridge	172:65be27845400	511	*/
AnnaBridge	172:65be27845400	512
AnnaBridge	172:65be27845400	513	/** @defgroup BUS_LL_EF_AHB1 AHB1
AnnaBridge	172:65be27845400	514	* @{
AnnaBridge	172:65be27845400	515	*/
AnnaBridge	172:65be27845400	516
AnnaBridge	172:65be27845400	517	/**
AnnaBridge	172:65be27845400	518	* @brief Enable AHB1 peripherals clock.
AnnaBridge	172:65be27845400	519	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	520	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	521	* AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	522	* AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	523	* AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	524	* AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	525	* AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	526	* AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	527	* AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	528	* AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	529	* AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock
AnnaBridge	172:65be27845400	530	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	531	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	172:65be27845400	532	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	172:65be27845400	533	* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
AnnaBridge	172:65be27845400	534	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
AnnaBridge	172:65be27845400	535	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
AnnaBridge	172:65be27845400	536	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
AnnaBridge	172:65be27845400	537	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
AnnaBridge	172:65be27845400	538	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
AnnaBridge	172:65be27845400	539	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
AnnaBridge	172:65be27845400	540	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
AnnaBridge	172:65be27845400	541	* @retval None
AnnaBridge	172:65be27845400	542	*/
AnnaBridge	172:65be27845400	543	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	544	{
AnnaBridge	172:65be27845400	545	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	546	SET_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	172:65be27845400	547	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	548	tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	172:65be27845400	549	(void)tmpreg;
AnnaBridge	172:65be27845400	550	}
AnnaBridge	172:65be27845400	551
AnnaBridge	172:65be27845400	552	/**
AnnaBridge	172:65be27845400	553	* @brief Check if AHB1 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	554	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	555	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	556	* AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	557	* AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	558	* AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	559	* AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	560	* AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	561	* AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	562	* AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	563	* AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	564	* AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	565	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	566	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	172:65be27845400	567	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	172:65be27845400	568	* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
AnnaBridge	172:65be27845400	569	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
AnnaBridge	172:65be27845400	570	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
AnnaBridge	172:65be27845400	571	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
AnnaBridge	172:65be27845400	572	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
AnnaBridge	172:65be27845400	573	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
AnnaBridge	172:65be27845400	574	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
AnnaBridge	172:65be27845400	575	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
AnnaBridge	172:65be27845400	576	* @retval uint32_t
AnnaBridge	172:65be27845400	577	*/
AnnaBridge	172:65be27845400	578	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	579	{
AnnaBridge	172:65be27845400	580	return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	581	}
AnnaBridge	172:65be27845400	582
AnnaBridge	172:65be27845400	583	/**
AnnaBridge	172:65be27845400	584	* @brief Disable AHB1 peripherals clock.
AnnaBridge	172:65be27845400	585	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	586	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	587	* AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	588	* AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	589	* AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	590	* AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	591	* AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	592	* AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	593	* AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	594	* AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	595	* AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock
AnnaBridge	172:65be27845400	596	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	597	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	172:65be27845400	598	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	172:65be27845400	599	* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
AnnaBridge	172:65be27845400	600	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
AnnaBridge	172:65be27845400	601	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
AnnaBridge	172:65be27845400	602	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
AnnaBridge	172:65be27845400	603	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
AnnaBridge	172:65be27845400	604	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
AnnaBridge	172:65be27845400	605	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
AnnaBridge	172:65be27845400	606	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
AnnaBridge	172:65be27845400	607	* @retval None
AnnaBridge	172:65be27845400	608	*/
AnnaBridge	172:65be27845400	609	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	610	{
AnnaBridge	172:65be27845400	611	CLEAR_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	172:65be27845400	612	}
AnnaBridge	172:65be27845400	613
AnnaBridge	172:65be27845400	614	/**
AnnaBridge	172:65be27845400	615	* @brief Force AHB1 peripherals reset.
AnnaBridge	172:65be27845400	616	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	617	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	618	* AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	619	* AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	620	* AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	621	* AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	622	* AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset
AnnaBridge	172:65be27845400	623	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	624	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	172:65be27845400	625	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	172:65be27845400	626	* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
AnnaBridge	172:65be27845400	627	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
AnnaBridge	172:65be27845400	628	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
AnnaBridge	172:65be27845400	629	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
AnnaBridge	172:65be27845400	630	* @retval None
AnnaBridge	172:65be27845400	631	*/
AnnaBridge	172:65be27845400	632	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	633	{
AnnaBridge	172:65be27845400	634	SET_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	172:65be27845400	635	}
AnnaBridge	172:65be27845400	636
AnnaBridge	172:65be27845400	637	/**
AnnaBridge	172:65be27845400	638	* @brief Release AHB1 peripherals reset.
AnnaBridge	172:65be27845400	639	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	640	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	641	* AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	642	* AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	643	* AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	644	* AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	645	* AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset
AnnaBridge	172:65be27845400	646	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	647	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	172:65be27845400	648	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	172:65be27845400	649	* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
AnnaBridge	172:65be27845400	650	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
AnnaBridge	172:65be27845400	651	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
AnnaBridge	172:65be27845400	652	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
AnnaBridge	172:65be27845400	653	* @retval None
AnnaBridge	172:65be27845400	654	*/
AnnaBridge	172:65be27845400	655	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	656	{
AnnaBridge	172:65be27845400	657	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	172:65be27845400	658	}
AnnaBridge	172:65be27845400	659
AnnaBridge	172:65be27845400	660	/**
AnnaBridge	172:65be27845400	661	* @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	662	* @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	663	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	664	* AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	665	* AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	666	* AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	667	* AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	668	* AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	669	* AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	670	* AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	671	* AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	672	* AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	673	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	674	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	172:65be27845400	675	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	172:65be27845400	676	* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
AnnaBridge	172:65be27845400	677	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
AnnaBridge	172:65be27845400	678	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
AnnaBridge	172:65be27845400	679	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
AnnaBridge	172:65be27845400	680	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
AnnaBridge	172:65be27845400	681	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
AnnaBridge	172:65be27845400	682	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
AnnaBridge	172:65be27845400	683	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
AnnaBridge	172:65be27845400	684	* @retval None
AnnaBridge	172:65be27845400	685	*/
AnnaBridge	172:65be27845400	686	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	687	{
AnnaBridge	172:65be27845400	688	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	689	SET_BIT(RCC->AHB1LPENR, Periphs);
AnnaBridge	172:65be27845400	690	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	691	tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
AnnaBridge	172:65be27845400	692	(void)tmpreg;
AnnaBridge	172:65be27845400	693	}
AnnaBridge	172:65be27845400	694
AnnaBridge	172:65be27845400	695	/**
AnnaBridge	172:65be27845400	696	* @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	697	* @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	698	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	699	* AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	700	* AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	701	* AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	702	* AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	703	* AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	704	* AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	705	* AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	706	* AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	707	* AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	708	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	709	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	172:65be27845400	710	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	172:65be27845400	711	* @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
AnnaBridge	172:65be27845400	712	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC
AnnaBridge	172:65be27845400	713	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX
AnnaBridge	172:65be27845400	714	* @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX
AnnaBridge	172:65be27845400	715	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS
AnnaBridge	172:65be27845400	716	* @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI
AnnaBridge	172:65be27845400	717	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS
AnnaBridge	172:65be27845400	718	* @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI
AnnaBridge	172:65be27845400	719	* @retval None
AnnaBridge	172:65be27845400	720	*/
AnnaBridge	172:65be27845400	721	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	722	{
AnnaBridge	172:65be27845400	723	CLEAR_BIT(RCC->AHB1LPENR, Periphs);
AnnaBridge	172:65be27845400	724	}
AnnaBridge	172:65be27845400	725
AnnaBridge	172:65be27845400	726	/**
AnnaBridge	172:65be27845400	727	* @}
AnnaBridge	172:65be27845400	728	*/
AnnaBridge	172:65be27845400	729
AnnaBridge	172:65be27845400	730	/** @defgroup BUS_LL_EF_AHB2 AHB2
AnnaBridge	172:65be27845400	731	* @{
AnnaBridge	172:65be27845400	732	*/
AnnaBridge	172:65be27845400	733
AnnaBridge	172:65be27845400	734	/**
AnnaBridge	172:65be27845400	735	* @brief Enable AHB2 peripherals clock.
AnnaBridge	172:65be27845400	736	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	737	* AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	738	* AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	739	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	740	* AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	741	* AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	742	* AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	743	* AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock
AnnaBridge	172:65be27845400	744	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	745	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
AnnaBridge	172:65be27845400	746	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	172:65be27845400	747	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	172:65be27845400	748	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	172:65be27845400	749	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
AnnaBridge	172:65be27845400	750	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
AnnaBridge	172:65be27845400	751	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
AnnaBridge	172:65be27845400	752	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
AnnaBridge	172:65be27845400	753	*
AnnaBridge	172:65be27845400	754	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	755	* @retval None
AnnaBridge	172:65be27845400	756	*/
AnnaBridge	172:65be27845400	757	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	758	{
AnnaBridge	172:65be27845400	759	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	760	SET_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	172:65be27845400	761	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	762	tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	172:65be27845400	763	(void)tmpreg;
AnnaBridge	172:65be27845400	764	}
AnnaBridge	172:65be27845400	765
AnnaBridge	172:65be27845400	766	/**
AnnaBridge	172:65be27845400	767	* @brief Check if AHB2 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	768	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	769	* AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	770	* AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	771	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	772	* AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	773	* AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	774	* AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	775	* AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	776	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	777	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
AnnaBridge	172:65be27845400	778	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	172:65be27845400	779	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	172:65be27845400	780	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	172:65be27845400	781	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
AnnaBridge	172:65be27845400	782	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
AnnaBridge	172:65be27845400	783	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
AnnaBridge	172:65be27845400	784	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
AnnaBridge	172:65be27845400	785	*
AnnaBridge	172:65be27845400	786	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	787	* @retval uint32_t
AnnaBridge	172:65be27845400	788	*/
AnnaBridge	172:65be27845400	789	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	790	{
AnnaBridge	172:65be27845400	791	return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	792	}
AnnaBridge	172:65be27845400	793
AnnaBridge	172:65be27845400	794	/**
AnnaBridge	172:65be27845400	795	* @brief Disable AHB2 peripherals clock.
AnnaBridge	172:65be27845400	796	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	797	* AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	798	* AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	799	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	800	* AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	801	* AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	802	* AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	803	* AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock
AnnaBridge	172:65be27845400	804	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	805	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
AnnaBridge	172:65be27845400	806	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	172:65be27845400	807	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	172:65be27845400	808	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	172:65be27845400	809	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
AnnaBridge	172:65be27845400	810	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
AnnaBridge	172:65be27845400	811	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
AnnaBridge	172:65be27845400	812	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
AnnaBridge	172:65be27845400	813	*
AnnaBridge	172:65be27845400	814	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	815	* @retval None
AnnaBridge	172:65be27845400	816	*/
AnnaBridge	172:65be27845400	817	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	818	{
AnnaBridge	172:65be27845400	819	CLEAR_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	172:65be27845400	820	}
AnnaBridge	172:65be27845400	821
AnnaBridge	172:65be27845400	822	/**
AnnaBridge	172:65be27845400	823	* @brief Force AHB2 peripherals reset.
AnnaBridge	172:65be27845400	824	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	825	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	826	* AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	827	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	828	* AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset
AnnaBridge	172:65be27845400	829	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	830	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
AnnaBridge	172:65be27845400	831	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	172:65be27845400	832	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	172:65be27845400	833	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	172:65be27845400	834	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
AnnaBridge	172:65be27845400	835	*
AnnaBridge	172:65be27845400	836	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	837	* @retval None
AnnaBridge	172:65be27845400	838	*/
AnnaBridge	172:65be27845400	839	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	840	{
AnnaBridge	172:65be27845400	841	SET_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	172:65be27845400	842	}
AnnaBridge	172:65be27845400	843
AnnaBridge	172:65be27845400	844	/**
AnnaBridge	172:65be27845400	845	* @brief Release AHB2 peripherals reset.
AnnaBridge	172:65be27845400	846	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	847	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	848	* AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	849	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	850	* AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset
AnnaBridge	172:65be27845400	851	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	852	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
AnnaBridge	172:65be27845400	853	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	172:65be27845400	854	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	172:65be27845400	855	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	172:65be27845400	856	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
AnnaBridge	172:65be27845400	857	*
AnnaBridge	172:65be27845400	858	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	859	* @retval None
AnnaBridge	172:65be27845400	860	*/
AnnaBridge	172:65be27845400	861	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	862	{
AnnaBridge	172:65be27845400	863	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	172:65be27845400	864	}
AnnaBridge	172:65be27845400	865
AnnaBridge	172:65be27845400	866	/**
AnnaBridge	172:65be27845400	867	* @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	868	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	869	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	870	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	871	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	872	* AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	873	* AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	874	* AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	875	* AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	876	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	877	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
AnnaBridge	172:65be27845400	878	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	172:65be27845400	879	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	172:65be27845400	880	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	172:65be27845400	881	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
AnnaBridge	172:65be27845400	882	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
AnnaBridge	172:65be27845400	883	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
AnnaBridge	172:65be27845400	884	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
AnnaBridge	172:65be27845400	885	*
AnnaBridge	172:65be27845400	886	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	887	* @retval None
AnnaBridge	172:65be27845400	888	*/
AnnaBridge	172:65be27845400	889	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	890	{
AnnaBridge	172:65be27845400	891	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	892	SET_BIT(RCC->AHB2LPENR, Periphs);
AnnaBridge	172:65be27845400	893	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	894	tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
AnnaBridge	172:65be27845400	895	(void)tmpreg;
AnnaBridge	172:65be27845400	896	}
AnnaBridge	172:65be27845400	897
AnnaBridge	172:65be27845400	898	/**
AnnaBridge	172:65be27845400	899	* @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	900	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	901	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	902	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	903	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	904	* AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	905	* AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	906	* AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	907	* AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	908	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	909	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
AnnaBridge	172:65be27845400	910	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
AnnaBridge	172:65be27845400	911	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	172:65be27845400	912	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	172:65be27845400	913	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
AnnaBridge	172:65be27845400	914	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1
AnnaBridge	172:65be27845400	915	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2
AnnaBridge	172:65be27845400	916	* @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3
AnnaBridge	172:65be27845400	917	*
AnnaBridge	172:65be27845400	918	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	919	* @retval None
AnnaBridge	172:65be27845400	920	*/
AnnaBridge	172:65be27845400	921	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	922	{
AnnaBridge	172:65be27845400	923	CLEAR_BIT(RCC->AHB2LPENR, Periphs);
AnnaBridge	172:65be27845400	924	}
AnnaBridge	172:65be27845400	925
AnnaBridge	172:65be27845400	926	/**
AnnaBridge	172:65be27845400	927	* @}
AnnaBridge	172:65be27845400	928	*/
AnnaBridge	172:65be27845400	929
AnnaBridge	172:65be27845400	930	/** @defgroup BUS_LL_EF_AHB4 AHB4
AnnaBridge	172:65be27845400	931	* @{
AnnaBridge	172:65be27845400	932	*/
AnnaBridge	172:65be27845400	933
AnnaBridge	172:65be27845400	934	/**
AnnaBridge	172:65be27845400	935	* @brief Enable AHB4 peripherals clock.
AnnaBridge	172:65be27845400	936	* @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	937	* AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	938	* AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	939	* AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	940	* AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	941	* AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	942	* AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	943	* AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	944	* AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	945	* AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	946	* AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	947	* AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	948	* AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	949	* AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	950	* AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	951	* AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	952	* AHB4ENR D3SRAM1EN LL_AHB4_GRP1_EnableClock
AnnaBridge	172:65be27845400	953	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	954	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
AnnaBridge	172:65be27845400	955	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
AnnaBridge	172:65be27845400	956	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
AnnaBridge	172:65be27845400	957	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
AnnaBridge	172:65be27845400	958	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
AnnaBridge	172:65be27845400	959	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
AnnaBridge	172:65be27845400	960	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
AnnaBridge	172:65be27845400	961	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
AnnaBridge	172:65be27845400	962	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
AnnaBridge	172:65be27845400	963	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
AnnaBridge	172:65be27845400	964	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
AnnaBridge	172:65be27845400	965	* @arg @ref LL_AHB4_GRP1_PERIPH_CRC
AnnaBridge	172:65be27845400	966	* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
AnnaBridge	172:65be27845400	967	* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
AnnaBridge	172:65be27845400	968	* @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
AnnaBridge	172:65be27845400	969	* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
AnnaBridge	172:65be27845400	970	* @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1
AnnaBridge	172:65be27845400	971	*
AnnaBridge	172:65be27845400	972	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	973	* @retval None
AnnaBridge	172:65be27845400	974	*/
AnnaBridge	172:65be27845400	975	__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	976	{
AnnaBridge	172:65be27845400	977	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	978	SET_BIT(RCC->AHB4ENR, Periphs);
AnnaBridge	172:65be27845400	979	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	980	tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);
AnnaBridge	172:65be27845400	981	(void)tmpreg;
AnnaBridge	172:65be27845400	982	}
AnnaBridge	172:65be27845400	983
AnnaBridge	172:65be27845400	984	/**
AnnaBridge	172:65be27845400	985	* @brief Check if AHB4 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	986	* @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	987	* AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	988	* AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	989	* AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	990	* AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	991	* AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	992	* AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	993	* AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	994	* AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	995	* AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	996	* AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	997	* AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	998	* AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	999	* AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1000	* AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1001	* AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1002	* AHB4ENR D3SRAM1EN LL_AHB4_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	1003	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1004	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
AnnaBridge	172:65be27845400	1005	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
AnnaBridge	172:65be27845400	1006	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
AnnaBridge	172:65be27845400	1007	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
AnnaBridge	172:65be27845400	1008	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
AnnaBridge	172:65be27845400	1009	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
AnnaBridge	172:65be27845400	1010	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
AnnaBridge	172:65be27845400	1011	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
AnnaBridge	172:65be27845400	1012	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
AnnaBridge	172:65be27845400	1013	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
AnnaBridge	172:65be27845400	1014	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
AnnaBridge	172:65be27845400	1015	* @arg @ref LL_AHB4_GRP1_PERIPH_CRC
AnnaBridge	172:65be27845400	1016	* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
AnnaBridge	172:65be27845400	1017	* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
AnnaBridge	172:65be27845400	1018	* @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
AnnaBridge	172:65be27845400	1019	* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
AnnaBridge	172:65be27845400	1020	* @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1
AnnaBridge	172:65be27845400	1021	*
AnnaBridge	172:65be27845400	1022	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1023	* @retval uint32_t
AnnaBridge	172:65be27845400	1024	*/
AnnaBridge	172:65be27845400	1025	__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1026	{
AnnaBridge	172:65be27845400	1027	return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	1028	}
AnnaBridge	172:65be27845400	1029
AnnaBridge	172:65be27845400	1030	/**
AnnaBridge	172:65be27845400	1031	* @brief Disable AHB4 peripherals clock.
AnnaBridge	172:65be27845400	1032	* @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1033	* AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1034	* AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1035	* AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1036	* AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1037	* AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1038	* AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1039	* AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1040	* AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1041	* AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1042	* AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1043	* AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1044	* AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1045	* AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1046	* AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1047	* AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1048	* AHB4ENR D3SRAM1EN LL_AHB4_GRP1_DisableClock
AnnaBridge	172:65be27845400	1049	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1050	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
AnnaBridge	172:65be27845400	1051	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
AnnaBridge	172:65be27845400	1052	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
AnnaBridge	172:65be27845400	1053	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
AnnaBridge	172:65be27845400	1054	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
AnnaBridge	172:65be27845400	1055	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
AnnaBridge	172:65be27845400	1056	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
AnnaBridge	172:65be27845400	1057	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
AnnaBridge	172:65be27845400	1058	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
AnnaBridge	172:65be27845400	1059	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
AnnaBridge	172:65be27845400	1060	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
AnnaBridge	172:65be27845400	1061	* @arg @ref LL_AHB4_GRP1_PERIPH_CRC
AnnaBridge	172:65be27845400	1062	* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
AnnaBridge	172:65be27845400	1063	* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
AnnaBridge	172:65be27845400	1064	* @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
AnnaBridge	172:65be27845400	1065	* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
AnnaBridge	172:65be27845400	1066	* @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1
AnnaBridge	172:65be27845400	1067	*
AnnaBridge	172:65be27845400	1068	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1069	* @retval None
AnnaBridge	172:65be27845400	1070	*/
AnnaBridge	172:65be27845400	1071	__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1072	{
AnnaBridge	172:65be27845400	1073	CLEAR_BIT(RCC->AHB4ENR, Periphs);
AnnaBridge	172:65be27845400	1074	}
AnnaBridge	172:65be27845400	1075
AnnaBridge	172:65be27845400	1076	/**
AnnaBridge	172:65be27845400	1077	* @brief Force AHB4 peripherals reset.
AnnaBridge	172:65be27845400	1078	* @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1079	* AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1080	* AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1081	* AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1082	* AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1083	* AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1084	* AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1085	* AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1086	* AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1087	* AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1088	* AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1089	* AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1090	* AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1091	* AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1092	* AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset
AnnaBridge	172:65be27845400	1093	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1094	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
AnnaBridge	172:65be27845400	1095	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
AnnaBridge	172:65be27845400	1096	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
AnnaBridge	172:65be27845400	1097	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
AnnaBridge	172:65be27845400	1098	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
AnnaBridge	172:65be27845400	1099	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
AnnaBridge	172:65be27845400	1100	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
AnnaBridge	172:65be27845400	1101	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
AnnaBridge	172:65be27845400	1102	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
AnnaBridge	172:65be27845400	1103	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
AnnaBridge	172:65be27845400	1104	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
AnnaBridge	172:65be27845400	1105	* @arg @ref LL_AHB4_GRP1_PERIPH_CRC
AnnaBridge	172:65be27845400	1106	* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
AnnaBridge	172:65be27845400	1107	* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
AnnaBridge	172:65be27845400	1108	* @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
AnnaBridge	172:65be27845400	1109	*
AnnaBridge	172:65be27845400	1110	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1111	* @retval None
AnnaBridge	172:65be27845400	1112	*/
AnnaBridge	172:65be27845400	1113	__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1114	{
AnnaBridge	172:65be27845400	1115	SET_BIT(RCC->AHB4RSTR, Periphs);
AnnaBridge	172:65be27845400	1116	}
AnnaBridge	172:65be27845400	1117
AnnaBridge	172:65be27845400	1118	/**
AnnaBridge	172:65be27845400	1119	* @brief Release AHB4 peripherals reset.
AnnaBridge	172:65be27845400	1120	* @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1121	* AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1122	* AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1123	* AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1124	* AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1125	* AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1126	* AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1127	* AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1128	* AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1129	* AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1130	* AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1131	* AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1132	* AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1133	* AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1134	* AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset
AnnaBridge	172:65be27845400	1135	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1136	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
AnnaBridge	172:65be27845400	1137	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
AnnaBridge	172:65be27845400	1138	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
AnnaBridge	172:65be27845400	1139	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
AnnaBridge	172:65be27845400	1140	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
AnnaBridge	172:65be27845400	1141	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
AnnaBridge	172:65be27845400	1142	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
AnnaBridge	172:65be27845400	1143	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
AnnaBridge	172:65be27845400	1144	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
AnnaBridge	172:65be27845400	1145	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
AnnaBridge	172:65be27845400	1146	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
AnnaBridge	172:65be27845400	1147	* @arg @ref LL_AHB4_GRP1_PERIPH_CRC
AnnaBridge	172:65be27845400	1148	* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
AnnaBridge	172:65be27845400	1149	* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
AnnaBridge	172:65be27845400	1150	* @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)
AnnaBridge	172:65be27845400	1151	*
AnnaBridge	172:65be27845400	1152	* (*) value not defined in all devices.
AnnaBridge	172:65be27845400	1153	* @retval None
AnnaBridge	172:65be27845400	1154	*/
AnnaBridge	172:65be27845400	1155	__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1156	{
AnnaBridge	172:65be27845400	1157	CLEAR_BIT(RCC->AHB4RSTR, Periphs);
AnnaBridge	172:65be27845400	1158	}
AnnaBridge	172:65be27845400	1159
AnnaBridge	172:65be27845400	1160	/**
AnnaBridge	172:65be27845400	1161	* @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1162	* @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1163	* AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1164	* AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1165	* AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1166	* AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1167	* AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1168	* AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1169	* AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1170	* AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1171	* AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1172	* AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1173	* AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1174	* AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1175	* AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1176	* AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1177	* AHB4LPENR D3SRAM1LPEN LL_AHB4_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	1178	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1179	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
AnnaBridge	172:65be27845400	1180	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
AnnaBridge	172:65be27845400	1181	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
AnnaBridge	172:65be27845400	1182	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
AnnaBridge	172:65be27845400	1183	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
AnnaBridge	172:65be27845400	1184	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
AnnaBridge	172:65be27845400	1185	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
AnnaBridge	172:65be27845400	1186	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
AnnaBridge	172:65be27845400	1187	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
AnnaBridge	172:65be27845400	1188	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
AnnaBridge	172:65be27845400	1189	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
AnnaBridge	172:65be27845400	1190	* @arg @ref LL_AHB4_GRP1_PERIPH_CRC
AnnaBridge	172:65be27845400	1191	* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
AnnaBridge	172:65be27845400	1192	* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
AnnaBridge	172:65be27845400	1193	* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
AnnaBridge	172:65be27845400	1194	* @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1
AnnaBridge	172:65be27845400	1195	* @retval None
AnnaBridge	172:65be27845400	1196	*/
AnnaBridge	172:65be27845400	1197	__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1198	{
AnnaBridge	172:65be27845400	1199	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1200	SET_BIT(RCC->AHB4LPENR, Periphs);
AnnaBridge	172:65be27845400	1201	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1202	tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);
AnnaBridge	172:65be27845400	1203	(void)tmpreg;
AnnaBridge	172:65be27845400	1204	}
AnnaBridge	172:65be27845400	1205
AnnaBridge	172:65be27845400	1206	/**
AnnaBridge	172:65be27845400	1207	* @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1208	* @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1209	* AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1210	* AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1211	* AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1212	* AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1213	* AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1214	* AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1215	* AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1216	* AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1217	* AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1218	* AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1219	* AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1220	* AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1221	* AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1222	* AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1223	* AHB4LPENR D3SRAM1LPEN LL_AHB4_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	1224	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1225	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA
AnnaBridge	172:65be27845400	1226	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB
AnnaBridge	172:65be27845400	1227	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC
AnnaBridge	172:65be27845400	1228	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD
AnnaBridge	172:65be27845400	1229	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE
AnnaBridge	172:65be27845400	1230	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF
AnnaBridge	172:65be27845400	1231	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG
AnnaBridge	172:65be27845400	1232	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH
AnnaBridge	172:65be27845400	1233	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI
AnnaBridge	172:65be27845400	1234	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ
AnnaBridge	172:65be27845400	1235	* @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK
AnnaBridge	172:65be27845400	1236	* @arg @ref LL_AHB4_GRP1_PERIPH_CRC
AnnaBridge	172:65be27845400	1237	* @arg @ref LL_AHB4_GRP1_PERIPH_BDMA
AnnaBridge	172:65be27845400	1238	* @arg @ref LL_AHB4_GRP1_PERIPH_ADC3
AnnaBridge	172:65be27845400	1239	* @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM
AnnaBridge	172:65be27845400	1240	* @arg @ref LL_AHB4_GRP1_PERIPH_D3SRAM1
AnnaBridge	172:65be27845400	1241	* @retval None
AnnaBridge	172:65be27845400	1242	*/
AnnaBridge	172:65be27845400	1243	__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1244	{
AnnaBridge	172:65be27845400	1245	CLEAR_BIT(RCC->AHB4LPENR, Periphs);
AnnaBridge	172:65be27845400	1246	}
AnnaBridge	172:65be27845400	1247
AnnaBridge	172:65be27845400	1248	/**
AnnaBridge	172:65be27845400	1249	* @}
AnnaBridge	172:65be27845400	1250	*/
AnnaBridge	172:65be27845400	1251
AnnaBridge	172:65be27845400	1252	/** @defgroup BUS_LL_EF_APB3 APB3
AnnaBridge	172:65be27845400	1253	* @{
AnnaBridge	172:65be27845400	1254	*/
AnnaBridge	172:65be27845400	1255
AnnaBridge	172:65be27845400	1256	/**
AnnaBridge	172:65be27845400	1257	* @brief Enable APB3 peripherals clock.
AnnaBridge	172:65be27845400	1258	* @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1259	* APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock
AnnaBridge	172:65be27845400	1260	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1261	* @arg @ref LL_APB3_GRP1_PERIPH_LTDC
AnnaBridge	172:65be27845400	1262	* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
AnnaBridge	172:65be27845400	1263	* @retval None
AnnaBridge	172:65be27845400	1264	*/
AnnaBridge	172:65be27845400	1265	__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1266	{
AnnaBridge	172:65be27845400	1267	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1268	SET_BIT(RCC->APB3ENR, Periphs);
AnnaBridge	172:65be27845400	1269	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1270	tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
AnnaBridge	172:65be27845400	1271	(void)tmpreg;
AnnaBridge	172:65be27845400	1272	}
AnnaBridge	172:65be27845400	1273
AnnaBridge	172:65be27845400	1274	/**
AnnaBridge	172:65be27845400	1275	* @brief Check if APB3 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	1276	* @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1277	* APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	1278	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1279	* @arg @ref LL_APB3_GRP1_PERIPH_LTDC
AnnaBridge	172:65be27845400	1280	* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
AnnaBridge	172:65be27845400	1281	* @retval uint32_t
AnnaBridge	172:65be27845400	1282	*/
AnnaBridge	172:65be27845400	1283	__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1284	{
AnnaBridge	172:65be27845400	1285	return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	1286	}
AnnaBridge	172:65be27845400	1287
AnnaBridge	172:65be27845400	1288	/**
AnnaBridge	172:65be27845400	1289	* @brief Disable APB3 peripherals clock.
AnnaBridge	172:65be27845400	1290	* @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1291	* APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock
AnnaBridge	172:65be27845400	1292	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1293	* @arg @ref LL_APB3_GRP1_PERIPH_LTDC
AnnaBridge	172:65be27845400	1294	* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
AnnaBridge	172:65be27845400	1295	* @retval None
AnnaBridge	172:65be27845400	1296	*/
AnnaBridge	172:65be27845400	1297	__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1298	{
AnnaBridge	172:65be27845400	1299	CLEAR_BIT(RCC->APB3ENR, Periphs);
AnnaBridge	172:65be27845400	1300	}
AnnaBridge	172:65be27845400	1301
AnnaBridge	172:65be27845400	1302	/**
AnnaBridge	172:65be27845400	1303	* @brief Force APB3 peripherals reset.
AnnaBridge	172:65be27845400	1304	* @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1305	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1306	* @arg @ref LL_APB3_GRP1_PERIPH_LTDC
AnnaBridge	172:65be27845400	1307	* @retval None
AnnaBridge	172:65be27845400	1308	*/
AnnaBridge	172:65be27845400	1309	__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1310	{
AnnaBridge	172:65be27845400	1311	SET_BIT(RCC->APB3RSTR, Periphs);
AnnaBridge	172:65be27845400	1312	}
AnnaBridge	172:65be27845400	1313
AnnaBridge	172:65be27845400	1314	/**
AnnaBridge	172:65be27845400	1315	* @brief Release APB3 peripherals reset.
AnnaBridge	172:65be27845400	1316	* @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1317	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1318	* @arg @ref LL_APB3_GRP1_PERIPH_LTDC
AnnaBridge	172:65be27845400	1319	* @retval None
AnnaBridge	172:65be27845400	1320	*/
AnnaBridge	172:65be27845400	1321	__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1322	{
AnnaBridge	172:65be27845400	1323	CLEAR_BIT(RCC->APB3RSTR, Periphs);
AnnaBridge	172:65be27845400	1324	}
AnnaBridge	172:65be27845400	1325
AnnaBridge	172:65be27845400	1326	/**
AnnaBridge	172:65be27845400	1327	* @brief Enable APB3 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1328	* @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1329	* APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	1330	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1331	* @arg @ref LL_APB3_GRP1_PERIPH_LTDC
AnnaBridge	172:65be27845400	1332	* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
AnnaBridge	172:65be27845400	1333	* @retval None
AnnaBridge	172:65be27845400	1334	*/
AnnaBridge	172:65be27845400	1335	__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1336	{
AnnaBridge	172:65be27845400	1337	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1338	SET_BIT(RCC->APB3LPENR, Periphs);
AnnaBridge	172:65be27845400	1339	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1340	tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);
AnnaBridge	172:65be27845400	1341	(void)tmpreg;
AnnaBridge	172:65be27845400	1342	}
AnnaBridge	172:65be27845400	1343
AnnaBridge	172:65be27845400	1344	/**
AnnaBridge	172:65be27845400	1345	* @brief Disable APB3 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1346	* @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1347	* APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	1348	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1349	* @arg @ref LL_APB3_GRP1_PERIPH_LTDC
AnnaBridge	172:65be27845400	1350	* @arg @ref LL_APB3_GRP1_PERIPH_WWDG1
AnnaBridge	172:65be27845400	1351	* @retval None
AnnaBridge	172:65be27845400	1352	*/
AnnaBridge	172:65be27845400	1353	__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1354	{
AnnaBridge	172:65be27845400	1355	CLEAR_BIT(RCC->APB3LPENR, Periphs);
AnnaBridge	172:65be27845400	1356	}
AnnaBridge	172:65be27845400	1357
AnnaBridge	172:65be27845400	1358	/**
AnnaBridge	172:65be27845400	1359	* @}
AnnaBridge	172:65be27845400	1360	*/
AnnaBridge	172:65be27845400	1361
AnnaBridge	172:65be27845400	1362	/** @defgroup BUS_LL_EF_APB1 APB1
AnnaBridge	172:65be27845400	1363	* @{
AnnaBridge	172:65be27845400	1364	*/
AnnaBridge	172:65be27845400	1365
AnnaBridge	172:65be27845400	1366	/**
AnnaBridge	172:65be27845400	1367	* @brief Enable APB1 peripherals clock.
AnnaBridge	172:65be27845400	1368	* @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1369	* APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1370	* APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1371	* APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1372	* APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1373	* APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1374	* APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1375	* APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1376	* APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1377	* APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1378	* APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1379	* APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1380	* APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1381	* APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1382	* APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1383	* APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1384	* APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1385	* APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1386	* APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1387	* APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1388	* APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1389	* APB1LENR CECEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1390	* APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1391	* APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1392	* APB1LENR UART8EN LL_APB1_GRP1_EnableClock
AnnaBridge	172:65be27845400	1393	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1394	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	172:65be27845400	1395	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
AnnaBridge	172:65be27845400	1396	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
AnnaBridge	172:65be27845400	1397	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	172:65be27845400	1398	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	172:65be27845400	1399	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	172:65be27845400	1400	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
AnnaBridge	172:65be27845400	1401	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
AnnaBridge	172:65be27845400	1402	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
AnnaBridge	172:65be27845400	1403	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	172:65be27845400	1404	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
AnnaBridge	172:65be27845400	1405	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	172:65be27845400	1406	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
AnnaBridge	172:65be27845400	1407	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	172:65be27845400	1408	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
AnnaBridge	172:65be27845400	1409	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
AnnaBridge	172:65be27845400	1410	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
AnnaBridge	172:65be27845400	1411	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	172:65be27845400	1412	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	172:65be27845400	1413	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	172:65be27845400	1414	* @arg @ref LL_APB1_GRP1_PERIPH_CEC
AnnaBridge	172:65be27845400	1415	* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
AnnaBridge	172:65be27845400	1416	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
AnnaBridge	172:65be27845400	1417	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
AnnaBridge	172:65be27845400	1418	* @retval None
AnnaBridge	172:65be27845400	1419	*/
AnnaBridge	172:65be27845400	1420	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1421	{
AnnaBridge	172:65be27845400	1422	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1423	SET_BIT(RCC->APB1LENR, Periphs);
AnnaBridge	172:65be27845400	1424	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1425	tmpreg = READ_BIT(RCC->APB1LENR, Periphs);
AnnaBridge	172:65be27845400	1426	(void)tmpreg;
AnnaBridge	172:65be27845400	1427	}
AnnaBridge	172:65be27845400	1428
AnnaBridge	172:65be27845400	1429	/**
AnnaBridge	172:65be27845400	1430	* @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	1431	* @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1432	* APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1433	* APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1434	* APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1435	* APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1436	* APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1437	* APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1438	* APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1439	* APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1440	* APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1441	* APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1442	* APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1443	* APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1444	* APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1445	* APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1446	* APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1447	* APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1448	* APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1449	* APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1450	* APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1451	* APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1452	* APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1453	* APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1454	* APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1455	* APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	1456	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1457	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	172:65be27845400	1458	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
AnnaBridge	172:65be27845400	1459	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
AnnaBridge	172:65be27845400	1460	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	172:65be27845400	1461	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	172:65be27845400	1462	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	172:65be27845400	1463	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
AnnaBridge	172:65be27845400	1464	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
AnnaBridge	172:65be27845400	1465	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
AnnaBridge	172:65be27845400	1466	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	172:65be27845400	1467	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
AnnaBridge	172:65be27845400	1468	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	172:65be27845400	1469	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
AnnaBridge	172:65be27845400	1470	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	172:65be27845400	1471	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
AnnaBridge	172:65be27845400	1472	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
AnnaBridge	172:65be27845400	1473	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
AnnaBridge	172:65be27845400	1474	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	172:65be27845400	1475	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	172:65be27845400	1476	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	172:65be27845400	1477	* @arg @ref LL_APB1_GRP1_PERIPH_CEC
AnnaBridge	172:65be27845400	1478	* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
AnnaBridge	172:65be27845400	1479	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
AnnaBridge	172:65be27845400	1480	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
AnnaBridge	172:65be27845400	1481	* @retval uint32_t
AnnaBridge	172:65be27845400	1482	*/
AnnaBridge	172:65be27845400	1483	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1484	{
AnnaBridge	172:65be27845400	1485	return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	1486	}
AnnaBridge	172:65be27845400	1487
AnnaBridge	172:65be27845400	1488	/**
AnnaBridge	172:65be27845400	1489	* @brief Disable APB1 peripherals clock.
AnnaBridge	172:65be27845400	1490	* @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1491	* APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1492	* APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1493	* APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1494	* APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1495	* APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1496	* APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1497	* APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1498	* APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1499	* APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1500	* APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1501	* APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1502	* APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1503	* APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1504	* APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1505	* APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1506	* APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1507	* APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1508	* APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1509	* APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1510	* APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1511	* APB1LENR CECEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1512	* APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1513	* APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	1514	* APB1LENR UART8EN LL_APB1_GRP1_DisableClock
AnnaBridge	172:65be27845400	1515	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1516	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	172:65be27845400	1517	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
AnnaBridge	172:65be27845400	1518	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
AnnaBridge	172:65be27845400	1519	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	172:65be27845400	1520	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	172:65be27845400	1521	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	172:65be27845400	1522	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
AnnaBridge	172:65be27845400	1523	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
AnnaBridge	172:65be27845400	1524	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
AnnaBridge	172:65be27845400	1525	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	172:65be27845400	1526	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
AnnaBridge	172:65be27845400	1527	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	172:65be27845400	1528	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
AnnaBridge	172:65be27845400	1529	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	172:65be27845400	1530	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
AnnaBridge	172:65be27845400	1531	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
AnnaBridge	172:65be27845400	1532	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
AnnaBridge	172:65be27845400	1533	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	172:65be27845400	1534	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	172:65be27845400	1535	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	172:65be27845400	1536	* @arg @ref LL_APB1_GRP1_PERIPH_CEC
AnnaBridge	172:65be27845400	1537	* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
AnnaBridge	172:65be27845400	1538	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
AnnaBridge	172:65be27845400	1539	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
AnnaBridge	172:65be27845400	1540	* @retval None
AnnaBridge	172:65be27845400	1541	*/
AnnaBridge	172:65be27845400	1542	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1543	{
AnnaBridge	172:65be27845400	1544	CLEAR_BIT(RCC->APB1LENR, Periphs);
AnnaBridge	172:65be27845400	1545	}
AnnaBridge	172:65be27845400	1546
AnnaBridge	172:65be27845400	1547	/**
AnnaBridge	172:65be27845400	1548	* @brief Force APB1 peripherals reset.
AnnaBridge	172:65be27845400	1549	* @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1550	* APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1551	* APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1552	* APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1553	* APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1554	* APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1555	* APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1556	* APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1557	* APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1558	* APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1559	* APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1560	* APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1561	* APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1562	* APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1563	* APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1564	* APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1565	* APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1566	* APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1567	* APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1568	* APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1569	* APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1570	* APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1571	* APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	1572	* APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset
AnnaBridge	172:65be27845400	1573	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1574	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	172:65be27845400	1575	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
AnnaBridge	172:65be27845400	1576	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
AnnaBridge	172:65be27845400	1577	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	172:65be27845400	1578	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	172:65be27845400	1579	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	172:65be27845400	1580	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
AnnaBridge	172:65be27845400	1581	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
AnnaBridge	172:65be27845400	1582	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
AnnaBridge	172:65be27845400	1583	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	172:65be27845400	1584	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
AnnaBridge	172:65be27845400	1585	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	172:65be27845400	1586	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
AnnaBridge	172:65be27845400	1587	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	172:65be27845400	1588	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
AnnaBridge	172:65be27845400	1589	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
AnnaBridge	172:65be27845400	1590	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
AnnaBridge	172:65be27845400	1591	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	172:65be27845400	1592	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	172:65be27845400	1593	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	172:65be27845400	1594	* @arg @ref LL_APB1_GRP1_PERIPH_CEC
AnnaBridge	172:65be27845400	1595	* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
AnnaBridge	172:65be27845400	1596	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
AnnaBridge	172:65be27845400	1597	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
AnnaBridge	172:65be27845400	1598	* @retval None
AnnaBridge	172:65be27845400	1599	*/
AnnaBridge	172:65be27845400	1600	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1601	{
AnnaBridge	172:65be27845400	1602	SET_BIT(RCC->APB1LRSTR, Periphs);
AnnaBridge	172:65be27845400	1603	}
AnnaBridge	172:65be27845400	1604
AnnaBridge	172:65be27845400	1605	/**
AnnaBridge	172:65be27845400	1606	* @brief Release APB1 peripherals reset.
AnnaBridge	172:65be27845400	1607	* @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1608	* APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1609	* APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1610	* APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1611	* APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1612	* APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1613	* APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1614	* APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1615	* APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1616	* APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1617	* APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1618	* APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1619	* APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1620	* APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1621	* APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1622	* APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1623	* APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1624	* APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1625	* APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1626	* APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1627	* APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1628	* APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1629	* APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	1630	* APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset
AnnaBridge	172:65be27845400	1631	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1632	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	172:65be27845400	1633	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
AnnaBridge	172:65be27845400	1634	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
AnnaBridge	172:65be27845400	1635	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	172:65be27845400	1636	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	172:65be27845400	1637	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	172:65be27845400	1638	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
AnnaBridge	172:65be27845400	1639	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
AnnaBridge	172:65be27845400	1640	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
AnnaBridge	172:65be27845400	1641	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	172:65be27845400	1642	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
AnnaBridge	172:65be27845400	1643	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	172:65be27845400	1644	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
AnnaBridge	172:65be27845400	1645	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	172:65be27845400	1646	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
AnnaBridge	172:65be27845400	1647	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
AnnaBridge	172:65be27845400	1648	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
AnnaBridge	172:65be27845400	1649	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	172:65be27845400	1650	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	172:65be27845400	1651	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	172:65be27845400	1652	* @arg @ref LL_APB1_GRP1_PERIPH_CEC
AnnaBridge	172:65be27845400	1653	* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
AnnaBridge	172:65be27845400	1654	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
AnnaBridge	172:65be27845400	1655	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
AnnaBridge	172:65be27845400	1656	* @retval None
AnnaBridge	172:65be27845400	1657	*/
AnnaBridge	172:65be27845400	1658	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1659	{
AnnaBridge	172:65be27845400	1660	CLEAR_BIT(RCC->APB1LRSTR, Periphs);
AnnaBridge	172:65be27845400	1661	}
AnnaBridge	172:65be27845400	1662
AnnaBridge	172:65be27845400	1663	/**
AnnaBridge	172:65be27845400	1664	* @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1665	* @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1666	* APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1667	* APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1668	* APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1669	* APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1670	* APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1671	* APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1672	* APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1673	* APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1674	* APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1675	* APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1676	* APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1677	* APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1678	* APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1679	* APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1680	* APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1681	* APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1682	* APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1683	* APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1684	* APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1685	* APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1686	* APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1687	* APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1688	* APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	1689	* APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	1690	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1691	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	172:65be27845400	1692	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
AnnaBridge	172:65be27845400	1693	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
AnnaBridge	172:65be27845400	1694	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	172:65be27845400	1695	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	172:65be27845400	1696	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	172:65be27845400	1697	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
AnnaBridge	172:65be27845400	1698	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
AnnaBridge	172:65be27845400	1699	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
AnnaBridge	172:65be27845400	1700	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	172:65be27845400	1701	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
AnnaBridge	172:65be27845400	1702	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	172:65be27845400	1703	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
AnnaBridge	172:65be27845400	1704	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	172:65be27845400	1705	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
AnnaBridge	172:65be27845400	1706	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
AnnaBridge	172:65be27845400	1707	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
AnnaBridge	172:65be27845400	1708	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	172:65be27845400	1709	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	172:65be27845400	1710	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	172:65be27845400	1711	* @arg @ref LL_APB1_GRP1_PERIPH_CEC
AnnaBridge	172:65be27845400	1712	* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
AnnaBridge	172:65be27845400	1713	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
AnnaBridge	172:65be27845400	1714	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
AnnaBridge	172:65be27845400	1715	* @retval None
AnnaBridge	172:65be27845400	1716	*/
AnnaBridge	172:65be27845400	1717	__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1718	{
AnnaBridge	172:65be27845400	1719	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1720	SET_BIT(RCC->APB1LLPENR, Periphs);
AnnaBridge	172:65be27845400	1721	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1722	tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);
AnnaBridge	172:65be27845400	1723	(void)tmpreg;
AnnaBridge	172:65be27845400	1724	}
AnnaBridge	172:65be27845400	1725
AnnaBridge	172:65be27845400	1726	/**
AnnaBridge	172:65be27845400	1727	* @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1728	* @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1729	* APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1730	* APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1731	* APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1732	* APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1733	* APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1734	* APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1735	* APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1736	* APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1737	* APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1738	* APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1739	* APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1740	* APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1741	* APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1742	* APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1743	* APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1744	* APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1745	* APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1746	* APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1747	* APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1748	* APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1749	* APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1750	* APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1751	* APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	1752	* APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	1753	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1754	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	172:65be27845400	1755	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
AnnaBridge	172:65be27845400	1756	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
AnnaBridge	172:65be27845400	1757	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
AnnaBridge	172:65be27845400	1758	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	172:65be27845400	1759	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	172:65be27845400	1760	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
AnnaBridge	172:65be27845400	1761	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
AnnaBridge	172:65be27845400	1762	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
AnnaBridge	172:65be27845400	1763	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	172:65be27845400	1764	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
AnnaBridge	172:65be27845400	1765	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	172:65be27845400	1766	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX
AnnaBridge	172:65be27845400	1767	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	172:65be27845400	1768	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
AnnaBridge	172:65be27845400	1769	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
AnnaBridge	172:65be27845400	1770	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
AnnaBridge	172:65be27845400	1771	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	172:65be27845400	1772	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
AnnaBridge	172:65be27845400	1773	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	172:65be27845400	1774	* @arg @ref LL_APB1_GRP1_PERIPH_CEC
AnnaBridge	172:65be27845400	1775	* @arg @ref LL_APB1_GRP1_PERIPH_DAC12
AnnaBridge	172:65be27845400	1776	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
AnnaBridge	172:65be27845400	1777	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
AnnaBridge	172:65be27845400	1778	* @retval None
AnnaBridge	172:65be27845400	1779	*/
AnnaBridge	172:65be27845400	1780	__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1781	{
AnnaBridge	172:65be27845400	1782	CLEAR_BIT(RCC->APB1LLPENR, Periphs);
AnnaBridge	172:65be27845400	1783	}
AnnaBridge	172:65be27845400	1784
AnnaBridge	172:65be27845400	1785	/**
AnnaBridge	172:65be27845400	1786	* @brief Enable APB1 peripherals clock.
AnnaBridge	172:65be27845400	1787	* @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n
AnnaBridge	172:65be27845400	1788	* APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n
AnnaBridge	172:65be27845400	1789	* APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n
AnnaBridge	172:65be27845400	1790	* APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n
AnnaBridge	172:65be27845400	1791	* APB1HENR FDCANEN LL_APB1_GRP2_EnableClock
AnnaBridge	172:65be27845400	1792	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1793	* @arg @ref LL_APB1_GRP2_PERIPH_CRS
AnnaBridge	172:65be27845400	1794	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
AnnaBridge	172:65be27845400	1795	* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
AnnaBridge	172:65be27845400	1796	* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
AnnaBridge	172:65be27845400	1797	* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
AnnaBridge	172:65be27845400	1798	* @retval None
AnnaBridge	172:65be27845400	1799	*/
AnnaBridge	172:65be27845400	1800	__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1801	{
AnnaBridge	172:65be27845400	1802	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1803	SET_BIT(RCC->APB1HENR, Periphs);
AnnaBridge	172:65be27845400	1804	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1805	tmpreg = READ_BIT(RCC->APB1HENR, Periphs);
AnnaBridge	172:65be27845400	1806	(void)tmpreg;
AnnaBridge	172:65be27845400	1807	}
AnnaBridge	172:65be27845400	1808
AnnaBridge	172:65be27845400	1809	/**
AnnaBridge	172:65be27845400	1810	* @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	1811	* @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	172:65be27845400	1812	* APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	172:65be27845400	1813	* APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	172:65be27845400	1814	* APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	172:65be27845400	1815	* APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock
AnnaBridge	172:65be27845400	1816	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1817	* @arg @ref LL_APB1_GRP2_PERIPH_CRS
AnnaBridge	172:65be27845400	1818	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
AnnaBridge	172:65be27845400	1819	* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
AnnaBridge	172:65be27845400	1820	* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
AnnaBridge	172:65be27845400	1821	* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
AnnaBridge	172:65be27845400	1822	* @retval uint32_t
AnnaBridge	172:65be27845400	1823	*/
AnnaBridge	172:65be27845400	1824	__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1825	{
AnnaBridge	172:65be27845400	1826	return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	1827	}
AnnaBridge	172:65be27845400	1828
AnnaBridge	172:65be27845400	1829	/**
AnnaBridge	172:65be27845400	1830	* @brief Disable APB1 peripherals clock.
AnnaBridge	172:65be27845400	1831	* @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n
AnnaBridge	172:65be27845400	1832	* APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n
AnnaBridge	172:65be27845400	1833	* APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n
AnnaBridge	172:65be27845400	1834	* APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n
AnnaBridge	172:65be27845400	1835	* APB1HENR FDCANEN LL_APB1_GRP2_DisableClock
AnnaBridge	172:65be27845400	1836	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1837	* @arg @ref LL_APB1_GRP2_PERIPH_CRS
AnnaBridge	172:65be27845400	1838	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
AnnaBridge	172:65be27845400	1839	* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
AnnaBridge	172:65be27845400	1840	* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
AnnaBridge	172:65be27845400	1841	* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
AnnaBridge	172:65be27845400	1842	* @retval None
AnnaBridge	172:65be27845400	1843	*/
AnnaBridge	172:65be27845400	1844	__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1845	{
AnnaBridge	172:65be27845400	1846	CLEAR_BIT(RCC->APB1HENR, Periphs);
AnnaBridge	172:65be27845400	1847	}
AnnaBridge	172:65be27845400	1848
AnnaBridge	172:65be27845400	1849	/**
AnnaBridge	172:65be27845400	1850	* @brief Force APB1 peripherals reset.
AnnaBridge	172:65be27845400	1851	* @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n
AnnaBridge	172:65be27845400	1852	* APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n
AnnaBridge	172:65be27845400	1853	* APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n
AnnaBridge	172:65be27845400	1854	* APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n
AnnaBridge	172:65be27845400	1855	* APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset
AnnaBridge	172:65be27845400	1856	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1857	* @arg @ref LL_APB1_GRP2_PERIPH_CRS
AnnaBridge	172:65be27845400	1858	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
AnnaBridge	172:65be27845400	1859	* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
AnnaBridge	172:65be27845400	1860	* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
AnnaBridge	172:65be27845400	1861	* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
AnnaBridge	172:65be27845400	1862	* @retval None
AnnaBridge	172:65be27845400	1863	*/
AnnaBridge	172:65be27845400	1864	__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1865	{
AnnaBridge	172:65be27845400	1866	SET_BIT(RCC->APB1HRSTR, Periphs);
AnnaBridge	172:65be27845400	1867	}
AnnaBridge	172:65be27845400	1868
AnnaBridge	172:65be27845400	1869	/**
AnnaBridge	172:65be27845400	1870	* @brief Release APB1 peripherals reset.
AnnaBridge	172:65be27845400	1871	* @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	172:65be27845400	1872	* APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	172:65be27845400	1873	* APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	172:65be27845400	1874	* APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	172:65be27845400	1875	* APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset
AnnaBridge	172:65be27845400	1876	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1877	* @arg @ref LL_APB1_GRP2_PERIPH_CRS
AnnaBridge	172:65be27845400	1878	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
AnnaBridge	172:65be27845400	1879	* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
AnnaBridge	172:65be27845400	1880	* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
AnnaBridge	172:65be27845400	1881	* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
AnnaBridge	172:65be27845400	1882	* @retval None
AnnaBridge	172:65be27845400	1883	*/
AnnaBridge	172:65be27845400	1884	__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	1885	{
AnnaBridge	172:65be27845400	1886	CLEAR_BIT(RCC->APB1HRSTR, Periphs);
AnnaBridge	172:65be27845400	1887	}
AnnaBridge	172:65be27845400	1888
AnnaBridge	172:65be27845400	1889	/**
AnnaBridge	172:65be27845400	1890	* @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1891	* @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n
AnnaBridge	172:65be27845400	1892	* APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n
AnnaBridge	172:65be27845400	1893	* APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n
AnnaBridge	172:65be27845400	1894	* APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n
AnnaBridge	172:65be27845400	1895	* APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep
AnnaBridge	172:65be27845400	1896	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1897	* @arg @ref LL_APB1_GRP2_PERIPH_CRS
AnnaBridge	172:65be27845400	1898	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
AnnaBridge	172:65be27845400	1899	* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
AnnaBridge	172:65be27845400	1900	* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
AnnaBridge	172:65be27845400	1901	* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
AnnaBridge	172:65be27845400	1902	* @retval None
AnnaBridge	172:65be27845400	1903	*/
AnnaBridge	172:65be27845400	1904	__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1905	{
AnnaBridge	172:65be27845400	1906	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1907	SET_BIT(RCC->APB1HLPENR, Periphs);
AnnaBridge	172:65be27845400	1908	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1909	tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);
AnnaBridge	172:65be27845400	1910	(void)tmpreg;
AnnaBridge	172:65be27845400	1911	}
AnnaBridge	172:65be27845400	1912
AnnaBridge	172:65be27845400	1913	/**
AnnaBridge	172:65be27845400	1914	* @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	1915	* @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n
AnnaBridge	172:65be27845400	1916	* APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n
AnnaBridge	172:65be27845400	1917	* APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n
AnnaBridge	172:65be27845400	1918	* APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n
AnnaBridge	172:65be27845400	1919	* APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep
AnnaBridge	172:65be27845400	1920	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1921	* @arg @ref LL_APB1_GRP2_PERIPH_CRS
AnnaBridge	172:65be27845400	1922	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
AnnaBridge	172:65be27845400	1923	* @arg @ref LL_APB1_GRP2_PERIPH_OPAMP
AnnaBridge	172:65be27845400	1924	* @arg @ref LL_APB1_GRP2_PERIPH_MDIOS
AnnaBridge	172:65be27845400	1925	* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN
AnnaBridge	172:65be27845400	1926	* @retval None
AnnaBridge	172:65be27845400	1927	*/
AnnaBridge	172:65be27845400	1928	__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	1929	{
AnnaBridge	172:65be27845400	1930	CLEAR_BIT(RCC->APB1HLPENR, Periphs);
AnnaBridge	172:65be27845400	1931	}
AnnaBridge	172:65be27845400	1932
AnnaBridge	172:65be27845400	1933	/**
AnnaBridge	172:65be27845400	1934	* @}
AnnaBridge	172:65be27845400	1935	*/
AnnaBridge	172:65be27845400	1936
AnnaBridge	172:65be27845400	1937	/** @defgroup BUS_LL_EF_APB2 APB2
AnnaBridge	172:65be27845400	1938	* @{
AnnaBridge	172:65be27845400	1939	*/
AnnaBridge	172:65be27845400	1940
AnnaBridge	172:65be27845400	1941	/**
AnnaBridge	172:65be27845400	1942	* @brief Enable APB2 peripherals clock.
AnnaBridge	172:65be27845400	1943	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1944	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1945	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1946	* APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1947	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1948	* APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1949	* APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1950	* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1951	* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1952	* APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1953	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1954	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1955	* APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1956	* APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	1957	* APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock
AnnaBridge	172:65be27845400	1958	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1959	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	172:65be27845400	1960	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
AnnaBridge	172:65be27845400	1961	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	172:65be27845400	1962	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
AnnaBridge	172:65be27845400	1963	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	172:65be27845400	1964	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
AnnaBridge	172:65be27845400	1965	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	172:65be27845400	1966	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	172:65be27845400	1967	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
AnnaBridge	172:65be27845400	1968	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
AnnaBridge	172:65be27845400	1969	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	172:65be27845400	1970	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
AnnaBridge	172:65be27845400	1971	* @arg @ref LL_APB2_GRP1_PERIPH_SAI3
AnnaBridge	172:65be27845400	1972	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	172:65be27845400	1973	* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
AnnaBridge	172:65be27845400	1974	* @retval None
AnnaBridge	172:65be27845400	1975	*/
AnnaBridge	172:65be27845400	1976	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	1977	{
AnnaBridge	172:65be27845400	1978	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	1979	SET_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	172:65be27845400	1980	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	1981	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	172:65be27845400	1982	(void)tmpreg;
AnnaBridge	172:65be27845400	1983	}
AnnaBridge	172:65be27845400	1984
AnnaBridge	172:65be27845400	1985	/**
AnnaBridge	172:65be27845400	1986	* @brief Check if APB2 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	1987	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1988	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1989	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1990	* APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1991	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1992	* APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1993	* APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1994	* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1995	* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1996	* APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1997	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1998	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	1999	* APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2000	* APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2001	* APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	2002	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2003	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	172:65be27845400	2004	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
AnnaBridge	172:65be27845400	2005	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	172:65be27845400	2006	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
AnnaBridge	172:65be27845400	2007	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	172:65be27845400	2008	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
AnnaBridge	172:65be27845400	2009	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	172:65be27845400	2010	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	172:65be27845400	2011	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
AnnaBridge	172:65be27845400	2012	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
AnnaBridge	172:65be27845400	2013	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	172:65be27845400	2014	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
AnnaBridge	172:65be27845400	2015	* @arg @ref LL_APB2_GRP1_PERIPH_SAI3
AnnaBridge	172:65be27845400	2016	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	172:65be27845400	2017	* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
AnnaBridge	172:65be27845400	2018	* @retval uint32_t
AnnaBridge	172:65be27845400	2019	*/
AnnaBridge	172:65be27845400	2020	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	2021	{
AnnaBridge	172:65be27845400	2022	return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	2023	}
AnnaBridge	172:65be27845400	2024
AnnaBridge	172:65be27845400	2025	/**
AnnaBridge	172:65be27845400	2026	* @brief Disable APB2 peripherals clock.
AnnaBridge	172:65be27845400	2027	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2028	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2029	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2030	* APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2031	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2032	* APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2033	* APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2034	* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2035	* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2036	* APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2037	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2038	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2039	* APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2040	* APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2041	* APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock
AnnaBridge	172:65be27845400	2042	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2043	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	172:65be27845400	2044	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
AnnaBridge	172:65be27845400	2045	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	172:65be27845400	2046	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
AnnaBridge	172:65be27845400	2047	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	172:65be27845400	2048	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
AnnaBridge	172:65be27845400	2049	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	172:65be27845400	2050	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	172:65be27845400	2051	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
AnnaBridge	172:65be27845400	2052	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
AnnaBridge	172:65be27845400	2053	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	172:65be27845400	2054	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
AnnaBridge	172:65be27845400	2055	* @arg @ref LL_APB2_GRP1_PERIPH_SAI3
AnnaBridge	172:65be27845400	2056	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	172:65be27845400	2057	* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
AnnaBridge	172:65be27845400	2058	* @retval None
AnnaBridge	172:65be27845400	2059	*/
AnnaBridge	172:65be27845400	2060	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	2061	{
AnnaBridge	172:65be27845400	2062	CLEAR_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	172:65be27845400	2063	}
AnnaBridge	172:65be27845400	2064
AnnaBridge	172:65be27845400	2065	/**
AnnaBridge	172:65be27845400	2066	* @brief Force APB2 peripherals reset.
AnnaBridge	172:65be27845400	2067	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2068	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2069	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2070	* APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2071	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2072	* APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2073	* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2074	* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2075	* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2076	* APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2077	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2078	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2079	* APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2080	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2081	* APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset
AnnaBridge	172:65be27845400	2082	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2083	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	172:65be27845400	2084	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
AnnaBridge	172:65be27845400	2085	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	172:65be27845400	2086	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
AnnaBridge	172:65be27845400	2087	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	172:65be27845400	2088	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
AnnaBridge	172:65be27845400	2089	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	172:65be27845400	2090	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	172:65be27845400	2091	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
AnnaBridge	172:65be27845400	2092	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
AnnaBridge	172:65be27845400	2093	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	172:65be27845400	2094	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
AnnaBridge	172:65be27845400	2095	* @arg @ref LL_APB2_GRP1_PERIPH_SAI3
AnnaBridge	172:65be27845400	2096	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	172:65be27845400	2097	* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
AnnaBridge	172:65be27845400	2098	* @retval None
AnnaBridge	172:65be27845400	2099	*/
AnnaBridge	172:65be27845400	2100	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	2101	{
AnnaBridge	172:65be27845400	2102	SET_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	172:65be27845400	2103	}
AnnaBridge	172:65be27845400	2104
AnnaBridge	172:65be27845400	2105	/**
AnnaBridge	172:65be27845400	2106	* @brief Release APB2 peripherals reset.
AnnaBridge	172:65be27845400	2107	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2108	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2109	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2110	* APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2111	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2112	* APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2113	* APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2114	* APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2115	* APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2116	* APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2117	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2118	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2119	* APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2120	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2121	* APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset
AnnaBridge	172:65be27845400	2122	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2123	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	172:65be27845400	2124	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
AnnaBridge	172:65be27845400	2125	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	172:65be27845400	2126	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
AnnaBridge	172:65be27845400	2127	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	172:65be27845400	2128	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
AnnaBridge	172:65be27845400	2129	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	172:65be27845400	2130	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	172:65be27845400	2131	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
AnnaBridge	172:65be27845400	2132	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
AnnaBridge	172:65be27845400	2133	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	172:65be27845400	2134	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
AnnaBridge	172:65be27845400	2135	* @arg @ref LL_APB2_GRP1_PERIPH_SAI3
AnnaBridge	172:65be27845400	2136	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	172:65be27845400	2137	* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
AnnaBridge	172:65be27845400	2138	* @retval None
AnnaBridge	172:65be27845400	2139	*/
AnnaBridge	172:65be27845400	2140	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	2141	{
AnnaBridge	172:65be27845400	2142	CLEAR_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	172:65be27845400	2143	}
AnnaBridge	172:65be27845400	2144
AnnaBridge	172:65be27845400	2145	/**
AnnaBridge	172:65be27845400	2146	* @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2147	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2148	* APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2149	* APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2150	* APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2151	* APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2152	* APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2153	* APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2154	* APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2155	* APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2156	* APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2157	* APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2158	* APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2159	* APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2160	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2161	* APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	2162	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2163	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	172:65be27845400	2164	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
AnnaBridge	172:65be27845400	2165	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	172:65be27845400	2166	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
AnnaBridge	172:65be27845400	2167	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	172:65be27845400	2168	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
AnnaBridge	172:65be27845400	2169	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	172:65be27845400	2170	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	172:65be27845400	2171	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
AnnaBridge	172:65be27845400	2172	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
AnnaBridge	172:65be27845400	2173	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	172:65be27845400	2174	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
AnnaBridge	172:65be27845400	2175	* @arg @ref LL_APB2_GRP1_PERIPH_SAI3
AnnaBridge	172:65be27845400	2176	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	172:65be27845400	2177	* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
AnnaBridge	172:65be27845400	2178	* @retval None
AnnaBridge	172:65be27845400	2179	*/
AnnaBridge	172:65be27845400	2180	__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	2181	{
AnnaBridge	172:65be27845400	2182	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	2183	SET_BIT(RCC->APB2LPENR, Periphs);
AnnaBridge	172:65be27845400	2184	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	2185	tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
AnnaBridge	172:65be27845400	2186	(void)tmpreg;
AnnaBridge	172:65be27845400	2187	}
AnnaBridge	172:65be27845400	2188
AnnaBridge	172:65be27845400	2189	/**
AnnaBridge	172:65be27845400	2190	* @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2191	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2192	* APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2193	* APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2194	* APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2195	* APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2196	* APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2197	* APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2198	* APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2199	* APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2200	* APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2201	* APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2202	* APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2203	* APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2204	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2205	* APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	2206	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2207	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	172:65be27845400	2208	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
AnnaBridge	172:65be27845400	2209	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	172:65be27845400	2210	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
AnnaBridge	172:65be27845400	2211	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	172:65be27845400	2212	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
AnnaBridge	172:65be27845400	2213	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	172:65be27845400	2214	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	172:65be27845400	2215	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
AnnaBridge	172:65be27845400	2216	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
AnnaBridge	172:65be27845400	2217	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	172:65be27845400	2218	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
AnnaBridge	172:65be27845400	2219	* @arg @ref LL_APB2_GRP1_PERIPH_SAI3
AnnaBridge	172:65be27845400	2220	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	172:65be27845400	2221	* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM
AnnaBridge	172:65be27845400	2222	* @retval None
AnnaBridge	172:65be27845400	2223	*/
AnnaBridge	172:65be27845400	2224	__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	2225	{
AnnaBridge	172:65be27845400	2226	CLEAR_BIT(RCC->APB2LPENR, Periphs);
AnnaBridge	172:65be27845400	2227	}
AnnaBridge	172:65be27845400	2228
AnnaBridge	172:65be27845400	2229	/**
AnnaBridge	172:65be27845400	2230	* @}
AnnaBridge	172:65be27845400	2231	*/
AnnaBridge	172:65be27845400	2232
AnnaBridge	172:65be27845400	2233	/** @defgroup BUS_LL_EF_APB4 APB4
AnnaBridge	172:65be27845400	2234	* @{
AnnaBridge	172:65be27845400	2235	*/
AnnaBridge	172:65be27845400	2236
AnnaBridge	172:65be27845400	2237	/**
AnnaBridge	172:65be27845400	2238	* @brief Enable APB4 peripherals clock.
AnnaBridge	172:65be27845400	2239	* @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2240	* APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2241	* APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2242	* APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2243	* APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2244	* APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2245	* APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2246	* APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2247	* APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2248	* APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2249	* APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n
AnnaBridge	172:65be27845400	2250	* APB4ENR SAI4EN LL_APB4_GRP1_EnableClock
AnnaBridge	172:65be27845400	2251	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2252	* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
AnnaBridge	172:65be27845400	2253	* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2254	* @arg @ref LL_APB4_GRP1_PERIPH_SPI6
AnnaBridge	172:65be27845400	2255	* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
AnnaBridge	172:65be27845400	2256	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2257	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2258	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2259	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2260	* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
AnnaBridge	172:65be27845400	2261	* @arg @ref LL_APB4_GRP1_PERIPH_VREF
AnnaBridge	172:65be27845400	2262	* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
AnnaBridge	172:65be27845400	2263	* @arg @ref LL_APB4_GRP1_PERIPH_SAI4
AnnaBridge	172:65be27845400	2264	* @retval None
AnnaBridge	172:65be27845400	2265	*/
AnnaBridge	172:65be27845400	2266	__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	2267	{
AnnaBridge	172:65be27845400	2268	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	2269	SET_BIT(RCC->APB4ENR, Periphs);
AnnaBridge	172:65be27845400	2270	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	2271	tmpreg = READ_BIT(RCC->APB4ENR, Periphs);
AnnaBridge	172:65be27845400	2272	(void)tmpreg;
AnnaBridge	172:65be27845400	2273	}
AnnaBridge	172:65be27845400	2274
AnnaBridge	172:65be27845400	2275	/**
AnnaBridge	172:65be27845400	2276	* @brief Check if APB4 peripheral clock is enabled or not
AnnaBridge	172:65be27845400	2277	* @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2278	* APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2279	* APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2280	* APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2281	* APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2282	* APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2283	* APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2284	* APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2285	* APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2286	* APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2287	* APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n
AnnaBridge	172:65be27845400	2288	* APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock
AnnaBridge	172:65be27845400	2289	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2290	* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
AnnaBridge	172:65be27845400	2291	* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2292	* @arg @ref LL_APB4_GRP1_PERIPH_SPI6
AnnaBridge	172:65be27845400	2293	* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
AnnaBridge	172:65be27845400	2294	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2295	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2296	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2297	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2298	* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
AnnaBridge	172:65be27845400	2299	* @arg @ref LL_APB4_GRP1_PERIPH_VREF
AnnaBridge	172:65be27845400	2300	* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
AnnaBridge	172:65be27845400	2301	* @arg @ref LL_APB4_GRP1_PERIPH_SAI4
AnnaBridge	172:65be27845400	2302	* @retval uint32_t
AnnaBridge	172:65be27845400	2303	*/
AnnaBridge	172:65be27845400	2304	__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	2305	{
AnnaBridge	172:65be27845400	2306	return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
AnnaBridge	172:65be27845400	2307	}
AnnaBridge	172:65be27845400	2308
AnnaBridge	172:65be27845400	2309	/**
AnnaBridge	172:65be27845400	2310	* @brief Disable APB4 peripherals clock.
AnnaBridge	172:65be27845400	2311	* @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2312	* APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2313	* APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2314	* APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2315	* APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2316	* APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2317	* APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2318	* APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2319	* APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2320	* APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2321	* APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n
AnnaBridge	172:65be27845400	2322	* APB4ENR SAI4EN LL_APB4_GRP1_DisableClock
AnnaBridge	172:65be27845400	2323	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2324	* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
AnnaBridge	172:65be27845400	2325	* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2326	* @arg @ref LL_APB4_GRP1_PERIPH_SPI6
AnnaBridge	172:65be27845400	2327	* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
AnnaBridge	172:65be27845400	2328	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2329	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2330	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2331	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2332	* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
AnnaBridge	172:65be27845400	2333	* @arg @ref LL_APB4_GRP1_PERIPH_VREF
AnnaBridge	172:65be27845400	2334	* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
AnnaBridge	172:65be27845400	2335	* @arg @ref LL_APB4_GRP1_PERIPH_SAI4
AnnaBridge	172:65be27845400	2336	* @retval None
AnnaBridge	172:65be27845400	2337	*/
AnnaBridge	172:65be27845400	2338	__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	172:65be27845400	2339	{
AnnaBridge	172:65be27845400	2340	CLEAR_BIT(RCC->APB4ENR, Periphs);
AnnaBridge	172:65be27845400	2341	}
AnnaBridge	172:65be27845400	2342
AnnaBridge	172:65be27845400	2343	/**
AnnaBridge	172:65be27845400	2344	* @brief Force APB4 peripherals reset.
AnnaBridge	172:65be27845400	2345	* @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2346	* APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2347	* APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2348	* APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2349	* APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2350	* APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2351	* APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2352	* APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2353	* APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2354	* APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n
AnnaBridge	172:65be27845400	2355	* APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset
AnnaBridge	172:65be27845400	2356	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2357	* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
AnnaBridge	172:65be27845400	2358	* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2359	* @arg @ref LL_APB4_GRP1_PERIPH_SPI6
AnnaBridge	172:65be27845400	2360	* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
AnnaBridge	172:65be27845400	2361	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2362	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2363	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2364	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2365	* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
AnnaBridge	172:65be27845400	2366	* @arg @ref LL_APB4_GRP1_PERIPH_VREF
AnnaBridge	172:65be27845400	2367	* @arg @ref LL_APB4_GRP1_PERIPH_SAI4
AnnaBridge	172:65be27845400	2368	* @retval None
AnnaBridge	172:65be27845400	2369	*/
AnnaBridge	172:65be27845400	2370	__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	2371	{
AnnaBridge	172:65be27845400	2372	SET_BIT(RCC->APB4RSTR, Periphs);
AnnaBridge	172:65be27845400	2373	}
AnnaBridge	172:65be27845400	2374
AnnaBridge	172:65be27845400	2375	/**
AnnaBridge	172:65be27845400	2376	* @brief Release APB4 peripherals reset.
AnnaBridge	172:65be27845400	2377	* @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2378	* APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2379	* APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2380	* APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2381	* APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2382	* APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2383	* APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2384	* APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2385	* APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2386	* APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n
AnnaBridge	172:65be27845400	2387	* APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset
AnnaBridge	172:65be27845400	2388	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2389	* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
AnnaBridge	172:65be27845400	2390	* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2391	* @arg @ref LL_APB4_GRP1_PERIPH_SPI6
AnnaBridge	172:65be27845400	2392	* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
AnnaBridge	172:65be27845400	2393	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2394	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2395	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2396	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2397	* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
AnnaBridge	172:65be27845400	2398	* @arg @ref LL_APB4_GRP1_PERIPH_VREF
AnnaBridge	172:65be27845400	2399	* @arg @ref LL_APB4_GRP1_PERIPH_SAI4
AnnaBridge	172:65be27845400	2400	* @retval None
AnnaBridge	172:65be27845400	2401	*/
AnnaBridge	172:65be27845400	2402	__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	172:65be27845400	2403	{
AnnaBridge	172:65be27845400	2404	CLEAR_BIT(RCC->APB4RSTR, Periphs);
AnnaBridge	172:65be27845400	2405	}
AnnaBridge	172:65be27845400	2406
AnnaBridge	172:65be27845400	2407	/**
AnnaBridge	172:65be27845400	2408	* @brief Enable APB4 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2409	* @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2410	* APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2411	* APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2412	* APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2413	* APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2414	* APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2415	* APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2416	* APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2417	* APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2418	* APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2419	* APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n
AnnaBridge	172:65be27845400	2420	* APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep
AnnaBridge	172:65be27845400	2421	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2422	* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
AnnaBridge	172:65be27845400	2423	* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2424	* @arg @ref LL_APB4_GRP1_PERIPH_SPI6
AnnaBridge	172:65be27845400	2425	* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
AnnaBridge	172:65be27845400	2426	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2427	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2428	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2429	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2430	* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
AnnaBridge	172:65be27845400	2431	* @arg @ref LL_APB4_GRP1_PERIPH_VREF
AnnaBridge	172:65be27845400	2432	* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
AnnaBridge	172:65be27845400	2433	* @arg @ref LL_APB4_GRP1_PERIPH_SAI4
AnnaBridge	172:65be27845400	2434	* @retval None
AnnaBridge	172:65be27845400	2435	*/
AnnaBridge	172:65be27845400	2436	__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	2437	{
AnnaBridge	172:65be27845400	2438	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	2439	SET_BIT(RCC->APB4LPENR, Periphs);
AnnaBridge	172:65be27845400	2440	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	2441	tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);
AnnaBridge	172:65be27845400	2442	(void)tmpreg;
AnnaBridge	172:65be27845400	2443	}
AnnaBridge	172:65be27845400	2444
AnnaBridge	172:65be27845400	2445	/**
AnnaBridge	172:65be27845400	2446	* @brief Disable APB4 peripherals clock during Low Power (Sleep) mode.
AnnaBridge	172:65be27845400	2447	* @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2448	* APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2449	* APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2450	* APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2451	* APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2452	* APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2453	* APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2454	* APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2455	* APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2456	* APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2457	* APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n
AnnaBridge	172:65be27845400	2458	* APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep
AnnaBridge	172:65be27845400	2459	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2460	* @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG
AnnaBridge	172:65be27845400	2461	* @arg @ref LL_APB4_GRP1_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2462	* @arg @ref LL_APB4_GRP1_PERIPH_SPI6
AnnaBridge	172:65be27845400	2463	* @arg @ref LL_APB4_GRP1_PERIPH_I2C4
AnnaBridge	172:65be27845400	2464	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2465	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2466	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2467	* @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2468	* @arg @ref LL_APB4_GRP1_PERIPH_COMP12
AnnaBridge	172:65be27845400	2469	* @arg @ref LL_APB4_GRP1_PERIPH_VREF
AnnaBridge	172:65be27845400	2470	* @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB
AnnaBridge	172:65be27845400	2471	* @arg @ref LL_APB4_GRP1_PERIPH_SAI4
AnnaBridge	172:65be27845400	2472	* @retval None
AnnaBridge	172:65be27845400	2473	*/
AnnaBridge	172:65be27845400	2474	__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
AnnaBridge	172:65be27845400	2475	{
AnnaBridge	172:65be27845400	2476	CLEAR_BIT(RCC->APB4LPENR, Periphs);
AnnaBridge	172:65be27845400	2477	}
AnnaBridge	172:65be27845400	2478
AnnaBridge	172:65be27845400	2479	/**
AnnaBridge	172:65be27845400	2480	* @}
AnnaBridge	172:65be27845400	2481	*/
AnnaBridge	172:65be27845400	2482
AnnaBridge	172:65be27845400	2483	/** @defgroup BUS_LL_EF_CLKAM BUS_LL_EF_CLKAM
AnnaBridge	172:65be27845400	2484	* @{
AnnaBridge	172:65be27845400	2485	*/
AnnaBridge	172:65be27845400	2486
AnnaBridge	172:65be27845400	2487	/**
AnnaBridge	172:65be27845400	2488	* @brief Enable peripherals clock for CLKAM Mode.
AnnaBridge	172:65be27845400	2489	* @rmtoll D3AMR BDMA LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2490	* D3AMR LPUART1 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2491	* D3AMR SPI6 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2492	* D3AMR I2C4 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2493	* D3AMR LPTIM2 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2494	* D3AMR LPTIM3 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2495	* D3AMR LPTIM4 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2496	* D3AMR LPTIM5 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2497	* D3AMR COMP12 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2498	* D3AMR VREF LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2499	* D3AMR RTC LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2500	* D3AMR CRC LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2501	* D3AMR SAI4 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2502	* D3AMR ADC3 LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2503	* D3AMR BKPRAM LL_CLKAM_Enable\n
AnnaBridge	172:65be27845400	2504	* D3AMR SRAM4 LL_CLKAM_Enable
AnnaBridge	172:65be27845400	2505	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2506	* @arg @ref LL_CLKAM_PERIPH_BDMA
AnnaBridge	172:65be27845400	2507	* @arg @ref LL_CLKAM_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2508	* @arg @ref LL_CLKAM_PERIPH_SPI6
AnnaBridge	172:65be27845400	2509	* @arg @ref LL_CLKAM_PERIPH_I2C4
AnnaBridge	172:65be27845400	2510	* @arg @ref LL_CLKAM_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2511	* @arg @ref LL_CLKAM_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2512	* @arg @ref LL_CLKAM_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2513	* @arg @ref LL_CLKAM_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2514	* @arg @ref LL_CLKAM_PERIPH_COMP12
AnnaBridge	172:65be27845400	2515	* @arg @ref LL_CLKAM_PERIPH_VREF
AnnaBridge	172:65be27845400	2516	* @arg @ref LL_CLKAM_PERIPH_RTC
AnnaBridge	172:65be27845400	2517	* @arg @ref LL_CLKAM_PERIPH_CRC
AnnaBridge	172:65be27845400	2518	* @arg @ref LL_CLKAM_PERIPH_SAI4
AnnaBridge	172:65be27845400	2519	* @arg @ref LL_CLKAM_PERIPH_ADC3
AnnaBridge	172:65be27845400	2520	* @arg @ref LL_CLKAM_PERIPH_BKPRAM
AnnaBridge	172:65be27845400	2521	* @arg @ref LL_CLKAM_PERIPH_SRAM4
AnnaBridge	172:65be27845400	2522	* @retval None
AnnaBridge	172:65be27845400	2523	*/
AnnaBridge	172:65be27845400	2524	__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
AnnaBridge	172:65be27845400	2525	{
AnnaBridge	172:65be27845400	2526	__IO uint32_t tmpreg;
AnnaBridge	172:65be27845400	2527	SET_BIT(RCC->D3AMR, Periphs);
AnnaBridge	172:65be27845400	2528	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	172:65be27845400	2529	tmpreg = READ_BIT(RCC->D3AMR, Periphs);
AnnaBridge	172:65be27845400	2530	(void)tmpreg;
AnnaBridge	172:65be27845400	2531	}
AnnaBridge	172:65be27845400	2532
AnnaBridge	172:65be27845400	2533	/**
AnnaBridge	172:65be27845400	2534	* @brief Disable peripherals clock for CLKAM Mode.
AnnaBridge	172:65be27845400	2535	* @rmtoll D3AMR BDMA LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2536	* D3AMR LPUART1 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2537	* D3AMR SPI6 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2538	* D3AMR I2C4 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2539	* D3AMR LPTIM2 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2540	* D3AMR LPTIM3 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2541	* D3AMR LPTIM4 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2542	* D3AMR LPTIM5 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2543	* D3AMR COMP12 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2544	* D3AMR VREF LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2545	* D3AMR RTC LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2546	* D3AMR CRC LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2547	* D3AMR SAI4 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2548	* D3AMR ADC3 LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2549	* D3AMR BKPRAM LL_CLKAM_Disable\n
AnnaBridge	172:65be27845400	2550	* D3AMR SRAM4 LL_CLKAM_Disable
AnnaBridge	172:65be27845400	2551	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2552	* @arg @ref LL_CLKAM_PERIPH_BDMA
AnnaBridge	172:65be27845400	2553	* @arg @ref LL_CLKAM_PERIPH_LPUART1
AnnaBridge	172:65be27845400	2554	* @arg @ref LL_CLKAM_PERIPH_SPI6
AnnaBridge	172:65be27845400	2555	* @arg @ref LL_CLKAM_PERIPH_I2C4
AnnaBridge	172:65be27845400	2556	* @arg @ref LL_CLKAM_PERIPH_LPTIM2
AnnaBridge	172:65be27845400	2557	* @arg @ref LL_CLKAM_PERIPH_LPTIM3
AnnaBridge	172:65be27845400	2558	* @arg @ref LL_CLKAM_PERIPH_LPTIM4
AnnaBridge	172:65be27845400	2559	* @arg @ref LL_CLKAM_PERIPH_LPTIM5
AnnaBridge	172:65be27845400	2560	* @arg @ref LL_CLKAM_PERIPH_COMP12
AnnaBridge	172:65be27845400	2561	* @arg @ref LL_CLKAM_PERIPH_VREF
AnnaBridge	172:65be27845400	2562	* @arg @ref LL_CLKAM_PERIPH_RTC
AnnaBridge	172:65be27845400	2563	* @arg @ref LL_CLKAM_PERIPH_CRC
AnnaBridge	172:65be27845400	2564	* @arg @ref LL_CLKAM_PERIPH_SAI4
AnnaBridge	172:65be27845400	2565	* @arg @ref LL_CLKAM_PERIPH_ADC3
AnnaBridge	172:65be27845400	2566	* @arg @ref LL_CLKAM_PERIPH_BKPRAM
AnnaBridge	172:65be27845400	2567	* @arg @ref LL_CLKAM_PERIPH_SRAM4
AnnaBridge	172:65be27845400	2568	* @retval None
AnnaBridge	172:65be27845400	2569	*/
AnnaBridge	172:65be27845400	2570	__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
AnnaBridge	172:65be27845400	2571	{
AnnaBridge	172:65be27845400	2572	CLEAR_BIT(RCC->D3AMR, Periphs);
AnnaBridge	172:65be27845400	2573	}
AnnaBridge	172:65be27845400	2574
AnnaBridge	172:65be27845400	2575	/**
AnnaBridge	172:65be27845400	2576	* @}
AnnaBridge	172:65be27845400	2577	*/
AnnaBridge	172:65be27845400	2578
AnnaBridge	172:65be27845400	2579	/**
AnnaBridge	172:65be27845400	2580	* @}
AnnaBridge	172:65be27845400	2581	*/
AnnaBridge	172:65be27845400	2582
AnnaBridge	172:65be27845400	2583	/**
AnnaBridge	172:65be27845400	2584	* @}
AnnaBridge	172:65be27845400	2585	*/
AnnaBridge	172:65be27845400	2586
AnnaBridge	172:65be27845400	2587	#endif /* defined(RCC) */
AnnaBridge	172:65be27845400	2588
AnnaBridge	172:65be27845400	2589	/**
AnnaBridge	172:65be27845400	2590	* @}
AnnaBridge	172:65be27845400	2591	*/
AnnaBridge	172:65be27845400	2592
AnnaBridge	172:65be27845400	2593	#ifdef __cplusplus
AnnaBridge	172:65be27845400	2594	}
AnnaBridge	172:65be27845400	2595	#endif
AnnaBridge	172:65be27845400	2596
AnnaBridge	172:65be27845400	2597	#endif /* STM32H7xx_LL_BUS_H */
AnnaBridge	172:65be27845400	2598
AnnaBridge	172:65be27845400	2599	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/