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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_sram.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32h7xx_hal_sram.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of SRAM HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 172:65be27845400 12 * the "License"; You may not use this file except in compliance with the
AnnaBridge 172:65be27845400 13 * License. You may obtain a copy of the License at:
AnnaBridge 172:65be27845400 14 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 172:65be27845400 15 *
AnnaBridge 172:65be27845400 16 ******************************************************************************
AnnaBridge 172:65be27845400 17 */
AnnaBridge 172:65be27845400 18
AnnaBridge 172:65be27845400 19 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 20 #ifndef STM32H7xx_HAL_SRAM_H
AnnaBridge 172:65be27845400 21 #define STM32H7xx_HAL_SRAM_H
AnnaBridge 172:65be27845400 22
AnnaBridge 172:65be27845400 23 #ifdef __cplusplus
AnnaBridge 172:65be27845400 24 extern "C" {
AnnaBridge 172:65be27845400 25 #endif
AnnaBridge 172:65be27845400 26
AnnaBridge 172:65be27845400 27
AnnaBridge 172:65be27845400 28 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 29 #include "stm32h7xx_ll_fmc.h"
AnnaBridge 172:65be27845400 30
AnnaBridge 172:65be27845400 31 /** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge 172:65be27845400 32 * @{
AnnaBridge 172:65be27845400 33 */
AnnaBridge 172:65be27845400 34 /** @addtogroup SRAM
AnnaBridge 172:65be27845400 35 * @{
AnnaBridge 172:65be27845400 36 */
AnnaBridge 172:65be27845400 37
AnnaBridge 172:65be27845400 38 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 /** @defgroup SRAM_Exported_Types SRAM Exported Types
AnnaBridge 172:65be27845400 41 * @{
AnnaBridge 172:65be27845400 42 */
AnnaBridge 172:65be27845400 43 /**
AnnaBridge 172:65be27845400 44 * @brief HAL SRAM State structures definition
AnnaBridge 172:65be27845400 45 */
AnnaBridge 172:65be27845400 46 typedef enum
AnnaBridge 172:65be27845400 47 {
AnnaBridge 172:65be27845400 48 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
AnnaBridge 172:65be27845400 49 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
AnnaBridge 172:65be27845400 50 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
AnnaBridge 172:65be27845400 51 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
AnnaBridge 172:65be27845400 52 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
AnnaBridge 172:65be27845400 53
AnnaBridge 172:65be27845400 54 } HAL_SRAM_StateTypeDef;
AnnaBridge 172:65be27845400 55
AnnaBridge 172:65be27845400 56 /**
AnnaBridge 172:65be27845400 57 * @brief SRAM handle Structure definition
AnnaBridge 172:65be27845400 58 */
AnnaBridge 172:65be27845400 59 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 60 typedef struct __SRAM_HandleTypeDef
AnnaBridge 172:65be27845400 61 #else
AnnaBridge 172:65be27845400 62 typedef struct
AnnaBridge 172:65be27845400 63 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
AnnaBridge 172:65be27845400 64 {
AnnaBridge 172:65be27845400 65 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 172:65be27845400 66
AnnaBridge 172:65be27845400 67 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
AnnaBridge 172:65be27845400 68
AnnaBridge 172:65be27845400 69 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
AnnaBridge 172:65be27845400 70
AnnaBridge 172:65be27845400 71 HAL_LockTypeDef Lock; /*!< SRAM locking object */
AnnaBridge 172:65be27845400 72
AnnaBridge 172:65be27845400 73 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
AnnaBridge 172:65be27845400 74
AnnaBridge 172:65be27845400 75 MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */
AnnaBridge 172:65be27845400 76
AnnaBridge 172:65be27845400 77 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 78 void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
AnnaBridge 172:65be27845400 79 void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
AnnaBridge 172:65be27845400 80 void (* DmaXferCpltCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SRAM DMA Xfer Complete callback */
AnnaBridge 172:65be27845400 81 void (* DmaXferErrorCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SRAM DMA Xfer Error callback */
AnnaBridge 172:65be27845400 82 #endif
AnnaBridge 172:65be27845400 83 } SRAM_HandleTypeDef;
AnnaBridge 172:65be27845400 84
AnnaBridge 172:65be27845400 85 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 86 /**
AnnaBridge 172:65be27845400 87 * @brief HAL SRAM Callback ID enumeration definition
AnnaBridge 172:65be27845400 88 */
AnnaBridge 172:65be27845400 89 typedef enum
AnnaBridge 172:65be27845400 90 {
AnnaBridge 172:65be27845400 91 HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
AnnaBridge 172:65be27845400 92 HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
AnnaBridge 172:65be27845400 93 HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
AnnaBridge 172:65be27845400 94 HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
AnnaBridge 172:65be27845400 95 }HAL_SRAM_CallbackIDTypeDef;
AnnaBridge 172:65be27845400 96
AnnaBridge 172:65be27845400 97 /**
AnnaBridge 172:65be27845400 98 * @brief HAL SRAM Callback pointer definition
AnnaBridge 172:65be27845400 99 */
AnnaBridge 172:65be27845400 100 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
AnnaBridge 172:65be27845400 101 typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);
AnnaBridge 172:65be27845400 102 #endif
AnnaBridge 172:65be27845400 103 /**
AnnaBridge 172:65be27845400 104 * @}
AnnaBridge 172:65be27845400 105 */
AnnaBridge 172:65be27845400 106
AnnaBridge 172:65be27845400 107 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 108 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 109
AnnaBridge 172:65be27845400 110 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
AnnaBridge 172:65be27845400 111 * @{
AnnaBridge 172:65be27845400 112 */
AnnaBridge 172:65be27845400 113
AnnaBridge 172:65be27845400 114 /** @brief Reset SRAM handle state
AnnaBridge 172:65be27845400 115 * @param __HANDLE__ SRAM handle
AnnaBridge 172:65be27845400 116 * @retval None
AnnaBridge 172:65be27845400 117 */
AnnaBridge 172:65be27845400 118 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 119 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
AnnaBridge 172:65be27845400 120 (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
AnnaBridge 172:65be27845400 121 (__HANDLE__)->MspInitCallback = NULL; \
AnnaBridge 172:65be27845400 122 (__HANDLE__)->MspDeInitCallback = NULL; \
AnnaBridge 172:65be27845400 123 } while(0)
AnnaBridge 172:65be27845400 124 #else
AnnaBridge 172:65be27845400 125 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
AnnaBridge 172:65be27845400 126 #endif
AnnaBridge 172:65be27845400 127
AnnaBridge 172:65be27845400 128 /**
AnnaBridge 172:65be27845400 129 * @}
AnnaBridge 172:65be27845400 130 */
AnnaBridge 172:65be27845400 131
AnnaBridge 172:65be27845400 132 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 133 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
AnnaBridge 172:65be27845400 134 * @{
AnnaBridge 172:65be27845400 135 */
AnnaBridge 172:65be27845400 136
AnnaBridge 172:65be27845400 137 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 172:65be27845400 138 * @{
AnnaBridge 172:65be27845400 139 */
AnnaBridge 172:65be27845400 140
AnnaBridge 172:65be27845400 141 /* Initialization/de-initialization functions ********************************/
AnnaBridge 172:65be27845400 142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
AnnaBridge 172:65be27845400 143 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 172:65be27845400 144 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 172:65be27845400 145 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
AnnaBridge 172:65be27845400 146
AnnaBridge 172:65be27845400 147 /**
AnnaBridge 172:65be27845400 148 * @}
AnnaBridge 172:65be27845400 149 */
AnnaBridge 172:65be27845400 150
AnnaBridge 172:65be27845400 151 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
AnnaBridge 172:65be27845400 152 * @{
AnnaBridge 172:65be27845400 153 */
AnnaBridge 172:65be27845400 154
AnnaBridge 172:65be27845400 155 /* I/O operation functions ***************************************************/
AnnaBridge 172:65be27845400 156 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 157 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 158 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 159 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 160 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 161 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 162 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 163 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
AnnaBridge 172:65be27845400 164
AnnaBridge 172:65be27845400 165 void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
AnnaBridge 172:65be27845400 166 void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
AnnaBridge 172:65be27845400 167
AnnaBridge 172:65be27845400 168 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
AnnaBridge 172:65be27845400 169 /* SRAM callback registering/unregistering */
AnnaBridge 172:65be27845400 170 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
AnnaBridge 172:65be27845400 171 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
AnnaBridge 172:65be27845400 172 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
AnnaBridge 172:65be27845400 173 #endif
AnnaBridge 172:65be27845400 174
AnnaBridge 172:65be27845400 175 /**
AnnaBridge 172:65be27845400 176 * @}
AnnaBridge 172:65be27845400 177 */
AnnaBridge 172:65be27845400 178
AnnaBridge 172:65be27845400 179 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
AnnaBridge 172:65be27845400 180 * @{
AnnaBridge 172:65be27845400 181 */
AnnaBridge 172:65be27845400 182
AnnaBridge 172:65be27845400 183 /* SRAM Control functions ****************************************************/
AnnaBridge 172:65be27845400 184 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
AnnaBridge 172:65be27845400 185 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
AnnaBridge 172:65be27845400 186
AnnaBridge 172:65be27845400 187 /**
AnnaBridge 172:65be27845400 188 * @}
AnnaBridge 172:65be27845400 189 */
AnnaBridge 172:65be27845400 190
AnnaBridge 172:65be27845400 191 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 172:65be27845400 192 * @{
AnnaBridge 172:65be27845400 193 */
AnnaBridge 172:65be27845400 194
AnnaBridge 172:65be27845400 195 /* SRAM State functions ******************************************************/
AnnaBridge 172:65be27845400 196 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
AnnaBridge 172:65be27845400 197
AnnaBridge 172:65be27845400 198 /**
AnnaBridge 172:65be27845400 199 * @}
AnnaBridge 172:65be27845400 200 */
AnnaBridge 172:65be27845400 201
AnnaBridge 172:65be27845400 202 /**
AnnaBridge 172:65be27845400 203 * @}
AnnaBridge 172:65be27845400 204 */
AnnaBridge 172:65be27845400 205
AnnaBridge 172:65be27845400 206 /**
AnnaBridge 172:65be27845400 207 * @}
AnnaBridge 172:65be27845400 208 */
AnnaBridge 172:65be27845400 209
AnnaBridge 172:65be27845400 210 /**
AnnaBridge 172:65be27845400 211 * @}
AnnaBridge 172:65be27845400 212 */
AnnaBridge 172:65be27845400 213
AnnaBridge 172:65be27845400 214
AnnaBridge 172:65be27845400 215 #ifdef __cplusplus
AnnaBridge 172:65be27845400 216 }
AnnaBridge 172:65be27845400 217 #endif
AnnaBridge 172:65be27845400 218
AnnaBridge 172:65be27845400 219 #endif /* STM32H7xx_HAL_SRAM_H */
AnnaBridge 172:65be27845400 220
AnnaBridge 172:65be27845400 221 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/